system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdint.h>
#include <stdio.h>
#include <assert.h>
/*******************************************************************
IPv4 Lookup with DIR-24-8-BASIC algorithm from Infocom'98 paper:
<Routing Lookups in Hardware at Memory Access Speeds>
******************************************************************/
extern "C" __global__ void ipv4lookup(const uint32_t *input_buf,
const uint64_t job_num,
uint8_t *output_buf,
const uint16_t *tbl24)
{
/* computer the thread id */
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int step = blockDim.x * gridDim.x;
int i;
uint32_t hash;
uint16_t value_tb1;
for (i = idx; i < job_num; i += step) {
hash = input_buf[i] >> 8;
value_tb1 = tbl24[hash];
output_buf[i] = (uint8_t)value_tb1; //FIXME
//printf("in %x [%x - hash %x], v %x, uint8 %x\n", input_buf[i], i, hash, value_tb1, (uint8_t)value_tb1);
}
return;
}
/**************************************************************************
Exported C++ function wrapper function for CUDA kernel
***************************************************************************/
extern "C" void IPv4_Lookup(const uint32_t *input_buf,
const uint32_t job_num,
uint8_t *output_buf,
const uint16_t *tbl24,
const unsigned int threads_per_blk,
const unsigned int num_cuda_blks,
hipStream_t stream)
{
//printf("%d = %d\n", threads_per_blk, num_cuda_blks);
if (stream == 0) {
ipv4lookup<<<num_cuda_blks, threads_per_blk>>>(
input_buf, job_num, output_buf, tbl24);
} else {
ipv4lookup<<<num_cuda_blks, threads_per_blk, 0, stream>>>(
input_buf, job_num, output_buf, tbl24);
}
} | .text
.file "ipv4lookup.hip"
.globl __device_stub__ipv4lookup # -- Begin function __device_stub__ipv4lookup
.p2align 4, 0x90
.type __device_stub__ipv4lookup,@function
__device_stub__ipv4lookup: # @__device_stub__ipv4lookup
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $ipv4lookup, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__ipv4lookup, .Lfunc_end0-__device_stub__ipv4lookup
.cfi_endproc
# -- End function
.globl IPv4_Lookup # -- Begin function IPv4_Lookup
.p2align 4, 0x90
.type IPv4_Lookup,@function
IPv4_Lookup: # @IPv4_Lookup
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %eax
movq %rcx, %rbx
movq %rdx, %r14
movl %esi, %ebp
movq %rdi, %r15
movq 160(%rsp), %r9
movl %eax, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %r8d, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
testq %r9, %r9
jne .LBB1_2
# %bb.1:
xorl %r9d, %r9d
.LBB1_2:
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movl %ebp, %eax
movq %r15, 72(%rsp)
movq %rax, 64(%rsp)
movq %r14, 56(%rsp)
movq %rbx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $ipv4lookup, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size IPv4_Lookup, .Lfunc_end1-IPv4_Lookup
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $ipv4lookup, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type ipv4lookup,@object # @ipv4lookup
.section .rodata,"a",@progbits
.globl ipv4lookup
.p2align 3, 0x0
ipv4lookup:
.quad __device_stub__ipv4lookup
.size ipv4lookup, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "ipv4lookup"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__ipv4lookup
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym ipv4lookup
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : ipv4lookup
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R2, c[0x0][0x16c], PT, P0 ; /* 0x00005b0002007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R9, RZ, RZ, R2 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0002 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD.MOV.U32 R8, RZ, RZ, R0 ; /* 0x000000ffff087224 */
/* 0x000fca00078e0000 */
/*00b0*/ LEA R4, P0, R8, c[0x0][0x160], 0x2 ; /* 0x0000580008047a11 */
/* 0x000fc800078010ff */
/*00c0*/ LEA.HI.X R5, R8, c[0x0][0x164], R9, 0x2, P0 ; /* 0x0000590008057a11 */
/* 0x000fca00000f1409 */
/*00d0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x2 ; /* 0x00000002ff037424 */
/* 0x001fe200078e00ff */
/*00f0*/ IADD3 R6, P0, R8, c[0x0][0x170], RZ ; /* 0x00005c0008067a10 */
/* 0x000fe40007f1e0ff */
/*0100*/ SHF.R.U32.HI R2, RZ, 0x8, R4 ; /* 0x00000008ff027819 */
/* 0x004fca0000011604 */
/*0110*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x178] ; /* 0x00005e0002027625 */
/* 0x000fcc00078e0003 */
/*0120*/ LDG.E.U16 R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1500 */
/*0130*/ IADD3.X R7, R9, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0009077a10 */
/* 0x000fe200007fe4ff */
/*0140*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fc800078e00ff */
/*0150*/ IMAD R8, R9, c[0x0][0xc], R0 ; /* 0x0000030009087a24 */
/* 0x000fc800078e0200 */
/*0160*/ IMAD.MOV.U32 R0, RZ, RZ, R8.reuse ; /* 0x000000ffff007224 */
/* 0x100fe200078e0008 */
/*0170*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x168], PT ; /* 0x00005a0008007a0c */
/* 0x000fe40003f06070 */
/*0180*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x000fc80000011408 */
/*0190*/ ISETP.GE.U32.AND.EX P0, PT, R9, c[0x0][0x16c], PT, P0 ; /* 0x00005b0009007a0c */
/* 0x000fe20003f06100 */
/*01a0*/ STG.E.U8 [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x0041d8000c101104 */
/*01b0*/ @!P0 BRA 0xb0 ; /* 0xfffffef000008947 */
/* 0x000fea000383ffff */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected ipv4lookup
.globl ipv4lookup
.p2align 8
.type ipv4lookup,@function
ipv4lookup:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x8
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s11, s[4:5], 0x0
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x0
s_load_b128 s[4:7], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_add_i32 s15, s15, s11
s_mul_i32 s1, s11, s10
v_mad_u64_u32 v[3:4], null, s15, s10, v[0:1]
s_ashr_i32 s10, s1, 31
s_mov_b32 s11, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v0, 31, v3
v_sub_co_u32 v3, vcc_lo, v3, s1
v_subrev_co_ci_u32_e32 v4, vcc_lo, s10, v0, vcc_lo
.p2align 6
.LBB0_2:
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s8, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
v_add_co_u32 v3, vcc_lo, v3, s1
v_add_co_ci_u32_e32 v4, vcc_lo, s10, v4, vcc_lo
global_load_b32 v0, v[5:6], off
v_add_co_u32 v5, vcc_lo, s4, v1
v_cmp_le_u64_e64 s0, s[2:3], v[3:4]
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v2, vcc_lo
v_ashrrev_i32_e32 v2, 31, v3
v_mov_b32_e32 v1, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_or_b32 s11, s0, s11
s_waitcnt vmcnt(0)
v_lshrrev_b32_e32 v0, 7, v0
v_and_b32_e32 v0, 0x1fffffe, v0
global_load_u16 v0, v0, s[6:7]
s_waitcnt vmcnt(0)
global_store_b8 v[5:6], v0, off
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel ipv4lookup
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size ipv4lookup, .Lfunc_end0-ipv4lookup
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: ipv4lookup
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: ipv4lookup.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009ca42_00000000-6_ipv4lookup.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z10ipv4lookupPKjmPhPKtPKjmPhPKt
.type _Z37__device_stub__Z10ipv4lookupPKjmPhPKtPKjmPhPKt, @function
_Z37__device_stub__Z10ipv4lookupPKjmPhPKtPKjmPhPKt:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq ipv4lookup(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z37__device_stub__Z10ipv4lookupPKjmPhPKtPKjmPhPKt, .-_Z37__device_stub__Z10ipv4lookupPKjmPhPKtPKjmPhPKt
.globl ipv4lookup
.type ipv4lookup, @function
ipv4lookup:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z10ipv4lookupPKjmPhPKtPKjmPhPKt
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size ipv4lookup, .-ipv4lookup
.globl IPv4_Lookup
.type IPv4_Lookup, @function
IPv4_Lookup:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movl %esi, %ebx
movq %rdx, %r12
movq %rcx, %r13
movl %r9d, %eax
movq 80(%rsp), %r9
testq %r9, %r9
je .L17
movl %r8d, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl %r8d, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L11
movl %ebx, %esi
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rdi
call _Z37__device_stub__Z10ipv4lookupPKjmPhPKtPKjmPhPKt
jmp .L11
.L18:
movl %ebx, %esi
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rdi
call _Z37__device_stub__Z10ipv4lookupPKjmPhPKtPKjmPhPKt
jmp .L11
.cfi_endproc
.LFE2057:
.size IPv4_Lookup, .-IPv4_Lookup
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "ipv4lookup"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq ipv4lookup(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ipv4lookup.hip"
.globl __device_stub__ipv4lookup # -- Begin function __device_stub__ipv4lookup
.p2align 4, 0x90
.type __device_stub__ipv4lookup,@function
__device_stub__ipv4lookup: # @__device_stub__ipv4lookup
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $ipv4lookup, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__ipv4lookup, .Lfunc_end0-__device_stub__ipv4lookup
.cfi_endproc
# -- End function
.globl IPv4_Lookup # -- Begin function IPv4_Lookup
.p2align 4, 0x90
.type IPv4_Lookup,@function
IPv4_Lookup: # @IPv4_Lookup
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %eax
movq %rcx, %rbx
movq %rdx, %r14
movl %esi, %ebp
movq %rdi, %r15
movq 160(%rsp), %r9
movl %eax, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %r8d, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
testq %r9, %r9
jne .LBB1_2
# %bb.1:
xorl %r9d, %r9d
.LBB1_2:
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movl %ebp, %eax
movq %r15, 72(%rsp)
movq %rax, 64(%rsp)
movq %r14, 56(%rsp)
movq %rbx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $ipv4lookup, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size IPv4_Lookup, .Lfunc_end1-IPv4_Lookup
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $ipv4lookup, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type ipv4lookup,@object # @ipv4lookup
.section .rodata,"a",@progbits
.globl ipv4lookup
.p2align 3, 0x0
ipv4lookup:
.quad __device_stub__ipv4lookup
.size ipv4lookup, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "ipv4lookup"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__ipv4lookup
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym ipv4lookup
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/*
* CudaOperations.cu
*
* Created on: Feb 6, 2019
* Author: alexander
*/
__global__ void cudaKernelPull(float* mat, float* spins, int size, float* temp, float tempStep, float* meanFieldElements, bool* continueIteration, float minDiff, int* unemptyCells, float linearCoef) {
int blockId = blockIdx.x;
int thrId = threadIdx.x;
do {
// Lessen temperature
if (thrId == 0)
temp[blockId] = temp[blockId] - tempStep;
// Stabilize
do {
__syncthreads();
// By default current iteration is the last one
if (thrId == 0)
continueIteration[blockId] = false;
for (int spinId = 0; spinId < size; ++spinId) {
__syncthreads();
// Transitional value assignment
int wIndex = thrId;
while (wIndex < unemptyCells[spinId * (size + 1)]) {
meanFieldElements[wIndex + blockId * size] =
spins[unemptyCells[spinId * (size + 1) + wIndex + 1]
+ blockId * size]
* mat[spinId * size
+ unemptyCells[spinId * (size + 1)
+ wIndex + 1]];
// BEWARE: Matrix is symmetrical!
wIndex = wIndex + blockDim.x;
}
__syncthreads();
// Parallelized mean-field computation
long long offset = 1;
while (offset < unemptyCells[spinId * (size + 1)]) {
wIndex = thrId;
while ((wIndex * 2 + 1) * offset
< unemptyCells[spinId * (size + 1)]) {
meanFieldElements[wIndex * 2 * offset + blockId * size] +=
meanFieldElements[(wIndex * 2 + 1) * offset
+ blockId * size];
wIndex = wIndex + blockDim.x;
}
offset *= 2;
__syncthreads();
}
__syncthreads();
// Mean-field calculation complete - write new spin and delta
if (thrId == 0) {
float meanField = meanFieldElements[blockId * size];
float old = spins[spinId + blockId * size];
if (temp[blockId] > 0) {
spins[spinId + blockId * size] = -1
* tanh(meanField / temp[blockId]) * linearCoef
+ spins[spinId + blockId * size]
* (1 - linearCoef);
} else if (meanField > 0)
spins[spinId + blockId * size] = -1;
else
spins[spinId + blockId * size] = 1;
if (minDiff < fabs(old - spins[spinId + blockId * size]))
continueIteration[blockId] = true; // Too big delta. One more iteration needed
}
__syncthreads();
}
} while (continueIteration[blockId]);
} while (temp[blockId] >= 0);
} | code for sm_80
Function : _Z14cudaKernelPullPfS_iS_fS_PbfPif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC UR5, c[0x0][0x170] ; /* 0x00005c0000057ab9 */
/* 0x000fe20000000800 */
/*0040*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x1a8] ; /* 0x00006a00ff107624 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e620000002500 */
/*0060*/ UIADD3 UR5, UR5, 0x1, URZ ; /* 0x0000000105057890 */
/* 0x000fe4000fffe03f */
/*0070*/ FADD R16, -R16, 1 ; /* 0x3f80000010107421 */
/* 0x000fe20000000100 */
/*0080*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD.SHL.U32 R17, R0.reuse, 0x2, RZ ; /* 0x0000000200117824 */
/* 0x041fe200078e00ff */
/*00a0*/ IADD3 R19, R0, 0x1, RZ ; /* 0x0000000100137810 */
/* 0x000fc40007ffe0ff */
/*00b0*/ IADD3 R6, P0, R2.reuse, c[0x0][0x190], RZ ; /* 0x0000640002067a10 */
/* 0x042fe20007f1e0ff */
/*00c0*/ IMAD R18, R2.reuse, c[0x0][0x170], RZ ; /* 0x00005c0002127a24 */
/* 0x040fe200078e02ff */
/*00d0*/ IADD3 R22, R17, 0x1, RZ ; /* 0x0000000111167810 */
/* 0x000fe20007ffe0ff */
/*00e0*/ IMAD.WIDE R4, R2.reuse, R3.reuse, c[0x0][0x178] ; /* 0x00005e0002047625 */
/* 0x0c0fe200078e0203 */
/*00f0*/ LEA.HI.X.SX32 R7, R2, c[0x0][0x194], 0x1, P0 ; /* 0x0000650002077a11 */
/* 0x000fe400000f0eff */
/*0100*/ SHF.R.S32.HI R20, RZ, 0x1f, R22 ; /* 0x0000001fff147819 */
/* 0x000fe20000011416 */
/*0110*/ IMAD.WIDE R2, R18, R3, c[0x0][0x188] ; /* 0x0000620012027625 */
/* 0x000fc800078e0203 */
/*0120*/ ISETP.NE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f45270 */
/*0130*/ BSSY B0, 0x190 ; /* 0x0000005000007945 */
/* 0x000fd80003800000 */
/*0140*/ @P2 BRA 0x180 ; /* 0x0000003000002947 */
/* 0x002fea0003800000 */
/*0150*/ LDG.E R8, [R4.64] ; /* 0x0000000604087981 */
/* 0x000ea4000c1e1900 */
/*0160*/ FADD R9, R8, -c[0x0][0x180] ; /* 0x8000600008097621 */
/* 0x004fca0000000000 */
/*0170*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101906 */
/*0180*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01a0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff087624 */
/* 0x000fca00078e00ff */
/*01b0*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fe20003f06270 */
/*01c0*/ @!P2 STG.E.U8 [R6.64], RZ ; /* 0x000000ff0600a986 */
/* 0x0023d8000c101106 */
/*01d0*/ @!P0 BRA 0xad0 ; /* 0x000008f000008947 */
/* 0x000fea0003800000 */
/*01e0*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ; /* 0x000000ffff157224 */
/* 0x000fe400078e00ff */
/*01f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0200*/ IMAD.MOV.U32 R23, RZ, RZ, 0x4 ; /* 0x00000004ff177424 */
/* 0x000fe400078e00ff */
/*0210*/ IMAD R26, R21, UR5, RZ ; /* 0x00000005151a7c24 */
/* 0x000fc8000f8e02ff */
/*0220*/ IMAD.WIDE R8, R26, R23, c[0x0][0x1a0] ; /* 0x000068001a087625 */
/* 0x001fca00078e0217 */
/*0230*/ LDG.E R11, [R8.64] ; /* 0x00000006080b7981 */
/* 0x000ea2000c1e1900 */
/*0240*/ BSSY B0, 0x3a0 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*0250*/ ISETP.GE.AND P0, PT, R0, R11, PT ; /* 0x0000000b0000720c */
/* 0x004fda0003f06270 */
/*0260*/ @P0 BRA 0x390 ; /* 0x0000012000000947 */
/* 0x000fea0003800000 */
/*0270*/ IMAD.IADD R26, R19, 0x1, R26 ; /* 0x00000001131a7824 */
/* 0x000fe400078e021a */
/*0280*/ IMAD.MOV.U32 R27, RZ, RZ, R0 ; /* 0x000000ffff1b7224 */
/* 0x000fe400078e0000 */
/*0290*/ IMAD.WIDE R14, R26, R23, c[0x0][0x1a0] ; /* 0x000068001a0e7625 */
/* 0x000fcc00078e0217 */
/*02a0*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ea4000c1e1900 */
/*02b0*/ IMAD.IADD R12, R18, 0x1, R14.reuse ; /* 0x00000001120c7824 */
/* 0x104fe400078e020e */
/*02c0*/ IMAD R10, R21, c[0x0][0x170], R14 ; /* 0x00005c00150a7a24 */
/* 0x000fe400078e020e */
/*02d0*/ IMAD.WIDE R12, R12, R23, c[0x0][0x168] ; /* 0x00005a000c0c7625 */
/* 0x000fc800078e0217 */
/*02e0*/ IMAD.WIDE R10, R10, R23, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fe400078e0217 */
/*02f0*/ LDG.E R13, [R12.64] ; /* 0x000000060c0d7981 */
/* 0x000ea8000c1e1900 */
/*0300*/ LDG.E R10, [R10.64] ; /* 0x000000060a0a7981 */
/* 0x000ea2000c1e1900 */
/*0310*/ IMAD.WIDE R24, R27, 0x4, R2 ; /* 0x000000041b187825 */
/* 0x000fc800078e0202 */
/*0320*/ FMUL R29, R10, R13 ; /* 0x0000000d0a1d7220 */
/* 0x004fca0000400000 */
/*0330*/ STG.E [R24.64], R29 ; /* 0x0000001d18007986 */
/* 0x0001e8000c101906 */
/*0340*/ LDG.E R28, [R8.64] ; /* 0x00000006081c7981 */
/* 0x000ea2000c1e1900 */
/*0350*/ IADD3 R27, R27, c[0x0][0x0], RZ ; /* 0x000000001b1b7a10 */
/* 0x000fe40007ffe0ff */
/*0360*/ IADD3 R26, R26, c[0x0][0x0], RZ ; /* 0x000000001a1a7a10 */
/* 0x000fe40007ffe0ff */
/*0370*/ ISETP.GE.AND P0, PT, R27, R28, PT ; /* 0x0000001c1b00720c */
/* 0x004fda0003f06270 */
/*0380*/ @!P0 BRA 0x290 ; /* 0xffffff0000008947 */
/* 0x001fea000383ffff */
/*0390*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03b0*/ LDG.E R10, [R8.64] ; /* 0x00000006080a7981 */
/* 0x000ea4000c1e1900 */
/*03c0*/ ISETP.GE.AND P0, PT, R10, 0x2, PT ; /* 0x000000020a00780c */
/* 0x004fda0003f06270 */
/*03d0*/ @!P0 BRA 0x720 ; /* 0x0000034000008947 */
/* 0x000fea0003800000 */
/*03e0*/ IMAD.MOV.U32 R13, RZ, RZ, R10 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e000a */
/*03f0*/ UMOV UR8, 0x1 ; /* 0x0000000100087882 */
/* 0x000fe40000000000 */
/*0400*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0410*/ IMAD R15, R22.reuse, UR4, RZ ; /* 0x00000004160f7c24 */
/* 0x040fe2000f8e02ff */
/*0420*/ SHF.R.S32.HI R12, RZ, 0x1f, R13 ; /* 0x0000001fff0c7819 */
/* 0x000fe2000001140d */
/*0430*/ IMAD.WIDE.U32 R10, R22, UR8, RZ ; /* 0x00000008160a7c25 */
/* 0x000fe2000f8e00ff */
/*0440*/ BSSY B0, 0x690 ; /* 0x0000024000007945 */
/* 0x000fe60003800000 */
/*0450*/ IMAD R15, R20, UR8, R15 ; /* 0x00000008140f7c24 */
/* 0x000fe2000f8e020f */
/*0460*/ ISETP.GE.U32.AND P0, PT, R10, R13, PT ; /* 0x0000000d0a00720c */
/* 0x000fc60003f06070 */
/*0470*/ IMAD.IADD R13, R11, 0x1, R15 ; /* 0x000000010b0d7824 */
/* 0x000fca00078e020f */
/*0480*/ ISETP.GE.AND.EX P0, PT, R13, R12, PT, P0 ; /* 0x0000000c0d00720c */
/* 0x000fda0003f06300 */
/*0490*/ @P0 BRA 0x680 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*04a0*/ IMAD.MOV.U32 R15, RZ, RZ, R10 ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e000a */
/*04b0*/ MOV R23, R0 ; /* 0x0000000000177202 */
/* 0x000fe20000000f00 */
/*04c0*/ IMAD.MOV.U32 R24, RZ, RZ, R17 ; /* 0x000000ffff187224 */
/* 0x000fca00078e0011 */
/*04d0*/ SHF.R.S32.HI R12, RZ, 0x1f, R24 ; /* 0x0000001fff0c7819 */
/* 0x000fe20000011418 */
/*04e0*/ IMAD R25, R24.reuse, UR4, RZ ; /* 0x0000000418197c24 */
/* 0x040fe4000f8e02ff */
/*04f0*/ IMAD.WIDE.U32 R10, R24, UR8, RZ ; /* 0x00000008180a7c25 */
/* 0x000fc8000f8e00ff */
/*0500*/ IMAD R25, R12, UR8, R25 ; /* 0x000000080c197c24 */
/* 0x000fe2000f8e0219 */
/*0510*/ LEA R12, P1, R15, R2.reuse, 0x2 ; /* 0x000000020f0c7211 */
/* 0x080fe400078210ff */
/*0520*/ LEA R14, P0, R10, R2, 0x2 ; /* 0x000000020a0e7211 */
/* 0x000fe200078010ff */
/*0530*/ IMAD.IADD R11, R11, 0x1, R25 ; /* 0x000000010b0b7824 */
/* 0x000fe200078e0219 */
/*0540*/ LEA.HI.X R13, R15, R3, R13, 0x2, P1 ; /* 0x000000030f0d7211 */
/* 0x000fc800008f140d */
/*0550*/ LEA.HI.X R15, R10, R3, R11, 0x2, P0 ; /* 0x000000030a0f7211 */
/* 0x000fe400000f140b */
/*0560*/ LDG.E R13, [R12.64] ; /* 0x000000060c0d7981 */
/* 0x000ea8000c1e1900 */
/*0570*/ LDG.E R10, [R14.64] ; /* 0x000000060e0a7981 */
/* 0x000ea2000c1e1900 */
/*0580*/ IADD3 R23, R23, c[0x0][0x0], RZ ; /* 0x0000000017177a10 */
/* 0x000fca0007ffe0ff */
/*0590*/ IMAD.SHL.U32 R24, R23, 0x2, RZ ; /* 0x0000000217187824 */
/* 0x000fe400078e00ff */
/*05a0*/ FADD R25, R10, R13 ; /* 0x0000000d0a197221 */
/* 0x004fca0000000000 */
/*05b0*/ STG.E [R14.64], R25 ; /* 0x000000190e007986 */
/* 0x0001e8000c101906 */
/*05c0*/ LDG.E R27, [R8.64] ; /* 0x00000006081b7981 */
/* 0x000ea2000c1e1900 */
/*05d0*/ IADD3 R10, R24, 0x1, RZ ; /* 0x00000001180a7810 */
/* 0x000fc80007ffe0ff */
/*05e0*/ SHF.R.S32.HI R26, RZ, 0x1f, R10 ; /* 0x0000001fff1a7819 */
/* 0x000fe2000001140a */
/*05f0*/ IMAD R29, R10.reuse, UR4, RZ ; /* 0x000000040a1d7c24 */
/* 0x040fe4000f8e02ff */
/*0600*/ IMAD.WIDE.U32 R10, R10, UR8, RZ ; /* 0x000000080a0a7c25 */
/* 0x000fc8000f8e00ff */
/*0610*/ IMAD R29, R26, UR8, R29 ; /* 0x000000081a1d7c24 */
/* 0x000fe4000f8e021d */
/*0620*/ IMAD.MOV.U32 R15, RZ, RZ, R10 ; /* 0x000000ffff0f7224 */
/* 0x001fe400078e000a */
/*0630*/ IMAD.IADD R13, R11, 0x1, R29 ; /* 0x000000010b0d7824 */
/* 0x000fe200078e021d */
/*0640*/ ISETP.GE.U32.AND P0, PT, R10, R27, PT ; /* 0x0000001b0a00720c */
/* 0x004fe40003f06070 */
/*0650*/ SHF.R.S32.HI R12, RZ, 0x1f, R27 ; /* 0x0000001fff0c7819 */
/* 0x000fc8000001141b */
/*0660*/ ISETP.GE.AND.EX P0, PT, R13, R12, PT, P0 ; /* 0x0000000c0d00720c */
/* 0x000fda0003f06300 */
/*0670*/ @!P0 BRA 0x4d0 ; /* 0xfffffe5000008947 */
/* 0x000fea000383ffff */
/*0680*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0690*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*06a0*/ LDG.E R13, [R8.64] ; /* 0x00000006080d7981 */
/* 0x000ea2000c1e1900 */
/*06b0*/ USHF.L.U64.HI UR4, UR8, 0x1, UR4 ; /* 0x0000000108047899 */
/* 0x000fe40008010204 */
/*06c0*/ USHF.L.U32 UR8, UR8, 0x1, URZ ; /* 0x0000000108087899 */
/* 0x000fc8000800063f */
/*06d0*/ IMAD.U32 R11, RZ, RZ, UR4 ; /* 0x00000004ff0b7e24 */
/* 0x000fe4000f8e00ff */
/*06e0*/ ISETP.LE.U32.AND P0, PT, R13, UR8, PT ; /* 0x000000080d007c0c */
/* 0x004fe4000bf03070 */
/*06f0*/ SHF.R.S32.HI R10, RZ, 0x1f, R13 ; /* 0x0000001fff0a7819 */
/* 0x000fc8000001140d */
/*0700*/ ISETP.GE.AND.EX P0, PT, R11, R10, PT, P0 ; /* 0x0000000a0b00720c */
/* 0x000fda0003f06300 */
/*0710*/ @!P0 BRA 0x410 ; /* 0xfffffcf000008947 */
/* 0x000fea000383ffff */
/*0720*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0730*/ BSSY B0, 0xa90 ; /* 0x0000035000007945 */
/* 0x000fe20003800000 */
/*0740*/ @P2 BRA 0xa80 ; /* 0x0000033000002947 */
/* 0x000fea0003800000 */
/*0750*/ LDG.E R13, [R4.64] ; /* 0x00000006040d7981 */
/* 0x000ea2000c1e1900 */
/*0760*/ IMAD.IADD R8, R18, 0x1, R21 ; /* 0x0000000112087824 */
/* 0x000fe400078e0215 */
/*0770*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0780*/ LDG.E R24, [R2.64] ; /* 0x0000000602187981 */
/* 0x000166000c1e1900 */
/*0790*/ IMAD.WIDE R8, R8, R9, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fca00078e0209 */
/*07a0*/ LDG.E R11, [R8.64] ; /* 0x00000006080b7981 */
/* 0x000162000c1e1900 */
/*07b0*/ FSETP.GT.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720b */
/* 0x004fda0003f04000 */
/*07c0*/ @P0 BRA 0x850 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*07d0*/ FSETP.GT.AND P0, PT, R24, RZ, PT ; /* 0x000000ff1800720b */
/* 0x021fda0003f04000 */
/*07e0*/ @!P0 IMAD.MOV.U32 R13, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff0d8424 */
/* 0x000fe200078e00ff */
/*07f0*/ @!P0 MOV R15, 0x3f800000 ; /* 0x3f800000000f8802 */
/* 0x000fe20000000f00 */
/*0800*/ @P0 IMAD.MOV.U32 R23, RZ, RZ, -0x40800000 ; /* 0xbf800000ff170424 */
/* 0x000fe400078e00ff */
/*0810*/ @P0 IMAD.MOV.U32 R15, RZ, RZ, -0x40800000 ; /* 0xbf800000ff0f0424 */
/* 0x000fe200078e00ff */
/*0820*/ @!P0 STG.E [R8.64], R13 ; /* 0x0000000d08008986 */
/* 0x0001e8000c101906 */
/*0830*/ @P0 STG.E [R8.64], R23 ; /* 0x0000001708000986 */
/* 0x0001e2000c101906 */
/*0840*/ BRA 0xa40 ; /* 0x000001f000007947 */
/* 0x000fea0003800000 */
/*0850*/ MUFU.RCP R10, R13 ; /* 0x0000000d000a7308 */
/* 0x001e300000001000 */
/*0860*/ FCHK P0, R24, R13 ; /* 0x0000000d18007302 */
/* 0x020ea20000000000 */
/*0870*/ FFMA R15, -R13, R10, 1 ; /* 0x3f8000000d0f7423 */
/* 0x001fc8000000010a */
/*0880*/ FFMA R15, R10, R15, R10 ; /* 0x0000000f0a0f7223 */
/* 0x000fc8000000000a */
/*0890*/ FFMA R10, R24, R15, RZ ; /* 0x0000000f180a7223 */
/* 0x000fc800000000ff */
/*08a0*/ FFMA R12, -R13, R10, R24 ; /* 0x0000000a0d0c7223 */
/* 0x000fc80000000118 */
/*08b0*/ FFMA R10, R15, R12, R10 ; /* 0x0000000c0f0a7223 */
/* 0x000fe2000000000a */
/*08c0*/ @!P0 BRA 0x900 ; /* 0x0000003000008947 */
/* 0x004fea0003800000 */
/*08d0*/ MOV R14, 0x8f0 ; /* 0x000008f0000e7802 */
/* 0x000fe40000000f00 */
/*08e0*/ CALL.REL.NOINC 0xb40 ; /* 0x0000025000007944 */
/* 0x002fea0003c00000 */
/*08f0*/ IMAD.MOV.U32 R10, RZ, RZ, R25 ; /* 0x000000ffff0a7224 */
/* 0x001fc800078e0019 */
/*0900*/ FMUL R12, |R10|.reuse, 2.8853900432586669922 ; /* 0x4038aa3b0a0c7820 */
/* 0x040fe20000400200 */
/*0910*/ FSETP.GE.AND P1, PT, |R10|.reuse, 0.60000002384185791016, PT ; /* 0x3f19999a0a00780b */
/* 0x040fe20003f26200 */
/*0920*/ IMAD.MOV.U32 R24, RZ, RZ, 0x3c80f082 ; /* 0x3c80f082ff187424 */
/* 0x000fe200078e00ff */
/*0930*/ FSETP.GE.AND P0, PT, |R10|.reuse, 9.010913848876953125, PT ; /* 0x41102cb40a00780b */
/* 0x040fe20003f06200 */
/*0940*/ FMUL R23, R10, R10 ; /* 0x0000000a0a177220 */
/* 0x000fe40000400000 */
/*0950*/ MUFU.EX2 R12, R12 ; /* 0x0000000c000c7308 */
/* 0x000e220000000800 */
/*0960*/ IMAD.MOV.U32 R14, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff0e7424 */
/* 0x000fe400078e00ff */
/*0970*/ FFMA R24, R23, R24, -0.052303962409496307373 ; /* 0xbd563cae17187423 */
/* 0x000fc80000000018 */
/*0980*/ FFMA R24, R23, R24, 0.1331529766321182251 ; /* 0x3e08594117187423 */
/* 0x000fc80000000018 */
/*0990*/ FFMA R24, R23, R24, -0.33332768082618713379 ; /* 0xbeaaa9ed17187423 */
/* 0x000fc80000000018 */
/*09a0*/ FFMA R23, R23, R24, RZ ; /* 0x0000001817177223 */
/* 0x000fe400000000ff */
/*09b0*/ FADD R13, R12, 1 ; /* 0x3f8000000c0d7421 */
/* 0x001fcc0000000000 */
/*09c0*/ MUFU.RCP R13, R13 ; /* 0x0000000d000d7308 */
/* 0x000e240000001000 */
/*09d0*/ FFMA R14, R13, -2, R14 ; /* 0xc00000000d0e7823 */
/* 0x001fca000000000e */
/*09e0*/ FSEL R15, R14, 1, !P0 ; /* 0x3f8000000e0f7808 */
/* 0x000fc80004000000 */
/*09f0*/ LOP3.LUT R15, R15, 0x80000000, R10.reuse, 0xf8, !PT ; /* 0x800000000f0f7812 */
/* 0x100fe200078ef80a */
/*0a00*/ @!P1 FFMA R15, R23, R10, R10 ; /* 0x0000000a170f9223 */
/* 0x000fc8000000000a */
/*0a10*/ FMUL R15, R15, c[0x0][0x1a8] ; /* 0x00006a000f0f7a20 */
/* 0x000fc80000400000 */
/*0a20*/ FFMA R15, R16, R11, -R15 ; /* 0x0000000b100f7223 */
/* 0x000fca000000080f */
/*0a30*/ STG.E [R8.64], R15 ; /* 0x0000000f08007986 */
/* 0x0001e4000c101906 */
/*0a40*/ FADD R11, R11, -R15 ; /* 0x8000000f0b0b7221 */
/* 0x000fe40000000000 */
/*0a50*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x001fc600078e00ff */
/*0a60*/ FSETP.GT.AND P0, PT, |R11|, c[0x0][0x198], PT ; /* 0x000066000b007a0b */
/* 0x000fda0003f04200 */
/*0a70*/ @P0 STG.E.U8 [R6.64], R8 ; /* 0x0000000806000986 */
/* 0x0001e4000c101106 */
/*0a80*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a90*/ IADD3 R21, R21, 0x1, RZ ; /* 0x0000000115157810 */
/* 0x000fe20007ffe0ff */
/*0aa0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0ab0*/ ISETP.GE.AND P0, PT, R21, c[0x0][0x170], PT ; /* 0x00005c0015007a0c */
/* 0x000fda0003f06270 */
/*0ac0*/ @!P0 BRA 0x1f0 ; /* 0xfffff72000008947 */
/* 0x000fea000383ffff */
/*0ad0*/ LDG.E.U8 R8, [R6.64] ; /* 0x0000000606087981 */
/* 0x001ea4000c1e1100 */
/*0ae0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x004fda0003f05270 */
/*0af0*/ @P0 BRA 0x190 ; /* 0xfffff69000000947 */
/* 0x000fea000383ffff */
/*0b00*/ LDG.E R8, [R4.64] ; /* 0x0000000604087981 */
/* 0x000ea4000c1e1900 */
/*0b10*/ FSETP.GE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720b */
/* 0x004fda0003f06000 */
/*0b20*/ @P0 BRA 0x120 ; /* 0xfffff5f000000947 */
/* 0x000fea000383ffff */
/*0b30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b40*/ SHF.R.U32.HI R12, RZ, 0x17, R13.reuse ; /* 0x00000017ff0c7819 */
/* 0x100fe2000001160d */
/*0b50*/ IMAD.MOV.U32 R25, RZ, RZ, R13 ; /* 0x000000ffff197224 */
/* 0x000fe200078e000d */
/*0b60*/ SHF.R.U32.HI R15, RZ, 0x17, R24 ; /* 0x00000017ff0f7819 */
/* 0x000fe40000011618 */
/*0b70*/ LOP3.LUT R12, R12, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0c0c7812 */
/* 0x000fe400078ec0ff */
/*0b80*/ LOP3.LUT R15, R15, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0f0f7812 */
/* 0x000fe400078ec0ff */
/*0b90*/ IADD3 R27, R12, -0x1, RZ ; /* 0xffffffff0c1b7810 */
/* 0x000fe40007ffe0ff */
/*0ba0*/ IADD3 R26, R15, -0x1, RZ ; /* 0xffffffff0f1a7810 */
/* 0x000fc40007ffe0ff */
/*0bb0*/ ISETP.GT.U32.AND P0, PT, R27, 0xfd, PT ; /* 0x000000fd1b00780c */
/* 0x000fc80003f04070 */
/*0bc0*/ ISETP.GT.U32.OR P0, PT, R26, 0xfd, P0 ; /* 0x000000fd1a00780c */
/* 0x000fda0000704470 */
/*0bd0*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe200078e00ff */
/*0be0*/ @!P0 BRA 0xd70 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0bf0*/ FSETP.GTU.FTZ.AND P0, PT, |R24|, +INF , PT ; /* 0x7f8000001800780b */
/* 0x000fe20003f1c200 */
/*0c00*/ IMAD.MOV.U32 R23, RZ, RZ, R24 ; /* 0x000000ffff177224 */
/* 0x000fe200078e0018 */
/*0c10*/ FSETP.GTU.FTZ.AND P1, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fc80003f3c200 */
/*0c20*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0c30*/ @P0 BRA 0x1150 ; /* 0x0000051000000947 */
/* 0x000fea0003800000 */
/*0c40*/ LOP3.LUT P0, RZ, R25, 0x7fffffff, R24, 0xc8, !PT ; /* 0x7fffffff19ff7812 */
/* 0x000fda000780c818 */
/*0c50*/ @!P0 BRA 0x1130 ; /* 0x000004d000008947 */
/* 0x000fea0003800000 */
/*0c60*/ FSETP.NEU.FTZ.AND P3, PT, |R23|, +INF , PT ; /* 0x7f8000001700780b */
/* 0x000fe40003f7d200 */
/*0c70*/ FSETP.NEU.FTZ.AND P1, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fe40003f3d200 */
/*0c80*/ FSETP.NEU.FTZ.AND P0, PT, |R23|, +INF , PT ; /* 0x7f8000001700780b */
/* 0x000fd60003f1d200 */
/*0c90*/ @!P1 BRA !P3, 0x1130 ; /* 0x0000049000009947 */
/* 0x000fea0005800000 */
/*0ca0*/ LOP3.LUT P3, RZ, R24, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff18ff7812 */
/* 0x000fc8000786c0ff */
/*0cb0*/ PLOP3.LUT P1, PT, P1, P3, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f26572 */
/*0cc0*/ @P1 BRA 0x1110 ; /* 0x0000044000001947 */
/* 0x000fea0003800000 */
/*0cd0*/ LOP3.LUT P1, RZ, R25, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff19ff7812 */
/* 0x000fc8000782c0ff */
/*0ce0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0cf0*/ @P0 BRA 0x10e0 ; /* 0x000003e000000947 */
/* 0x000fea0003800000 */
/*0d00*/ ISETP.GE.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe40003f06270 */
/*0d10*/ ISETP.GE.AND P1, PT, R27, RZ, PT ; /* 0x000000ff1b00720c */
/* 0x000fd60003f26270 */
/*0d20*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe200078e00ff */
/*0d30*/ @!P0 MOV R10, 0xffffffc0 ; /* 0xffffffc0000a8802 */
/* 0x000fe20000000f00 */
/*0d40*/ @!P0 FFMA R24, R23, 1.84467440737095516160e+19, RZ ; /* 0x5f80000017188823 */
/* 0x000fe400000000ff */
/*0d50*/ @!P1 FFMA R25, R13, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000d199823 */
/* 0x000fe200000000ff */
/*0d60*/ @!P1 IADD3 R10, R10, 0x40, RZ ; /* 0x000000400a0a9810 */
/* 0x000fe40007ffe0ff */
/*0d70*/ LEA R26, R12, 0xc0800000, 0x17 ; /* 0xc08000000c1a7811 */
/* 0x000fe400078eb8ff */
/*0d80*/ IADD3 R15, R15, -0x7f, RZ ; /* 0xffffff810f0f7810 */
/* 0x000fc60007ffe0ff */
/*0d90*/ IMAD.IADD R27, R25, 0x1, -R26 ; /* 0x00000001191b7824 */
/* 0x000fe400078e0a1a */
/*0da0*/ IMAD R26, R15.reuse, -0x800000, R24 ; /* 0xff8000000f1a7824 */
/* 0x040fe200078e0218 */
/*0db0*/ IADD3 R15, R15, 0x7f, -R12 ; /* 0x0000007f0f0f7810 */
/* 0x000fe20007ffe80c */
/*0dc0*/ MUFU.RCP R28, R27 ; /* 0x0000001b001c7308 */
/* 0x000e220000001000 */
/*0dd0*/ FADD.FTZ R23, -R27, -RZ ; /* 0x800000ff1b177221 */
/* 0x000fc60000010100 */
/*0de0*/ IMAD.IADD R15, R15, 0x1, R10 ; /* 0x000000010f0f7824 */
/* 0x000fe400078e020a */
/*0df0*/ FFMA R13, R28, R23, 1 ; /* 0x3f8000001c0d7423 */
/* 0x001fc80000000017 */
/*0e00*/ FFMA R13, R28, R13, R28 ; /* 0x0000000d1c0d7223 */
/* 0x000fc8000000001c */
/*0e10*/ FFMA R24, R26, R13, RZ ; /* 0x0000000d1a187223 */
/* 0x000fc800000000ff */
/*0e20*/ FFMA R25, R23, R24, R26 ; /* 0x0000001817197223 */
/* 0x000fc8000000001a */
/*0e30*/ FFMA R24, R13, R25, R24 ; /* 0x000000190d187223 */
/* 0x000fc80000000018 */
/*0e40*/ FFMA R23, R23, R24, R26 ; /* 0x0000001817177223 */
/* 0x000fc8000000001a */
/*0e50*/ FFMA R25, R13, R23, R24 ; /* 0x000000170d197223 */
/* 0x000fca0000000018 */
/*0e60*/ SHF.R.U32.HI R12, RZ, 0x17, R25 ; /* 0x00000017ff0c7819 */
/* 0x000fc80000011619 */
/*0e70*/ LOP3.LUT R12, R12, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0c0c7812 */
/* 0x000fca00078ec0ff */
/*0e80*/ IMAD.IADD R12, R12, 0x1, R15 ; /* 0x000000010c0c7824 */
/* 0x000fca00078e020f */
/*0e90*/ IADD3 R10, R12, -0x1, RZ ; /* 0xffffffff0c0a7810 */
/* 0x000fc80007ffe0ff */
/*0ea0*/ ISETP.GE.U32.AND P0, PT, R10, 0xfe, PT ; /* 0x000000fe0a00780c */
/* 0x000fda0003f06070 */
/*0eb0*/ @!P0 BRA 0x10c0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0ec0*/ ISETP.GT.AND P0, PT, R12, 0xfe, PT ; /* 0x000000fe0c00780c */
/* 0x000fda0003f04270 */
/*0ed0*/ @P0 BRA 0x1090 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0ee0*/ ISETP.GE.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fda0003f06270 */
/*0ef0*/ @P0 BRA 0x1160 ; /* 0x0000026000000947 */
/* 0x000fea0003800000 */
/*0f00*/ ISETP.GE.AND P0, PT, R12, -0x18, PT ; /* 0xffffffe80c00780c */
/* 0x000fe40003f06270 */
/*0f10*/ LOP3.LUT R25, R25, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000019197812 */
/* 0x000fd600078ec0ff */
/*0f20*/ @!P0 BRA 0x1160 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0f30*/ FFMA.RZ R10, R13.reuse, R23.reuse, R24.reuse ; /* 0x000000170d0a7223 */
/* 0x1c0fe2000000c018 */
/*0f40*/ ISETP.NE.AND P3, PT, R12.reuse, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x040fe40003f65270 */
/*0f50*/ ISETP.NE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f25270 */
/*0f60*/ LOP3.LUT R15, R10, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0a0f7812 */
/* 0x000fe200078ec0ff */
/*0f70*/ FFMA.RP R10, R13.reuse, R23.reuse, R24.reuse ; /* 0x000000170d0a7223 */
/* 0x1c0fe40000008018 */
/*0f80*/ FFMA.RM R13, R13, R23, R24 ; /* 0x000000170d0d7223 */
/* 0x000fe20000004018 */
/*0f90*/ IADD3 R24, R12, 0x20, RZ ; /* 0x000000200c187810 */
/* 0x000fe20007ffe0ff */
/*0fa0*/ IMAD.MOV R12, RZ, RZ, -R12 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0a0c */
/*0fb0*/ LOP3.LUT R15, R15, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000f0f7812 */
/* 0x000fc400078efcff */
/*0fc0*/ FSETP.NEU.FTZ.AND P0, PT, R10, R13, PT ; /* 0x0000000d0a00720b */
/* 0x000fe40003f1d000 */
/*0fd0*/ SHF.L.U32 R24, R15, R24, RZ ; /* 0x000000180f187219 */
/* 0x000fe400000006ff */
/*0fe0*/ SEL R10, R12, RZ, P3 ; /* 0x000000ff0c0a7207 */
/* 0x000fe40001800000 */
/*0ff0*/ ISETP.NE.AND P1, PT, R24, RZ, P1 ; /* 0x000000ff1800720c */
/* 0x000fe40000f25270 */
/*1000*/ SHF.R.U32.HI R10, RZ, R10, R15 ; /* 0x0000000aff0a7219 */
/* 0x000fe4000001160f */
/*1010*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40000703570 */
/*1020*/ SHF.R.U32.HI R13, RZ, 0x1, R10 ; /* 0x00000001ff0d7819 */
/* 0x000fe4000001160a */
/*1030*/ SEL R12, RZ, 0x1, !P0 ; /* 0x00000001ff0c7807 */
/* 0x000fc80004000000 */
/*1040*/ LOP3.LUT R15, R12, 0x1, R13, 0xf8, !PT ; /* 0x000000010c0f7812 */
/* 0x000fc800078ef80d */
/*1050*/ LOP3.LUT R10, R15, R10, RZ, 0xc0, !PT ; /* 0x0000000a0f0a7212 */
/* 0x000fca00078ec0ff */
/*1060*/ IMAD.IADD R10, R13, 0x1, R10 ; /* 0x000000010d0a7824 */
/* 0x000fca00078e020a */
/*1070*/ LOP3.LUT R25, R10, R25, RZ, 0xfc, !PT ; /* 0x000000190a197212 */
/* 0x000fe200078efcff */
/*1080*/ BRA 0x1160 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*1090*/ LOP3.LUT R25, R25, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000019197812 */
/* 0x000fc800078ec0ff */
/*10a0*/ LOP3.LUT R25, R25, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000019197812 */
/* 0x000fe200078efcff */
/*10b0*/ BRA 0x1160 ; /* 0x000000a000007947 */
/* 0x000fea0003800000 */
/*10c0*/ IMAD R25, R15, 0x800000, R25 ; /* 0x008000000f197824 */
/* 0x000fe200078e0219 */
/*10d0*/ BRA 0x1160 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*10e0*/ LOP3.LUT R25, R25, 0x80000000, R24, 0x48, !PT ; /* 0x8000000019197812 */
/* 0x000fc800078e4818 */
/*10f0*/ LOP3.LUT R25, R25, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000019197812 */
/* 0x000fe200078efcff */
/*1100*/ BRA 0x1160 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*1110*/ LOP3.LUT R25, R25, 0x80000000, R24, 0x48, !PT ; /* 0x8000000019197812 */
/* 0x000fe200078e4818 */
/*1120*/ BRA 0x1160 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*1130*/ MUFU.RSQ R25, -QNAN ; /* 0xffc0000000197908 */
/* 0x000e220000001400 */
/*1140*/ BRA 0x1160 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*1150*/ FADD.FTZ R25, R23, R13 ; /* 0x0000000d17197221 */
/* 0x000fe40000010000 */
/*1160*/ IMAD.MOV.U32 R15, RZ, RZ, 0x0 ; /* 0x00000000ff0f7424 */
/* 0x000fc800078e00ff */
/*1170*/ RET.REL.NODEC R14 0x0 ; /* 0xffffee800e007950 */
/* 0x000fea0003c3ffff */
/*1180*/ BRA 0x1180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/*
* CudaOperations.cu
*
* Created on: Feb 6, 2019
* Author: alexander
*/
__global__ void cudaKernelPull(float* mat, float* spins, int size, float* temp, float tempStep, float* meanFieldElements, bool* continueIteration, float minDiff, int* unemptyCells, float linearCoef) {
int blockId = blockIdx.x;
int thrId = threadIdx.x;
do {
// Lessen temperature
if (thrId == 0)
temp[blockId] = temp[blockId] - tempStep;
// Stabilize
do {
__syncthreads();
// By default current iteration is the last one
if (thrId == 0)
continueIteration[blockId] = false;
for (int spinId = 0; spinId < size; ++spinId) {
__syncthreads();
// Transitional value assignment
int wIndex = thrId;
while (wIndex < unemptyCells[spinId * (size + 1)]) {
meanFieldElements[wIndex + blockId * size] =
spins[unemptyCells[spinId * (size + 1) + wIndex + 1]
+ blockId * size]
* mat[spinId * size
+ unemptyCells[spinId * (size + 1)
+ wIndex + 1]];
// BEWARE: Matrix is symmetrical!
wIndex = wIndex + blockDim.x;
}
__syncthreads();
// Parallelized mean-field computation
long long offset = 1;
while (offset < unemptyCells[spinId * (size + 1)]) {
wIndex = thrId;
while ((wIndex * 2 + 1) * offset
< unemptyCells[spinId * (size + 1)]) {
meanFieldElements[wIndex * 2 * offset + blockId * size] +=
meanFieldElements[(wIndex * 2 + 1) * offset
+ blockId * size];
wIndex = wIndex + blockDim.x;
}
offset *= 2;
__syncthreads();
}
__syncthreads();
// Mean-field calculation complete - write new spin and delta
if (thrId == 0) {
float meanField = meanFieldElements[blockId * size];
float old = spins[spinId + blockId * size];
if (temp[blockId] > 0) {
spins[spinId + blockId * size] = -1
* tanh(meanField / temp[blockId]) * linearCoef
+ spins[spinId + blockId * size]
* (1 - linearCoef);
} else if (meanField > 0)
spins[spinId + blockId * size] = -1;
else
spins[spinId + blockId * size] = 1;
if (minDiff < fabs(old - spins[spinId + blockId * size]))
continueIteration[blockId] = true; // Too big delta. One more iteration needed
}
__syncthreads();
}
} while (continueIteration[blockId]);
} while (temp[blockId] >= 0);
} | .file "tmpxft_00147a92_00000000-6_cudaKernelPull.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z14cudaKernelPullPfS_iS_fS_PbfPifPfS_iS_fS_PbfPif
.type _Z48__device_stub__Z14cudaKernelPullPfS_iS_fS_PbfPifPfS_iS_fS_PbfPif, @function
_Z48__device_stub__Z14cudaKernelPullPfS_iS_fS_PbfPifPfS_iS_fS_PbfPif:
.LFB2051:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movl %edx, 44(%rsp)
movq %rcx, 32(%rsp)
movss %xmm0, 40(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movss %xmm1, 12(%rsp)
movss %xmm2, 8(%rsp)
movq 240(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
movq %rsp, %rax
movq %rax, 192(%rsp)
leaq 8(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z14cudaKernelPullPfS_iS_fS_PbfPif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z14cudaKernelPullPfS_iS_fS_PbfPifPfS_iS_fS_PbfPif, .-_Z48__device_stub__Z14cudaKernelPullPfS_iS_fS_PbfPifPfS_iS_fS_PbfPif
.globl _Z14cudaKernelPullPfS_iS_fS_PbfPif
.type _Z14cudaKernelPullPfS_iS_fS_PbfPif, @function
_Z14cudaKernelPullPfS_iS_fS_PbfPif:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z48__device_stub__Z14cudaKernelPullPfS_iS_fS_PbfPifPfS_iS_fS_PbfPif
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14cudaKernelPullPfS_iS_fS_PbfPif, .-_Z14cudaKernelPullPfS_iS_fS_PbfPif
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z14cudaKernelPullPfS_iS_fS_PbfPif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14cudaKernelPullPfS_iS_fS_PbfPif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/*
* CudaOperations.cu
*
* Created on: Feb 6, 2019
* Author: alexander
*/
__global__ void cudaKernelPull(float* mat, float* spins, int size, float* temp, float tempStep, float* meanFieldElements, bool* continueIteration, float minDiff, int* unemptyCells, float linearCoef) {
int blockId = blockIdx.x;
int thrId = threadIdx.x;
do {
// Lessen temperature
if (thrId == 0)
temp[blockId] = temp[blockId] - tempStep;
// Stabilize
do {
__syncthreads();
// By default current iteration is the last one
if (thrId == 0)
continueIteration[blockId] = false;
for (int spinId = 0; spinId < size; ++spinId) {
__syncthreads();
// Transitional value assignment
int wIndex = thrId;
while (wIndex < unemptyCells[spinId * (size + 1)]) {
meanFieldElements[wIndex + blockId * size] =
spins[unemptyCells[spinId * (size + 1) + wIndex + 1]
+ blockId * size]
* mat[spinId * size
+ unemptyCells[spinId * (size + 1)
+ wIndex + 1]];
// BEWARE: Matrix is symmetrical!
wIndex = wIndex + blockDim.x;
}
__syncthreads();
// Parallelized mean-field computation
long long offset = 1;
while (offset < unemptyCells[spinId * (size + 1)]) {
wIndex = thrId;
while ((wIndex * 2 + 1) * offset
< unemptyCells[spinId * (size + 1)]) {
meanFieldElements[wIndex * 2 * offset + blockId * size] +=
meanFieldElements[(wIndex * 2 + 1) * offset
+ blockId * size];
wIndex = wIndex + blockDim.x;
}
offset *= 2;
__syncthreads();
}
__syncthreads();
// Mean-field calculation complete - write new spin and delta
if (thrId == 0) {
float meanField = meanFieldElements[blockId * size];
float old = spins[spinId + blockId * size];
if (temp[blockId] > 0) {
spins[spinId + blockId * size] = -1
* tanh(meanField / temp[blockId]) * linearCoef
+ spins[spinId + blockId * size]
* (1 - linearCoef);
} else if (meanField > 0)
spins[spinId + blockId * size] = -1;
else
spins[spinId + blockId * size] = 1;
if (minDiff < fabs(old - spins[spinId + blockId * size]))
continueIteration[blockId] = true; // Too big delta. One more iteration needed
}
__syncthreads();
}
} while (continueIteration[blockId]);
} while (temp[blockId] >= 0);
} | #include <hip/hip_runtime.h>
#include "includes.h"
/*
* CudaOperations.cu
*
* Created on: Feb 6, 2019
* Author: alexander
*/
__global__ void cudaKernelPull(float* mat, float* spins, int size, float* temp, float tempStep, float* meanFieldElements, bool* continueIteration, float minDiff, int* unemptyCells, float linearCoef) {
int blockId = blockIdx.x;
int thrId = threadIdx.x;
do {
// Lessen temperature
if (thrId == 0)
temp[blockId] = temp[blockId] - tempStep;
// Stabilize
do {
__syncthreads();
// By default current iteration is the last one
if (thrId == 0)
continueIteration[blockId] = false;
for (int spinId = 0; spinId < size; ++spinId) {
__syncthreads();
// Transitional value assignment
int wIndex = thrId;
while (wIndex < unemptyCells[spinId * (size + 1)]) {
meanFieldElements[wIndex + blockId * size] =
spins[unemptyCells[spinId * (size + 1) + wIndex + 1]
+ blockId * size]
* mat[spinId * size
+ unemptyCells[spinId * (size + 1)
+ wIndex + 1]];
// BEWARE: Matrix is symmetrical!
wIndex = wIndex + blockDim.x;
}
__syncthreads();
// Parallelized mean-field computation
long long offset = 1;
while (offset < unemptyCells[spinId * (size + 1)]) {
wIndex = thrId;
while ((wIndex * 2 + 1) * offset
< unemptyCells[spinId * (size + 1)]) {
meanFieldElements[wIndex * 2 * offset + blockId * size] +=
meanFieldElements[(wIndex * 2 + 1) * offset
+ blockId * size];
wIndex = wIndex + blockDim.x;
}
offset *= 2;
__syncthreads();
}
__syncthreads();
// Mean-field calculation complete - write new spin and delta
if (thrId == 0) {
float meanField = meanFieldElements[blockId * size];
float old = spins[spinId + blockId * size];
if (temp[blockId] > 0) {
spins[spinId + blockId * size] = -1
* tanh(meanField / temp[blockId]) * linearCoef
+ spins[spinId + blockId * size]
* (1 - linearCoef);
} else if (meanField > 0)
spins[spinId + blockId * size] = -1;
else
spins[spinId + blockId * size] = 1;
if (minDiff < fabs(old - spins[spinId + blockId * size]))
continueIteration[blockId] = true; // Too big delta. One more iteration needed
}
__syncthreads();
}
} while (continueIteration[blockId]);
} while (temp[blockId] >= 0);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*
* CudaOperations.cu
*
* Created on: Feb 6, 2019
* Author: alexander
*/
__global__ void cudaKernelPull(float* mat, float* spins, int size, float* temp, float tempStep, float* meanFieldElements, bool* continueIteration, float minDiff, int* unemptyCells, float linearCoef) {
int blockId = blockIdx.x;
int thrId = threadIdx.x;
do {
// Lessen temperature
if (thrId == 0)
temp[blockId] = temp[blockId] - tempStep;
// Stabilize
do {
__syncthreads();
// By default current iteration is the last one
if (thrId == 0)
continueIteration[blockId] = false;
for (int spinId = 0; spinId < size; ++spinId) {
__syncthreads();
// Transitional value assignment
int wIndex = thrId;
while (wIndex < unemptyCells[spinId * (size + 1)]) {
meanFieldElements[wIndex + blockId * size] =
spins[unemptyCells[spinId * (size + 1) + wIndex + 1]
+ blockId * size]
* mat[spinId * size
+ unemptyCells[spinId * (size + 1)
+ wIndex + 1]];
// BEWARE: Matrix is symmetrical!
wIndex = wIndex + blockDim.x;
}
__syncthreads();
// Parallelized mean-field computation
long long offset = 1;
while (offset < unemptyCells[spinId * (size + 1)]) {
wIndex = thrId;
while ((wIndex * 2 + 1) * offset
< unemptyCells[spinId * (size + 1)]) {
meanFieldElements[wIndex * 2 * offset + blockId * size] +=
meanFieldElements[(wIndex * 2 + 1) * offset
+ blockId * size];
wIndex = wIndex + blockDim.x;
}
offset *= 2;
__syncthreads();
}
__syncthreads();
// Mean-field calculation complete - write new spin and delta
if (thrId == 0) {
float meanField = meanFieldElements[blockId * size];
float old = spins[spinId + blockId * size];
if (temp[blockId] > 0) {
spins[spinId + blockId * size] = -1
* tanh(meanField / temp[blockId]) * linearCoef
+ spins[spinId + blockId * size]
* (1 - linearCoef);
} else if (meanField > 0)
spins[spinId + blockId * size] = -1;
else
spins[spinId + blockId * size] = 1;
if (minDiff < fabs(old - spins[spinId + blockId * size]))
continueIteration[blockId] = true; // Too big delta. One more iteration needed
}
__syncthreads();
}
} while (continueIteration[blockId]);
} while (temp[blockId] >= 0);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14cudaKernelPullPfS_iS_fS_PbfPif
.globl _Z14cudaKernelPullPfS_iS_fS_PbfPif
.p2align 8
.type _Z14cudaKernelPullPfS_iS_fS_PbfPif,@function
_Z14cudaKernelPullPfS_iS_fS_PbfPif:
s_clause 0x6
s_load_b64 s[16:17], s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x28
s_load_b32 s3, s[0:1], 0x10
s_load_b64 s[12:13], s[0:1], 0x40
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b32 s26, s[0:1], 0x48
s_load_b32 s28, s[0:1], 0x38
s_mov_b32 s18, s15
s_load_b32 s27, s[0:1], 0x20
s_ashr_i32 s19, s18, 31
v_mov_b32_e32 v2, 0
s_lshl_b64 s[20:21], s[18:19], 2
v_cmp_eq_u32_e64 s2, 0, v0
s_mov_b32 s15, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s16, s16, s20
s_addc_u32 s17, s17, s21
s_add_u32 s6, s6, s18
s_addc_u32 s7, s7, s19
s_cmp_gt_i32 s3, 0
s_mul_i32 s18, s18, s3
s_cselect_b32 s29, -1, 0
s_add_i32 s30, s3, 1
s_add_u32 s31, s12, 4
s_addc_u32 s33, s13, 0
s_add_u32 s20, s0, 0x50
s_addc_u32 s21, s1, 0
s_ashr_i32 s19, s18, 31
v_sub_f32_e64 v7, 1.0, s26
s_lshl_b64 s[0:1], s[18:19], 2
s_mov_b32 s19, 0xbbbac73d
s_add_u32 s22, s4, s0
s_addc_u32 s23, s5, s1
s_branch .LBB0_2
.LBB0_1:
global_load_b32 v1, v2, s[16:17]
s_waitcnt vmcnt(0)
v_cmp_le_f32_e32 vcc_lo, 0, v1
s_cbranch_vccz .LBB0_32
.LBB0_2:
s_and_saveexec_b32 s0, s2
s_cbranch_execz .LBB0_4
global_load_b32 v1, v2, s[16:17]
s_waitcnt vmcnt(0)
v_subrev_f32_e32 v1, s27, v1
global_store_b32 v2, v1, s[16:17]
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s0
s_branch .LBB0_6
.LBB0_5:
global_load_u8 v1, v2, s[6:7]
s_waitcnt vmcnt(0)
v_cmp_eq_u16_e32 vcc_lo, 0, v1
s_cbranch_vccnz .LBB0_1
.LBB0_6:
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s0, s2
s_cbranch_execz .LBB0_8
v_mov_b32_e32 v1, 0
global_store_b8 v2, v1, s[6:7]
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s29
s_cbranch_vccnz .LBB0_5
s_mov_b32 s34, 0
s_mov_b32 s35, 0
s_branch .LBB0_11
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s14
s_add_i32 s35, s35, 1
s_add_i32 s34, s34, s30
s_cmp_eq_u32 s35, s3
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_5
.LBB0_11:
s_mul_i32 s14, s35, s30
s_waitcnt_vscnt null, 0x0
s_lshl_b64 s[0:1], s[14:15], 2
s_barrier
s_add_u32 s24, s12, s0
s_addc_u32 s25, s13, s1
buffer_gl0_inv
global_load_b32 v1, v2, s[24:25]
s_mov_b32 s1, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v0, v1
s_cbranch_execz .LBB0_14
s_load_b32 s0, s[20:21], 0xc
v_mov_b32_e32 v3, v0
s_mul_i32 s14, s35, s3
s_mov_b32 s37, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s36, s0, 0xffff
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_13:
v_add_nc_u32_e32 v4, s34, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s31, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s33, v5, vcc_lo
global_load_b32 v5, v[4:5], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, s18, v5
v_add_nc_u32_e32 v8, s14, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s10, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v8, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
global_load_b32 v6, v[4:5], off
global_load_b32 v8, v[8:9], off
v_add_nc_u32_e32 v4, s18, v3
v_add_nc_u32_e32 v3, s36, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s0, s4, v4
v_add_co_ci_u32_e64 v5, s0, s5, v5, s0
s_waitcnt vmcnt(0)
v_mul_f32_e32 v6, v6, v8
v_cmp_ge_i32_e32 vcc_lo, v3, v1
global_store_b32 v[4:5], v6, off
s_or_b32 s37, vcc_lo, s37
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s37
s_cbranch_execnz .LBB0_13
.LBB0_14:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s1
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_load_b32 v1, v2, s[24:25]
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, 2, v1
s_cbranch_vccnz .LBB0_21
v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
s_mov_b64 s[0:1], 1
s_branch .LBB0_17
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_load_b32 v3, v2, s[24:25]
s_lshl_b64 s[0:1], s[0:1], 1
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i64_e32 vcc_lo, s[0:1], v[3:4]
s_cbranch_vccz .LBB0_21
.LBB0_17:
v_mov_b32_e32 v1, v0
s_mov_b32 s14, 0
s_branch .LBB0_19
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s37
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s37, exec_lo, s36
s_or_b32 s14, s37, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s14
s_cbranch_execz .LBB0_16
.LBB0_19:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v8, 1, v1
s_or_b32 s36, s36, exec_lo
s_mov_b32 s37, exec_lo
v_ashrrev_i32_e32 v9, 31, v8
v_or_b32_e32 v10, 1, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v11, s0, v9
v_mul_lo_u32 v12, s1, v10
v_mad_u64_u32 v[5:6], null, s0, v10, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v6, v6, v11, v12
v_cmpx_lt_i64_e64 v[5:6], v[3:4]
s_cbranch_execz .LBB0_18
v_mul_lo_u32 v11, s1, v8
v_mul_lo_u32 v12, s0, v9
v_mad_u64_u32 v[9:10], null, s0, v8, 0
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_and_not1_b32 s36, s36, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s22, v5
v_add3_u32 v10, v10, v12, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s23, v6, vcc_lo
v_lshlrev_b64 v[8:9], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s22, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s23, v9, vcc_lo
s_clause 0x1
global_load_b32 v5, v[5:6], off
global_load_b32 v6, v[8:9], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v5, v5, v6
global_store_b32 v[8:9], v5, off
s_load_b32 s38, s[20:21], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s38, s38, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_add_nc_u32_e32 v1, s38, v1
s_branch .LBB0_18
.LBB0_21:
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s14, s2
s_cbranch_execz .LBB0_10
s_add_i32 s0, s35, s18
global_load_b32 v3, v2, s[16:17]
s_ashr_i32 s1, s0, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[0:1], 2
s_add_u32 s0, s10, s0
s_addc_u32 s1, s11, s1
s_clause 0x1
global_load_b32 v4, v2, s[22:23]
global_load_b32 v1, v2, s[0:1]
s_waitcnt vmcnt(2)
v_cmp_nlt_f32_e32 vcc_lo, 0, v3
s_cbranch_vccz .LBB0_24
s_waitcnt vmcnt(1)
v_cmp_lt_f32_e32 vcc_lo, 0, v4
v_cndmask_b32_e64 v5, 1.0, -1.0, vcc_lo
s_cbranch_execz .LBB0_25
s_branch .LBB0_30
.LBB0_24:
.LBB0_25:
s_waitcnt vmcnt(1)
v_div_scale_f32 v5, null, v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v6, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v5, v6, 1.0
v_fmac_f32_e32 v6, v8, v6
v_div_scale_f32 v8, vcc_lo, v4, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v9, v8, v6
v_fma_f32 v10, -v5, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v9, v10, v6
v_fma_f32 v5, -v5, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v5, v5, v6, v9
v_div_fixup_f32 v3, v5, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ngt_f32_e64 s24, 0x3f200000, |v3|
s_and_b32 vcc_lo, exec_lo, s24
s_cbranch_vccz .LBB0_27
v_add_f32_e64 v4, |v3|, |v3|
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v5, 0x3fb8aa3b, v4
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v4
v_rndne_f32_e32 v6, v5
v_fma_f32 v8, v4, 0x3fb8aa3b, -v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_sub_f32 v5, v5, v6 :: v_dual_fmac_f32 v8, 0x32a5705f, v4
v_cvt_i32_f32_e32 v6, v6
v_add_f32_e32 v5, v5, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v5, v5
s_waitcnt_depctr 0xfff
v_ldexp_f32 v5, v5, v6
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, 0x7f800000, v5, vcc_lo
v_add_f32_e32 v4, 1.0, v4
s_delay_alu instid0(VALU_DEP_1)
v_rcp_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v4, v4, -2.0, 1.0
s_cbranch_execz .LBB0_28
s_branch .LBB0_29
.LBB0_27:
.LBB0_28:
v_mul_f32_e32 v4, v3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v5, s19, v4, 0x3ca908c9
v_fmaak_f32 v5, v4, v5, 0xbd5c1c4e
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v5, v4, v5, 0x3e088382
v_fmaak_f32 v5, v4, v5, 0xbeaaaa99
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e64 v5, |v3|, v5
v_fma_f32 v4, v4, v5, |v3|
.LBB0_29:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_bfi_b32 v3, 0x7fffffff, v4, v3
v_mul_f32_e32 v3, s26, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fma_f32 v5, v7, v1, -v3
.LBB0_30:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_sub_f32_e32 v1, v1, v5
global_store_b32 v2, v5, s[0:1]
v_cmp_ngt_f32_e64 s24, |v1|, s28
s_and_b32 vcc_lo, exec_lo, s24
s_cbranch_vccnz .LBB0_10
v_mov_b32_e32 v1, 1
global_store_b8 v2, v1, s[6:7]
s_branch .LBB0_10
.LBB0_32:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14cudaKernelPullPfS_iS_fS_PbfPif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 336
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 39
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14cudaKernelPullPfS_iS_fS_PbfPif, .Lfunc_end0-_Z14cudaKernelPullPfS_iS_fS_PbfPif
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .offset: 72
.size: 4
.value_kind: by_value
- .offset: 80
.size: 4
.value_kind: hidden_block_count_x
- .offset: 84
.size: 4
.value_kind: hidden_block_count_y
- .offset: 88
.size: 4
.value_kind: hidden_block_count_z
- .offset: 92
.size: 2
.value_kind: hidden_group_size_x
- .offset: 94
.size: 2
.value_kind: hidden_group_size_y
- .offset: 96
.size: 2
.value_kind: hidden_group_size_z
- .offset: 98
.size: 2
.value_kind: hidden_remainder_x
- .offset: 100
.size: 2
.value_kind: hidden_remainder_y
- .offset: 102
.size: 2
.value_kind: hidden_remainder_z
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 144
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 336
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14cudaKernelPullPfS_iS_fS_PbfPif
.private_segment_fixed_size: 0
.sgpr_count: 41
.sgpr_spill_count: 0
.symbol: _Z14cudaKernelPullPfS_iS_fS_PbfPif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/*
* CudaOperations.cu
*
* Created on: Feb 6, 2019
* Author: alexander
*/
__global__ void cudaKernelPull(float* mat, float* spins, int size, float* temp, float tempStep, float* meanFieldElements, bool* continueIteration, float minDiff, int* unemptyCells, float linearCoef) {
int blockId = blockIdx.x;
int thrId = threadIdx.x;
do {
// Lessen temperature
if (thrId == 0)
temp[blockId] = temp[blockId] - tempStep;
// Stabilize
do {
__syncthreads();
// By default current iteration is the last one
if (thrId == 0)
continueIteration[blockId] = false;
for (int spinId = 0; spinId < size; ++spinId) {
__syncthreads();
// Transitional value assignment
int wIndex = thrId;
while (wIndex < unemptyCells[spinId * (size + 1)]) {
meanFieldElements[wIndex + blockId * size] =
spins[unemptyCells[spinId * (size + 1) + wIndex + 1]
+ blockId * size]
* mat[spinId * size
+ unemptyCells[spinId * (size + 1)
+ wIndex + 1]];
// BEWARE: Matrix is symmetrical!
wIndex = wIndex + blockDim.x;
}
__syncthreads();
// Parallelized mean-field computation
long long offset = 1;
while (offset < unemptyCells[spinId * (size + 1)]) {
wIndex = thrId;
while ((wIndex * 2 + 1) * offset
< unemptyCells[spinId * (size + 1)]) {
meanFieldElements[wIndex * 2 * offset + blockId * size] +=
meanFieldElements[(wIndex * 2 + 1) * offset
+ blockId * size];
wIndex = wIndex + blockDim.x;
}
offset *= 2;
__syncthreads();
}
__syncthreads();
// Mean-field calculation complete - write new spin and delta
if (thrId == 0) {
float meanField = meanFieldElements[blockId * size];
float old = spins[spinId + blockId * size];
if (temp[blockId] > 0) {
spins[spinId + blockId * size] = -1
* tanh(meanField / temp[blockId]) * linearCoef
+ spins[spinId + blockId * size]
* (1 - linearCoef);
} else if (meanField > 0)
spins[spinId + blockId * size] = -1;
else
spins[spinId + blockId * size] = 1;
if (minDiff < fabs(old - spins[spinId + blockId * size]))
continueIteration[blockId] = true; // Too big delta. One more iteration needed
}
__syncthreads();
}
} while (continueIteration[blockId]);
} while (temp[blockId] >= 0);
} | .text
.file "cudaKernelPull.hip"
.globl _Z29__device_stub__cudaKernelPullPfS_iS_fS_PbfPif # -- Begin function _Z29__device_stub__cudaKernelPullPfS_iS_fS_PbfPif
.p2align 4, 0x90
.type _Z29__device_stub__cudaKernelPullPfS_iS_fS_PbfPif,@function
_Z29__device_stub__cudaKernelPullPfS_iS_fS_PbfPif: # @_Z29__device_stub__cudaKernelPullPfS_iS_fS_PbfPif
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 88(%rsp)
movss %xmm0, 16(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
movss %xmm1, 12(%rsp)
movss %xmm2, 8(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rax
movq %rax, 152(%rsp)
leaq 72(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 208(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z14cudaKernelPullPfS_iS_fS_PbfPif, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z29__device_stub__cudaKernelPullPfS_iS_fS_PbfPif, .Lfunc_end0-_Z29__device_stub__cudaKernelPullPfS_iS_fS_PbfPif
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14cudaKernelPullPfS_iS_fS_PbfPif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14cudaKernelPullPfS_iS_fS_PbfPif,@object # @_Z14cudaKernelPullPfS_iS_fS_PbfPif
.section .rodata,"a",@progbits
.globl _Z14cudaKernelPullPfS_iS_fS_PbfPif
.p2align 3, 0x0
_Z14cudaKernelPullPfS_iS_fS_PbfPif:
.quad _Z29__device_stub__cudaKernelPullPfS_iS_fS_PbfPif
.size _Z14cudaKernelPullPfS_iS_fS_PbfPif, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14cudaKernelPullPfS_iS_fS_PbfPif"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__cudaKernelPullPfS_iS_fS_PbfPif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14cudaKernelPullPfS_iS_fS_PbfPif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00147a92_00000000-6_cudaKernelPull.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z14cudaKernelPullPfS_iS_fS_PbfPifPfS_iS_fS_PbfPif
.type _Z48__device_stub__Z14cudaKernelPullPfS_iS_fS_PbfPifPfS_iS_fS_PbfPif, @function
_Z48__device_stub__Z14cudaKernelPullPfS_iS_fS_PbfPifPfS_iS_fS_PbfPif:
.LFB2051:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movl %edx, 44(%rsp)
movq %rcx, 32(%rsp)
movss %xmm0, 40(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movss %xmm1, 12(%rsp)
movss %xmm2, 8(%rsp)
movq 240(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
leaq 24(%rsp), %rax
movq %rax, 168(%rsp)
leaq 16(%rsp), %rax
movq %rax, 176(%rsp)
leaq 12(%rsp), %rax
movq %rax, 184(%rsp)
movq %rsp, %rax
movq %rax, 192(%rsp)
leaq 8(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z14cudaKernelPullPfS_iS_fS_PbfPif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z14cudaKernelPullPfS_iS_fS_PbfPifPfS_iS_fS_PbfPif, .-_Z48__device_stub__Z14cudaKernelPullPfS_iS_fS_PbfPifPfS_iS_fS_PbfPif
.globl _Z14cudaKernelPullPfS_iS_fS_PbfPif
.type _Z14cudaKernelPullPfS_iS_fS_PbfPif, @function
_Z14cudaKernelPullPfS_iS_fS_PbfPif:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z48__device_stub__Z14cudaKernelPullPfS_iS_fS_PbfPifPfS_iS_fS_PbfPif
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14cudaKernelPullPfS_iS_fS_PbfPif, .-_Z14cudaKernelPullPfS_iS_fS_PbfPif
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z14cudaKernelPullPfS_iS_fS_PbfPif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14cudaKernelPullPfS_iS_fS_PbfPif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cudaKernelPull.hip"
.globl _Z29__device_stub__cudaKernelPullPfS_iS_fS_PbfPif # -- Begin function _Z29__device_stub__cudaKernelPullPfS_iS_fS_PbfPif
.p2align 4, 0x90
.type _Z29__device_stub__cudaKernelPullPfS_iS_fS_PbfPif,@function
_Z29__device_stub__cudaKernelPullPfS_iS_fS_PbfPif: # @_Z29__device_stub__cudaKernelPullPfS_iS_fS_PbfPif
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 88(%rsp)
movss %xmm0, 16(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
movss %xmm1, 12(%rsp)
movss %xmm2, 8(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rax
movq %rax, 152(%rsp)
leaq 72(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 208(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z14cudaKernelPullPfS_iS_fS_PbfPif, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z29__device_stub__cudaKernelPullPfS_iS_fS_PbfPif, .Lfunc_end0-_Z29__device_stub__cudaKernelPullPfS_iS_fS_PbfPif
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14cudaKernelPullPfS_iS_fS_PbfPif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14cudaKernelPullPfS_iS_fS_PbfPif,@object # @_Z14cudaKernelPullPfS_iS_fS_PbfPif
.section .rodata,"a",@progbits
.globl _Z14cudaKernelPullPfS_iS_fS_PbfPif
.p2align 3, 0x0
_Z14cudaKernelPullPfS_iS_fS_PbfPif:
.quad _Z29__device_stub__cudaKernelPullPfS_iS_fS_PbfPif
.size _Z14cudaKernelPullPfS_iS_fS_PbfPif, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14cudaKernelPullPfS_iS_fS_PbfPif"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__cudaKernelPullPfS_iS_fS_PbfPif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14cudaKernelPullPfS_iS_fS_PbfPif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<iostream>
#include <fstream>
#include <string>
#include <stdio.h>
#include <stdlib.h>
using namespace std;
__global__ void kernel( float* r_gpu, float* g_gpu, float* b_gpu, int N) {
int tId = threadIdx.x + blockIdx.x * blockDim.x;
if(tId < N) {
r_gpu[tId] = 1 - r_gpu[tId];
g_gpu[tId] = 1 - g_gpu[tId];
b_gpu[tId] = 1 - b_gpu[tId];
}
}
void CambiarColores(float* r, float* g, float* b) {
//cout << *r << "|" << 1-*r << endl;
*r = 1 - *r;
*g = 1 - *g;
*b = 1 - *b;
}
int main(int argc, char const *argv[]) {
FILE * pFile;
int n, m;
float* r, *g, *b;
pFile = fopen ("img.txt","r");
fscanf(pFile, "%d %d", &m, &n);
int block_size = 256;
int grid_size = (int) ceil((float) n*m / block_size);
float* r_gpu, *g_gpu, *b_gpu;
cudaMalloc(&r_gpu, sizeof(float) * n * m);
cudaMalloc(&g_gpu, sizeof(float) * n * m);
cudaMalloc(&b_gpu, sizeof(float) * n * m);
r = new float[n*m];
g = new float[n*m];
b = new float[n*m];
for (int i = 0; i < n*m; ++i) {
fscanf (pFile, "%f", &r[i]);
}
for (int i = 0; i < n*m; ++i) {
fscanf (pFile, "%f", &g[i]);
}
for (int i = 0; i < n*m; ++i) {
fscanf (pFile, "%f", &b[i]);
}
fclose (pFile);
cudaMemcpy(r_gpu, r, sizeof(float) * n * m, cudaMemcpyHostToDevice);
cudaMemcpy(g_gpu, g, sizeof(float) * n * m, cudaMemcpyHostToDevice);
cudaMemcpy(b_gpu, b, sizeof(float) * n * m, cudaMemcpyHostToDevice);
int tamanio = n * m;
cudaEvent_t ct1, ct2;
float dt;
cudaEventCreate(&ct1);
cudaEventCreate(&ct2);
cudaEventRecord(ct1);
kernel<<<grid_size, block_size>>>(r_gpu, g_gpu, b_gpu, tamanio);
cudaEventRecord(ct2);
cudaEventSynchronize(ct2);
cudaEventElapsedTime(&dt, ct1, ct2);
cout << "Tiempo GPU: " << dt << " [ms]" << endl;
cudaMemcpy(r, r_gpu, sizeof(float) * n * m, cudaMemcpyDeviceToHost);
cudaMemcpy(g, g_gpu, sizeof(float) * n * m, cudaMemcpyDeviceToHost);
cudaMemcpy(b, b_gpu, sizeof(float) * n * m, cudaMemcpyDeviceToHost);
cudaFree(r_gpu);
cudaFree(g_gpu);
cudaFree(b_gpu);
FILE * pSalida;
pSalida = fopen ("img_salida.txt","w");
fprintf(pSalida, "%d %d\n", m, n);
for (int i = 0; i < n*m; ++i) {
if(i == n*m - 1) {
fprintf(pSalida, "%f", r[i]);
} else {
fprintf(pSalida, "%f ", r[i]);
}
}
fprintf(pSalida, "\n");
for (int i = 0; i < n*m; ++i) {
if(i == n*m - 1) {
fprintf(pSalida, "%f", g[i]);
} else {
fprintf(pSalida, "%f ", g[i]);
}
}
fprintf(pSalida, "\n");
for (int i = 0; i < n*m; ++i) {
if(i == n*m - 1) {
fprintf(pSalida, "%f", b[i]);
} else {
fprintf(pSalida, "%f ", b[i]);
}
}
delete r;
delete g;
delete b;
//cin.get();
return 0;
} | code for sm_80
Function : _Z6kernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fca00078e0207 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*00b0*/ FADD R9, -R0, 1 ; /* 0x3f80000000097421 */
/* 0x004fca0000000100 */
/*00c0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*00d0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00f0*/ FADD R11, -R0, 1 ; /* 0x3f800000000b7421 */
/* 0x004fca0000000100 */
/*0100*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x000fe8000c101904 */
/*0110*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000ea4000c1e1900 */
/*0120*/ FADD R13, -R0, 1 ; /* 0x3f800000000d7421 */
/* 0x004fca0000000100 */
/*0130*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<iostream>
#include <fstream>
#include <string>
#include <stdio.h>
#include <stdlib.h>
using namespace std;
__global__ void kernel( float* r_gpu, float* g_gpu, float* b_gpu, int N) {
int tId = threadIdx.x + blockIdx.x * blockDim.x;
if(tId < N) {
r_gpu[tId] = 1 - r_gpu[tId];
g_gpu[tId] = 1 - g_gpu[tId];
b_gpu[tId] = 1 - b_gpu[tId];
}
}
void CambiarColores(float* r, float* g, float* b) {
//cout << *r << "|" << 1-*r << endl;
*r = 1 - *r;
*g = 1 - *g;
*b = 1 - *b;
}
int main(int argc, char const *argv[]) {
FILE * pFile;
int n, m;
float* r, *g, *b;
pFile = fopen ("img.txt","r");
fscanf(pFile, "%d %d", &m, &n);
int block_size = 256;
int grid_size = (int) ceil((float) n*m / block_size);
float* r_gpu, *g_gpu, *b_gpu;
cudaMalloc(&r_gpu, sizeof(float) * n * m);
cudaMalloc(&g_gpu, sizeof(float) * n * m);
cudaMalloc(&b_gpu, sizeof(float) * n * m);
r = new float[n*m];
g = new float[n*m];
b = new float[n*m];
for (int i = 0; i < n*m; ++i) {
fscanf (pFile, "%f", &r[i]);
}
for (int i = 0; i < n*m; ++i) {
fscanf (pFile, "%f", &g[i]);
}
for (int i = 0; i < n*m; ++i) {
fscanf (pFile, "%f", &b[i]);
}
fclose (pFile);
cudaMemcpy(r_gpu, r, sizeof(float) * n * m, cudaMemcpyHostToDevice);
cudaMemcpy(g_gpu, g, sizeof(float) * n * m, cudaMemcpyHostToDevice);
cudaMemcpy(b_gpu, b, sizeof(float) * n * m, cudaMemcpyHostToDevice);
int tamanio = n * m;
cudaEvent_t ct1, ct2;
float dt;
cudaEventCreate(&ct1);
cudaEventCreate(&ct2);
cudaEventRecord(ct1);
kernel<<<grid_size, block_size>>>(r_gpu, g_gpu, b_gpu, tamanio);
cudaEventRecord(ct2);
cudaEventSynchronize(ct2);
cudaEventElapsedTime(&dt, ct1, ct2);
cout << "Tiempo GPU: " << dt << " [ms]" << endl;
cudaMemcpy(r, r_gpu, sizeof(float) * n * m, cudaMemcpyDeviceToHost);
cudaMemcpy(g, g_gpu, sizeof(float) * n * m, cudaMemcpyDeviceToHost);
cudaMemcpy(b, b_gpu, sizeof(float) * n * m, cudaMemcpyDeviceToHost);
cudaFree(r_gpu);
cudaFree(g_gpu);
cudaFree(b_gpu);
FILE * pSalida;
pSalida = fopen ("img_salida.txt","w");
fprintf(pSalida, "%d %d\n", m, n);
for (int i = 0; i < n*m; ++i) {
if(i == n*m - 1) {
fprintf(pSalida, "%f", r[i]);
} else {
fprintf(pSalida, "%f ", r[i]);
}
}
fprintf(pSalida, "\n");
for (int i = 0; i < n*m; ++i) {
if(i == n*m - 1) {
fprintf(pSalida, "%f", g[i]);
} else {
fprintf(pSalida, "%f ", g[i]);
}
}
fprintf(pSalida, "\n");
for (int i = 0; i < n*m; ++i) {
if(i == n*m - 1) {
fprintf(pSalida, "%f", b[i]);
} else {
fprintf(pSalida, "%f ", b[i]);
}
}
delete r;
delete g;
delete b;
//cin.get();
return 0;
} | .file "tmpxft_00056b83_00000000-6_invertir_colores_gpu.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3804:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3804:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14CambiarColoresPfS_S_
.type _Z14CambiarColoresPfS_S_, @function
_Z14CambiarColoresPfS_S_:
.LFB3800:
.cfi_startproc
endbr64
movss .LC0(%rip), %xmm0
movaps %xmm0, %xmm1
subss (%rdi), %xmm1
movss %xmm1, (%rdi)
movaps %xmm0, %xmm1
subss (%rsi), %xmm1
movss %xmm1, (%rsi)
subss (%rdx), %xmm0
movss %xmm0, (%rdx)
ret
.cfi_endproc
.LFE3800:
.size _Z14CambiarColoresPfS_S_, .-_Z14CambiarColoresPfS_S_
.globl _Z30__device_stub__Z6kernelPfS_S_iPfS_S_i
.type _Z30__device_stub__Z6kernelPfS_S_iPfS_S_i, @function
_Z30__device_stub__Z6kernelPfS_S_iPfS_S_i:
.LFB3826:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L8
.L4:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L4
.L9:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3826:
.size _Z30__device_stub__Z6kernelPfS_S_iPfS_S_i, .-_Z30__device_stub__Z6kernelPfS_S_iPfS_S_i
.globl _Z6kernelPfS_S_i
.type _Z6kernelPfS_S_i, @function
_Z6kernelPfS_S_i:
.LFB3827:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6kernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3827:
.size _Z6kernelPfS_S_i, .-_Z6kernelPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "r"
.LC2:
.string "img.txt"
.LC3:
.string "%d %d"
.LC7:
.string "%f"
.LC8:
.string "Tiempo GPU: "
.LC9:
.string " [ms]"
.LC10:
.string "w"
.LC11:
.string "img_salida.txt"
.LC12:
.string "%d %d\n"
.LC13:
.string "%f "
.LC14:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3801:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq .LC1(%rip), %rsi
leaq .LC2(%rip), %rdi
call fopen@PLT
movq %rax, %rbx
leaq 16(%rsp), %rcx
leaq 20(%rsp), %rdx
leaq .LC3(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 16(%rsp), %eax
movl 20(%rsp), %edx
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %edx, %xmm1
mulss %xmm1, %xmm0
mulss .LC4(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC15(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC5(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L13
cvttss2sil %xmm0, %ecx
pxor %xmm1, %xmm1
cvtsi2ssl %ecx, %xmm1
cmpnless %xmm1, %xmm3
movss .LC0(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L13:
cvttss2sil %xmm3, %ecx
movl %ecx, 12(%rsp)
movslq %eax, %rsi
movslq %edx, %rdx
movq %rsi, %rax
imulq %rdx, %rax
leaq 0(,%rax,4), %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movslq 16(%rsp), %rsi
movslq 20(%rsp), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
movslq 16(%rsp), %rsi
movslq 20(%rsp), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 40(%rsp), %rdi
call cudaMalloc@PLT
movl 16(%rsp), %edi
imull 20(%rsp), %edi
movslq %edi, %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L14
salq $2, %rdi
call _Znam@PLT
movq %rax, %r13
movl 16(%rsp), %edi
imull 20(%rsp), %edi
movslq %edi, %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L52
salq $2, %rdi
call _Znam@PLT
movq %rax, %r15
movl 16(%rsp), %edi
imull 20(%rsp), %edi
movslq %edi, %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L53
salq $2, %rdi
call _Znam@PLT
movq %rax, %r14
movl 16(%rsp), %eax
imull 20(%rsp), %eax
movq %r13, %r12
movl $0, %ebp
testl %eax, %eax
jle .L26
.L24:
movq %r12, %rdx
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %ebp
movl 16(%rsp), %eax
imull 20(%rsp), %eax
addq $4, %r12
cmpl %ebp, %eax
jg .L24
testl %eax, %eax
jle .L26
movq %r15, %r12
movl $0, %ebp
.L25:
movq %r12, %rdx
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %ebp
movl 16(%rsp), %eax
imull 20(%rsp), %eax
addq $4, %r12
cmpl %ebp, %eax
jg .L25
testl %eax, %eax
jle .L26
movq %r14, %r12
movl $0, %ebp
.L27:
movq %r12, %rdx
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %ebp
addq $4, %r12
movl 16(%rsp), %eax
imull 20(%rsp), %eax
cmpl %ebp, %eax
jg .L27
.L26:
movq %rbx, %rdi
call fclose@PLT
movslq 16(%rsp), %rdx
movslq 20(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movslq 16(%rsp), %rdx
movslq 20(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r15, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movslq 16(%rsp), %rdx
movslq 20(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r14, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl 16(%rsp), %ebx
movl 20(%rsp), %ebp
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl 12(%rsp), %eax
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L28:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 76(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 76(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC9(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movslq 16(%rsp), %rdx
movslq 20(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $2, %ecx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movslq 16(%rsp), %rdx
movslq 20(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $2, %ecx
movq 32(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movslq 16(%rsp), %rdx
movslq 20(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $2, %ecx
movq 40(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
leaq .LC10(%rip), %rsi
leaq .LC11(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
movl 16(%rsp), %r8d
movl 20(%rsp), %ecx
leaq .LC12(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 16(%rsp), %eax
imull 20(%rsp), %eax
testl %eax, %eax
jle .L29
movl $0, %ebx
leaq .LC13(%rip), %r12
jmp .L32
.L14:
movq 88(%rsp), %rax
subq %fs:40, %rax
je .L17
call __stack_chk_fail@PLT
.L17:
call __cxa_throw_bad_array_new_length@PLT
.L52:
movq 88(%rsp), %rax
subq %fs:40, %rax
je .L20
call __stack_chk_fail@PLT
.L20:
call __cxa_throw_bad_array_new_length@PLT
.L53:
movq 88(%rsp), %rax
subq %fs:40, %rax
je .L23
call __stack_chk_fail@PLT
.L23:
call __cxa_throw_bad_array_new_length@PLT
.L54:
movl %ebx, %ecx
imull %ebp, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z30__device_stub__Z6kernelPfS_S_iPfS_S_i
jmp .L28
.L55:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
leaq .LC7(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
.L31:
movl 16(%rsp), %eax
imull 20(%rsp), %eax
addq $1, %rbx
cmpl %ebx, %eax
jle .L29
.L32:
subl $1, %eax
cmpl %ebx, %eax
je .L55
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
jmp .L31
.L29:
leaq .LC14(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 16(%rsp), %eax
imull 20(%rsp), %eax
testl %eax, %eax
jle .L33
movl $0, %ebx
leaq .LC13(%rip), %r12
jmp .L36
.L56:
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbx,4), %xmm0
leaq .LC7(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
.L35:
movl 16(%rsp), %eax
imull 20(%rsp), %eax
addq $1, %rbx
cmpl %ebx, %eax
jle .L33
.L36:
subl $1, %eax
cmpl %ebx, %eax
je .L56
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbx,4), %xmm0
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
jmp .L35
.L33:
leaq .LC14(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 16(%rsp), %eax
imull 20(%rsp), %eax
testl %eax, %eax
jle .L37
movl $0, %ebx
leaq .LC13(%rip), %r12
jmp .L40
.L57:
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx,4), %xmm0
leaq .LC7(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
.L39:
movl 16(%rsp), %eax
imull 20(%rsp), %eax
addq $1, %rbx
cmpl %ebx, %eax
jle .L37
.L40:
subl $1, %eax
cmpl %ebx, %eax
je .L57
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx,4), %xmm0
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
jmp .L39
.L37:
movl $4, %esi
movq %r13, %rdi
call _ZdlPvm@PLT
movl $4, %esi
movq %r15, %rdi
call _ZdlPvm@PLT
movl $4, %esi
movq %r14, %rdi
call _ZdlPvm@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L58
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3801:
.size main, .-main
.section .rodata.str1.1
.LC16:
.string "_Z6kernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3829:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3829:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC4:
.long 998244352
.align 4
.LC5:
.long 1258291200
.align 4
.LC15:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<iostream>
#include <fstream>
#include <string>
#include <stdio.h>
#include <stdlib.h>
using namespace std;
__global__ void kernel( float* r_gpu, float* g_gpu, float* b_gpu, int N) {
int tId = threadIdx.x + blockIdx.x * blockDim.x;
if(tId < N) {
r_gpu[tId] = 1 - r_gpu[tId];
g_gpu[tId] = 1 - g_gpu[tId];
b_gpu[tId] = 1 - b_gpu[tId];
}
}
void CambiarColores(float* r, float* g, float* b) {
//cout << *r << "|" << 1-*r << endl;
*r = 1 - *r;
*g = 1 - *g;
*b = 1 - *b;
}
int main(int argc, char const *argv[]) {
FILE * pFile;
int n, m;
float* r, *g, *b;
pFile = fopen ("img.txt","r");
fscanf(pFile, "%d %d", &m, &n);
int block_size = 256;
int grid_size = (int) ceil((float) n*m / block_size);
float* r_gpu, *g_gpu, *b_gpu;
cudaMalloc(&r_gpu, sizeof(float) * n * m);
cudaMalloc(&g_gpu, sizeof(float) * n * m);
cudaMalloc(&b_gpu, sizeof(float) * n * m);
r = new float[n*m];
g = new float[n*m];
b = new float[n*m];
for (int i = 0; i < n*m; ++i) {
fscanf (pFile, "%f", &r[i]);
}
for (int i = 0; i < n*m; ++i) {
fscanf (pFile, "%f", &g[i]);
}
for (int i = 0; i < n*m; ++i) {
fscanf (pFile, "%f", &b[i]);
}
fclose (pFile);
cudaMemcpy(r_gpu, r, sizeof(float) * n * m, cudaMemcpyHostToDevice);
cudaMemcpy(g_gpu, g, sizeof(float) * n * m, cudaMemcpyHostToDevice);
cudaMemcpy(b_gpu, b, sizeof(float) * n * m, cudaMemcpyHostToDevice);
int tamanio = n * m;
cudaEvent_t ct1, ct2;
float dt;
cudaEventCreate(&ct1);
cudaEventCreate(&ct2);
cudaEventRecord(ct1);
kernel<<<grid_size, block_size>>>(r_gpu, g_gpu, b_gpu, tamanio);
cudaEventRecord(ct2);
cudaEventSynchronize(ct2);
cudaEventElapsedTime(&dt, ct1, ct2);
cout << "Tiempo GPU: " << dt << " [ms]" << endl;
cudaMemcpy(r, r_gpu, sizeof(float) * n * m, cudaMemcpyDeviceToHost);
cudaMemcpy(g, g_gpu, sizeof(float) * n * m, cudaMemcpyDeviceToHost);
cudaMemcpy(b, b_gpu, sizeof(float) * n * m, cudaMemcpyDeviceToHost);
cudaFree(r_gpu);
cudaFree(g_gpu);
cudaFree(b_gpu);
FILE * pSalida;
pSalida = fopen ("img_salida.txt","w");
fprintf(pSalida, "%d %d\n", m, n);
for (int i = 0; i < n*m; ++i) {
if(i == n*m - 1) {
fprintf(pSalida, "%f", r[i]);
} else {
fprintf(pSalida, "%f ", r[i]);
}
}
fprintf(pSalida, "\n");
for (int i = 0; i < n*m; ++i) {
if(i == n*m - 1) {
fprintf(pSalida, "%f", g[i]);
} else {
fprintf(pSalida, "%f ", g[i]);
}
}
fprintf(pSalida, "\n");
for (int i = 0; i < n*m; ++i) {
if(i == n*m - 1) {
fprintf(pSalida, "%f", b[i]);
} else {
fprintf(pSalida, "%f ", b[i]);
}
}
delete r;
delete g;
delete b;
//cin.get();
return 0;
} | #include <hip/hip_runtime.h>
#include<iostream>
#include <fstream>
#include <string>
#include <stdio.h>
#include <stdlib.h>
using namespace std;
__global__ void kernel( float* r_gpu, float* g_gpu, float* b_gpu, int N) {
int tId = threadIdx.x + blockIdx.x * blockDim.x;
if(tId < N) {
r_gpu[tId] = 1 - r_gpu[tId];
g_gpu[tId] = 1 - g_gpu[tId];
b_gpu[tId] = 1 - b_gpu[tId];
}
}
void CambiarColores(float* r, float* g, float* b) {
//cout << *r << "|" << 1-*r << endl;
*r = 1 - *r;
*g = 1 - *g;
*b = 1 - *b;
}
int main(int argc, char const *argv[]) {
FILE * pFile;
int n, m;
float* r, *g, *b;
pFile = fopen ("img.txt","r");
fscanf(pFile, "%d %d", &m, &n);
int block_size = 256;
int grid_size = (int) ceil((float) n*m / block_size);
float* r_gpu, *g_gpu, *b_gpu;
hipMalloc(&r_gpu, sizeof(float) * n * m);
hipMalloc(&g_gpu, sizeof(float) * n * m);
hipMalloc(&b_gpu, sizeof(float) * n * m);
r = new float[n*m];
g = new float[n*m];
b = new float[n*m];
for (int i = 0; i < n*m; ++i) {
fscanf (pFile, "%f", &r[i]);
}
for (int i = 0; i < n*m; ++i) {
fscanf (pFile, "%f", &g[i]);
}
for (int i = 0; i < n*m; ++i) {
fscanf (pFile, "%f", &b[i]);
}
fclose (pFile);
hipMemcpy(r_gpu, r, sizeof(float) * n * m, hipMemcpyHostToDevice);
hipMemcpy(g_gpu, g, sizeof(float) * n * m, hipMemcpyHostToDevice);
hipMemcpy(b_gpu, b, sizeof(float) * n * m, hipMemcpyHostToDevice);
int tamanio = n * m;
hipEvent_t ct1, ct2;
float dt;
hipEventCreate(&ct1);
hipEventCreate(&ct2);
hipEventRecord(ct1);
kernel<<<grid_size, block_size>>>(r_gpu, g_gpu, b_gpu, tamanio);
hipEventRecord(ct2);
hipEventSynchronize(ct2);
hipEventElapsedTime(&dt, ct1, ct2);
cout << "Tiempo GPU: " << dt << " [ms]" << endl;
hipMemcpy(r, r_gpu, sizeof(float) * n * m, hipMemcpyDeviceToHost);
hipMemcpy(g, g_gpu, sizeof(float) * n * m, hipMemcpyDeviceToHost);
hipMemcpy(b, b_gpu, sizeof(float) * n * m, hipMemcpyDeviceToHost);
hipFree(r_gpu);
hipFree(g_gpu);
hipFree(b_gpu);
FILE * pSalida;
pSalida = fopen ("img_salida.txt","w");
fprintf(pSalida, "%d %d\n", m, n);
for (int i = 0; i < n*m; ++i) {
if(i == n*m - 1) {
fprintf(pSalida, "%f", r[i]);
} else {
fprintf(pSalida, "%f ", r[i]);
}
}
fprintf(pSalida, "\n");
for (int i = 0; i < n*m; ++i) {
if(i == n*m - 1) {
fprintf(pSalida, "%f", g[i]);
} else {
fprintf(pSalida, "%f ", g[i]);
}
}
fprintf(pSalida, "\n");
for (int i = 0; i < n*m; ++i) {
if(i == n*m - 1) {
fprintf(pSalida, "%f", b[i]);
} else {
fprintf(pSalida, "%f ", b[i]);
}
}
delete r;
delete g;
delete b;
//cin.get();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<iostream>
#include <fstream>
#include <string>
#include <stdio.h>
#include <stdlib.h>
using namespace std;
__global__ void kernel( float* r_gpu, float* g_gpu, float* b_gpu, int N) {
int tId = threadIdx.x + blockIdx.x * blockDim.x;
if(tId < N) {
r_gpu[tId] = 1 - r_gpu[tId];
g_gpu[tId] = 1 - g_gpu[tId];
b_gpu[tId] = 1 - b_gpu[tId];
}
}
void CambiarColores(float* r, float* g, float* b) {
//cout << *r << "|" << 1-*r << endl;
*r = 1 - *r;
*g = 1 - *g;
*b = 1 - *b;
}
int main(int argc, char const *argv[]) {
FILE * pFile;
int n, m;
float* r, *g, *b;
pFile = fopen ("img.txt","r");
fscanf(pFile, "%d %d", &m, &n);
int block_size = 256;
int grid_size = (int) ceil((float) n*m / block_size);
float* r_gpu, *g_gpu, *b_gpu;
hipMalloc(&r_gpu, sizeof(float) * n * m);
hipMalloc(&g_gpu, sizeof(float) * n * m);
hipMalloc(&b_gpu, sizeof(float) * n * m);
r = new float[n*m];
g = new float[n*m];
b = new float[n*m];
for (int i = 0; i < n*m; ++i) {
fscanf (pFile, "%f", &r[i]);
}
for (int i = 0; i < n*m; ++i) {
fscanf (pFile, "%f", &g[i]);
}
for (int i = 0; i < n*m; ++i) {
fscanf (pFile, "%f", &b[i]);
}
fclose (pFile);
hipMemcpy(r_gpu, r, sizeof(float) * n * m, hipMemcpyHostToDevice);
hipMemcpy(g_gpu, g, sizeof(float) * n * m, hipMemcpyHostToDevice);
hipMemcpy(b_gpu, b, sizeof(float) * n * m, hipMemcpyHostToDevice);
int tamanio = n * m;
hipEvent_t ct1, ct2;
float dt;
hipEventCreate(&ct1);
hipEventCreate(&ct2);
hipEventRecord(ct1);
kernel<<<grid_size, block_size>>>(r_gpu, g_gpu, b_gpu, tamanio);
hipEventRecord(ct2);
hipEventSynchronize(ct2);
hipEventElapsedTime(&dt, ct1, ct2);
cout << "Tiempo GPU: " << dt << " [ms]" << endl;
hipMemcpy(r, r_gpu, sizeof(float) * n * m, hipMemcpyDeviceToHost);
hipMemcpy(g, g_gpu, sizeof(float) * n * m, hipMemcpyDeviceToHost);
hipMemcpy(b, b_gpu, sizeof(float) * n * m, hipMemcpyDeviceToHost);
hipFree(r_gpu);
hipFree(g_gpu);
hipFree(b_gpu);
FILE * pSalida;
pSalida = fopen ("img_salida.txt","w");
fprintf(pSalida, "%d %d\n", m, n);
for (int i = 0; i < n*m; ++i) {
if(i == n*m - 1) {
fprintf(pSalida, "%f", r[i]);
} else {
fprintf(pSalida, "%f ", r[i]);
}
}
fprintf(pSalida, "\n");
for (int i = 0; i < n*m; ++i) {
if(i == n*m - 1) {
fprintf(pSalida, "%f", g[i]);
} else {
fprintf(pSalida, "%f ", g[i]);
}
}
fprintf(pSalida, "\n");
for (int i = 0; i < n*m; ++i) {
if(i == n*m - 1) {
fprintf(pSalida, "%f", b[i]);
} else {
fprintf(pSalida, "%f ", b[i]);
}
}
delete r;
delete g;
delete b;
//cin.get();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPfS_S_i
.globl _Z6kernelPfS_S_i
.p2align 8
.type _Z6kernelPfS_S_i,@function
_Z6kernelPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v6, 1.0, v4
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
global_store_b32 v[2:3], v6, off
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, 1.0, v2
global_store_b32 v[4:5], v2, off
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, 1.0, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPfS_S_i, .Lfunc_end0-_Z6kernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<iostream>
#include <fstream>
#include <string>
#include <stdio.h>
#include <stdlib.h>
using namespace std;
__global__ void kernel( float* r_gpu, float* g_gpu, float* b_gpu, int N) {
int tId = threadIdx.x + blockIdx.x * blockDim.x;
if(tId < N) {
r_gpu[tId] = 1 - r_gpu[tId];
g_gpu[tId] = 1 - g_gpu[tId];
b_gpu[tId] = 1 - b_gpu[tId];
}
}
void CambiarColores(float* r, float* g, float* b) {
//cout << *r << "|" << 1-*r << endl;
*r = 1 - *r;
*g = 1 - *g;
*b = 1 - *b;
}
int main(int argc, char const *argv[]) {
FILE * pFile;
int n, m;
float* r, *g, *b;
pFile = fopen ("img.txt","r");
fscanf(pFile, "%d %d", &m, &n);
int block_size = 256;
int grid_size = (int) ceil((float) n*m / block_size);
float* r_gpu, *g_gpu, *b_gpu;
hipMalloc(&r_gpu, sizeof(float) * n * m);
hipMalloc(&g_gpu, sizeof(float) * n * m);
hipMalloc(&b_gpu, sizeof(float) * n * m);
r = new float[n*m];
g = new float[n*m];
b = new float[n*m];
for (int i = 0; i < n*m; ++i) {
fscanf (pFile, "%f", &r[i]);
}
for (int i = 0; i < n*m; ++i) {
fscanf (pFile, "%f", &g[i]);
}
for (int i = 0; i < n*m; ++i) {
fscanf (pFile, "%f", &b[i]);
}
fclose (pFile);
hipMemcpy(r_gpu, r, sizeof(float) * n * m, hipMemcpyHostToDevice);
hipMemcpy(g_gpu, g, sizeof(float) * n * m, hipMemcpyHostToDevice);
hipMemcpy(b_gpu, b, sizeof(float) * n * m, hipMemcpyHostToDevice);
int tamanio = n * m;
hipEvent_t ct1, ct2;
float dt;
hipEventCreate(&ct1);
hipEventCreate(&ct2);
hipEventRecord(ct1);
kernel<<<grid_size, block_size>>>(r_gpu, g_gpu, b_gpu, tamanio);
hipEventRecord(ct2);
hipEventSynchronize(ct2);
hipEventElapsedTime(&dt, ct1, ct2);
cout << "Tiempo GPU: " << dt << " [ms]" << endl;
hipMemcpy(r, r_gpu, sizeof(float) * n * m, hipMemcpyDeviceToHost);
hipMemcpy(g, g_gpu, sizeof(float) * n * m, hipMemcpyDeviceToHost);
hipMemcpy(b, b_gpu, sizeof(float) * n * m, hipMemcpyDeviceToHost);
hipFree(r_gpu);
hipFree(g_gpu);
hipFree(b_gpu);
FILE * pSalida;
pSalida = fopen ("img_salida.txt","w");
fprintf(pSalida, "%d %d\n", m, n);
for (int i = 0; i < n*m; ++i) {
if(i == n*m - 1) {
fprintf(pSalida, "%f", r[i]);
} else {
fprintf(pSalida, "%f ", r[i]);
}
}
fprintf(pSalida, "\n");
for (int i = 0; i < n*m; ++i) {
if(i == n*m - 1) {
fprintf(pSalida, "%f", g[i]);
} else {
fprintf(pSalida, "%f ", g[i]);
}
}
fprintf(pSalida, "\n");
for (int i = 0; i < n*m; ++i) {
if(i == n*m - 1) {
fprintf(pSalida, "%f", b[i]);
} else {
fprintf(pSalida, "%f ", b[i]);
}
}
delete r;
delete g;
delete b;
//cin.get();
return 0;
} | .text
.file "invertir_colores_gpu.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__kernelPfS_S_i # -- Begin function _Z21__device_stub__kernelPfS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__kernelPfS_S_i,@function
_Z21__device_stub__kernelPfS_S_i: # @_Z21__device_stub__kernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPfS_S_i, .Lfunc_end0-_Z21__device_stub__kernelPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z14CambiarColoresPfS_S_
.LCPI1_0:
.long 0x3f800000 # float 1
.text
.globl _Z14CambiarColoresPfS_S_
.p2align 4, 0x90
.type _Z14CambiarColoresPfS_S_,@function
_Z14CambiarColoresPfS_S_: # @_Z14CambiarColoresPfS_S_
.cfi_startproc
# %bb.0:
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps %xmm0, %xmm1
subss (%rdi), %xmm1
movss %xmm1, (%rdi)
movaps %xmm0, %xmm1
subss (%rsi), %xmm1
movss %xmm1, (%rsi)
subss (%rdx), %xmm0
movss %xmm0, (%rdx)
retq
.Lfunc_end1:
.size _Z14CambiarColoresPfS_S_, .Lfunc_end1-_Z14CambiarColoresPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x3b800000 # float 0.00390625
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r12
leaq 12(%rsp), %rdx
leaq 16(%rsp), %rcx
movl $.L.str.2, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movslq 16(%rsp), %rbx
cvtsi2ss %ebx, %xmm1
movslq 12(%rsp), %r14
cvtsi2ss %r14d, %xmm0
mulss %xmm1, %xmm0
mulss .LCPI2_0(%rip), %xmm0
callq ceilf@PLT
movss %xmm0, 20(%rsp) # 4-byte Spill
imulq %r14, %rbx
shlq $2, %rbx
leaq 40(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movslq 16(%rsp), %rax
movslq 12(%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 32(%rsp), %rdi
callq hipMalloc
movslq 16(%rsp), %rax
movslq 12(%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movslq 16(%rsp), %rax
movslq 12(%rsp), %rcx
imulq %rax, %rcx
movq %rcx, %rax
shlq $2, %rax
testl %ecx, %ecx
movq $-1, %r15
cmovnsq %rax, %r15
movq %r15, %rdi
callq _Znam
movq %rax, %rbx
movq %r15, %rdi
callq _Znam
movq %rax, %r14
movq %r15, %rdi
callq _Znam
movq %rax, %r15
movl 12(%rsp), %eax
imull 16(%rsp), %eax
testl %eax, %eax
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
movq %rbx, %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %esi
movq %r12, %rdi
movq %r13, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
incq %rbp
movslq 16(%rsp), %rax
movslq 12(%rsp), %rcx
imulq %rax, %rcx
addq $4, %r13
cmpq %rcx, %rbp
jl .LBB2_2
.LBB2_3: # %.preheader73
movl 12(%rsp), %eax
imull 16(%rsp), %eax
testl %eax, %eax
jle .LBB2_6
# %bb.4: # %.lr.ph76.preheader
movq %r14, %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_5: # %.lr.ph76
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %esi
movq %r12, %rdi
movq %r13, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
incq %rbp
movslq 16(%rsp), %rax
movslq 12(%rsp), %rcx
imulq %rax, %rcx
addq $4, %r13
cmpq %rcx, %rbp
jl .LBB2_5
.LBB2_6: # %.preheader
cvttss2si 20(%rsp), %eax # 4-byte Folded Reload
movl %eax, 20(%rsp) # 4-byte Spill
movl 12(%rsp), %eax
imull 16(%rsp), %eax
testl %eax, %eax
jle .LBB2_9
# %bb.7: # %.lr.ph78.preheader
movq %r15, %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_8: # %.lr.ph78
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %esi
movq %r12, %rdi
movq %r13, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
incq %rbp
movslq 16(%rsp), %rax
movslq 12(%rsp), %rcx
imulq %rax, %rcx
addq $4, %r13
cmpq %rcx, %rbp
jl .LBB2_8
.LBB2_9: # %._crit_edge
movq %r12, %rdi
callq fclose
movq 40(%rsp), %rdi
movslq 16(%rsp), %rax
movslq 12(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movslq 16(%rsp), %rax
movslq 12(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movslq 16(%rsp), %rax
movslq 12(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movl 16(%rsp), %r13d
movl 12(%rsp), %r12d
leaq 64(%rsp), %rdi
callq hipEventCreate
leaq 48(%rsp), %rdi
callq hipEventCreate
movq 64(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl 20(%rsp), %edi # 4-byte Reload
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_11
# %bb.10:
imull %r13d, %r12d
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl %r12d, 60(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 60(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z6kernelPfS_S_i, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_11:
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 48(%rsp), %rdi
callq hipEventSynchronize
movq 64(%rsp), %rsi
movq 48(%rsp), %rdx
leaq 144(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 144(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
movl $.L.str.5, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB2_31
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r13)
je .LBB2_14
# %bb.13:
movzbl 67(%r13), %eax
jmp .LBB2_15
.LBB2_14:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 40(%rsp), %rsi
movslq 16(%rsp), %rax
movslq 12(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rsi
movslq 16(%rsp), %rax
movslq 12(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rsi
movslq 16(%rsp), %rax
movslq 12(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movl $.L.str.6, %edi
movl $.L.str.7, %esi
callq fopen
movq %rax, %r12
movl 12(%rsp), %edx
movl 16(%rsp), %ecx
movl $.L.str.8, %esi
movq %rax, %rdi
xorl %eax, %eax
callq fprintf
movl 12(%rsp), %eax
imull 16(%rsp), %eax
testl %eax, %eax
jle .LBB2_20
# %bb.16: # %.lr.ph80.preheader
xorl %r13d, %r13d
jmp .LBB2_17
.p2align 4, 0x90
.LBB2_19: # %.lr.ph80
# in Loop: Header=BB2_17 Depth=1
movss (%rbx,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r12, %rdi
movb $1, %al
callq fprintf
incq %r13
movslq 16(%rsp), %rcx
movslq 12(%rsp), %rax
imulq %rcx, %rax
cmpq %rax, %r13
jge .LBB2_20
.LBB2_17: # %.lr.ph80
# =>This Inner Loop Header: Depth=1
decl %eax
movl $.L.str.3, %esi
cmpq %rax, %r13
je .LBB2_19
# %bb.18: # %.lr.ph80
# in Loop: Header=BB2_17 Depth=1
movl $.L.str.9, %esi
jmp .LBB2_19
.LBB2_20: # %._crit_edge81
movl $10, %edi
movq %r12, %rsi
callq fputc@PLT
movl 12(%rsp), %eax
imull 16(%rsp), %eax
testl %eax, %eax
jle .LBB2_25
# %bb.21: # %.lr.ph84.preheader
xorl %r13d, %r13d
jmp .LBB2_22
.p2align 4, 0x90
.LBB2_24: # %.lr.ph84
# in Loop: Header=BB2_22 Depth=1
movss (%r14,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r12, %rdi
movb $1, %al
callq fprintf
incq %r13
movslq 16(%rsp), %rcx
movslq 12(%rsp), %rax
imulq %rcx, %rax
cmpq %rax, %r13
jge .LBB2_25
.LBB2_22: # %.lr.ph84
# =>This Inner Loop Header: Depth=1
decl %eax
movl $.L.str.3, %esi
cmpq %rax, %r13
je .LBB2_24
# %bb.23: # %.lr.ph84
# in Loop: Header=BB2_22 Depth=1
movl $.L.str.9, %esi
jmp .LBB2_24
.LBB2_25: # %._crit_edge85
movl $10, %edi
movq %r12, %rsi
callq fputc@PLT
movl 12(%rsp), %eax
imull 16(%rsp), %eax
testl %eax, %eax
jle .LBB2_30
# %bb.26: # %.lr.ph88.preheader
xorl %r13d, %r13d
jmp .LBB2_27
.p2align 4, 0x90
.LBB2_29: # %.lr.ph88
# in Loop: Header=BB2_27 Depth=1
movss (%r15,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r12, %rdi
movb $1, %al
callq fprintf
incq %r13
movslq 16(%rsp), %rcx
movslq 12(%rsp), %rax
imulq %rcx, %rax
cmpq %rax, %r13
jge .LBB2_30
.LBB2_27: # %.lr.ph88
# =>This Inner Loop Header: Depth=1
decl %eax
movl $.L.str.3, %esi
cmpq %rax, %r13
je .LBB2_29
# %bb.28: # %.lr.ph88
# in Loop: Header=BB2_27 Depth=1
movl $.L.str.9, %esi
jmp .LBB2_29
.LBB2_30: # %._crit_edge89
movq %rbx, %rdi
callq _ZdlPv
movq %r14, %rdi
callq _ZdlPv
movq %r15, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_31:
.cfi_def_cfa_offset 240
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPfS_S_i,@object # @_Z6kernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z6kernelPfS_S_i
.p2align 3, 0x0
_Z6kernelPfS_S_i:
.quad _Z21__device_stub__kernelPfS_S_i
.size _Z6kernelPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "img.txt"
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d %d"
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%f"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Tiempo GPU: "
.size .L.str.4, 13
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " [ms]"
.size .L.str.5, 6
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "img_salida.txt"
.size .L.str.6, 15
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "w"
.size .L.str.7, 2
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%d %d\n"
.size .L.str.8, 7
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%f "
.size .L.str.9, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPfS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPfS_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fca00078e0207 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*00b0*/ FADD R9, -R0, 1 ; /* 0x3f80000000097421 */
/* 0x004fca0000000100 */
/*00c0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*00d0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00f0*/ FADD R11, -R0, 1 ; /* 0x3f800000000b7421 */
/* 0x004fca0000000100 */
/*0100*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x000fe8000c101904 */
/*0110*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000ea4000c1e1900 */
/*0120*/ FADD R13, -R0, 1 ; /* 0x3f800000000d7421 */
/* 0x004fca0000000100 */
/*0130*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPfS_S_i
.globl _Z6kernelPfS_S_i
.p2align 8
.type _Z6kernelPfS_S_i,@function
_Z6kernelPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v6, 1.0, v4
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
global_store_b32 v[2:3], v6, off
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, 1.0, v2
global_store_b32 v[4:5], v2, off
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, 1.0, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPfS_S_i, .Lfunc_end0-_Z6kernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00056b83_00000000-6_invertir_colores_gpu.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3804:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3804:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14CambiarColoresPfS_S_
.type _Z14CambiarColoresPfS_S_, @function
_Z14CambiarColoresPfS_S_:
.LFB3800:
.cfi_startproc
endbr64
movss .LC0(%rip), %xmm0
movaps %xmm0, %xmm1
subss (%rdi), %xmm1
movss %xmm1, (%rdi)
movaps %xmm0, %xmm1
subss (%rsi), %xmm1
movss %xmm1, (%rsi)
subss (%rdx), %xmm0
movss %xmm0, (%rdx)
ret
.cfi_endproc
.LFE3800:
.size _Z14CambiarColoresPfS_S_, .-_Z14CambiarColoresPfS_S_
.globl _Z30__device_stub__Z6kernelPfS_S_iPfS_S_i
.type _Z30__device_stub__Z6kernelPfS_S_iPfS_S_i, @function
_Z30__device_stub__Z6kernelPfS_S_iPfS_S_i:
.LFB3826:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L8
.L4:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L4
.L9:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3826:
.size _Z30__device_stub__Z6kernelPfS_S_iPfS_S_i, .-_Z30__device_stub__Z6kernelPfS_S_iPfS_S_i
.globl _Z6kernelPfS_S_i
.type _Z6kernelPfS_S_i, @function
_Z6kernelPfS_S_i:
.LFB3827:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6kernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3827:
.size _Z6kernelPfS_S_i, .-_Z6kernelPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "r"
.LC2:
.string "img.txt"
.LC3:
.string "%d %d"
.LC7:
.string "%f"
.LC8:
.string "Tiempo GPU: "
.LC9:
.string " [ms]"
.LC10:
.string "w"
.LC11:
.string "img_salida.txt"
.LC12:
.string "%d %d\n"
.LC13:
.string "%f "
.LC14:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3801:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq .LC1(%rip), %rsi
leaq .LC2(%rip), %rdi
call fopen@PLT
movq %rax, %rbx
leaq 16(%rsp), %rcx
leaq 20(%rsp), %rdx
leaq .LC3(%rip), %rsi
movq %rax, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 16(%rsp), %eax
movl 20(%rsp), %edx
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %edx, %xmm1
mulss %xmm1, %xmm0
mulss .LC4(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC15(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC5(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L13
cvttss2sil %xmm0, %ecx
pxor %xmm1, %xmm1
cvtsi2ssl %ecx, %xmm1
cmpnless %xmm1, %xmm3
movss .LC0(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L13:
cvttss2sil %xmm3, %ecx
movl %ecx, 12(%rsp)
movslq %eax, %rsi
movslq %edx, %rdx
movq %rsi, %rax
imulq %rdx, %rax
leaq 0(,%rax,4), %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movslq 16(%rsp), %rsi
movslq 20(%rsp), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
movslq 16(%rsp), %rsi
movslq 20(%rsp), %rax
imulq %rax, %rsi
salq $2, %rsi
leaq 40(%rsp), %rdi
call cudaMalloc@PLT
movl 16(%rsp), %edi
imull 20(%rsp), %edi
movslq %edi, %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L14
salq $2, %rdi
call _Znam@PLT
movq %rax, %r13
movl 16(%rsp), %edi
imull 20(%rsp), %edi
movslq %edi, %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L52
salq $2, %rdi
call _Znam@PLT
movq %rax, %r15
movl 16(%rsp), %edi
imull 20(%rsp), %edi
movslq %edi, %rdi
movabsq $2305843009213693950, %rax
cmpq %rdi, %rax
jb .L53
salq $2, %rdi
call _Znam@PLT
movq %rax, %r14
movl 16(%rsp), %eax
imull 20(%rsp), %eax
movq %r13, %r12
movl $0, %ebp
testl %eax, %eax
jle .L26
.L24:
movq %r12, %rdx
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %ebp
movl 16(%rsp), %eax
imull 20(%rsp), %eax
addq $4, %r12
cmpl %ebp, %eax
jg .L24
testl %eax, %eax
jle .L26
movq %r15, %r12
movl $0, %ebp
.L25:
movq %r12, %rdx
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %ebp
movl 16(%rsp), %eax
imull 20(%rsp), %eax
addq $4, %r12
cmpl %ebp, %eax
jg .L25
testl %eax, %eax
jle .L26
movq %r14, %r12
movl $0, %ebp
.L27:
movq %r12, %rdx
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %ebp
addq $4, %r12
movl 16(%rsp), %eax
imull 20(%rsp), %eax
cmpl %ebp, %eax
jg .L27
.L26:
movq %rbx, %rdi
call fclose@PLT
movslq 16(%rsp), %rdx
movslq 20(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movslq 16(%rsp), %rdx
movslq 20(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r15, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movslq 16(%rsp), %rdx
movslq 20(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r14, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl 16(%rsp), %ebx
movl 20(%rsp), %ebp
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl 12(%rsp), %eax
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L28:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 76(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 76(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC9(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movslq 16(%rsp), %rdx
movslq 20(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $2, %ecx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movslq 16(%rsp), %rdx
movslq 20(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $2, %ecx
movq 32(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movslq 16(%rsp), %rdx
movslq 20(%rsp), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $2, %ecx
movq 40(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
leaq .LC10(%rip), %rsi
leaq .LC11(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
movl 16(%rsp), %r8d
movl 20(%rsp), %ecx
leaq .LC12(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 16(%rsp), %eax
imull 20(%rsp), %eax
testl %eax, %eax
jle .L29
movl $0, %ebx
leaq .LC13(%rip), %r12
jmp .L32
.L14:
movq 88(%rsp), %rax
subq %fs:40, %rax
je .L17
call __stack_chk_fail@PLT
.L17:
call __cxa_throw_bad_array_new_length@PLT
.L52:
movq 88(%rsp), %rax
subq %fs:40, %rax
je .L20
call __stack_chk_fail@PLT
.L20:
call __cxa_throw_bad_array_new_length@PLT
.L53:
movq 88(%rsp), %rax
subq %fs:40, %rax
je .L23
call __stack_chk_fail@PLT
.L23:
call __cxa_throw_bad_array_new_length@PLT
.L54:
movl %ebx, %ecx
imull %ebp, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z30__device_stub__Z6kernelPfS_S_iPfS_S_i
jmp .L28
.L55:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
leaq .LC7(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
.L31:
movl 16(%rsp), %eax
imull 20(%rsp), %eax
addq $1, %rbx
cmpl %ebx, %eax
jle .L29
.L32:
subl $1, %eax
cmpl %ebx, %eax
je .L55
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
jmp .L31
.L29:
leaq .LC14(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 16(%rsp), %eax
imull 20(%rsp), %eax
testl %eax, %eax
jle .L33
movl $0, %ebx
leaq .LC13(%rip), %r12
jmp .L36
.L56:
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbx,4), %xmm0
leaq .LC7(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
.L35:
movl 16(%rsp), %eax
imull 20(%rsp), %eax
addq $1, %rbx
cmpl %ebx, %eax
jle .L33
.L36:
subl $1, %eax
cmpl %ebx, %eax
je .L56
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbx,4), %xmm0
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
jmp .L35
.L33:
leaq .LC14(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 16(%rsp), %eax
imull 20(%rsp), %eax
testl %eax, %eax
jle .L37
movl $0, %ebx
leaq .LC13(%rip), %r12
jmp .L40
.L57:
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx,4), %xmm0
leaq .LC7(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
.L39:
movl 16(%rsp), %eax
imull 20(%rsp), %eax
addq $1, %rbx
cmpl %ebx, %eax
jle .L37
.L40:
subl $1, %eax
cmpl %ebx, %eax
je .L57
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx,4), %xmm0
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
jmp .L39
.L37:
movl $4, %esi
movq %r13, %rdi
call _ZdlPvm@PLT
movl $4, %esi
movq %r15, %rdi
call _ZdlPvm@PLT
movl $4, %esi
movq %r14, %rdi
call _ZdlPvm@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L58
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3801:
.size main, .-main
.section .rodata.str1.1
.LC16:
.string "_Z6kernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3829:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3829:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC4:
.long 998244352
.align 4
.LC5:
.long 1258291200
.align 4
.LC15:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "invertir_colores_gpu.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__kernelPfS_S_i # -- Begin function _Z21__device_stub__kernelPfS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__kernelPfS_S_i,@function
_Z21__device_stub__kernelPfS_S_i: # @_Z21__device_stub__kernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPfS_S_i, .Lfunc_end0-_Z21__device_stub__kernelPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z14CambiarColoresPfS_S_
.LCPI1_0:
.long 0x3f800000 # float 1
.text
.globl _Z14CambiarColoresPfS_S_
.p2align 4, 0x90
.type _Z14CambiarColoresPfS_S_,@function
_Z14CambiarColoresPfS_S_: # @_Z14CambiarColoresPfS_S_
.cfi_startproc
# %bb.0:
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps %xmm0, %xmm1
subss (%rdi), %xmm1
movss %xmm1, (%rdi)
movaps %xmm0, %xmm1
subss (%rsi), %xmm1
movss %xmm1, (%rsi)
subss (%rdx), %xmm0
movss %xmm0, (%rdx)
retq
.Lfunc_end1:
.size _Z14CambiarColoresPfS_S_, .Lfunc_end1-_Z14CambiarColoresPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x3b800000 # float 0.00390625
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r12
leaq 12(%rsp), %rdx
leaq 16(%rsp), %rcx
movl $.L.str.2, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movslq 16(%rsp), %rbx
cvtsi2ss %ebx, %xmm1
movslq 12(%rsp), %r14
cvtsi2ss %r14d, %xmm0
mulss %xmm1, %xmm0
mulss .LCPI2_0(%rip), %xmm0
callq ceilf@PLT
movss %xmm0, 20(%rsp) # 4-byte Spill
imulq %r14, %rbx
shlq $2, %rbx
leaq 40(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movslq 16(%rsp), %rax
movslq 12(%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 32(%rsp), %rdi
callq hipMalloc
movslq 16(%rsp), %rax
movslq 12(%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movslq 16(%rsp), %rax
movslq 12(%rsp), %rcx
imulq %rax, %rcx
movq %rcx, %rax
shlq $2, %rax
testl %ecx, %ecx
movq $-1, %r15
cmovnsq %rax, %r15
movq %r15, %rdi
callq _Znam
movq %rax, %rbx
movq %r15, %rdi
callq _Znam
movq %rax, %r14
movq %r15, %rdi
callq _Znam
movq %rax, %r15
movl 12(%rsp), %eax
imull 16(%rsp), %eax
testl %eax, %eax
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
movq %rbx, %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %esi
movq %r12, %rdi
movq %r13, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
incq %rbp
movslq 16(%rsp), %rax
movslq 12(%rsp), %rcx
imulq %rax, %rcx
addq $4, %r13
cmpq %rcx, %rbp
jl .LBB2_2
.LBB2_3: # %.preheader73
movl 12(%rsp), %eax
imull 16(%rsp), %eax
testl %eax, %eax
jle .LBB2_6
# %bb.4: # %.lr.ph76.preheader
movq %r14, %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_5: # %.lr.ph76
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %esi
movq %r12, %rdi
movq %r13, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
incq %rbp
movslq 16(%rsp), %rax
movslq 12(%rsp), %rcx
imulq %rax, %rcx
addq $4, %r13
cmpq %rcx, %rbp
jl .LBB2_5
.LBB2_6: # %.preheader
cvttss2si 20(%rsp), %eax # 4-byte Folded Reload
movl %eax, 20(%rsp) # 4-byte Spill
movl 12(%rsp), %eax
imull 16(%rsp), %eax
testl %eax, %eax
jle .LBB2_9
# %bb.7: # %.lr.ph78.preheader
movq %r15, %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_8: # %.lr.ph78
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %esi
movq %r12, %rdi
movq %r13, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
incq %rbp
movslq 16(%rsp), %rax
movslq 12(%rsp), %rcx
imulq %rax, %rcx
addq $4, %r13
cmpq %rcx, %rbp
jl .LBB2_8
.LBB2_9: # %._crit_edge
movq %r12, %rdi
callq fclose
movq 40(%rsp), %rdi
movslq 16(%rsp), %rax
movslq 12(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movslq 16(%rsp), %rax
movslq 12(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movslq 16(%rsp), %rax
movslq 12(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movl 16(%rsp), %r13d
movl 12(%rsp), %r12d
leaq 64(%rsp), %rdi
callq hipEventCreate
leaq 48(%rsp), %rdi
callq hipEventCreate
movq 64(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl 20(%rsp), %edi # 4-byte Reload
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_11
# %bb.10:
imull %r13d, %r12d
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl %r12d, 60(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 60(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z6kernelPfS_S_i, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_11:
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 48(%rsp), %rdi
callq hipEventSynchronize
movq 64(%rsp), %rsi
movq 48(%rsp), %rdx
leaq 144(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 144(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
movl $.L.str.5, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB2_31
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r13)
je .LBB2_14
# %bb.13:
movzbl 67(%r13), %eax
jmp .LBB2_15
.LBB2_14:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 40(%rsp), %rsi
movslq 16(%rsp), %rax
movslq 12(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rsi
movslq 16(%rsp), %rax
movslq 12(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rsi
movslq 16(%rsp), %rax
movslq 12(%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movl $.L.str.6, %edi
movl $.L.str.7, %esi
callq fopen
movq %rax, %r12
movl 12(%rsp), %edx
movl 16(%rsp), %ecx
movl $.L.str.8, %esi
movq %rax, %rdi
xorl %eax, %eax
callq fprintf
movl 12(%rsp), %eax
imull 16(%rsp), %eax
testl %eax, %eax
jle .LBB2_20
# %bb.16: # %.lr.ph80.preheader
xorl %r13d, %r13d
jmp .LBB2_17
.p2align 4, 0x90
.LBB2_19: # %.lr.ph80
# in Loop: Header=BB2_17 Depth=1
movss (%rbx,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r12, %rdi
movb $1, %al
callq fprintf
incq %r13
movslq 16(%rsp), %rcx
movslq 12(%rsp), %rax
imulq %rcx, %rax
cmpq %rax, %r13
jge .LBB2_20
.LBB2_17: # %.lr.ph80
# =>This Inner Loop Header: Depth=1
decl %eax
movl $.L.str.3, %esi
cmpq %rax, %r13
je .LBB2_19
# %bb.18: # %.lr.ph80
# in Loop: Header=BB2_17 Depth=1
movl $.L.str.9, %esi
jmp .LBB2_19
.LBB2_20: # %._crit_edge81
movl $10, %edi
movq %r12, %rsi
callq fputc@PLT
movl 12(%rsp), %eax
imull 16(%rsp), %eax
testl %eax, %eax
jle .LBB2_25
# %bb.21: # %.lr.ph84.preheader
xorl %r13d, %r13d
jmp .LBB2_22
.p2align 4, 0x90
.LBB2_24: # %.lr.ph84
# in Loop: Header=BB2_22 Depth=1
movss (%r14,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r12, %rdi
movb $1, %al
callq fprintf
incq %r13
movslq 16(%rsp), %rcx
movslq 12(%rsp), %rax
imulq %rcx, %rax
cmpq %rax, %r13
jge .LBB2_25
.LBB2_22: # %.lr.ph84
# =>This Inner Loop Header: Depth=1
decl %eax
movl $.L.str.3, %esi
cmpq %rax, %r13
je .LBB2_24
# %bb.23: # %.lr.ph84
# in Loop: Header=BB2_22 Depth=1
movl $.L.str.9, %esi
jmp .LBB2_24
.LBB2_25: # %._crit_edge85
movl $10, %edi
movq %r12, %rsi
callq fputc@PLT
movl 12(%rsp), %eax
imull 16(%rsp), %eax
testl %eax, %eax
jle .LBB2_30
# %bb.26: # %.lr.ph88.preheader
xorl %r13d, %r13d
jmp .LBB2_27
.p2align 4, 0x90
.LBB2_29: # %.lr.ph88
# in Loop: Header=BB2_27 Depth=1
movss (%r15,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r12, %rdi
movb $1, %al
callq fprintf
incq %r13
movslq 16(%rsp), %rcx
movslq 12(%rsp), %rax
imulq %rcx, %rax
cmpq %rax, %r13
jge .LBB2_30
.LBB2_27: # %.lr.ph88
# =>This Inner Loop Header: Depth=1
decl %eax
movl $.L.str.3, %esi
cmpq %rax, %r13
je .LBB2_29
# %bb.28: # %.lr.ph88
# in Loop: Header=BB2_27 Depth=1
movl $.L.str.9, %esi
jmp .LBB2_29
.LBB2_30: # %._crit_edge89
movq %rbx, %rdi
callq _ZdlPv
movq %r14, %rdi
callq _ZdlPv
movq %r15, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_31:
.cfi_def_cfa_offset 240
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPfS_S_i,@object # @_Z6kernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z6kernelPfS_S_i
.p2align 3, 0x0
_Z6kernelPfS_S_i:
.quad _Z21__device_stub__kernelPfS_S_i
.size _Z6kernelPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "img.txt"
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d %d"
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%f"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Tiempo GPU: "
.size .L.str.4, 13
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " [ms]"
.size .L.str.5, 6
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "img_salida.txt"
.size .L.str.6, 15
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "w"
.size .L.str.7, 2
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%d %d\n"
.size .L.str.8, 7
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%f "
.size .L.str.9, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPfS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPfS_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include<iostream>
#include <stdio.h>
using namespace std;
cudaError_t addWithCuda(int *c, const int *a, const int *b, size_t size);
__global__ void addKernel(int *c, const int *a, const int *b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
int main()
{
const int arraySize = 5;
const int a[arraySize] = { 1, 2, 3, 4, 5 };
const int b[arraySize] = { 10, 20, 30, 40, 50 };
int c[arraySize] = { 0 };
//get device prop
cudaError_t cudaStatus;
int num = 0;
cudaDeviceProp deviceProp;
cudaStatus = cudaGetDeviceCount(&num);
for(int i=0;i<num;i++)
{
cudaGetDeviceProperties(&deviceProp, i);
cout << "设备 " << i + 1 << " 的主要属性： " << endl;
cout << "设备显卡型号： " << deviceProp.name << endl;
printf("maxGridSize:%d,%d,%d\n",deviceProp.maxGridSize[0],deviceProp.maxGridSize[1],deviceProp.maxGridSize[2]);
printf("maxThreadDim:%d,%d,%d\n",deviceProp.maxThreadsDim[0],deviceProp.maxThreadsDim[1],deviceProp.maxThreadsDim[2]);
printf("warpSize:%d\n",deviceProp.warpSize);
printf("constanMemory:%d(K)\n",deviceProp.totalConstMem/1024);
cout << "设备全局内存总量（以MB为单位）： " << deviceProp.totalGlobalMem / 1024 / 1024 << endl;
cout << "设备上一个线程块（Block）中可用的最大共享内存（以KB为单位）： " << deviceProp.sharedMemPerBlock / 1024 << endl;
cout << "设备上一个线程块（Block）种可用的32位寄存器数量： " << deviceProp.regsPerBlock << endl;
cout << "设备上一个线程块（Block）可包含的最大线程数量： " << deviceProp.maxThreadsPerBlock << endl;
cout << "设备的计算功能集（Compute Capability）的版本号： " << deviceProp.major << "." << deviceProp.minor << endl;
cout << "设备上多处理器的数量： " << deviceProp.multiProcessorCount << endl;
}
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
cudaError_t addWithCuda(int *c, const int *a, const int *b, size_t size)
{
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
cudaError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = cudaMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_b, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(dev_b, b, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
// cudaThreadSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = cudaThreadSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaThreadSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error:
cudaFree(dev_c);
cudaFree(dev_a);
cudaFree(dev_b);
return cudaStatus;
} | code for sm_80
Function : _Z9addKernelPiPKiS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include<iostream>
#include <stdio.h>
using namespace std;
cudaError_t addWithCuda(int *c, const int *a, const int *b, size_t size);
__global__ void addKernel(int *c, const int *a, const int *b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
int main()
{
const int arraySize = 5;
const int a[arraySize] = { 1, 2, 3, 4, 5 };
const int b[arraySize] = { 10, 20, 30, 40, 50 };
int c[arraySize] = { 0 };
//get device prop
cudaError_t cudaStatus;
int num = 0;
cudaDeviceProp deviceProp;
cudaStatus = cudaGetDeviceCount(&num);
for(int i=0;i<num;i++)
{
cudaGetDeviceProperties(&deviceProp, i);
cout << "设备 " << i + 1 << " 的主要属性： " << endl;
cout << "设备显卡型号： " << deviceProp.name << endl;
printf("maxGridSize:%d,%d,%d\n",deviceProp.maxGridSize[0],deviceProp.maxGridSize[1],deviceProp.maxGridSize[2]);
printf("maxThreadDim:%d,%d,%d\n",deviceProp.maxThreadsDim[0],deviceProp.maxThreadsDim[1],deviceProp.maxThreadsDim[2]);
printf("warpSize:%d\n",deviceProp.warpSize);
printf("constanMemory:%d(K)\n",deviceProp.totalConstMem/1024);
cout << "设备全局内存总量（以MB为单位）： " << deviceProp.totalGlobalMem / 1024 / 1024 << endl;
cout << "设备上一个线程块（Block）中可用的最大共享内存（以KB为单位）： " << deviceProp.sharedMemPerBlock / 1024 << endl;
cout << "设备上一个线程块（Block）种可用的32位寄存器数量： " << deviceProp.regsPerBlock << endl;
cout << "设备上一个线程块（Block）可包含的最大线程数量： " << deviceProp.maxThreadsPerBlock << endl;
cout << "设备的计算功能集（Compute Capability）的版本号： " << deviceProp.major << "." << deviceProp.minor << endl;
cout << "设备上多处理器的数量： " << deviceProp.multiProcessorCount << endl;
}
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
cudaError_t addWithCuda(int *c, const int *a, const int *b, size_t size)
{
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
cudaError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = cudaMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_b, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(dev_b, b, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
// cudaThreadSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = cudaThreadSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaThreadSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error:
cudaFree(dev_c);
cudaFree(dev_a);
cudaFree(dev_b);
return cudaStatus;
} | .file "tmpxft_000953b2_00000000-6_myDeviceMsg.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\350\256\276\345\244\207 "
.LC1:
.string " \347\232\204\344\270\273\350\246\201\345\261\236\346\200\247\357\274\232 "
.LC2:
.string "\350\256\276\345\244\207\346\230\276\345\215\241\345\236\213\345\217\267\357\274\232 "
.LC3:
.string "maxGridSize:%d,%d,%d\n"
.LC4:
.string "maxThreadDim:%d,%d,%d\n"
.LC5:
.string "warpSize:%d\n"
.LC6:
.string "constanMemory:%d(K)\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "\350\256\276\345\244\207\345\205\250\345\261\200\345\206\205\345\255\230\346\200\273\351\207\217\357\274\210\344\273\245MB\344\270\272\345\215\225\344\275\215\357\274\211\357\274\232 "
.align 8
.LC8:
.string "\350\256\276\345\244\207\344\270\212\344\270\200\344\270\252\347\272\277\347\250\213\345\235\227\357\274\210Block\357\274\211\344\270\255\345\217\257\347\224\250\347\232\204\346\234\200\345\244\247\345\205\261\344\272\253\345\206\205\345\255\230\357\274\210\344\273\245KB\344\270\272\345\215\225\344\275\215\357\274\211\357\274\232 "
.align 8
.LC9:
.string "\350\256\276\345\244\207\344\270\212\344\270\200\344\270\252\347\272\277\347\250\213\345\235\227\357\274\210Block\357\274\211\347\247\215\345\217\257\347\224\250\347\232\20432\344\275\215\345\257\204\345\255\230\345\231\250\346\225\260\351\207\217\357\274\232 "
.align 8
.LC10:
.string "\350\256\276\345\244\207\344\270\212\344\270\200\344\270\252\347\272\277\347\250\213\345\235\227\357\274\210Block\357\274\211\345\217\257\345\214\205\345\220\253\347\232\204\346\234\200\345\244\247\347\272\277\347\250\213\346\225\260\351\207\217\357\274\232 "
.align 8
.LC11:
.string "\350\256\276\345\244\207\347\232\204\350\256\241\347\256\227\345\212\237\350\203\275\351\233\206\357\274\210Compute Capability\357\274\211\347\232\204\347\211\210\346\234\254\345\217\267\357\274\232 "
.section .rodata.str1.1
.LC12:
.string "."
.section .rodata.str1.8
.align 8
.LC13:
.string "\350\256\276\345\244\207\344\270\212\345\244\232\345\244\204\347\220\206\345\231\250\347\232\204\346\225\260\351\207\217\357\274\232 "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
jle .L4
movl $0, %r12d
leaq .LC0(%rip), %r14
leaq _ZSt4cout(%rip), %rbx
leaq .LC1(%rip), %r13
jmp .L37
.L49:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L41
call _ZSt16__throw_bad_castv@PLT
.L41:
call __stack_chk_fail@PLT
.L7:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L8
.L50:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L42
call _ZSt16__throw_bad_castv@PLT
.L42:
call __stack_chk_fail@PLT
.L11:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L12
.L51:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L43
call _ZSt16__throw_bad_castv@PLT
.L43:
call __stack_chk_fail@PLT
.L15:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L16
.L52:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L44
call _ZSt16__throw_bad_castv@PLT
.L44:
call __stack_chk_fail@PLT
.L19:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L20
.L53:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L45
call _ZSt16__throw_bad_castv@PLT
.L45:
call __stack_chk_fail@PLT
.L23:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L24
.L54:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L46
call _ZSt16__throw_bad_castv@PLT
.L46:
call __stack_chk_fail@PLT
.L27:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L28
.L55:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L47
call _ZSt16__throw_bad_castv@PLT
.L47:
call __stack_chk_fail@PLT
.L31:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L32
.L56:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L48
call _ZSt16__throw_bad_castv@PLT
.L48:
call __stack_chk_fail@PLT
.L57:
movzbl 67(%r15), %esi
.L36:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
cmpl 12(%rsp), %r12d
jge .L4
.L37:
leaq 16(%rsp), %rdi
movl %r12d, %esi
call cudaGetDeviceProperties_v2@PLT
movl $7, %edx
movq %r14, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addl $1, %r12d
movl %r12d, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $20, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L49
cmpb $0, 56(%r15)
je .L7
movzbl 67(%r15), %esi
.L8:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $22, %edx
leaq .LC2(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
leaq 16(%rsp), %rbp
movq %rbp, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L50
cmpb $0, 56(%rbp)
je .L11
movzbl 67(%rbp), %esi
.L12:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 324(%rsp), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 368(%rsp), %rdx
shrq $10, %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $48, %edx
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 304(%rsp), %rsi
shrq $20, %rsi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L51
cmpb $0, 56(%r15)
je .L15
movzbl 67(%r15), %esi
.L16:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $89, %edx
leaq .LC8(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 312(%rsp), %rsi
shrq $10, %rsi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L52
cmpb $0, 56(%r15)
je .L19
movzbl 67(%r15), %esi
.L20:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $71, %edx
leaq .LC9(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 320(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L53
cmpb $0, 56(%r15)
je .L23
movzbl 67(%r15), %esi
.L24:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $69, %edx
leaq .LC10(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 336(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L54
cmpb $0, 56(%r15)
je .L27
movzbl 67(%r15), %esi
.L28:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $64, %edx
leaq .LC11(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 376(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $1, %edx
leaq .LC12(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 380(%rsp), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L55
cmpb $0, 56(%r15)
je .L31
movzbl 67(%r15), %esi
.L32:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $34, %edx
leaq .LC13(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 404(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L56
cmpb $0, 56(%r15)
jne .L57
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L36
.L4:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L58
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.globl _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
.type _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_, @function
_Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_:
.LFB3695:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L63
.L59:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L64
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L63:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addKernelPiPKiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L59
.L64:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_, .-_Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
.globl _Z9addKernelPiPKiS1_
.type _Z9addKernelPiPKiS1_, @function
_Z9addKernelPiPKiS1_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z9addKernelPiPKiS1_, .-_Z9addKernelPiPKiS1_
.section .rodata.str1.8
.align 8
.LC14:
.string "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?"
.section .rodata.str1.1
.LC15:
.string "cudaMalloc failed!"
.LC16:
.string "cudaMemcpy failed!"
.section .rodata.str1.8
.align 8
.LC17:
.string "cudaThreadSynchronize returned error code %d after launching addKernel!\n"
.text
.globl _Z11addWithCudaPiPKiS1_m
.type _Z11addWithCudaPiPKiS1_m, @function
_Z11addWithCudaPiPKiS1_m:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r14
movq %rsi, %r12
movq %rdx, %r13
movq %rcx, %rbp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L79
leaq 0(,%rbp,4), %r15
leaq 24(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L80
leaq 8(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L81
leaq 16(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L82
movl $1, %ecx
movq %r15, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L83
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L84
movl %ebp, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L85
.L75:
call cudaThreadSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L86
movl $2, %ecx
movq %r15, %rdx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
je .L69
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L69
.L79:
movl %eax, %ebx
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L69:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L87
movl %ebx, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L80:
.cfi_restore_state
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L69
.L81:
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L69
.L82:
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L69
.L83:
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L69
.L84:
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L69
.L85:
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
jmp .L75
.L86:
movl %eax, %ecx
leaq .LC17(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L69
.L87:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size _Z11addWithCudaPiPKiS1_m, .-_Z11addWithCudaPiPKiS1_m
.section .rodata.str1.1
.LC18:
.string "_Z9addKernelPiPKiS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addKernelPiPKiS1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include<iostream>
#include <stdio.h>
using namespace std;
cudaError_t addWithCuda(int *c, const int *a, const int *b, size_t size);
__global__ void addKernel(int *c, const int *a, const int *b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
int main()
{
const int arraySize = 5;
const int a[arraySize] = { 1, 2, 3, 4, 5 };
const int b[arraySize] = { 10, 20, 30, 40, 50 };
int c[arraySize] = { 0 };
//get device prop
cudaError_t cudaStatus;
int num = 0;
cudaDeviceProp deviceProp;
cudaStatus = cudaGetDeviceCount(&num);
for(int i=0;i<num;i++)
{
cudaGetDeviceProperties(&deviceProp, i);
cout << "设备 " << i + 1 << " 的主要属性： " << endl;
cout << "设备显卡型号： " << deviceProp.name << endl;
printf("maxGridSize:%d,%d,%d\n",deviceProp.maxGridSize[0],deviceProp.maxGridSize[1],deviceProp.maxGridSize[2]);
printf("maxThreadDim:%d,%d,%d\n",deviceProp.maxThreadsDim[0],deviceProp.maxThreadsDim[1],deviceProp.maxThreadsDim[2]);
printf("warpSize:%d\n",deviceProp.warpSize);
printf("constanMemory:%d(K)\n",deviceProp.totalConstMem/1024);
cout << "设备全局内存总量（以MB为单位）： " << deviceProp.totalGlobalMem / 1024 / 1024 << endl;
cout << "设备上一个线程块（Block）中可用的最大共享内存（以KB为单位）： " << deviceProp.sharedMemPerBlock / 1024 << endl;
cout << "设备上一个线程块（Block）种可用的32位寄存器数量： " << deviceProp.regsPerBlock << endl;
cout << "设备上一个线程块（Block）可包含的最大线程数量： " << deviceProp.maxThreadsPerBlock << endl;
cout << "设备的计算功能集（Compute Capability）的版本号： " << deviceProp.major << "." << deviceProp.minor << endl;
cout << "设备上多处理器的数量： " << deviceProp.multiProcessorCount << endl;
}
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
cudaError_t addWithCuda(int *c, const int *a, const int *b, size_t size)
{
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
cudaError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = cudaSetDevice(0);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = cudaMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
cudaStatus = cudaMalloc((void**)&dev_b, size * sizeof(int));
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
cudaStatus = cudaMemcpy(dev_b, b, size * sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
// cudaThreadSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = cudaThreadSynchronize();
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaThreadSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess) {
fprintf(stderr, "cudaMemcpy failed!");
goto Error;
}
Error:
cudaFree(dev_c);
cudaFree(dev_a);
cudaFree(dev_b);
return cudaStatus;
} | #include "hip/hip_runtime.h"
#include<iostream>
#include <stdio.h>
using namespace std;
hipError_t addWithCuda(int *c, const int *a, const int *b, size_t size);
__global__ void addKernel(int *c, const int *a, const int *b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
int main()
{
const int arraySize = 5;
const int a[arraySize] = { 1, 2, 3, 4, 5 };
const int b[arraySize] = { 10, 20, 30, 40, 50 };
int c[arraySize] = { 0 };
//get device prop
hipError_t cudaStatus;
int num = 0;
hipDeviceProp_t deviceProp;
cudaStatus = hipGetDeviceCount(&num);
for(int i=0;i<num;i++)
{
hipGetDeviceProperties(&deviceProp, i);
cout << "设备 " << i + 1 << " 的主要属性： " << endl;
cout << "设备显卡型号： " << deviceProp.name << endl;
printf("maxGridSize:%d,%d,%d\n",deviceProp.maxGridSize[0],deviceProp.maxGridSize[1],deviceProp.maxGridSize[2]);
printf("maxThreadDim:%d,%d,%d\n",deviceProp.maxThreadsDim[0],deviceProp.maxThreadsDim[1],deviceProp.maxThreadsDim[2]);
printf("warpSize:%d\n",deviceProp.warpSize);
printf("constanMemory:%d(K)\n",deviceProp.totalConstMem/1024);
cout << "设备全局内存总量（以MB为单位）： " << deviceProp.totalGlobalMem / 1024 / 1024 << endl;
cout << "设备上一个线程块（Block）中可用的最大共享内存（以KB为单位）： " << deviceProp.sharedMemPerBlock / 1024 << endl;
cout << "设备上一个线程块（Block）种可用的32位寄存器数量： " << deviceProp.regsPerBlock << endl;
cout << "设备上一个线程块（Block）可包含的最大线程数量： " << deviceProp.maxThreadsPerBlock << endl;
cout << "设备的计算功能集（Compute Capability）的版本号： " << deviceProp.major << "." << deviceProp.minor << endl;
cout << "设备上多处理器的数量： " << deviceProp.multiProcessorCount << endl;
}
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
hipError_t addWithCuda(int *c, const int *a, const int *b, size_t size)
{
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
hipError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = hipMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_b, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(dev_a, a, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
cudaStatus = hipMemcpy(dev_b, b, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
// cudaThreadSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = hipMemcpy(c, dev_c, size * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error:
hipFree(dev_c);
hipFree(dev_a);
hipFree(dev_b);
return cudaStatus;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include<iostream>
#include <stdio.h>
using namespace std;
hipError_t addWithCuda(int *c, const int *a, const int *b, size_t size);
__global__ void addKernel(int *c, const int *a, const int *b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
int main()
{
const int arraySize = 5;
const int a[arraySize] = { 1, 2, 3, 4, 5 };
const int b[arraySize] = { 10, 20, 30, 40, 50 };
int c[arraySize] = { 0 };
//get device prop
hipError_t cudaStatus;
int num = 0;
hipDeviceProp_t deviceProp;
cudaStatus = hipGetDeviceCount(&num);
for(int i=0;i<num;i++)
{
hipGetDeviceProperties(&deviceProp, i);
cout << "设备 " << i + 1 << " 的主要属性： " << endl;
cout << "设备显卡型号： " << deviceProp.name << endl;
printf("maxGridSize:%d,%d,%d\n",deviceProp.maxGridSize[0],deviceProp.maxGridSize[1],deviceProp.maxGridSize[2]);
printf("maxThreadDim:%d,%d,%d\n",deviceProp.maxThreadsDim[0],deviceProp.maxThreadsDim[1],deviceProp.maxThreadsDim[2]);
printf("warpSize:%d\n",deviceProp.warpSize);
printf("constanMemory:%d(K)\n",deviceProp.totalConstMem/1024);
cout << "设备全局内存总量（以MB为单位）： " << deviceProp.totalGlobalMem / 1024 / 1024 << endl;
cout << "设备上一个线程块（Block）中可用的最大共享内存（以KB为单位）： " << deviceProp.sharedMemPerBlock / 1024 << endl;
cout << "设备上一个线程块（Block）种可用的32位寄存器数量： " << deviceProp.regsPerBlock << endl;
cout << "设备上一个线程块（Block）可包含的最大线程数量： " << deviceProp.maxThreadsPerBlock << endl;
cout << "设备的计算功能集（Compute Capability）的版本号： " << deviceProp.major << "." << deviceProp.minor << endl;
cout << "设备上多处理器的数量： " << deviceProp.multiProcessorCount << endl;
}
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
hipError_t addWithCuda(int *c, const int *a, const int *b, size_t size)
{
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
hipError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = hipMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_b, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(dev_a, a, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
cudaStatus = hipMemcpy(dev_b, b, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
// cudaThreadSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = hipMemcpy(c, dev_c, size * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error:
hipFree(dev_c);
hipFree(dev_a);
hipFree(dev_b);
return cudaStatus;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addKernelPiPKiS1_
.globl _Z9addKernelPiPKiS1_
.p2align 8
.type _Z9addKernelPiPKiS1_,@function
_Z9addKernelPiPKiS1_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[4:5]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addKernelPiPKiS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addKernelPiPKiS1_, .Lfunc_end0-_Z9addKernelPiPKiS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addKernelPiPKiS1_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z9addKernelPiPKiS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include<iostream>
#include <stdio.h>
using namespace std;
hipError_t addWithCuda(int *c, const int *a, const int *b, size_t size);
__global__ void addKernel(int *c, const int *a, const int *b)
{
int i = threadIdx.x;
c[i] = a[i] + b[i];
}
int main()
{
const int arraySize = 5;
const int a[arraySize] = { 1, 2, 3, 4, 5 };
const int b[arraySize] = { 10, 20, 30, 40, 50 };
int c[arraySize] = { 0 };
//get device prop
hipError_t cudaStatus;
int num = 0;
hipDeviceProp_t deviceProp;
cudaStatus = hipGetDeviceCount(&num);
for(int i=0;i<num;i++)
{
hipGetDeviceProperties(&deviceProp, i);
cout << "设备 " << i + 1 << " 的主要属性： " << endl;
cout << "设备显卡型号： " << deviceProp.name << endl;
printf("maxGridSize:%d,%d,%d\n",deviceProp.maxGridSize[0],deviceProp.maxGridSize[1],deviceProp.maxGridSize[2]);
printf("maxThreadDim:%d,%d,%d\n",deviceProp.maxThreadsDim[0],deviceProp.maxThreadsDim[1],deviceProp.maxThreadsDim[2]);
printf("warpSize:%d\n",deviceProp.warpSize);
printf("constanMemory:%d(K)\n",deviceProp.totalConstMem/1024);
cout << "设备全局内存总量（以MB为单位）： " << deviceProp.totalGlobalMem / 1024 / 1024 << endl;
cout << "设备上一个线程块（Block）中可用的最大共享内存（以KB为单位）： " << deviceProp.sharedMemPerBlock / 1024 << endl;
cout << "设备上一个线程块（Block）种可用的32位寄存器数量： " << deviceProp.regsPerBlock << endl;
cout << "设备上一个线程块（Block）可包含的最大线程数量： " << deviceProp.maxThreadsPerBlock << endl;
cout << "设备的计算功能集（Compute Capability）的版本号： " << deviceProp.major << "." << deviceProp.minor << endl;
cout << "设备上多处理器的数量： " << deviceProp.multiProcessorCount << endl;
}
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
hipError_t addWithCuda(int *c, const int *a, const int *b, size_t size)
{
int *dev_a = 0;
int *dev_b = 0;
int *dev_c = 0;
hipError_t cudaStatus;
// Choose which GPU to run on, change this on a multi-GPU system.
cudaStatus = hipSetDevice(0);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipSetDevice failed! Do you have a CUDA-capable GPU installed?");
goto Error;
}
// Allocate GPU buffers for three vectors (two input, one output) .
cudaStatus = hipMalloc((void**)&dev_c, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_a, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
cudaStatus = hipMalloc((void**)&dev_b, size * sizeof(int));
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMalloc failed!");
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(dev_a, a, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
cudaStatus = hipMemcpy(dev_b, b, size * sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
// Launch a kernel on the GPU with one thread for each element.
addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
// cudaThreadSynchronize waits for the kernel to finish, and returns
// any errors encountered during the launch.
cudaStatus = hipDeviceSynchronize();
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
goto Error;
}
// Copy output vector from GPU buffer to host memory.
cudaStatus = hipMemcpy(c, dev_c, size * sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess) {
fprintf(stderr, "hipMemcpy failed!");
goto Error;
}
Error:
hipFree(dev_c);
hipFree(dev_a);
hipFree(dev_b);
return cudaStatus;
} | .text
.file "myDeviceMsg.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__addKernelPiPKiS1_ # -- Begin function _Z24__device_stub__addKernelPiPKiS1_
.p2align 4, 0x90
.type _Z24__device_stub__addKernelPiPKiS1_,@function
_Z24__device_stub__addKernelPiPKiS1_: # @_Z24__device_stub__addKernelPiPKiS1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addKernelPiPKiS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__addKernelPiPKiS1_, .Lfunc_end0-_Z24__device_stub__addKernelPiPKiS1_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $0, 4(%rsp)
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 4(%rsp)
jle .LBB1_35
# %bb.1: # %.lr.ph
leaq 8(%rsp), %rbx
xorl %ebp, %ebp
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_33: # in Loop: Header=BB1_2 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_34: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit43
# in Loop: Header=BB1_2 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cmpl 4(%rsp), %ebp
jge .LBB1_35
.LBB1_2: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incl %ebp
movl $_ZSt4cout, %edi
movl %ebp, %esi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.1, %esi
movl $20, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB1_36
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_2 Depth=1
cmpb $0, 56(%r15)
je .LBB1_5
# %bb.4: # in Loop: Header=BB1_2 Depth=1
movzbl 67(%r15), %eax
jmp .LBB1_6
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_2 Depth=1
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_2 Depth=1
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
callq strlen
movl $_ZSt4cout, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB1_36
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i10
# in Loop: Header=BB1_2 Depth=1
cmpb $0, 56(%r14)
je .LBB1_9
# %bb.8: # in Loop: Header=BB1_2 Depth=1
movzbl 67(%r14), %eax
jmp .LBB1_10
.p2align 4, 0x90
.LBB1_9: # in Loop: Header=BB1_2 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit13
# in Loop: Header=BB1_2 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl 344(%rsp), %esi
movl 348(%rsp), %edx
movl 352(%rsp), %ecx
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl 332(%rsp), %esi
movl 336(%rsp), %edx
movl 340(%rsp), %ecx
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl 316(%rsp), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movq 360(%rsp), %rsi
shrq $10, %rsi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $48, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 296(%rsp), %rsi
shrq $20, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_36
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i15
# in Loop: Header=BB1_2 Depth=1
cmpb $0, 56(%r14)
je .LBB1_13
# %bb.12: # in Loop: Header=BB1_2 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB1_14
.p2align 4, 0x90
.LBB1_13: # in Loop: Header=BB1_2 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit18
# in Loop: Header=BB1_2 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $89, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 304(%rsp), %rsi
shrq $10, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_36
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i20
# in Loop: Header=BB1_2 Depth=1
cmpb $0, 56(%r14)
je .LBB1_17
# %bb.16: # in Loop: Header=BB1_2 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB1_18
.p2align 4, 0x90
.LBB1_17: # in Loop: Header=BB1_2 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit23
# in Loop: Header=BB1_2 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $71, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 312(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_36
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i25
# in Loop: Header=BB1_2 Depth=1
cmpb $0, 56(%r14)
je .LBB1_21
# %bb.20: # in Loop: Header=BB1_2 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB1_22
.p2align 4, 0x90
.LBB1_21: # in Loop: Header=BB1_2 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit28
# in Loop: Header=BB1_2 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.10, %esi
movl $69, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 328(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_36
# %bb.23: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i30
# in Loop: Header=BB1_2 Depth=1
cmpb $0, 56(%r14)
je .LBB1_25
# %bb.24: # in Loop: Header=BB1_2 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB1_26
.p2align 4, 0x90
.LBB1_25: # in Loop: Header=BB1_2 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_26: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit33
# in Loop: Header=BB1_2 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.11, %esi
movl $64, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 368(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.12, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 372(%rsp), %esi
movq %r14, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_36
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i35
# in Loop: Header=BB1_2 Depth=1
cmpb $0, 56(%r14)
je .LBB1_29
# %bb.28: # in Loop: Header=BB1_2 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB1_30
.p2align 4, 0x90
.LBB1_29: # in Loop: Header=BB1_2 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit38
# in Loop: Header=BB1_2 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.13, %esi
movl $34, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 396(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_36
# %bb.31: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i40
# in Loop: Header=BB1_2 Depth=1
cmpb $0, 56(%r14)
je .LBB1_33
# %bb.32: # in Loop: Header=BB1_2 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB1_34
.LBB1_35: # %._crit_edge
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_36:
.cfi_def_cfa_offset 1520
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z11addWithCudaPiPKiS1_m # -- Begin function _Z11addWithCudaPiPKiS1_m
.p2align 4, 0x90
.type _Z11addWithCudaPiPKiS1_m,@function
_Z11addWithCudaPiPKiS1_m: # @_Z11addWithCudaPiPKiS1_m
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbx
movq $0, 16(%rsp)
movq $0, 8(%rsp)
movq $0, (%rsp)
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB2_17
# %bb.1:
leaq (,%r15,4), %r14
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_11
# %bb.2:
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_11
# %bb.3:
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_11
# %bb.4:
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_12
# %bb.5:
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_12
# %bb.6:
movl %r15d, %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq (%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9addKernelPiPKiS1_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_18
# %bb.9:
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
testl %eax, %eax
je .LBB2_16
# %bb.10:
movq stderr(%rip), %rcx
movl $.L.str.16, %edi
movl $17, %esi
movl $1, %edx
movl %eax, %ebx
jmp .LBB2_15
.LBB2_11:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.15, %edi
jmp .LBB2_13
.LBB2_12:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.16, %edi
.LBB2_13:
movl $17, %esi
.LBB2_14:
movl $1, %edx
.LBB2_15:
callq fwrite@PLT
.LBB2_16:
movq (%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl %ebx, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_17:
.cfi_def_cfa_offset 176
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.14, %edi
movl $63, %esi
jmp .LBB2_14
.LBB2_18:
movq stderr(%rip), %rdi
movl $.L.str.17, %esi
movl %eax, %ebx
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB2_16
.Lfunc_end2:
.size _Z11addWithCudaPiPKiS1_m, .Lfunc_end2-_Z11addWithCudaPiPKiS1_m
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addKernelPiPKiS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addKernelPiPKiS1_,@object # @_Z9addKernelPiPKiS1_
.section .rodata,"a",@progbits
.globl _Z9addKernelPiPKiS1_
.p2align 3, 0x0
_Z9addKernelPiPKiS1_:
.quad _Z24__device_stub__addKernelPiPKiS1_
.size _Z9addKernelPiPKiS1_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\350\256\276\345\244\207 "
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " \347\232\204\344\270\273\350\246\201\345\261\236\346\200\247\357\274\232 "
.size .L.str.1, 21
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\350\256\276\345\244\207\346\230\276\345\215\241\345\236\213\345\217\267\357\274\232 "
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "maxGridSize:%d,%d,%d\n"
.size .L.str.3, 22
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "maxThreadDim:%d,%d,%d\n"
.size .L.str.4, 23
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "warpSize:%d\n"
.size .L.str.5, 13
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "constanMemory:%d(K)\n"
.size .L.str.6, 21
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\350\256\276\345\244\207\345\205\250\345\261\200\345\206\205\345\255\230\346\200\273\351\207\217\357\274\210\344\273\245MB\344\270\272\345\215\225\344\275\215\357\274\211\357\274\232 "
.size .L.str.7, 49
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\350\256\276\345\244\207\344\270\212\344\270\200\344\270\252\347\272\277\347\250\213\345\235\227\357\274\210Block\357\274\211\344\270\255\345\217\257\347\224\250\347\232\204\346\234\200\345\244\247\345\205\261\344\272\253\345\206\205\345\255\230\357\274\210\344\273\245KB\344\270\272\345\215\225\344\275\215\357\274\211\357\274\232 "
.size .L.str.8, 90
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "\350\256\276\345\244\207\344\270\212\344\270\200\344\270\252\347\272\277\347\250\213\345\235\227\357\274\210Block\357\274\211\347\247\215\345\217\257\347\224\250\347\232\20432\344\275\215\345\257\204\345\255\230\345\231\250\346\225\260\351\207\217\357\274\232 "
.size .L.str.9, 72
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\350\256\276\345\244\207\344\270\212\344\270\200\344\270\252\347\272\277\347\250\213\345\235\227\357\274\210Block\357\274\211\345\217\257\345\214\205\345\220\253\347\232\204\346\234\200\345\244\247\347\272\277\347\250\213\346\225\260\351\207\217\357\274\232 "
.size .L.str.10, 70
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "\350\256\276\345\244\207\347\232\204\350\256\241\347\256\227\345\212\237\350\203\275\351\233\206\357\274\210Compute Capability\357\274\211\347\232\204\347\211\210\346\234\254\345\217\267\357\274\232 "
.size .L.str.11, 65
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "."
.size .L.str.12, 2
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "\350\256\276\345\244\207\344\270\212\345\244\232\345\244\204\347\220\206\345\231\250\347\232\204\346\225\260\351\207\217\357\274\232 "
.size .L.str.13, 35
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "hipSetDevice failed! Do you have a CUDA-capable GPU installed?"
.size .L.str.14, 64
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "hipMalloc failed!"
.size .L.str.15, 18
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "hipMemcpy failed!"
.size .L.str.16, 18
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "hipDeviceSynchronize returned error code %d after launching addKernel!\n"
.size .L.str.17, 72
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addKernelPiPKiS1_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addKernelPiPKiS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addKernelPiPKiS1_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9addKernelPiPKiS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addKernelPiPKiS1_
.globl _Z9addKernelPiPKiS1_
.p2align 8
.type _Z9addKernelPiPKiS1_,@function
_Z9addKernelPiPKiS1_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[6:7]
global_load_b32 v2, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[4:5]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addKernelPiPKiS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addKernelPiPKiS1_, .Lfunc_end0-_Z9addKernelPiPKiS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addKernelPiPKiS1_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z9addKernelPiPKiS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000953b2_00000000-6_myDeviceMsg.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\350\256\276\345\244\207 "
.LC1:
.string " \347\232\204\344\270\273\350\246\201\345\261\236\346\200\247\357\274\232 "
.LC2:
.string "\350\256\276\345\244\207\346\230\276\345\215\241\345\236\213\345\217\267\357\274\232 "
.LC3:
.string "maxGridSize:%d,%d,%d\n"
.LC4:
.string "maxThreadDim:%d,%d,%d\n"
.LC5:
.string "warpSize:%d\n"
.LC6:
.string "constanMemory:%d(K)\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "\350\256\276\345\244\207\345\205\250\345\261\200\345\206\205\345\255\230\346\200\273\351\207\217\357\274\210\344\273\245MB\344\270\272\345\215\225\344\275\215\357\274\211\357\274\232 "
.align 8
.LC8:
.string "\350\256\276\345\244\207\344\270\212\344\270\200\344\270\252\347\272\277\347\250\213\345\235\227\357\274\210Block\357\274\211\344\270\255\345\217\257\347\224\250\347\232\204\346\234\200\345\244\247\345\205\261\344\272\253\345\206\205\345\255\230\357\274\210\344\273\245KB\344\270\272\345\215\225\344\275\215\357\274\211\357\274\232 "
.align 8
.LC9:
.string "\350\256\276\345\244\207\344\270\212\344\270\200\344\270\252\347\272\277\347\250\213\345\235\227\357\274\210Block\357\274\211\347\247\215\345\217\257\347\224\250\347\232\20432\344\275\215\345\257\204\345\255\230\345\231\250\346\225\260\351\207\217\357\274\232 "
.align 8
.LC10:
.string "\350\256\276\345\244\207\344\270\212\344\270\200\344\270\252\347\272\277\347\250\213\345\235\227\357\274\210Block\357\274\211\345\217\257\345\214\205\345\220\253\347\232\204\346\234\200\345\244\247\347\272\277\347\250\213\346\225\260\351\207\217\357\274\232 "
.align 8
.LC11:
.string "\350\256\276\345\244\207\347\232\204\350\256\241\347\256\227\345\212\237\350\203\275\351\233\206\357\274\210Compute Capability\357\274\211\347\232\204\347\211\210\346\234\254\345\217\267\357\274\232 "
.section .rodata.str1.1
.LC12:
.string "."
.section .rodata.str1.8
.align 8
.LC13:
.string "\350\256\276\345\244\207\344\270\212\345\244\232\345\244\204\347\220\206\345\231\250\347\232\204\346\225\260\351\207\217\357\274\232 "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
jle .L4
movl $0, %r12d
leaq .LC0(%rip), %r14
leaq _ZSt4cout(%rip), %rbx
leaq .LC1(%rip), %r13
jmp .L37
.L49:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L41
call _ZSt16__throw_bad_castv@PLT
.L41:
call __stack_chk_fail@PLT
.L7:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L8
.L50:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L42
call _ZSt16__throw_bad_castv@PLT
.L42:
call __stack_chk_fail@PLT
.L11:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L12
.L51:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L43
call _ZSt16__throw_bad_castv@PLT
.L43:
call __stack_chk_fail@PLT
.L15:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L16
.L52:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L44
call _ZSt16__throw_bad_castv@PLT
.L44:
call __stack_chk_fail@PLT
.L19:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L20
.L53:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L45
call _ZSt16__throw_bad_castv@PLT
.L45:
call __stack_chk_fail@PLT
.L23:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L24
.L54:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L46
call _ZSt16__throw_bad_castv@PLT
.L46:
call __stack_chk_fail@PLT
.L27:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L28
.L55:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L47
call _ZSt16__throw_bad_castv@PLT
.L47:
call __stack_chk_fail@PLT
.L31:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L32
.L56:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L48
call _ZSt16__throw_bad_castv@PLT
.L48:
call __stack_chk_fail@PLT
.L57:
movzbl 67(%r15), %esi
.L36:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
cmpl 12(%rsp), %r12d
jge .L4
.L37:
leaq 16(%rsp), %rdi
movl %r12d, %esi
call cudaGetDeviceProperties_v2@PLT
movl $7, %edx
movq %r14, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addl $1, %r12d
movl %r12d, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $20, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L49
cmpb $0, 56(%r15)
je .L7
movzbl 67(%r15), %esi
.L8:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $22, %edx
leaq .LC2(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
leaq 16(%rsp), %rbp
movq %rbp, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L50
cmpb $0, 56(%rbp)
je .L11
movzbl 67(%rbp), %esi
.L12:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 324(%rsp), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 368(%rsp), %rdx
shrq $10, %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $48, %edx
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 304(%rsp), %rsi
shrq $20, %rsi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L51
cmpb $0, 56(%r15)
je .L15
movzbl 67(%r15), %esi
.L16:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $89, %edx
leaq .LC8(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 312(%rsp), %rsi
shrq $10, %rsi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L52
cmpb $0, 56(%r15)
je .L19
movzbl 67(%r15), %esi
.L20:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $71, %edx
leaq .LC9(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 320(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L53
cmpb $0, 56(%r15)
je .L23
movzbl 67(%r15), %esi
.L24:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $69, %edx
leaq .LC10(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 336(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L54
cmpb $0, 56(%r15)
je .L27
movzbl 67(%r15), %esi
.L28:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $64, %edx
leaq .LC11(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 376(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $1, %edx
leaq .LC12(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 380(%rsp), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L55
cmpb $0, 56(%r15)
je .L31
movzbl 67(%r15), %esi
.L32:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $34, %edx
leaq .LC13(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 404(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L56
cmpb $0, 56(%r15)
jne .L57
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L36
.L4:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L58
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.globl _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
.type _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_, @function
_Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_:
.LFB3695:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L63
.L59:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L64
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L63:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addKernelPiPKiS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L59
.L64:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_, .-_Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
.globl _Z9addKernelPiPKiS1_
.type _Z9addKernelPiPKiS1_, @function
_Z9addKernelPiPKiS1_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z9addKernelPiPKiS1_, .-_Z9addKernelPiPKiS1_
.section .rodata.str1.8
.align 8
.LC14:
.string "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?"
.section .rodata.str1.1
.LC15:
.string "cudaMalloc failed!"
.LC16:
.string "cudaMemcpy failed!"
.section .rodata.str1.8
.align 8
.LC17:
.string "cudaThreadSynchronize returned error code %d after launching addKernel!\n"
.text
.globl _Z11addWithCudaPiPKiS1_m
.type _Z11addWithCudaPiPKiS1_m, @function
_Z11addWithCudaPiPKiS1_m:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r14
movq %rsi, %r12
movq %rdx, %r13
movq %rcx, %rbp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L79
leaq 0(,%rbp,4), %r15
leaq 24(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L80
leaq 8(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L81
leaq 16(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L82
movl $1, %ecx
movq %r15, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L83
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L84
movl %ebp, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L85
.L75:
call cudaThreadSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L86
movl $2, %ecx
movq %r15, %rdx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
je .L69
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L69
.L79:
movl %eax, %ebx
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L69:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L87
movl %ebx, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L80:
.cfi_restore_state
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L69
.L81:
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L69
.L82:
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L69
.L83:
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L69
.L84:
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L69
.L85:
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z34__device_stub__Z9addKernelPiPKiS1_PiPKiS1_
jmp .L75
.L86:
movl %eax, %ecx
leaq .LC17(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L69
.L87:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size _Z11addWithCudaPiPKiS1_m, .-_Z11addWithCudaPiPKiS1_m
.section .rodata.str1.1
.LC18:
.string "_Z9addKernelPiPKiS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addKernelPiPKiS1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "myDeviceMsg.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__addKernelPiPKiS1_ # -- Begin function _Z24__device_stub__addKernelPiPKiS1_
.p2align 4, 0x90
.type _Z24__device_stub__addKernelPiPKiS1_,@function
_Z24__device_stub__addKernelPiPKiS1_: # @_Z24__device_stub__addKernelPiPKiS1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addKernelPiPKiS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__addKernelPiPKiS1_, .Lfunc_end0-_Z24__device_stub__addKernelPiPKiS1_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $0, 4(%rsp)
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 4(%rsp)
jle .LBB1_35
# %bb.1: # %.lr.ph
leaq 8(%rsp), %rbx
xorl %ebp, %ebp
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_33: # in Loop: Header=BB1_2 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_34: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit43
# in Loop: Header=BB1_2 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cmpl 4(%rsp), %ebp
jge .LBB1_35
.LBB1_2: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incl %ebp
movl $_ZSt4cout, %edi
movl %ebp, %esi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.1, %esi
movl $20, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB1_36
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_2 Depth=1
cmpb $0, 56(%r15)
je .LBB1_5
# %bb.4: # in Loop: Header=BB1_2 Depth=1
movzbl 67(%r15), %eax
jmp .LBB1_6
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_2 Depth=1
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_2 Depth=1
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
callq strlen
movl $_ZSt4cout, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB1_36
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i10
# in Loop: Header=BB1_2 Depth=1
cmpb $0, 56(%r14)
je .LBB1_9
# %bb.8: # in Loop: Header=BB1_2 Depth=1
movzbl 67(%r14), %eax
jmp .LBB1_10
.p2align 4, 0x90
.LBB1_9: # in Loop: Header=BB1_2 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit13
# in Loop: Header=BB1_2 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl 344(%rsp), %esi
movl 348(%rsp), %edx
movl 352(%rsp), %ecx
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl 332(%rsp), %esi
movl 336(%rsp), %edx
movl 340(%rsp), %ecx
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl 316(%rsp), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movq 360(%rsp), %rsi
shrq $10, %rsi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $48, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 296(%rsp), %rsi
shrq $20, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_36
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i15
# in Loop: Header=BB1_2 Depth=1
cmpb $0, 56(%r14)
je .LBB1_13
# %bb.12: # in Loop: Header=BB1_2 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB1_14
.p2align 4, 0x90
.LBB1_13: # in Loop: Header=BB1_2 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit18
# in Loop: Header=BB1_2 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $89, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 304(%rsp), %rsi
shrq $10, %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_36
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i20
# in Loop: Header=BB1_2 Depth=1
cmpb $0, 56(%r14)
je .LBB1_17
# %bb.16: # in Loop: Header=BB1_2 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB1_18
.p2align 4, 0x90
.LBB1_17: # in Loop: Header=BB1_2 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit23
# in Loop: Header=BB1_2 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $71, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 312(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_36
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i25
# in Loop: Header=BB1_2 Depth=1
cmpb $0, 56(%r14)
je .LBB1_21
# %bb.20: # in Loop: Header=BB1_2 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB1_22
.p2align 4, 0x90
.LBB1_21: # in Loop: Header=BB1_2 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit28
# in Loop: Header=BB1_2 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.10, %esi
movl $69, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 328(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_36
# %bb.23: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i30
# in Loop: Header=BB1_2 Depth=1
cmpb $0, 56(%r14)
je .LBB1_25
# %bb.24: # in Loop: Header=BB1_2 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB1_26
.p2align 4, 0x90
.LBB1_25: # in Loop: Header=BB1_2 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_26: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit33
# in Loop: Header=BB1_2 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.11, %esi
movl $64, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 368(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.12, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 372(%rsp), %esi
movq %r14, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_36
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i35
# in Loop: Header=BB1_2 Depth=1
cmpb $0, 56(%r14)
je .LBB1_29
# %bb.28: # in Loop: Header=BB1_2 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB1_30
.p2align 4, 0x90
.LBB1_29: # in Loop: Header=BB1_2 Depth=1
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit38
# in Loop: Header=BB1_2 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.13, %esi
movl $34, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 396(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_36
# %bb.31: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i40
# in Loop: Header=BB1_2 Depth=1
cmpb $0, 56(%r14)
je .LBB1_33
# %bb.32: # in Loop: Header=BB1_2 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB1_34
.LBB1_35: # %._crit_edge
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_36:
.cfi_def_cfa_offset 1520
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z11addWithCudaPiPKiS1_m # -- Begin function _Z11addWithCudaPiPKiS1_m
.p2align 4, 0x90
.type _Z11addWithCudaPiPKiS1_m,@function
_Z11addWithCudaPiPKiS1_m: # @_Z11addWithCudaPiPKiS1_m
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbx
movq $0, 16(%rsp)
movq $0, 8(%rsp)
movq $0, (%rsp)
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB2_17
# %bb.1:
leaq (,%r15,4), %r14
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_11
# %bb.2:
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_11
# %bb.3:
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_11
# %bb.4:
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_12
# %bb.5:
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_12
# %bb.6:
movl %r15d, %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq (%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9addKernelPiPKiS1_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_18
# %bb.9:
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
testl %eax, %eax
je .LBB2_16
# %bb.10:
movq stderr(%rip), %rcx
movl $.L.str.16, %edi
movl $17, %esi
movl $1, %edx
movl %eax, %ebx
jmp .LBB2_15
.LBB2_11:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.15, %edi
jmp .LBB2_13
.LBB2_12:
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.16, %edi
.LBB2_13:
movl $17, %esi
.LBB2_14:
movl $1, %edx
.LBB2_15:
callq fwrite@PLT
.LBB2_16:
movq (%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl %ebx, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_17:
.cfi_def_cfa_offset 176
movl %eax, %ebx
movq stderr(%rip), %rcx
movl $.L.str.14, %edi
movl $63, %esi
jmp .LBB2_14
.LBB2_18:
movq stderr(%rip), %rdi
movl $.L.str.17, %esi
movl %eax, %ebx
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB2_16
.Lfunc_end2:
.size _Z11addWithCudaPiPKiS1_m, .Lfunc_end2-_Z11addWithCudaPiPKiS1_m
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addKernelPiPKiS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addKernelPiPKiS1_,@object # @_Z9addKernelPiPKiS1_
.section .rodata,"a",@progbits
.globl _Z9addKernelPiPKiS1_
.p2align 3, 0x0
_Z9addKernelPiPKiS1_:
.quad _Z24__device_stub__addKernelPiPKiS1_
.size _Z9addKernelPiPKiS1_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\350\256\276\345\244\207 "
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " \347\232\204\344\270\273\350\246\201\345\261\236\346\200\247\357\274\232 "
.size .L.str.1, 21
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\350\256\276\345\244\207\346\230\276\345\215\241\345\236\213\345\217\267\357\274\232 "
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "maxGridSize:%d,%d,%d\n"
.size .L.str.3, 22
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "maxThreadDim:%d,%d,%d\n"
.size .L.str.4, 23
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "warpSize:%d\n"
.size .L.str.5, 13
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "constanMemory:%d(K)\n"
.size .L.str.6, 21
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\350\256\276\345\244\207\345\205\250\345\261\200\345\206\205\345\255\230\346\200\273\351\207\217\357\274\210\344\273\245MB\344\270\272\345\215\225\344\275\215\357\274\211\357\274\232 "
.size .L.str.7, 49
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\350\256\276\345\244\207\344\270\212\344\270\200\344\270\252\347\272\277\347\250\213\345\235\227\357\274\210Block\357\274\211\344\270\255\345\217\257\347\224\250\347\232\204\346\234\200\345\244\247\345\205\261\344\272\253\345\206\205\345\255\230\357\274\210\344\273\245KB\344\270\272\345\215\225\344\275\215\357\274\211\357\274\232 "
.size .L.str.8, 90
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "\350\256\276\345\244\207\344\270\212\344\270\200\344\270\252\347\272\277\347\250\213\345\235\227\357\274\210Block\357\274\211\347\247\215\345\217\257\347\224\250\347\232\20432\344\275\215\345\257\204\345\255\230\345\231\250\346\225\260\351\207\217\357\274\232 "
.size .L.str.9, 72
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\350\256\276\345\244\207\344\270\212\344\270\200\344\270\252\347\272\277\347\250\213\345\235\227\357\274\210Block\357\274\211\345\217\257\345\214\205\345\220\253\347\232\204\346\234\200\345\244\247\347\272\277\347\250\213\346\225\260\351\207\217\357\274\232 "
.size .L.str.10, 70
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "\350\256\276\345\244\207\347\232\204\350\256\241\347\256\227\345\212\237\350\203\275\351\233\206\357\274\210Compute Capability\357\274\211\347\232\204\347\211\210\346\234\254\345\217\267\357\274\232 "
.size .L.str.11, 65
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "."
.size .L.str.12, 2
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "\350\256\276\345\244\207\344\270\212\345\244\232\345\244\204\347\220\206\345\231\250\347\232\204\346\225\260\351\207\217\357\274\232 "
.size .L.str.13, 35
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "hipSetDevice failed! Do you have a CUDA-capable GPU installed?"
.size .L.str.14, 64
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "hipMalloc failed!"
.size .L.str.15, 18
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "hipMemcpy failed!"
.size .L.str.16, 18
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "hipDeviceSynchronize returned error code %d after launching addKernel!\n"
.size .L.str.17, 72
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addKernelPiPKiS1_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addKernelPiPKiS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addKernelPiPKiS1_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <cuda_runtime_api.h>
#define N_MEM_OPS_PER_KERNEL 2
//-----------------------------------------------------------------------------
// Simple test kernel template for memory ops test
// @param d_counters - Simple memory location to exploit for lots of memory accesses
// @param n_threads - Total number of threads per block
//-----------------------------------------------------------------------------
__global__
void max_flops_kernel(float* d_in, float* d_out, int offset) {
// Increment the counter
int it = blockIdx.x * blockDim.x + threadIdx.x + offset;
d_out[it] = d_in[it];
} | code for sm_80
Function : _Z16max_flops_kernelPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ IADD3 R0, R0, c[0x0][0x170], RZ ; /* 0x00005c0000007a10 */
/* 0x000fca0007ffe0ff */
/*0070*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0205 */
/*0080*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0090*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0205 */
/*00a0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cuda_runtime_api.h>
#define N_MEM_OPS_PER_KERNEL 2
//-----------------------------------------------------------------------------
// Simple test kernel template for memory ops test
// @param d_counters - Simple memory location to exploit for lots of memory accesses
// @param n_threads - Total number of threads per block
//-----------------------------------------------------------------------------
__global__
void max_flops_kernel(float* d_in, float* d_out, int offset) {
// Increment the counter
int it = blockIdx.x * blockDim.x + threadIdx.x + offset;
d_out[it] = d_in[it];
} | .file "tmpxft_000d8652_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z16max_flops_kernelPfS_iPfS_i
.type _Z39__device_stub__Z16max_flops_kernelPfS_iPfS_i, @function
_Z39__device_stub__Z16max_flops_kernelPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16max_flops_kernelPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z16max_flops_kernelPfS_iPfS_i, .-_Z39__device_stub__Z16max_flops_kernelPfS_iPfS_i
.globl _Z16max_flops_kernelPfS_i
.type _Z16max_flops_kernelPfS_i, @function
_Z16max_flops_kernelPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16max_flops_kernelPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16max_flops_kernelPfS_i, .-_Z16max_flops_kernelPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16max_flops_kernelPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16max_flops_kernelPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cuda_runtime_api.h>
#define N_MEM_OPS_PER_KERNEL 2
//-----------------------------------------------------------------------------
// Simple test kernel template for memory ops test
// @param d_counters - Simple memory location to exploit for lots of memory accesses
// @param n_threads - Total number of threads per block
//-----------------------------------------------------------------------------
__global__
void max_flops_kernel(float* d_in, float* d_out, int offset) {
// Increment the counter
int it = blockIdx.x * blockDim.x + threadIdx.x + offset;
d_out[it] = d_in[it];
} | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#define N_MEM_OPS_PER_KERNEL 2
//-----------------------------------------------------------------------------
// Simple test kernel template for memory ops test
// @param d_counters - Simple memory location to exploit for lots of memory accesses
// @param n_threads - Total number of threads per block
//-----------------------------------------------------------------------------
__global__
void max_flops_kernel(float* d_in, float* d_out, int offset) {
// Increment the counter
int it = blockIdx.x * blockDim.x + threadIdx.x + offset;
d_out[it] = d_in[it];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#define N_MEM_OPS_PER_KERNEL 2
//-----------------------------------------------------------------------------
// Simple test kernel template for memory ops test
// @param d_counters - Simple memory location to exploit for lots of memory accesses
// @param n_threads - Total number of threads per block
//-----------------------------------------------------------------------------
__global__
void max_flops_kernel(float* d_in, float* d_out, int offset) {
// Increment the counter
int it = blockIdx.x * blockDim.x + threadIdx.x + offset;
d_out[it] = d_in[it];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16max_flops_kernelPfS_i
.globl _Z16max_flops_kernelPfS_i
.p2align 8
.type _Z16max_flops_kernelPfS_i,@function
_Z16max_flops_kernelPfS_i:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s5, s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s4
v_add3_u32 v0, s15, s5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16max_flops_kernelPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16max_flops_kernelPfS_i, .Lfunc_end0-_Z16max_flops_kernelPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16max_flops_kernelPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16max_flops_kernelPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#define N_MEM_OPS_PER_KERNEL 2
//-----------------------------------------------------------------------------
// Simple test kernel template for memory ops test
// @param d_counters - Simple memory location to exploit for lots of memory accesses
// @param n_threads - Total number of threads per block
//-----------------------------------------------------------------------------
__global__
void max_flops_kernel(float* d_in, float* d_out, int offset) {
// Increment the counter
int it = blockIdx.x * blockDim.x + threadIdx.x + offset;
d_out[it] = d_in[it];
} | .text
.file "kernel.hip"
.globl _Z31__device_stub__max_flops_kernelPfS_i # -- Begin function _Z31__device_stub__max_flops_kernelPfS_i
.p2align 4, 0x90
.type _Z31__device_stub__max_flops_kernelPfS_i,@function
_Z31__device_stub__max_flops_kernelPfS_i: # @_Z31__device_stub__max_flops_kernelPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16max_flops_kernelPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z31__device_stub__max_flops_kernelPfS_i, .Lfunc_end0-_Z31__device_stub__max_flops_kernelPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16max_flops_kernelPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16max_flops_kernelPfS_i,@object # @_Z16max_flops_kernelPfS_i
.section .rodata,"a",@progbits
.globl _Z16max_flops_kernelPfS_i
.p2align 3, 0x0
_Z16max_flops_kernelPfS_i:
.quad _Z31__device_stub__max_flops_kernelPfS_i
.size _Z16max_flops_kernelPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16max_flops_kernelPfS_i"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__max_flops_kernelPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16max_flops_kernelPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16max_flops_kernelPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ IADD3 R0, R0, c[0x0][0x170], RZ ; /* 0x00005c0000007a10 */
/* 0x000fca0007ffe0ff */
/*0070*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0205 */
/*0080*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0090*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0205 */
/*00a0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16max_flops_kernelPfS_i
.globl _Z16max_flops_kernelPfS_i
.p2align 8
.type _Z16max_flops_kernelPfS_i,@function
_Z16max_flops_kernelPfS_i:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s5, s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s4
v_add3_u32 v0, s15, s5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16max_flops_kernelPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16max_flops_kernelPfS_i, .Lfunc_end0-_Z16max_flops_kernelPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16max_flops_kernelPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16max_flops_kernelPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d8652_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z16max_flops_kernelPfS_iPfS_i
.type _Z39__device_stub__Z16max_flops_kernelPfS_iPfS_i, @function
_Z39__device_stub__Z16max_flops_kernelPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16max_flops_kernelPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z16max_flops_kernelPfS_iPfS_i, .-_Z39__device_stub__Z16max_flops_kernelPfS_iPfS_i
.globl _Z16max_flops_kernelPfS_i
.type _Z16max_flops_kernelPfS_i, @function
_Z16max_flops_kernelPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16max_flops_kernelPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16max_flops_kernelPfS_i, .-_Z16max_flops_kernelPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16max_flops_kernelPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16max_flops_kernelPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z31__device_stub__max_flops_kernelPfS_i # -- Begin function _Z31__device_stub__max_flops_kernelPfS_i
.p2align 4, 0x90
.type _Z31__device_stub__max_flops_kernelPfS_i,@function
_Z31__device_stub__max_flops_kernelPfS_i: # @_Z31__device_stub__max_flops_kernelPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16max_flops_kernelPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z31__device_stub__max_flops_kernelPfS_i, .Lfunc_end0-_Z31__device_stub__max_flops_kernelPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16max_flops_kernelPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16max_flops_kernelPfS_i,@object # @_Z16max_flops_kernelPfS_i
.section .rodata,"a",@progbits
.globl _Z16max_flops_kernelPfS_i
.p2align 3, 0x0
_Z16max_flops_kernelPfS_i:
.quad _Z31__device_stub__max_flops_kernelPfS_i
.size _Z16max_flops_kernelPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16max_flops_kernelPfS_i"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__max_flops_kernelPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16max_flops_kernelPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
using namespace std;
__global__ void recMapKernel(float *ptr, int width, int height, float contrast, float intensity, float colorc, float lighta, float *adaptGlobal)
{
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if(x < width && y < height)
{
int idx = 3 * (width * y + x);
ptr += idx;
float lum = 0.2125f * ptr[0] + 0.7154f * ptr[1] + 0.0721f * ptr[2];
for(int channel = 0; channel < 3; channel++) {
float adaptLocal = colorc * ptr[channel] + (1.0f - colorc) * lum;
float adapt = lighta * adaptLocal + (1.0f - lighta) * adaptGlobal[channel];
ptr[channel] = ptr[channel] / (ptr[channel] + powf(intensity * adapt, contrast));
}
}
}
extern "C"
void recMapApply(float *ptr, int width, int height, float contrast, float intensity, float colorc, float lighta, float *adaptGlobal)
{
int image_memory = width * height * 3 * sizeof(*ptr);
float *gpuPtr = NULL;
cudaMalloc((void**) &gpuPtr, image_memory);
float *adaptGpu = NULL;
cudaMalloc((void**) &adaptGpu, 3*sizeof(float));
cudaMemcpy(gpuPtr, ptr, image_memory, cudaMemcpyHostToDevice);
cudaMemcpy(adaptGpu, adaptGlobal, 3*sizeof(float), cudaMemcpyHostToDevice);
dim3 threads(16, 16);
dim3 blocks((width + threads.x - 1) / threads.x, (height + threads.y - 1) / threads.y);
recMapKernel<<<blocks, threads>>>(gpuPtr, width, height, contrast, intensity, colorc, lighta, adaptGpu);
cudaMemcpy(ptr, gpuPtr, image_memory, cudaMemcpyDeviceToHost);
cudaFree(gpuPtr);
} | .file "tmpxft_001788de_00000000-6_rec_map.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z12recMapKernelPfiiffffS_PfiiffffS_
.type _Z40__device_stub__Z12recMapKernelPfiiffffS_PfiiffffS_, @function
_Z40__device_stub__Z12recMapKernelPfiiffffS_PfiiffffS_:
.LFB3694:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12recMapKernelPfiiffffS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z40__device_stub__Z12recMapKernelPfiiffffS_PfiiffffS_, .-_Z40__device_stub__Z12recMapKernelPfiiffffS_PfiiffffS_
.globl _Z12recMapKernelPfiiffffS_
.type _Z12recMapKernelPfiiffffS_, @function
_Z12recMapKernelPfiiffffS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z12recMapKernelPfiiffffS_PfiiffffS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z12recMapKernelPfiiffffS_, .-_Z12recMapKernelPfiiffffS_
.globl recMapApply
.type recMapApply, @function
recMapApply:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r13
movl %esi, %ebp
movl %edx, %r12d
movss %xmm0, (%rsp)
movss %xmm1, 4(%rsp)
movss %xmm2, 8(%rsp)
movss %xmm3, 12(%rsp)
movq %rcx, %r14
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq $0, 16(%rsp)
movl %esi, %eax
imull %edx, %eax
leal (%rax,%rax,2), %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movl $12, %esi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $12, %edx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leal 15(%rbp), %eax
shrl $4, %eax
movl %eax, 44(%rsp)
leal 15(%r12), %eax
shrl $4, %eax
movl %eax, 48(%rsp)
movl $16, 32(%rsp)
movl $16, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 24(%rsp), %rcx
movss 12(%rsp), %xmm3
movss 8(%rsp), %xmm2
movss 4(%rsp), %xmm1
movss (%rsp), %xmm0
movl %r12d, %edx
movl %ebp, %esi
movq 16(%rsp), %rdi
call _Z40__device_stub__Z12recMapKernelPfiiffffS_PfiiffffS_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size recMapApply, .-recMapApply
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12recMapKernelPfiiffffS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12recMapKernelPfiiffffS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
using namespace std;
__global__ void recMapKernel(float *ptr, int width, int height, float contrast, float intensity, float colorc, float lighta, float *adaptGlobal)
{
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if(x < width && y < height)
{
int idx = 3 * (width * y + x);
ptr += idx;
float lum = 0.2125f * ptr[0] + 0.7154f * ptr[1] + 0.0721f * ptr[2];
for(int channel = 0; channel < 3; channel++) {
float adaptLocal = colorc * ptr[channel] + (1.0f - colorc) * lum;
float adapt = lighta * adaptLocal + (1.0f - lighta) * adaptGlobal[channel];
ptr[channel] = ptr[channel] / (ptr[channel] + powf(intensity * adapt, contrast));
}
}
}
extern "C"
void recMapApply(float *ptr, int width, int height, float contrast, float intensity, float colorc, float lighta, float *adaptGlobal)
{
int image_memory = width * height * 3 * sizeof(*ptr);
float *gpuPtr = NULL;
cudaMalloc((void**) &gpuPtr, image_memory);
float *adaptGpu = NULL;
cudaMalloc((void**) &adaptGpu, 3*sizeof(float));
cudaMemcpy(gpuPtr, ptr, image_memory, cudaMemcpyHostToDevice);
cudaMemcpy(adaptGpu, adaptGlobal, 3*sizeof(float), cudaMemcpyHostToDevice);
dim3 threads(16, 16);
dim3 blocks((width + threads.x - 1) / threads.x, (height + threads.y - 1) / threads.y);
recMapKernel<<<blocks, threads>>>(gpuPtr, width, height, contrast, intensity, colorc, lighta, adaptGpu);
cudaMemcpy(ptr, gpuPtr, image_memory, cudaMemcpyDeviceToHost);
cudaFree(gpuPtr);
} | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
__global__ void recMapKernel(float *ptr, int width, int height, float contrast, float intensity, float colorc, float lighta, float *adaptGlobal)
{
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if(x < width && y < height)
{
int idx = 3 * (width * y + x);
ptr += idx;
float lum = 0.2125f * ptr[0] + 0.7154f * ptr[1] + 0.0721f * ptr[2];
for(int channel = 0; channel < 3; channel++) {
float adaptLocal = colorc * ptr[channel] + (1.0f - colorc) * lum;
float adapt = lighta * adaptLocal + (1.0f - lighta) * adaptGlobal[channel];
ptr[channel] = ptr[channel] / (ptr[channel] + powf(intensity * adapt, contrast));
}
}
}
extern "C"
void recMapApply(float *ptr, int width, int height, float contrast, float intensity, float colorc, float lighta, float *adaptGlobal)
{
int image_memory = width * height * 3 * sizeof(*ptr);
float *gpuPtr = NULL;
hipMalloc((void**) &gpuPtr, image_memory);
float *adaptGpu = NULL;
hipMalloc((void**) &adaptGpu, 3*sizeof(float));
hipMemcpy(gpuPtr, ptr, image_memory, hipMemcpyHostToDevice);
hipMemcpy(adaptGpu, adaptGlobal, 3*sizeof(float), hipMemcpyHostToDevice);
dim3 threads(16, 16);
dim3 blocks((width + threads.x - 1) / threads.x, (height + threads.y - 1) / threads.y);
recMapKernel<<<blocks, threads>>>(gpuPtr, width, height, contrast, intensity, colorc, lighta, adaptGpu);
hipMemcpy(ptr, gpuPtr, image_memory, hipMemcpyDeviceToHost);
hipFree(gpuPtr);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
__global__ void recMapKernel(float *ptr, int width, int height, float contrast, float intensity, float colorc, float lighta, float *adaptGlobal)
{
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if(x < width && y < height)
{
int idx = 3 * (width * y + x);
ptr += idx;
float lum = 0.2125f * ptr[0] + 0.7154f * ptr[1] + 0.0721f * ptr[2];
for(int channel = 0; channel < 3; channel++) {
float adaptLocal = colorc * ptr[channel] + (1.0f - colorc) * lum;
float adapt = lighta * adaptLocal + (1.0f - lighta) * adaptGlobal[channel];
ptr[channel] = ptr[channel] / (ptr[channel] + powf(intensity * adapt, contrast));
}
}
}
extern "C"
void recMapApply(float *ptr, int width, int height, float contrast, float intensity, float colorc, float lighta, float *adaptGlobal)
{
int image_memory = width * height * 3 * sizeof(*ptr);
float *gpuPtr = NULL;
hipMalloc((void**) &gpuPtr, image_memory);
float *adaptGpu = NULL;
hipMalloc((void**) &adaptGpu, 3*sizeof(float));
hipMemcpy(gpuPtr, ptr, image_memory, hipMemcpyHostToDevice);
hipMemcpy(adaptGpu, adaptGlobal, 3*sizeof(float), hipMemcpyHostToDevice);
dim3 threads(16, 16);
dim3 blocks((width + threads.x - 1) / threads.x, (height + threads.y - 1) / threads.y);
recMapKernel<<<blocks, threads>>>(gpuPtr, width, height, contrast, intensity, colorc, lighta, adaptGpu);
hipMemcpy(ptr, gpuPtr, image_memory, hipMemcpyDeviceToHost);
hipFree(gpuPtr);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12recMapKernelPfiiffffS_
.globl _Z12recMapKernelPfiiffffS_
.p2align 8
.type _Z12recMapKernelPfiiffffS_,@function
_Z12recMapKernelPfiiffffS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_3
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x18
s_mov_b64 s[10:11], 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v0, v2, 1, v2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_mov_b32 s3, 0x3e76c4e1
global_load_b96 v[2:4], v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v3, 0x3f372474, v3
v_fmamk_f32 v2, v2, 0x3e59999a, v3
v_sub_f32_e64 v3, 1.0, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmamk_f32 v4, v4, 0x3d93a92a, v2
v_sub_f32_e64 v2, 1.0, s5
v_dual_mul_f32 v3, v3, v4 :: v_dual_mov_b32 v4, 0
.LBB0_2:
v_add_co_u32 v5, vcc_lo, v0, s10
v_add_co_ci_u32_e32 v6, vcc_lo, s11, v1, vcc_lo
s_add_u32 s0, s6, s10
s_addc_u32 s1, s7, s11
global_load_b32 v7, v[5:6], off
global_load_b32 v8, v4, s[0:1]
s_waitcnt vmcnt(1)
v_fma_f32 v9, s4, v7, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v9, s5, v9
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v9, v2, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v8, s9, v9
v_cmp_neq_f32_e32 vcc_lo, 1.0, v8
v_cndmask_b32_e64 v9, 1.0, s8, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cmp_neq_f32_e32 vcc_lo, 0, v9
v_cmp_neq_f32_e64 s12, v9, |v9|
v_cmp_gt_f32_e64 s1, 0, v9
v_cndmask_b32_e32 v8, 1.0, v8, vcc_lo
v_frexp_mant_f32_e64 v10, |v8|
v_frexp_exp_i32_f32_e32 v11, v8
v_cmp_lt_f32_e64 s13, |v8|, 1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v10
s_xor_b32 s12, s12, s13
v_cndmask_b32_e64 v12, 0, 1, vcc_lo
v_subrev_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ldexp_f32 v10, v10, v12
v_cvt_f32_i32_e32 v11, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f32_e32 v13, -1.0, v10
v_add_f32_e32 v12, 1.0, v10
v_mul_f32_e32 v16, 0x3f317218, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v14, v12
v_add_f32_e32 v15, -1.0, v12
v_sub_f32_e32 v10, v10, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_fma_f32 v15, v11, 0x3f317218, -v16
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v17, v13, v14
v_fmac_f32_e32 v15, 0xb102e308, v11
v_mul_f32_e32 v11, v12, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v12, v17, v12, -v11
v_fmac_f32_e32 v12, v17, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v10, v11, v12
v_sub_f32_e32 v18, v13, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v13, v13, v18
v_dual_sub_f32 v11, v10, v11 :: v_dual_sub_f32 v10, v13, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v11, v11, v12
v_add_f32_e32 v10, v11, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v10, v18, v10
v_mul_f32_e32 v10, v14, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v11, v17, v10
v_sub_f32_e32 v12, v11, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v13, v11, v11 :: v_dual_sub_f32 v10, v10, v12
v_fma_f32 v12, v11, v11, -v13
v_ldexp_f32 v14, v11, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v17, v10, v10
v_ldexp_f32 v18, v10, 1
v_fmac_f32_e32 v12, v11, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v17, v13, v12
v_fmaak_f32 v19, s3, v17, 0x3e91f4c4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmaak_f32 v19, v17, v19, 0x3ecccdef
v_sub_f32_e32 v13, v17, v13
v_dual_mul_f32 v20, v11, v17 :: v_dual_mul_f32 v21, v17, v19
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v12, v12, v13
v_fma_f32 v13, v17, v11, -v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fmac_f32_e32 v13, v17, v10
v_fma_f32 v10, v17, v19, -v21
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v13, v12, v11
v_fmac_f32_e32 v10, v12, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v12, v21, v10
v_sub_f32_e32 v19, v12, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v11, v20, v13 :: v_dual_sub_f32 v10, v10, v19
v_sub_f32_e32 v17, v11, v20
v_add_f32_e32 v20, 0x3f2aaaaa, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_add_f32 v10, 0x31739010, v10 :: v_dual_sub_f32 v13, v13, v17
v_add_f32_e32 v17, 0xbf2aaaaa, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v12, v12, v17
v_add_f32_e32 v10, v10, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v12, v20, v10
v_sub_f32_e32 v17, v20, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v19, v11, v12 :: v_dual_add_f32 v10, v10, v17
v_fma_f32 v17, v11, v12, -v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v17, v11, v10
v_fmac_f32_e32 v17, v13, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v10, v19, v17
v_sub_f32_e32 v12, v10, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v11, v14, v10 :: v_dual_sub_f32 v12, v17, v12
v_dual_sub_f32 v13, v11, v14 :: v_dual_add_f32 v12, v18, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v10, v10, v13 :: v_dual_add_f32 v13, v16, v15
v_add_f32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v14, v11, v10
v_dual_sub_f32 v12, v13, v16 :: v_dual_sub_f32 v11, v14, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v12, v15, v12 :: v_dual_add_f32 v15, v13, v14
v_sub_f32_e32 v16, v15, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v10, v10, v11 :: v_dual_sub_f32 v11, v15, v16
v_dual_sub_f32 v11, v13, v11 :: v_dual_sub_f32 v14, v14, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v16, v12, v10 :: v_dual_add_f32 v11, v14, v11
v_sub_f32_e32 v13, v16, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v11, v16, v11
v_sub_f32_e32 v14, v16, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_sub_f32 v10, v10, v13 :: v_dual_add_f32 v13, v15, v11
v_sub_f32_e32 v12, v12, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v14, v13, v15
v_dual_sub_f32 v11, v11, v14 :: v_dual_add_f32 v10, v10, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v10, v10, v11
v_add_f32_e32 v11, v13, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v12, v11, v13 :: v_dual_mul_f32 v13, v9, v11
v_sub_f32_e32 v10, v10, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v11, v9, v11, -v13
v_cmp_class_f32_e64 vcc_lo, v13, 0x204
v_fmac_f32_e32 v11, v9, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v10, v13, v11
v_cndmask_b32_e32 v12, v10, v13, vcc_lo
v_sub_f32_e32 v10, v10, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v12
v_sub_f32_e32 v10, v11, v10
v_cndmask_b32_e64 v14, 0, 0x37000000, vcc_lo
v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v12|
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_f32_e32 v15, v12, v14
v_cndmask_b32_e32 v10, 0, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_f32_e32 v16, 0x3fb8aa3b, v15
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v15
v_add_f32_e32 v10, v14, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v17, v15, 0x3fb8aa3b, -v16
v_rndne_f32_e32 v18, v16
v_dual_fmac_f32 v17, 0x32a5705f, v15 :: v_dual_sub_f32 v16, v16, v18
v_cvt_i32_f32_e32 v13, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v16, v16, v17
v_trunc_f32_e32 v17, v9
v_exp_f32_e32 v16, v16
s_waitcnt_depctr 0xfff
v_ldexp_f32 v11, v16, v13
v_mul_f32_e32 v13, 0.5, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v11, 0, v11, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v15
v_trunc_f32_e32 v12, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v11, 0x7f800000, v11, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, v17, v9
v_cmp_neq_f32_e64 s0, v12, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v10, v11, v10, v11
v_cmp_eq_f32_e64 s2, 0x7f800000, v11
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v12, 1.0, v8, s0
v_cndmask_b32_e64 v14, 0, v8, s0
v_cndmask_b32_e64 v10, v10, v11, s2
v_cmp_eq_f32_e64 s2, 0, v8
v_cndmask_b32_e64 v11, |v9|, 0, s12
v_cmp_class_f32_e64 s0, v8, 0x204
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_bfi_b32 v10, 0x7fffffff, v10, v12
s_xor_b32 s1, s1, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v12, 0x7f800000, 0, s1
v_cmp_eq_f32_e64 s1, |v8|, 1.0
v_cndmask_b32_e32 v13, 0x7fc00000, v10, vcc_lo
v_cmp_gt_f32_e32 vcc_lo, 0, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_bfi_b32 v12, 0x7fffffff, v12, v14
v_cndmask_b32_e64 v11, v11, |v8|, s1
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v10, v10, v13, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v9, 0x204
v_cndmask_b32_e32 v10, v10, v11, vcc_lo
s_or_b32 vcc_lo, s2, s0
s_add_u32 s10, s10, 4
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s10, 12
v_cndmask_b32_e32 v10, v10, v12, vcc_lo
v_cmp_o_f32_e32 vcc_lo, v8, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v8, 0x7fc00000, v10, vcc_lo
v_add_f32_e32 v8, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v9, null, v8, v8, v7
v_div_scale_f32 v12, vcc_lo, v7, v8, v7
v_rcp_f32_e32 v10, v9
s_waitcnt_depctr 0xfff
v_fma_f32 v11, -v9, v10, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v10, v11, v10
v_mul_f32_e32 v11, v12, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v13, -v9, v11, v12
v_fmac_f32_e32 v11, v13, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v9, -v9, v11, v12
v_div_fmas_f32 v9, v9, v10, v11
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v7, v9, v8, v7
global_store_b32 v[5:6], v7, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12recMapKernelPfiiffffS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 22
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12recMapKernelPfiiffffS_, .Lfunc_end0-_Z12recMapKernelPfiiffffS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12recMapKernelPfiiffffS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12recMapKernelPfiiffffS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 22
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
__global__ void recMapKernel(float *ptr, int width, int height, float contrast, float intensity, float colorc, float lighta, float *adaptGlobal)
{
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if(x < width && y < height)
{
int idx = 3 * (width * y + x);
ptr += idx;
float lum = 0.2125f * ptr[0] + 0.7154f * ptr[1] + 0.0721f * ptr[2];
for(int channel = 0; channel < 3; channel++) {
float adaptLocal = colorc * ptr[channel] + (1.0f - colorc) * lum;
float adapt = lighta * adaptLocal + (1.0f - lighta) * adaptGlobal[channel];
ptr[channel] = ptr[channel] / (ptr[channel] + powf(intensity * adapt, contrast));
}
}
}
extern "C"
void recMapApply(float *ptr, int width, int height, float contrast, float intensity, float colorc, float lighta, float *adaptGlobal)
{
int image_memory = width * height * 3 * sizeof(*ptr);
float *gpuPtr = NULL;
hipMalloc((void**) &gpuPtr, image_memory);
float *adaptGpu = NULL;
hipMalloc((void**) &adaptGpu, 3*sizeof(float));
hipMemcpy(gpuPtr, ptr, image_memory, hipMemcpyHostToDevice);
hipMemcpy(adaptGpu, adaptGlobal, 3*sizeof(float), hipMemcpyHostToDevice);
dim3 threads(16, 16);
dim3 blocks((width + threads.x - 1) / threads.x, (height + threads.y - 1) / threads.y);
recMapKernel<<<blocks, threads>>>(gpuPtr, width, height, contrast, intensity, colorc, lighta, adaptGpu);
hipMemcpy(ptr, gpuPtr, image_memory, hipMemcpyDeviceToHost);
hipFree(gpuPtr);
} | .text
.file "rec_map.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__recMapKernelPfiiffffS_ # -- Begin function _Z27__device_stub__recMapKernelPfiiffffS_
.p2align 4, 0x90
.type _Z27__device_stub__recMapKernelPfiiffffS_,@function
_Z27__device_stub__recMapKernelPfiiffffS_: # @_Z27__device_stub__recMapKernelPfiiffffS_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movl %esi, 28(%rsp)
movl %edx, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movss %xmm3, 8(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 28(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12recMapKernelPfiiffffS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z27__device_stub__recMapKernelPfiiffffS_, .Lfunc_end0-_Z27__device_stub__recMapKernelPfiiffffS_
.cfi_endproc
# -- End function
.globl recMapApply # -- Begin function recMapApply
.p2align 4, 0x90
.type recMapApply,@function
recMapApply: # @recMapApply
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $192, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %r13
movss %xmm3, 36(%rsp) # 4-byte Spill
movss %xmm2, 32(%rsp) # 4-byte Spill
movss %xmm1, 28(%rsp) # 4-byte Spill
movss %xmm0, 24(%rsp) # 4-byte Spill
movl %edx, %r15d
movl %esi, %r12d
movq %rdi, %rbx
movl %esi, %eax
imull %edx, %eax
shll $2, %eax
leal (%rax,%rax,2), %eax
movq $0, 8(%rsp)
movslq %eax, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movl $12, %esi
callq hipMalloc
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $12, %edx
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
leal 15(%r12), %eax
shrl $4, %eax
leal 15(%r15), %edi
shrl $4, %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 120(%rsp)
movl %r12d, 60(%rsp)
movl %r15d, 56(%rsp)
movss 24(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 52(%rsp)
movss 28(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 48(%rsp)
movss 32(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 44(%rsp)
movss 36(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 40(%rsp)
movq %rcx, 112(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 60(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rax
movq %rax, 144(%rsp)
leaq 52(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rax
movq %rax, 160(%rsp)
leaq 44(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 112(%rsp), %rax
movq %rax, 184(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z12recMapKernelPfiiffffS_, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
addq $192, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size recMapApply, .Lfunc_end1-recMapApply
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12recMapKernelPfiiffffS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12recMapKernelPfiiffffS_,@object # @_Z12recMapKernelPfiiffffS_
.section .rodata,"a",@progbits
.globl _Z12recMapKernelPfiiffffS_
.p2align 3, 0x0
_Z12recMapKernelPfiiffffS_:
.quad _Z27__device_stub__recMapKernelPfiiffffS_
.size _Z12recMapKernelPfiiffffS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12recMapKernelPfiiffffS_"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__recMapKernelPfiiffffS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12recMapKernelPfiiffffS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001788de_00000000-6_rec_map.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z12recMapKernelPfiiffffS_PfiiffffS_
.type _Z40__device_stub__Z12recMapKernelPfiiffffS_PfiiffffS_, @function
_Z40__device_stub__Z12recMapKernelPfiiffffS_PfiiffffS_:
.LFB3694:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12recMapKernelPfiiffffS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z40__device_stub__Z12recMapKernelPfiiffffS_PfiiffffS_, .-_Z40__device_stub__Z12recMapKernelPfiiffffS_PfiiffffS_
.globl _Z12recMapKernelPfiiffffS_
.type _Z12recMapKernelPfiiffffS_, @function
_Z12recMapKernelPfiiffffS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z12recMapKernelPfiiffffS_PfiiffffS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z12recMapKernelPfiiffffS_, .-_Z12recMapKernelPfiiffffS_
.globl recMapApply
.type recMapApply, @function
recMapApply:
.LFB3669:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r13
movl %esi, %ebp
movl %edx, %r12d
movss %xmm0, (%rsp)
movss %xmm1, 4(%rsp)
movss %xmm2, 8(%rsp)
movss %xmm3, 12(%rsp)
movq %rcx, %r14
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq $0, 16(%rsp)
movl %esi, %eax
imull %edx, %eax
leal (%rax,%rax,2), %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movl $12, %esi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $12, %edx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leal 15(%rbp), %eax
shrl $4, %eax
movl %eax, 44(%rsp)
leal 15(%r12), %eax
shrl $4, %eax
movl %eax, 48(%rsp)
movl $16, 32(%rsp)
movl $16, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 24(%rsp), %rcx
movss 12(%rsp), %xmm3
movss 8(%rsp), %xmm2
movss 4(%rsp), %xmm1
movss (%rsp), %xmm0
movl %r12d, %edx
movl %ebp, %esi
movq 16(%rsp), %rdi
call _Z40__device_stub__Z12recMapKernelPfiiffffS_PfiiffffS_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size recMapApply, .-recMapApply
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12recMapKernelPfiiffffS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12recMapKernelPfiiffffS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "rec_map.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__recMapKernelPfiiffffS_ # -- Begin function _Z27__device_stub__recMapKernelPfiiffffS_
.p2align 4, 0x90
.type _Z27__device_stub__recMapKernelPfiiffffS_,@function
_Z27__device_stub__recMapKernelPfiiffffS_: # @_Z27__device_stub__recMapKernelPfiiffffS_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movl %esi, 28(%rsp)
movl %edx, 24(%rsp)
movss %xmm0, 20(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 12(%rsp)
movss %xmm3, 8(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 28(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12recMapKernelPfiiffffS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z27__device_stub__recMapKernelPfiiffffS_, .Lfunc_end0-_Z27__device_stub__recMapKernelPfiiffffS_
.cfi_endproc
# -- End function
.globl recMapApply # -- Begin function recMapApply
.p2align 4, 0x90
.type recMapApply,@function
recMapApply: # @recMapApply
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $192, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %r13
movss %xmm3, 36(%rsp) # 4-byte Spill
movss %xmm2, 32(%rsp) # 4-byte Spill
movss %xmm1, 28(%rsp) # 4-byte Spill
movss %xmm0, 24(%rsp) # 4-byte Spill
movl %edx, %r15d
movl %esi, %r12d
movq %rdi, %rbx
movl %esi, %eax
imull %edx, %eax
shll $2, %eax
leal (%rax,%rax,2), %eax
movq $0, 8(%rsp)
movslq %eax, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movl $12, %esi
callq hipMalloc
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $12, %edx
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
leal 15(%r12), %eax
shrl $4, %eax
leal 15(%r15), %edi
shrl $4, %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 120(%rsp)
movl %r12d, 60(%rsp)
movl %r15d, 56(%rsp)
movss 24(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 52(%rsp)
movss 28(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 48(%rsp)
movss 32(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 44(%rsp)
movss 36(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 40(%rsp)
movq %rcx, 112(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 60(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rax
movq %rax, 144(%rsp)
leaq 52(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rax
movq %rax, 160(%rsp)
leaq 44(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 112(%rsp), %rax
movq %rax, 184(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z12recMapKernelPfiiffffS_, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
addq $192, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size recMapApply, .Lfunc_end1-recMapApply
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12recMapKernelPfiiffffS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12recMapKernelPfiiffffS_,@object # @_Z12recMapKernelPfiiffffS_
.section .rodata,"a",@progbits
.globl _Z12recMapKernelPfiiffffS_
.p2align 3, 0x0
_Z12recMapKernelPfiiffffS_:
.quad _Z27__device_stub__recMapKernelPfiiffffS_
.size _Z12recMapKernelPfiiffffS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12recMapKernelPfiiffffS_"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__recMapKernelPfiiffffS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12recMapKernelPfiiffffS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
============================================================================
Name : ThrustPrime.cu
Author : Stephen Mathews
Version :
Copyright : Your copyright notice
Description : Compute sum of reciprocals using STL on CPU and Thrust on GPU
============================================================================
*/
#include <algorithm>
#include <iostream>
#include <numeric>
#include <vector>
#include <thrust/reduce.h>
#include <thrust/device_vector.h>
template <typename T> __host__ __device__ T is_primo(const T &x)
{
if( x == 2 ) return 1;
for( int i=2; i <= ((x/2)+1); i++)
if( (x % i) == 0 )
return 0;
return 1;
}
template <typename T> class ReciprocalFunctor {
public:
__host__ __device__ T operator()(const T &x) {
return is_primo(x);
}
};
template <typename T, class OpClass> T transformAndSumCPU(std::vector<T> data, OpClass op)
{
std::vector<T> temp(data.size());
std::transform(data.begin(), data.end(), temp.begin(), op);
return std::accumulate(temp.begin(), temp.end(), (T)0);
}
template <typename T, class OpClass> T transformAndSumGPU(std::vector<T> data, OpClass op)
{
thrust::device_vector<T> temp(data.begin(), data.end());
thrust::transform(temp.begin(), temp.end(), temp.begin(), op);
return thrust::reduce(temp.begin(), temp.end());
}
template<typename T> void initialize(std::vector<T> &data, T workStart, T workEnd)
{
/* Initialize the vector */
for (unsigned i = workStart; i <= workEnd; i++)
data.push_back( i );
}
template<typename T> void doCompute(T workStart, T workEnd )
{
std::vector<T> hostData;
initialize(hostData, workStart, workEnd );
T gpuResults = transformAndSumGPU(hostData, ReciprocalFunctor<T>());
std::cout<<"transformAndSumGPU = "<<gpuResults<<std::endl << std::flush;
T cpuResults = transformAndSumCPU(hostData, ReciprocalFunctor<T>());
std::cout<<"transformAndSumCPU = "<<cpuResults<<std::endl << std::flush;
}
int main(int argc, char** argv)
{
int max = 100000;
if( argc > 1 )
max = atoi( argv[1] );
doCompute<int> ( 2, max );
return 0;
} | /*
============================================================================
Name : ThrustPrime.cu
Author : Stephen Mathews
Version :
Copyright : Your copyright notice
Description : Compute sum of reciprocals using STL on CPU and Thrust on GPU
============================================================================
*/
#include <hip/hip_runtime.h>
#include <algorithm>
#include <iostream>
#include <numeric>
#include <vector>
#include <thrust/reduce.h>
#include <thrust/device_vector.h>
template <typename T> __host__ __device__ T is_primo(const T &x)
{
if( x == 2 ) return 1;
for( int i=2; i <= ((x/2)+1); i++)
if( (x % i) == 0 )
return 0;
return 1;
}
template <typename T> class ReciprocalFunctor {
public:
__host__ __device__ T operator()(const T &x) {
return is_primo(x);
}
};
template <typename T, class OpClass> T transformAndSumCPU(std::vector<T> data, OpClass op)
{
std::vector<T> temp(data.size());
std::transform(data.begin(), data.end(), temp.begin(), op);
return std::accumulate(temp.begin(), temp.end(), (T)0);
}
template <typename T, class OpClass> T transformAndSumGPU(std::vector<T> data, OpClass op)
{
thrust::device_vector<T> temp(data.begin(), data.end());
thrust::transform(temp.begin(), temp.end(), temp.begin(), op);
return thrust::reduce(temp.begin(), temp.end());
}
template<typename T> void initialize(std::vector<T> &data, T workStart, T workEnd)
{
/* Initialize the vector */
for (unsigned i = workStart; i <= workEnd; i++)
data.push_back( i );
}
template<typename T> void doCompute(T workStart, T workEnd )
{
std::vector<T> hostData;
initialize(hostData, workStart, workEnd );
T gpuResults = transformAndSumGPU(hostData, ReciprocalFunctor<T>());
std::cout<<"transformAndSumGPU = "<<gpuResults<<std::endl << std::flush;
T cpuResults = transformAndSumCPU(hostData, ReciprocalFunctor<T>());
std::cout<<"transformAndSumCPU = "<<cpuResults<<std::endl << std::flush;
}
int main(int argc, char** argv)
{
int max = 100000;
if( argc > 1 )
max = atoi( argv[1] );
doCompute<int> ( 2, max );
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
///////////////////////////////////////////////////////////////////////////////
//Round a / b to nearest higher integer value
__global__ void updateHeightmapKernel(float* heightMap, float2* ht, unsigned int width){
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
unsigned int i = y*width+x;
float sign_correction = ((x + y) & 0x01) ? -1.0f : 1.0f;
heightMap[i] = ht[i].x * sign_correction;
} | code for sm_80
Function : _Z21updateHeightmapKernelPfP6float2j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0040*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0050*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe200078e0203 */
/*0070*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fe200000001ff */
/*0080*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x002fc800078e0202 */
/*0090*/ IMAD R4, R5, c[0x0][0x170], R0 ; /* 0x00005c0005047a24 */
/* 0x000fca00078e0200 */
/*00a0*/ IMAD.WIDE.U32 R2, R4, R3, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0003 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IADD3 R0, R0, R5, RZ ; /* 0x0000000500007210 */
/* 0x000fe20007ffe0ff */
/*00d0*/ HFMA2.MMA R5, -RZ, RZ, 1.875, 0 ; /* 0x3f800000ff057435 */
/* 0x000fe200000001ff */
/*00e0*/ MOV R7, 0x4 ; /* 0x0000000400077802 */
/* 0x000fe40000000f00 */
/*00f0*/ LOP3.LUT R0, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100007812 */
/* 0x000fc800078ec0ff */
/*0100*/ ISETP.NE.U32.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc80003f05070 */
/*0110*/ FSEL R0, -R5, 1, !P0 ; /* 0x3f80000005007808 */
/* 0x000fe20004000100 */
/*0120*/ IMAD.WIDE.U32 R4, R4, R7, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0007 */
/*0130*/ FMUL R7, R0, R3 ; /* 0x0000000300077220 */
/* 0x004fca0000400000 */
/*0140*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
///////////////////////////////////////////////////////////////////////////////
//Round a / b to nearest higher integer value
__global__ void updateHeightmapKernel(float* heightMap, float2* ht, unsigned int width){
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
unsigned int i = y*width+x;
float sign_correction = ((x + y) & 0x01) ? -1.0f : 1.0f;
heightMap[i] = ht[i].x * sign_correction;
} | .file "tmpxft_001bd187_00000000-6_updateHeightmapKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z21updateHeightmapKernelPfP6float2jPfP6float2j
.type _Z50__device_stub__Z21updateHeightmapKernelPfP6float2jPfP6float2j, @function
_Z50__device_stub__Z21updateHeightmapKernelPfP6float2jPfP6float2j:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21updateHeightmapKernelPfP6float2j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z21updateHeightmapKernelPfP6float2jPfP6float2j, .-_Z50__device_stub__Z21updateHeightmapKernelPfP6float2jPfP6float2j
.globl _Z21updateHeightmapKernelPfP6float2j
.type _Z21updateHeightmapKernelPfP6float2j, @function
_Z21updateHeightmapKernelPfP6float2j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z21updateHeightmapKernelPfP6float2jPfP6float2j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z21updateHeightmapKernelPfP6float2j, .-_Z21updateHeightmapKernelPfP6float2j
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z21updateHeightmapKernelPfP6float2j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21updateHeightmapKernelPfP6float2j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
///////////////////////////////////////////////////////////////////////////////
//Round a / b to nearest higher integer value
__global__ void updateHeightmapKernel(float* heightMap, float2* ht, unsigned int width){
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
unsigned int i = y*width+x;
float sign_correction = ((x + y) & 0x01) ? -1.0f : 1.0f;
heightMap[i] = ht[i].x * sign_correction;
} | #include <hip/hip_runtime.h>
#include "includes.h"
///////////////////////////////////////////////////////////////////////////////
//Round a / b to nearest higher integer value
__global__ void updateHeightmapKernel(float* heightMap, float2* ht, unsigned int width){
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
unsigned int i = y*width+x;
float sign_correction = ((x + y) & 0x01) ? -1.0f : 1.0f;
heightMap[i] = ht[i].x * sign_correction;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
///////////////////////////////////////////////////////////////////////////////
//Round a / b to nearest higher integer value
__global__ void updateHeightmapKernel(float* heightMap, float2* ht, unsigned int width){
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
unsigned int i = y*width+x;
float sign_correction = ((x + y) & 0x01) ? -1.0f : 1.0f;
heightMap[i] = ht[i].x * sign_correction;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj
.globl _Z21updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj
.p2align 8
.type _Z21updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj,@function
_Z21updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v3, s4, v[2:3]
v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v2, v3, v2
v_and_b32_e32 v2, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 3, v[0:1]
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v2
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cndmask_b32_e64 v2, -v4, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj, .Lfunc_end0-_Z21updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
///////////////////////////////////////////////////////////////////////////////
//Round a / b to nearest higher integer value
__global__ void updateHeightmapKernel(float* heightMap, float2* ht, unsigned int width){
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
unsigned int i = y*width+x;
float sign_correction = ((x + y) & 0x01) ? -1.0f : 1.0f;
heightMap[i] = ht[i].x * sign_correction;
} | .text
.file "updateHeightmapKernel.hip"
.globl _Z36__device_stub__updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj # -- Begin function _Z36__device_stub__updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj
.p2align 4, 0x90
.type _Z36__device_stub__updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj,@function
_Z36__device_stub__updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj: # @_Z36__device_stub__updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z36__device_stub__updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj, .Lfunc_end0-_Z36__device_stub__updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj,@object # @_Z21updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj
.section .rodata,"a",@progbits
.globl _Z21updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj
.p2align 3, 0x0
_Z21updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj:
.quad _Z36__device_stub__updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj
.size _Z21updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj"
.size .L__unnamed_1, 54
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z21updateHeightmapKernelPfP6float2j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0040*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0050*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe200078e0203 */
/*0070*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fe200000001ff */
/*0080*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x002fc800078e0202 */
/*0090*/ IMAD R4, R5, c[0x0][0x170], R0 ; /* 0x00005c0005047a24 */
/* 0x000fca00078e0200 */
/*00a0*/ IMAD.WIDE.U32 R2, R4, R3, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0003 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IADD3 R0, R0, R5, RZ ; /* 0x0000000500007210 */
/* 0x000fe20007ffe0ff */
/*00d0*/ HFMA2.MMA R5, -RZ, RZ, 1.875, 0 ; /* 0x3f800000ff057435 */
/* 0x000fe200000001ff */
/*00e0*/ MOV R7, 0x4 ; /* 0x0000000400077802 */
/* 0x000fe40000000f00 */
/*00f0*/ LOP3.LUT R0, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100007812 */
/* 0x000fc800078ec0ff */
/*0100*/ ISETP.NE.U32.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc80003f05070 */
/*0110*/ FSEL R0, -R5, 1, !P0 ; /* 0x3f80000005007808 */
/* 0x000fe20004000100 */
/*0120*/ IMAD.WIDE.U32 R4, R4, R7, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0007 */
/*0130*/ FMUL R7, R0, R3 ; /* 0x0000000300077220 */
/* 0x004fca0000400000 */
/*0140*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj
.globl _Z21updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj
.p2align 8
.type _Z21updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj,@function
_Z21updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v3, s4, v[2:3]
v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v2, v3, v2
v_and_b32_e32 v2, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 3, v[0:1]
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v2
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cndmask_b32_e64 v2, -v4, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj, .Lfunc_end0-_Z21updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001bd187_00000000-6_updateHeightmapKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z21updateHeightmapKernelPfP6float2jPfP6float2j
.type _Z50__device_stub__Z21updateHeightmapKernelPfP6float2jPfP6float2j, @function
_Z50__device_stub__Z21updateHeightmapKernelPfP6float2jPfP6float2j:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21updateHeightmapKernelPfP6float2j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z21updateHeightmapKernelPfP6float2jPfP6float2j, .-_Z50__device_stub__Z21updateHeightmapKernelPfP6float2jPfP6float2j
.globl _Z21updateHeightmapKernelPfP6float2j
.type _Z21updateHeightmapKernelPfP6float2j, @function
_Z21updateHeightmapKernelPfP6float2j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z21updateHeightmapKernelPfP6float2jPfP6float2j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z21updateHeightmapKernelPfP6float2j, .-_Z21updateHeightmapKernelPfP6float2j
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z21updateHeightmapKernelPfP6float2j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21updateHeightmapKernelPfP6float2j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "updateHeightmapKernel.hip"
.globl _Z36__device_stub__updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj # -- Begin function _Z36__device_stub__updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj
.p2align 4, 0x90
.type _Z36__device_stub__updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj,@function
_Z36__device_stub__updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj: # @_Z36__device_stub__updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z36__device_stub__updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj, .Lfunc_end0-_Z36__device_stub__updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj,@object # @_Z21updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj
.section .rodata,"a",@progbits
.globl _Z21updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj
.p2align 3, 0x0
_Z21updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj:
.quad _Z36__device_stub__updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj
.size _Z21updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj"
.size .L__unnamed_1, 54
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21updateHeightmapKernelPfP15HIP_vector_typeIfLj2EEj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void
apply_rows_max(float* X, /** matrix to apply .. row major **/
float* y, /** result vector **/
int* iy,
int rows,
int cols
) {
unsigned int thidx = threadIdx.x;
unsigned int thidy = threadIdx.y;
unsigned int bid = blockIdx.x;
unsigned int bdx = blockDim.x; // assumed equal to blockDim.y .. 16 or 32 ..
unsigned int stride = bdx + 1; // shared mem padded for bank conflicts
unsigned int currow = bdx*bid;
// flexible block size
extern __shared__ float shared_data[];
float *sh_max = shared_data + bdx*stride;
// if( thidy == 0 && thidx + currow < rows ){
// sh_max[thidx] = -1e37;
// }
// __syncthreads();
float cur_val; float new_val; int argmax=0;
for(int chunk = 0; chunk < cols; chunk+=bdx){
// get some values chunking accross rows ...
if(currow+thidy < rows && chunk + thidx < cols){
shared_data[thidx*stride + thidy] = X[(currow + thidy)*cols + chunk + thidx];}
__syncthreads();
// get maximum in chunk ...
if( thidy == 0 && thidx + currow < rows ){
// if first val, it's the max
if( chunk==0 ){
sh_max[thidx] = shared_data[thidx];
}
// get maximmum in chunk ...
for( int i = 0; i < bdx; i++){
if(chunk + i < cols){
cur_val = sh_max[thidx];
new_val = shared_data[i*stride + thidx];
if( cur_val < new_val ){
sh_max[thidx] = new_val;
argmax = chunk + i;
}
}
}
}
__syncthreads();
}
// save values
if(thidx + currow < rows && thidy==0){
y[currow+thidx] = sh_max[thidx];
iy[currow+thidx] = argmax;
}
} | code for sm_80
Function : _Z14apply_rows_maxPfS_Piii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe20003f01270 */
/*0030*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff067624 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e660000002200 */
/*0060*/ IADD3 R7, R6, 0x1, RZ ; /* 0x0000000106077810 */
/* 0x000fe20007ffe0ff */
/*0070*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000eac0000002500 */
/*0080*/ @!P0 IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff008224 */
/* 0x000fc400078e00ff */
/*0090*/ IMAD R4, R7, c[0x0][0x0], R2 ; /* 0x0000000007047a24 */
/* 0x001fe200078e0202 */
/*00a0*/ @!P0 BRA 0x880 ; /* 0x000007d000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IMAD R0, R5, c[0x0][0x0], R2 ; /* 0x0000000005007a24 */
/* 0x004fe200078e0202 */
/*00c0*/ IADD3 R8, R6.reuse, -0x1, RZ ; /* 0xffffffff06087810 */
/* 0x040fe20007ffe0ff */
/*00d0*/ IMAD R9, R7, R2, R3.reuse ; /* 0x0000000207097224 */
/* 0x102fe200078e0203 */
/*00e0*/ LOP3.LUT R6, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306067812 */
/* 0x000fe200078ec0ff */
/*00f0*/ IMAD.SHL.U32 R10, R2, 0x4, RZ ; /* 0x00000004020a7824 */
/* 0x000fe200078e00ff */
/*0100*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06070 */
/*0110*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*0120*/ ISETP.GE.U32.AND P2, PT, R8, 0x3, PT ; /* 0x000000030800780c */
/* 0x000fe20003f46070 */
/*0130*/ IMAD R8, R5, c[0x0][0x0], R3 ; /* 0x0000000005087a24 */
/* 0x000fe200078e0203 */
/*0140*/ ISETP.EQ.AND P0, PT, R3, RZ, !P0 ; /* 0x000000ff0300720c */
/* 0x000fe20004702270 */
/*0150*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0160*/ IADD3 R12, -R6, c[0x0][0x0], RZ ; /* 0x00000000060c7a10 */
/* 0x000fc40007ffe1ff */
/*0170*/ IMAD.IADD R13, R2, 0x1, R11 ; /* 0x00000001020d7824 */
/* 0x001fe200078e020b */
/*0180*/ BSSY B0, 0x220 ; /* 0x0000009000007945 */
/* 0x000fe80003800000 */
/*0190*/ ISETP.GE.U32.AND P1, PT, R13, c[0x0][0x17c], PT ; /* 0x00005f000d007a0c */
/* 0x000fc80003f26070 */
/*01a0*/ ISETP.GE.U32.OR P1, PT, R8, c[0x0][0x178], P1 ; /* 0x00005e0008007a0c */
/* 0x000fda0000f26470 */
/*01b0*/ @P1 BRA 0x210 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*01c0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fe400078e00ff */
/*01d0*/ IMAD R14, R8, c[0x0][0x17c], R13 ; /* 0x00005f00080e7a24 */
/* 0x000fc800078e020d */
/*01e0*/ IMAD.WIDE.U32 R14, R14, R15, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fcc00078e000f */
/*01f0*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ea8000c1e1900 */
/*0200*/ STS [R9.X4], R14 ; /* 0x0000000e09007388 */
/* 0x0041e40000004800 */
/*0210*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0220*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0230*/ BSSY B0, 0x840 ; /* 0x0000060000007945 */
/* 0x000fe20003800000 */
/*0240*/ @!P0 BRA 0x830 ; /* 0x000005e000008947 */
/* 0x000fea0003800000 */
/*0250*/ ISETP.NE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fda0003f25270 */
/*0260*/ @!P1 LDS R13, [R2.X4] ; /* 0x00000000020d9984 */
/* 0x000e680000004800 */
/*0270*/ @!P1 STS [R4.X4], R13 ; /* 0x0000000d04009388 */
/* 0x0023e20000004800 */
/*0280*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fda0003f25270 */
/*0290*/ @!P1 BRA 0x830 ; /* 0x0000059000009947 */
/* 0x000fea0003800000 */
/*02a0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x002fe20008000000 */
/*02b0*/ @!P2 BRA 0x5d0 ; /* 0x000003100000a947 */
/* 0x000fea0003800000 */
/*02c0*/ IMAD.MOV.U32 R13, RZ, RZ, R12 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e000c */
/*02d0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*02e0*/ IADD3 R17, R11, UR4, RZ ; /* 0x000000040b117c10 */
/* 0x000fe2000fffe0ff */
/*02f0*/ UIADD3 UR5, UR4, 0x1, URZ ; /* 0x0000000104057890 */
/* 0x000fe2000fffe03f */
/*0300*/ IADD3 R13, R13, -0x4, RZ ; /* 0xfffffffc0d0d7810 */
/* 0x000fe20007ffe0ff */
/*0310*/ UIADD3 UR8, UR4, 0x2, URZ ; /* 0x0000000204087890 */
/* 0x000fe2000fffe03f */
/*0320*/ ISETP.GE.AND P6, PT, R17, c[0x0][0x17c], PT ; /* 0x00005f0011007a0c */
/* 0x000fe20003fc6270 */
/*0330*/ UIADD3 UR9, UR4, 0x3, URZ ; /* 0x0000000304097890 */
/* 0x000fe2000fffe03f */
/*0340*/ ISETP.NE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe40003f25270 */
/*0350*/ IADD3 R18, R11, UR5, RZ ; /* 0x000000050b127c10 */
/* 0x000fc4000fffe0ff */
/*0360*/ IADD3 R19, R11.reuse, UR8, RZ ; /* 0x000000080b137c10 */
/* 0x040fe4000fffe0ff */
/*0370*/ IADD3 R16, R11, UR9, RZ ; /* 0x000000090b107c10 */
/* 0x000fe4000fffe0ff */
/*0380*/ ISETP.GE.AND P3, PT, R18, c[0x0][0x17c], PT ; /* 0x00005f0012007a0c */
/* 0x000fe40003f66270 */
/*0390*/ ISETP.GE.AND P4, PT, R19, c[0x0][0x17c], PT ; /* 0x00005f0013007a0c */
/* 0x000fe40003f86270 */
/*03a0*/ ISETP.GE.AND P5, PT, R16, c[0x0][0x17c], PT ; /* 0x00005f0010007a0c */
/* 0x000fe20003fa6270 */
/*03b0*/ @P6 BRA 0x430 ; /* 0x0000007000006947 */
/* 0x001ff00003800000 */
/*03c0*/ IMAD R15, R7, UR4, RZ ; /* 0x00000004070f7c24 */
/* 0x000fe2000f8e02ff */
/*03d0*/ LDS R14, [R4.X4] ; /* 0x00000000040e7984 */
/* 0x001fe60000004800 */
/*03e0*/ IMAD R15, R15, 0x4, R10 ; /* 0x000000040f0f7824 */
/* 0x000fcc00078e020a */
/*03f0*/ LDS R15, [R15] ; /* 0x000000000f0f7984 */
/* 0x000e240000000800 */
/*0400*/ FSETP.GEU.AND P6, PT, R14, R15, PT ; /* 0x0000000f0e00720b */
/* 0x001fda0003fce000 */
/*0410*/ @!P6 STS [R4.X4], R15 ; /* 0x0000000f0400e388 */
/* 0x0001e20000004800 */
/*0420*/ @!P6 IMAD.MOV.U32 R0, RZ, RZ, R17 ; /* 0x000000ffff00e224 */
/* 0x000fc600078e0011 */
/*0430*/ @P3 BRA 0x4b0 ; /* 0x0000007000003947 */
/* 0x000fea0003800000 */
/*0440*/ IMAD R15, R7, UR5, RZ ; /* 0x00000005070f7c24 */
/* 0x001fe2000f8e02ff */
/*0450*/ LDS R14, [R4.X4] ; /* 0x00000000040e7984 */
/* 0x000fe60000004800 */
/*0460*/ IMAD R15, R15, 0x4, R10 ; /* 0x000000040f0f7824 */
/* 0x000fcc00078e020a */
/*0470*/ LDS R15, [R15] ; /* 0x000000000f0f7984 */
/* 0x000e240000000800 */
/*0480*/ FSETP.GEU.AND P3, PT, R14, R15, PT ; /* 0x0000000f0e00720b */
/* 0x001fda0003f6e000 */
/*0490*/ @!P3 STS [R4.X4], R15 ; /* 0x0000000f0400b388 */
/* 0x0001e20000004800 */
/*04a0*/ @!P3 IMAD.MOV.U32 R0, RZ, RZ, R18 ; /* 0x000000ffff00b224 */
/* 0x000fc600078e0012 */
/*04b0*/ @P4 BRA 0x530 ; /* 0x0000007000004947 */
/* 0x000fea0003800000 */
/*04c0*/ IMAD R15, R7, UR8, RZ ; /* 0x00000008070f7c24 */
/* 0x001fe2000f8e02ff */
/*04d0*/ LDS R14, [R4.X4] ; /* 0x00000000040e7984 */
/* 0x000fe60000004800 */
/*04e0*/ IMAD R15, R15, 0x4, R10 ; /* 0x000000040f0f7824 */
/* 0x000fcc00078e020a */
/*04f0*/ LDS R15, [R15] ; /* 0x000000000f0f7984 */
/* 0x000e240000000800 */
/*0500*/ FSETP.GEU.AND P3, PT, R14, R15, PT ; /* 0x0000000f0e00720b */
/* 0x001fda0003f6e000 */
/*0510*/ @!P3 STS [R4.X4], R15 ; /* 0x0000000f0400b388 */
/* 0x0001e20000004800 */
/*0520*/ @!P3 IMAD.MOV.U32 R0, RZ, RZ, R19 ; /* 0x000000ffff00b224 */
/* 0x000fc600078e0013 */
/*0530*/ @P5 BRA 0x5b0 ; /* 0x0000007000005947 */
/* 0x000fea0003800000 */
/*0540*/ IMAD R15, R7, UR9, RZ ; /* 0x00000009070f7c24 */
/* 0x001fe2000f8e02ff */
/*0550*/ LDS R14, [R4.X4] ; /* 0x00000000040e7984 */
/* 0x000fe60000004800 */
/*0560*/ IMAD R15, R15, 0x4, R10 ; /* 0x000000040f0f7824 */
/* 0x000fcc00078e020a */
/*0570*/ LDS R15, [R15] ; /* 0x000000000f0f7984 */
/* 0x000e240000000800 */
/*0580*/ FSETP.GEU.AND P3, PT, R14, R15, PT ; /* 0x0000000f0e00720b */
/* 0x001fda0003f6e000 */
/*0590*/ @!P3 STS [R4.X4], R15 ; /* 0x0000000f0400b388 */
/* 0x0001e20000004800 */
/*05a0*/ @!P3 IMAD.MOV.U32 R0, RZ, RZ, R16 ; /* 0x000000ffff00b224 */
/* 0x000fc600078e0010 */
/*05b0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*05c0*/ @P1 BRA 0x2e0 ; /* 0xfffffd1000001947 */
/* 0x000fea000383ffff */
/*05d0*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f25270 */
/*05e0*/ @!P1 BRA 0x830 ; /* 0x0000024000009947 */
/* 0x000fea0003800000 */
/*05f0*/ IADD3 R15, R11, UR4, RZ ; /* 0x000000040b0f7c10 */
/* 0x001fe4000fffe0ff */
/*0600*/ ISETP.NE.AND P3, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe40003f65270 */
/*0610*/ ISETP.GE.AND P1, PT, R15, c[0x0][0x17c], PT ; /* 0x00005f000f007a0c */
/* 0x000fda0003f26270 */
/*0620*/ @P1 BRA 0x6a0 ; /* 0x0000007000001947 */
/* 0x000fea0003800000 */
/*0630*/ IMAD R13, R7, UR4, RZ ; /* 0x00000004070d7c24 */
/* 0x000fe2000f8e02ff */
/*0640*/ LDS R14, [R4.X4] ; /* 0x00000000040e7984 */
/* 0x000fe60000004800 */
/*0650*/ IMAD R13, R13, 0x4, R10 ; /* 0x000000040d0d7824 */
/* 0x000fcc00078e020a */
/*0660*/ LDS R13, [R13] ; /* 0x000000000d0d7984 */
/* 0x000e240000000800 */
/*0670*/ FSETP.GEU.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720b */
/* 0x001fda0003f2e000 */
/*0680*/ @!P1 STS [R4.X4], R13 ; /* 0x0000000d04009388 */
/* 0x0001e20000004800 */
/*0690*/ @!P1 IMAD.MOV.U32 R0, RZ, RZ, R15 ; /* 0x000000ffff009224 */
/* 0x000fc600078e000f */
/*06a0*/ @!P3 BRA 0x830 ; /* 0x000001800000b947 */
/* 0x000fea0003800000 */
/*06b0*/ UIADD3 UR5, UR4, 0x1, URZ ; /* 0x0000000104057890 */
/* 0x000fe2000fffe03f */
/*06c0*/ ISETP.NE.AND P3, PT, R6, 0x2, PT ; /* 0x000000020600780c */
/* 0x000fca0003f65270 */
/*06d0*/ IADD3 R15, R11, UR5, RZ ; /* 0x000000050b0f7c10 */
/* 0x000fc8000fffe0ff */
/*06e0*/ ISETP.GE.AND P1, PT, R15, c[0x0][0x17c], PT ; /* 0x00005f000f007a0c */
/* 0x000fda0003f26270 */
/*06f0*/ @P1 BRA 0x770 ; /* 0x0000007000001947 */
/* 0x000fea0003800000 */
/*0700*/ IMAD R13, R7, UR5, RZ ; /* 0x00000005070d7c24 */
/* 0x001fe2000f8e02ff */
/*0710*/ LDS R14, [R4.X4] ; /* 0x00000000040e7984 */
/* 0x000fe60000004800 */
/*0720*/ IMAD R13, R13, 0x4, R10 ; /* 0x000000040d0d7824 */
/* 0x000fcc00078e020a */
/*0730*/ LDS R13, [R13] ; /* 0x000000000d0d7984 */
/* 0x000e240000000800 */
/*0740*/ FSETP.GEU.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720b */
/* 0x001fda0003f2e000 */
/*0750*/ @!P1 STS [R4.X4], R13 ; /* 0x0000000d04009388 */
/* 0x0001e20000004800 */
/*0760*/ @!P1 IMAD.MOV.U32 R0, RZ, RZ, R15 ; /* 0x000000ffff009224 */
/* 0x000fc600078e000f */
/*0770*/ @!P3 BRA 0x830 ; /* 0x000000b00000b947 */
/* 0x000fea0003800000 */
/*0780*/ UIADD3 UR4, UR4, 0x2, URZ ; /* 0x0000000204047890 */
/* 0x000fcc000fffe03f */
/*0790*/ IADD3 R15, R11, UR4, RZ ; /* 0x000000040b0f7c10 */
/* 0x000fc8000fffe0ff */
/*07a0*/ ISETP.GE.AND P1, PT, R15, c[0x0][0x17c], PT ; /* 0x00005f000f007a0c */
/* 0x000fda0003f26270 */
/*07b0*/ @P1 BRA 0x830 ; /* 0x0000007000001947 */
/* 0x000fea0003800000 */
/*07c0*/ IMAD R13, R7, UR4, RZ ; /* 0x00000004070d7c24 */
/* 0x001fe2000f8e02ff */
/*07d0*/ LDS R14, [R4.X4] ; /* 0x00000000040e7984 */
/* 0x000fe60000004800 */
/*07e0*/ IMAD R13, R13, 0x4, R10 ; /* 0x000000040d0d7824 */
/* 0x000fcc00078e020a */
/*07f0*/ LDS R13, [R13] ; /* 0x000000000d0d7984 */
/* 0x000e240000000800 */
/*0800*/ FSETP.GEU.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720b */
/* 0x001fda0003f2e000 */
/*0810*/ @!P1 STS [R4.X4], R13 ; /* 0x0000000d04009388 */
/* 0x0001e20000004800 */
/*0820*/ @!P1 IMAD.MOV.U32 R0, RZ, RZ, R15 ; /* 0x000000ffff009224 */
/* 0x000fc600078e000f */
/*0830*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0840*/ IADD3 R11, R11, c[0x0][0x0], RZ ; /* 0x000000000b0b7a10 */
/* 0x000fe20007ffe0ff */
/*0850*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0860*/ ISETP.GE.AND P1, PT, R11, c[0x0][0x17c], PT ; /* 0x00005f000b007a0c */
/* 0x000fda0003f26270 */
/*0870*/ @!P1 BRA 0x170 ; /* 0xfffff8f000009947 */
/* 0x000fea000383ffff */
/*0880*/ IMAD R6, R5, c[0x0][0x0], R2 ; /* 0x0000000005067a24 */
/* 0x004fca00078e0202 */
/*0890*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fc80003f06070 */
/*08a0*/ ISETP.NE.OR P0, PT, R3, RZ, P0 ; /* 0x000000ff0300720c */
/* 0x002fda0000705670 */
/*08b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*08c0*/ LDS R5, [R4.X4] ; /* 0x0000000004057984 */
/* 0x000e620000004800 */
/*08d0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc800078e00ff */
/*08e0*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fc800078e0007 */
/*08f0*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0007 */
/*0900*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe8000c101906 */
/*0910*/ STG.E [R6.64], R0 ; /* 0x0000000006007986 */
/* 0x000fe2000c101906 */
/*0920*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0930*/ BRA 0x930; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void
apply_rows_max(float* X, /** matrix to apply .. row major **/
float* y, /** result vector **/
int* iy,
int rows,
int cols
) {
unsigned int thidx = threadIdx.x;
unsigned int thidy = threadIdx.y;
unsigned int bid = blockIdx.x;
unsigned int bdx = blockDim.x; // assumed equal to blockDim.y .. 16 or 32 ..
unsigned int stride = bdx + 1; // shared mem padded for bank conflicts
unsigned int currow = bdx*bid;
// flexible block size
extern __shared__ float shared_data[];
float *sh_max = shared_data + bdx*stride;
// if( thidy == 0 && thidx + currow < rows ){
// sh_max[thidx] = -1e37;
// }
// __syncthreads();
float cur_val; float new_val; int argmax=0;
for(int chunk = 0; chunk < cols; chunk+=bdx){
// get some values chunking accross rows ...
if(currow+thidy < rows && chunk + thidx < cols){
shared_data[thidx*stride + thidy] = X[(currow + thidy)*cols + chunk + thidx];}
__syncthreads();
// get maximum in chunk ...
if( thidy == 0 && thidx + currow < rows ){
// if first val, it's the max
if( chunk==0 ){
sh_max[thidx] = shared_data[thidx];
}
// get maximmum in chunk ...
for( int i = 0; i < bdx; i++){
if(chunk + i < cols){
cur_val = sh_max[thidx];
new_val = shared_data[i*stride + thidx];
if( cur_val < new_val ){
sh_max[thidx] = new_val;
argmax = chunk + i;
}
}
}
}
__syncthreads();
}
// save values
if(thidx + currow < rows && thidy==0){
y[currow+thidx] = sh_max[thidx];
iy[currow+thidx] = argmax;
}
} | .file "tmpxft_00193e38_00000000-6_apply_rows_max.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z14apply_rows_maxPfS_PiiiPfS_Piii
.type _Z40__device_stub__Z14apply_rows_maxPfS_PiiiPfS_Piii, @function
_Z40__device_stub__Z14apply_rows_maxPfS_PiiiPfS_Piii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14apply_rows_maxPfS_Piii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z14apply_rows_maxPfS_PiiiPfS_Piii, .-_Z40__device_stub__Z14apply_rows_maxPfS_PiiiPfS_Piii
.globl _Z14apply_rows_maxPfS_Piii
.type _Z14apply_rows_maxPfS_Piii, @function
_Z14apply_rows_maxPfS_Piii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z14apply_rows_maxPfS_PiiiPfS_Piii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14apply_rows_maxPfS_Piii, .-_Z14apply_rows_maxPfS_Piii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14apply_rows_maxPfS_Piii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14apply_rows_maxPfS_Piii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void
apply_rows_max(float* X, /** matrix to apply .. row major **/
float* y, /** result vector **/
int* iy,
int rows,
int cols
) {
unsigned int thidx = threadIdx.x;
unsigned int thidy = threadIdx.y;
unsigned int bid = blockIdx.x;
unsigned int bdx = blockDim.x; // assumed equal to blockDim.y .. 16 or 32 ..
unsigned int stride = bdx + 1; // shared mem padded for bank conflicts
unsigned int currow = bdx*bid;
// flexible block size
extern __shared__ float shared_data[];
float *sh_max = shared_data + bdx*stride;
// if( thidy == 0 && thidx + currow < rows ){
// sh_max[thidx] = -1e37;
// }
// __syncthreads();
float cur_val; float new_val; int argmax=0;
for(int chunk = 0; chunk < cols; chunk+=bdx){
// get some values chunking accross rows ...
if(currow+thidy < rows && chunk + thidx < cols){
shared_data[thidx*stride + thidy] = X[(currow + thidy)*cols + chunk + thidx];}
__syncthreads();
// get maximum in chunk ...
if( thidy == 0 && thidx + currow < rows ){
// if first val, it's the max
if( chunk==0 ){
sh_max[thidx] = shared_data[thidx];
}
// get maximmum in chunk ...
for( int i = 0; i < bdx; i++){
if(chunk + i < cols){
cur_val = sh_max[thidx];
new_val = shared_data[i*stride + thidx];
if( cur_val < new_val ){
sh_max[thidx] = new_val;
argmax = chunk + i;
}
}
}
}
__syncthreads();
}
// save values
if(thidx + currow < rows && thidy==0){
y[currow+thidx] = sh_max[thidx];
iy[currow+thidx] = argmax;
}
} | #include <hip/hip_runtime.h>
__global__ void
apply_rows_max(float* X, /** matrix to apply .. row major **/
float* y, /** result vector **/
int* iy,
int rows,
int cols
) {
unsigned int thidx = threadIdx.x;
unsigned int thidy = threadIdx.y;
unsigned int bid = blockIdx.x;
unsigned int bdx = blockDim.x; // assumed equal to blockDim.y .. 16 or 32 ..
unsigned int stride = bdx + 1; // shared mem padded for bank conflicts
unsigned int currow = bdx*bid;
// flexible block size
extern __shared__ float shared_data[];
float *sh_max = shared_data + bdx*stride;
// if( thidy == 0 && thidx + currow < rows ){
// sh_max[thidx] = -1e37;
// }
// __syncthreads();
float cur_val; float new_val; int argmax=0;
for(int chunk = 0; chunk < cols; chunk+=bdx){
// get some values chunking accross rows ...
if(currow+thidy < rows && chunk + thidx < cols){
shared_data[thidx*stride + thidy] = X[(currow + thidy)*cols + chunk + thidx];}
__syncthreads();
// get maximum in chunk ...
if( thidy == 0 && thidx + currow < rows ){
// if first val, it's the max
if( chunk==0 ){
sh_max[thidx] = shared_data[thidx];
}
// get maximmum in chunk ...
for( int i = 0; i < bdx; i++){
if(chunk + i < cols){
cur_val = sh_max[thidx];
new_val = shared_data[i*stride + thidx];
if( cur_val < new_val ){
sh_max[thidx] = new_val;
argmax = chunk + i;
}
}
}
}
__syncthreads();
}
// save values
if(thidx + currow < rows && thidy==0){
y[currow+thidx] = sh_max[thidx];
iy[currow+thidx] = argmax;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void
apply_rows_max(float* X, /** matrix to apply .. row major **/
float* y, /** result vector **/
int* iy,
int rows,
int cols
) {
unsigned int thidx = threadIdx.x;
unsigned int thidy = threadIdx.y;
unsigned int bid = blockIdx.x;
unsigned int bdx = blockDim.x; // assumed equal to blockDim.y .. 16 or 32 ..
unsigned int stride = bdx + 1; // shared mem padded for bank conflicts
unsigned int currow = bdx*bid;
// flexible block size
extern __shared__ float shared_data[];
float *sh_max = shared_data + bdx*stride;
// if( thidy == 0 && thidx + currow < rows ){
// sh_max[thidx] = -1e37;
// }
// __syncthreads();
float cur_val; float new_val; int argmax=0;
for(int chunk = 0; chunk < cols; chunk+=bdx){
// get some values chunking accross rows ...
if(currow+thidy < rows && chunk + thidx < cols){
shared_data[thidx*stride + thidy] = X[(currow + thidy)*cols + chunk + thidx];}
__syncthreads();
// get maximum in chunk ...
if( thidy == 0 && thidx + currow < rows ){
// if first val, it's the max
if( chunk==0 ){
sh_max[thidx] = shared_data[thidx];
}
// get maximmum in chunk ...
for( int i = 0; i < bdx; i++){
if(chunk + i < cols){
cur_val = sh_max[thidx];
new_val = shared_data[i*stride + thidx];
if( cur_val < new_val ){
sh_max[thidx] = new_val;
argmax = chunk + i;
}
}
}
}
__syncthreads();
}
// save values
if(thidx + currow < rows && thidy==0){
y[currow+thidx] = sh_max[thidx];
iy[currow+thidx] = argmax;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14apply_rows_maxPfS_Piii
.globl _Z14apply_rows_maxPfS_Piii
.p2align 8
.type _Z14apply_rows_maxPfS_Piii,@function
_Z14apply_rows_maxPfS_Piii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v5, v0, 10, 10
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s9, 1
s_mul_i32 s15, s15, s9
s_mul_i32 s3, s2, s9
v_add_nc_u32_e32 v0, s15, v1
s_lshl_b32 s3, s3, 2
s_add_i32 s8, s3, 0
s_cmp_lt_i32 s5, 1
s_cbranch_scc1 .LBB0_15
s_load_b64 s[6:7], s[0:1], 0x0
v_add_nc_u32_e32 v4, s15, v5
v_cmp_eq_u32_e32 vcc_lo, 0, v5
v_cmp_gt_u32_e64 s3, s4, v0
v_mad_u32_u24 v6, s2, v1, v5
v_lshlrev_b32_e32 v9, 2, v1
v_mad_u64_u32 v[2:3], null, v4, s5, v[1:2]
s_delay_alu instid0(VALU_DEP_4)
s_and_b32 s3, vcc_lo, s3
s_cmp_lg_u32 s9, 0
v_cmp_gt_u32_e64 s2, s4, v4
v_lshl_add_u32 v7, v6, 2, 0
v_mov_b32_e32 v6, 0
v_add_nc_u32_e32 v8, 0, v9
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v9, s8, v9
s_cselect_b32 s11, -1, 0
s_lshl_b32 s12, s9, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s12, s12, 4
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s13
s_add_i32 s10, s10, s9
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s10, s5
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_16
.LBB0_3:
v_add_nc_u32_e32 v3, s10, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s5, v3
s_and_b32 s14, s2, vcc_lo
s_and_saveexec_b32 s13, s14
s_cbranch_execz .LBB0_5
v_add_nc_u32_e32 v3, s10, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v10, vcc_lo, s6, v10
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
global_load_b32 v3, v[10:11], off
s_waitcnt vmcnt(0)
ds_store_b32 v7, v3
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s13
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s13, s3
s_cbranch_execz .LBB0_2
s_cmp_lg_u32 s10, 0
s_cbranch_scc0 .LBB0_8
s_and_not1_b32 vcc_lo, exec_lo, s11
s_cbranch_vccz .LBB0_9
s_branch .LBB0_2
.LBB0_8:
ds_load_b32 v3, v8
s_waitcnt lgkmcnt(0)
ds_store_b32 v9, v3
s_and_not1_b32 vcc_lo, exec_lo, s11
s_cbranch_vccnz .LBB0_2
.LBB0_9:
v_mov_b32_e32 v3, v8
s_mov_b32 s14, 0
s_branch .LBB0_12
.p2align 6
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s16
.LBB0_11:
v_add_nc_u32_e32 v3, s12, v3
s_add_i32 s14, s14, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s9, s14
s_cbranch_scc0 .LBB0_2
.LBB0_12:
s_add_i32 s15, s10, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s15, s5
s_cbranch_scc1 .LBB0_11
ds_load_b32 v11, v9
ds_load_b32 v10, v3
s_mov_b32 s16, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_lt_f32_e32 v11, v10
s_cbranch_execz .LBB0_10
v_mov_b32_e32 v6, s15
ds_store_b32 v9, v10
s_branch .LBB0_10
.LBB0_15:
v_mov_b32_e32 v6, 0
.LBB0_16:
v_cmp_gt_u32_e32 vcc_lo, s4, v0
v_cmp_eq_u32_e64 s2, 0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_18
s_load_b128 s[0:3], s[0:1], 0x8
v_lshl_add_u32 v2, v1, 2, s8
v_mov_b32_e32 v1, 0
ds_load_b32 v4, v2
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[2:3], v4, off
global_store_b32 v[0:1], v6, off
.LBB0_18:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14apply_rows_maxPfS_Piii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14apply_rows_maxPfS_Piii, .Lfunc_end0-_Z14apply_rows_maxPfS_Piii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14apply_rows_maxPfS_Piii
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z14apply_rows_maxPfS_Piii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void
apply_rows_max(float* X, /** matrix to apply .. row major **/
float* y, /** result vector **/
int* iy,
int rows,
int cols
) {
unsigned int thidx = threadIdx.x;
unsigned int thidy = threadIdx.y;
unsigned int bid = blockIdx.x;
unsigned int bdx = blockDim.x; // assumed equal to blockDim.y .. 16 or 32 ..
unsigned int stride = bdx + 1; // shared mem padded for bank conflicts
unsigned int currow = bdx*bid;
// flexible block size
extern __shared__ float shared_data[];
float *sh_max = shared_data + bdx*stride;
// if( thidy == 0 && thidx + currow < rows ){
// sh_max[thidx] = -1e37;
// }
// __syncthreads();
float cur_val; float new_val; int argmax=0;
for(int chunk = 0; chunk < cols; chunk+=bdx){
// get some values chunking accross rows ...
if(currow+thidy < rows && chunk + thidx < cols){
shared_data[thidx*stride + thidy] = X[(currow + thidy)*cols + chunk + thidx];}
__syncthreads();
// get maximum in chunk ...
if( thidy == 0 && thidx + currow < rows ){
// if first val, it's the max
if( chunk==0 ){
sh_max[thidx] = shared_data[thidx];
}
// get maximmum in chunk ...
for( int i = 0; i < bdx; i++){
if(chunk + i < cols){
cur_val = sh_max[thidx];
new_val = shared_data[i*stride + thidx];
if( cur_val < new_val ){
sh_max[thidx] = new_val;
argmax = chunk + i;
}
}
}
}
__syncthreads();
}
// save values
if(thidx + currow < rows && thidy==0){
y[currow+thidx] = sh_max[thidx];
iy[currow+thidx] = argmax;
}
} | .text
.file "apply_rows_max.hip"
.globl _Z29__device_stub__apply_rows_maxPfS_Piii # -- Begin function _Z29__device_stub__apply_rows_maxPfS_Piii
.p2align 4, 0x90
.type _Z29__device_stub__apply_rows_maxPfS_Piii,@function
_Z29__device_stub__apply_rows_maxPfS_Piii: # @_Z29__device_stub__apply_rows_maxPfS_Piii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14apply_rows_maxPfS_Piii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__apply_rows_maxPfS_Piii, .Lfunc_end0-_Z29__device_stub__apply_rows_maxPfS_Piii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14apply_rows_maxPfS_Piii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14apply_rows_maxPfS_Piii,@object # @_Z14apply_rows_maxPfS_Piii
.section .rodata,"a",@progbits
.globl _Z14apply_rows_maxPfS_Piii
.p2align 3, 0x0
_Z14apply_rows_maxPfS_Piii:
.quad _Z29__device_stub__apply_rows_maxPfS_Piii
.size _Z14apply_rows_maxPfS_Piii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14apply_rows_maxPfS_Piii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__apply_rows_maxPfS_Piii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14apply_rows_maxPfS_Piii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14apply_rows_maxPfS_Piii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe20003f01270 */
/*0030*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff067624 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e660000002200 */
/*0060*/ IADD3 R7, R6, 0x1, RZ ; /* 0x0000000106077810 */
/* 0x000fe20007ffe0ff */
/*0070*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000eac0000002500 */
/*0080*/ @!P0 IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff008224 */
/* 0x000fc400078e00ff */
/*0090*/ IMAD R4, R7, c[0x0][0x0], R2 ; /* 0x0000000007047a24 */
/* 0x001fe200078e0202 */
/*00a0*/ @!P0 BRA 0x880 ; /* 0x000007d000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IMAD R0, R5, c[0x0][0x0], R2 ; /* 0x0000000005007a24 */
/* 0x004fe200078e0202 */
/*00c0*/ IADD3 R8, R6.reuse, -0x1, RZ ; /* 0xffffffff06087810 */
/* 0x040fe20007ffe0ff */
/*00d0*/ IMAD R9, R7, R2, R3.reuse ; /* 0x0000000207097224 */
/* 0x102fe200078e0203 */
/*00e0*/ LOP3.LUT R6, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306067812 */
/* 0x000fe200078ec0ff */
/*00f0*/ IMAD.SHL.U32 R10, R2, 0x4, RZ ; /* 0x00000004020a7824 */
/* 0x000fe200078e00ff */
/*0100*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06070 */
/*0110*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*0120*/ ISETP.GE.U32.AND P2, PT, R8, 0x3, PT ; /* 0x000000030800780c */
/* 0x000fe20003f46070 */
/*0130*/ IMAD R8, R5, c[0x0][0x0], R3 ; /* 0x0000000005087a24 */
/* 0x000fe200078e0203 */
/*0140*/ ISETP.EQ.AND P0, PT, R3, RZ, !P0 ; /* 0x000000ff0300720c */
/* 0x000fe20004702270 */
/*0150*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0160*/ IADD3 R12, -R6, c[0x0][0x0], RZ ; /* 0x00000000060c7a10 */
/* 0x000fc40007ffe1ff */
/*0170*/ IMAD.IADD R13, R2, 0x1, R11 ; /* 0x00000001020d7824 */
/* 0x001fe200078e020b */
/*0180*/ BSSY B0, 0x220 ; /* 0x0000009000007945 */
/* 0x000fe80003800000 */
/*0190*/ ISETP.GE.U32.AND P1, PT, R13, c[0x0][0x17c], PT ; /* 0x00005f000d007a0c */
/* 0x000fc80003f26070 */
/*01a0*/ ISETP.GE.U32.OR P1, PT, R8, c[0x0][0x178], P1 ; /* 0x00005e0008007a0c */
/* 0x000fda0000f26470 */
/*01b0*/ @P1 BRA 0x210 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*01c0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fe400078e00ff */
/*01d0*/ IMAD R14, R8, c[0x0][0x17c], R13 ; /* 0x00005f00080e7a24 */
/* 0x000fc800078e020d */
/*01e0*/ IMAD.WIDE.U32 R14, R14, R15, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fcc00078e000f */
/*01f0*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ea8000c1e1900 */
/*0200*/ STS [R9.X4], R14 ; /* 0x0000000e09007388 */
/* 0x0041e40000004800 */
/*0210*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0220*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0230*/ BSSY B0, 0x840 ; /* 0x0000060000007945 */
/* 0x000fe20003800000 */
/*0240*/ @!P0 BRA 0x830 ; /* 0x000005e000008947 */
/* 0x000fea0003800000 */
/*0250*/ ISETP.NE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fda0003f25270 */
/*0260*/ @!P1 LDS R13, [R2.X4] ; /* 0x00000000020d9984 */
/* 0x000e680000004800 */
/*0270*/ @!P1 STS [R4.X4], R13 ; /* 0x0000000d04009388 */
/* 0x0023e20000004800 */
/*0280*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fda0003f25270 */
/*0290*/ @!P1 BRA 0x830 ; /* 0x0000059000009947 */
/* 0x000fea0003800000 */
/*02a0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x002fe20008000000 */
/*02b0*/ @!P2 BRA 0x5d0 ; /* 0x000003100000a947 */
/* 0x000fea0003800000 */
/*02c0*/ IMAD.MOV.U32 R13, RZ, RZ, R12 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e000c */
/*02d0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*02e0*/ IADD3 R17, R11, UR4, RZ ; /* 0x000000040b117c10 */
/* 0x000fe2000fffe0ff */
/*02f0*/ UIADD3 UR5, UR4, 0x1, URZ ; /* 0x0000000104057890 */
/* 0x000fe2000fffe03f */
/*0300*/ IADD3 R13, R13, -0x4, RZ ; /* 0xfffffffc0d0d7810 */
/* 0x000fe20007ffe0ff */
/*0310*/ UIADD3 UR8, UR4, 0x2, URZ ; /* 0x0000000204087890 */
/* 0x000fe2000fffe03f */
/*0320*/ ISETP.GE.AND P6, PT, R17, c[0x0][0x17c], PT ; /* 0x00005f0011007a0c */
/* 0x000fe20003fc6270 */
/*0330*/ UIADD3 UR9, UR4, 0x3, URZ ; /* 0x0000000304097890 */
/* 0x000fe2000fffe03f */
/*0340*/ ISETP.NE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe40003f25270 */
/*0350*/ IADD3 R18, R11, UR5, RZ ; /* 0x000000050b127c10 */
/* 0x000fc4000fffe0ff */
/*0360*/ IADD3 R19, R11.reuse, UR8, RZ ; /* 0x000000080b137c10 */
/* 0x040fe4000fffe0ff */
/*0370*/ IADD3 R16, R11, UR9, RZ ; /* 0x000000090b107c10 */
/* 0x000fe4000fffe0ff */
/*0380*/ ISETP.GE.AND P3, PT, R18, c[0x0][0x17c], PT ; /* 0x00005f0012007a0c */
/* 0x000fe40003f66270 */
/*0390*/ ISETP.GE.AND P4, PT, R19, c[0x0][0x17c], PT ; /* 0x00005f0013007a0c */
/* 0x000fe40003f86270 */
/*03a0*/ ISETP.GE.AND P5, PT, R16, c[0x0][0x17c], PT ; /* 0x00005f0010007a0c */
/* 0x000fe20003fa6270 */
/*03b0*/ @P6 BRA 0x430 ; /* 0x0000007000006947 */
/* 0x001ff00003800000 */
/*03c0*/ IMAD R15, R7, UR4, RZ ; /* 0x00000004070f7c24 */
/* 0x000fe2000f8e02ff */
/*03d0*/ LDS R14, [R4.X4] ; /* 0x00000000040e7984 */
/* 0x001fe60000004800 */
/*03e0*/ IMAD R15, R15, 0x4, R10 ; /* 0x000000040f0f7824 */
/* 0x000fcc00078e020a */
/*03f0*/ LDS R15, [R15] ; /* 0x000000000f0f7984 */
/* 0x000e240000000800 */
/*0400*/ FSETP.GEU.AND P6, PT, R14, R15, PT ; /* 0x0000000f0e00720b */
/* 0x001fda0003fce000 */
/*0410*/ @!P6 STS [R4.X4], R15 ; /* 0x0000000f0400e388 */
/* 0x0001e20000004800 */
/*0420*/ @!P6 IMAD.MOV.U32 R0, RZ, RZ, R17 ; /* 0x000000ffff00e224 */
/* 0x000fc600078e0011 */
/*0430*/ @P3 BRA 0x4b0 ; /* 0x0000007000003947 */
/* 0x000fea0003800000 */
/*0440*/ IMAD R15, R7, UR5, RZ ; /* 0x00000005070f7c24 */
/* 0x001fe2000f8e02ff */
/*0450*/ LDS R14, [R4.X4] ; /* 0x00000000040e7984 */
/* 0x000fe60000004800 */
/*0460*/ IMAD R15, R15, 0x4, R10 ; /* 0x000000040f0f7824 */
/* 0x000fcc00078e020a */
/*0470*/ LDS R15, [R15] ; /* 0x000000000f0f7984 */
/* 0x000e240000000800 */
/*0480*/ FSETP.GEU.AND P3, PT, R14, R15, PT ; /* 0x0000000f0e00720b */
/* 0x001fda0003f6e000 */
/*0490*/ @!P3 STS [R4.X4], R15 ; /* 0x0000000f0400b388 */
/* 0x0001e20000004800 */
/*04a0*/ @!P3 IMAD.MOV.U32 R0, RZ, RZ, R18 ; /* 0x000000ffff00b224 */
/* 0x000fc600078e0012 */
/*04b0*/ @P4 BRA 0x530 ; /* 0x0000007000004947 */
/* 0x000fea0003800000 */
/*04c0*/ IMAD R15, R7, UR8, RZ ; /* 0x00000008070f7c24 */
/* 0x001fe2000f8e02ff */
/*04d0*/ LDS R14, [R4.X4] ; /* 0x00000000040e7984 */
/* 0x000fe60000004800 */
/*04e0*/ IMAD R15, R15, 0x4, R10 ; /* 0x000000040f0f7824 */
/* 0x000fcc00078e020a */
/*04f0*/ LDS R15, [R15] ; /* 0x000000000f0f7984 */
/* 0x000e240000000800 */
/*0500*/ FSETP.GEU.AND P3, PT, R14, R15, PT ; /* 0x0000000f0e00720b */
/* 0x001fda0003f6e000 */
/*0510*/ @!P3 STS [R4.X4], R15 ; /* 0x0000000f0400b388 */
/* 0x0001e20000004800 */
/*0520*/ @!P3 IMAD.MOV.U32 R0, RZ, RZ, R19 ; /* 0x000000ffff00b224 */
/* 0x000fc600078e0013 */
/*0530*/ @P5 BRA 0x5b0 ; /* 0x0000007000005947 */
/* 0x000fea0003800000 */
/*0540*/ IMAD R15, R7, UR9, RZ ; /* 0x00000009070f7c24 */
/* 0x001fe2000f8e02ff */
/*0550*/ LDS R14, [R4.X4] ; /* 0x00000000040e7984 */
/* 0x000fe60000004800 */
/*0560*/ IMAD R15, R15, 0x4, R10 ; /* 0x000000040f0f7824 */
/* 0x000fcc00078e020a */
/*0570*/ LDS R15, [R15] ; /* 0x000000000f0f7984 */
/* 0x000e240000000800 */
/*0580*/ FSETP.GEU.AND P3, PT, R14, R15, PT ; /* 0x0000000f0e00720b */
/* 0x001fda0003f6e000 */
/*0590*/ @!P3 STS [R4.X4], R15 ; /* 0x0000000f0400b388 */
/* 0x0001e20000004800 */
/*05a0*/ @!P3 IMAD.MOV.U32 R0, RZ, RZ, R16 ; /* 0x000000ffff00b224 */
/* 0x000fc600078e0010 */
/*05b0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*05c0*/ @P1 BRA 0x2e0 ; /* 0xfffffd1000001947 */
/* 0x000fea000383ffff */
/*05d0*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f25270 */
/*05e0*/ @!P1 BRA 0x830 ; /* 0x0000024000009947 */
/* 0x000fea0003800000 */
/*05f0*/ IADD3 R15, R11, UR4, RZ ; /* 0x000000040b0f7c10 */
/* 0x001fe4000fffe0ff */
/*0600*/ ISETP.NE.AND P3, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe40003f65270 */
/*0610*/ ISETP.GE.AND P1, PT, R15, c[0x0][0x17c], PT ; /* 0x00005f000f007a0c */
/* 0x000fda0003f26270 */
/*0620*/ @P1 BRA 0x6a0 ; /* 0x0000007000001947 */
/* 0x000fea0003800000 */
/*0630*/ IMAD R13, R7, UR4, RZ ; /* 0x00000004070d7c24 */
/* 0x000fe2000f8e02ff */
/*0640*/ LDS R14, [R4.X4] ; /* 0x00000000040e7984 */
/* 0x000fe60000004800 */
/*0650*/ IMAD R13, R13, 0x4, R10 ; /* 0x000000040d0d7824 */
/* 0x000fcc00078e020a */
/*0660*/ LDS R13, [R13] ; /* 0x000000000d0d7984 */
/* 0x000e240000000800 */
/*0670*/ FSETP.GEU.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720b */
/* 0x001fda0003f2e000 */
/*0680*/ @!P1 STS [R4.X4], R13 ; /* 0x0000000d04009388 */
/* 0x0001e20000004800 */
/*0690*/ @!P1 IMAD.MOV.U32 R0, RZ, RZ, R15 ; /* 0x000000ffff009224 */
/* 0x000fc600078e000f */
/*06a0*/ @!P3 BRA 0x830 ; /* 0x000001800000b947 */
/* 0x000fea0003800000 */
/*06b0*/ UIADD3 UR5, UR4, 0x1, URZ ; /* 0x0000000104057890 */
/* 0x000fe2000fffe03f */
/*06c0*/ ISETP.NE.AND P3, PT, R6, 0x2, PT ; /* 0x000000020600780c */
/* 0x000fca0003f65270 */
/*06d0*/ IADD3 R15, R11, UR5, RZ ; /* 0x000000050b0f7c10 */
/* 0x000fc8000fffe0ff */
/*06e0*/ ISETP.GE.AND P1, PT, R15, c[0x0][0x17c], PT ; /* 0x00005f000f007a0c */
/* 0x000fda0003f26270 */
/*06f0*/ @P1 BRA 0x770 ; /* 0x0000007000001947 */
/* 0x000fea0003800000 */
/*0700*/ IMAD R13, R7, UR5, RZ ; /* 0x00000005070d7c24 */
/* 0x001fe2000f8e02ff */
/*0710*/ LDS R14, [R4.X4] ; /* 0x00000000040e7984 */
/* 0x000fe60000004800 */
/*0720*/ IMAD R13, R13, 0x4, R10 ; /* 0x000000040d0d7824 */
/* 0x000fcc00078e020a */
/*0730*/ LDS R13, [R13] ; /* 0x000000000d0d7984 */
/* 0x000e240000000800 */
/*0740*/ FSETP.GEU.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720b */
/* 0x001fda0003f2e000 */
/*0750*/ @!P1 STS [R4.X4], R13 ; /* 0x0000000d04009388 */
/* 0x0001e20000004800 */
/*0760*/ @!P1 IMAD.MOV.U32 R0, RZ, RZ, R15 ; /* 0x000000ffff009224 */
/* 0x000fc600078e000f */
/*0770*/ @!P3 BRA 0x830 ; /* 0x000000b00000b947 */
/* 0x000fea0003800000 */
/*0780*/ UIADD3 UR4, UR4, 0x2, URZ ; /* 0x0000000204047890 */
/* 0x000fcc000fffe03f */
/*0790*/ IADD3 R15, R11, UR4, RZ ; /* 0x000000040b0f7c10 */
/* 0x000fc8000fffe0ff */
/*07a0*/ ISETP.GE.AND P1, PT, R15, c[0x0][0x17c], PT ; /* 0x00005f000f007a0c */
/* 0x000fda0003f26270 */
/*07b0*/ @P1 BRA 0x830 ; /* 0x0000007000001947 */
/* 0x000fea0003800000 */
/*07c0*/ IMAD R13, R7, UR4, RZ ; /* 0x00000004070d7c24 */
/* 0x001fe2000f8e02ff */
/*07d0*/ LDS R14, [R4.X4] ; /* 0x00000000040e7984 */
/* 0x000fe60000004800 */
/*07e0*/ IMAD R13, R13, 0x4, R10 ; /* 0x000000040d0d7824 */
/* 0x000fcc00078e020a */
/*07f0*/ LDS R13, [R13] ; /* 0x000000000d0d7984 */
/* 0x000e240000000800 */
/*0800*/ FSETP.GEU.AND P1, PT, R14, R13, PT ; /* 0x0000000d0e00720b */
/* 0x001fda0003f2e000 */
/*0810*/ @!P1 STS [R4.X4], R13 ; /* 0x0000000d04009388 */
/* 0x0001e20000004800 */
/*0820*/ @!P1 IMAD.MOV.U32 R0, RZ, RZ, R15 ; /* 0x000000ffff009224 */
/* 0x000fc600078e000f */
/*0830*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0840*/ IADD3 R11, R11, c[0x0][0x0], RZ ; /* 0x000000000b0b7a10 */
/* 0x000fe20007ffe0ff */
/*0850*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0860*/ ISETP.GE.AND P1, PT, R11, c[0x0][0x17c], PT ; /* 0x00005f000b007a0c */
/* 0x000fda0003f26270 */
/*0870*/ @!P1 BRA 0x170 ; /* 0xfffff8f000009947 */
/* 0x000fea000383ffff */
/*0880*/ IMAD R6, R5, c[0x0][0x0], R2 ; /* 0x0000000005067a24 */
/* 0x004fca00078e0202 */
/*0890*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fc80003f06070 */
/*08a0*/ ISETP.NE.OR P0, PT, R3, RZ, P0 ; /* 0x000000ff0300720c */
/* 0x002fda0000705670 */
/*08b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*08c0*/ LDS R5, [R4.X4] ; /* 0x0000000004057984 */
/* 0x000e620000004800 */
/*08d0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc800078e00ff */
/*08e0*/ IMAD.WIDE.U32 R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fc800078e0007 */
/*08f0*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0007 */
/*0900*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe8000c101906 */
/*0910*/ STG.E [R6.64], R0 ; /* 0x0000000006007986 */
/* 0x000fe2000c101906 */
/*0920*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0930*/ BRA 0x930; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14apply_rows_maxPfS_Piii
.globl _Z14apply_rows_maxPfS_Piii
.p2align 8
.type _Z14apply_rows_maxPfS_Piii,@function
_Z14apply_rows_maxPfS_Piii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v5, v0, 10, 10
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s9, 1
s_mul_i32 s15, s15, s9
s_mul_i32 s3, s2, s9
v_add_nc_u32_e32 v0, s15, v1
s_lshl_b32 s3, s3, 2
s_add_i32 s8, s3, 0
s_cmp_lt_i32 s5, 1
s_cbranch_scc1 .LBB0_15
s_load_b64 s[6:7], s[0:1], 0x0
v_add_nc_u32_e32 v4, s15, v5
v_cmp_eq_u32_e32 vcc_lo, 0, v5
v_cmp_gt_u32_e64 s3, s4, v0
v_mad_u32_u24 v6, s2, v1, v5
v_lshlrev_b32_e32 v9, 2, v1
v_mad_u64_u32 v[2:3], null, v4, s5, v[1:2]
s_delay_alu instid0(VALU_DEP_4)
s_and_b32 s3, vcc_lo, s3
s_cmp_lg_u32 s9, 0
v_cmp_gt_u32_e64 s2, s4, v4
v_lshl_add_u32 v7, v6, 2, 0
v_mov_b32_e32 v6, 0
v_add_nc_u32_e32 v8, 0, v9
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v9, s8, v9
s_cselect_b32 s11, -1, 0
s_lshl_b32 s12, s9, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s12, s12, 4
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s13
s_add_i32 s10, s10, s9
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s10, s5
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_16
.LBB0_3:
v_add_nc_u32_e32 v3, s10, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s5, v3
s_and_b32 s14, s2, vcc_lo
s_and_saveexec_b32 s13, s14
s_cbranch_execz .LBB0_5
v_add_nc_u32_e32 v3, s10, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v10, vcc_lo, s6, v10
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
global_load_b32 v3, v[10:11], off
s_waitcnt vmcnt(0)
ds_store_b32 v7, v3
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s13
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s13, s3
s_cbranch_execz .LBB0_2
s_cmp_lg_u32 s10, 0
s_cbranch_scc0 .LBB0_8
s_and_not1_b32 vcc_lo, exec_lo, s11
s_cbranch_vccz .LBB0_9
s_branch .LBB0_2
.LBB0_8:
ds_load_b32 v3, v8
s_waitcnt lgkmcnt(0)
ds_store_b32 v9, v3
s_and_not1_b32 vcc_lo, exec_lo, s11
s_cbranch_vccnz .LBB0_2
.LBB0_9:
v_mov_b32_e32 v3, v8
s_mov_b32 s14, 0
s_branch .LBB0_12
.p2align 6
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s16
.LBB0_11:
v_add_nc_u32_e32 v3, s12, v3
s_add_i32 s14, s14, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s9, s14
s_cbranch_scc0 .LBB0_2
.LBB0_12:
s_add_i32 s15, s10, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s15, s5
s_cbranch_scc1 .LBB0_11
ds_load_b32 v11, v9
ds_load_b32 v10, v3
s_mov_b32 s16, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_lt_f32_e32 v11, v10
s_cbranch_execz .LBB0_10
v_mov_b32_e32 v6, s15
ds_store_b32 v9, v10
s_branch .LBB0_10
.LBB0_15:
v_mov_b32_e32 v6, 0
.LBB0_16:
v_cmp_gt_u32_e32 vcc_lo, s4, v0
v_cmp_eq_u32_e64 s2, 0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_18
s_load_b128 s[0:3], s[0:1], 0x8
v_lshl_add_u32 v2, v1, 2, s8
v_mov_b32_e32 v1, 0
ds_load_b32 v4, v2
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[2:3], v4, off
global_store_b32 v[0:1], v6, off
.LBB0_18:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14apply_rows_maxPfS_Piii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14apply_rows_maxPfS_Piii, .Lfunc_end0-_Z14apply_rows_maxPfS_Piii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
- .offset: 152
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14apply_rows_maxPfS_Piii
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z14apply_rows_maxPfS_Piii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00193e38_00000000-6_apply_rows_max.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z14apply_rows_maxPfS_PiiiPfS_Piii
.type _Z40__device_stub__Z14apply_rows_maxPfS_PiiiPfS_Piii, @function
_Z40__device_stub__Z14apply_rows_maxPfS_PiiiPfS_Piii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14apply_rows_maxPfS_Piii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z14apply_rows_maxPfS_PiiiPfS_Piii, .-_Z40__device_stub__Z14apply_rows_maxPfS_PiiiPfS_Piii
.globl _Z14apply_rows_maxPfS_Piii
.type _Z14apply_rows_maxPfS_Piii, @function
_Z14apply_rows_maxPfS_Piii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z14apply_rows_maxPfS_PiiiPfS_Piii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14apply_rows_maxPfS_Piii, .-_Z14apply_rows_maxPfS_Piii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14apply_rows_maxPfS_Piii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14apply_rows_maxPfS_Piii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "apply_rows_max.hip"
.globl _Z29__device_stub__apply_rows_maxPfS_Piii # -- Begin function _Z29__device_stub__apply_rows_maxPfS_Piii
.p2align 4, 0x90
.type _Z29__device_stub__apply_rows_maxPfS_Piii,@function
_Z29__device_stub__apply_rows_maxPfS_Piii: # @_Z29__device_stub__apply_rows_maxPfS_Piii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14apply_rows_maxPfS_Piii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__apply_rows_maxPfS_Piii, .Lfunc_end0-_Z29__device_stub__apply_rows_maxPfS_Piii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14apply_rows_maxPfS_Piii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14apply_rows_maxPfS_Piii,@object # @_Z14apply_rows_maxPfS_Piii
.section .rodata,"a",@progbits
.globl _Z14apply_rows_maxPfS_Piii
.p2align 3, 0x0
_Z14apply_rows_maxPfS_Piii:
.quad _Z29__device_stub__apply_rows_maxPfS_Piii
.size _Z14apply_rows_maxPfS_Piii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14apply_rows_maxPfS_Piii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__apply_rows_maxPfS_Piii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14apply_rows_maxPfS_Piii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void mykernel() {
printf("Hello World \n");
}
int main(void) {
mykernel<<<1, 1 >>>();
} | code for sm_80
Function : _Z8mykernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void mykernel() {
printf("Hello World \n");
}
int main(void) {
mykernel<<<1, 1 >>>();
} | .file "tmpxft_0008cfc4_00000000-6_hello_world.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z8mykernelvv
.type _Z26__device_stub__Z8mykernelvv, @function
_Z26__device_stub__Z8mykernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8mykernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z8mykernelvv, .-_Z26__device_stub__Z8mykernelvv
.globl _Z8mykernelv
.type _Z8mykernelv, @function
_Z8mykernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8mykernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8mykernelv, .-_Z8mykernelv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z26__device_stub__Z8mykernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8mykernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8mykernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void mykernel() {
printf("Hello World \n");
}
int main(void) {
mykernel<<<1, 1 >>>();
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void mykernel() {
printf("Hello World \n");
}
int main(void) {
mykernel<<<1, 1 >>>();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void mykernel() {
printf("Hello World \n");
}
int main(void) {
mykernel<<<1, 1 >>>();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8mykernelv
.globl _Z8mykernelv
.p2align 8
.type _Z8mykernelv,@function
_Z8mykernelv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 14
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8mykernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8mykernelv, .Lfunc_end0-_Z8mykernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello World \n"
.size .str, 14
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8mykernelv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z8mykernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void mykernel() {
printf("Hello World \n");
}
int main(void) {
mykernel<<<1, 1 >>>();
} | .text
.file "hello_world.hip"
.globl _Z23__device_stub__mykernelv # -- Begin function _Z23__device_stub__mykernelv
.p2align 4, 0x90
.type _Z23__device_stub__mykernelv,@function
_Z23__device_stub__mykernelv: # @_Z23__device_stub__mykernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8mykernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__mykernelv, .Lfunc_end0-_Z23__device_stub__mykernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8mykernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8mykernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8mykernelv,@object # @_Z8mykernelv
.section .rodata,"a",@progbits
.globl _Z8mykernelv
.p2align 3, 0x0
_Z8mykernelv:
.quad _Z23__device_stub__mykernelv
.size _Z8mykernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8mykernelv"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__mykernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8mykernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8mykernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8mykernelv
.globl _Z8mykernelv
.p2align 8
.type _Z8mykernelv,@function
_Z8mykernelv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 14
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8mykernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8mykernelv, .Lfunc_end0-_Z8mykernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello World \n"
.size .str, 14
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8mykernelv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z8mykernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008cfc4_00000000-6_hello_world.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z8mykernelvv
.type _Z26__device_stub__Z8mykernelvv, @function
_Z26__device_stub__Z8mykernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8mykernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z8mykernelvv, .-_Z26__device_stub__Z8mykernelvv
.globl _Z8mykernelv
.type _Z8mykernelv, @function
_Z8mykernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8mykernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8mykernelv, .-_Z8mykernelv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z26__device_stub__Z8mykernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8mykernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8mykernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello_world.hip"
.globl _Z23__device_stub__mykernelv # -- Begin function _Z23__device_stub__mykernelv
.p2align 4, 0x90
.type _Z23__device_stub__mykernelv,@function
_Z23__device_stub__mykernelv: # @_Z23__device_stub__mykernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8mykernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__mykernelv, .Lfunc_end0-_Z23__device_stub__mykernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8mykernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8mykernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8mykernelv,@object # @_Z8mykernelv
.section .rodata,"a",@progbits
.globl _Z8mykernelv
.p2align 3, 0x0
_Z8mykernelv:
.quad _Z23__device_stub__mykernelv
.size _Z8mykernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8mykernelv"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__mykernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8mykernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <cuda.h>
__global__ void getmaxcu(unsigned int num[], unsigned int size, unsigned int gap)
{
unsigned int i=gap, //loop variables
start = (threadIdx.x)*gap;
if(start%2!=0 || size<=0)
return;
else{
//bottom-up tree search
while(start+i<size && start%(2*i)==0){
if(num[start]<num[start+i])
num[start]=num[start+i];
i*=2;
__syncthreads();
}
}
}
int main(int argc, char *argv[])
{
if(argc !=2)
{
printf("usage: maxgpu num\n");
printf("num = size of the array\n");
exit(1);
}
cudaError_t err; // error var
unsigned int size = 0, backup_size, // The size of array
thread_num,
i; // loop index
struct cudaDeviceProp prop; // specs
unsigned int *numbers, *cudanumbers, // pointers to array
*max=(unsigned int *)malloc(sizeof(unsigned int)); // pointers to max number
size = atol(argv[1]);
backup_size=size;
numbers = (unsigned int *)malloc(size * sizeof(unsigned int));
if(!numbers)
{
printf("Unable to allocate mem for an array of size %u\n", size);
exit(1);
}
srand(time(NULL)); // setting a seed for the random number generator
// Fill-up the array with random numbers from 0 to size-1
for( i = 0; i < size; i++)
numbers[i] = rand() % size;
cudaGetDeviceProperties(&prop, 0);
cudaMalloc((void**)&cudanumbers, size * sizeof(unsigned int));
cudaMemcpy(cudanumbers, numbers, size * sizeof(unsigned int), cudaMemcpyHostToDevice);
thread_num=ceil(prop.maxThreadsPerBlock/32)*32;
unsigned int offset=0;
i=0;
//search 1024 elements at once; search remaining elements
//structure: |----1024----| |----1024----| ... |size%1024| left to right
while(offset<backup_size){
if(backup_size-offset>=thread_num){
getmaxcu<<<1, thread_num>>>((cudanumbers+offset), thread_num, 1);
}
else{
getmaxcu<<<1, backup_size-offset>>>((cudanumbers+offset), backup_size-offset, 1);
}
getmaxcu<<<1, 1>>>((cudanumbers), backup_size, offset);
offset+=thread_num;
}
cudaMemcpy(max, cudanumbers, sizeof(unsigned int), cudaMemcpyDeviceToHost);
err=cudaGetLastError();
if(err!=cudaSuccess){
printf("CUDA error: %s\n", cudaGetErrorString(err));
exit(-1);
}
cudaThreadSynchronize();
cudaFree(cudanumbers);
printf("CUDA returns: %d\n", *max);
//printf("Sequential returns: %u\n", getmax(numbers, backup_size));
free(numbers);
free(max);
exit(0);
}
/*
unsigned int getmax(unsigned int num[], unsigned int size)
{
unsigned int i, j;
unsigned int max = num[0];
for(i = 1; i < size; i++)
if(num[i] > max){
max = num[i];
j=i;
}
//printf("Sequential found max at %d\n", j);
return max;
}
__global__ void printArray(unsigned int arr[], unsigned int length, unsigned int jump){
for(int i = 0; i+jump<length; i++)
printf("%d: %d\n", i+jump, arr[i+jump]);
}
void search(unsigned int arr[], unsigned int size, unsigned int target){
printf("CUDA found max at");
for(int i = 1; i < size; i++)
if(arr[i] == target)
printf(" %d ", i);
printf("\n");
}
*/ | code for sm_80
Function : _Z8getmaxcuPjjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ IMAD R0, R0, c[0x0][0x16c], RZ ; /* 0x00005b0000007a24 */
/* 0x001fca00078e02ff */
/*0030*/ LOP3.LUT R2, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100027812 */
/* 0x000fc800078ec0ff */
/*0040*/ ISETP.NE.U32.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fc80003f05070 */
/*0050*/ ISETP.EQ.OR P0, PT, RZ, c[0x0][0x168], !P0 ; /* 0x00005a00ff007a0c */
/* 0x000fda0004702670 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IADD3 R2, R0, c[0x0][0x16c], RZ ; /* 0x00005b0000027a10 */
/* 0x000fc80007ffe0ff */
/*0080*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06070 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*00b0*/ MOV R7, c[0x0][0x16c] ; /* 0x00005b0000077a02 */
/* 0x000fe20000000f00 */
/*00c0*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0002 */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00e0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0003 */
/*00f0*/ IMAD.SHL.U32 R7, R7, 0x2, RZ ; /* 0x0000000207077824 */
/* 0x000fc800078e00ff */
/*0100*/ I2F.U32.RP R8, R7 ; /* 0x0000000700087306 */
/* 0x000e220000209000 */
/*0110*/ IMAD.MOV R9, RZ, RZ, -R7 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a07 */
/*0120*/ ISETP.NE.U32.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fcc0003f25070 */
/*0130*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e240000001000 */
/*0140*/ IADD3 R4, R8, 0xffffffe, RZ ; /* 0x0ffffffe08047810 */
/* 0x001fcc0007ffe0ff */
/*0150*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0160*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0170*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fd200078e02ff */
/*0180*/ IMAD.HI.U32 R5, R5, R9, R4 ; /* 0x0000000905057227 */
/* 0x000fcc00078e0004 */
/*0190*/ IMAD.HI.U32 R5, R5, R0, RZ ; /* 0x0000000005057227 */
/* 0x000fc800078e00ff */
/*01a0*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a05 */
/*01b0*/ IMAD R10, R7, R5, R0 ; /* 0x00000005070a7224 */
/* 0x000fca00078e0200 */
/*01c0*/ ISETP.GE.U32.AND P0, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x000fda0003f06070 */
/*01d0*/ @P0 IMAD.IADD R10, R10, 0x1, -R7 ; /* 0x000000010a0a0824 */
/* 0x000fca00078e0a07 */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x000fda0003f06070 */
/*01f0*/ @P0 IADD3 R10, -R7, R10, RZ ; /* 0x0000000a070a0210 */
/* 0x000fe40007ffe1ff */
/*0200*/ @!P1 LOP3.LUT R10, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff0a9212 */
/* 0x000fc800078e33ff */
/*0210*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f05270 */
/*0220*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0230*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0240*/ IMAD.WIDE.U32 R4, R6, R5, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fe400078e0005 */
/*0250*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea8000c1e1900 */
/*0260*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0270*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0280*/ ISETP.GE.U32.AND P0, PT, R6, R5, PT ; /* 0x000000050600720c */
/* 0x004fe40003f06070 */
/*0290*/ IADD3 R6, R0, R7, RZ ; /* 0x0000000700067210 */
/* 0x000fd60007ffe0ff */
/*02a0*/ @!P0 STG.E [R2.64], R5 ; /* 0x0000000502008986 */
/* 0x0001e8000c101904 */
/*02b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02c0*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fda0003f06070 */
/*02d0*/ @!P0 BRA 0xf0 ; /* 0xfffffe1000008947 */
/* 0x001fea000383ffff */
/*02e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02f0*/ BRA 0x2f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <cuda.h>
__global__ void getmaxcu(unsigned int num[], unsigned int size, unsigned int gap)
{
unsigned int i=gap, //loop variables
start = (threadIdx.x)*gap;
if(start%2!=0 || size<=0)
return;
else{
//bottom-up tree search
while(start+i<size && start%(2*i)==0){
if(num[start]<num[start+i])
num[start]=num[start+i];
i*=2;
__syncthreads();
}
}
}
int main(int argc, char *argv[])
{
if(argc !=2)
{
printf("usage: maxgpu num\n");
printf("num = size of the array\n");
exit(1);
}
cudaError_t err; // error var
unsigned int size = 0, backup_size, // The size of array
thread_num,
i; // loop index
struct cudaDeviceProp prop; // specs
unsigned int *numbers, *cudanumbers, // pointers to array
*max=(unsigned int *)malloc(sizeof(unsigned int)); // pointers to max number
size = atol(argv[1]);
backup_size=size;
numbers = (unsigned int *)malloc(size * sizeof(unsigned int));
if(!numbers)
{
printf("Unable to allocate mem for an array of size %u\n", size);
exit(1);
}
srand(time(NULL)); // setting a seed for the random number generator
// Fill-up the array with random numbers from 0 to size-1
for( i = 0; i < size; i++)
numbers[i] = rand() % size;
cudaGetDeviceProperties(&prop, 0);
cudaMalloc((void**)&cudanumbers, size * sizeof(unsigned int));
cudaMemcpy(cudanumbers, numbers, size * sizeof(unsigned int), cudaMemcpyHostToDevice);
thread_num=ceil(prop.maxThreadsPerBlock/32)*32;
unsigned int offset=0;
i=0;
//search 1024 elements at once; search remaining elements
//structure: |----1024----| |----1024----| ... |size%1024| left to right
while(offset<backup_size){
if(backup_size-offset>=thread_num){
getmaxcu<<<1, thread_num>>>((cudanumbers+offset), thread_num, 1);
}
else{
getmaxcu<<<1, backup_size-offset>>>((cudanumbers+offset), backup_size-offset, 1);
}
getmaxcu<<<1, 1>>>((cudanumbers), backup_size, offset);
offset+=thread_num;
}
cudaMemcpy(max, cudanumbers, sizeof(unsigned int), cudaMemcpyDeviceToHost);
err=cudaGetLastError();
if(err!=cudaSuccess){
printf("CUDA error: %s\n", cudaGetErrorString(err));
exit(-1);
}
cudaThreadSynchronize();
cudaFree(cudanumbers);
printf("CUDA returns: %d\n", *max);
//printf("Sequential returns: %u\n", getmax(numbers, backup_size));
free(numbers);
free(max);
exit(0);
}
/*
unsigned int getmax(unsigned int num[], unsigned int size)
{
unsigned int i, j;
unsigned int max = num[0];
for(i = 1; i < size; i++)
if(num[i] > max){
max = num[i];
j=i;
}
//printf("Sequential found max at %d\n", j);
return max;
}
__global__ void printArray(unsigned int arr[], unsigned int length, unsigned int jump){
for(int i = 0; i+jump<length; i++)
printf("%d: %d\n", i+jump, arr[i+jump]);
}
void search(unsigned int arr[], unsigned int size, unsigned int target){
printf("CUDA found max at");
for(int i = 1; i < size; i++)
if(arr[i] == target)
printf(" %d ", i);
printf("\n");
}
*/ | .file "tmpxft_0009e9f9_00000000-6_maxgpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z8getmaxcuPjjjPjjj
.type _Z29__device_stub__Z8getmaxcuPjjjPjjj, @function
_Z29__device_stub__Z8getmaxcuPjjjPjjj:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8getmaxcuPjjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z8getmaxcuPjjjPjjj, .-_Z29__device_stub__Z8getmaxcuPjjjPjjj
.globl _Z8getmaxcuPjjj
.type _Z8getmaxcuPjjj, @function
_Z8getmaxcuPjjj:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8getmaxcuPjjjPjjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8getmaxcuPjjj, .-_Z8getmaxcuPjjj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "usage: maxgpu num\n"
.LC1:
.string "num = size of the array\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Unable to allocate mem for an array of size %u\n"
.section .rodata.str1.1
.LC4:
.string "CUDA error: %s\n"
.LC5:
.string "CUDA returns: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1096, %rsp
.cfi_def_cfa_offset 1152
movq %fs:40, %rax
movq %rax, 1080(%rsp)
xorl %eax, %eax
cmpl $2, %edi
je .L12
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L12:
movq %rsi, %rbx
movl $4, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %r12d
movl %eax, %r15d
salq $2, %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %r14
testq %rax, %rax
je .L28
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
testl %ebx, %ebx
je .L14
movq %r14, %rbp
leal -1(%rbx), %eax
leaq 4(%r14,%rax,4), %r13
.L15:
call rand@PLT
movl $0, %edx
divl %r12d
movl %edx, 0(%rbp)
addq $4, %rbp
cmpq %r13, %rbp
jne .L15
leaq 48(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
leaq 16(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl 368(%rsp), %eax
movl $32, %ecx
cltd
idivl %ecx
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd .LC3(%rip), %xmm0
cvttsd2siq %xmm0, %rbp
movl $0, %r13d
jmp .L21
.L28:
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L16:
movl %ebx, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L18:
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L20:
addl %ebp, %r13d
subl %ebp, %ebx
cmpl %r12d, %r13d
jnb .L23
.L21:
cmpl %ebp, %ebx
jb .L16
movl %ebp, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L18
movl %r13d, %eax
movq 16(%rsp), %rdx
leaq (%rdx,%rax,4), %rdi
movl $1, %edx
movl %ebp, %esi
call _Z29__device_stub__Z8getmaxcuPjjjPjjj
jmp .L18
.L29:
movl %r13d, %eax
movq 16(%rsp), %rdx
leaq (%rdx,%rax,4), %rdi
movl $1, %edx
movl %ebx, %esi
call _Z29__device_stub__Z8getmaxcuPjjjPjjj
jmp .L18
.L30:
movl %r13d, %edx
movl %r12d, %esi
movq 16(%rsp), %rdi
call _Z29__device_stub__Z8getmaxcuPjjjPjjj
jmp .L20
.L22:
call cudaThreadSynchronize@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rbx
movl (%rbx), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r14, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %edi
call exit@PLT
.L14:
leaq 48(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
leaq 16(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
.L23:
movl $2, %ecx
movl $4, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
je .L22
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z8getmaxcuPjjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z8getmaxcuPjjj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1077936128
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <cuda.h>
__global__ void getmaxcu(unsigned int num[], unsigned int size, unsigned int gap)
{
unsigned int i=gap, //loop variables
start = (threadIdx.x)*gap;
if(start%2!=0 || size<=0)
return;
else{
//bottom-up tree search
while(start+i<size && start%(2*i)==0){
if(num[start]<num[start+i])
num[start]=num[start+i];
i*=2;
__syncthreads();
}
}
}
int main(int argc, char *argv[])
{
if(argc !=2)
{
printf("usage: maxgpu num\n");
printf("num = size of the array\n");
exit(1);
}
cudaError_t err; // error var
unsigned int size = 0, backup_size, // The size of array
thread_num,
i; // loop index
struct cudaDeviceProp prop; // specs
unsigned int *numbers, *cudanumbers, // pointers to array
*max=(unsigned int *)malloc(sizeof(unsigned int)); // pointers to max number
size = atol(argv[1]);
backup_size=size;
numbers = (unsigned int *)malloc(size * sizeof(unsigned int));
if(!numbers)
{
printf("Unable to allocate mem for an array of size %u\n", size);
exit(1);
}
srand(time(NULL)); // setting a seed for the random number generator
// Fill-up the array with random numbers from 0 to size-1
for( i = 0; i < size; i++)
numbers[i] = rand() % size;
cudaGetDeviceProperties(&prop, 0);
cudaMalloc((void**)&cudanumbers, size * sizeof(unsigned int));
cudaMemcpy(cudanumbers, numbers, size * sizeof(unsigned int), cudaMemcpyHostToDevice);
thread_num=ceil(prop.maxThreadsPerBlock/32)*32;
unsigned int offset=0;
i=0;
//search 1024 elements at once; search remaining elements
//structure: |----1024----| |----1024----| ... |size%1024| left to right
while(offset<backup_size){
if(backup_size-offset>=thread_num){
getmaxcu<<<1, thread_num>>>((cudanumbers+offset), thread_num, 1);
}
else{
getmaxcu<<<1, backup_size-offset>>>((cudanumbers+offset), backup_size-offset, 1);
}
getmaxcu<<<1, 1>>>((cudanumbers), backup_size, offset);
offset+=thread_num;
}
cudaMemcpy(max, cudanumbers, sizeof(unsigned int), cudaMemcpyDeviceToHost);
err=cudaGetLastError();
if(err!=cudaSuccess){
printf("CUDA error: %s\n", cudaGetErrorString(err));
exit(-1);
}
cudaThreadSynchronize();
cudaFree(cudanumbers);
printf("CUDA returns: %d\n", *max);
//printf("Sequential returns: %u\n", getmax(numbers, backup_size));
free(numbers);
free(max);
exit(0);
}
/*
unsigned int getmax(unsigned int num[], unsigned int size)
{
unsigned int i, j;
unsigned int max = num[0];
for(i = 1; i < size; i++)
if(num[i] > max){
max = num[i];
j=i;
}
//printf("Sequential found max at %d\n", j);
return max;
}
__global__ void printArray(unsigned int arr[], unsigned int length, unsigned int jump){
for(int i = 0; i+jump<length; i++)
printf("%d: %d\n", i+jump, arr[i+jump]);
}
void search(unsigned int arr[], unsigned int size, unsigned int target){
printf("CUDA found max at");
for(int i = 1; i < size; i++)
if(arr[i] == target)
printf(" %d ", i);
printf("\n");
}
*/ | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <hip/hip_runtime.h>
__global__ void getmaxcu(unsigned int num[], unsigned int size, unsigned int gap)
{
unsigned int i=gap, //loop variables
start = (threadIdx.x)*gap;
if(start%2!=0 || size<=0)
return;
else{
//bottom-up tree search
while(start+i<size && start%(2*i)==0){
if(num[start]<num[start+i])
num[start]=num[start+i];
i*=2;
__syncthreads();
}
}
}
int main(int argc, char *argv[])
{
if(argc !=2)
{
printf("usage: maxgpu num\n");
printf("num = size of the array\n");
exit(1);
}
hipError_t err; // error var
unsigned int size = 0, backup_size, // The size of array
thread_num,
i; // loop index
struct hipDeviceProp_t prop; // specs
unsigned int *numbers, *cudanumbers, // pointers to array
*max=(unsigned int *)malloc(sizeof(unsigned int)); // pointers to max number
size = atol(argv[1]);
backup_size=size;
numbers = (unsigned int *)malloc(size * sizeof(unsigned int));
if(!numbers)
{
printf("Unable to allocate mem for an array of size %u\n", size);
exit(1);
}
srand(time(NULL)); // setting a seed for the random number generator
// Fill-up the array with random numbers from 0 to size-1
for( i = 0; i < size; i++)
numbers[i] = rand() % size;
hipGetDeviceProperties(&prop, 0);
hipMalloc((void**)&cudanumbers, size * sizeof(unsigned int));
hipMemcpy(cudanumbers, numbers, size * sizeof(unsigned int), hipMemcpyHostToDevice);
thread_num=ceil(prop.maxThreadsPerBlock/32)*32;
unsigned int offset=0;
i=0;
//search 1024 elements at once; search remaining elements
//structure: |----1024----| |----1024----| ... |size%1024| left to right
while(offset<backup_size){
if(backup_size-offset>=thread_num){
getmaxcu<<<1, thread_num>>>((cudanumbers+offset), thread_num, 1);
}
else{
getmaxcu<<<1, backup_size-offset>>>((cudanumbers+offset), backup_size-offset, 1);
}
getmaxcu<<<1, 1>>>((cudanumbers), backup_size, offset);
offset+=thread_num;
}
hipMemcpy(max, cudanumbers, sizeof(unsigned int), hipMemcpyDeviceToHost);
err=hipGetLastError();
if(err!=hipSuccess){
printf("CUDA error: %s\n", hipGetErrorString(err));
exit(-1);
}
hipDeviceSynchronize();
hipFree(cudanumbers);
printf("CUDA returns: %d\n", *max);
//printf("Sequential returns: %u\n", getmax(numbers, backup_size));
free(numbers);
free(max);
exit(0);
}
/*
unsigned int getmax(unsigned int num[], unsigned int size)
{
unsigned int i, j;
unsigned int max = num[0];
for(i = 1; i < size; i++)
if(num[i] > max){
max = num[i];
j=i;
}
//printf("Sequential found max at %d\n", j);
return max;
}
__global__ void printArray(unsigned int arr[], unsigned int length, unsigned int jump){
for(int i = 0; i+jump<length; i++)
printf("%d: %d\n", i+jump, arr[i+jump]);
}
void search(unsigned int arr[], unsigned int size, unsigned int target){
printf("CUDA found max at");
for(int i = 1; i < size; i++)
if(arr[i] == target)
printf(" %d ", i);
printf("\n");
}
*/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <hip/hip_runtime.h>
__global__ void getmaxcu(unsigned int num[], unsigned int size, unsigned int gap)
{
unsigned int i=gap, //loop variables
start = (threadIdx.x)*gap;
if(start%2!=0 || size<=0)
return;
else{
//bottom-up tree search
while(start+i<size && start%(2*i)==0){
if(num[start]<num[start+i])
num[start]=num[start+i];
i*=2;
__syncthreads();
}
}
}
int main(int argc, char *argv[])
{
if(argc !=2)
{
printf("usage: maxgpu num\n");
printf("num = size of the array\n");
exit(1);
}
hipError_t err; // error var
unsigned int size = 0, backup_size, // The size of array
thread_num,
i; // loop index
struct hipDeviceProp_t prop; // specs
unsigned int *numbers, *cudanumbers, // pointers to array
*max=(unsigned int *)malloc(sizeof(unsigned int)); // pointers to max number
size = atol(argv[1]);
backup_size=size;
numbers = (unsigned int *)malloc(size * sizeof(unsigned int));
if(!numbers)
{
printf("Unable to allocate mem for an array of size %u\n", size);
exit(1);
}
srand(time(NULL)); // setting a seed for the random number generator
// Fill-up the array with random numbers from 0 to size-1
for( i = 0; i < size; i++)
numbers[i] = rand() % size;
hipGetDeviceProperties(&prop, 0);
hipMalloc((void**)&cudanumbers, size * sizeof(unsigned int));
hipMemcpy(cudanumbers, numbers, size * sizeof(unsigned int), hipMemcpyHostToDevice);
thread_num=ceil(prop.maxThreadsPerBlock/32)*32;
unsigned int offset=0;
i=0;
//search 1024 elements at once; search remaining elements
//structure: |----1024----| |----1024----| ... |size%1024| left to right
while(offset<backup_size){
if(backup_size-offset>=thread_num){
getmaxcu<<<1, thread_num>>>((cudanumbers+offset), thread_num, 1);
}
else{
getmaxcu<<<1, backup_size-offset>>>((cudanumbers+offset), backup_size-offset, 1);
}
getmaxcu<<<1, 1>>>((cudanumbers), backup_size, offset);
offset+=thread_num;
}
hipMemcpy(max, cudanumbers, sizeof(unsigned int), hipMemcpyDeviceToHost);
err=hipGetLastError();
if(err!=hipSuccess){
printf("CUDA error: %s\n", hipGetErrorString(err));
exit(-1);
}
hipDeviceSynchronize();
hipFree(cudanumbers);
printf("CUDA returns: %d\n", *max);
//printf("Sequential returns: %u\n", getmax(numbers, backup_size));
free(numbers);
free(max);
exit(0);
}
/*
unsigned int getmax(unsigned int num[], unsigned int size)
{
unsigned int i, j;
unsigned int max = num[0];
for(i = 1; i < size; i++)
if(num[i] > max){
max = num[i];
j=i;
}
//printf("Sequential found max at %d\n", j);
return max;
}
__global__ void printArray(unsigned int arr[], unsigned int length, unsigned int jump){
for(int i = 0; i+jump<length; i++)
printf("%d: %d\n", i+jump, arr[i+jump]);
}
void search(unsigned int arr[], unsigned int size, unsigned int target){
printf("CUDA found max at");
for(int i = 1; i < size; i++)
if(arr[i] == target)
printf(" %d ", i);
printf("\n");
}
*/ | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8getmaxcuPjjj
.globl _Z8getmaxcuPjjj
.p2align 8
.type _Z8getmaxcuPjjj,@function
_Z8getmaxcuPjjj:
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v0, v0, s3
s_cmp_lg_u32 s2, 0
s_cselect_b32 s4, -1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, 1, v0
v_cmp_eq_u32_e32 vcc_lo, 0, v1
s_and_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v2, s3, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s2, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_8
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v3, 0
s_mov_b32 s4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v1, v3
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_branch .LBB0_5
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v2, s3, v0
s_and_not1_b32 s5, s5, exec_lo
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmp_le_u32_e32 vcc_lo, s2, v2
s_and_b32 s7, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s5, s5, s7
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s6, exec_lo, s5
s_or_b32 s4, s6, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB0_8
.LBB0_5:
s_lshl_b32 s3, s3, 1
s_or_b32 s5, s5, exec_lo
v_cvt_f32_u32_e32 v1, s3
s_sub_i32 s6, 0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v6, s6, v1
s_mov_b32 s6, exec_lo
v_mul_hi_u32 v6, v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v6
v_mul_hi_u32 v1, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v1, s3
v_sub_nc_u32_e32 v1, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s3, v1
v_cmp_le_u32_e32 vcc_lo, s3, v1
v_cndmask_b32_e32 v1, v1, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s3, v1
v_cmp_le_u32_e32 vcc_lo, s3, v1
v_cndmask_b32_e32 v1, v1, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB0_4
v_lshlrev_b64 v[1:2], 2, v[2:3]
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b32 v6, v[4:5], off
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_cmpx_lt_u32_e64 v6, v1
s_cbranch_execz .LBB0_3
global_store_b32 v[4:5], v1, off
s_branch .LBB0_3
.LBB0_8:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8getmaxcuPjjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8getmaxcuPjjj, .Lfunc_end0-_Z8getmaxcuPjjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8getmaxcuPjjj
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z8getmaxcuPjjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <hip/hip_runtime.h>
__global__ void getmaxcu(unsigned int num[], unsigned int size, unsigned int gap)
{
unsigned int i=gap, //loop variables
start = (threadIdx.x)*gap;
if(start%2!=0 || size<=0)
return;
else{
//bottom-up tree search
while(start+i<size && start%(2*i)==0){
if(num[start]<num[start+i])
num[start]=num[start+i];
i*=2;
__syncthreads();
}
}
}
int main(int argc, char *argv[])
{
if(argc !=2)
{
printf("usage: maxgpu num\n");
printf("num = size of the array\n");
exit(1);
}
hipError_t err; // error var
unsigned int size = 0, backup_size, // The size of array
thread_num,
i; // loop index
struct hipDeviceProp_t prop; // specs
unsigned int *numbers, *cudanumbers, // pointers to array
*max=(unsigned int *)malloc(sizeof(unsigned int)); // pointers to max number
size = atol(argv[1]);
backup_size=size;
numbers = (unsigned int *)malloc(size * sizeof(unsigned int));
if(!numbers)
{
printf("Unable to allocate mem for an array of size %u\n", size);
exit(1);
}
srand(time(NULL)); // setting a seed for the random number generator
// Fill-up the array with random numbers from 0 to size-1
for( i = 0; i < size; i++)
numbers[i] = rand() % size;
hipGetDeviceProperties(&prop, 0);
hipMalloc((void**)&cudanumbers, size * sizeof(unsigned int));
hipMemcpy(cudanumbers, numbers, size * sizeof(unsigned int), hipMemcpyHostToDevice);
thread_num=ceil(prop.maxThreadsPerBlock/32)*32;
unsigned int offset=0;
i=0;
//search 1024 elements at once; search remaining elements
//structure: |----1024----| |----1024----| ... |size%1024| left to right
while(offset<backup_size){
if(backup_size-offset>=thread_num){
getmaxcu<<<1, thread_num>>>((cudanumbers+offset), thread_num, 1);
}
else{
getmaxcu<<<1, backup_size-offset>>>((cudanumbers+offset), backup_size-offset, 1);
}
getmaxcu<<<1, 1>>>((cudanumbers), backup_size, offset);
offset+=thread_num;
}
hipMemcpy(max, cudanumbers, sizeof(unsigned int), hipMemcpyDeviceToHost);
err=hipGetLastError();
if(err!=hipSuccess){
printf("CUDA error: %s\n", hipGetErrorString(err));
exit(-1);
}
hipDeviceSynchronize();
hipFree(cudanumbers);
printf("CUDA returns: %d\n", *max);
//printf("Sequential returns: %u\n", getmax(numbers, backup_size));
free(numbers);
free(max);
exit(0);
}
/*
unsigned int getmax(unsigned int num[], unsigned int size)
{
unsigned int i, j;
unsigned int max = num[0];
for(i = 1; i < size; i++)
if(num[i] > max){
max = num[i];
j=i;
}
//printf("Sequential found max at %d\n", j);
return max;
}
__global__ void printArray(unsigned int arr[], unsigned int length, unsigned int jump){
for(int i = 0; i+jump<length; i++)
printf("%d: %d\n", i+jump, arr[i+jump]);
}
void search(unsigned int arr[], unsigned int size, unsigned int target){
printf("CUDA found max at");
for(int i = 1; i < size; i++)
if(arr[i] == target)
printf(" %d ", i);
printf("\n");
}
*/ | .text
.file "maxgpu.hip"
.globl _Z23__device_stub__getmaxcuPjjj # -- Begin function _Z23__device_stub__getmaxcuPjjj
.p2align 4, 0x90
.type _Z23__device_stub__getmaxcuPjjj,@function
_Z23__device_stub__getmaxcuPjjj: # @_Z23__device_stub__getmaxcuPjjj
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8getmaxcuPjjj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__getmaxcuPjjj, .Lfunc_end0-_Z23__device_stub__getmaxcuPjjj
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1608, %rsp # imm = 0x648
.cfi_def_cfa_offset 1664
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB1_18
# %bb.1:
movq %rsi, %rbx
movl $4, %edi
callq malloc
movq %rax, %r14
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movl %r15d, %r12d
shlq $2, %r12
movq %r12, %rdi
callq malloc
testq %rax, %rax
jne .LBB1_2
# %bb.19:
movl $.L.str.2, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB1_18:
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
movl $1, %edi
callq exit
.LBB1_2:
movq %rax, %r13
movq %r14, 120(%rsp) # 8-byte Spill
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
testl %r15d, %r15d
je .LBB1_5
# %bb.3: # %.lr.ph.preheader
movl %r15d, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorl %edx, %edx
divl %r15d
movl %edx, (%r13,%r14,4)
incq %r14
cmpq %r14, %rbx
jne .LBB1_4
.LBB1_5: # %._crit_edge
leaq 136(%rsp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r13, 112(%rsp) # 8-byte Spill
movq %r13, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl 456(%rsp), %eax
leal 31(%rax), %ebp
testl %eax, %eax
cmovnsl %eax, %ebp
testl %r15d, %r15d
jne .LBB1_6
.LBB1_16: # %._crit_edge91
movq 16(%rsp), %rsi
movl $4, %edx
movq 120(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB1_20
# %bb.17:
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
callq hipFree
movl (%rbx), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movq 112(%rsp), %rdi # 8-byte Reload
callq free
movq %rbx, %rdi
callq free
xorl %edi, %edi
callq exit
.LBB1_6: # %.lr.ph90
andl $-32, %ebp
movabsq $4294967297, %r12 # imm = 0x100000001
movl %ebp, %eax
addq %r12, %rax
decq %rax
movq %rax, 128(%rsp) # 8-byte Spill
movl %r15d, %r13d
movl %r15d, %r14d
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_15: # in Loop: Header=BB1_7 Depth=1
addl %ebp, %ebx
movl %r14d, %r13d
cmpl %r15d, %ebx
jae .LBB1_16
.LBB1_7: # =>This Inner Loop Header: Depth=1
subl %ebp, %r14d
jae .LBB1_8
# %bb.10: # in Loop: Header=BB1_7 Depth=1
movl %r13d, %eax
leaq (%r12,%rax), %rdx
decq %rdx
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_13
# %bb.11: # in Loop: Header=BB1_7 Depth=1
movl %ebx, %eax
shlq $2, %rax
addq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl %r13d, 12(%rsp)
jmp .LBB1_12
.p2align 4, 0x90
.LBB1_8: # in Loop: Header=BB1_7 Depth=1
movq %r12, %rdi
movl $1, %esi
movq 128(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_13
# %bb.9: # in Loop: Header=BB1_7 Depth=1
movl %ebx, %eax
shlq $2, %rax
addq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl %ebp, 12(%rsp)
.LBB1_12: # in Loop: Header=BB1_7 Depth=1
movl $1, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z8getmaxcuPjjj, %edi
leaq 80(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_13: # in Loop: Header=BB1_7 Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_15
# %bb.14: # in Loop: Header=BB1_7 Depth=1
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl %r15d, 12(%rsp)
movl %ebx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z8getmaxcuPjjj, %edi
leaq 80(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_15
.LBB1_20:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8getmaxcuPjjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8getmaxcuPjjj,@object # @_Z8getmaxcuPjjj
.section .rodata,"a",@progbits
.globl _Z8getmaxcuPjjj
.p2align 3, 0x0
_Z8getmaxcuPjjj:
.quad _Z23__device_stub__getmaxcuPjjj
.size _Z8getmaxcuPjjj, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Unable to allocate mem for an array of size %u\n"
.size .L.str.2, 48
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "CUDA error: %s\n"
.size .L.str.3, 16
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "CUDA returns: %d\n"
.size .L.str.4, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8getmaxcuPjjj"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "usage: maxgpu num"
.size .Lstr, 18
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "num = size of the array"
.size .Lstr.1, 24
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__getmaxcuPjjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8getmaxcuPjjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8getmaxcuPjjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ IMAD R0, R0, c[0x0][0x16c], RZ ; /* 0x00005b0000007a24 */
/* 0x001fca00078e02ff */
/*0030*/ LOP3.LUT R2, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100027812 */
/* 0x000fc800078ec0ff */
/*0040*/ ISETP.NE.U32.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fc80003f05070 */
/*0050*/ ISETP.EQ.OR P0, PT, RZ, c[0x0][0x168], !P0 ; /* 0x00005a00ff007a0c */
/* 0x000fda0004702670 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IADD3 R2, R0, c[0x0][0x16c], RZ ; /* 0x00005b0000027a10 */
/* 0x000fc80007ffe0ff */
/*0080*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06070 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*00b0*/ MOV R7, c[0x0][0x16c] ; /* 0x00005b0000077a02 */
/* 0x000fe20000000f00 */
/*00c0*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0002 */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00e0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0003 */
/*00f0*/ IMAD.SHL.U32 R7, R7, 0x2, RZ ; /* 0x0000000207077824 */
/* 0x000fc800078e00ff */
/*0100*/ I2F.U32.RP R8, R7 ; /* 0x0000000700087306 */
/* 0x000e220000209000 */
/*0110*/ IMAD.MOV R9, RZ, RZ, -R7 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a07 */
/*0120*/ ISETP.NE.U32.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fcc0003f25070 */
/*0130*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e240000001000 */
/*0140*/ IADD3 R4, R8, 0xffffffe, RZ ; /* 0x0ffffffe08047810 */
/* 0x001fcc0007ffe0ff */
/*0150*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0160*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0170*/ IMAD R9, R9, R5, RZ ; /* 0x0000000509097224 */
/* 0x002fd200078e02ff */
/*0180*/ IMAD.HI.U32 R5, R5, R9, R4 ; /* 0x0000000905057227 */
/* 0x000fcc00078e0004 */
/*0190*/ IMAD.HI.U32 R5, R5, R0, RZ ; /* 0x0000000005057227 */
/* 0x000fc800078e00ff */
/*01a0*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a05 */
/*01b0*/ IMAD R10, R7, R5, R0 ; /* 0x00000005070a7224 */
/* 0x000fca00078e0200 */
/*01c0*/ ISETP.GE.U32.AND P0, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x000fda0003f06070 */
/*01d0*/ @P0 IMAD.IADD R10, R10, 0x1, -R7 ; /* 0x000000010a0a0824 */
/* 0x000fca00078e0a07 */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x000fda0003f06070 */
/*01f0*/ @P0 IADD3 R10, -R7, R10, RZ ; /* 0x0000000a070a0210 */
/* 0x000fe40007ffe1ff */
/*0200*/ @!P1 LOP3.LUT R10, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff0a9212 */
/* 0x000fc800078e33ff */
/*0210*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f05270 */
/*0220*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0230*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0240*/ IMAD.WIDE.U32 R4, R6, R5, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fe400078e0005 */
/*0250*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea8000c1e1900 */
/*0260*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0270*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0280*/ ISETP.GE.U32.AND P0, PT, R6, R5, PT ; /* 0x000000050600720c */
/* 0x004fe40003f06070 */
/*0290*/ IADD3 R6, R0, R7, RZ ; /* 0x0000000700067210 */
/* 0x000fd60007ffe0ff */
/*02a0*/ @!P0 STG.E [R2.64], R5 ; /* 0x0000000502008986 */
/* 0x0001e8000c101904 */
/*02b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02c0*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fda0003f06070 */
/*02d0*/ @!P0 BRA 0xf0 ; /* 0xfffffe1000008947 */
/* 0x001fea000383ffff */
/*02e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02f0*/ BRA 0x2f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8getmaxcuPjjj
.globl _Z8getmaxcuPjjj
.p2align 8
.type _Z8getmaxcuPjjj,@function
_Z8getmaxcuPjjj:
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v0, v0, s3
s_cmp_lg_u32 s2, 0
s_cselect_b32 s4, -1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, 1, v0
v_cmp_eq_u32_e32 vcc_lo, 0, v1
s_and_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_8
v_add_nc_u32_e32 v2, s3, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u32_e32 vcc_lo, s2, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_8
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v3, 0
s_mov_b32 s4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v1, v3
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_branch .LBB0_5
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s7
v_add_nc_u32_e32 v2, s3, v0
s_and_not1_b32 s5, s5, exec_lo
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmp_le_u32_e32 vcc_lo, s2, v2
s_and_b32 s7, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s5, s5, s7
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s6, exec_lo, s5
s_or_b32 s4, s6, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB0_8
.LBB0_5:
s_lshl_b32 s3, s3, 1
s_or_b32 s5, s5, exec_lo
v_cvt_f32_u32_e32 v1, s3
s_sub_i32 s6, 0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v6, s6, v1
s_mov_b32 s6, exec_lo
v_mul_hi_u32 v6, v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v6
v_mul_hi_u32 v1, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v1, s3
v_sub_nc_u32_e32 v1, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s3, v1
v_cmp_le_u32_e32 vcc_lo, s3, v1
v_cndmask_b32_e32 v1, v1, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s3, v1
v_cmp_le_u32_e32 vcc_lo, s3, v1
v_cndmask_b32_e32 v1, v1, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB0_4
v_lshlrev_b64 v[1:2], 2, v[2:3]
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_clause 0x1
global_load_b32 v6, v[4:5], off
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_cmpx_lt_u32_e64 v6, v1
s_cbranch_execz .LBB0_3
global_store_b32 v[4:5], v1, off
s_branch .LBB0_3
.LBB0_8:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8getmaxcuPjjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8getmaxcuPjjj, .Lfunc_end0-_Z8getmaxcuPjjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8getmaxcuPjjj
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z8getmaxcuPjjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009e9f9_00000000-6_maxgpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z8getmaxcuPjjjPjjj
.type _Z29__device_stub__Z8getmaxcuPjjjPjjj, @function
_Z29__device_stub__Z8getmaxcuPjjjPjjj:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8getmaxcuPjjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z8getmaxcuPjjjPjjj, .-_Z29__device_stub__Z8getmaxcuPjjjPjjj
.globl _Z8getmaxcuPjjj
.type _Z8getmaxcuPjjj, @function
_Z8getmaxcuPjjj:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z8getmaxcuPjjjPjjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8getmaxcuPjjj, .-_Z8getmaxcuPjjj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "usage: maxgpu num\n"
.LC1:
.string "num = size of the array\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Unable to allocate mem for an array of size %u\n"
.section .rodata.str1.1
.LC4:
.string "CUDA error: %s\n"
.LC5:
.string "CUDA returns: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1096, %rsp
.cfi_def_cfa_offset 1152
movq %fs:40, %rax
movq %rax, 1080(%rsp)
xorl %eax, %eax
cmpl $2, %edi
je .L12
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L12:
movq %rsi, %rbx
movl $4, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %r12d
movl %eax, %r15d
salq $2, %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %r14
testq %rax, %rax
je .L28
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
testl %ebx, %ebx
je .L14
movq %r14, %rbp
leal -1(%rbx), %eax
leaq 4(%r14,%rax,4), %r13
.L15:
call rand@PLT
movl $0, %edx
divl %r12d
movl %edx, 0(%rbp)
addq $4, %rbp
cmpq %r13, %rbp
jne .L15
leaq 48(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
leaq 16(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl 368(%rsp), %eax
movl $32, %ecx
cltd
idivl %ecx
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd .LC3(%rip), %xmm0
cvttsd2siq %xmm0, %rbp
movl $0, %r13d
jmp .L21
.L28:
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L16:
movl %ebx, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L18:
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L20:
addl %ebp, %r13d
subl %ebp, %ebx
cmpl %r12d, %r13d
jnb .L23
.L21:
cmpl %ebp, %ebx
jb .L16
movl %ebp, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L18
movl %r13d, %eax
movq 16(%rsp), %rdx
leaq (%rdx,%rax,4), %rdi
movl $1, %edx
movl %ebp, %esi
call _Z29__device_stub__Z8getmaxcuPjjjPjjj
jmp .L18
.L29:
movl %r13d, %eax
movq 16(%rsp), %rdx
leaq (%rdx,%rax,4), %rdi
movl $1, %edx
movl %ebx, %esi
call _Z29__device_stub__Z8getmaxcuPjjjPjjj
jmp .L18
.L30:
movl %r13d, %edx
movl %r12d, %esi
movq 16(%rsp), %rdi
call _Z29__device_stub__Z8getmaxcuPjjjPjjj
jmp .L20
.L22:
call cudaThreadSynchronize@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rbx
movl (%rbx), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r14, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %edi
call exit@PLT
.L14:
leaq 48(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
leaq 16(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
.L23:
movl $2, %ecx
movl $4, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
je .L22
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z8getmaxcuPjjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z8getmaxcuPjjj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1077936128
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "maxgpu.hip"
.globl _Z23__device_stub__getmaxcuPjjj # -- Begin function _Z23__device_stub__getmaxcuPjjj
.p2align 4, 0x90
.type _Z23__device_stub__getmaxcuPjjj,@function
_Z23__device_stub__getmaxcuPjjj: # @_Z23__device_stub__getmaxcuPjjj
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8getmaxcuPjjj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__getmaxcuPjjj, .Lfunc_end0-_Z23__device_stub__getmaxcuPjjj
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1608, %rsp # imm = 0x648
.cfi_def_cfa_offset 1664
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB1_18
# %bb.1:
movq %rsi, %rbx
movl $4, %edi
callq malloc
movq %rax, %r14
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movl %r15d, %r12d
shlq $2, %r12
movq %r12, %rdi
callq malloc
testq %rax, %rax
jne .LBB1_2
# %bb.19:
movl $.L.str.2, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB1_18:
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
movl $1, %edi
callq exit
.LBB1_2:
movq %rax, %r13
movq %r14, 120(%rsp) # 8-byte Spill
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
testl %r15d, %r15d
je .LBB1_5
# %bb.3: # %.lr.ph.preheader
movl %r15d, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorl %edx, %edx
divl %r15d
movl %edx, (%r13,%r14,4)
incq %r14
cmpq %r14, %rbx
jne .LBB1_4
.LBB1_5: # %._crit_edge
leaq 136(%rsp), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r13, 112(%rsp) # 8-byte Spill
movq %r13, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl 456(%rsp), %eax
leal 31(%rax), %ebp
testl %eax, %eax
cmovnsl %eax, %ebp
testl %r15d, %r15d
jne .LBB1_6
.LBB1_16: # %._crit_edge91
movq 16(%rsp), %rsi
movl $4, %edx
movq 120(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB1_20
# %bb.17:
callq hipDeviceSynchronize
movq 16(%rsp), %rdi
callq hipFree
movl (%rbx), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movq 112(%rsp), %rdi # 8-byte Reload
callq free
movq %rbx, %rdi
callq free
xorl %edi, %edi
callq exit
.LBB1_6: # %.lr.ph90
andl $-32, %ebp
movabsq $4294967297, %r12 # imm = 0x100000001
movl %ebp, %eax
addq %r12, %rax
decq %rax
movq %rax, 128(%rsp) # 8-byte Spill
movl %r15d, %r13d
movl %r15d, %r14d
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_15: # in Loop: Header=BB1_7 Depth=1
addl %ebp, %ebx
movl %r14d, %r13d
cmpl %r15d, %ebx
jae .LBB1_16
.LBB1_7: # =>This Inner Loop Header: Depth=1
subl %ebp, %r14d
jae .LBB1_8
# %bb.10: # in Loop: Header=BB1_7 Depth=1
movl %r13d, %eax
leaq (%r12,%rax), %rdx
decq %rdx
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_13
# %bb.11: # in Loop: Header=BB1_7 Depth=1
movl %ebx, %eax
shlq $2, %rax
addq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl %r13d, 12(%rsp)
jmp .LBB1_12
.p2align 4, 0x90
.LBB1_8: # in Loop: Header=BB1_7 Depth=1
movq %r12, %rdi
movl $1, %esi
movq 128(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_13
# %bb.9: # in Loop: Header=BB1_7 Depth=1
movl %ebx, %eax
shlq $2, %rax
addq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl %ebp, 12(%rsp)
.LBB1_12: # in Loop: Header=BB1_7 Depth=1
movl $1, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z8getmaxcuPjjj, %edi
leaq 80(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_13: # in Loop: Header=BB1_7 Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_15
# %bb.14: # in Loop: Header=BB1_7 Depth=1
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl %r15d, 12(%rsp)
movl %ebx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z8getmaxcuPjjj, %edi
leaq 80(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_15
.LBB1_20:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8getmaxcuPjjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8getmaxcuPjjj,@object # @_Z8getmaxcuPjjj
.section .rodata,"a",@progbits
.globl _Z8getmaxcuPjjj
.p2align 3, 0x0
_Z8getmaxcuPjjj:
.quad _Z23__device_stub__getmaxcuPjjj
.size _Z8getmaxcuPjjj, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Unable to allocate mem for an array of size %u\n"
.size .L.str.2, 48
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "CUDA error: %s\n"
.size .L.str.3, 16
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "CUDA returns: %d\n"
.size .L.str.4, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8getmaxcuPjjj"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "usage: maxgpu num"
.size .Lstr, 18
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "num = size of the array"
.size .Lstr.1, 24
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__getmaxcuPjjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8getmaxcuPjjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
It is instructive to compare zero-copy and unified memory. For the former, the memory is allocated in
page-locked fashion on the host. A device thread has to reach out to get the data. No guarantee of
coherence is provided as, for instance, the host could change the content of the pinned memory while the
device reads its content. For UM, the memory is allocated on the device and transparently made available
where needed. Specifically, upon a call to
cudaError_t cudaMallocManaged(void** devPtr, size_t size, unsigned int flag);
the user has, in devPtr, a pointer to an address of a chunk of device memory. This address can be
equally well manipulated on the device and the host (although, as illustrated below, not simultaneously).
Note that cudaMallocManaged and cudaMalloc are semantically identical; in fact, the former can be
used anywhere the latter is used.
UM enables a “single-pointer-to-data” memory model. For instance, the same pointer can be used on the
host in a memcpy operation to copy a set of integers to an array mA, and then on the device to alter, just
like in the code snippet above, the value of each entry in mA. The data in mA will be coherent as long as
the host does not touch entries in mA when the GPU executes a kernel. The host can safely operate
with/on mA only after a cudaDeviceSynchronize call. Failure to obey this rule will lead to a segfault,
as illustrated in the following example lifted from the CUDA Programming guide.
*/
#include <iostream>
#include <cmath>
const int ARRAY_SIZE = 1000;
__global__ void increment(double* aArray, double val, unsigned int sz) {
unsigned int indx = blockIdx.x * blockDim.x + threadIdx.x;
if (indx < sz)
aArray[indx] += val;
}
int main() {
double* mA;
cudaMallocManaged(&mA, ARRAY_SIZE * sizeof(double));
for (int i = 0; i < ARRAY_SIZE; i++)
mA[i] = 1.*i;
double inc_val = 2.0;
increment<<<2, 512>>>(mA, inc_val, ARRAY_SIZE);
cudaDeviceSynchronize();
double error = 0.;
for (int i = 0; i < ARRAY_SIZE; i++)
error += std::fabs(mA[i] - (i + inc_val));
for (int i=0;i<ARRAY_SIZE;++i){
std::cout<<mA[i]<<' ';
}
std::cout<<'\n';
std::cout << "Test: " << (error < 1.E-9 ? "Passed" : "Failed") << std::endl;
cudaFree(mA);
return 0;
} | code for sm_80
Function : _Z9incrementPddj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0003 */
/*0090*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1b00 */
/*00a0*/ DADD R4, R4, c[0x0][0x168] ; /* 0x00005a0004047629 */
/* 0x004e0e0000000000 */
/*00b0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe2000c101b04 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
It is instructive to compare zero-copy and unified memory. For the former, the memory is allocated in
page-locked fashion on the host. A device thread has to reach out to get the data. No guarantee of
coherence is provided as, for instance, the host could change the content of the pinned memory while the
device reads its content. For UM, the memory is allocated on the device and transparently made available
where needed. Specifically, upon a call to
cudaError_t cudaMallocManaged(void** devPtr, size_t size, unsigned int flag);
the user has, in devPtr, a pointer to an address of a chunk of device memory. This address can be
equally well manipulated on the device and the host (although, as illustrated below, not simultaneously).
Note that cudaMallocManaged and cudaMalloc are semantically identical; in fact, the former can be
used anywhere the latter is used.
UM enables a “single-pointer-to-data” memory model. For instance, the same pointer can be used on the
host in a memcpy operation to copy a set of integers to an array mA, and then on the device to alter, just
like in the code snippet above, the value of each entry in mA. The data in mA will be coherent as long as
the host does not touch entries in mA when the GPU executes a kernel. The host can safely operate
with/on mA only after a cudaDeviceSynchronize call. Failure to obey this rule will lead to a segfault,
as illustrated in the following example lifted from the CUDA Programming guide.
*/
#include <iostream>
#include <cmath>
const int ARRAY_SIZE = 1000;
__global__ void increment(double* aArray, double val, unsigned int sz) {
unsigned int indx = blockIdx.x * blockDim.x + threadIdx.x;
if (indx < sz)
aArray[indx] += val;
}
int main() {
double* mA;
cudaMallocManaged(&mA, ARRAY_SIZE * sizeof(double));
for (int i = 0; i < ARRAY_SIZE; i++)
mA[i] = 1.*i;
double inc_val = 2.0;
increment<<<2, 512>>>(mA, inc_val, ARRAY_SIZE);
cudaDeviceSynchronize();
double error = 0.;
for (int i = 0; i < ARRAY_SIZE; i++)
error += std::fabs(mA[i] - (i + inc_val));
for (int i=0;i<ARRAY_SIZE;++i){
std::cout<<mA[i]<<' ';
}
std::cout<<'\n';
std::cout << "Test: " << (error < 1.E-9 ? "Passed" : "Failed") << std::endl;
cudaFree(mA);
return 0;
} | .file "tmpxft_00112c52_00000000-6_unified_memory.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9incrementPddjPddj
.type _Z30__device_stub__Z9incrementPddjPddj, @function
_Z30__device_stub__Z9incrementPddjPddj:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movsd %xmm0, 16(%rsp)
movl %esi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9incrementPddj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z30__device_stub__Z9incrementPddjPddj, .-_Z30__device_stub__Z9incrementPddjPddj
.globl _Z9incrementPddj
.type _Z9incrementPddj, @function
_Z9incrementPddj:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9incrementPddjPddj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z9incrementPddj, .-_Z9incrementPddj
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Passed"
.LC2:
.string "Failed"
.LC5:
.string "Test: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
movl $1, %edx
movl $8000, %esi
call cudaMallocManaged@PLT
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movq 24(%rsp), %rdx
movsd %xmm0, (%rdx,%rax,8)
addq $1, %rax
cmpq $1000, %rax
jne .L12
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $2, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L13:
call cudaDeviceSynchronize@PLT
movq 24(%rsp), %rdx
movl $0, %eax
movq $0x000000000, 8(%rsp)
movsd .LC3(%rip), %xmm3
movq .LC4(%rip), %xmm2
.L14:
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
addsd %xmm3, %xmm1
movsd (%rdx,%rax,8), %xmm0
subsd %xmm1, %xmm0
andpd %xmm2, %xmm0
addsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
addq $1, %rax
cmpq $1000, %rax
jne .L14
movl $0, %ebx
leaq _ZSt4cout(%rip), %rbp
jmp .L17
.L27:
movl $1000, %esi
movsd .LC3(%rip), %xmm0
movq 24(%rsp), %rdi
call _Z30__device_stub__Z9incrementPddjPddj
jmp .L13
.L15:
movl $32, %esi
call _ZNSo3putEc@PLT
.L16:
addq $8, %rbx
cmpq $8000, %rbx
je .L28
.L17:
movq 24(%rsp), %rax
movsd (%rax,%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movb $32, 44(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L15
leaq 44(%rsp), %rsi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L16
.L28:
movl $10, %esi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
leaq .LC5(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd .LC6(%rip), %xmm0
comisd 8(%rsp), %xmm0
leaq .LC1(%rip), %rsi
leaq .LC2(%rip), %rax
cmovbe %rax, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z9incrementPddj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z9incrementPddj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1073741824
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC6:
.long -400107883
.long 1041313291
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
It is instructive to compare zero-copy and unified memory. For the former, the memory is allocated in
page-locked fashion on the host. A device thread has to reach out to get the data. No guarantee of
coherence is provided as, for instance, the host could change the content of the pinned memory while the
device reads its content. For UM, the memory is allocated on the device and transparently made available
where needed. Specifically, upon a call to
cudaError_t cudaMallocManaged(void** devPtr, size_t size, unsigned int flag);
the user has, in devPtr, a pointer to an address of a chunk of device memory. This address can be
equally well manipulated on the device and the host (although, as illustrated below, not simultaneously).
Note that cudaMallocManaged and cudaMalloc are semantically identical; in fact, the former can be
used anywhere the latter is used.
UM enables a “single-pointer-to-data” memory model. For instance, the same pointer can be used on the
host in a memcpy operation to copy a set of integers to an array mA, and then on the device to alter, just
like in the code snippet above, the value of each entry in mA. The data in mA will be coherent as long as
the host does not touch entries in mA when the GPU executes a kernel. The host can safely operate
with/on mA only after a cudaDeviceSynchronize call. Failure to obey this rule will lead to a segfault,
as illustrated in the following example lifted from the CUDA Programming guide.
*/
#include <iostream>
#include <cmath>
const int ARRAY_SIZE = 1000;
__global__ void increment(double* aArray, double val, unsigned int sz) {
unsigned int indx = blockIdx.x * blockDim.x + threadIdx.x;
if (indx < sz)
aArray[indx] += val;
}
int main() {
double* mA;
cudaMallocManaged(&mA, ARRAY_SIZE * sizeof(double));
for (int i = 0; i < ARRAY_SIZE; i++)
mA[i] = 1.*i;
double inc_val = 2.0;
increment<<<2, 512>>>(mA, inc_val, ARRAY_SIZE);
cudaDeviceSynchronize();
double error = 0.;
for (int i = 0; i < ARRAY_SIZE; i++)
error += std::fabs(mA[i] - (i + inc_val));
for (int i=0;i<ARRAY_SIZE;++i){
std::cout<<mA[i]<<' ';
}
std::cout<<'\n';
std::cout << "Test: " << (error < 1.E-9 ? "Passed" : "Failed") << std::endl;
cudaFree(mA);
return 0;
} | /*
It is instructive to compare zero-copy and unified memory. For the former, the memory is allocated in
page-locked fashion on the host. A device thread has to reach out to get the data. No guarantee of
coherence is provided as, for instance, the host could change the content of the pinned memory while the
device reads its content. For UM, the memory is allocated on the device and transparently made available
where needed. Specifically, upon a call to
cudaError_t cudaMallocManaged(void** devPtr, size_t size, unsigned int flag);
the user has, in devPtr, a pointer to an address of a chunk of device memory. This address can be
equally well manipulated on the device and the host (although, as illustrated below, not simultaneously).
Note that cudaMallocManaged and cudaMalloc are semantically identical; in fact, the former can be
used anywhere the latter is used.
UM enables a “single-pointer-to-data” memory model. For instance, the same pointer can be used on the
host in a memcpy operation to copy a set of integers to an array mA, and then on the device to alter, just
like in the code snippet above, the value of each entry in mA. The data in mA will be coherent as long as
the host does not touch entries in mA when the GPU executes a kernel. The host can safely operate
with/on mA only after a cudaDeviceSynchronize call. Failure to obey this rule will lead to a segfault,
as illustrated in the following example lifted from the CUDA Programming guide.
*/
#include <hip/hip_runtime.h>
#include <iostream>
#include <cmath>
const int ARRAY_SIZE = 1000;
__global__ void increment(double* aArray, double val, unsigned int sz) {
unsigned int indx = blockIdx.x * blockDim.x + threadIdx.x;
if (indx < sz)
aArray[indx] += val;
}
int main() {
double* mA;
hipMallocManaged(&mA, ARRAY_SIZE * sizeof(double));
for (int i = 0; i < ARRAY_SIZE; i++)
mA[i] = 1.*i;
double inc_val = 2.0;
increment<<<2, 512>>>(mA, inc_val, ARRAY_SIZE);
hipDeviceSynchronize();
double error = 0.;
for (int i = 0; i < ARRAY_SIZE; i++)
error += std::fabs(mA[i] - (i + inc_val));
for (int i=0;i<ARRAY_SIZE;++i){
std::cout<<mA[i]<<' ';
}
std::cout<<'\n';
std::cout << "Test: " << (error < 1.E-9 ? "Passed" : "Failed") << std::endl;
hipFree(mA);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
It is instructive to compare zero-copy and unified memory. For the former, the memory is allocated in
page-locked fashion on the host. A device thread has to reach out to get the data. No guarantee of
coherence is provided as, for instance, the host could change the content of the pinned memory while the
device reads its content. For UM, the memory is allocated on the device and transparently made available
where needed. Specifically, upon a call to
cudaError_t cudaMallocManaged(void** devPtr, size_t size, unsigned int flag);
the user has, in devPtr, a pointer to an address of a chunk of device memory. This address can be
equally well manipulated on the device and the host (although, as illustrated below, not simultaneously).
Note that cudaMallocManaged and cudaMalloc are semantically identical; in fact, the former can be
used anywhere the latter is used.
UM enables a “single-pointer-to-data” memory model. For instance, the same pointer can be used on the
host in a memcpy operation to copy a set of integers to an array mA, and then on the device to alter, just
like in the code snippet above, the value of each entry in mA. The data in mA will be coherent as long as
the host does not touch entries in mA when the GPU executes a kernel. The host can safely operate
with/on mA only after a cudaDeviceSynchronize call. Failure to obey this rule will lead to a segfault,
as illustrated in the following example lifted from the CUDA Programming guide.
*/
#include <hip/hip_runtime.h>
#include <iostream>
#include <cmath>
const int ARRAY_SIZE = 1000;
__global__ void increment(double* aArray, double val, unsigned int sz) {
unsigned int indx = blockIdx.x * blockDim.x + threadIdx.x;
if (indx < sz)
aArray[indx] += val;
}
int main() {
double* mA;
hipMallocManaged(&mA, ARRAY_SIZE * sizeof(double));
for (int i = 0; i < ARRAY_SIZE; i++)
mA[i] = 1.*i;
double inc_val = 2.0;
increment<<<2, 512>>>(mA, inc_val, ARRAY_SIZE);
hipDeviceSynchronize();
double error = 0.;
for (int i = 0; i < ARRAY_SIZE; i++)
error += std::fabs(mA[i] - (i + inc_val));
for (int i=0;i<ARRAY_SIZE;++i){
std::cout<<mA[i]<<' ';
}
std::cout<<'\n';
std::cout << "Test: " << (error < 1.E-9 ? "Passed" : "Failed") << std::endl;
hipFree(mA);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9incrementPddj
.globl _Z9incrementPddj
.p2align 8
.type _Z9incrementPddj,@function
_Z9incrementPddj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], s[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9incrementPddj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9incrementPddj, .Lfunc_end0-_Z9incrementPddj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9incrementPddj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9incrementPddj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
It is instructive to compare zero-copy and unified memory. For the former, the memory is allocated in
page-locked fashion on the host. A device thread has to reach out to get the data. No guarantee of
coherence is provided as, for instance, the host could change the content of the pinned memory while the
device reads its content. For UM, the memory is allocated on the device and transparently made available
where needed. Specifically, upon a call to
cudaError_t cudaMallocManaged(void** devPtr, size_t size, unsigned int flag);
the user has, in devPtr, a pointer to an address of a chunk of device memory. This address can be
equally well manipulated on the device and the host (although, as illustrated below, not simultaneously).
Note that cudaMallocManaged and cudaMalloc are semantically identical; in fact, the former can be
used anywhere the latter is used.
UM enables a “single-pointer-to-data” memory model. For instance, the same pointer can be used on the
host in a memcpy operation to copy a set of integers to an array mA, and then on the device to alter, just
like in the code snippet above, the value of each entry in mA. The data in mA will be coherent as long as
the host does not touch entries in mA when the GPU executes a kernel. The host can safely operate
with/on mA only after a cudaDeviceSynchronize call. Failure to obey this rule will lead to a segfault,
as illustrated in the following example lifted from the CUDA Programming guide.
*/
#include <hip/hip_runtime.h>
#include <iostream>
#include <cmath>
const int ARRAY_SIZE = 1000;
__global__ void increment(double* aArray, double val, unsigned int sz) {
unsigned int indx = blockIdx.x * blockDim.x + threadIdx.x;
if (indx < sz)
aArray[indx] += val;
}
int main() {
double* mA;
hipMallocManaged(&mA, ARRAY_SIZE * sizeof(double));
for (int i = 0; i < ARRAY_SIZE; i++)
mA[i] = 1.*i;
double inc_val = 2.0;
increment<<<2, 512>>>(mA, inc_val, ARRAY_SIZE);
hipDeviceSynchronize();
double error = 0.;
for (int i = 0; i < ARRAY_SIZE; i++)
error += std::fabs(mA[i] - (i + inc_val));
for (int i=0;i<ARRAY_SIZE;++i){
std::cout<<mA[i]<<' ';
}
std::cout<<'\n';
std::cout << "Test: " << (error < 1.E-9 ? "Passed" : "Failed") << std::endl;
hipFree(mA);
return 0;
} | .text
.file "unified_memory.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__incrementPddj # -- Begin function _Z24__device_stub__incrementPddj
.p2align 4, 0x90
.type _Z24__device_stub__incrementPddj,@function
_Z24__device_stub__incrementPddj: # @_Z24__device_stub__incrementPddj
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movsd %xmm0, 64(%rsp)
movl %esi, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9incrementPddj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__incrementPddj, .Lfunc_end0-_Z24__device_stub__incrementPddj
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x3e112e0be826d695 # double 1.0000000000000001E-9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $120, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsp, %rdi
movl $8000, %esi # imm = 0x1F40
movl $1, %edx
callq hipMallocManaged
xorl %eax, %eax
movq (%rsp), %rcx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%rcx,%rax,8)
incq %rax
cmpq $1000, %rax # imm = 0x3E8
jne .LBB1_1
# %bb.2:
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 510(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq (%rsp), %rax
movq %rax, 112(%rsp)
movabsq $4611686018427387904, %rax # imm = 0x4000000000000000
movq %rax, 104(%rsp)
movl $1000, 12(%rsp) # imm = 0x3E8
leaq 112(%rsp), %rax
movq %rax, 16(%rsp)
leaq 104(%rsp), %rax
movq %rax, 24(%rsp)
leaq 12(%rsp), %rax
movq %rax, 32(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z9incrementPddj, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
xorpd %xmm3, %xmm3
xorl %eax, %eax
movq (%rsp), %rcx
movapd .LCPI1_0(%rip), %xmm0 # xmm0 = [NaN,NaN]
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movsd (%rcx,%rax,8), %xmm1 # xmm1 = mem[0],zero
leal 2(%rax), %edx
xorps %xmm2, %xmm2
cvtsi2sd %edx, %xmm2
subsd %xmm2, %xmm1
andpd %xmm0, %xmm1
addsd %xmm1, %xmm3
incq %rax
cmpq $1000, %rax # imm = 0x3E8
jne .LBB1_5
# %bb.6: # %.preheader.preheader
movsd %xmm3, 48(%rsp) # 8-byte Spill
xorl %r14d, %r14d
leaq 16(%rsp), %rbx
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_17: # in Loop: Header=BB1_7 Depth=1
movq %rax, %rdi
movl $32, %esi
callq _ZNSo3putEc
.LBB1_18: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit22
# in Loop: Header=BB1_7 Depth=1
incq %r14
cmpq $1000, %r14 # imm = 0x3E8
je .LBB1_9
.LBB1_7: # %.preheader
# =>This Inner Loop Header: Depth=1
movq (%rsp), %rax
movsd (%rax,%r14,8), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movb $32, 16(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB1_17
# %bb.8: # in Loop: Header=BB1_7 Depth=1
movl $1, %edx
movq %rax, %rdi
movq %rbx, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_18
.LBB1_9:
movb $10, 16(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB1_11
# %bb.10:
leaq 16(%rsp), %rsi
movl $_ZSt4cout, %edi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_12
.LBB1_11:
movl $_ZSt4cout, %edi
movl $10, %esi
callq _ZNSo3putEc
.LBB1_12: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd .LCPI1_1(%rip), %xmm0 # xmm0 = mem[0],zero
ucomisd 48(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.1, %eax
movl $.L.str.2, %esi
cmovaq %rax, %rsi
movl $_ZSt4cout, %edi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_19
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_15
# %bb.14:
movzbl 67(%rbx), %eax
jmp .LBB1_16
.LBB1_15:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_19:
.cfi_def_cfa_offset 144
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9incrementPddj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9incrementPddj,@object # @_Z9incrementPddj
.section .rodata,"a",@progbits
.globl _Z9incrementPddj
.p2align 3, 0x0
_Z9incrementPddj:
.quad _Z24__device_stub__incrementPddj
.size _Z9incrementPddj, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Test: "
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Passed"
.size .L.str.1, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed"
.size .L.str.2, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9incrementPddj"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__incrementPddj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9incrementPddj
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9incrementPddj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0003 */
/*0090*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1b00 */
/*00a0*/ DADD R4, R4, c[0x0][0x168] ; /* 0x00005a0004047629 */
/* 0x004e0e0000000000 */
/*00b0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe2000c101b04 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9incrementPddj
.globl _Z9incrementPddj
.p2align 8
.type _Z9incrementPddj,@function
_Z9incrementPddj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], s[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9incrementPddj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9incrementPddj, .Lfunc_end0-_Z9incrementPddj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9incrementPddj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9incrementPddj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00112c52_00000000-6_unified_memory.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9incrementPddjPddj
.type _Z30__device_stub__Z9incrementPddjPddj, @function
_Z30__device_stub__Z9incrementPddjPddj:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movsd %xmm0, 16(%rsp)
movl %esi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9incrementPddj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z30__device_stub__Z9incrementPddjPddj, .-_Z30__device_stub__Z9incrementPddjPddj
.globl _Z9incrementPddj
.type _Z9incrementPddj, @function
_Z9incrementPddj:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9incrementPddjPddj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z9incrementPddj, .-_Z9incrementPddj
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Passed"
.LC2:
.string "Failed"
.LC5:
.string "Test: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
movl $1, %edx
movl $8000, %esi
call cudaMallocManaged@PLT
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movq 24(%rsp), %rdx
movsd %xmm0, (%rdx,%rax,8)
addq $1, %rax
cmpq $1000, %rax
jne .L12
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $2, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L13:
call cudaDeviceSynchronize@PLT
movq 24(%rsp), %rdx
movl $0, %eax
movq $0x000000000, 8(%rsp)
movsd .LC3(%rip), %xmm3
movq .LC4(%rip), %xmm2
.L14:
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
addsd %xmm3, %xmm1
movsd (%rdx,%rax,8), %xmm0
subsd %xmm1, %xmm0
andpd %xmm2, %xmm0
addsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
addq $1, %rax
cmpq $1000, %rax
jne .L14
movl $0, %ebx
leaq _ZSt4cout(%rip), %rbp
jmp .L17
.L27:
movl $1000, %esi
movsd .LC3(%rip), %xmm0
movq 24(%rsp), %rdi
call _Z30__device_stub__Z9incrementPddjPddj
jmp .L13
.L15:
movl $32, %esi
call _ZNSo3putEc@PLT
.L16:
addq $8, %rbx
cmpq $8000, %rbx
je .L28
.L17:
movq 24(%rsp), %rax
movsd (%rax,%rbx), %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movb $32, 44(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L15
leaq 44(%rsp), %rsi
movl $1, %edx
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L16
.L28:
movl $10, %esi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
leaq .LC5(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd .LC6(%rip), %xmm0
comisd 8(%rsp), %xmm0
leaq .LC1(%rip), %rsi
leaq .LC2(%rip), %rax
cmovbe %rax, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z9incrementPddj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z9incrementPddj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1073741824
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long -1
.long 2147483647
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC6:
.long -400107883
.long 1041313291
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "unified_memory.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__incrementPddj # -- Begin function _Z24__device_stub__incrementPddj
.p2align 4, 0x90
.type _Z24__device_stub__incrementPddj,@function
_Z24__device_stub__incrementPddj: # @_Z24__device_stub__incrementPddj
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movsd %xmm0, 64(%rsp)
movl %esi, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9incrementPddj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__incrementPddj, .Lfunc_end0-_Z24__device_stub__incrementPddj
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x3e112e0be826d695 # double 1.0000000000000001E-9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $120, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsp, %rdi
movl $8000, %esi # imm = 0x1F40
movl $1, %edx
callq hipMallocManaged
xorl %eax, %eax
movq (%rsp), %rcx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%rcx,%rax,8)
incq %rax
cmpq $1000, %rax # imm = 0x3E8
jne .LBB1_1
# %bb.2:
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 510(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq (%rsp), %rax
movq %rax, 112(%rsp)
movabsq $4611686018427387904, %rax # imm = 0x4000000000000000
movq %rax, 104(%rsp)
movl $1000, 12(%rsp) # imm = 0x3E8
leaq 112(%rsp), %rax
movq %rax, 16(%rsp)
leaq 104(%rsp), %rax
movq %rax, 24(%rsp)
leaq 12(%rsp), %rax
movq %rax, 32(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z9incrementPddj, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
xorpd %xmm3, %xmm3
xorl %eax, %eax
movq (%rsp), %rcx
movapd .LCPI1_0(%rip), %xmm0 # xmm0 = [NaN,NaN]
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movsd (%rcx,%rax,8), %xmm1 # xmm1 = mem[0],zero
leal 2(%rax), %edx
xorps %xmm2, %xmm2
cvtsi2sd %edx, %xmm2
subsd %xmm2, %xmm1
andpd %xmm0, %xmm1
addsd %xmm1, %xmm3
incq %rax
cmpq $1000, %rax # imm = 0x3E8
jne .LBB1_5
# %bb.6: # %.preheader.preheader
movsd %xmm3, 48(%rsp) # 8-byte Spill
xorl %r14d, %r14d
leaq 16(%rsp), %rbx
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_17: # in Loop: Header=BB1_7 Depth=1
movq %rax, %rdi
movl $32, %esi
callq _ZNSo3putEc
.LBB1_18: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit22
# in Loop: Header=BB1_7 Depth=1
incq %r14
cmpq $1000, %r14 # imm = 0x3E8
je .LBB1_9
.LBB1_7: # %.preheader
# =>This Inner Loop Header: Depth=1
movq (%rsp), %rax
movsd (%rax,%r14,8), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movb $32, 16(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB1_17
# %bb.8: # in Loop: Header=BB1_7 Depth=1
movl $1, %edx
movq %rax, %rdi
movq %rbx, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_18
.LBB1_9:
movb $10, 16(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB1_11
# %bb.10:
leaq 16(%rsp), %rsi
movl $_ZSt4cout, %edi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_12
.LBB1_11:
movl $_ZSt4cout, %edi
movl $10, %esi
callq _ZNSo3putEc
.LBB1_12: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd .LCPI1_1(%rip), %xmm0 # xmm0 = mem[0],zero
ucomisd 48(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.1, %eax
movl $.L.str.2, %esi
cmovaq %rax, %rsi
movl $_ZSt4cout, %edi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_19
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_15
# %bb.14:
movzbl 67(%rbx), %eax
jmp .LBB1_16
.LBB1_15:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_19:
.cfi_def_cfa_offset 144
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9incrementPddj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9incrementPddj,@object # @_Z9incrementPddj
.section .rodata,"a",@progbits
.globl _Z9incrementPddj
.p2align 3, 0x0
_Z9incrementPddj:
.quad _Z24__device_stub__incrementPddj
.size _Z9incrementPddj, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Test: "
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Passed"
.size .L.str.1, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed"
.size .L.str.2, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9incrementPddj"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__incrementPddj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9incrementPddj
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
int main() {
int dimx = 10;
int num_bytes = dimx * sizeof (int);
// device and host pointers
int *d_a = 0;
int *h_a = 0;
/*Aloca memória na CPU para n inteiros*/
h_a = (int*) malloc(num_bytes);
printf("%i\n", num_bytes);
/*Aloca memória na GPU para n inteiros*/
cudaMalloc(&d_a, num_bytes);
if (0 == h_a || 0 == d_a) {
printf("couldn't allocate memory\n");
return 1;
}
cudaMemset(d_a, 0, num_bytes);
cudaMemcpy(h_a, d_a, num_bytes, cudaMemcpyDeviceToHost);
for (int i = 0; i < dimx; i++){
printf("%d ", i+1);
}
printf("\n");
free(h_a);
cudaFree(d_a);
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
int main() {
int dimx = 10;
int num_bytes = dimx * sizeof (int);
// device and host pointers
int *d_a = 0;
int *h_a = 0;
/*Aloca memória na CPU para n inteiros*/
h_a = (int*) malloc(num_bytes);
printf("%i\n", num_bytes);
/*Aloca memória na GPU para n inteiros*/
cudaMalloc(&d_a, num_bytes);
if (0 == h_a || 0 == d_a) {
printf("couldn't allocate memory\n");
return 1;
}
cudaMemset(d_a, 0, num_bytes);
cudaMemcpy(h_a, d_a, num_bytes, cudaMemcpyDeviceToHost);
for (int i = 0; i < dimx; i++){
printf("%d ", i+1);
}
printf("\n");
free(h_a);
cudaFree(d_a);
return 0;
} | .file "tmpxft_00024a09_00000000-6_cuda-code-1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%i\n"
.LC1:
.string "couldn't allocate memory\n"
.LC2:
.string "%d "
.LC3:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movl $40, %edi
call malloc@PLT
movq %rax, %r12
movl $40, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rdi
movl $40, %esi
call cudaMalloc@PLT
testq %r12, %r12
je .L4
movq (%rsp), %rdi
testq %rdi, %rdi
je .L4
movl $40, %edx
movl $0, %esi
call cudaMemset@PLT
movl $2, %ecx
movl $40, %edx
movq (%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC2(%rip), %rbp
.L7:
addl $1, %ebx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $10, %ebx
jne .L7
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
.L3:
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L11
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L3
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
int main() {
int dimx = 10;
int num_bytes = dimx * sizeof (int);
// device and host pointers
int *d_a = 0;
int *h_a = 0;
/*Aloca memória na CPU para n inteiros*/
h_a = (int*) malloc(num_bytes);
printf("%i\n", num_bytes);
/*Aloca memória na GPU para n inteiros*/
cudaMalloc(&d_a, num_bytes);
if (0 == h_a || 0 == d_a) {
printf("couldn't allocate memory\n");
return 1;
}
cudaMemset(d_a, 0, num_bytes);
cudaMemcpy(h_a, d_a, num_bytes, cudaMemcpyDeviceToHost);
for (int i = 0; i < dimx; i++){
printf("%d ", i+1);
}
printf("\n");
free(h_a);
cudaFree(d_a);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
int main() {
int dimx = 10;
int num_bytes = dimx * sizeof (int);
// device and host pointers
int *d_a = 0;
int *h_a = 0;
/*Aloca memória na CPU para n inteiros*/
h_a = (int*) malloc(num_bytes);
printf("%i\n", num_bytes);
/*Aloca memória na GPU para n inteiros*/
hipMalloc(&d_a, num_bytes);
if (0 == h_a || 0 == d_a) {
printf("couldn't allocate memory\n");
return 1;
}
hipMemset(d_a, 0, num_bytes);
hipMemcpy(h_a, d_a, num_bytes, hipMemcpyDeviceToHost);
for (int i = 0; i < dimx; i++){
printf("%d ", i+1);
}
printf("\n");
free(h_a);
hipFree(d_a);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
int main() {
int dimx = 10;
int num_bytes = dimx * sizeof (int);
// device and host pointers
int *d_a = 0;
int *h_a = 0;
/*Aloca memória na CPU para n inteiros*/
h_a = (int*) malloc(num_bytes);
printf("%i\n", num_bytes);
/*Aloca memória na GPU para n inteiros*/
hipMalloc(&d_a, num_bytes);
if (0 == h_a || 0 == d_a) {
printf("couldn't allocate memory\n");
return 1;
}
hipMemset(d_a, 0, num_bytes);
hipMemcpy(h_a, d_a, num_bytes, hipMemcpyDeviceToHost);
for (int i = 0; i < dimx; i++){
printf("%d ", i+1);
}
printf("\n");
free(h_a);
hipFree(d_a);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
int main() {
int dimx = 10;
int num_bytes = dimx * sizeof (int);
// device and host pointers
int *d_a = 0;
int *h_a = 0;
/*Aloca memória na CPU para n inteiros*/
h_a = (int*) malloc(num_bytes);
printf("%i\n", num_bytes);
/*Aloca memória na GPU para n inteiros*/
hipMalloc(&d_a, num_bytes);
if (0 == h_a || 0 == d_a) {
printf("couldn't allocate memory\n");
return 1;
}
hipMemset(d_a, 0, num_bytes);
hipMemcpy(h_a, d_a, num_bytes, hipMemcpyDeviceToHost);
for (int i = 0; i < dimx; i++){
printf("%d ", i+1);
}
printf("\n");
free(h_a);
hipFree(d_a);
return 0;
} | .text
.file "cuda-code-1.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movq $0, (%rsp)
movl $40, %edi
callq malloc
movq %rax, %rbx
movl $.L.str, %edi
movl $40, %esi
xorl %eax, %eax
callq printf
movq %rsp, %rdi
movl $40, %esi
callq hipMalloc
testq %rbx, %rbx
je .LBB0_2
# %bb.1:
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB0_2
# %bb.3:
movl $40, %edx
xorl %esi, %esi
callq hipMemset
movq (%rsp), %rsi
movl $40, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $1, %ebp
.p2align 4, 0x90
.LBB0_4: # =>This Inner Loop Header: Depth=1
movl $.L.str.2, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
incl %ebp
cmpl $11, %ebp
jne .LBB0_4
# %bb.5:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
jmp .LBB0_6
.LBB0_2:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %eax
.LBB0_6:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%i\n"
.size .L.str, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d "
.size .L.str.2, 4
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "couldn't allocate memory"
.size .Lstr, 25
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00024a09_00000000-6_cuda-code-1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%i\n"
.LC1:
.string "couldn't allocate memory\n"
.LC2:
.string "%d "
.LC3:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movl $40, %edi
call malloc@PLT
movq %rax, %r12
movl $40, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rdi
movl $40, %esi
call cudaMalloc@PLT
testq %r12, %r12
je .L4
movq (%rsp), %rdi
testq %rdi, %rdi
je .L4
movl $40, %edx
movl $0, %esi
call cudaMemset@PLT
movl $2, %ecx
movl $40, %edx
movq (%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC2(%rip), %rbp
.L7:
addl $1, %ebx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $10, %ebx
jne .L7
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
.L3:
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L11
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L3
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda-code-1.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movq $0, (%rsp)
movl $40, %edi
callq malloc
movq %rax, %rbx
movl $.L.str, %edi
movl $40, %esi
xorl %eax, %eax
callq printf
movq %rsp, %rdi
movl $40, %esi
callq hipMalloc
testq %rbx, %rbx
je .LBB0_2
# %bb.1:
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB0_2
# %bb.3:
movl $40, %edx
xorl %esi, %esi
callq hipMemset
movq (%rsp), %rsi
movl $40, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $1, %ebp
.p2align 4, 0x90
.LBB0_4: # =>This Inner Loop Header: Depth=1
movl $.L.str.2, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
incl %ebp
cmpl $11, %ebp
jne .LBB0_4
# %bb.5:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
jmp .LBB0_6
.LBB0_2:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %eax
.LBB0_6:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%i\n"
.size .L.str, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d "
.size .L.str.2, 4
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "couldn't allocate memory"
.size .Lstr, 25
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // 1D stencil example using CUDA C++
#include <iostream>
// Global Parameters
#define NUMBLOCKS 8
#define BLOCKSIZE 4
#define RADIUS 1
#define NUMELEMENTS (NUMBLOCKS * BLOCKSIZE)
// Function and macro to handle CUDA errors
static void handleError(cudaError_t err, const char *file, int line) {
if (err != cudaSuccess) {
std::cout << cudaGetErrorString(err) << " in " << file << " at line " << line << std::endl;
exit(EXIT_FAILURE);
}
}
#define cudaCheck(err) (handleError(err, __FILE__, __LINE__))
// A 1D stencil reads in a block of an array, and adds up all elements within a stencil of fixed raduis
// and writes them to an output vector
__global__ void stencil1d(int *in, int *out) {
__shared__ int temp[BLOCKSIZE + 2*RADIUS];
int gindex = threadIdx.x + blockIdx.x * blockDim.x + RADIUS;
int lindex = threadIdx.x + RADIUS;
// Read in data corresponding to the actual block elements
temp[lindex] = in[gindex];
// Read in boundary-data ('halo' on either side, with length commensurate to the radius)
if (threadIdx.x < RADIUS) {
// Left halo
temp[lindex - RADIUS] = in[gindex - RADIUS];
// Right halo
temp[lindex + BLOCKSIZE] = in[gindex + BLOCKSIZE];
}
// Prevent WAR/RAW/WAW conflicts
__syncthreads();
// Apply the stencil
int result = 0;
for (int offset = -RADIUS; offset <= RADIUS; ++offset) {
result += temp[lindex + offset];
}
// Store the result
out[gindex-RADIUS] = result;
}
int main(void) {
// Initialize host copies of in, out
int in[NUMELEMENTS + 2*RADIUS], out[NUMELEMENTS];
for (int i = 0; i < NUMELEMENTS + 2*RADIUS; ++i) {
if (i < RADIUS) {
in[i] = 0;
} else if (i < NUMELEMENTS + RADIUS) {
in[i] = 1;
} else {
in[i] = 0;
}
}
// // Verify input by printing
// for (int i = 0; i < NUMELEMENTS + 2*RADIUS; ++i) {
// std::cout << in[i] << " ";
// }
// std::cout << std::endl;
// Sizes
int size_in = (NUMELEMENTS + 2*RADIUS) * sizeof(int);
int size_out = NUMELEMENTS * sizeof(int);
// Initialize device copies of in, out
int *d_in, *d_out;
cudaCheck(cudaMalloc((void **)&d_in, size_in));
cudaCheck(cudaMalloc((void **)&d_out, size_out));
// Copy variables from host to device
cudaCheck(cudaMemcpy(d_in, in, size_in, cudaMemcpyHostToDevice));
// Launch the kernel
stencil1d<<<NUMBLOCKS, BLOCKSIZE>>>(d_in, d_out);
// Check for kernel launch errors
cudaCheck(cudaPeekAtLastError());
// Copy variables from device to host
cudaCheck(cudaMemcpy(out, d_out, size_out, cudaMemcpyDeviceToHost));
// Print the result
for (int i = 0; i < NUMELEMENTS; ++i) {
std::cout << out[i] << " ";
}
std::cout << std::endl;
} | code for sm_80
Function : _Z9stencil1dPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e620000002500 */
/*0050*/ ISETP.NE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x001fe20003f05270 */
/*0060*/ IMAD R4, R4, c[0x0][0x0], R11 ; /* 0x0000000004047a24 */
/* 0x002fca00078e020b */
/*0070*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fca00078e0205 */
/*0080*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040402007981 */
/* 0x000ea8000c1e1900 */
/*0090*/ @!P0 LDG.E R6, [R2.64] ; /* 0x0000000402068981 */
/* 0x000ee8000c1e1900 */
/*00a0*/ @!P0 LDG.E R7, [R2.64+0x14] ; /* 0x0000140402078981 */
/* 0x000f22000c1e1900 */
/*00b0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc600078e0205 */
/*00c0*/ STS [R11.X4+0x4], R0 ; /* 0x000004000b007388 */
/* 0x004fe80000004800 */
/*00d0*/ @!P0 STS [RZ], R6 ; /* 0x00000006ff008388 */
/* 0x008fe80000000800 */
/*00e0*/ @!P0 STS [0x14], R7 ; /* 0x00001407ff008388 */
/* 0x010fe80000000800 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0100*/ LDS R8, [R11.X4+0x4] ; /* 0x000004000b087984 */
/* 0x000fe80000004800 */
/*0110*/ LDS R9, [R11.X4] ; /* 0x000000000b097984 */
/* 0x000fe80000004800 */
/*0120*/ LDS R10, [R11.X4+0x8] ; /* 0x000008000b0a7984 */
/* 0x000e240000004800 */
/*0130*/ IADD3 R9, R10, R8, R9 ; /* 0x000000080a097210 */
/* 0x001fca0007ffe009 */
/*0140*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // 1D stencil example using CUDA C++
#include <iostream>
// Global Parameters
#define NUMBLOCKS 8
#define BLOCKSIZE 4
#define RADIUS 1
#define NUMELEMENTS (NUMBLOCKS * BLOCKSIZE)
// Function and macro to handle CUDA errors
static void handleError(cudaError_t err, const char *file, int line) {
if (err != cudaSuccess) {
std::cout << cudaGetErrorString(err) << " in " << file << " at line " << line << std::endl;
exit(EXIT_FAILURE);
}
}
#define cudaCheck(err) (handleError(err, __FILE__, __LINE__))
// A 1D stencil reads in a block of an array, and adds up all elements within a stencil of fixed raduis
// and writes them to an output vector
__global__ void stencil1d(int *in, int *out) {
__shared__ int temp[BLOCKSIZE + 2*RADIUS];
int gindex = threadIdx.x + blockIdx.x * blockDim.x + RADIUS;
int lindex = threadIdx.x + RADIUS;
// Read in data corresponding to the actual block elements
temp[lindex] = in[gindex];
// Read in boundary-data ('halo' on either side, with length commensurate to the radius)
if (threadIdx.x < RADIUS) {
// Left halo
temp[lindex - RADIUS] = in[gindex - RADIUS];
// Right halo
temp[lindex + BLOCKSIZE] = in[gindex + BLOCKSIZE];
}
// Prevent WAR/RAW/WAW conflicts
__syncthreads();
// Apply the stencil
int result = 0;
for (int offset = -RADIUS; offset <= RADIUS; ++offset) {
result += temp[lindex + offset];
}
// Store the result
out[gindex-RADIUS] = result;
}
int main(void) {
// Initialize host copies of in, out
int in[NUMELEMENTS + 2*RADIUS], out[NUMELEMENTS];
for (int i = 0; i < NUMELEMENTS + 2*RADIUS; ++i) {
if (i < RADIUS) {
in[i] = 0;
} else if (i < NUMELEMENTS + RADIUS) {
in[i] = 1;
} else {
in[i] = 0;
}
}
// // Verify input by printing
// for (int i = 0; i < NUMELEMENTS + 2*RADIUS; ++i) {
// std::cout << in[i] << " ";
// }
// std::cout << std::endl;
// Sizes
int size_in = (NUMELEMENTS + 2*RADIUS) * sizeof(int);
int size_out = NUMELEMENTS * sizeof(int);
// Initialize device copies of in, out
int *d_in, *d_out;
cudaCheck(cudaMalloc((void **)&d_in, size_in));
cudaCheck(cudaMalloc((void **)&d_out, size_out));
// Copy variables from host to device
cudaCheck(cudaMemcpy(d_in, in, size_in, cudaMemcpyHostToDevice));
// Launch the kernel
stencil1d<<<NUMBLOCKS, BLOCKSIZE>>>(d_in, d_out);
// Check for kernel launch errors
cudaCheck(cudaPeekAtLastError());
// Copy variables from device to host
cudaCheck(cudaMemcpy(out, d_out, size_out, cudaMemcpyDeviceToHost));
// Print the result
for (int i = 0; i < NUMELEMENTS; ++i) {
std::cout << out[i] << " ";
}
std::cout << std::endl;
} | .file "tmpxft_000e7ac1_00000000-6_stencil1d.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " in "
.LC1:
.string " at line "
#NO_APP
.text
.type _ZL11handleError9cudaErrorPKci, @function
_ZL11handleError9cudaErrorPKci:
.LFB3669:
.cfi_startproc
testl %edi, %edi
jne .L6
ret
.L6:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbp
movl %edx, %ebx
call cudaGetErrorString@PLT
movq %rax, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _ZL11handleError9cudaErrorPKci, .-_ZL11handleError9cudaErrorPKci
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9stencil1dPiS_PiS_
.type _Z30__device_stub__Z9stencil1dPiS_PiS_, @function
_Z30__device_stub__Z9stencil1dPiS_PiS_:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9stencil1dPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z30__device_stub__Z9stencil1dPiS_PiS_, .-_Z30__device_stub__Z9stencil1dPiS_PiS_
.globl _Z9stencil1dPiS_
.type _Z9stencil1dPiS_, @function
_Z9stencil1dPiS_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9stencil1dPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z9stencil1dPiS_, .-_Z9stencil1dPiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/krrish94/learn-cuda/master/stencil1d.cu"
.section .rodata.str1.1
.LC3:
.string " "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $328, %rsp
.cfi_def_cfa_offset 368
movq %fs:40, %rax
movq %rax, 312(%rsp)
xorl %eax, %eax
movl $1, %ecx
jmp .L21
.L31:
movl $0, 308(%rsp)
leaq 8(%rsp), %rdi
movl $136, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $83, %edx
leaq .LC2(%rip), %rbx
movq %rbx, %rsi
call _ZL11handleError9cudaErrorPKci
leaq 16(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $84, %edx
movq %rbx, %rsi
call _ZL11handleError9cudaErrorPKci
leaq 176(%rsp), %rsi
movl $1, %ecx
movl $136, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $87, %edx
movq %rbx, %rsi
call _ZL11handleError9cudaErrorPKci
movl $4, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $8, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L19:
call cudaPeekAtLastError@PLT
movl %eax, %edi
movl $93, %edx
leaq .LC2(%rip), %rbp
movq %rbp, %rsi
call _ZL11handleError9cudaErrorPKci
leaq 48(%rsp), %rbx
movl $2, %ecx
movl $128, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $96, %edx
movq %rbp, %rsi
call _ZL11handleError9cudaErrorPKci
leaq 176(%rsp), %r13
leaq _ZSt4cout(%rip), %r12
leaq .LC3(%rip), %rbp
.L22:
movl (%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %rbp, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L22
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 312(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $328, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl $0, %edx
.L18:
movl %edx, 176(%rsp,%rax,4)
addq $1, %rax
.L21:
testl %eax, %eax
jle .L24
cmpl $32, %eax
jg .L31
movl %ecx, %edx
jmp .L18
.L29:
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z9stencil1dPiS_PiS_
jmp .L19
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z9stencil1dPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z9stencil1dPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // 1D stencil example using CUDA C++
#include <iostream>
// Global Parameters
#define NUMBLOCKS 8
#define BLOCKSIZE 4
#define RADIUS 1
#define NUMELEMENTS (NUMBLOCKS * BLOCKSIZE)
// Function and macro to handle CUDA errors
static void handleError(cudaError_t err, const char *file, int line) {
if (err != cudaSuccess) {
std::cout << cudaGetErrorString(err) << " in " << file << " at line " << line << std::endl;
exit(EXIT_FAILURE);
}
}
#define cudaCheck(err) (handleError(err, __FILE__, __LINE__))
// A 1D stencil reads in a block of an array, and adds up all elements within a stencil of fixed raduis
// and writes them to an output vector
__global__ void stencil1d(int *in, int *out) {
__shared__ int temp[BLOCKSIZE + 2*RADIUS];
int gindex = threadIdx.x + blockIdx.x * blockDim.x + RADIUS;
int lindex = threadIdx.x + RADIUS;
// Read in data corresponding to the actual block elements
temp[lindex] = in[gindex];
// Read in boundary-data ('halo' on either side, with length commensurate to the radius)
if (threadIdx.x < RADIUS) {
// Left halo
temp[lindex - RADIUS] = in[gindex - RADIUS];
// Right halo
temp[lindex + BLOCKSIZE] = in[gindex + BLOCKSIZE];
}
// Prevent WAR/RAW/WAW conflicts
__syncthreads();
// Apply the stencil
int result = 0;
for (int offset = -RADIUS; offset <= RADIUS; ++offset) {
result += temp[lindex + offset];
}
// Store the result
out[gindex-RADIUS] = result;
}
int main(void) {
// Initialize host copies of in, out
int in[NUMELEMENTS + 2*RADIUS], out[NUMELEMENTS];
for (int i = 0; i < NUMELEMENTS + 2*RADIUS; ++i) {
if (i < RADIUS) {
in[i] = 0;
} else if (i < NUMELEMENTS + RADIUS) {
in[i] = 1;
} else {
in[i] = 0;
}
}
// // Verify input by printing
// for (int i = 0; i < NUMELEMENTS + 2*RADIUS; ++i) {
// std::cout << in[i] << " ";
// }
// std::cout << std::endl;
// Sizes
int size_in = (NUMELEMENTS + 2*RADIUS) * sizeof(int);
int size_out = NUMELEMENTS * sizeof(int);
// Initialize device copies of in, out
int *d_in, *d_out;
cudaCheck(cudaMalloc((void **)&d_in, size_in));
cudaCheck(cudaMalloc((void **)&d_out, size_out));
// Copy variables from host to device
cudaCheck(cudaMemcpy(d_in, in, size_in, cudaMemcpyHostToDevice));
// Launch the kernel
stencil1d<<<NUMBLOCKS, BLOCKSIZE>>>(d_in, d_out);
// Check for kernel launch errors
cudaCheck(cudaPeekAtLastError());
// Copy variables from device to host
cudaCheck(cudaMemcpy(out, d_out, size_out, cudaMemcpyDeviceToHost));
// Print the result
for (int i = 0; i < NUMELEMENTS; ++i) {
std::cout << out[i] << " ";
}
std::cout << std::endl;
} | // 1D stencil example using CUDA C++
#include <hip/hip_runtime.h>
#include <iostream>
// Global Parameters
#define NUMBLOCKS 8
#define BLOCKSIZE 4
#define RADIUS 1
#define NUMELEMENTS (NUMBLOCKS * BLOCKSIZE)
// Function and macro to handle CUDA errors
static void handleError(hipError_t err, const char *file, int line) {
if (err != hipSuccess) {
std::cout << hipGetErrorString(err) << " in " << file << " at line " << line << std::endl;
exit(EXIT_FAILURE);
}
}
#define cudaCheck(err) (handleError(err, __FILE__, __LINE__))
// A 1D stencil reads in a block of an array, and adds up all elements within a stencil of fixed raduis
// and writes them to an output vector
__global__ void stencil1d(int *in, int *out) {
__shared__ int temp[BLOCKSIZE + 2*RADIUS];
int gindex = threadIdx.x + blockIdx.x * blockDim.x + RADIUS;
int lindex = threadIdx.x + RADIUS;
// Read in data corresponding to the actual block elements
temp[lindex] = in[gindex];
// Read in boundary-data ('halo' on either side, with length commensurate to the radius)
if (threadIdx.x < RADIUS) {
// Left halo
temp[lindex - RADIUS] = in[gindex - RADIUS];
// Right halo
temp[lindex + BLOCKSIZE] = in[gindex + BLOCKSIZE];
}
// Prevent WAR/RAW/WAW conflicts
__syncthreads();
// Apply the stencil
int result = 0;
for (int offset = -RADIUS; offset <= RADIUS; ++offset) {
result += temp[lindex + offset];
}
// Store the result
out[gindex-RADIUS] = result;
}
int main(void) {
// Initialize host copies of in, out
int in[NUMELEMENTS + 2*RADIUS], out[NUMELEMENTS];
for (int i = 0; i < NUMELEMENTS + 2*RADIUS; ++i) {
if (i < RADIUS) {
in[i] = 0;
} else if (i < NUMELEMENTS + RADIUS) {
in[i] = 1;
} else {
in[i] = 0;
}
}
// // Verify input by printing
// for (int i = 0; i < NUMELEMENTS + 2*RADIUS; ++i) {
// std::cout << in[i] << " ";
// }
// std::cout << std::endl;
// Sizes
int size_in = (NUMELEMENTS + 2*RADIUS) * sizeof(int);
int size_out = NUMELEMENTS * sizeof(int);
// Initialize device copies of in, out
int *d_in, *d_out;
cudaCheck(hipMalloc((void **)&d_in, size_in));
cudaCheck(hipMalloc((void **)&d_out, size_out));
// Copy variables from host to device
cudaCheck(hipMemcpy(d_in, in, size_in, hipMemcpyHostToDevice));
// Launch the kernel
stencil1d<<<NUMBLOCKS, BLOCKSIZE>>>(d_in, d_out);
// Check for kernel launch errors
cudaCheck(hipPeekAtLastError());
// Copy variables from device to host
cudaCheck(hipMemcpy(out, d_out, size_out, hipMemcpyDeviceToHost));
// Print the result
for (int i = 0; i < NUMELEMENTS; ++i) {
std::cout << out[i] << " ";
}
std::cout << std::endl;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // 1D stencil example using CUDA C++
#include <hip/hip_runtime.h>
#include <iostream>
// Global Parameters
#define NUMBLOCKS 8
#define BLOCKSIZE 4
#define RADIUS 1
#define NUMELEMENTS (NUMBLOCKS * BLOCKSIZE)
// Function and macro to handle CUDA errors
static void handleError(hipError_t err, const char *file, int line) {
if (err != hipSuccess) {
std::cout << hipGetErrorString(err) << " in " << file << " at line " << line << std::endl;
exit(EXIT_FAILURE);
}
}
#define cudaCheck(err) (handleError(err, __FILE__, __LINE__))
// A 1D stencil reads in a block of an array, and adds up all elements within a stencil of fixed raduis
// and writes them to an output vector
__global__ void stencil1d(int *in, int *out) {
__shared__ int temp[BLOCKSIZE + 2*RADIUS];
int gindex = threadIdx.x + blockIdx.x * blockDim.x + RADIUS;
int lindex = threadIdx.x + RADIUS;
// Read in data corresponding to the actual block elements
temp[lindex] = in[gindex];
// Read in boundary-data ('halo' on either side, with length commensurate to the radius)
if (threadIdx.x < RADIUS) {
// Left halo
temp[lindex - RADIUS] = in[gindex - RADIUS];
// Right halo
temp[lindex + BLOCKSIZE] = in[gindex + BLOCKSIZE];
}
// Prevent WAR/RAW/WAW conflicts
__syncthreads();
// Apply the stencil
int result = 0;
for (int offset = -RADIUS; offset <= RADIUS; ++offset) {
result += temp[lindex + offset];
}
// Store the result
out[gindex-RADIUS] = result;
}
int main(void) {
// Initialize host copies of in, out
int in[NUMELEMENTS + 2*RADIUS], out[NUMELEMENTS];
for (int i = 0; i < NUMELEMENTS + 2*RADIUS; ++i) {
if (i < RADIUS) {
in[i] = 0;
} else if (i < NUMELEMENTS + RADIUS) {
in[i] = 1;
} else {
in[i] = 0;
}
}
// // Verify input by printing
// for (int i = 0; i < NUMELEMENTS + 2*RADIUS; ++i) {
// std::cout << in[i] << " ";
// }
// std::cout << std::endl;
// Sizes
int size_in = (NUMELEMENTS + 2*RADIUS) * sizeof(int);
int size_out = NUMELEMENTS * sizeof(int);
// Initialize device copies of in, out
int *d_in, *d_out;
cudaCheck(hipMalloc((void **)&d_in, size_in));
cudaCheck(hipMalloc((void **)&d_out, size_out));
// Copy variables from host to device
cudaCheck(hipMemcpy(d_in, in, size_in, hipMemcpyHostToDevice));
// Launch the kernel
stencil1d<<<NUMBLOCKS, BLOCKSIZE>>>(d_in, d_out);
// Check for kernel launch errors
cudaCheck(hipPeekAtLastError());
// Copy variables from device to host
cudaCheck(hipMemcpy(out, d_out, size_out, hipMemcpyDeviceToHost));
// Print the result
for (int i = 0; i < NUMELEMENTS; ++i) {
std::cout << out[i] << " ";
}
std::cout << std::endl;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9stencil1dPiS_
.globl _Z9stencil1dPiS_
.p2align 8
.type _Z9stencil1dPiS_,@function
_Z9stencil1dPiS_:
s_load_b32 s2, s[0:1], 0x1c
s_mov_b32 s4, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_load_b64 s[2:3], s[0:1], 0x0
v_add_nc_u32_e32 v2, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v4, v[2:3], off
v_lshlrev_b32_e32 v3, 2, v0
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt vmcnt(0)
ds_store_b32 v3, v4 offset:4
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v4, 5, v1
v_lshlrev_b64 v[6:7], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_clause 0x1
global_load_b32 v0, v[6:7], off
global_load_b32 v4, v[4:5], off
v_mov_b32_e32 v5, 0
s_waitcnt vmcnt(1)
ds_store_b32 v3, v0
s_waitcnt vmcnt(0)
ds_store_b32 v5, v4 offset:20
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s5
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v4, s4, v3
s_add_i32 s4, s4, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s4, 12
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, v4, v0
s_cbranch_scc0 .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9stencil1dPiS_
.amdhsa_group_segment_fixed_size 24
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9stencil1dPiS_, .Lfunc_end0-_Z9stencil1dPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 24
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9stencil1dPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9stencil1dPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // 1D stencil example using CUDA C++
#include <hip/hip_runtime.h>
#include <iostream>
// Global Parameters
#define NUMBLOCKS 8
#define BLOCKSIZE 4
#define RADIUS 1
#define NUMELEMENTS (NUMBLOCKS * BLOCKSIZE)
// Function and macro to handle CUDA errors
static void handleError(hipError_t err, const char *file, int line) {
if (err != hipSuccess) {
std::cout << hipGetErrorString(err) << " in " << file << " at line " << line << std::endl;
exit(EXIT_FAILURE);
}
}
#define cudaCheck(err) (handleError(err, __FILE__, __LINE__))
// A 1D stencil reads in a block of an array, and adds up all elements within a stencil of fixed raduis
// and writes them to an output vector
__global__ void stencil1d(int *in, int *out) {
__shared__ int temp[BLOCKSIZE + 2*RADIUS];
int gindex = threadIdx.x + blockIdx.x * blockDim.x + RADIUS;
int lindex = threadIdx.x + RADIUS;
// Read in data corresponding to the actual block elements
temp[lindex] = in[gindex];
// Read in boundary-data ('halo' on either side, with length commensurate to the radius)
if (threadIdx.x < RADIUS) {
// Left halo
temp[lindex - RADIUS] = in[gindex - RADIUS];
// Right halo
temp[lindex + BLOCKSIZE] = in[gindex + BLOCKSIZE];
}
// Prevent WAR/RAW/WAW conflicts
__syncthreads();
// Apply the stencil
int result = 0;
for (int offset = -RADIUS; offset <= RADIUS; ++offset) {
result += temp[lindex + offset];
}
// Store the result
out[gindex-RADIUS] = result;
}
int main(void) {
// Initialize host copies of in, out
int in[NUMELEMENTS + 2*RADIUS], out[NUMELEMENTS];
for (int i = 0; i < NUMELEMENTS + 2*RADIUS; ++i) {
if (i < RADIUS) {
in[i] = 0;
} else if (i < NUMELEMENTS + RADIUS) {
in[i] = 1;
} else {
in[i] = 0;
}
}
// // Verify input by printing
// for (int i = 0; i < NUMELEMENTS + 2*RADIUS; ++i) {
// std::cout << in[i] << " ";
// }
// std::cout << std::endl;
// Sizes
int size_in = (NUMELEMENTS + 2*RADIUS) * sizeof(int);
int size_out = NUMELEMENTS * sizeof(int);
// Initialize device copies of in, out
int *d_in, *d_out;
cudaCheck(hipMalloc((void **)&d_in, size_in));
cudaCheck(hipMalloc((void **)&d_out, size_out));
// Copy variables from host to device
cudaCheck(hipMemcpy(d_in, in, size_in, hipMemcpyHostToDevice));
// Launch the kernel
stencil1d<<<NUMBLOCKS, BLOCKSIZE>>>(d_in, d_out);
// Check for kernel launch errors
cudaCheck(hipPeekAtLastError());
// Copy variables from device to host
cudaCheck(hipMemcpy(out, d_out, size_out, hipMemcpyDeviceToHost));
// Print the result
for (int i = 0; i < NUMELEMENTS; ++i) {
std::cout << out[i] << " ";
}
std::cout << std::endl;
} | .text
.file "stencil1d.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__stencil1dPiS_ # -- Begin function _Z24__device_stub__stencil1dPiS_
.p2align 4, 0x90
.type _Z24__device_stub__stencil1dPiS_,@function
_Z24__device_stub__stencil1dPiS_: # @_Z24__device_stub__stencil1dPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9stencil1dPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__stencil1dPiS_, .Lfunc_end0-_Z24__device_stub__stencil1dPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $352, %rsp # imm = 0x160
.cfi_def_cfa_offset 368
.cfi_offset %rbx, -16
xorl %eax, %eax
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_1 Depth=1
movl $0, 340(%rsp)
.LBB1_6: # in Loop: Header=BB1_1 Depth=1
incq %rax
cmpq $34, %rax
je .LBB1_7
.LBB1_1: # =>This Inner Loop Header: Depth=1
cmpl $33, %eax
je .LBB1_5
# %bb.2: # in Loop: Header=BB1_1 Depth=1
testl %eax, %eax
jne .LBB1_4
# %bb.3: # in Loop: Header=BB1_1 Depth=1
movl $0, 208(%rsp,%rax,4)
jmp .LBB1_6
.p2align 4, 0x90
.LBB1_4: # in Loop: Header=BB1_1 Depth=1
movl $1, 208(%rsp,%rax,4)
jmp .LBB1_6
.LBB1_7:
leaq 8(%rsp), %rdi
movl $136, %esi
callq hipMalloc
movl %eax, %edi
movl $85, %esi
callq _ZL11handleError10hipError_tPKci
movq %rsp, %rdi
movl $128, %esi
callq hipMalloc
movl %eax, %edi
movl $86, %esi
callq _ZL11handleError10hipError_tPKci
movq 8(%rsp), %rdi
leaq 208(%rsp), %rsi
movl $136, %edx
movl $1, %ecx
callq hipMemcpy
movl %eax, %edi
movl $89, %esi
callq _ZL11handleError10hipError_tPKci
movabsq $4294967300, %rdx # imm = 0x100000004
leaq 4(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_9
# %bb.8:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9stencil1dPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_9:
callq hipPeekAtLastError
movl %eax, %edi
movl $95, %esi
callq _ZL11handleError10hipError_tPKci
movq (%rsp), %rsi
leaq 80(%rsp), %rdi
movl $128, %edx
movl $2, %ecx
callq hipMemcpy
movl %eax, %edi
movl $98, %esi
callq _ZL11handleError10hipError_tPKci
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_10: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbx
cmpq $32, %rbx
jne .LBB1_10
# %bb.11:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_16
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_14
# %bb.13:
movzbl 67(%rbx), %eax
jmp .LBB1_15
.LBB1_14:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $352, %rsp # imm = 0x160
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_16:
.cfi_def_cfa_offset 368
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL11handleError10hipError_tPKci
.type _ZL11handleError10hipError_tPKci,@function
_ZL11handleError10hipError_tPKci: # @_ZL11handleError10hipError_tPKci
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB2_2
# %bb.1:
retq
.LBB2_2:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %esi, %ebx
callq hipGetErrorString
movl $_ZSt4cout, %edi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.2, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.3, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end2:
.size _ZL11handleError10hipError_tPKci, .Lfunc_end2-_ZL11handleError10hipError_tPKci
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9stencil1dPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9stencil1dPiS_,@object # @_Z9stencil1dPiS_
.section .rodata,"a",@progbits
.globl _Z9stencil1dPiS_
.p2align 3, 0x0
_Z9stencil1dPiS_:
.quad _Z24__device_stub__stencil1dPiS_
.size _Z9stencil1dPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/krrish94/learn-cuda/master/stencil1d.hip"
.size .L.str, 98
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " "
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " in "
.size .L.str.2, 5
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " at line "
.size .L.str.3, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9stencil1dPiS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__stencil1dPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9stencil1dPiS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9stencil1dPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e620000002500 */
/*0050*/ ISETP.NE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x001fe20003f05270 */
/*0060*/ IMAD R4, R4, c[0x0][0x0], R11 ; /* 0x0000000004047a24 */
/* 0x002fca00078e020b */
/*0070*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fca00078e0205 */
/*0080*/ LDG.E R0, [R2.64+0x4] ; /* 0x0000040402007981 */
/* 0x000ea8000c1e1900 */
/*0090*/ @!P0 LDG.E R6, [R2.64] ; /* 0x0000000402068981 */
/* 0x000ee8000c1e1900 */
/*00a0*/ @!P0 LDG.E R7, [R2.64+0x14] ; /* 0x0000140402078981 */
/* 0x000f22000c1e1900 */
/*00b0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc600078e0205 */
/*00c0*/ STS [R11.X4+0x4], R0 ; /* 0x000004000b007388 */
/* 0x004fe80000004800 */
/*00d0*/ @!P0 STS [RZ], R6 ; /* 0x00000006ff008388 */
/* 0x008fe80000000800 */
/*00e0*/ @!P0 STS [0x14], R7 ; /* 0x00001407ff008388 */
/* 0x010fe80000000800 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0100*/ LDS R8, [R11.X4+0x4] ; /* 0x000004000b087984 */
/* 0x000fe80000004800 */
/*0110*/ LDS R9, [R11.X4] ; /* 0x000000000b097984 */
/* 0x000fe80000004800 */
/*0120*/ LDS R10, [R11.X4+0x8] ; /* 0x000008000b0a7984 */
/* 0x000e240000004800 */
/*0130*/ IADD3 R9, R10, R8, R9 ; /* 0x000000080a097210 */
/* 0x001fca0007ffe009 */
/*0140*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9stencil1dPiS_
.globl _Z9stencil1dPiS_
.p2align 8
.type _Z9stencil1dPiS_,@function
_Z9stencil1dPiS_:
s_load_b32 s2, s[0:1], 0x1c
s_mov_b32 s4, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_load_b64 s[2:3], s[0:1], 0x0
v_add_nc_u32_e32 v2, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v4, v[2:3], off
v_lshlrev_b32_e32 v3, 2, v0
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt vmcnt(0)
ds_store_b32 v3, v4 offset:4
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v4, 5, v1
v_lshlrev_b64 v[6:7], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_clause 0x1
global_load_b32 v0, v[6:7], off
global_load_b32 v4, v[4:5], off
v_mov_b32_e32 v5, 0
s_waitcnt vmcnt(1)
ds_store_b32 v3, v0
s_waitcnt vmcnt(0)
ds_store_b32 v5, v4 offset:20
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s5
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_3:
v_add_nc_u32_e32 v4, s4, v3
s_add_i32 s4, s4, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s4, 12
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, v4, v0
s_cbranch_scc0 .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9stencil1dPiS_
.amdhsa_group_segment_fixed_size 24
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9stencil1dPiS_, .Lfunc_end0-_Z9stencil1dPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 24
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9stencil1dPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9stencil1dPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e7ac1_00000000-6_stencil1d.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " in "
.LC1:
.string " at line "
#NO_APP
.text
.type _ZL11handleError9cudaErrorPKci, @function
_ZL11handleError9cudaErrorPKci:
.LFB3669:
.cfi_startproc
testl %edi, %edi
jne .L6
ret
.L6:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbp
movl %edx, %ebx
call cudaGetErrorString@PLT
movq %rax, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _ZL11handleError9cudaErrorPKci, .-_ZL11handleError9cudaErrorPKci
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9stencil1dPiS_PiS_
.type _Z30__device_stub__Z9stencil1dPiS_PiS_, @function
_Z30__device_stub__Z9stencil1dPiS_PiS_:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9stencil1dPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z30__device_stub__Z9stencil1dPiS_PiS_, .-_Z30__device_stub__Z9stencil1dPiS_PiS_
.globl _Z9stencil1dPiS_
.type _Z9stencil1dPiS_, @function
_Z9stencil1dPiS_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9stencil1dPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z9stencil1dPiS_, .-_Z9stencil1dPiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/krrish94/learn-cuda/master/stencil1d.cu"
.section .rodata.str1.1
.LC3:
.string " "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $328, %rsp
.cfi_def_cfa_offset 368
movq %fs:40, %rax
movq %rax, 312(%rsp)
xorl %eax, %eax
movl $1, %ecx
jmp .L21
.L31:
movl $0, 308(%rsp)
leaq 8(%rsp), %rdi
movl $136, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $83, %edx
leaq .LC2(%rip), %rbx
movq %rbx, %rsi
call _ZL11handleError9cudaErrorPKci
leaq 16(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $84, %edx
movq %rbx, %rsi
call _ZL11handleError9cudaErrorPKci
leaq 176(%rsp), %rsi
movl $1, %ecx
movl $136, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $87, %edx
movq %rbx, %rsi
call _ZL11handleError9cudaErrorPKci
movl $4, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $8, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L19:
call cudaPeekAtLastError@PLT
movl %eax, %edi
movl $93, %edx
leaq .LC2(%rip), %rbp
movq %rbp, %rsi
call _ZL11handleError9cudaErrorPKci
leaq 48(%rsp), %rbx
movl $2, %ecx
movl $128, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $96, %edx
movq %rbp, %rsi
call _ZL11handleError9cudaErrorPKci
leaq 176(%rsp), %r13
leaq _ZSt4cout(%rip), %r12
leaq .LC3(%rip), %rbp
.L22:
movl (%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %rbp, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L22
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 312(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $328, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl $0, %edx
.L18:
movl %edx, 176(%rsp,%rax,4)
addq $1, %rax
.L21:
testl %eax, %eax
jle .L24
cmpl $32, %eax
jg .L31
movl %ecx, %edx
jmp .L18
.L29:
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z9stencil1dPiS_PiS_
jmp .L19
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z9stencil1dPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z9stencil1dPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "stencil1d.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__stencil1dPiS_ # -- Begin function _Z24__device_stub__stencil1dPiS_
.p2align 4, 0x90
.type _Z24__device_stub__stencil1dPiS_,@function
_Z24__device_stub__stencil1dPiS_: # @_Z24__device_stub__stencil1dPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9stencil1dPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__stencil1dPiS_, .Lfunc_end0-_Z24__device_stub__stencil1dPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $352, %rsp # imm = 0x160
.cfi_def_cfa_offset 368
.cfi_offset %rbx, -16
xorl %eax, %eax
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_1 Depth=1
movl $0, 340(%rsp)
.LBB1_6: # in Loop: Header=BB1_1 Depth=1
incq %rax
cmpq $34, %rax
je .LBB1_7
.LBB1_1: # =>This Inner Loop Header: Depth=1
cmpl $33, %eax
je .LBB1_5
# %bb.2: # in Loop: Header=BB1_1 Depth=1
testl %eax, %eax
jne .LBB1_4
# %bb.3: # in Loop: Header=BB1_1 Depth=1
movl $0, 208(%rsp,%rax,4)
jmp .LBB1_6
.p2align 4, 0x90
.LBB1_4: # in Loop: Header=BB1_1 Depth=1
movl $1, 208(%rsp,%rax,4)
jmp .LBB1_6
.LBB1_7:
leaq 8(%rsp), %rdi
movl $136, %esi
callq hipMalloc
movl %eax, %edi
movl $85, %esi
callq _ZL11handleError10hipError_tPKci
movq %rsp, %rdi
movl $128, %esi
callq hipMalloc
movl %eax, %edi
movl $86, %esi
callq _ZL11handleError10hipError_tPKci
movq 8(%rsp), %rdi
leaq 208(%rsp), %rsi
movl $136, %edx
movl $1, %ecx
callq hipMemcpy
movl %eax, %edi
movl $89, %esi
callq _ZL11handleError10hipError_tPKci
movabsq $4294967300, %rdx # imm = 0x100000004
leaq 4(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_9
# %bb.8:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9stencil1dPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_9:
callq hipPeekAtLastError
movl %eax, %edi
movl $95, %esi
callq _ZL11handleError10hipError_tPKci
movq (%rsp), %rsi
leaq 80(%rsp), %rdi
movl $128, %edx
movl $2, %ecx
callq hipMemcpy
movl %eax, %edi
movl $98, %esi
callq _ZL11handleError10hipError_tPKci
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_10: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbx
cmpq $32, %rbx
jne .LBB1_10
# %bb.11:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_16
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_14
# %bb.13:
movzbl 67(%rbx), %eax
jmp .LBB1_15
.LBB1_14:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $352, %rsp # imm = 0x160
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_16:
.cfi_def_cfa_offset 368
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL11handleError10hipError_tPKci
.type _ZL11handleError10hipError_tPKci,@function
_ZL11handleError10hipError_tPKci: # @_ZL11handleError10hipError_tPKci
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB2_2
# %bb.1:
retq
.LBB2_2:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %esi, %ebx
callq hipGetErrorString
movl $_ZSt4cout, %edi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.2, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.3, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end2:
.size _ZL11handleError10hipError_tPKci, .Lfunc_end2-_ZL11handleError10hipError_tPKci
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9stencil1dPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9stencil1dPiS_,@object # @_Z9stencil1dPiS_
.section .rodata,"a",@progbits
.globl _Z9stencil1dPiS_
.p2align 3, 0x0
_Z9stencil1dPiS_:
.quad _Z24__device_stub__stencil1dPiS_
.size _Z9stencil1dPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/krrish94/learn-cuda/master/stencil1d.hip"
.size .L.str, 98
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " "
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " in "
.size .L.str.2, 5
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " at line "
.size .L.str.3, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9stencil1dPiS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__stencil1dPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9stencil1dPiS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <time.h>
#include <stdlib.h>
#include <stdint.h>
#include <cuda_runtime.h>
#include <cuda_runtime_api.h>
#include <curand_kernel.h>
#include <device_functions.h>
__constant__ uint32_t expo_d[4] = { 1, 256, 65536, 16777216 };
__device__ __host__ inline uint32_t f_CUDA(uint32_t B, uint32_t C, uint32_t D, int t)
{
if (t < 20)
{
return ((B & C) ^ (~B & D));
}
if ((t > 19)& (t < 40))
{
return (B ^ C ^ D);
}
if ((t > 39)& (t < 60))
{
return ((B & C) ^ (B & D) ^ (C & D));
}
if (t > 59)
{
return (B ^ C ^ D);
}
return B;
}
__device__ __host__ inline uint32_t Rol_CUDA(uint32_t x, int y)
{
if (y % 32 == 0) { return x; }
else { return ((x << y) ^ (x >> -y)); }
}
//SHA1-Function
__device__ __host__ void SHA1(unsigned char* s, int slen, uint32_t *h0, uint32_t* h1, uint32_t* h2, uint32_t* h3, uint32_t* h4)
{
uint32_t H[5];
uint32_t K[80];
uint32_t A, B, C, D, E, TEMP;
int r, k, ln, t, l, i, j;
H[0] = 0x67452301;
H[1] = 0xefcdab89;
H[2] = 0x98badcfe;
H[3] = 0x10325476;
H[4] = 0xc3d2e1f0;
ln = slen;
r = (int)((ln + 1) / 64);
if (((ln + 1) % 64) > 56)
{
r = r + 1;
}
// initialize Constants
//pragma unroll
for (t = 0; t < 80; t++)
{
if (t < 20)
{
K[t] = 0x5a827999;
}
if ((t > 19)& (t < 40))
{
K[t] = 0x6ED9EBA1;
}
if ((t > 39)& (t < 60))
{
K[t] = 0x8F1BBCDC;
}
if (t > 59)
{
K[t] = 0xca62c1d6;
}
}
for (l = 0; l <= r; l++)
{
uint32_t W[80] = { 0 };
//Initialize Text
for (i = 0; i < 16; i++)
{
//pragma unroll
for (j = 0; j < 4; j++)
{
if (4 * i + j < ln)
{
k = s[64 * l + 4 * i + j];
}
else
{
k = 0;
}
if (k < 0)
{
k = k + 256;
}
if (4 * i + j == ln)
{
k = 0x80;
}
// W[i]= W[i] + k*(uint32_t)pow(256,(double)3-j);
W[i] = W[i] + k * expo_d[3 - j];
}
}
if ((W[14] == 0) & (W[15] == 0))
{
W[15] = 8 * slen;
}
// Hash Cycle
for (t = 16; t < 80; t++)
{
W[t] = Rol_CUDA(W[t - 3] ^ W[t - 8] ^ W[t - 14] ^ W[t - 16], 1);
}
A = H[0];
B = H[1];
C = H[2];
D = H[3];
E = H[4];
for (t = 0; t < 80; t++)
{
TEMP = (Rol_CUDA(A, 5) + f_CUDA(B, C, D, t) + E + W[t] + K[t]);
E = D;
D = C;
C = Rol_CUDA(B, 30);
B = A;
A = TEMP;
}
H[0] = H[0] + A;
H[1] = H[1] + B;
H[2] = H[2] + C;
H[3] = H[3] + D;
H[4] = H[4] + E;
ln = ln - 64;
}
h0 = &H[0];
h1 = &H[1];
h2 = &H[3];
h3 = &H[3];
h4 = &H[4];
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <time.h>
#include <stdlib.h>
#include <stdint.h>
#include <cuda_runtime.h>
#include <cuda_runtime_api.h>
#include <curand_kernel.h>
#include <device_functions.h>
__constant__ uint32_t expo_d[4] = { 1, 256, 65536, 16777216 };
__device__ __host__ inline uint32_t f_CUDA(uint32_t B, uint32_t C, uint32_t D, int t)
{
if (t < 20)
{
return ((B & C) ^ (~B & D));
}
if ((t > 19)& (t < 40))
{
return (B ^ C ^ D);
}
if ((t > 39)& (t < 60))
{
return ((B & C) ^ (B & D) ^ (C & D));
}
if (t > 59)
{
return (B ^ C ^ D);
}
return B;
}
__device__ __host__ inline uint32_t Rol_CUDA(uint32_t x, int y)
{
if (y % 32 == 0) { return x; }
else { return ((x << y) ^ (x >> -y)); }
}
//SHA1-Function
__device__ __host__ void SHA1(unsigned char* s, int slen, uint32_t *h0, uint32_t* h1, uint32_t* h2, uint32_t* h3, uint32_t* h4)
{
uint32_t H[5];
uint32_t K[80];
uint32_t A, B, C, D, E, TEMP;
int r, k, ln, t, l, i, j;
H[0] = 0x67452301;
H[1] = 0xefcdab89;
H[2] = 0x98badcfe;
H[3] = 0x10325476;
H[4] = 0xc3d2e1f0;
ln = slen;
r = (int)((ln + 1) / 64);
if (((ln + 1) % 64) > 56)
{
r = r + 1;
}
// initialize Constants
//pragma unroll
for (t = 0; t < 80; t++)
{
if (t < 20)
{
K[t] = 0x5a827999;
}
if ((t > 19)& (t < 40))
{
K[t] = 0x6ED9EBA1;
}
if ((t > 39)& (t < 60))
{
K[t] = 0x8F1BBCDC;
}
if (t > 59)
{
K[t] = 0xca62c1d6;
}
}
for (l = 0; l <= r; l++)
{
uint32_t W[80] = { 0 };
//Initialize Text
for (i = 0; i < 16; i++)
{
//pragma unroll
for (j = 0; j < 4; j++)
{
if (4 * i + j < ln)
{
k = s[64 * l + 4 * i + j];
}
else
{
k = 0;
}
if (k < 0)
{
k = k + 256;
}
if (4 * i + j == ln)
{
k = 0x80;
}
// W[i]= W[i] + k*(uint32_t)pow(256,(double)3-j);
W[i] = W[i] + k * expo_d[3 - j];
}
}
if ((W[14] == 0) & (W[15] == 0))
{
W[15] = 8 * slen;
}
// Hash Cycle
for (t = 16; t < 80; t++)
{
W[t] = Rol_CUDA(W[t - 3] ^ W[t - 8] ^ W[t - 14] ^ W[t - 16], 1);
}
A = H[0];
B = H[1];
C = H[2];
D = H[3];
E = H[4];
for (t = 0; t < 80; t++)
{
TEMP = (Rol_CUDA(A, 5) + f_CUDA(B, C, D, t) + E + W[t] + K[t]);
E = D;
D = C;
C = Rol_CUDA(B, 30);
B = A;
A = TEMP;
}
H[0] = H[0] + A;
H[1] = H[1] + B;
H[2] = H[2] + C;
H[3] = H[3] + D;
H[4] = H[4] + E;
ln = ln - 64;
}
h0 = &H[0];
h1 = &H[1];
h2 = &H[3];
h3 = &H[3];
h4 = &H[4];
} | .file "tmpxft_0001592e_00000000-6_sha11.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2276:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2276:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4SHA1PhiPjS0_S0_S0_S0_
.type _Z4SHA1PhiPjS0_S0_S0_S0_, @function
_Z4SHA1PhiPjS0_S0_S0_S0_:
.LFB2273:
.cfi_startproc
endbr64
movl %esi, %eax
leal 64(%rsi), %ecx
addl $1, %eax
cmovns %eax, %ecx
sarl $6, %ecx
cltd
shrl $26, %edx
addl %edx, %eax
andl $63, %eax
subl %edx, %eax
cmpl $56, %eax
setg %al
movzbl %al, %eax
addl %eax, %ecx
movl $80, %eax
.L5:
subl $1, %eax
jne .L5
testl %ecx, %ecx
js .L3
addl $1, %ecx
movl $0, %edx
.L7:
movl $64, %eax
.L8:
subl $1, %eax
jne .L8
movl $80, %eax
.L9:
subl $1, %eax
jne .L9
addl $1, %edx
cmpl %ecx, %edx
jne .L7
.L3:
ret
.cfi_endproc
.LFE2273:
.size _Z4SHA1PhiPjS0_S0_S0_S0_, .-_Z4SHA1PhiPjS0_S0_S0_S0_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "precalc_xorwow_matrix"
.LC1:
.string "precalc_xorwow_offset_matrix"
.LC2:
.string "mrg32k3aM1"
.LC3:
.string "mrg32k3aM2"
.LC4:
.string "mrg32k3aM1SubSeq"
.LC5:
.string "mrg32k3aM2SubSeq"
.LC6:
.string "mrg32k3aM1Seq"
.LC7:
.string "mrg32k3aM2Seq"
.LC8:
.string "__cr_lgamma_table"
.LC9:
.string "expo_d"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2299:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $16, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6expo_d(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2299:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL6expo_d
.comm _ZL6expo_d,16,16
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <time.h>
#include <stdlib.h>
#include <stdint.h>
#include <cuda_runtime.h>
#include <cuda_runtime_api.h>
#include <curand_kernel.h>
#include <device_functions.h>
__constant__ uint32_t expo_d[4] = { 1, 256, 65536, 16777216 };
__device__ __host__ inline uint32_t f_CUDA(uint32_t B, uint32_t C, uint32_t D, int t)
{
if (t < 20)
{
return ((B & C) ^ (~B & D));
}
if ((t > 19)& (t < 40))
{
return (B ^ C ^ D);
}
if ((t > 39)& (t < 60))
{
return ((B & C) ^ (B & D) ^ (C & D));
}
if (t > 59)
{
return (B ^ C ^ D);
}
return B;
}
__device__ __host__ inline uint32_t Rol_CUDA(uint32_t x, int y)
{
if (y % 32 == 0) { return x; }
else { return ((x << y) ^ (x >> -y)); }
}
//SHA1-Function
__device__ __host__ void SHA1(unsigned char* s, int slen, uint32_t *h0, uint32_t* h1, uint32_t* h2, uint32_t* h3, uint32_t* h4)
{
uint32_t H[5];
uint32_t K[80];
uint32_t A, B, C, D, E, TEMP;
int r, k, ln, t, l, i, j;
H[0] = 0x67452301;
H[1] = 0xefcdab89;
H[2] = 0x98badcfe;
H[3] = 0x10325476;
H[4] = 0xc3d2e1f0;
ln = slen;
r = (int)((ln + 1) / 64);
if (((ln + 1) % 64) > 56)
{
r = r + 1;
}
// initialize Constants
//pragma unroll
for (t = 0; t < 80; t++)
{
if (t < 20)
{
K[t] = 0x5a827999;
}
if ((t > 19)& (t < 40))
{
K[t] = 0x6ED9EBA1;
}
if ((t > 39)& (t < 60))
{
K[t] = 0x8F1BBCDC;
}
if (t > 59)
{
K[t] = 0xca62c1d6;
}
}
for (l = 0; l <= r; l++)
{
uint32_t W[80] = { 0 };
//Initialize Text
for (i = 0; i < 16; i++)
{
//pragma unroll
for (j = 0; j < 4; j++)
{
if (4 * i + j < ln)
{
k = s[64 * l + 4 * i + j];
}
else
{
k = 0;
}
if (k < 0)
{
k = k + 256;
}
if (4 * i + j == ln)
{
k = 0x80;
}
// W[i]= W[i] + k*(uint32_t)pow(256,(double)3-j);
W[i] = W[i] + k * expo_d[3 - j];
}
}
if ((W[14] == 0) & (W[15] == 0))
{
W[15] = 8 * slen;
}
// Hash Cycle
for (t = 16; t < 80; t++)
{
W[t] = Rol_CUDA(W[t - 3] ^ W[t - 8] ^ W[t - 14] ^ W[t - 16], 1);
}
A = H[0];
B = H[1];
C = H[2];
D = H[3];
E = H[4];
for (t = 0; t < 80; t++)
{
TEMP = (Rol_CUDA(A, 5) + f_CUDA(B, C, D, t) + E + W[t] + K[t]);
E = D;
D = C;
C = Rol_CUDA(B, 30);
B = A;
A = TEMP;
}
H[0] = H[0] + A;
H[1] = H[1] + B;
H[2] = H[2] + C;
H[3] = H[3] + D;
H[4] = H[4] + E;
ln = ln - 64;
}
h0 = &H[0];
h1 = &H[1];
h2 = &H[3];
h3 = &H[3];
h4 = &H[4];
} | #include <stdio.h>
#include <time.h>
#include <stdlib.h>
#include <stdint.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <hiprand/hiprand_kernel.h>
#include <hip/device_functions.h>
__constant__ uint32_t expo_d[4] = { 1, 256, 65536, 16777216 };
__device__ __host__ inline uint32_t f_CUDA(uint32_t B, uint32_t C, uint32_t D, int t)
{
if (t < 20)
{
return ((B & C) ^ (~B & D));
}
if ((t > 19)& (t < 40))
{
return (B ^ C ^ D);
}
if ((t > 39)& (t < 60))
{
return ((B & C) ^ (B & D) ^ (C & D));
}
if (t > 59)
{
return (B ^ C ^ D);
}
return B;
}
__device__ __host__ inline uint32_t Rol_CUDA(uint32_t x, int y)
{
if (y % 32 == 0) { return x; }
else { return ((x << y) ^ (x >> -y)); }
}
//SHA1-Function
__device__ __host__ void SHA1(unsigned char* s, int slen, uint32_t *h0, uint32_t* h1, uint32_t* h2, uint32_t* h3, uint32_t* h4)
{
uint32_t H[5];
uint32_t K[80];
uint32_t A, B, C, D, E, TEMP;
int r, k, ln, t, l, i, j;
H[0] = 0x67452301;
H[1] = 0xefcdab89;
H[2] = 0x98badcfe;
H[3] = 0x10325476;
H[4] = 0xc3d2e1f0;
ln = slen;
r = (int)((ln + 1) / 64);
if (((ln + 1) % 64) > 56)
{
r = r + 1;
}
// initialize Constants
//pragma unroll
for (t = 0; t < 80; t++)
{
if (t < 20)
{
K[t] = 0x5a827999;
}
if ((t > 19)& (t < 40))
{
K[t] = 0x6ED9EBA1;
}
if ((t > 39)& (t < 60))
{
K[t] = 0x8F1BBCDC;
}
if (t > 59)
{
K[t] = 0xca62c1d6;
}
}
for (l = 0; l <= r; l++)
{
uint32_t W[80] = { 0 };
//Initialize Text
for (i = 0; i < 16; i++)
{
//pragma unroll
for (j = 0; j < 4; j++)
{
if (4 * i + j < ln)
{
k = s[64 * l + 4 * i + j];
}
else
{
k = 0;
}
if (k < 0)
{
k = k + 256;
}
if (4 * i + j == ln)
{
k = 0x80;
}
// W[i]= W[i] + k*(uint32_t)pow(256,(double)3-j);
W[i] = W[i] + k * expo_d[3 - j];
}
}
if ((W[14] == 0) & (W[15] == 0))
{
W[15] = 8 * slen;
}
// Hash Cycle
for (t = 16; t < 80; t++)
{
W[t] = Rol_CUDA(W[t - 3] ^ W[t - 8] ^ W[t - 14] ^ W[t - 16], 1);
}
A = H[0];
B = H[1];
C = H[2];
D = H[3];
E = H[4];
for (t = 0; t < 80; t++)
{
TEMP = (Rol_CUDA(A, 5) + f_CUDA(B, C, D, t) + E + W[t] + K[t]);
E = D;
D = C;
C = Rol_CUDA(B, 30);
B = A;
A = TEMP;
}
H[0] = H[0] + A;
H[1] = H[1] + B;
H[2] = H[2] + C;
H[3] = H[3] + D;
H[4] = H[4] + E;
ln = ln - 64;
}
h0 = &H[0];
h1 = &H[1];
h2 = &H[3];
h3 = &H[3];
h4 = &H[4];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <time.h>
#include <stdlib.h>
#include <stdint.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <hiprand/hiprand_kernel.h>
#include <hip/device_functions.h>
__constant__ uint32_t expo_d[4] = { 1, 256, 65536, 16777216 };
__device__ __host__ inline uint32_t f_CUDA(uint32_t B, uint32_t C, uint32_t D, int t)
{
if (t < 20)
{
return ((B & C) ^ (~B & D));
}
if ((t > 19)& (t < 40))
{
return (B ^ C ^ D);
}
if ((t > 39)& (t < 60))
{
return ((B & C) ^ (B & D) ^ (C & D));
}
if (t > 59)
{
return (B ^ C ^ D);
}
return B;
}
__device__ __host__ inline uint32_t Rol_CUDA(uint32_t x, int y)
{
if (y % 32 == 0) { return x; }
else { return ((x << y) ^ (x >> -y)); }
}
//SHA1-Function
__device__ __host__ void SHA1(unsigned char* s, int slen, uint32_t *h0, uint32_t* h1, uint32_t* h2, uint32_t* h3, uint32_t* h4)
{
uint32_t H[5];
uint32_t K[80];
uint32_t A, B, C, D, E, TEMP;
int r, k, ln, t, l, i, j;
H[0] = 0x67452301;
H[1] = 0xefcdab89;
H[2] = 0x98badcfe;
H[3] = 0x10325476;
H[4] = 0xc3d2e1f0;
ln = slen;
r = (int)((ln + 1) / 64);
if (((ln + 1) % 64) > 56)
{
r = r + 1;
}
// initialize Constants
//pragma unroll
for (t = 0; t < 80; t++)
{
if (t < 20)
{
K[t] = 0x5a827999;
}
if ((t > 19)& (t < 40))
{
K[t] = 0x6ED9EBA1;
}
if ((t > 39)& (t < 60))
{
K[t] = 0x8F1BBCDC;
}
if (t > 59)
{
K[t] = 0xca62c1d6;
}
}
for (l = 0; l <= r; l++)
{
uint32_t W[80] = { 0 };
//Initialize Text
for (i = 0; i < 16; i++)
{
//pragma unroll
for (j = 0; j < 4; j++)
{
if (4 * i + j < ln)
{
k = s[64 * l + 4 * i + j];
}
else
{
k = 0;
}
if (k < 0)
{
k = k + 256;
}
if (4 * i + j == ln)
{
k = 0x80;
}
// W[i]= W[i] + k*(uint32_t)pow(256,(double)3-j);
W[i] = W[i] + k * expo_d[3 - j];
}
}
if ((W[14] == 0) & (W[15] == 0))
{
W[15] = 8 * slen;
}
// Hash Cycle
for (t = 16; t < 80; t++)
{
W[t] = Rol_CUDA(W[t - 3] ^ W[t - 8] ^ W[t - 14] ^ W[t - 16], 1);
}
A = H[0];
B = H[1];
C = H[2];
D = H[3];
E = H[4];
for (t = 0; t < 80; t++)
{
TEMP = (Rol_CUDA(A, 5) + f_CUDA(B, C, D, t) + E + W[t] + K[t]);
E = D;
D = C;
C = Rol_CUDA(B, 30);
B = A;
A = TEMP;
}
H[0] = H[0] + A;
H[1] = H[1] + B;
H[2] = H[2] + C;
H[3] = H[3] + D;
H[4] = H[4] + E;
ln = ln - 64;
}
h0 = &H[0];
h1 = &H[1];
h2 = &H[3];
h3 = &H[3];
h4 = &H[4];
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected expo_d
.type expo_d,@object
.data
.globl expo_d
.p2align 4, 0x0
expo_d:
.long 1
.long 256
.long 65536
.long 16777216
.size expo_d, 16
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym expo_d
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <time.h>
#include <stdlib.h>
#include <stdint.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <hiprand/hiprand_kernel.h>
#include <hip/device_functions.h>
__constant__ uint32_t expo_d[4] = { 1, 256, 65536, 16777216 };
__device__ __host__ inline uint32_t f_CUDA(uint32_t B, uint32_t C, uint32_t D, int t)
{
if (t < 20)
{
return ((B & C) ^ (~B & D));
}
if ((t > 19)& (t < 40))
{
return (B ^ C ^ D);
}
if ((t > 39)& (t < 60))
{
return ((B & C) ^ (B & D) ^ (C & D));
}
if (t > 59)
{
return (B ^ C ^ D);
}
return B;
}
__device__ __host__ inline uint32_t Rol_CUDA(uint32_t x, int y)
{
if (y % 32 == 0) { return x; }
else { return ((x << y) ^ (x >> -y)); }
}
//SHA1-Function
__device__ __host__ void SHA1(unsigned char* s, int slen, uint32_t *h0, uint32_t* h1, uint32_t* h2, uint32_t* h3, uint32_t* h4)
{
uint32_t H[5];
uint32_t K[80];
uint32_t A, B, C, D, E, TEMP;
int r, k, ln, t, l, i, j;
H[0] = 0x67452301;
H[1] = 0xefcdab89;
H[2] = 0x98badcfe;
H[3] = 0x10325476;
H[4] = 0xc3d2e1f0;
ln = slen;
r = (int)((ln + 1) / 64);
if (((ln + 1) % 64) > 56)
{
r = r + 1;
}
// initialize Constants
//pragma unroll
for (t = 0; t < 80; t++)
{
if (t < 20)
{
K[t] = 0x5a827999;
}
if ((t > 19)& (t < 40))
{
K[t] = 0x6ED9EBA1;
}
if ((t > 39)& (t < 60))
{
K[t] = 0x8F1BBCDC;
}
if (t > 59)
{
K[t] = 0xca62c1d6;
}
}
for (l = 0; l <= r; l++)
{
uint32_t W[80] = { 0 };
//Initialize Text
for (i = 0; i < 16; i++)
{
//pragma unroll
for (j = 0; j < 4; j++)
{
if (4 * i + j < ln)
{
k = s[64 * l + 4 * i + j];
}
else
{
k = 0;
}
if (k < 0)
{
k = k + 256;
}
if (4 * i + j == ln)
{
k = 0x80;
}
// W[i]= W[i] + k*(uint32_t)pow(256,(double)3-j);
W[i] = W[i] + k * expo_d[3 - j];
}
}
if ((W[14] == 0) & (W[15] == 0))
{
W[15] = 8 * slen;
}
// Hash Cycle
for (t = 16; t < 80; t++)
{
W[t] = Rol_CUDA(W[t - 3] ^ W[t - 8] ^ W[t - 14] ^ W[t - 16], 1);
}
A = H[0];
B = H[1];
C = H[2];
D = H[3];
E = H[4];
for (t = 0; t < 80; t++)
{
TEMP = (Rol_CUDA(A, 5) + f_CUDA(B, C, D, t) + E + W[t] + K[t]);
E = D;
D = C;
C = Rol_CUDA(B, 30);
B = A;
A = TEMP;
}
H[0] = H[0] + A;
H[1] = H[1] + B;
H[2] = H[2] + C;
H[3] = H[3] + D;
H[4] = H[4] + E;
ln = ln - 64;
}
h0 = &H[0];
h1 = &H[1];
h2 = &H[3];
h3 = &H[3];
h4 = &H[4];
} | .text
.file "sha11.hip"
.globl _Z4SHA1PhiPjS0_S0_S0_S0_ # -- Begin function _Z4SHA1PhiPjS0_S0_S0_S0_
.p2align 4, 0x90
.type _Z4SHA1PhiPjS0_S0_S0_S0_,@function
_Z4SHA1PhiPjS0_S0_S0_S0_: # @_Z4SHA1PhiPjS0_S0_S0_S0_
.cfi_startproc
# %bb.0: # %.preheader88
# kill: def $esi killed $esi def $rsi
leal 1(%rsi), %ecx
leal 64(%rsi), %eax
testl %ecx, %ecx
cmovnsl %ecx, %eax
movl %eax, %ecx
andl $-64, %ecx
negl %ecx
leal (%rsi,%rcx), %edx
incl %edx
xorl %ecx, %ecx
cmpl $57, %edx
setge %cl
sarl $6, %eax
movl %eax, %edx
addl %ecx, %edx
js .LBB0_10
# %bb.1: # %.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $344, %rsp # imm = 0x158
.cfi_def_cfa_offset 400
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
movslq %esi, %r15
addl %ecx, %eax
incl %eax
movq %rax, (%rsp) # 8-byte Spill
xorl %r13d, %r13d
movl $128, %ebp
xorl %r14d, %r14d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_8: # %_Z6f_CUDAjjji.exit.preheader
# in Loop: Header=BB0_2 Depth=1
addq $-64, %r15
incq %r14
movq 8(%rsp), %r13 # 8-byte Reload
addq $64, %r13
cmpq (%rsp), %r14 # 8-byte Folded Reload
je .LBB0_9
.LBB0_2: # =>This Loop Header: Depth=1
# Child Loop BB0_3 Depth 2
# Child Loop BB0_4 Depth 3
movq %r13, 8(%rsp) # 8-byte Spill
shrq $2, %r13
movl %r15d, %r12d
negq %r12
movl $320, %edx # imm = 0x140
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq memset@PLT
xorl %eax, %eax
xorl %ecx, %ecx
jmp .LBB0_3
.p2align 4, 0x90
.LBB0_7: # in Loop: Header=BB0_3 Depth=2
movl %esi, 16(%rsp,%rcx,4)
incq %rcx
incl %r13d
addq $4, %rax
cmpq $16, %rcx
je .LBB0_8
.LBB0_3: # %.preheader
# Parent Loop BB0_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_4 Depth 3
leal (,%r13,4), %edx
addq %rbx, %rdx
movl 16(%rsp,%rcx,4), %esi
leaq (%r12,%rax), %rdi
xorl %r8d, %r8d
jmp .LBB0_4
.p2align 4, 0x90
.LBB0_6: # in Loop: Header=BB0_4 Depth=3
movq %rdi, %r10
addq %r8, %r10
cmovel %ebp, %r9d
movq %r8, %r10
xorq $3, %r10
imull expo_d(,%r10,4), %r9d
addl %r9d, %esi
incq %r8
cmpq $4, %r8
je .LBB0_7
.LBB0_4: # Parent Loop BB0_2 Depth=1
# Parent Loop BB0_3 Depth=2
# => This Inner Loop Header: Depth=3
leaq (%rax,%r8), %r10
xorl %r9d, %r9d
cmpq %r15, %r10
jge .LBB0_6
# %bb.5: # in Loop: Header=BB0_4 Depth=3
movzbl (%rdx,%r8), %r9d
jmp .LBB0_6
.LBB0_9:
addq $344, %rsp # imm = 0x158
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB0_10: # %._crit_edge
retq
.Lfunc_end0:
.size _Z4SHA1PhiPjS0_S0_S0_S0_, .Lfunc_end0-_Z4SHA1PhiPjS0_S0_S0_S0_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
movl $expo_d, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $16, %r9d
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type expo_d,@object # @expo_d
.local expo_d
.comm expo_d,16,16
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "expo_d"
.size .L__unnamed_1, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym expo_d
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected expo_d
.type expo_d,@object
.data
.globl expo_d
.p2align 4, 0x0
expo_d:
.long 1
.long 256
.long 65536
.long 16777216
.size expo_d, 16
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym expo_d
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001592e_00000000-6_sha11.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2276:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2276:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4SHA1PhiPjS0_S0_S0_S0_
.type _Z4SHA1PhiPjS0_S0_S0_S0_, @function
_Z4SHA1PhiPjS0_S0_S0_S0_:
.LFB2273:
.cfi_startproc
endbr64
movl %esi, %eax
leal 64(%rsi), %ecx
addl $1, %eax
cmovns %eax, %ecx
sarl $6, %ecx
cltd
shrl $26, %edx
addl %edx, %eax
andl $63, %eax
subl %edx, %eax
cmpl $56, %eax
setg %al
movzbl %al, %eax
addl %eax, %ecx
movl $80, %eax
.L5:
subl $1, %eax
jne .L5
testl %ecx, %ecx
js .L3
addl $1, %ecx
movl $0, %edx
.L7:
movl $64, %eax
.L8:
subl $1, %eax
jne .L8
movl $80, %eax
.L9:
subl $1, %eax
jne .L9
addl $1, %edx
cmpl %ecx, %edx
jne .L7
.L3:
ret
.cfi_endproc
.LFE2273:
.size _Z4SHA1PhiPjS0_S0_S0_S0_, .-_Z4SHA1PhiPjS0_S0_S0_S0_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "precalc_xorwow_matrix"
.LC1:
.string "precalc_xorwow_offset_matrix"
.LC2:
.string "mrg32k3aM1"
.LC3:
.string "mrg32k3aM2"
.LC4:
.string "mrg32k3aM1SubSeq"
.LC5:
.string "mrg32k3aM2SubSeq"
.LC6:
.string "mrg32k3aM1Seq"
.LC7:
.string "mrg32k3aM2Seq"
.LC8:
.string "__cr_lgamma_table"
.LC9:
.string "expo_d"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2299:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $16, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6expo_d(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2299:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL6expo_d
.comm _ZL6expo_d,16,16
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sha11.hip"
.globl _Z4SHA1PhiPjS0_S0_S0_S0_ # -- Begin function _Z4SHA1PhiPjS0_S0_S0_S0_
.p2align 4, 0x90
.type _Z4SHA1PhiPjS0_S0_S0_S0_,@function
_Z4SHA1PhiPjS0_S0_S0_S0_: # @_Z4SHA1PhiPjS0_S0_S0_S0_
.cfi_startproc
# %bb.0: # %.preheader88
# kill: def $esi killed $esi def $rsi
leal 1(%rsi), %ecx
leal 64(%rsi), %eax
testl %ecx, %ecx
cmovnsl %ecx, %eax
movl %eax, %ecx
andl $-64, %ecx
negl %ecx
leal (%rsi,%rcx), %edx
incl %edx
xorl %ecx, %ecx
cmpl $57, %edx
setge %cl
sarl $6, %eax
movl %eax, %edx
addl %ecx, %edx
js .LBB0_10
# %bb.1: # %.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $344, %rsp # imm = 0x158
.cfi_def_cfa_offset 400
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
movslq %esi, %r15
addl %ecx, %eax
incl %eax
movq %rax, (%rsp) # 8-byte Spill
xorl %r13d, %r13d
movl $128, %ebp
xorl %r14d, %r14d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_8: # %_Z6f_CUDAjjji.exit.preheader
# in Loop: Header=BB0_2 Depth=1
addq $-64, %r15
incq %r14
movq 8(%rsp), %r13 # 8-byte Reload
addq $64, %r13
cmpq (%rsp), %r14 # 8-byte Folded Reload
je .LBB0_9
.LBB0_2: # =>This Loop Header: Depth=1
# Child Loop BB0_3 Depth 2
# Child Loop BB0_4 Depth 3
movq %r13, 8(%rsp) # 8-byte Spill
shrq $2, %r13
movl %r15d, %r12d
negq %r12
movl $320, %edx # imm = 0x140
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq memset@PLT
xorl %eax, %eax
xorl %ecx, %ecx
jmp .LBB0_3
.p2align 4, 0x90
.LBB0_7: # in Loop: Header=BB0_3 Depth=2
movl %esi, 16(%rsp,%rcx,4)
incq %rcx
incl %r13d
addq $4, %rax
cmpq $16, %rcx
je .LBB0_8
.LBB0_3: # %.preheader
# Parent Loop BB0_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_4 Depth 3
leal (,%r13,4), %edx
addq %rbx, %rdx
movl 16(%rsp,%rcx,4), %esi
leaq (%r12,%rax), %rdi
xorl %r8d, %r8d
jmp .LBB0_4
.p2align 4, 0x90
.LBB0_6: # in Loop: Header=BB0_4 Depth=3
movq %rdi, %r10
addq %r8, %r10
cmovel %ebp, %r9d
movq %r8, %r10
xorq $3, %r10
imull expo_d(,%r10,4), %r9d
addl %r9d, %esi
incq %r8
cmpq $4, %r8
je .LBB0_7
.LBB0_4: # Parent Loop BB0_2 Depth=1
# Parent Loop BB0_3 Depth=2
# => This Inner Loop Header: Depth=3
leaq (%rax,%r8), %r10
xorl %r9d, %r9d
cmpq %r15, %r10
jge .LBB0_6
# %bb.5: # in Loop: Header=BB0_4 Depth=3
movzbl (%rdx,%r8), %r9d
jmp .LBB0_6
.LBB0_9:
addq $344, %rsp # imm = 0x158
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB0_10: # %._crit_edge
retq
.Lfunc_end0:
.size _Z4SHA1PhiPjS0_S0_S0_S0_, .Lfunc_end0-_Z4SHA1PhiPjS0_S0_S0_S0_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
movl $expo_d, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $16, %r9d
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type expo_d,@object # @expo_d
.local expo_d
.comm expo_d,16,16
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "expo_d"
.size .L__unnamed_1, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym expo_d
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#ifndef _KERNEL_H
#define _KERNEL_H
typedef struct Node {
int starting;
int no_of_edges;
}Node;
#endif
__global__ void test1(bool* d_graph_visited, int no_of_nodes) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < no_of_nodes) {
d_graph_visited[tid] = true;
}
} | code for sm_80
Function : _Z5test1Pbi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R2, P0, R0.reuse, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x040fe20007f1e0ff */
/*0070*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0090*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000037a11 */
/* 0x000fe400000f0eff */
/*00a0*/ PRMT R0, R4, 0x7610, R0 ; /* 0x0000761004007816 */
/* 0x000fca0000000000 */
/*00b0*/ STG.E.U8 [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101104 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#ifndef _KERNEL_H
#define _KERNEL_H
typedef struct Node {
int starting;
int no_of_edges;
}Node;
#endif
__global__ void test1(bool* d_graph_visited, int no_of_nodes) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < no_of_nodes) {
d_graph_visited[tid] = true;
}
} | .file "tmpxft_00144374_00000000-6_test1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z5test1PbiPbi
.type _Z25__device_stub__Z5test1PbiPbi, @function
_Z25__device_stub__Z5test1PbiPbi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5test1Pbi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z25__device_stub__Z5test1PbiPbi, .-_Z25__device_stub__Z5test1PbiPbi
.globl _Z5test1Pbi
.type _Z5test1Pbi, @function
_Z5test1Pbi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z5test1PbiPbi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5test1Pbi, .-_Z5test1Pbi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5test1Pbi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5test1Pbi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#ifndef _KERNEL_H
#define _KERNEL_H
typedef struct Node {
int starting;
int no_of_edges;
}Node;
#endif
__global__ void test1(bool* d_graph_visited, int no_of_nodes) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < no_of_nodes) {
d_graph_visited[tid] = true;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
#ifndef _KERNEL_H
#define _KERNEL_H
typedef struct Node {
int starting;
int no_of_edges;
}Node;
#endif
__global__ void test1(bool* d_graph_visited, int no_of_nodes) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < no_of_nodes) {
d_graph_visited[tid] = true;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#ifndef _KERNEL_H
#define _KERNEL_H
typedef struct Node {
int starting;
int no_of_edges;
}Node;
#endif
__global__ void test1(bool* d_graph_visited, int no_of_nodes) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < no_of_nodes) {
d_graph_visited[tid] = true;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5test1Pbi
.globl _Z5test1Pbi
.p2align 8
.type _Z5test1Pbi,@function
_Z5test1Pbi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
v_mov_b32_e32 v2, 1
global_store_b8 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5test1Pbi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5test1Pbi, .Lfunc_end0-_Z5test1Pbi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5test1Pbi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5test1Pbi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#ifndef _KERNEL_H
#define _KERNEL_H
typedef struct Node {
int starting;
int no_of_edges;
}Node;
#endif
__global__ void test1(bool* d_graph_visited, int no_of_nodes) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < no_of_nodes) {
d_graph_visited[tid] = true;
}
} | .text
.file "test1.hip"
.globl _Z20__device_stub__test1Pbi # -- Begin function _Z20__device_stub__test1Pbi
.p2align 4, 0x90
.type _Z20__device_stub__test1Pbi,@function
_Z20__device_stub__test1Pbi: # @_Z20__device_stub__test1Pbi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z5test1Pbi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z20__device_stub__test1Pbi, .Lfunc_end0-_Z20__device_stub__test1Pbi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5test1Pbi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5test1Pbi,@object # @_Z5test1Pbi
.section .rodata,"a",@progbits
.globl _Z5test1Pbi
.p2align 3, 0x0
_Z5test1Pbi:
.quad _Z20__device_stub__test1Pbi
.size _Z5test1Pbi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5test1Pbi"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__test1Pbi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5test1Pbi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5test1Pbi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R2, P0, R0.reuse, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x040fe20007f1e0ff */
/*0070*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0090*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000037a11 */
/* 0x000fe400000f0eff */
/*00a0*/ PRMT R0, R4, 0x7610, R0 ; /* 0x0000761004007816 */
/* 0x000fca0000000000 */
/*00b0*/ STG.E.U8 [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101104 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5test1Pbi
.globl _Z5test1Pbi
.p2align 8
.type _Z5test1Pbi,@function
_Z5test1Pbi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
v_mov_b32_e32 v2, 1
global_store_b8 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5test1Pbi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5test1Pbi, .Lfunc_end0-_Z5test1Pbi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5test1Pbi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5test1Pbi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00144374_00000000-6_test1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z5test1PbiPbi
.type _Z25__device_stub__Z5test1PbiPbi, @function
_Z25__device_stub__Z5test1PbiPbi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5test1Pbi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z25__device_stub__Z5test1PbiPbi, .-_Z25__device_stub__Z5test1PbiPbi
.globl _Z5test1Pbi
.type _Z5test1Pbi, @function
_Z5test1Pbi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z5test1PbiPbi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5test1Pbi, .-_Z5test1Pbi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5test1Pbi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5test1Pbi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test1.hip"
.globl _Z20__device_stub__test1Pbi # -- Begin function _Z20__device_stub__test1Pbi
.p2align 4, 0x90
.type _Z20__device_stub__test1Pbi,@function
_Z20__device_stub__test1Pbi: # @_Z20__device_stub__test1Pbi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z5test1Pbi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z20__device_stub__test1Pbi, .Lfunc_end0-_Z20__device_stub__test1Pbi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5test1Pbi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5test1Pbi,@object # @_Z5test1Pbi
.section .rodata,"a",@progbits
.globl _Z5test1Pbi
.p2align 3, 0x0
_Z5test1Pbi:
.quad _Z20__device_stub__test1Pbi
.size _Z5test1Pbi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5test1Pbi"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__test1Pbi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5test1Pbi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<math.h>
#define N 8
__global__ void exclusive_scan(int *d_in) {
__shared__ int temp_in[N];
int id = threadIdx.x;
temp_in[id] = d_in[id];
__syncthreads();
unsigned int s = 1;
for(; s <= N-1; s <<= 1) {
int i = 2 * s * (threadIdx.x + 1) - 1;
if(i >= s && i < N){
//printf("s = %d, i = %d \n", s, i);
int a = temp_in[i];
int b = temp_in[i-s];
__syncthreads();
temp_in[i] = a + b;
}
__syncthreads();
}
if(threadIdx.x == 0) {
temp_in[N-1] = 0;
}
for(s = s/2; s >= 1; s >>= 1) {
int i = 2*s*(threadIdx.x+1)-1;
if(i >= s && i < N){
//printf("s = %d, i = %d \n", s, i);
int r = temp_in[i];
int l = temp_in[i-s];
__syncthreads();
temp_in[i] = l + r;
temp_in[i-s] = r;
}
__syncthreads();
}
d_in[id] = temp_in[id];
//Teacher's code
/*
//Phase 1 Uptree
int s = 1;
for(; s <= N-1; s <<= 1) {
int i = 2 * s * (threadIdx.x + 1) - 1;
if(i-s >= 0 && i < N){
//printf("s = %d, i = %d \n", s, i);
int a = d_in[i];
int b = d_in[i-s];
__syncthreads();
d_in[i] = a + b;
}
__syncthreads();
}
//Phase 2 Downtree
if(threadIdx.x == 0) {
d_in[N-1] = 0;
}
for(s = s/2; s >= 1; s >>= 1) {
int i = 2*s*(threadIdx.x+1)-1;
if(i-s >= 0 && i < N){
//printf("s = %d, i = %d \n", s, i);
int r = d_in[i];
int l = d_in[i-s];
__syncthreads();
d_in[i] = l + r;
d_in[i-s] = r;
}
__syncthreads();
}
*/
}
__global__ void inclusive_scan(int *d_in) {
__shared__ int temp_in[N];
int i = threadIdx.x;
temp_in[i] = d_in[i];
__syncthreads();
for(unsigned int s = 1; s <= N-1; s <<= 1) {
if(i >= s && i < N) {
int a = temp_in[i];
int b = temp_in[i-s];
int c = a + b;
temp_in[i] = c;
}
__syncthreads();
}
d_in[i] = temp_in[i];
}
int main()
{
int h_in[N] = {3, 1, 7, 0, 4, 1, 6, 3};
int h_out[N];
//for(int i=0; i < N; i++)
// h_in[i] = 1;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
int *d_in;
//int *d_out;
cudaMalloc((void**) &d_in, N*sizeof(int));
//cudaMalloc((void**) &d_out, N*sizeof(int));
cudaMemcpy(d_in, &h_in, N*sizeof(int), cudaMemcpyHostToDevice);
//Implementing kernel call
//Timed each kernel call
cudaEventRecord(start);
//inclusive_scan<<<1, N>>>(d_in);
exclusive_scan<<<1, N>>>(d_in);
cudaEventRecord(stop);
cudaMemcpy(&h_out, d_in, N*sizeof(int), cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
cudaFree(d_in);
//cudaFree(d_out);
for(int i=0; i<N; i++)
printf("out[%d] = %d\n", i, h_out[i]);
printf("Time used: %f milliseconds\n", milliseconds);
return -1;
} | code for sm_80
Function : _Z14inclusive_scanPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE R2, R9, R2, c[0x0][0x160] ; /* 0x0000580009027625 */
/* 0x001fca00078e0202 */
/*0050*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*0060*/ ISETP.GT.AND P0, PT, R9, 0x7, PT ; /* 0x000000070900780c */
/* 0x000fc80003f04270 */
/*0070*/ ISETP.EQ.OR P2, PT, R9.reuse, RZ, P0 ; /* 0x000000ff0900720c */
/* 0x040fe40000742670 */
/*0080*/ ISETP.LT.U32.OR P1, PT, R9.reuse, 0x2, P0 ; /* 0x000000020900780c */
/* 0x040fe40000721470 */
/*0090*/ ISETP.LT.U32.OR P0, PT, R9, 0x4, P0 ; /* 0x000000040900780c */
/* 0x000fe20000701470 */
/*00a0*/ STS [R9.X4], R0 ; /* 0x0000000009007388 */
/* 0x004fe80000004800 */
/*00b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00c0*/ @!P2 LDS R4, [R9.X4] ; /* 0x000000000904a984 */
/* 0x000fe80000004800 */
/*00d0*/ @!P2 LDS R5, [R9.X4+-0x4] ; /* 0xfffffc000905a984 */
/* 0x000e240000004800 */
/*00e0*/ @!P2 IADD3 R4, R4, R5, RZ ; /* 0x000000050404a210 */
/* 0x001fca0007ffe0ff */
/*00f0*/ @!P2 STS [R9.X4], R4 ; /* 0x000000040900a388 */
/* 0x000fe80000004800 */
/*0100*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0110*/ @!P1 LDS R5, [R9.X4] ; /* 0x0000000009059984 */
/* 0x000fe80000004800 */
/*0120*/ @!P1 LDS R6, [R9.X4+-0x8] ; /* 0xfffff80009069984 */
/* 0x000e240000004800 */
/*0130*/ @!P1 IMAD.IADD R5, R5, 0x1, R6 ; /* 0x0000000105059824 */
/* 0x001fca00078e0206 */
/*0140*/ @!P1 STS [R9.X4], R5 ; /* 0x0000000509009388 */
/* 0x000fe80000004800 */
/*0150*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0160*/ @!P0 LDS R0, [R9.X4] ; /* 0x0000000009008984 */
/* 0x000fe80000004800 */
/*0170*/ @!P0 LDS R7, [R9.X4+-0x10] ; /* 0xfffff00009078984 */
/* 0x000e240000004800 */
/*0180*/ @!P0 IADD3 R0, R0, R7, RZ ; /* 0x0000000700008210 */
/* 0x001fca0007ffe0ff */
/*0190*/ @!P0 STS [R9.X4], R0 ; /* 0x0000000009008388 */
/* 0x000fe80000004800 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01b0*/ LDS R7, [R9.X4] ; /* 0x0000000009077984 */
/* 0x000e280000004800 */
/*01c0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z14exclusive_scanPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fca00078e0203 */
/*0050*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IADD3 R6, R0.reuse, 0x1, RZ ; /* 0x0000000100067810 */
/* 0x040fe40007ffe0ff */
/*0070*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*0080*/ LEA R4, R6, 0xffffffff, 0x1 ; /* 0xffffffff06047811 */
/* 0x000fc800078e08ff */
/*0090*/ ISETP.GT.AND P3, PT, R4, 0x7, PT ; /* 0x000000070400780c */
/* 0x000fe20003f64270 */
/*00a0*/ IMAD.SHL.U32 R4, R0, 0x4, RZ ; /* 0x0000000400047824 */
/* 0x000fca00078e00ff */
/*00b0*/ IADD3 R8, R4, 0x3, RZ ; /* 0x0000000304087810 */
/* 0x000fe20007ffe0ff */
/*00c0*/ IMAD.SHL.U32 R4, R6, 0x8, RZ ; /* 0x0000000806047824 */
/* 0x000fc600078e00ff */
/*00d0*/ ISETP.GT.AND P2, PT, R8, 0x7, PT ; /* 0x000000070800780c */
/* 0x000fe40003f44270 */
/*00e0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fc80007ffe0ff */
/*00f0*/ ISETP.GT.AND P1, PT, R4, 0x7, PT ; /* 0x000000070400780c */
/* 0x000fe20003f24270 */
/*0100*/ STS [R0.X4], R5 ; /* 0x0000000500007388 */
/* 0x004fe80000004800 */
/*0110*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0120*/ @!P3 WARPSYNC 0xffffffff ; /* 0xffffffff0000b948 */
/* 0x000fe20003800000 */
/*0130*/ @!P3 LDS.64 R10, [R6.X8+-0x8] ; /* 0xfffff800060ab984 */
/* 0x000e240000008a00 */
/*0140*/ @!P3 IADD3 R7, R11, R10, RZ ; /* 0x0000000a0b07b210 */
/* 0x001fc40007ffe0ff */
/*0150*/ @!P3 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x000000000000bb1d */
/* 0x000fec0000010000 */
/*0160*/ @!P3 STS [R6.X8+-0x4], R7 ; /* 0xfffffc070600b388 */
/* 0x000fe80000008800 */
/*0170*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0180*/ @!P2 WARPSYNC 0xffffffff ; /* 0xffffffff0000a948 */
/* 0x000fe20003800000 */
/*0190*/ @!P2 LDS R5, [R8.X4] ; /* 0x000000000805a984 */
/* 0x000fe80000004800 */
/*01a0*/ @!P2 LDS R10, [R8.X4+-0x8] ; /* 0xfffff800080aa984 */
/* 0x000e240000004800 */
/*01b0*/ @!P2 IMAD.IADD R5, R5, 0x1, R10 ; /* 0x000000010505a824 */
/* 0x001fc400078e020a */
/*01c0*/ @!P2 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x000000000000ab1d */
/* 0x000fec0000010000 */
/*01d0*/ @!P2 STS [R8.X4], R5 ; /* 0x000000050800a388 */
/* 0x000fe80000004800 */
/*01e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01f0*/ @!P1 WARPSYNC 0xffffffff ; /* 0xffffffff00009948 */
/* 0x000fe20003800000 */
/*0200*/ @!P1 LDS R7, [R4.X4] ; /* 0x0000000004079984 */
/* 0x000fe80000004800 */
/*0210*/ @!P1 LDS R10, [R4.X4+-0x10] ; /* 0xfffff000040a9984 */
/* 0x000e240000004800 */
/*0220*/ @!P1 IADD3 R7, R7, R10, RZ ; /* 0x0000000a07079210 */
/* 0x001fc40007ffe0ff */
/*0230*/ @!P1 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000009b1d */
/* 0x000fec0000010000 */
/*0240*/ @!P1 STS [R4.X4], R7 ; /* 0x0000000704009388 */
/* 0x000fe80000004800 */
/*0250*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0260*/ @!P1 WARPSYNC 0xffffffff ; /* 0xffffffff00009948 */
/* 0x000fe20003800000 */
/*0270*/ @!P0 STS [0x1c], RZ ; /* 0x00001cffff008388 */
/* 0x000fe80000000800 */
/*0280*/ @!P1 LDS R5, [R4.X4] ; /* 0x0000000004059984 */
/* 0x000e280000004800 */
/*0290*/ @!P1 LDS R10, [R4.X4+-0x10] ; /* 0xfffff000040a9984 */
/* 0x000e680000004800 */
/*02a0*/ @!P1 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000009b1d */
/* 0x000fec0000010000 */
/*02b0*/ @!P1 STS [R4.X4+-0x10], R5 ; /* 0xfffff00504009388 */
/* 0x001fe20000004800 */
/*02c0*/ @!P1 IMAD.IADD R9, R5, 0x1, R10 ; /* 0x0000000105099824 */
/* 0x002fca00078e020a */
/*02d0*/ @!P1 STS [R4.X4], R9 ; /* 0x0000000904009388 */
/* 0x000fe80000004800 */
/*02e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02f0*/ @!P2 WARPSYNC 0xffffffff ; /* 0xffffffff0000a948 */
/* 0x000fe20003800000 */
/*0300*/ @!P2 LDS R7, [R8.X4] ; /* 0x000000000807a984 */
/* 0x000e280000004800 */
/*0310*/ @!P2 LDS R10, [R8.X4+-0x8] ; /* 0xfffff800080aa984 */
/* 0x000e680000004800 */
/*0320*/ @!P2 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x000000000000ab1d */
/* 0x000fec0000010000 */
/*0330*/ @!P2 STS [R8.X4+-0x8], R7 ; /* 0xfffff8070800a388 */
/* 0x001fe20000004800 */
/*0340*/ @!P2 IMAD.IADD R11, R7, 0x1, R10 ; /* 0x00000001070ba824 */
/* 0x002fca00078e020a */
/*0350*/ @!P2 STS [R8.X4], R11 ; /* 0x0000000b0800a388 */
/* 0x000fe80000004800 */
/*0360*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0370*/ @!P3 WARPSYNC 0xffffffff ; /* 0xffffffff0000b948 */
/* 0x000fe20003800000 */
/*0380*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0390*/ @!P3 LDS.64 R12, [R6.X8+-0x8] ; /* 0xfffff800060cb984 */
/* 0x000e240000008a00 */
/*03a0*/ @!P3 IADD3 R15, R13, R12, RZ ; /* 0x0000000c0d0fb210 */
/* 0x001fe20007ffe0ff */
/*03b0*/ IMAD.MOV.U32 R14, RZ, RZ, R13 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e000d */
/*03c0*/ @!P3 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x000000000000bb1d */
/* 0x000fec0000010000 */
/*03d0*/ @!P3 STS.64 [R6.X8+-0x8], R14 ; /* 0xfffff80e0600b388 */
/* 0x000fe80000008a00 */
/*03e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03f0*/ LDS R5, [R0.X4] ; /* 0x0000000000057984 */
/* 0x000e280000004800 */
/*0400*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0410*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0420*/ BRA 0x420; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
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