system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<math.h>
#define N 8
__global__ void exclusive_scan(int *d_in) {
__shared__ int temp_in[N];
int id = threadIdx.x;
temp_in[id] = d_in[id];
__syncthreads();
unsigned int s = 1;
for(; s <= N-1; s <<= 1) {
int i = 2 * s * (threadIdx.x + 1) - 1;
if(i >= s && i < N){
//printf("s = %d, i = %d \n", s, i);
int a = temp_in[i];
int b = temp_in[i-s];
__syncthreads();
temp_in[i] = a + b;
}
__syncthreads();
}
if(threadIdx.x == 0) {
temp_in[N-1] = 0;
}
for(s = s/2; s >= 1; s >>= 1) {
int i = 2*s*(threadIdx.x+1)-1;
if(i >= s && i < N){
//printf("s = %d, i = %d \n", s, i);
int r = temp_in[i];
int l = temp_in[i-s];
__syncthreads();
temp_in[i] = l + r;
temp_in[i-s] = r;
}
__syncthreads();
}
d_in[id] = temp_in[id];
//Teacher's code
/*
//Phase 1 Uptree
int s = 1;
for(; s <= N-1; s <<= 1) {
int i = 2 * s * (threadIdx.x + 1) - 1;
if(i-s >= 0 && i < N){
//printf("s = %d, i = %d \n", s, i);
int a = d_in[i];
int b = d_in[i-s];
__syncthreads();
d_in[i] = a + b;
}
__syncthreads();
}
//Phase 2 Downtree
if(threadIdx.x == 0) {
d_in[N-1] = 0;
}
for(s = s/2; s >= 1; s >>= 1) {
int i = 2*s*(threadIdx.x+1)-1;
if(i-s >= 0 && i < N){
//printf("s = %d, i = %d \n", s, i);
int r = d_in[i];
int l = d_in[i-s];
__syncthreads();
d_in[i] = l + r;
d_in[i-s] = r;
}
__syncthreads();
}
*/
}
__global__ void inclusive_scan(int *d_in) {
__shared__ int temp_in[N];
int i = threadIdx.x;
temp_in[i] = d_in[i];
__syncthreads();
for(unsigned int s = 1; s <= N-1; s <<= 1) {
if(i >= s && i < N) {
int a = temp_in[i];
int b = temp_in[i-s];
int c = a + b;
temp_in[i] = c;
}
__syncthreads();
}
d_in[i] = temp_in[i];
}
int main()
{
int h_in[N] = {3, 1, 7, 0, 4, 1, 6, 3};
int h_out[N];
//for(int i=0; i < N; i++)
// h_in[i] = 1;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
int *d_in;
//int *d_out;
cudaMalloc((void**) &d_in, N*sizeof(int));
//cudaMalloc((void**) &d_out, N*sizeof(int));
cudaMemcpy(d_in, &h_in, N*sizeof(int), cudaMemcpyHostToDevice);
//Implementing kernel call
//Timed each kernel call
cudaEventRecord(start);
//inclusive_scan<<<1, N>>>(d_in);
exclusive_scan<<<1, N>>>(d_in);
cudaEventRecord(stop);
cudaMemcpy(&h_out, d_in, N*sizeof(int), cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
cudaFree(d_in);
//cudaFree(d_out);
for(int i=0; i<N; i++)
printf("out[%d] = %d\n", i, h_out[i]);
printf("Time used: %f milliseconds\n", milliseconds);
return -1;
} | .file "tmpxft_000df553_00000000-6_scan_template.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z14exclusive_scanPiPi
.type _Z34__device_stub__Z14exclusive_scanPiPi, @function
_Z34__device_stub__Z14exclusive_scanPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14exclusive_scanPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z14exclusive_scanPiPi, .-_Z34__device_stub__Z14exclusive_scanPiPi
.globl _Z14exclusive_scanPi
.type _Z14exclusive_scanPi, @function
_Z14exclusive_scanPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z14exclusive_scanPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14exclusive_scanPi, .-_Z14exclusive_scanPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "out[%d] = %d\n"
.LC2:
.string "Time used: %f milliseconds\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $136, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $3, 48(%rsp)
movl $1, 52(%rsp)
movl $7, 56(%rsp)
movl $0, 60(%rsp)
movl $4, 64(%rsp)
movl $1, 68(%rsp)
movl $6, 72(%rsp)
movl $3, 76(%rsp)
movq %rsp, %rdi
call cudaEventCreate@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $32, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq (%rsp), %rdi
call cudaEventRecord@PLT
movl $8, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
leaq 80(%rsp), %rdi
movl $2, %ecx
movl $32, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 36(%rsp)
leaq 36(%rsp), %rdi
movq 8(%rsp), %rdx
movq (%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movl $0, %ebx
leaq .LC1(%rip), %rbp
.L13:
movl 80(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $8, %rbx
jne .L13
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $-1, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 16(%rsp), %rdi
call _Z34__device_stub__Z14exclusive_scanPiPi
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z34__device_stub__Z14inclusive_scanPiPi
.type _Z34__device_stub__Z14inclusive_scanPiPi, @function
_Z34__device_stub__Z14inclusive_scanPiPi:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14inclusive_scanPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z34__device_stub__Z14inclusive_scanPiPi, .-_Z34__device_stub__Z14inclusive_scanPiPi
.globl _Z14inclusive_scanPi
.type _Z14inclusive_scanPi, @function
_Z14inclusive_scanPi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z14inclusive_scanPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z14inclusive_scanPi, .-_Z14inclusive_scanPi
.section .rodata.str1.1
.LC3:
.string "_Z14inclusive_scanPi"
.LC4:
.string "_Z14exclusive_scanPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z14inclusive_scanPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z14exclusive_scanPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<math.h>
#define N 8
__global__ void exclusive_scan(int *d_in) {
__shared__ int temp_in[N];
int id = threadIdx.x;
temp_in[id] = d_in[id];
__syncthreads();
unsigned int s = 1;
for(; s <= N-1; s <<= 1) {
int i = 2 * s * (threadIdx.x + 1) - 1;
if(i >= s && i < N){
//printf("s = %d, i = %d \n", s, i);
int a = temp_in[i];
int b = temp_in[i-s];
__syncthreads();
temp_in[i] = a + b;
}
__syncthreads();
}
if(threadIdx.x == 0) {
temp_in[N-1] = 0;
}
for(s = s/2; s >= 1; s >>= 1) {
int i = 2*s*(threadIdx.x+1)-1;
if(i >= s && i < N){
//printf("s = %d, i = %d \n", s, i);
int r = temp_in[i];
int l = temp_in[i-s];
__syncthreads();
temp_in[i] = l + r;
temp_in[i-s] = r;
}
__syncthreads();
}
d_in[id] = temp_in[id];
//Teacher's code
/*
//Phase 1 Uptree
int s = 1;
for(; s <= N-1; s <<= 1) {
int i = 2 * s * (threadIdx.x + 1) - 1;
if(i-s >= 0 && i < N){
//printf("s = %d, i = %d \n", s, i);
int a = d_in[i];
int b = d_in[i-s];
__syncthreads();
d_in[i] = a + b;
}
__syncthreads();
}
//Phase 2 Downtree
if(threadIdx.x == 0) {
d_in[N-1] = 0;
}
for(s = s/2; s >= 1; s >>= 1) {
int i = 2*s*(threadIdx.x+1)-1;
if(i-s >= 0 && i < N){
//printf("s = %d, i = %d \n", s, i);
int r = d_in[i];
int l = d_in[i-s];
__syncthreads();
d_in[i] = l + r;
d_in[i-s] = r;
}
__syncthreads();
}
*/
}
__global__ void inclusive_scan(int *d_in) {
__shared__ int temp_in[N];
int i = threadIdx.x;
temp_in[i] = d_in[i];
__syncthreads();
for(unsigned int s = 1; s <= N-1; s <<= 1) {
if(i >= s && i < N) {
int a = temp_in[i];
int b = temp_in[i-s];
int c = a + b;
temp_in[i] = c;
}
__syncthreads();
}
d_in[i] = temp_in[i];
}
int main()
{
int h_in[N] = {3, 1, 7, 0, 4, 1, 6, 3};
int h_out[N];
//for(int i=0; i < N; i++)
// h_in[i] = 1;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
int *d_in;
//int *d_out;
cudaMalloc((void**) &d_in, N*sizeof(int));
//cudaMalloc((void**) &d_out, N*sizeof(int));
cudaMemcpy(d_in, &h_in, N*sizeof(int), cudaMemcpyHostToDevice);
//Implementing kernel call
//Timed each kernel call
cudaEventRecord(start);
//inclusive_scan<<<1, N>>>(d_in);
exclusive_scan<<<1, N>>>(d_in);
cudaEventRecord(stop);
cudaMemcpy(&h_out, d_in, N*sizeof(int), cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
cudaFree(d_in);
//cudaFree(d_out);
for(int i=0; i<N; i++)
printf("out[%d] = %d\n", i, h_out[i]);
printf("Time used: %f milliseconds\n", milliseconds);
return -1;
} | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<math.h>
#define N 8
__global__ void exclusive_scan(int *d_in) {
__shared__ int temp_in[N];
int id = threadIdx.x;
temp_in[id] = d_in[id];
__syncthreads();
unsigned int s = 1;
for(; s <= N-1; s <<= 1) {
int i = 2 * s * (threadIdx.x + 1) - 1;
if(i >= s && i < N){
//printf("s = %d, i = %d \n", s, i);
int a = temp_in[i];
int b = temp_in[i-s];
__syncthreads();
temp_in[i] = a + b;
}
__syncthreads();
}
if(threadIdx.x == 0) {
temp_in[N-1] = 0;
}
for(s = s/2; s >= 1; s >>= 1) {
int i = 2*s*(threadIdx.x+1)-1;
if(i >= s && i < N){
//printf("s = %d, i = %d \n", s, i);
int r = temp_in[i];
int l = temp_in[i-s];
__syncthreads();
temp_in[i] = l + r;
temp_in[i-s] = r;
}
__syncthreads();
}
d_in[id] = temp_in[id];
//Teacher's code
/*
//Phase 1 Uptree
int s = 1;
for(; s <= N-1; s <<= 1) {
int i = 2 * s * (threadIdx.x + 1) - 1;
if(i-s >= 0 && i < N){
//printf("s = %d, i = %d \n", s, i);
int a = d_in[i];
int b = d_in[i-s];
__syncthreads();
d_in[i] = a + b;
}
__syncthreads();
}
//Phase 2 Downtree
if(threadIdx.x == 0) {
d_in[N-1] = 0;
}
for(s = s/2; s >= 1; s >>= 1) {
int i = 2*s*(threadIdx.x+1)-1;
if(i-s >= 0 && i < N){
//printf("s = %d, i = %d \n", s, i);
int r = d_in[i];
int l = d_in[i-s];
__syncthreads();
d_in[i] = l + r;
d_in[i-s] = r;
}
__syncthreads();
}
*/
}
__global__ void inclusive_scan(int *d_in) {
__shared__ int temp_in[N];
int i = threadIdx.x;
temp_in[i] = d_in[i];
__syncthreads();
for(unsigned int s = 1; s <= N-1; s <<= 1) {
if(i >= s && i < N) {
int a = temp_in[i];
int b = temp_in[i-s];
int c = a + b;
temp_in[i] = c;
}
__syncthreads();
}
d_in[i] = temp_in[i];
}
int main()
{
int h_in[N] = {3, 1, 7, 0, 4, 1, 6, 3};
int h_out[N];
//for(int i=0; i < N; i++)
// h_in[i] = 1;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
int *d_in;
//int *d_out;
hipMalloc((void**) &d_in, N*sizeof(int));
//cudaMalloc((void**) &d_out, N*sizeof(int));
hipMemcpy(d_in, &h_in, N*sizeof(int), hipMemcpyHostToDevice);
//Implementing kernel call
//Timed each kernel call
hipEventRecord(start);
//inclusive_scan<<<1, N>>>(d_in);
exclusive_scan<<<1, N>>>(d_in);
hipEventRecord(stop);
hipMemcpy(&h_out, d_in, N*sizeof(int), hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
hipFree(d_in);
//cudaFree(d_out);
for(int i=0; i<N; i++)
printf("out[%d] = %d\n", i, h_out[i]);
printf("Time used: %f milliseconds\n", milliseconds);
return -1;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<math.h>
#define N 8
__global__ void exclusive_scan(int *d_in) {
__shared__ int temp_in[N];
int id = threadIdx.x;
temp_in[id] = d_in[id];
__syncthreads();
unsigned int s = 1;
for(; s <= N-1; s <<= 1) {
int i = 2 * s * (threadIdx.x + 1) - 1;
if(i >= s && i < N){
//printf("s = %d, i = %d \n", s, i);
int a = temp_in[i];
int b = temp_in[i-s];
__syncthreads();
temp_in[i] = a + b;
}
__syncthreads();
}
if(threadIdx.x == 0) {
temp_in[N-1] = 0;
}
for(s = s/2; s >= 1; s >>= 1) {
int i = 2*s*(threadIdx.x+1)-1;
if(i >= s && i < N){
//printf("s = %d, i = %d \n", s, i);
int r = temp_in[i];
int l = temp_in[i-s];
__syncthreads();
temp_in[i] = l + r;
temp_in[i-s] = r;
}
__syncthreads();
}
d_in[id] = temp_in[id];
//Teacher's code
/*
//Phase 1 Uptree
int s = 1;
for(; s <= N-1; s <<= 1) {
int i = 2 * s * (threadIdx.x + 1) - 1;
if(i-s >= 0 && i < N){
//printf("s = %d, i = %d \n", s, i);
int a = d_in[i];
int b = d_in[i-s];
__syncthreads();
d_in[i] = a + b;
}
__syncthreads();
}
//Phase 2 Downtree
if(threadIdx.x == 0) {
d_in[N-1] = 0;
}
for(s = s/2; s >= 1; s >>= 1) {
int i = 2*s*(threadIdx.x+1)-1;
if(i-s >= 0 && i < N){
//printf("s = %d, i = %d \n", s, i);
int r = d_in[i];
int l = d_in[i-s];
__syncthreads();
d_in[i] = l + r;
d_in[i-s] = r;
}
__syncthreads();
}
*/
}
__global__ void inclusive_scan(int *d_in) {
__shared__ int temp_in[N];
int i = threadIdx.x;
temp_in[i] = d_in[i];
__syncthreads();
for(unsigned int s = 1; s <= N-1; s <<= 1) {
if(i >= s && i < N) {
int a = temp_in[i];
int b = temp_in[i-s];
int c = a + b;
temp_in[i] = c;
}
__syncthreads();
}
d_in[i] = temp_in[i];
}
int main()
{
int h_in[N] = {3, 1, 7, 0, 4, 1, 6, 3};
int h_out[N];
//for(int i=0; i < N; i++)
// h_in[i] = 1;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
int *d_in;
//int *d_out;
hipMalloc((void**) &d_in, N*sizeof(int));
//cudaMalloc((void**) &d_out, N*sizeof(int));
hipMemcpy(d_in, &h_in, N*sizeof(int), hipMemcpyHostToDevice);
//Implementing kernel call
//Timed each kernel call
hipEventRecord(start);
//inclusive_scan<<<1, N>>>(d_in);
exclusive_scan<<<1, N>>>(d_in);
hipEventRecord(stop);
hipMemcpy(&h_out, d_in, N*sizeof(int), hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
hipFree(d_in);
//cudaFree(d_out);
for(int i=0; i<N; i++)
printf("out[%d] = %d\n", i, h_out[i]);
printf("Time used: %f milliseconds\n", milliseconds);
return -1;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14exclusive_scanPi
.globl _Z14exclusive_scanPi
.p2align 8
.type _Z14exclusive_scanPi,@function
_Z14exclusive_scanPi:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 2, v0
v_add_nc_u32_e32 v4, 1, v0
s_mov_b32 s1, 1
s_waitcnt lgkmcnt(0)
global_load_b32 v5, v3, s[2:3]
v_add_co_u32 v1, s0, s2, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, null, s3, 0, s0
s_waitcnt vmcnt(0)
ds_store_b32 v3, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s0
s_cmp_lt_u32 s1, 4
s_mov_b32 s1, s2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_4
.LBB0_2:
s_lshl_b32 s2, s1, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v6, s2, v4
v_add_nc_u32_e32 v5, -1, v6
v_cmp_gt_u32_e64 s0, 9, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s1, v5
s_and_b32 s3, s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s3
s_cbranch_execz .LBB0_1
v_subrev_nc_u32_e32 v6, s1, v5
v_lshlrev_b32_e32 v5, 2, v5
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b32_e32 v6, 2, v6
ds_load_b32 v7, v5
ds_load_b32 v6, v6
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add_nc_u32_e32 v6, v6, v7
ds_store_b32 v5, v6
s_branch .LBB0_1
.LBB0_4:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v4, 0
ds_store_b32 v4, v4 offset:28
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v0, 1, v0
s_mov_b32 s1, 8
s_mov_b32 s0, 4
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_8
.p2align 6
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s0
s_lshr_b32 s0, s1, 1
s_cmp_gt_u32 s1, 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_10
.LBB0_8:
s_and_b32 s1, s1, 14
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u32_u24 v4, s1, v0, -1
v_mul_u32_u24_e32 v5, s1, v0
s_mov_b32 s1, s0
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_u32_e32 vcc_lo, s1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s0, 9, v5
s_and_b32 s2, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s2
s_cbranch_execz .LBB0_7
v_subrev_nc_u32_e32 v5, s1, v4
v_lshlrev_b32_e32 v4, 2, v4
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b32_e32 v5, 2, v5
ds_load_b32 v6, v4
ds_load_b32 v7, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add_nc_u32_e32 v7, v7, v6
ds_store_b32 v4, v7
ds_store_b32 v5, v6
s_branch .LBB0_7
.LBB0_10:
s_set_inst_prefetch_distance 0x2
ds_load_b32 v0, v3
s_waitcnt lgkmcnt(0)
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14exclusive_scanPi
.amdhsa_group_segment_fixed_size 32
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14exclusive_scanPi, .Lfunc_end0-_Z14exclusive_scanPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14inclusive_scanPi
.globl _Z14inclusive_scanPi
.p2align 8
.type _Z14inclusive_scanPi,@function
_Z14inclusive_scanPi:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 2, v0
v_cmp_gt_u32_e32 vcc_lo, 8, v0
s_mov_b32 s1, 1
s_waitcnt lgkmcnt(0)
global_load_b32 v4, v3, s[2:3]
v_add_co_u32 v1, s0, s2, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, null, s3, 0, s0
s_waitcnt vmcnt(0)
ds_store_b32 v3, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB1_2
.p2align 6
.LBB1_1:
s_or_b32 exec_lo, exec_lo, s0
s_lshl_b32 s0, s1, 1
s_cmp_gt_u32 s1, 3
s_mov_b32 s1, s0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_4
.LBB1_2:
v_cmp_le_u32_e64 s0, s1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s0
s_and_saveexec_b32 s0, s2
s_cbranch_execz .LBB1_1
v_subrev_nc_u32_e32 v4, s1, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v4, 2, v4
ds_load_b32 v5, v3
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v4, v4, v5
ds_store_b32 v3, v4
s_branch .LBB1_1
.LBB1_4:
ds_load_b32 v0, v3
s_waitcnt lgkmcnt(0)
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14inclusive_scanPi
.amdhsa_group_segment_fixed_size 32
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z14inclusive_scanPi, .Lfunc_end1-_Z14inclusive_scanPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 32
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14exclusive_scanPi
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z14exclusive_scanPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 32
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14inclusive_scanPi
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z14inclusive_scanPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<math.h>
#define N 8
__global__ void exclusive_scan(int *d_in) {
__shared__ int temp_in[N];
int id = threadIdx.x;
temp_in[id] = d_in[id];
__syncthreads();
unsigned int s = 1;
for(; s <= N-1; s <<= 1) {
int i = 2 * s * (threadIdx.x + 1) - 1;
if(i >= s && i < N){
//printf("s = %d, i = %d \n", s, i);
int a = temp_in[i];
int b = temp_in[i-s];
__syncthreads();
temp_in[i] = a + b;
}
__syncthreads();
}
if(threadIdx.x == 0) {
temp_in[N-1] = 0;
}
for(s = s/2; s >= 1; s >>= 1) {
int i = 2*s*(threadIdx.x+1)-1;
if(i >= s && i < N){
//printf("s = %d, i = %d \n", s, i);
int r = temp_in[i];
int l = temp_in[i-s];
__syncthreads();
temp_in[i] = l + r;
temp_in[i-s] = r;
}
__syncthreads();
}
d_in[id] = temp_in[id];
//Teacher's code
/*
//Phase 1 Uptree
int s = 1;
for(; s <= N-1; s <<= 1) {
int i = 2 * s * (threadIdx.x + 1) - 1;
if(i-s >= 0 && i < N){
//printf("s = %d, i = %d \n", s, i);
int a = d_in[i];
int b = d_in[i-s];
__syncthreads();
d_in[i] = a + b;
}
__syncthreads();
}
//Phase 2 Downtree
if(threadIdx.x == 0) {
d_in[N-1] = 0;
}
for(s = s/2; s >= 1; s >>= 1) {
int i = 2*s*(threadIdx.x+1)-1;
if(i-s >= 0 && i < N){
//printf("s = %d, i = %d \n", s, i);
int r = d_in[i];
int l = d_in[i-s];
__syncthreads();
d_in[i] = l + r;
d_in[i-s] = r;
}
__syncthreads();
}
*/
}
__global__ void inclusive_scan(int *d_in) {
__shared__ int temp_in[N];
int i = threadIdx.x;
temp_in[i] = d_in[i];
__syncthreads();
for(unsigned int s = 1; s <= N-1; s <<= 1) {
if(i >= s && i < N) {
int a = temp_in[i];
int b = temp_in[i-s];
int c = a + b;
temp_in[i] = c;
}
__syncthreads();
}
d_in[i] = temp_in[i];
}
int main()
{
int h_in[N] = {3, 1, 7, 0, 4, 1, 6, 3};
int h_out[N];
//for(int i=0; i < N; i++)
// h_in[i] = 1;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
int *d_in;
//int *d_out;
hipMalloc((void**) &d_in, N*sizeof(int));
//cudaMalloc((void**) &d_out, N*sizeof(int));
hipMemcpy(d_in, &h_in, N*sizeof(int), hipMemcpyHostToDevice);
//Implementing kernel call
//Timed each kernel call
hipEventRecord(start);
//inclusive_scan<<<1, N>>>(d_in);
exclusive_scan<<<1, N>>>(d_in);
hipEventRecord(stop);
hipMemcpy(&h_out, d_in, N*sizeof(int), hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
hipFree(d_in);
//cudaFree(d_out);
for(int i=0; i<N; i++)
printf("out[%d] = %d\n", i, h_out[i]);
printf("Time used: %f milliseconds\n", milliseconds);
return -1;
} | .text
.file "scan_template.hip"
.globl _Z29__device_stub__exclusive_scanPi # -- Begin function _Z29__device_stub__exclusive_scanPi
.p2align 4, 0x90
.type _Z29__device_stub__exclusive_scanPi,@function
_Z29__device_stub__exclusive_scanPi: # @_Z29__device_stub__exclusive_scanPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z14exclusive_scanPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z29__device_stub__exclusive_scanPi, .Lfunc_end0-_Z29__device_stub__exclusive_scanPi
.cfi_endproc
# -- End function
.globl _Z29__device_stub__inclusive_scanPi # -- Begin function _Z29__device_stub__inclusive_scanPi
.p2align 4, 0x90
.type _Z29__device_stub__inclusive_scanPi,@function
_Z29__device_stub__inclusive_scanPi: # @_Z29__device_stub__inclusive_scanPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z14inclusive_scanPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z29__device_stub__inclusive_scanPi, .Lfunc_end1-_Z29__device_stub__inclusive_scanPi
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI2_0:
.long 3 # 0x3
.long 1 # 0x1
.long 7 # 0x7
.long 0 # 0x0
.LCPI2_1:
.long 4 # 0x4
.long 1 # 0x1
.long 6 # 0x6
.long 3 # 0x3
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
movaps .LCPI2_0(%rip), %xmm0 # xmm0 = [3,1,7,0]
movaps %xmm0, 112(%rsp)
movaps .LCPI2_1(%rip), %xmm0 # xmm0 = [4,1,6,3]
movaps %xmm0, 128(%rsp)
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
movl $32, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 112(%rsp), %rsi
movl $32, %edx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 7(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 48(%rsp)
leaq 80(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14exclusive_scanPi, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rsi
leaq 80(%rsp), %rdi
movl $32, %edx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipEventSynchronize
movl $0, 24(%rsp)
movq 40(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 24(%rsp), %rdi
callq hipEventElapsedTime
movq 8(%rsp), %rdi
callq hipFree
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx,4), %edx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $8, %rbx
jne .LBB2_3
# %bb.4:
movss 24(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movl $-1, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14exclusive_scanPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14inclusive_scanPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14exclusive_scanPi,@object # @_Z14exclusive_scanPi
.section .rodata,"a",@progbits
.globl _Z14exclusive_scanPi
.p2align 3, 0x0
_Z14exclusive_scanPi:
.quad _Z29__device_stub__exclusive_scanPi
.size _Z14exclusive_scanPi, 8
.type _Z14inclusive_scanPi,@object # @_Z14inclusive_scanPi
.globl _Z14inclusive_scanPi
.p2align 3, 0x0
_Z14inclusive_scanPi:
.quad _Z29__device_stub__inclusive_scanPi
.size _Z14inclusive_scanPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "out[%d] = %d\n"
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Time used: %f milliseconds\n"
.size .L.str.1, 28
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14exclusive_scanPi"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z14inclusive_scanPi"
.size .L__unnamed_2, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__exclusive_scanPi
.addrsig_sym _Z29__device_stub__inclusive_scanPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14exclusive_scanPi
.addrsig_sym _Z14inclusive_scanPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14inclusive_scanPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE R2, R9, R2, c[0x0][0x160] ; /* 0x0000580009027625 */
/* 0x001fca00078e0202 */
/*0050*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*0060*/ ISETP.GT.AND P0, PT, R9, 0x7, PT ; /* 0x000000070900780c */
/* 0x000fc80003f04270 */
/*0070*/ ISETP.EQ.OR P2, PT, R9.reuse, RZ, P0 ; /* 0x000000ff0900720c */
/* 0x040fe40000742670 */
/*0080*/ ISETP.LT.U32.OR P1, PT, R9.reuse, 0x2, P0 ; /* 0x000000020900780c */
/* 0x040fe40000721470 */
/*0090*/ ISETP.LT.U32.OR P0, PT, R9, 0x4, P0 ; /* 0x000000040900780c */
/* 0x000fe20000701470 */
/*00a0*/ STS [R9.X4], R0 ; /* 0x0000000009007388 */
/* 0x004fe80000004800 */
/*00b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00c0*/ @!P2 LDS R4, [R9.X4] ; /* 0x000000000904a984 */
/* 0x000fe80000004800 */
/*00d0*/ @!P2 LDS R5, [R9.X4+-0x4] ; /* 0xfffffc000905a984 */
/* 0x000e240000004800 */
/*00e0*/ @!P2 IADD3 R4, R4, R5, RZ ; /* 0x000000050404a210 */
/* 0x001fca0007ffe0ff */
/*00f0*/ @!P2 STS [R9.X4], R4 ; /* 0x000000040900a388 */
/* 0x000fe80000004800 */
/*0100*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0110*/ @!P1 LDS R5, [R9.X4] ; /* 0x0000000009059984 */
/* 0x000fe80000004800 */
/*0120*/ @!P1 LDS R6, [R9.X4+-0x8] ; /* 0xfffff80009069984 */
/* 0x000e240000004800 */
/*0130*/ @!P1 IMAD.IADD R5, R5, 0x1, R6 ; /* 0x0000000105059824 */
/* 0x001fca00078e0206 */
/*0140*/ @!P1 STS [R9.X4], R5 ; /* 0x0000000509009388 */
/* 0x000fe80000004800 */
/*0150*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0160*/ @!P0 LDS R0, [R9.X4] ; /* 0x0000000009008984 */
/* 0x000fe80000004800 */
/*0170*/ @!P0 LDS R7, [R9.X4+-0x10] ; /* 0xfffff00009078984 */
/* 0x000e240000004800 */
/*0180*/ @!P0 IADD3 R0, R0, R7, RZ ; /* 0x0000000700008210 */
/* 0x001fca0007ffe0ff */
/*0190*/ @!P0 STS [R9.X4], R0 ; /* 0x0000000009008388 */
/* 0x000fe80000004800 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01b0*/ LDS R7, [R9.X4] ; /* 0x0000000009077984 */
/* 0x000e280000004800 */
/*01c0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z14exclusive_scanPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fca00078e0203 */
/*0050*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IADD3 R6, R0.reuse, 0x1, RZ ; /* 0x0000000100067810 */
/* 0x040fe40007ffe0ff */
/*0070*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*0080*/ LEA R4, R6, 0xffffffff, 0x1 ; /* 0xffffffff06047811 */
/* 0x000fc800078e08ff */
/*0090*/ ISETP.GT.AND P3, PT, R4, 0x7, PT ; /* 0x000000070400780c */
/* 0x000fe20003f64270 */
/*00a0*/ IMAD.SHL.U32 R4, R0, 0x4, RZ ; /* 0x0000000400047824 */
/* 0x000fca00078e00ff */
/*00b0*/ IADD3 R8, R4, 0x3, RZ ; /* 0x0000000304087810 */
/* 0x000fe20007ffe0ff */
/*00c0*/ IMAD.SHL.U32 R4, R6, 0x8, RZ ; /* 0x0000000806047824 */
/* 0x000fc600078e00ff */
/*00d0*/ ISETP.GT.AND P2, PT, R8, 0x7, PT ; /* 0x000000070800780c */
/* 0x000fe40003f44270 */
/*00e0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fc80007ffe0ff */
/*00f0*/ ISETP.GT.AND P1, PT, R4, 0x7, PT ; /* 0x000000070400780c */
/* 0x000fe20003f24270 */
/*0100*/ STS [R0.X4], R5 ; /* 0x0000000500007388 */
/* 0x004fe80000004800 */
/*0110*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0120*/ @!P3 WARPSYNC 0xffffffff ; /* 0xffffffff0000b948 */
/* 0x000fe20003800000 */
/*0130*/ @!P3 LDS.64 R10, [R6.X8+-0x8] ; /* 0xfffff800060ab984 */
/* 0x000e240000008a00 */
/*0140*/ @!P3 IADD3 R7, R11, R10, RZ ; /* 0x0000000a0b07b210 */
/* 0x001fc40007ffe0ff */
/*0150*/ @!P3 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x000000000000bb1d */
/* 0x000fec0000010000 */
/*0160*/ @!P3 STS [R6.X8+-0x4], R7 ; /* 0xfffffc070600b388 */
/* 0x000fe80000008800 */
/*0170*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0180*/ @!P2 WARPSYNC 0xffffffff ; /* 0xffffffff0000a948 */
/* 0x000fe20003800000 */
/*0190*/ @!P2 LDS R5, [R8.X4] ; /* 0x000000000805a984 */
/* 0x000fe80000004800 */
/*01a0*/ @!P2 LDS R10, [R8.X4+-0x8] ; /* 0xfffff800080aa984 */
/* 0x000e240000004800 */
/*01b0*/ @!P2 IMAD.IADD R5, R5, 0x1, R10 ; /* 0x000000010505a824 */
/* 0x001fc400078e020a */
/*01c0*/ @!P2 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x000000000000ab1d */
/* 0x000fec0000010000 */
/*01d0*/ @!P2 STS [R8.X4], R5 ; /* 0x000000050800a388 */
/* 0x000fe80000004800 */
/*01e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01f0*/ @!P1 WARPSYNC 0xffffffff ; /* 0xffffffff00009948 */
/* 0x000fe20003800000 */
/*0200*/ @!P1 LDS R7, [R4.X4] ; /* 0x0000000004079984 */
/* 0x000fe80000004800 */
/*0210*/ @!P1 LDS R10, [R4.X4+-0x10] ; /* 0xfffff000040a9984 */
/* 0x000e240000004800 */
/*0220*/ @!P1 IADD3 R7, R7, R10, RZ ; /* 0x0000000a07079210 */
/* 0x001fc40007ffe0ff */
/*0230*/ @!P1 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000009b1d */
/* 0x000fec0000010000 */
/*0240*/ @!P1 STS [R4.X4], R7 ; /* 0x0000000704009388 */
/* 0x000fe80000004800 */
/*0250*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0260*/ @!P1 WARPSYNC 0xffffffff ; /* 0xffffffff00009948 */
/* 0x000fe20003800000 */
/*0270*/ @!P0 STS [0x1c], RZ ; /* 0x00001cffff008388 */
/* 0x000fe80000000800 */
/*0280*/ @!P1 LDS R5, [R4.X4] ; /* 0x0000000004059984 */
/* 0x000e280000004800 */
/*0290*/ @!P1 LDS R10, [R4.X4+-0x10] ; /* 0xfffff000040a9984 */
/* 0x000e680000004800 */
/*02a0*/ @!P1 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000009b1d */
/* 0x000fec0000010000 */
/*02b0*/ @!P1 STS [R4.X4+-0x10], R5 ; /* 0xfffff00504009388 */
/* 0x001fe20000004800 */
/*02c0*/ @!P1 IMAD.IADD R9, R5, 0x1, R10 ; /* 0x0000000105099824 */
/* 0x002fca00078e020a */
/*02d0*/ @!P1 STS [R4.X4], R9 ; /* 0x0000000904009388 */
/* 0x000fe80000004800 */
/*02e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02f0*/ @!P2 WARPSYNC 0xffffffff ; /* 0xffffffff0000a948 */
/* 0x000fe20003800000 */
/*0300*/ @!P2 LDS R7, [R8.X4] ; /* 0x000000000807a984 */
/* 0x000e280000004800 */
/*0310*/ @!P2 LDS R10, [R8.X4+-0x8] ; /* 0xfffff800080aa984 */
/* 0x000e680000004800 */
/*0320*/ @!P2 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x000000000000ab1d */
/* 0x000fec0000010000 */
/*0330*/ @!P2 STS [R8.X4+-0x8], R7 ; /* 0xfffff8070800a388 */
/* 0x001fe20000004800 */
/*0340*/ @!P2 IMAD.IADD R11, R7, 0x1, R10 ; /* 0x00000001070ba824 */
/* 0x002fca00078e020a */
/*0350*/ @!P2 STS [R8.X4], R11 ; /* 0x0000000b0800a388 */
/* 0x000fe80000004800 */
/*0360*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0370*/ @!P3 WARPSYNC 0xffffffff ; /* 0xffffffff0000b948 */
/* 0x000fe20003800000 */
/*0380*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0390*/ @!P3 LDS.64 R12, [R6.X8+-0x8] ; /* 0xfffff800060cb984 */
/* 0x000e240000008a00 */
/*03a0*/ @!P3 IADD3 R15, R13, R12, RZ ; /* 0x0000000c0d0fb210 */
/* 0x001fe20007ffe0ff */
/*03b0*/ IMAD.MOV.U32 R14, RZ, RZ, R13 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e000d */
/*03c0*/ @!P3 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x000000000000bb1d */
/* 0x000fec0000010000 */
/*03d0*/ @!P3 STS.64 [R6.X8+-0x8], R14 ; /* 0xfffff80e0600b388 */
/* 0x000fe80000008a00 */
/*03e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03f0*/ LDS R5, [R0.X4] ; /* 0x0000000000057984 */
/* 0x000e280000004800 */
/*0400*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0410*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0420*/ BRA 0x420; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14exclusive_scanPi
.globl _Z14exclusive_scanPi
.p2align 8
.type _Z14exclusive_scanPi,@function
_Z14exclusive_scanPi:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 2, v0
v_add_nc_u32_e32 v4, 1, v0
s_mov_b32 s1, 1
s_waitcnt lgkmcnt(0)
global_load_b32 v5, v3, s[2:3]
v_add_co_u32 v1, s0, s2, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, null, s3, 0, s0
s_waitcnt vmcnt(0)
ds_store_b32 v3, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s0
s_cmp_lt_u32 s1, 4
s_mov_b32 s1, s2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_4
.LBB0_2:
s_lshl_b32 s2, s1, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v6, s2, v4
v_add_nc_u32_e32 v5, -1, v6
v_cmp_gt_u32_e64 s0, 9, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s1, v5
s_and_b32 s3, s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s3
s_cbranch_execz .LBB0_1
v_subrev_nc_u32_e32 v6, s1, v5
v_lshlrev_b32_e32 v5, 2, v5
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b32_e32 v6, 2, v6
ds_load_b32 v7, v5
ds_load_b32 v6, v6
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add_nc_u32_e32 v6, v6, v7
ds_store_b32 v5, v6
s_branch .LBB0_1
.LBB0_4:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v4, 0
ds_store_b32 v4, v4 offset:28
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v0, 1, v0
s_mov_b32 s1, 8
s_mov_b32 s0, 4
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_8
.p2align 6
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s0
s_lshr_b32 s0, s1, 1
s_cmp_gt_u32 s1, 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_10
.LBB0_8:
s_and_b32 s1, s1, 14
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u32_u24 v4, s1, v0, -1
v_mul_u32_u24_e32 v5, s1, v0
s_mov_b32 s1, s0
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_u32_e32 vcc_lo, s1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s0, 9, v5
s_and_b32 s2, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s2
s_cbranch_execz .LBB0_7
v_subrev_nc_u32_e32 v5, s1, v4
v_lshlrev_b32_e32 v4, 2, v4
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b32_e32 v5, 2, v5
ds_load_b32 v6, v4
ds_load_b32 v7, v5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add_nc_u32_e32 v7, v7, v6
ds_store_b32 v4, v7
ds_store_b32 v5, v6
s_branch .LBB0_7
.LBB0_10:
s_set_inst_prefetch_distance 0x2
ds_load_b32 v0, v3
s_waitcnt lgkmcnt(0)
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14exclusive_scanPi
.amdhsa_group_segment_fixed_size 32
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14exclusive_scanPi, .Lfunc_end0-_Z14exclusive_scanPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14inclusive_scanPi
.globl _Z14inclusive_scanPi
.p2align 8
.type _Z14inclusive_scanPi,@function
_Z14inclusive_scanPi:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 2, v0
v_cmp_gt_u32_e32 vcc_lo, 8, v0
s_mov_b32 s1, 1
s_waitcnt lgkmcnt(0)
global_load_b32 v4, v3, s[2:3]
v_add_co_u32 v1, s0, s2, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, null, s3, 0, s0
s_waitcnt vmcnt(0)
ds_store_b32 v3, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB1_2
.p2align 6
.LBB1_1:
s_or_b32 exec_lo, exec_lo, s0
s_lshl_b32 s0, s1, 1
s_cmp_gt_u32 s1, 3
s_mov_b32 s1, s0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_4
.LBB1_2:
v_cmp_le_u32_e64 s0, s1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s0
s_and_saveexec_b32 s0, s2
s_cbranch_execz .LBB1_1
v_subrev_nc_u32_e32 v4, s1, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v4, 2, v4
ds_load_b32 v5, v3
ds_load_b32 v4, v4
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v4, v4, v5
ds_store_b32 v3, v4
s_branch .LBB1_1
.LBB1_4:
ds_load_b32 v0, v3
s_waitcnt lgkmcnt(0)
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14inclusive_scanPi
.amdhsa_group_segment_fixed_size 32
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z14inclusive_scanPi, .Lfunc_end1-_Z14inclusive_scanPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 32
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14exclusive_scanPi
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z14exclusive_scanPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 32
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14inclusive_scanPi
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z14inclusive_scanPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000df553_00000000-6_scan_template.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z14exclusive_scanPiPi
.type _Z34__device_stub__Z14exclusive_scanPiPi, @function
_Z34__device_stub__Z14exclusive_scanPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14exclusive_scanPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z14exclusive_scanPiPi, .-_Z34__device_stub__Z14exclusive_scanPiPi
.globl _Z14exclusive_scanPi
.type _Z14exclusive_scanPi, @function
_Z14exclusive_scanPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z14exclusive_scanPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14exclusive_scanPi, .-_Z14exclusive_scanPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "out[%d] = %d\n"
.LC2:
.string "Time used: %f milliseconds\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $136, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $3, 48(%rsp)
movl $1, 52(%rsp)
movl $7, 56(%rsp)
movl $0, 60(%rsp)
movl $4, 64(%rsp)
movl $1, 68(%rsp)
movl $6, 72(%rsp)
movl $3, 76(%rsp)
movq %rsp, %rdi
call cudaEventCreate@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $32, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq (%rsp), %rdi
call cudaEventRecord@PLT
movl $8, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
leaq 80(%rsp), %rdi
movl $2, %ecx
movl $32, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 36(%rsp)
leaq 36(%rsp), %rdi
movq 8(%rsp), %rdx
movq (%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movl $0, %ebx
leaq .LC1(%rip), %rbp
.L13:
movl 80(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $8, %rbx
jne .L13
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $-1, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 16(%rsp), %rdi
call _Z34__device_stub__Z14exclusive_scanPiPi
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z34__device_stub__Z14inclusive_scanPiPi
.type _Z34__device_stub__Z14inclusive_scanPiPi, @function
_Z34__device_stub__Z14inclusive_scanPiPi:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14inclusive_scanPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z34__device_stub__Z14inclusive_scanPiPi, .-_Z34__device_stub__Z14inclusive_scanPiPi
.globl _Z14inclusive_scanPi
.type _Z14inclusive_scanPi, @function
_Z14inclusive_scanPi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z14inclusive_scanPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z14inclusive_scanPi, .-_Z14inclusive_scanPi
.section .rodata.str1.1
.LC3:
.string "_Z14inclusive_scanPi"
.LC4:
.string "_Z14exclusive_scanPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z14inclusive_scanPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z14exclusive_scanPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "scan_template.hip"
.globl _Z29__device_stub__exclusive_scanPi # -- Begin function _Z29__device_stub__exclusive_scanPi
.p2align 4, 0x90
.type _Z29__device_stub__exclusive_scanPi,@function
_Z29__device_stub__exclusive_scanPi: # @_Z29__device_stub__exclusive_scanPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z14exclusive_scanPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z29__device_stub__exclusive_scanPi, .Lfunc_end0-_Z29__device_stub__exclusive_scanPi
.cfi_endproc
# -- End function
.globl _Z29__device_stub__inclusive_scanPi # -- Begin function _Z29__device_stub__inclusive_scanPi
.p2align 4, 0x90
.type _Z29__device_stub__inclusive_scanPi,@function
_Z29__device_stub__inclusive_scanPi: # @_Z29__device_stub__inclusive_scanPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z14inclusive_scanPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z29__device_stub__inclusive_scanPi, .Lfunc_end1-_Z29__device_stub__inclusive_scanPi
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI2_0:
.long 3 # 0x3
.long 1 # 0x1
.long 7 # 0x7
.long 0 # 0x0
.LCPI2_1:
.long 4 # 0x4
.long 1 # 0x1
.long 6 # 0x6
.long 3 # 0x3
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $144, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -16
movaps .LCPI2_0(%rip), %xmm0 # xmm0 = [3,1,7,0]
movaps %xmm0, 112(%rsp)
movaps .LCPI2_1(%rip), %xmm0 # xmm0 = [4,1,6,3]
movaps %xmm0, 128(%rsp)
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
movl $32, %esi
callq hipMalloc
movq 8(%rsp), %rdi
leaq 112(%rsp), %rsi
movl $32, %edx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 7(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 48(%rsp)
leaq 80(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14exclusive_scanPi, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rsi
leaq 80(%rsp), %rdi
movl $32, %edx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipEventSynchronize
movl $0, 24(%rsp)
movq 40(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 24(%rsp), %rdi
callq hipEventElapsedTime
movq 8(%rsp), %rdi
callq hipFree
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx,4), %edx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $8, %rbx
jne .LBB2_3
# %bb.4:
movss 24(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movl $-1, %eax
addq $144, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14exclusive_scanPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14inclusive_scanPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14exclusive_scanPi,@object # @_Z14exclusive_scanPi
.section .rodata,"a",@progbits
.globl _Z14exclusive_scanPi
.p2align 3, 0x0
_Z14exclusive_scanPi:
.quad _Z29__device_stub__exclusive_scanPi
.size _Z14exclusive_scanPi, 8
.type _Z14inclusive_scanPi,@object # @_Z14inclusive_scanPi
.globl _Z14inclusive_scanPi
.p2align 3, 0x0
_Z14inclusive_scanPi:
.quad _Z29__device_stub__inclusive_scanPi
.size _Z14inclusive_scanPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "out[%d] = %d\n"
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Time used: %f milliseconds\n"
.size .L.str.1, 28
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14exclusive_scanPi"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z14inclusive_scanPi"
.size .L__unnamed_2, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__exclusive_scanPi
.addrsig_sym _Z29__device_stub__inclusive_scanPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14exclusive_scanPi
.addrsig_sym _Z14inclusive_scanPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdlib.h>
#include<stdio.h>
#include<time.h>
__global__ void scan_shared(float *d_in,float *d_out,const int size){
extern __shared__ float s_in[];
int idx = threadIdx.x;
s_in[idx] = d_in[idx];
__syncthreads();
float out;
for(int step=1;step<size;step*=2){
if(idx-step>=0){
out = s_in[idx]+s_in[idx-step];
}
__syncthreads();
if(idx-step>=0){
s_in[idx] = out;
}
__syncthreads();
}
d_out[idx] = s_in[idx];
}
void init(float *p,const int size){
for(int i=0;i<size;i++)
p[i] = i;
}
int main(){
int size = 1024;
float *h_in,*h_out;
float *d_in,*d_out;
h_in = (float *)malloc(size*sizeof(float));
h_out = (float *)malloc(size*sizeof(float));
init(h_in,size);
printf("array:");
for(int i=0;i<size;i++)
printf("%f ",h_in[i]);
printf("\n");
cudaMalloc((float **)&d_in,size*sizeof(float));
cudaMalloc((float **)&d_out,size*sizeof(float));
cudaMemcpy(d_in,h_in,size*sizeof(float),cudaMemcpyHostToDevice);
time_t t_start = clock();
scan_shared<<<1,size,size*sizeof(float)>>>(d_in,d_out,size);
time_t t_end = clock();
cudaMemcpy(h_out,d_out,size*sizeof(float),cudaMemcpyDeviceToHost);
printf("time:%fms\n",difftime(t_end,t_start));
printf("result:");
for(int i=0;i<size;i++)
printf("%f ",h_out[i]);
printf("\n");
free(h_in);
free(h_out);
cudaFree(d_in);
cudaFree(d_out);
return 0;
} | code for sm_80
Function : _Z11scan_sharedPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE R2, R7, R2, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x001fcc00078e0202 */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff007624 */
/* 0x000fca00078e00ff */
/*0070*/ ISETP.GE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f06270 */
/*0080*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x0041e80000004800 */
/*0090*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00a0*/ @!P0 BRA 0x170 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R0, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff007435 */
/* 0x001fd400000001ff */
/*00c0*/ ISETP.GE.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06270 */
/*00d0*/ @P0 IMAD.IADD R2, R7, 0x1, -R0 ; /* 0x0000000107020824 */
/* 0x000fe200078e0a00 */
/*00e0*/ @P0 LDS R3, [R7.X4] ; /* 0x0000000007030984 */
/* 0x000fe20000004800 */
/*00f0*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fc800000006ff */
/*0100*/ @P0 LDS R2, [R2.X4] ; /* 0x0000000002020984 */
/* 0x000e240000004800 */
/*0110*/ @P0 FADD R4, R2, R3 ; /* 0x0000000302040221 */
/* 0x001fe40000000000 */
/*0120*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0130*/ @P0 STS [R7.X4], R4 ; /* 0x0000000407000388 */
/* 0x0001e80000004800 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0150*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0160*/ @!P0 BRA 0xc0 ; /* 0xffffff5000008947 */
/* 0x001fea000383ffff */
/*0170*/ LDS R5, [R7.X4] ; /* 0x0000000007057984 */
/* 0x001e220000004800 */
/*0180*/ SHF.R.S32.HI R0, RZ, 0x1f, R7 ; /* 0x0000001fff007819 */
/* 0x000fe40000011407 */
/*0190*/ LEA R2, P0, R7, c[0x0][0x168], 0x2 ; /* 0x00005a0007027a11 */
/* 0x000fc800078010ff */
/*01a0*/ LEA.HI.X R3, R7, c[0x0][0x16c], R0, 0x2, P0 ; /* 0x00005b0007037a11 */
/* 0x000fca00000f1400 */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdlib.h>
#include<stdio.h>
#include<time.h>
__global__ void scan_shared(float *d_in,float *d_out,const int size){
extern __shared__ float s_in[];
int idx = threadIdx.x;
s_in[idx] = d_in[idx];
__syncthreads();
float out;
for(int step=1;step<size;step*=2){
if(idx-step>=0){
out = s_in[idx]+s_in[idx-step];
}
__syncthreads();
if(idx-step>=0){
s_in[idx] = out;
}
__syncthreads();
}
d_out[idx] = s_in[idx];
}
void init(float *p,const int size){
for(int i=0;i<size;i++)
p[i] = i;
}
int main(){
int size = 1024;
float *h_in,*h_out;
float *d_in,*d_out;
h_in = (float *)malloc(size*sizeof(float));
h_out = (float *)malloc(size*sizeof(float));
init(h_in,size);
printf("array:");
for(int i=0;i<size;i++)
printf("%f ",h_in[i]);
printf("\n");
cudaMalloc((float **)&d_in,size*sizeof(float));
cudaMalloc((float **)&d_out,size*sizeof(float));
cudaMemcpy(d_in,h_in,size*sizeof(float),cudaMemcpyHostToDevice);
time_t t_start = clock();
scan_shared<<<1,size,size*sizeof(float)>>>(d_in,d_out,size);
time_t t_end = clock();
cudaMemcpy(h_out,d_out,size*sizeof(float),cudaMemcpyDeviceToHost);
printf("time:%fms\n",difftime(t_end,t_start));
printf("result:");
for(int i=0;i<size;i++)
printf("%f ",h_out[i]);
printf("\n");
free(h_in);
free(h_out);
cudaFree(d_in);
cudaFree(d_out);
return 0;
} | .file "tmpxft_00024b6c_00000000-6_scan_shared.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4initPfi
.type _Z4initPfi, @function
_Z4initPfi:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L3
movslq %esi, %rsi
movl $0, %eax
.L5:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rdi,%rax,4)
addq $1, %rax
cmpq %rsi, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z4initPfi, .-_Z4initPfi
.globl _Z34__device_stub__Z11scan_sharedPfS_iPfS_i
.type _Z34__device_stub__Z11scan_sharedPfS_iPfS_i, @function
_Z34__device_stub__Z11scan_sharedPfS_iPfS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11scan_sharedPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z34__device_stub__Z11scan_sharedPfS_iPfS_i, .-_Z34__device_stub__Z11scan_sharedPfS_iPfS_i
.globl _Z11scan_sharedPfS_i
.type _Z11scan_sharedPfS_i, @function
_Z11scan_sharedPfS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11scan_sharedPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z11scan_sharedPfS_i, .-_Z11scan_sharedPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "array:"
.LC1:
.string "%f "
.LC2:
.string "\n"
.LC3:
.string "time:%fms\n"
.LC4:
.string "result:"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $4096, %edi
call malloc@PLT
movq %rax, %rbp
movl $4096, %edi
call malloc@PLT
movq %rax, %r12
movl $1024, %esi
movq %rbp, %rdi
call _Z4initPfi
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rbx
leaq 4096(%rbp), %r14
leaq .LC1(%rip), %r13
.L16:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r14, %rbx
jne .L16
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4096, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
call clock@PLT
movq %rax, %r13
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $4096, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L17:
call clock@PLT
movq %rax, %rbx
movl $2, %ecx
movl $4096, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq %r13, %rsi
movq %rbx, %rdi
call difftime@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rbx
leaq 4096(%r12), %r14
leaq .LC1(%rip), %r13
.L18:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r14, %rbx
jne .L18
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl $1024, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z34__device_stub__Z11scan_sharedPfS_iPfS_i
jmp .L17
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z11scan_sharedPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z11scan_sharedPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdlib.h>
#include<stdio.h>
#include<time.h>
__global__ void scan_shared(float *d_in,float *d_out,const int size){
extern __shared__ float s_in[];
int idx = threadIdx.x;
s_in[idx] = d_in[idx];
__syncthreads();
float out;
for(int step=1;step<size;step*=2){
if(idx-step>=0){
out = s_in[idx]+s_in[idx-step];
}
__syncthreads();
if(idx-step>=0){
s_in[idx] = out;
}
__syncthreads();
}
d_out[idx] = s_in[idx];
}
void init(float *p,const int size){
for(int i=0;i<size;i++)
p[i] = i;
}
int main(){
int size = 1024;
float *h_in,*h_out;
float *d_in,*d_out;
h_in = (float *)malloc(size*sizeof(float));
h_out = (float *)malloc(size*sizeof(float));
init(h_in,size);
printf("array:");
for(int i=0;i<size;i++)
printf("%f ",h_in[i]);
printf("\n");
cudaMalloc((float **)&d_in,size*sizeof(float));
cudaMalloc((float **)&d_out,size*sizeof(float));
cudaMemcpy(d_in,h_in,size*sizeof(float),cudaMemcpyHostToDevice);
time_t t_start = clock();
scan_shared<<<1,size,size*sizeof(float)>>>(d_in,d_out,size);
time_t t_end = clock();
cudaMemcpy(h_out,d_out,size*sizeof(float),cudaMemcpyDeviceToHost);
printf("time:%fms\n",difftime(t_end,t_start));
printf("result:");
for(int i=0;i<size;i++)
printf("%f ",h_out[i]);
printf("\n");
free(h_in);
free(h_out);
cudaFree(d_in);
cudaFree(d_out);
return 0;
} | #include <hip/hip_runtime.h>
#include<stdlib.h>
#include<stdio.h>
#include<time.h>
__global__ void scan_shared(float *d_in,float *d_out,const int size){
extern __shared__ float s_in[];
int idx = threadIdx.x;
s_in[idx] = d_in[idx];
__syncthreads();
float out;
for(int step=1;step<size;step*=2){
if(idx-step>=0){
out = s_in[idx]+s_in[idx-step];
}
__syncthreads();
if(idx-step>=0){
s_in[idx] = out;
}
__syncthreads();
}
d_out[idx] = s_in[idx];
}
void init(float *p,const int size){
for(int i=0;i<size;i++)
p[i] = i;
}
int main(){
int size = 1024;
float *h_in,*h_out;
float *d_in,*d_out;
h_in = (float *)malloc(size*sizeof(float));
h_out = (float *)malloc(size*sizeof(float));
init(h_in,size);
printf("array:");
for(int i=0;i<size;i++)
printf("%f ",h_in[i]);
printf("\n");
hipMalloc((float **)&d_in,size*sizeof(float));
hipMalloc((float **)&d_out,size*sizeof(float));
hipMemcpy(d_in,h_in,size*sizeof(float),hipMemcpyHostToDevice);
time_t t_start = clock();
scan_shared<<<1,size,size*sizeof(float)>>>(d_in,d_out,size);
time_t t_end = clock();
hipMemcpy(h_out,d_out,size*sizeof(float),hipMemcpyDeviceToHost);
printf("time:%fms\n",difftime(t_end,t_start));
printf("result:");
for(int i=0;i<size;i++)
printf("%f ",h_out[i]);
printf("\n");
free(h_in);
free(h_out);
hipFree(d_in);
hipFree(d_out);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdlib.h>
#include<stdio.h>
#include<time.h>
__global__ void scan_shared(float *d_in,float *d_out,const int size){
extern __shared__ float s_in[];
int idx = threadIdx.x;
s_in[idx] = d_in[idx];
__syncthreads();
float out;
for(int step=1;step<size;step*=2){
if(idx-step>=0){
out = s_in[idx]+s_in[idx-step];
}
__syncthreads();
if(idx-step>=0){
s_in[idx] = out;
}
__syncthreads();
}
d_out[idx] = s_in[idx];
}
void init(float *p,const int size){
for(int i=0;i<size;i++)
p[i] = i;
}
int main(){
int size = 1024;
float *h_in,*h_out;
float *d_in,*d_out;
h_in = (float *)malloc(size*sizeof(float));
h_out = (float *)malloc(size*sizeof(float));
init(h_in,size);
printf("array:");
for(int i=0;i<size;i++)
printf("%f ",h_in[i]);
printf("\n");
hipMalloc((float **)&d_in,size*sizeof(float));
hipMalloc((float **)&d_out,size*sizeof(float));
hipMemcpy(d_in,h_in,size*sizeof(float),hipMemcpyHostToDevice);
time_t t_start = clock();
scan_shared<<<1,size,size*sizeof(float)>>>(d_in,d_out,size);
time_t t_end = clock();
hipMemcpy(h_out,d_out,size*sizeof(float),hipMemcpyDeviceToHost);
printf("time:%fms\n",difftime(t_end,t_start));
printf("result:");
for(int i=0;i<size;i++)
printf("%f ",h_out[i]);
printf("\n");
free(h_in);
free(h_out);
hipFree(d_in);
hipFree(d_out);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11scan_sharedPfS_i
.globl _Z11scan_sharedPfS_i
.p2align 8
.type _Z11scan_sharedPfS_i,@function
_Z11scan_sharedPfS_i:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s2, s[0:1], 0x10
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v1, s[4:5]
v_add_nc_u32_e32 v1, 0, v1
s_cmp_lt_i32 s2, 2
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
s_mov_b32 s3, 1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_lshl_b32 s3, s3, 1
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s3, s2
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
.LBB0_3:
v_subrev_nc_u32_e32 v3, s3, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v3
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_5
v_lshl_add_u32 v2, v3, 2, 0
ds_load_b32 v3, v1
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_2
ds_store_b32 v1, v2
s_branch .LBB0_2
.LBB0_7:
s_load_b64 s[0:1], s[0:1], 0x8
ds_load_b32 v1, v1
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11scan_sharedPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11scan_sharedPfS_i, .Lfunc_end0-_Z11scan_sharedPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11scan_sharedPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z11scan_sharedPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdlib.h>
#include<stdio.h>
#include<time.h>
__global__ void scan_shared(float *d_in,float *d_out,const int size){
extern __shared__ float s_in[];
int idx = threadIdx.x;
s_in[idx] = d_in[idx];
__syncthreads();
float out;
for(int step=1;step<size;step*=2){
if(idx-step>=0){
out = s_in[idx]+s_in[idx-step];
}
__syncthreads();
if(idx-step>=0){
s_in[idx] = out;
}
__syncthreads();
}
d_out[idx] = s_in[idx];
}
void init(float *p,const int size){
for(int i=0;i<size;i++)
p[i] = i;
}
int main(){
int size = 1024;
float *h_in,*h_out;
float *d_in,*d_out;
h_in = (float *)malloc(size*sizeof(float));
h_out = (float *)malloc(size*sizeof(float));
init(h_in,size);
printf("array:");
for(int i=0;i<size;i++)
printf("%f ",h_in[i]);
printf("\n");
hipMalloc((float **)&d_in,size*sizeof(float));
hipMalloc((float **)&d_out,size*sizeof(float));
hipMemcpy(d_in,h_in,size*sizeof(float),hipMemcpyHostToDevice);
time_t t_start = clock();
scan_shared<<<1,size,size*sizeof(float)>>>(d_in,d_out,size);
time_t t_end = clock();
hipMemcpy(h_out,d_out,size*sizeof(float),hipMemcpyDeviceToHost);
printf("time:%fms\n",difftime(t_end,t_start));
printf("result:");
for(int i=0;i<size;i++)
printf("%f ",h_out[i]);
printf("\n");
free(h_in);
free(h_out);
hipFree(d_in);
hipFree(d_out);
return 0;
} | .text
.file "scan_shared.hip"
.globl _Z26__device_stub__scan_sharedPfS_i # -- Begin function _Z26__device_stub__scan_sharedPfS_i
.p2align 4, 0x90
.type _Z26__device_stub__scan_sharedPfS_i,@function
_Z26__device_stub__scan_sharedPfS_i: # @_Z26__device_stub__scan_sharedPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11scan_sharedPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__scan_sharedPfS_i, .Lfunc_end0-_Z26__device_stub__scan_sharedPfS_i
.cfi_endproc
# -- End function
.globl _Z4initPfi # -- Begin function _Z4initPfi
.p2align 4, 0x90
.type _Z4initPfi,@function
_Z4initPfi: # @_Z4initPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z4initPfi, .Lfunc_end1-_Z4initPfi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB2_1
# %bb.2: # %_Z4initPfi.exit
xorl %r15d, %r15d
movl $.L.str, %edi
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r15
cmpq $1024, %r15 # imm = 0x400
jne .LBB2_3
# %bb.4:
movl $10, %edi
callq putchar@PLT
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq 16(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
callq clock
movq %rax, %r15
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $4096, %r8d # imm = 0x1000
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $1024, 28(%rsp) # imm = 0x400
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11scan_sharedPfS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
callq clock
movq %rax, %r12
movq 8(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq %r12, %rdi
movq %r15, %rsi
callq difftime
movl $.L.str.3, %edi
movb $1, %al
callq printf
xorl %r15d, %r15d
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r15
cmpq $1024, %r15 # imm = 0x400
jne .LBB2_7
# %bb.8:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11scan_sharedPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11scan_sharedPfS_i,@object # @_Z11scan_sharedPfS_i
.section .rodata,"a",@progbits
.globl _Z11scan_sharedPfS_i
.p2align 3, 0x0
_Z11scan_sharedPfS_i:
.quad _Z26__device_stub__scan_sharedPfS_i
.size _Z11scan_sharedPfS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "array:"
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%f "
.size .L.str.1, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "time:%fms\n"
.size .L.str.3, 11
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "result:"
.size .L.str.4, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11scan_sharedPfS_i"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__scan_sharedPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11scan_sharedPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11scan_sharedPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE R2, R7, R2, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x001fcc00078e0202 */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff007624 */
/* 0x000fca00078e00ff */
/*0070*/ ISETP.GE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe20003f06270 */
/*0080*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x0041e80000004800 */
/*0090*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00a0*/ @!P0 BRA 0x170 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R0, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff007435 */
/* 0x001fd400000001ff */
/*00c0*/ ISETP.GE.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f06270 */
/*00d0*/ @P0 IMAD.IADD R2, R7, 0x1, -R0 ; /* 0x0000000107020824 */
/* 0x000fe200078e0a00 */
/*00e0*/ @P0 LDS R3, [R7.X4] ; /* 0x0000000007030984 */
/* 0x000fe20000004800 */
/*00f0*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fc800000006ff */
/*0100*/ @P0 LDS R2, [R2.X4] ; /* 0x0000000002020984 */
/* 0x000e240000004800 */
/*0110*/ @P0 FADD R4, R2, R3 ; /* 0x0000000302040221 */
/* 0x001fe40000000000 */
/*0120*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0130*/ @P0 STS [R7.X4], R4 ; /* 0x0000000407000388 */
/* 0x0001e80000004800 */
/*0140*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0150*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0160*/ @!P0 BRA 0xc0 ; /* 0xffffff5000008947 */
/* 0x001fea000383ffff */
/*0170*/ LDS R5, [R7.X4] ; /* 0x0000000007057984 */
/* 0x001e220000004800 */
/*0180*/ SHF.R.S32.HI R0, RZ, 0x1f, R7 ; /* 0x0000001fff007819 */
/* 0x000fe40000011407 */
/*0190*/ LEA R2, P0, R7, c[0x0][0x168], 0x2 ; /* 0x00005a0007027a11 */
/* 0x000fc800078010ff */
/*01a0*/ LEA.HI.X R3, R7, c[0x0][0x16c], R0, 0x2, P0 ; /* 0x00005b0007037a11 */
/* 0x000fca00000f1400 */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11scan_sharedPfS_i
.globl _Z11scan_sharedPfS_i
.p2align 8
.type _Z11scan_sharedPfS_i,@function
_Z11scan_sharedPfS_i:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s2, s[0:1], 0x10
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v1, s[4:5]
v_add_nc_u32_e32 v1, 0, v1
s_cmp_lt_i32 s2, 2
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
s_mov_b32 s3, 1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_lshl_b32 s3, s3, 1
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s3, s2
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
.LBB0_3:
v_subrev_nc_u32_e32 v3, s3, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v3
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_5
v_lshl_add_u32 v2, v3, 2, 0
ds_load_b32 v3, v1
ds_load_b32 v2, v2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v3, v2
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_2
ds_store_b32 v1, v2
s_branch .LBB0_2
.LBB0_7:
s_load_b64 s[0:1], s[0:1], 0x8
ds_load_b32 v1, v1
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11scan_sharedPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11scan_sharedPfS_i, .Lfunc_end0-_Z11scan_sharedPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11scan_sharedPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z11scan_sharedPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00024b6c_00000000-6_scan_shared.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4initPfi
.type _Z4initPfi, @function
_Z4initPfi:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L3
movslq %esi, %rsi
movl $0, %eax
.L5:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rdi,%rax,4)
addq $1, %rax
cmpq %rsi, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z4initPfi, .-_Z4initPfi
.globl _Z34__device_stub__Z11scan_sharedPfS_iPfS_i
.type _Z34__device_stub__Z11scan_sharedPfS_iPfS_i, @function
_Z34__device_stub__Z11scan_sharedPfS_iPfS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11scan_sharedPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z34__device_stub__Z11scan_sharedPfS_iPfS_i, .-_Z34__device_stub__Z11scan_sharedPfS_iPfS_i
.globl _Z11scan_sharedPfS_i
.type _Z11scan_sharedPfS_i, @function
_Z11scan_sharedPfS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11scan_sharedPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z11scan_sharedPfS_i, .-_Z11scan_sharedPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "array:"
.LC1:
.string "%f "
.LC2:
.string "\n"
.LC3:
.string "time:%fms\n"
.LC4:
.string "result:"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $4096, %edi
call malloc@PLT
movq %rax, %rbp
movl $4096, %edi
call malloc@PLT
movq %rax, %r12
movl $1024, %esi
movq %rbp, %rdi
call _Z4initPfi
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rbx
leaq 4096(%rbp), %r14
leaq .LC1(%rip), %r13
.L16:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r14, %rbx
jne .L16
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4096, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
call clock@PLT
movq %rax, %r13
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $4096, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L17:
call clock@PLT
movq %rax, %rbx
movl $2, %ecx
movl $4096, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq %r13, %rsi
movq %rbx, %rdi
call difftime@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rbx
leaq 4096(%r12), %r14
leaq .LC1(%rip), %r13
.L18:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r14, %rbx
jne .L18
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl $1024, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z34__device_stub__Z11scan_sharedPfS_iPfS_i
jmp .L17
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z11scan_sharedPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z11scan_sharedPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "scan_shared.hip"
.globl _Z26__device_stub__scan_sharedPfS_i # -- Begin function _Z26__device_stub__scan_sharedPfS_i
.p2align 4, 0x90
.type _Z26__device_stub__scan_sharedPfS_i,@function
_Z26__device_stub__scan_sharedPfS_i: # @_Z26__device_stub__scan_sharedPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11scan_sharedPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__scan_sharedPfS_i, .Lfunc_end0-_Z26__device_stub__scan_sharedPfS_i
.cfi_endproc
# -- End function
.globl _Z4initPfi # -- Begin function _Z4initPfi
.p2align 4, 0x90
.type _Z4initPfi,@function
_Z4initPfi: # @_Z4initPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z4initPfi, .Lfunc_end1-_Z4initPfi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB2_1
# %bb.2: # %_Z4initPfi.exit
xorl %r15d, %r15d
movl $.L.str, %edi
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r15
cmpq $1024, %r15 # imm = 0x400
jne .LBB2_3
# %bb.4:
movl $10, %edi
callq putchar@PLT
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq 16(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
callq clock
movq %rax, %r15
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $4096, %r8d # imm = 0x1000
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $1024, 28(%rsp) # imm = 0x400
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11scan_sharedPfS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
callq clock
movq %rax, %r12
movq 8(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq %r12, %rdi
movq %r15, %rsi
callq difftime
movl $.L.str.3, %edi
movb $1, %al
callq printf
xorl %r15d, %r15d
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r15
cmpq $1024, %r15 # imm = 0x400
jne .LBB2_7
# %bb.8:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11scan_sharedPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11scan_sharedPfS_i,@object # @_Z11scan_sharedPfS_i
.section .rodata,"a",@progbits
.globl _Z11scan_sharedPfS_i
.p2align 3, 0x0
_Z11scan_sharedPfS_i:
.quad _Z26__device_stub__scan_sharedPfS_i
.size _Z11scan_sharedPfS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "array:"
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%f "
.size .L.str.1, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "time:%fms\n"
.size .L.str.3, 11
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "result:"
.size .L.str.4, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11scan_sharedPfS_i"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__scan_sharedPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11scan_sharedPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
/**
* Computes the log of reaction rate.
* @param a: Pointer to coefficient matrix.
* @param temp: Pointer to temperature array.
* @param lam: Matrix to write the results to.
* @param nsets: Number of sets / number of rows in coefficient matrix.
* @param ncells: Number of cells / length of temperature array.
* @param ncoeff: Number of coefficients / number of columns in coefficient matrix.
*/
template <class dtype>
__device__ void rates(dtype *a, dtype *temp, dtype *lam, int nsets, int ncells, int ncoeff)
{
int istart = blockIdx.x * blockDim.x + threadIdx.x;
int istep = blockDim.x * gridDim.x;
int jstart = blockIdx.y * blockDim.y + threadIdx.y;
int jstep = blockDim.y * gridDim.y;
int kstart = blockIdx.z * blockDim.z + threadIdx.z;
int kstep = blockDim.z * gridDim.z;
for(int i = istart; i < nsets; i += istep)
{
for(int j = jstart; j < ncells; j += jstep)
{
dtype temp9 = temp[j] * 1.0e-9;
for(int k = kstart; k < ncoeff; k += kstep)
{
switch(k)
{
case 0:
atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k]);
break;
case 6:
atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k] * log(temp9));
break;
default:
atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k] * pow(temp9, (2 * k - 5) / 3.0));
break;
}
}
}
}
}
template <>
__device__ void rates<float>(float *a, float *temp, float *lam, int nsets, int ncells, int ncoeff)
{
int istart = blockIdx.x * blockDim.x + threadIdx.x;
int istep = blockDim.x * gridDim.x;
int jstart = blockIdx.y * blockDim.y + threadIdx.y;
int jstep = blockDim.y * gridDim.y;
int kstart = blockIdx.z * blockDim.z + threadIdx.z;
int kstep = blockDim.z * gridDim.z;
for(int i = istart; i < nsets; i += istep)
{
for(int j = jstart; j < ncells; j += jstep)
{
float temp9 = temp[j] * 1.0e-9;
for(int k = kstart; k < ncoeff; k += kstep)
{
switch(k)
{
case 0:
atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k]);
break;
case 6:
atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k] * logf(temp9));
break;
default:
atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k] * powf(temp9, (2 * k - 5) / 3.0f));
break;
}
}
}
}
}
template <class dtype, int nsets, int ncells, int ncoeff>
__global__ void exec(dtype* lam)
{
// Tensors
__shared__ dtype a[nsets * ncoeff];
__shared__ dtype temp[ncells];
int xInd = blockIdx.x * blockDim.x + threadIdx.x;
int yInd = blockIdx.y * blockDim.y + threadIdx.y;
int ySize = blockDim.y * gridDim.y;
int zInd = blockIdx.z * blockDim.z + threadIdx.z;
int zSize = blockDim.z * gridDim.z;
int ind = xInd * ySize * zSize + yInd * zSize + zInd;
/********************************
* Initialize coefficient matrix *
********************************/
if(ind < nsets * ncoeff)
{
if(ind % ncoeff != 7)
{
a[ind] = ind - (ind / ncoeff - 1);
}
else
{
a[ind] = 0.0;
}
}
/******************************************
* Initialize the temperature in each cell *
******************************************/
if(ind < ncells)
{
temp[ind] = (ind + 1) * 1e9;
}
/****************************
* Zero the array of results *
****************************/
if(ind < nsets * ncells)
{
lam[ind] = 0.0;
}
/*******************************************
* Compute ln(lambda) for each set and cell *
*******************************************/
rates<dtype>(a, temp, lam, nsets, ncells, ncoeff);
}
int main()
{
// Tensor dimensions
const int nsets = 4, ncells = 4, ncoeff = 8;
// Results and elapsed time
float *lam;
cudaMallocManaged(&lam, nsets * ncells * sizeof(float));
// Compute the rates
dim3 threadsPerBlock(nsets, ncells, ncoeff);
dim3 numBlocks(1, 1, 1);
exec<float, nsets, ncells, ncoeff><<<numBlocks, threadsPerBlock>>>(lam);
// Print ln(lambda)
cudaDeviceSynchronize();
printf("lambda:\n");
for(int i = 0; i < nsets; i++)
{
for(int j = 0; j < ncells; j++)
{
printf("%.3f\t", lam[i * ncells + j]);
}
printf("\n");
}
return 0;
} | .file "tmpxft_00110d06_00000000-6_react_shared.cudafe1.cpp"
.text
#APP
#NO_APP
.section .text._Z4execIfLi4ELi4ELi8EEvPT_,"axG",@progbits,_Z4execIfLi4ELi4ELi8EEvPT_,comdat
.weak _Z4execIfLi4ELi4ELi8EEvPT_
.type _Z4execIfLi4ELi4ELi8EEvPT_, @function
_Z4execIfLi4ELi4ELi8EEvPT_:
.LFB2136:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4execIfLi4ELi4ELi8EEvPT_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2136:
.size _Z4execIfLi4ELi4ELi8EEvPT_, .-_Z4execIfLi4ELi4ELi8EEvPT_
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5ratesIfEvPT_S1_S1_iii
.type _Z5ratesIfEvPT_S1_S1_iii, @function
_Z5ratesIfEvPT_S1_S1_iii:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z5ratesIfEvPT_S1_S1_iii, .-_Z5ratesIfEvPT_S1_S1_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "lambda:\n"
.LC1:
.string "%.3f\t"
.LC2:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $64, %esi
call cudaMallocManaged@PLT
movl $4, 16(%rsp)
movl $4, 20(%rsp)
movl $8, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $8, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L12:
call cudaDeviceSynchronize@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16, %ebp
leaq .LC1(%rip), %r12
leaq .LC2(%rip), %r13
.L13:
leaq -16(%rbp), %rbx
.L14:
movq 8(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L14
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rbp
cmpq $80, %rbp
jne .L13
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z4execIfLi4ELi4ELi8EEvPT_
jmp .L12
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z4execIfLi4ELi4ELi8EEvPT_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z4execIfLi4ELi4ELi8EEvPT_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
/**
* Computes the log of reaction rate.
* @param a: Pointer to coefficient matrix.
* @param temp: Pointer to temperature array.
* @param lam: Matrix to write the results to.
* @param nsets: Number of sets / number of rows in coefficient matrix.
* @param ncells: Number of cells / length of temperature array.
* @param ncoeff: Number of coefficients / number of columns in coefficient matrix.
*/
template <class dtype>
__device__ void rates(dtype *a, dtype *temp, dtype *lam, int nsets, int ncells, int ncoeff)
{
int istart = blockIdx.x * blockDim.x + threadIdx.x;
int istep = blockDim.x * gridDim.x;
int jstart = blockIdx.y * blockDim.y + threadIdx.y;
int jstep = blockDim.y * gridDim.y;
int kstart = blockIdx.z * blockDim.z + threadIdx.z;
int kstep = blockDim.z * gridDim.z;
for(int i = istart; i < nsets; i += istep)
{
for(int j = jstart; j < ncells; j += jstep)
{
dtype temp9 = temp[j] * 1.0e-9;
for(int k = kstart; k < ncoeff; k += kstep)
{
switch(k)
{
case 0:
atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k]);
break;
case 6:
atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k] * log(temp9));
break;
default:
atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k] * pow(temp9, (2 * k - 5) / 3.0));
break;
}
}
}
}
}
template <>
__device__ void rates<float>(float *a, float *temp, float *lam, int nsets, int ncells, int ncoeff)
{
int istart = blockIdx.x * blockDim.x + threadIdx.x;
int istep = blockDim.x * gridDim.x;
int jstart = blockIdx.y * blockDim.y + threadIdx.y;
int jstep = blockDim.y * gridDim.y;
int kstart = blockIdx.z * blockDim.z + threadIdx.z;
int kstep = blockDim.z * gridDim.z;
for(int i = istart; i < nsets; i += istep)
{
for(int j = jstart; j < ncells; j += jstep)
{
float temp9 = temp[j] * 1.0e-9;
for(int k = kstart; k < ncoeff; k += kstep)
{
switch(k)
{
case 0:
atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k]);
break;
case 6:
atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k] * logf(temp9));
break;
default:
atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k] * powf(temp9, (2 * k - 5) / 3.0f));
break;
}
}
}
}
}
template <class dtype, int nsets, int ncells, int ncoeff>
__global__ void exec(dtype* lam)
{
// Tensors
__shared__ dtype a[nsets * ncoeff];
__shared__ dtype temp[ncells];
int xInd = blockIdx.x * blockDim.x + threadIdx.x;
int yInd = blockIdx.y * blockDim.y + threadIdx.y;
int ySize = blockDim.y * gridDim.y;
int zInd = blockIdx.z * blockDim.z + threadIdx.z;
int zSize = blockDim.z * gridDim.z;
int ind = xInd * ySize * zSize + yInd * zSize + zInd;
/********************************
* Initialize coefficient matrix *
********************************/
if(ind < nsets * ncoeff)
{
if(ind % ncoeff != 7)
{
a[ind] = ind - (ind / ncoeff - 1);
}
else
{
a[ind] = 0.0;
}
}
/******************************************
* Initialize the temperature in each cell *
******************************************/
if(ind < ncells)
{
temp[ind] = (ind + 1) * 1e9;
}
/****************************
* Zero the array of results *
****************************/
if(ind < nsets * ncells)
{
lam[ind] = 0.0;
}
/*******************************************
* Compute ln(lambda) for each set and cell *
*******************************************/
rates<dtype>(a, temp, lam, nsets, ncells, ncoeff);
}
int main()
{
// Tensor dimensions
const int nsets = 4, ncells = 4, ncoeff = 8;
// Results and elapsed time
float *lam;
cudaMallocManaged(&lam, nsets * ncells * sizeof(float));
// Compute the rates
dim3 threadsPerBlock(nsets, ncells, ncoeff);
dim3 numBlocks(1, 1, 1);
exec<float, nsets, ncells, ncoeff><<<numBlocks, threadsPerBlock>>>(lam);
// Print ln(lambda)
cudaDeviceSynchronize();
printf("lambda:\n");
for(int i = 0; i < nsets; i++)
{
for(int j = 0; j < ncells; j++)
{
printf("%.3f\t", lam[i * ncells + j]);
}
printf("\n");
}
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
/**
* Computes the log of reaction rate.
* @param a: Pointer to coefficient matrix.
* @param temp: Pointer to temperature array.
* @param lam: Matrix to write the results to.
* @param nsets: Number of sets / number of rows in coefficient matrix.
* @param ncells: Number of cells / length of temperature array.
* @param ncoeff: Number of coefficients / number of columns in coefficient matrix.
*/
template <class dtype>
__device__ void rates(dtype *a, dtype *temp, dtype *lam, int nsets, int ncells, int ncoeff)
{
int istart = blockIdx.x * blockDim.x + threadIdx.x;
int istep = blockDim.x * gridDim.x;
int jstart = blockIdx.y * blockDim.y + threadIdx.y;
int jstep = blockDim.y * gridDim.y;
int kstart = blockIdx.z * blockDim.z + threadIdx.z;
int kstep = blockDim.z * gridDim.z;
for(int i = istart; i < nsets; i += istep)
{
for(int j = jstart; j < ncells; j += jstep)
{
dtype temp9 = temp[j] * 1.0e-9;
for(int k = kstart; k < ncoeff; k += kstep)
{
switch(k)
{
case 0:
atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k]);
break;
case 6:
atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k] * log(temp9));
break;
default:
atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k] * pow(temp9, (2 * k - 5) / 3.0));
break;
}
}
}
}
}
template <>
__device__ void rates<float>(float *a, float *temp, float *lam, int nsets, int ncells, int ncoeff)
{
int istart = blockIdx.x * blockDim.x + threadIdx.x;
int istep = blockDim.x * gridDim.x;
int jstart = blockIdx.y * blockDim.y + threadIdx.y;
int jstep = blockDim.y * gridDim.y;
int kstart = blockIdx.z * blockDim.z + threadIdx.z;
int kstep = blockDim.z * gridDim.z;
for(int i = istart; i < nsets; i += istep)
{
for(int j = jstart; j < ncells; j += jstep)
{
float temp9 = temp[j] * 1.0e-9;
for(int k = kstart; k < ncoeff; k += kstep)
{
switch(k)
{
case 0:
atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k]);
break;
case 6:
atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k] * logf(temp9));
break;
default:
atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k] * powf(temp9, (2 * k - 5) / 3.0f));
break;
}
}
}
}
}
template <class dtype, int nsets, int ncells, int ncoeff>
__global__ void exec(dtype* lam)
{
// Tensors
__shared__ dtype a[nsets * ncoeff];
__shared__ dtype temp[ncells];
int xInd = blockIdx.x * blockDim.x + threadIdx.x;
int yInd = blockIdx.y * blockDim.y + threadIdx.y;
int ySize = blockDim.y * gridDim.y;
int zInd = blockIdx.z * blockDim.z + threadIdx.z;
int zSize = blockDim.z * gridDim.z;
int ind = xInd * ySize * zSize + yInd * zSize + zInd;
/********************************
* Initialize coefficient matrix *
********************************/
if(ind < nsets * ncoeff)
{
if(ind % ncoeff != 7)
{
a[ind] = ind - (ind / ncoeff - 1);
}
else
{
a[ind] = 0.0;
}
}
/******************************************
* Initialize the temperature in each cell *
******************************************/
if(ind < ncells)
{
temp[ind] = (ind + 1) * 1e9;
}
/****************************
* Zero the array of results *
****************************/
if(ind < nsets * ncells)
{
lam[ind] = 0.0;
}
/*******************************************
* Compute ln(lambda) for each set and cell *
*******************************************/
rates<dtype>(a, temp, lam, nsets, ncells, ncoeff);
}
int main()
{
// Tensor dimensions
const int nsets = 4, ncells = 4, ncoeff = 8;
// Results and elapsed time
float *lam;
hipMallocManaged(&lam, nsets * ncells * sizeof(float));
// Compute the rates
dim3 threadsPerBlock(nsets, ncells, ncoeff);
dim3 numBlocks(1, 1, 1);
exec<float, nsets, ncells, ncoeff><<<numBlocks, threadsPerBlock>>>(lam);
// Print ln(lambda)
hipDeviceSynchronize();
printf("lambda:\n");
for(int i = 0; i < nsets; i++)
{
for(int j = 0; j < ncells; j++)
{
printf("%.3f\t", lam[i * ncells + j]);
}
printf("\n");
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
/**
* Computes the log of reaction rate.
* @param a: Pointer to coefficient matrix.
* @param temp: Pointer to temperature array.
* @param lam: Matrix to write the results to.
* @param nsets: Number of sets / number of rows in coefficient matrix.
* @param ncells: Number of cells / length of temperature array.
* @param ncoeff: Number of coefficients / number of columns in coefficient matrix.
*/
template <class dtype>
__device__ void rates(dtype *a, dtype *temp, dtype *lam, int nsets, int ncells, int ncoeff)
{
int istart = blockIdx.x * blockDim.x + threadIdx.x;
int istep = blockDim.x * gridDim.x;
int jstart = blockIdx.y * blockDim.y + threadIdx.y;
int jstep = blockDim.y * gridDim.y;
int kstart = blockIdx.z * blockDim.z + threadIdx.z;
int kstep = blockDim.z * gridDim.z;
for(int i = istart; i < nsets; i += istep)
{
for(int j = jstart; j < ncells; j += jstep)
{
dtype temp9 = temp[j] * 1.0e-9;
for(int k = kstart; k < ncoeff; k += kstep)
{
switch(k)
{
case 0:
atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k]);
break;
case 6:
atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k] * log(temp9));
break;
default:
atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k] * pow(temp9, (2 * k - 5) / 3.0));
break;
}
}
}
}
}
template <>
__device__ void rates<float>(float *a, float *temp, float *lam, int nsets, int ncells, int ncoeff)
{
int istart = blockIdx.x * blockDim.x + threadIdx.x;
int istep = blockDim.x * gridDim.x;
int jstart = blockIdx.y * blockDim.y + threadIdx.y;
int jstep = blockDim.y * gridDim.y;
int kstart = blockIdx.z * blockDim.z + threadIdx.z;
int kstep = blockDim.z * gridDim.z;
for(int i = istart; i < nsets; i += istep)
{
for(int j = jstart; j < ncells; j += jstep)
{
float temp9 = temp[j] * 1.0e-9;
for(int k = kstart; k < ncoeff; k += kstep)
{
switch(k)
{
case 0:
atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k]);
break;
case 6:
atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k] * logf(temp9));
break;
default:
atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k] * powf(temp9, (2 * k - 5) / 3.0f));
break;
}
}
}
}
}
template <class dtype, int nsets, int ncells, int ncoeff>
__global__ void exec(dtype* lam)
{
// Tensors
__shared__ dtype a[nsets * ncoeff];
__shared__ dtype temp[ncells];
int xInd = blockIdx.x * blockDim.x + threadIdx.x;
int yInd = blockIdx.y * blockDim.y + threadIdx.y;
int ySize = blockDim.y * gridDim.y;
int zInd = blockIdx.z * blockDim.z + threadIdx.z;
int zSize = blockDim.z * gridDim.z;
int ind = xInd * ySize * zSize + yInd * zSize + zInd;
/********************************
* Initialize coefficient matrix *
********************************/
if(ind < nsets * ncoeff)
{
if(ind % ncoeff != 7)
{
a[ind] = ind - (ind / ncoeff - 1);
}
else
{
a[ind] = 0.0;
}
}
/******************************************
* Initialize the temperature in each cell *
******************************************/
if(ind < ncells)
{
temp[ind] = (ind + 1) * 1e9;
}
/****************************
* Zero the array of results *
****************************/
if(ind < nsets * ncells)
{
lam[ind] = 0.0;
}
/*******************************************
* Compute ln(lambda) for each set and cell *
*******************************************/
rates<dtype>(a, temp, lam, nsets, ncells, ncoeff);
}
int main()
{
// Tensor dimensions
const int nsets = 4, ncells = 4, ncoeff = 8;
// Results and elapsed time
float *lam;
hipMallocManaged(&lam, nsets * ncells * sizeof(float));
// Compute the rates
dim3 threadsPerBlock(nsets, ncells, ncoeff);
dim3 numBlocks(1, 1, 1);
exec<float, nsets, ncells, ncoeff><<<numBlocks, threadsPerBlock>>>(lam);
// Print ln(lambda)
hipDeviceSynchronize();
printf("lambda:\n");
for(int i = 0; i < nsets; i++)
{
for(int j = 0; j < ncells; j++)
{
printf("%.3f\t", lam[i * ncells + j]);
}
printf("\n");
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z4execIfLi4ELi4ELi8EEvPT_,"axG",@progbits,_Z4execIfLi4ELi4ELi8EEvPT_,comdat
.protected _Z4execIfLi4ELi4ELi8EEvPT_
.globl _Z4execIfLi4ELi4ELi8EEvPT_
.p2align 8
.type _Z4execIfLi4ELi4ELi8EEvPT_,@function
_Z4execIfLi4ELi4ELi8EEvPT_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b32 s8, s[0:1], 0x18
v_bfe_u32 v3, v0, 10, 10
s_add_u32 s2, s0, 8
s_addc_u32 s3, s1, 0
v_and_b32_e32 v5, 0x3ff, v0
v_bfe_u32 v0, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s7, 0xffff
s_lshr_b32 s7, s7, 16
v_mad_u64_u32 v[6:7], null, s13, s9, v[5:6]
v_mad_u64_u32 v[1:2], null, s14, s7, v[3:4]
s_mul_i32 s5, s5, s7
s_and_b32 s7, s8, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_mul_i32 s10, s6, s7
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[2:3], null, s15, s7, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[7:8], null, s5, v6, v[1:2]
v_mad_u64_u32 v[3:4], null, v7, s10, v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 32, v3
s_cbranch_execz .LBB0_4
v_and_b32_e32 v0, 0x80000007, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, 7, v0
v_mov_b32_e32 v0, 0
s_and_saveexec_b32 s7, vcc_lo
v_ashrrev_i32_e32 v0, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v0, 29, v0
v_add_nc_u32_e32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v0, 3, v0
v_sub_nc_u32_e32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, 1, v0
v_cvt_f32_i32_e32 v0, v0
s_or_b32 exec_lo, exec_lo, s7
v_lshlrev_b32_e32 v4, 2, v3
ds_store_b32 v4, v0
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s6, exec_lo
v_cmpx_gt_i32_e32 4, v3
s_cbranch_execz .LBB0_6
v_add_nc_u32_e32 v0, 1, v3
v_lshlrev_b32_e32 v4, 2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_i32_e32 v[6:7], v0
v_mul_f64 v[6:7], v[6:7], 0x41cdcd65
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v0, v[6:7]
ds_store_b32 v4, v0 offset:128
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s6
s_load_b64 s[6:7], s[0:1], 0x0
s_mov_b32 s0, exec_lo
v_cmpx_gt_i32_e32 16, v3
s_cbranch_execz .LBB0_8
v_ashrrev_i32_e32 v4, 31, v3
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_store_b32 v[3:4], v0, off
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s0
s_cmp_lt_u32 s13, s4
s_cselect_b32 s0, 12, 18
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_mov_b32_e32 v0, s0
s_mov_b32 s0, exec_lo
global_load_u16 v0, v0, s[2:3]
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, s13, v0, v[5:6]
v_cmpx_gt_i32_e32 4, v3
s_cbranch_execz .LBB0_27
v_mul_lo_u32 v0, s4, v0
v_cmp_gt_i32_e64 s0, 4, v1
v_cmp_gt_i32_e64 s1, 8, v2
s_mov_b32 s11, 0
s_mov_b32 s9, 0x3e112e0b
s_mov_b32 s8, 0xe826d695
s_mov_b32 s12, 0x3e76c4e1
s_branch .LBB0_11
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s13
v_add_nc_u32_e32 v3, v3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_lt_i32_e32 vcc_lo, 3, v3
s_or_b32 s11, vcc_lo, s11
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execz .LBB0_27
.LBB0_11:
s_and_saveexec_b32 s13, s0
s_cbranch_execz .LBB0_10
v_lshlrev_b32_e32 v8, 2, v3
v_dual_mov_b32 v10, v1 :: v_dual_lshlrev_b32 v9, 5, v3
s_mov_b32 s14, 0
s_branch .LBB0_14
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s15
v_add_nc_u32_e32 v10, s5, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_lt_i32_e32 vcc_lo, 3, v10
s_or_b32 s14, vcc_lo, s14
s_and_not1_b32 exec_lo, exec_lo, s14
s_cbranch_execz .LBB0_10
.LBB0_14:
s_and_saveexec_b32 s15, s1
s_cbranch_execz .LBB0_13
v_lshlrev_b32_e32 v4, 2, v10
s_mov_b32 s17, 0
v_mov_b32_e32 v13, v2
ds_load_b32 v4, v4 offset:128
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[4:5], v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[4:5], v[4:5], s[8:9]
v_cvt_f32_f64_e32 v11, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_gt_f32_e32 vcc_lo, 0x800000, v11
v_cmp_eq_f32_e64 s16, 1.0, v11
v_cndmask_b32_e64 v4, 1.0, 0x4f800000, vcc_lo
v_mul_f32_e32 v4, v11, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_log_f32_e32 v6, v4
v_add_nc_u32_e32 v4, v10, v8
v_ashrrev_i32_e32 v5, 31, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v7, 0x3f317217, v6
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v12, v6, 0x3f317217, -v7
v_fmac_f32_e32 v12, 0x3377d1cf, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_f32_e32 v7, v7, v12
v_cndmask_b32_e64 v12, 0, 0x41b17218, vcc_lo
v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v6|
v_cndmask_b32_e32 v6, v6, v7, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_sub_f32_e32 v12, v6, v12
.LBB0_16:
v_lshl_add_u32 v6, v13, 2, v9
s_mov_b32 s2, 0
s_mov_b32 s3, exec_lo
ds_load_b32 v6, v6
v_cmpx_lt_i32_e32 5, v13
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_20
s_mov_b32 s2, -1
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 6, v13
s_cbranch_execz .LBB0_19
s_waitcnt lgkmcnt(0)
v_mul_f32_e32 v14, v12, v6
s_xor_b32 s2, exec_lo, -1
.LBB0_19:
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s2, s2, exec_lo
.LBB0_20:
s_and_not1_saveexec_b32 s3, s3
s_cbranch_execz .LBB0_22
v_cmp_ne_u32_e32 vcc_lo, 0, v13
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v14, v6
s_and_not1_b32 s2, s2, exec_lo
s_and_b32 s4, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s2, s4
.LBB0_22:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s18, s2
s_cbranch_execz .LBB0_24
v_lshl_add_u32 v7, v13, 1, -5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v7, v7
v_div_scale_f32 v14, null, 0x40400000, 0x40400000, v7
v_div_scale_f32 v17, vcc_lo, v7, 0x40400000, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v15, v14
s_waitcnt_depctr 0xfff
v_fma_f32 v16, -v14, v15, 1.0
v_fmac_f32_e32 v15, v16, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v16, v17, v15
v_fma_f32 v18, -v14, v16, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v16, v18, v15
v_fma_f32 v14, -v14, v16, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v14, v14, v15, v16
v_div_fixup_f32 v7, v14, 0x40400000, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v7, v7, 1.0, s16
v_cmp_neq_f32_e32 vcc_lo, 0, v7
v_cmp_neq_f32_e64 s19, v7, |v7|
v_cndmask_b32_e32 v14, 1.0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_frexp_mant_f32_e64 v15, |v14|
v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v15
v_cndmask_b32_e64 v16, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f32 v15, v15, v16
v_add_f32_e32 v16, 1.0, v15
v_add_f32_e32 v18, -1.0, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v17, v16
v_add_f32_e32 v20, -1.0, v16
v_sub_f32_e32 v15, v15, v20
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v19, v18, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v21, v16, v19
v_fma_f32 v16, v19, v16, -v21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v16, v19, v15
v_add_f32_e32 v15, v21, v16
v_cmp_lt_f32_e64 s20, |v14|, 1.0
v_cmp_eq_f32_e64 s4, 0, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v20, v18, v15
s_xor_b32 s19, s19, s20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v18, v18, v20 :: v_dual_sub_f32 v21, v15, v21
v_dual_sub_f32 v15, v18, v15 :: v_dual_sub_f32 v16, v21, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v15, v16, v15
v_add_f32_e32 v15, v20, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v15, v17, v15
v_add_f32_e32 v16, v19, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v17, v16, v19
v_dual_mul_f32 v18, v16, v16 :: v_dual_sub_f32 v15, v15, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v17, v16, v16, -v18
v_add_f32_e32 v19, v15, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v17, v16, v19
v_add_f32_e32 v19, v18, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmaak_f32 v20, s12, v19, 0x3e91f4c4
v_sub_f32_e32 v18, v19, v18
v_dual_fmaak_f32 v20, v19, v20, 0x3ecccdef :: v_dual_sub_f32 v17, v17, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v21, v19, v20
v_fma_f32 v18, v19, v20, -v21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v18, v17, v20
v_add_f32_e32 v20, v21, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v21, v20, v21
v_dual_mul_f32 v23, v16, v19 :: v_dual_add_f32 v22, 0x3f2aaaaa, v20
v_sub_f32_e32 v18, v18, v21
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v24, v19, v16, -v23
v_add_f32_e32 v21, 0xbf2aaaaa, v22
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v18, 0x31739010, v18
v_fmac_f32_e32 v24, v19, v15
v_ldexp_f32 v15, v15, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v24, v17, v16
v_sub_f32_e32 v20, v20, v21
v_ldexp_f32 v16, v16, 1
v_add_f32_e32 v19, v23, v24
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v18, v18, v20
v_add_f32_e32 v17, v22, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_f32_e32 v21, v19, v17
v_sub_f32_e32 v20, v22, v17
v_sub_f32_e32 v22, v19, v23
v_add_f32_e32 v18, v18, v20
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v20, v19, v17, -v21
v_sub_f32_e32 v22, v24, v22
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v20, v19, v18
v_frexp_exp_i32_f32_e32 v18, v14
v_fmac_f32_e32 v20, v22, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_subrev_co_ci_u32_e32 v17, vcc_lo, 0, v18, vcc_lo
v_add_f32_e32 v18, v21, v20
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v17, v17
v_sub_f32_e32 v21, v18, v21
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mul_f32 v22, 0x3f317218, v17 :: v_dual_add_f32 v19, v16, v18
v_sub_f32_e32 v20, v20, v21
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v21, v17, 0x3f317218, -v22
v_add_f32_e32 v15, v15, v20
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmac_f32 v21, 0xb102e308, v17 :: v_dual_sub_f32 v16, v19, v16
v_sub_f32_e32 v16, v18, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v15, v15, v16
v_dual_add_f32 v17, v19, v15 :: v_dual_add_f32 v16, v22, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v19, v17, v19 :: v_dual_add_f32 v18, v16, v17
v_dual_sub_f32 v15, v15, v19 :: v_dual_sub_f32 v20, v18, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_f32_e32 v23, v18, v20
v_dual_sub_f32 v17, v17, v20 :: v_dual_sub_f32 v22, v16, v22
v_dual_sub_f32 v16, v16, v23 :: v_dual_sub_f32 v21, v21, v22
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v16, v17, v16
v_add_f32_e32 v19, v21, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v17, v19, v21
v_add_f32_e32 v16, v19, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v19, v19, v17
v_sub_f32_e32 v15, v15, v17
v_dual_sub_f32 v17, v21, v19 :: v_dual_add_f32 v20, v18, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v15, v15, v17 :: v_dual_sub_f32 v18, v20, v18
v_sub_f32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v15, v15, v16
v_add_f32_e32 v16, v20, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v17, v16, v20
v_mul_f32_e32 v18, v7, v16
v_sub_f32_e32 v15, v15, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v16, v7, v16, -v18
v_cmp_class_f32_e64 vcc_lo, v18, 0x204
v_fmac_f32_e32 v16, v7, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v15, v18, v16
v_cndmask_b32_e32 v17, v15, v18, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v17
v_cndmask_b32_e64 v19, 0, 0x37000000, vcc_lo
v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v17|
v_sub_f32_e32 v20, v17, v19
v_trunc_f32_e32 v17, v7
v_sub_f32_e32 v15, v15, v18
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v21, 0x3fb8aa3b, v20
v_sub_f32_e32 v15, v16, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v22, v20, 0x3fb8aa3b, -v21
v_rndne_f32_e32 v23, v21
v_dual_fmac_f32 v22, 0x32a5705f, v20 :: v_dual_sub_f32 v21, v21, v23
v_cvt_i32_f32_e32 v18, v23
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v21, v21, v22
v_exp_f32_e32 v21, v21
s_waitcnt_depctr 0xfff
v_ldexp_f32 v16, v21, v18
v_cndmask_b32_e32 v15, 0, v15, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v20
v_mul_f32_e32 v18, 0.5, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v16, 0, v16, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v20
v_trunc_f32_e32 v21, v18
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_add_f32 v15, v19, v15 :: v_dual_cndmask_b32 v16, 0x7f800000, v16
v_cmp_eq_f32_e32 vcc_lo, v17, v7
v_cmp_neq_f32_e64 s2, v21, v18
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v15, v16, v15, v16
v_cmp_eq_f32_e64 s3, 0x7f800000, v16
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v17, 1.0, v14, s2
v_cndmask_b32_e64 v15, v15, v16, s3
v_cmp_gt_f32_e64 s3, 0, v7
v_cndmask_b32_e64 v16, |v7|, 0, s19
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_bfi_b32 v15, 0x7fffffff, v15, v17
s_xor_b32 s3, s3, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v18, 0x7f800000, 0, s3
v_cmp_eq_f32_e64 s3, |v14|, 1.0
v_cndmask_b32_e32 v17, 0x7fc00000, v15, vcc_lo
v_cmp_gt_f32_e32 vcc_lo, 0, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v16, v16, |v14|, s3
v_cndmask_b32_e32 v15, v15, v17, vcc_lo
v_cndmask_b32_e64 v17, 0, v14, s2
v_cmp_class_f32_e64 vcc_lo, v7, 0x204
v_cmp_class_f32_e64 s2, v14, 0x204
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v7, v15, v16, vcc_lo
v_bfi_b32 v15, 0x7fffffff, v18, v17
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
s_or_b32 vcc_lo, s4, s2
v_cndmask_b32_e32 v7, v7, v15, vcc_lo
v_cmp_o_f32_e32 vcc_lo, v14, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v7, 0x7fc00000, v7, vcc_lo
s_waitcnt lgkmcnt(0)
v_mul_f32_e32 v14, v7, v6
.LBB0_24:
s_or_b32 exec_lo, exec_lo, s18
global_load_b32 v7, v[4:5], off
s_mov_b32 s2, 0
.LBB0_25:
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v6, v7, v14
global_atomic_cmpswap_b32 v6, v[4:5], v[6:7], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v6, v7
v_mov_b32_e32 v7, v6
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_25
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v13, s10, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_lt_i32_e32 vcc_lo, 7, v13
s_or_b32 s17, vcc_lo, s17
s_and_not1_b32 exec_lo, exec_lo, s17
s_cbranch_execnz .LBB0_16
s_branch .LBB0_13
.LBB0_27:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4execIfLi4ELi4ELi8EEvPT_
.amdhsa_group_segment_fixed_size 144
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 25
.amdhsa_next_free_sgpr 21
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z4execIfLi4ELi4ELi8EEvPT_,"axG",@progbits,_Z4execIfLi4ELi4ELi8EEvPT_,comdat
.Lfunc_end0:
.size _Z4execIfLi4ELi4ELi8EEvPT_, .Lfunc_end0-_Z4execIfLi4ELi4ELi8EEvPT_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 144
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4execIfLi4ELi4ELi8EEvPT_
.private_segment_fixed_size: 0
.sgpr_count: 23
.sgpr_spill_count: 0
.symbol: _Z4execIfLi4ELi4ELi8EEvPT_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 25
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
/**
* Computes the log of reaction rate.
* @param a: Pointer to coefficient matrix.
* @param temp: Pointer to temperature array.
* @param lam: Matrix to write the results to.
* @param nsets: Number of sets / number of rows in coefficient matrix.
* @param ncells: Number of cells / length of temperature array.
* @param ncoeff: Number of coefficients / number of columns in coefficient matrix.
*/
template <class dtype>
__device__ void rates(dtype *a, dtype *temp, dtype *lam, int nsets, int ncells, int ncoeff)
{
int istart = blockIdx.x * blockDim.x + threadIdx.x;
int istep = blockDim.x * gridDim.x;
int jstart = blockIdx.y * blockDim.y + threadIdx.y;
int jstep = blockDim.y * gridDim.y;
int kstart = blockIdx.z * blockDim.z + threadIdx.z;
int kstep = blockDim.z * gridDim.z;
for(int i = istart; i < nsets; i += istep)
{
for(int j = jstart; j < ncells; j += jstep)
{
dtype temp9 = temp[j] * 1.0e-9;
for(int k = kstart; k < ncoeff; k += kstep)
{
switch(k)
{
case 0:
atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k]);
break;
case 6:
atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k] * log(temp9));
break;
default:
atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k] * pow(temp9, (2 * k - 5) / 3.0));
break;
}
}
}
}
}
template <>
__device__ void rates<float>(float *a, float *temp, float *lam, int nsets, int ncells, int ncoeff)
{
int istart = blockIdx.x * blockDim.x + threadIdx.x;
int istep = blockDim.x * gridDim.x;
int jstart = blockIdx.y * blockDim.y + threadIdx.y;
int jstep = blockDim.y * gridDim.y;
int kstart = blockIdx.z * blockDim.z + threadIdx.z;
int kstep = blockDim.z * gridDim.z;
for(int i = istart; i < nsets; i += istep)
{
for(int j = jstart; j < ncells; j += jstep)
{
float temp9 = temp[j] * 1.0e-9;
for(int k = kstart; k < ncoeff; k += kstep)
{
switch(k)
{
case 0:
atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k]);
break;
case 6:
atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k] * logf(temp9));
break;
default:
atomicAdd(&lam[i * ncells + j], a[i * ncoeff + k] * powf(temp9, (2 * k - 5) / 3.0f));
break;
}
}
}
}
}
template <class dtype, int nsets, int ncells, int ncoeff>
__global__ void exec(dtype* lam)
{
// Tensors
__shared__ dtype a[nsets * ncoeff];
__shared__ dtype temp[ncells];
int xInd = blockIdx.x * blockDim.x + threadIdx.x;
int yInd = blockIdx.y * blockDim.y + threadIdx.y;
int ySize = blockDim.y * gridDim.y;
int zInd = blockIdx.z * blockDim.z + threadIdx.z;
int zSize = blockDim.z * gridDim.z;
int ind = xInd * ySize * zSize + yInd * zSize + zInd;
/********************************
* Initialize coefficient matrix *
********************************/
if(ind < nsets * ncoeff)
{
if(ind % ncoeff != 7)
{
a[ind] = ind - (ind / ncoeff - 1);
}
else
{
a[ind] = 0.0;
}
}
/******************************************
* Initialize the temperature in each cell *
******************************************/
if(ind < ncells)
{
temp[ind] = (ind + 1) * 1e9;
}
/****************************
* Zero the array of results *
****************************/
if(ind < nsets * ncells)
{
lam[ind] = 0.0;
}
/*******************************************
* Compute ln(lambda) for each set and cell *
*******************************************/
rates<dtype>(a, temp, lam, nsets, ncells, ncoeff);
}
int main()
{
// Tensor dimensions
const int nsets = 4, ncells = 4, ncoeff = 8;
// Results and elapsed time
float *lam;
hipMallocManaged(&lam, nsets * ncells * sizeof(float));
// Compute the rates
dim3 threadsPerBlock(nsets, ncells, ncoeff);
dim3 numBlocks(1, 1, 1);
exec<float, nsets, ncells, ncoeff><<<numBlocks, threadsPerBlock>>>(lam);
// Print ln(lambda)
hipDeviceSynchronize();
printf("lambda:\n");
for(int i = 0; i < nsets; i++)
{
for(int j = 0; j < ncells; j++)
{
printf("%.3f\t", lam[i * ncells + j]);
}
printf("\n");
}
return 0;
} | .text
.file "react_shared.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $80, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 8(%rsp), %rdi
movl $64, %esi
movl $1, %edx
callq hipMallocManaged
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $17179869188, %rdx # imm = 0x400000004
movl $1, %esi
movl $8, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z4execIfLi4ELi4ELi8EEvPT_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
callq hipDeviceSynchronize
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_3 Depth=1
# => This Inner Loop Header: Depth=2
movq 8(%rsp), %rax
addq %rbx, %rax
movss (%rax,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r15
cmpq $4, %r15
jne .LBB0_4
# %bb.5: # in Loop: Header=BB0_3 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $16, %rbx
cmpq $4, %r14
jne .LBB0_3
# %bb.6:
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .text._Z19__device_stub__execIfLi4ELi4ELi8EEvPT_,"axG",@progbits,_Z19__device_stub__execIfLi4ELi4ELi8EEvPT_,comdat
.weak _Z19__device_stub__execIfLi4ELi4ELi8EEvPT_ # -- Begin function _Z19__device_stub__execIfLi4ELi4ELi8EEvPT_
.p2align 4, 0x90
.type _Z19__device_stub__execIfLi4ELi4ELi8EEvPT_,@function
_Z19__device_stub__execIfLi4ELi4ELi8EEvPT_: # @_Z19__device_stub__execIfLi4ELi4ELi8EEvPT_
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z4execIfLi4ELi4ELi8EEvPT_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z19__device_stub__execIfLi4ELi4ELi8EEvPT_, .Lfunc_end1-_Z19__device_stub__execIfLi4ELi4ELi8EEvPT_
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4execIfLi4ELi4ELi8EEvPT_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4execIfLi4ELi4ELi8EEvPT_,@object # @_Z4execIfLi4ELi4ELi8EEvPT_
.section .rodata._Z4execIfLi4ELi4ELi8EEvPT_,"aG",@progbits,_Z4execIfLi4ELi4ELi8EEvPT_,comdat
.weak _Z4execIfLi4ELi4ELi8EEvPT_
.p2align 3, 0x0
_Z4execIfLi4ELi4ELi8EEvPT_:
.quad _Z19__device_stub__execIfLi4ELi4ELi8EEvPT_
.size _Z4execIfLi4ELi4ELi8EEvPT_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%.3f\t"
.size .L.str.1, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4execIfLi4ELi4ELi8EEvPT_"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "lambda:"
.size .Lstr, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__execIfLi4ELi4ELi8EEvPT_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4execIfLi4ELi4ELi8EEvPT_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00110d06_00000000-6_react_shared.cudafe1.cpp"
.text
#APP
#NO_APP
.section .text._Z4execIfLi4ELi4ELi8EEvPT_,"axG",@progbits,_Z4execIfLi4ELi4ELi8EEvPT_,comdat
.weak _Z4execIfLi4ELi4ELi8EEvPT_
.type _Z4execIfLi4ELi4ELi8EEvPT_, @function
_Z4execIfLi4ELi4ELi8EEvPT_:
.LFB2136:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4execIfLi4ELi4ELi8EEvPT_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2136:
.size _Z4execIfLi4ELi4ELi8EEvPT_, .-_Z4execIfLi4ELi4ELi8EEvPT_
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5ratesIfEvPT_S1_S1_iii
.type _Z5ratesIfEvPT_S1_S1_iii, @function
_Z5ratesIfEvPT_S1_S1_iii:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z5ratesIfEvPT_S1_S1_iii, .-_Z5ratesIfEvPT_S1_S1_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "lambda:\n"
.LC1:
.string "%.3f\t"
.LC2:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2061:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $64, %esi
call cudaMallocManaged@PLT
movl $4, 16(%rsp)
movl $4, 20(%rsp)
movl $8, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $8, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L12:
call cudaDeviceSynchronize@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16, %ebp
leaq .LC1(%rip), %r12
leaq .LC2(%rip), %r13
.L13:
leaq -16(%rbp), %rbx
.L14:
movq 8(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L14
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rbp
cmpq $80, %rbp
jne .L13
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z4execIfLi4ELi4ELi8EEvPT_
jmp .L12
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z4execIfLi4ELi4ELi8EEvPT_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z4execIfLi4ELi4ELi8EEvPT_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "react_shared.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $80, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 8(%rsp), %rdi
movl $64, %esi
movl $1, %edx
callq hipMallocManaged
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $17179869188, %rdx # imm = 0x400000004
movl $1, %esi
movl $8, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z4execIfLi4ELi4ELi8EEvPT_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
callq hipDeviceSynchronize
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_3 Depth=1
# => This Inner Loop Header: Depth=2
movq 8(%rsp), %rax
addq %rbx, %rax
movss (%rax,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r15
cmpq $4, %r15
jne .LBB0_4
# %bb.5: # in Loop: Header=BB0_3 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $16, %rbx
cmpq $4, %r14
jne .LBB0_3
# %bb.6:
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .text._Z19__device_stub__execIfLi4ELi4ELi8EEvPT_,"axG",@progbits,_Z19__device_stub__execIfLi4ELi4ELi8EEvPT_,comdat
.weak _Z19__device_stub__execIfLi4ELi4ELi8EEvPT_ # -- Begin function _Z19__device_stub__execIfLi4ELi4ELi8EEvPT_
.p2align 4, 0x90
.type _Z19__device_stub__execIfLi4ELi4ELi8EEvPT_,@function
_Z19__device_stub__execIfLi4ELi4ELi8EEvPT_: # @_Z19__device_stub__execIfLi4ELi4ELi8EEvPT_
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z4execIfLi4ELi4ELi8EEvPT_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z19__device_stub__execIfLi4ELi4ELi8EEvPT_, .Lfunc_end1-_Z19__device_stub__execIfLi4ELi4ELi8EEvPT_
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4execIfLi4ELi4ELi8EEvPT_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4execIfLi4ELi4ELi8EEvPT_,@object # @_Z4execIfLi4ELi4ELi8EEvPT_
.section .rodata._Z4execIfLi4ELi4ELi8EEvPT_,"aG",@progbits,_Z4execIfLi4ELi4ELi8EEvPT_,comdat
.weak _Z4execIfLi4ELi4ELi8EEvPT_
.p2align 3, 0x0
_Z4execIfLi4ELi4ELi8EEvPT_:
.quad _Z19__device_stub__execIfLi4ELi4ELi8EEvPT_
.size _Z4execIfLi4ELi4ELi8EEvPT_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%.3f\t"
.size .L.str.1, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4execIfLi4ELi4ELi8EEvPT_"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "lambda:"
.size .Lstr, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__execIfLi4ELi4ELi8EEvPT_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4execIfLi4ELi4ELi8EEvPT_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* Voxel sampling GPU implementation
* Author Zhaoyu SU
* All Rights Reserved. Sep., 2019.
*/
#include <stdio.h>
#include <iostream>
#include <float.h>
//__global__ void output_init_gpu_kernel(int center_num, int kernel_num,
// float padding, int channels,
// float* output_features) {
// int thread_id = threadIdx.x + blockIdx.x * blockDim.x;
// if (thread_id < center_num * kernel_num) {
// for (int c=0; c<channels; c++) {
// output_features[thread_id*channels + c] = padding;
// }
// }
//}
__global__ void voxel_sampling_feature_gpu_kernel(int center_num, int channels, int kernel_num, float padding,
int output_pooling_size,
const float* input_features,
const int* output_idx,
float* output_features) {
int thread_id = threadIdx.x + blockIdx.x * blockDim.x;
int c = thread_id % channels;
int voxel_coor = thread_id / channels;
if (thread_id < center_num * kernel_num * channels) {
int pooling_count = 0;
for (int p=0; p<output_pooling_size; p++) {
int point_id = output_idx[voxel_coor*output_pooling_size + p];
if (point_id >= 0) {
output_features[thread_id] += input_features[point_id * channels + c];
pooling_count += 1;
// printf("%f\n", input_features[point_id * channels + c]);
}
}
// if (pooling_count > 1)
// printf("%f\n", output_features[thread_id]);
if (pooling_count > 0)
output_features[thread_id] /= pooling_count;
if (pooling_count == 0)
output_features[thread_id] = padding;
}
}
__global__ void voxel_sampling_feature_grad_gpu_kernel(int center_num, int kernel_num, int channels,
int output_pooling_size,
const int* output_idx,
const float* output_features_grad,
float* input_features_grad) {
int thread_id = threadIdx.x + blockIdx.x * blockDim.x;
if (thread_id < center_num * kernel_num) {
int pooling_count = 0;
for (int p=0; p<output_pooling_size; p++) {
if (output_idx[thread_id*output_pooling_size + p] >= 0)
pooling_count += 1;
}
for (int p=0; p<pooling_count; p++) {
int point_id = output_idx[thread_id*output_pooling_size + p];
for (int c=0; c<channels; c++) {
atomicAdd(&input_features_grad[point_id*channels + c], output_features_grad[thread_id*channels + c] / pooling_count);
}
}
}
}
void voxel_sampling_feature_gpu_launcher(int center_num, int kernel_num, int channels, float padding,
int output_pooling_size,
const float* input_features,
const int* output_idx,
float* output_features) {
if (center_num * channels <= 0) {
printf("VoxelSampleFeatureOp ERROR: Invalid CUDA input dimensions.\n");
return;
}
int blockSize; // The launch configurator returned block size
int minGridSize; // The minimum grid size needed to achieve the maximum occupancy for a full device launch
int gridSize; // The actual grid size needed, based on input size
// cudaOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, output_init_gpu_kernel, 0, center_num * kernel_num);
// gridSize = (center_num * kernel_num + blockSize - 1) / blockSize;
// output_init_gpu_kernel<<<gridSize, blockSize>>>(center_num, kernel_num,
// padding, channels,
// output_features);
cudaOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, voxel_sampling_feature_gpu_kernel, 0, center_num * kernel_num * channels);
gridSize = (center_num * kernel_num * channels + blockSize - 1) / blockSize;
voxel_sampling_feature_gpu_kernel<<<gridSize, blockSize>>>(center_num, channels, kernel_num, padding,
output_pooling_size,
input_features,
output_idx,
output_features);
}
void voxel_sampling_feature_grad_gpu_launcher(int center_num, int kernel_num, int channels,
int output_pooling_size,
const int* output_idx,
const float* output_features_grad,
float* input_features_grad) {
if (center_num==0 || kernel_num*channels == 0) {
printf("VoxelSampleGradOp ERROR: Invalid CUDA input dimensions.\n");
return;
}
int blockSize; // The launch configurator returned block size
int minGridSize; // The minimum grid size needed to achieve the maximum occupancy for a full device launch
int gridSize; // The actual grid size needed, based on input size
cudaOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, voxel_sampling_feature_grad_gpu_kernel, 0, center_num * kernel_num);
gridSize = (center_num * kernel_num + blockSize - 1) / blockSize;
voxel_sampling_feature_grad_gpu_kernel<<<gridSize, blockSize>>>(center_num, kernel_num, channels,
output_pooling_size,
output_idx,
output_features_grad,
input_features_grad);
} | .file "tmpxft_001284da_00000000-6_voxel_sampling_feature.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z64__device_stub__Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPfiiifiPKfPKiPf
.type _Z64__device_stub__Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPfiiifiPKfPKiPf, @function
_Z64__device_stub__Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPfiiifiPKfPKiPf:
.LFB3695:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movss %xmm0, 32(%rsp)
movl %ecx, 28(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq 208(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsp, %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z64__device_stub__Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPfiiifiPKfPKiPf, .-_Z64__device_stub__Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPfiiifiPKfPKiPf
.globl _Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf
.type _Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf, @function
_Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf:
.LFB3696:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z64__device_stub__Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPfiiifiPKfPKiPf
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf, .-_Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "VoxelSampleFeatureOp ERROR: Invalid CUDA input dimensions.\n"
.text
.globl _Z35voxel_sampling_feature_gpu_launcheriiifiPKfPKiPf
.type _Z35voxel_sampling_feature_gpu_launcheriiifiPKfPKiPf, @function
_Z35voxel_sampling_feature_gpu_launcheriiifiPKfPKiPf:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $280, %rsp
.cfi_def_cfa_offset 336
movss %xmm0, 8(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 16(%rsp)
movq %r9, 24(%rsp)
movq 336(%rsp), %r14
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
movl %edi, %eax
imull %edx, %eax
testl %eax, %eax
jle .L27
movl %edi, %ebx
movl %esi, %r15d
movl %edx, %ebp
movl %edi, %r12d
imull %esi, %r12d
imull %edx, %r12d
leaq 72(%rsp), %rdi
call cudaGetDevice@PLT
testl %eax, %eax
je .L28
.L14:
movl %r13d, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
leal -1(%r12,%r13), %eax
cltd
idivl %r13d
movl %eax, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 100(%rsp), %rdx
movl $1, %ecx
movq 88(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L11:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L11
.L28:
leaq 76(%rsp), %rdi
movl 72(%rsp), %edx
movl $39, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L14
leaq 80(%rsp), %rdi
movl 72(%rsp), %edx
movl $10, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L14
leaq 84(%rsp), %rdi
movl 72(%rsp), %edx
movl $1, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L14
leaq 88(%rsp), %rdi
movl 72(%rsp), %edx
movl $16, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L14
leaq 112(%rsp), %rdi
leaq _Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf(%rip), %rsi
call cudaFuncGetAttributes@PLT
testl %eax, %eax
jne .L14
movl 136(%rsp), %eax
movl 76(%rsp), %esi
movl 80(%rsp), %ecx
movl %r12d, %edx
testl %r12d, %r12d
jne .L15
movl 84(%rsp), %edx
.L15:
movl 84(%rsp), %edi
cmpl %edi, %eax
cmovg %edi, %eax
cmpl %edx, %eax
cmovle %eax, %edx
movl %edx, %edi
leal -1(%rcx,%rdx), %eax
cltd
idivl %ecx
imull %ecx, %eax
testl %eax, %eax
jle .L21
movl $0, 32(%rsp)
movl $0, %edx
movl %r12d, 36(%rsp)
movl %edx, %r12d
movl %r13d, 60(%rsp)
movl %edi, %r13d
movl %ebx, 40(%rsp)
movl %eax, %ebx
movl %r15d, 44(%rsp)
movl %ecx, %r15d
movl %ebp, 56(%rsp)
movq %r14, 48(%rsp)
movl %esi, %r14d
jmp .L17
.L16:
cmpl %r12d, %r14d
je .L23
subl %r15d, %ebx
testl %ebx, %ebx
jle .L31
.L17:
cmpl %ebx, %r13d
movl %ebx, %ebp
cmovle %r13d, %ebp
leaq 100(%rsp), %rdi
movl $0, %r8d
movl $0, %ecx
movl %ebp, %edx
leaq _Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf(%rip), %rsi
call cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags@PLT
testl %eax, %eax
jne .L25
movl %ebp, %eax
imull 100(%rsp), %eax
cmpl %eax, %r12d
jge .L16
movl %eax, %r12d
movl %ebp, 32(%rsp)
jmp .L16
.L31:
movl 36(%rsp), %r12d
movl 40(%rsp), %ebx
movl 44(%rsp), %r15d
movl 56(%rsp), %ebp
movq 48(%rsp), %r14
movl 32(%rsp), %r13d
jmp .L14
.L21:
movl $0, %r13d
jmp .L14
.L23:
movl 36(%rsp), %r12d
movl 40(%rsp), %ebx
movl 44(%rsp), %r15d
movl 56(%rsp), %ebp
movq 48(%rsp), %r14
movl 32(%rsp), %r13d
jmp .L14
.L25:
movl 36(%rsp), %r12d
movl 60(%rsp), %r13d
movl 40(%rsp), %ebx
movl 44(%rsp), %r15d
movl 56(%rsp), %ebp
movq 48(%rsp), %r14
jmp .L14
.L29:
subq $8, %rsp
.cfi_def_cfa_offset 344
pushq %r14
.cfi_def_cfa_offset 352
movq 40(%rsp), %r9
movq 32(%rsp), %r8
movl 28(%rsp), %ecx
movss 24(%rsp), %xmm0
movl %r15d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z64__device_stub__Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPfiiifiPKfPKiPf
addq $16, %rsp
.cfi_def_cfa_offset 336
jmp .L11
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z35voxel_sampling_feature_gpu_launcheriiifiPKfPKiPf, .-_Z35voxel_sampling_feature_gpu_launcheriiifiPKfPKiPf
.globl _Z68__device_stub__Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPfiiiiPKiPKfPf
.type _Z68__device_stub__Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPfiiiiPKiPKfPf, @function
_Z68__device_stub__Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPfiiiiPKiPKfPf:
.LFB3697:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movl %ecx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 192(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L36
.L32:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L37
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L32
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z68__device_stub__Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPfiiiiPKiPKfPf, .-_Z68__device_stub__Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPfiiiiPKiPKfPf
.globl _Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf
.type _Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf, @function
_Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf:
.LFB3698:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z68__device_stub__Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPfiiiiPKiPKfPf
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf, .-_Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf
.section .rodata.str1.8
.align 8
.LC1:
.string "VoxelSampleGradOp ERROR: Invalid CUDA input dimensions.\n"
.text
.globl _Z40voxel_sampling_feature_grad_gpu_launcheriiiiPKiPKfPf
.type _Z40voxel_sampling_feature_grad_gpu_launcheriiiiPKiPKfPf, @function
_Z40voxel_sampling_feature_grad_gpu_launcheriiiiPKiPKfPf:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $280, %rsp
.cfi_def_cfa_offset 336
movl %ecx, 12(%rsp)
movq %r8, 16(%rsp)
movq %r9, 24(%rsp)
movq 336(%rsp), %r14
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
testl %edi, %edi
je .L41
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movl %esi, %eax
imull %edx, %eax
testl %eax, %eax
jne .L42
.L41:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L40:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L57
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
movl %edi, %r15d
imull %esi, %r15d
leaq 72(%rsp), %rdi
call cudaGetDevice@PLT
testl %eax, %eax
je .L58
.L44:
movl %r13d, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
leal -1(%r15,%r13), %eax
cltd
idivl %r13d
movl %eax, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 100(%rsp), %rdx
movl $1, %ecx
movq 88(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L40
subq $8, %rsp
.cfi_def_cfa_offset 344
pushq %r14
.cfi_def_cfa_offset 352
movq 40(%rsp), %r9
movq 32(%rsp), %r8
movl 28(%rsp), %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z68__device_stub__Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPfiiiiPKiPKfPf
addq $16, %rsp
.cfi_def_cfa_offset 336
jmp .L40
.L58:
leaq 76(%rsp), %rdi
movl 72(%rsp), %edx
movl $39, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L44
leaq 80(%rsp), %rdi
movl 72(%rsp), %edx
movl $10, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L44
leaq 84(%rsp), %rdi
movl 72(%rsp), %edx
movl $1, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L44
leaq 88(%rsp), %rdi
movl 72(%rsp), %edx
movl $16, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L44
leaq 112(%rsp), %rdi
leaq _Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf(%rip), %rsi
call cudaFuncGetAttributes@PLT
testl %eax, %eax
jne .L44
movl 136(%rsp), %eax
movl 76(%rsp), %ecx
movl %ecx, %edi
movl 80(%rsp), %ecx
movl %r15d, %edx
testl %r15d, %r15d
jne .L45
movl 84(%rsp), %edx
.L45:
movl 84(%rsp), %esi
cmpl %esi, %eax
cmovg %esi, %eax
cmpl %edx, %eax
cmovle %eax, %edx
movl %edx, %esi
leal -1(%rcx,%rdx), %eax
cltd
idivl %ecx
imull %ecx, %eax
testl %eax, %eax
jle .L51
movl $0, 32(%rsp)
movl $0, %edx
movl %r15d, 36(%rsp)
movl %ecx, %r15d
movl %r13d, 60(%rsp)
movl %esi, %r13d
movl %ebx, 40(%rsp)
movl %eax, %ebx
movl %ebp, 44(%rsp)
movl %r12d, 56(%rsp)
movl %edx, %r12d
movq %r14, 48(%rsp)
movl %edi, %r14d
jmp .L47
.L46:
cmpl %r12d, %r14d
je .L53
subl %r15d, %ebx
testl %ebx, %ebx
jle .L59
.L47:
cmpl %ebx, %r13d
movl %ebx, %ebp
cmovle %r13d, %ebp
leaq 100(%rsp), %rdi
movl $0, %r8d
movl $0, %ecx
movl %ebp, %edx
leaq _Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf(%rip), %rsi
call cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags@PLT
testl %eax, %eax
jne .L55
movl %ebp, %eax
imull 100(%rsp), %eax
cmpl %eax, %r12d
jge .L46
movl %eax, %r12d
movl %ebp, 32(%rsp)
jmp .L46
.L59:
movl 36(%rsp), %r15d
movl 40(%rsp), %ebx
movl 44(%rsp), %ebp
movl 56(%rsp), %r12d
movq 48(%rsp), %r14
movl 32(%rsp), %r13d
jmp .L44
.L51:
movl $0, %r13d
jmp .L44
.L53:
movl 36(%rsp), %r15d
movl 40(%rsp), %ebx
movl 44(%rsp), %ebp
movl 56(%rsp), %r12d
movq 48(%rsp), %r14
movl 32(%rsp), %r13d
jmp .L44
.L55:
movl 36(%rsp), %r15d
movl 60(%rsp), %r13d
movl 40(%rsp), %ebx
movl 44(%rsp), %ebp
movl 56(%rsp), %r12d
movq 48(%rsp), %r14
jmp .L44
.L57:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size _Z40voxel_sampling_feature_grad_gpu_launcheriiiiPKiPKfPf, .-_Z40voxel_sampling_feature_grad_gpu_launcheriiiiPKiPKfPf
.section .rodata.str1.8
.align 8
.LC2:
.string "_Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf"
.align 8
.LC3:
.string "_Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* Voxel sampling GPU implementation
* Author Zhaoyu SU
* All Rights Reserved. Sep., 2019.
*/
#include <stdio.h>
#include <iostream>
#include <float.h>
//__global__ void output_init_gpu_kernel(int center_num, int kernel_num,
// float padding, int channels,
// float* output_features) {
// int thread_id = threadIdx.x + blockIdx.x * blockDim.x;
// if (thread_id < center_num * kernel_num) {
// for (int c=0; c<channels; c++) {
// output_features[thread_id*channels + c] = padding;
// }
// }
//}
__global__ void voxel_sampling_feature_gpu_kernel(int center_num, int channels, int kernel_num, float padding,
int output_pooling_size,
const float* input_features,
const int* output_idx,
float* output_features) {
int thread_id = threadIdx.x + blockIdx.x * blockDim.x;
int c = thread_id % channels;
int voxel_coor = thread_id / channels;
if (thread_id < center_num * kernel_num * channels) {
int pooling_count = 0;
for (int p=0; p<output_pooling_size; p++) {
int point_id = output_idx[voxel_coor*output_pooling_size + p];
if (point_id >= 0) {
output_features[thread_id] += input_features[point_id * channels + c];
pooling_count += 1;
// printf("%f\n", input_features[point_id * channels + c]);
}
}
// if (pooling_count > 1)
// printf("%f\n", output_features[thread_id]);
if (pooling_count > 0)
output_features[thread_id] /= pooling_count;
if (pooling_count == 0)
output_features[thread_id] = padding;
}
}
__global__ void voxel_sampling_feature_grad_gpu_kernel(int center_num, int kernel_num, int channels,
int output_pooling_size,
const int* output_idx,
const float* output_features_grad,
float* input_features_grad) {
int thread_id = threadIdx.x + blockIdx.x * blockDim.x;
if (thread_id < center_num * kernel_num) {
int pooling_count = 0;
for (int p=0; p<output_pooling_size; p++) {
if (output_idx[thread_id*output_pooling_size + p] >= 0)
pooling_count += 1;
}
for (int p=0; p<pooling_count; p++) {
int point_id = output_idx[thread_id*output_pooling_size + p];
for (int c=0; c<channels; c++) {
atomicAdd(&input_features_grad[point_id*channels + c], output_features_grad[thread_id*channels + c] / pooling_count);
}
}
}
}
void voxel_sampling_feature_gpu_launcher(int center_num, int kernel_num, int channels, float padding,
int output_pooling_size,
const float* input_features,
const int* output_idx,
float* output_features) {
if (center_num * channels <= 0) {
printf("VoxelSampleFeatureOp ERROR: Invalid CUDA input dimensions.\n");
return;
}
int blockSize; // The launch configurator returned block size
int minGridSize; // The minimum grid size needed to achieve the maximum occupancy for a full device launch
int gridSize; // The actual grid size needed, based on input size
// cudaOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, output_init_gpu_kernel, 0, center_num * kernel_num);
// gridSize = (center_num * kernel_num + blockSize - 1) / blockSize;
// output_init_gpu_kernel<<<gridSize, blockSize>>>(center_num, kernel_num,
// padding, channels,
// output_features);
cudaOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, voxel_sampling_feature_gpu_kernel, 0, center_num * kernel_num * channels);
gridSize = (center_num * kernel_num * channels + blockSize - 1) / blockSize;
voxel_sampling_feature_gpu_kernel<<<gridSize, blockSize>>>(center_num, channels, kernel_num, padding,
output_pooling_size,
input_features,
output_idx,
output_features);
}
void voxel_sampling_feature_grad_gpu_launcher(int center_num, int kernel_num, int channels,
int output_pooling_size,
const int* output_idx,
const float* output_features_grad,
float* input_features_grad) {
if (center_num==0 || kernel_num*channels == 0) {
printf("VoxelSampleGradOp ERROR: Invalid CUDA input dimensions.\n");
return;
}
int blockSize; // The launch configurator returned block size
int minGridSize; // The minimum grid size needed to achieve the maximum occupancy for a full device launch
int gridSize; // The actual grid size needed, based on input size
cudaOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, voxel_sampling_feature_grad_gpu_kernel, 0, center_num * kernel_num);
gridSize = (center_num * kernel_num + blockSize - 1) / blockSize;
voxel_sampling_feature_grad_gpu_kernel<<<gridSize, blockSize>>>(center_num, kernel_num, channels,
output_pooling_size,
output_idx,
output_features_grad,
input_features_grad);
} | /* Voxel sampling GPU implementation
* Author Zhaoyu SU
* All Rights Reserved. Sep., 2019.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <float.h>
//__global__ void output_init_gpu_kernel(int center_num, int kernel_num,
// float padding, int channels,
// float* output_features) {
// int thread_id = threadIdx.x + blockIdx.x * blockDim.x;
// if (thread_id < center_num * kernel_num) {
// for (int c=0; c<channels; c++) {
// output_features[thread_id*channels + c] = padding;
// }
// }
//}
__global__ void voxel_sampling_feature_gpu_kernel(int center_num, int channels, int kernel_num, float padding,
int output_pooling_size,
const float* input_features,
const int* output_idx,
float* output_features) {
int thread_id = threadIdx.x + blockIdx.x * blockDim.x;
int c = thread_id % channels;
int voxel_coor = thread_id / channels;
if (thread_id < center_num * kernel_num * channels) {
int pooling_count = 0;
for (int p=0; p<output_pooling_size; p++) {
int point_id = output_idx[voxel_coor*output_pooling_size + p];
if (point_id >= 0) {
output_features[thread_id] += input_features[point_id * channels + c];
pooling_count += 1;
// printf("%f\n", input_features[point_id * channels + c]);
}
}
// if (pooling_count > 1)
// printf("%f\n", output_features[thread_id]);
if (pooling_count > 0)
output_features[thread_id] /= pooling_count;
if (pooling_count == 0)
output_features[thread_id] = padding;
}
}
__global__ void voxel_sampling_feature_grad_gpu_kernel(int center_num, int kernel_num, int channels,
int output_pooling_size,
const int* output_idx,
const float* output_features_grad,
float* input_features_grad) {
int thread_id = threadIdx.x + blockIdx.x * blockDim.x;
if (thread_id < center_num * kernel_num) {
int pooling_count = 0;
for (int p=0; p<output_pooling_size; p++) {
if (output_idx[thread_id*output_pooling_size + p] >= 0)
pooling_count += 1;
}
for (int p=0; p<pooling_count; p++) {
int point_id = output_idx[thread_id*output_pooling_size + p];
for (int c=0; c<channels; c++) {
atomicAdd(&input_features_grad[point_id*channels + c], output_features_grad[thread_id*channels + c] / pooling_count);
}
}
}
}
void voxel_sampling_feature_gpu_launcher(int center_num, int kernel_num, int channels, float padding,
int output_pooling_size,
const float* input_features,
const int* output_idx,
float* output_features) {
if (center_num * channels <= 0) {
printf("VoxelSampleFeatureOp ERROR: Invalid CUDA input dimensions.\n");
return;
}
int blockSize; // The launch configurator returned block size
int minGridSize; // The minimum grid size needed to achieve the maximum occupancy for a full device launch
int gridSize; // The actual grid size needed, based on input size
// cudaOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, output_init_gpu_kernel, 0, center_num * kernel_num);
// gridSize = (center_num * kernel_num + blockSize - 1) / blockSize;
// output_init_gpu_kernel<<<gridSize, blockSize>>>(center_num, kernel_num,
// padding, channels,
// output_features);
hipOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, voxel_sampling_feature_gpu_kernel, 0, center_num * kernel_num * channels);
gridSize = (center_num * kernel_num * channels + blockSize - 1) / blockSize;
voxel_sampling_feature_gpu_kernel<<<gridSize, blockSize>>>(center_num, channels, kernel_num, padding,
output_pooling_size,
input_features,
output_idx,
output_features);
}
void voxel_sampling_feature_grad_gpu_launcher(int center_num, int kernel_num, int channels,
int output_pooling_size,
const int* output_idx,
const float* output_features_grad,
float* input_features_grad) {
if (center_num==0 || kernel_num*channels == 0) {
printf("VoxelSampleGradOp ERROR: Invalid CUDA input dimensions.\n");
return;
}
int blockSize; // The launch configurator returned block size
int minGridSize; // The minimum grid size needed to achieve the maximum occupancy for a full device launch
int gridSize; // The actual grid size needed, based on input size
hipOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, voxel_sampling_feature_grad_gpu_kernel, 0, center_num * kernel_num);
gridSize = (center_num * kernel_num + blockSize - 1) / blockSize;
voxel_sampling_feature_grad_gpu_kernel<<<gridSize, blockSize>>>(center_num, kernel_num, channels,
output_pooling_size,
output_idx,
output_features_grad,
input_features_grad);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* Voxel sampling GPU implementation
* Author Zhaoyu SU
* All Rights Reserved. Sep., 2019.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <float.h>
//__global__ void output_init_gpu_kernel(int center_num, int kernel_num,
// float padding, int channels,
// float* output_features) {
// int thread_id = threadIdx.x + blockIdx.x * blockDim.x;
// if (thread_id < center_num * kernel_num) {
// for (int c=0; c<channels; c++) {
// output_features[thread_id*channels + c] = padding;
// }
// }
//}
__global__ void voxel_sampling_feature_gpu_kernel(int center_num, int channels, int kernel_num, float padding,
int output_pooling_size,
const float* input_features,
const int* output_idx,
float* output_features) {
int thread_id = threadIdx.x + blockIdx.x * blockDim.x;
int c = thread_id % channels;
int voxel_coor = thread_id / channels;
if (thread_id < center_num * kernel_num * channels) {
int pooling_count = 0;
for (int p=0; p<output_pooling_size; p++) {
int point_id = output_idx[voxel_coor*output_pooling_size + p];
if (point_id >= 0) {
output_features[thread_id] += input_features[point_id * channels + c];
pooling_count += 1;
// printf("%f\n", input_features[point_id * channels + c]);
}
}
// if (pooling_count > 1)
// printf("%f\n", output_features[thread_id]);
if (pooling_count > 0)
output_features[thread_id] /= pooling_count;
if (pooling_count == 0)
output_features[thread_id] = padding;
}
}
__global__ void voxel_sampling_feature_grad_gpu_kernel(int center_num, int kernel_num, int channels,
int output_pooling_size,
const int* output_idx,
const float* output_features_grad,
float* input_features_grad) {
int thread_id = threadIdx.x + blockIdx.x * blockDim.x;
if (thread_id < center_num * kernel_num) {
int pooling_count = 0;
for (int p=0; p<output_pooling_size; p++) {
if (output_idx[thread_id*output_pooling_size + p] >= 0)
pooling_count += 1;
}
for (int p=0; p<pooling_count; p++) {
int point_id = output_idx[thread_id*output_pooling_size + p];
for (int c=0; c<channels; c++) {
atomicAdd(&input_features_grad[point_id*channels + c], output_features_grad[thread_id*channels + c] / pooling_count);
}
}
}
}
void voxel_sampling_feature_gpu_launcher(int center_num, int kernel_num, int channels, float padding,
int output_pooling_size,
const float* input_features,
const int* output_idx,
float* output_features) {
if (center_num * channels <= 0) {
printf("VoxelSampleFeatureOp ERROR: Invalid CUDA input dimensions.\n");
return;
}
int blockSize; // The launch configurator returned block size
int minGridSize; // The minimum grid size needed to achieve the maximum occupancy for a full device launch
int gridSize; // The actual grid size needed, based on input size
// cudaOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, output_init_gpu_kernel, 0, center_num * kernel_num);
// gridSize = (center_num * kernel_num + blockSize - 1) / blockSize;
// output_init_gpu_kernel<<<gridSize, blockSize>>>(center_num, kernel_num,
// padding, channels,
// output_features);
hipOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, voxel_sampling_feature_gpu_kernel, 0, center_num * kernel_num * channels);
gridSize = (center_num * kernel_num * channels + blockSize - 1) / blockSize;
voxel_sampling_feature_gpu_kernel<<<gridSize, blockSize>>>(center_num, channels, kernel_num, padding,
output_pooling_size,
input_features,
output_idx,
output_features);
}
void voxel_sampling_feature_grad_gpu_launcher(int center_num, int kernel_num, int channels,
int output_pooling_size,
const int* output_idx,
const float* output_features_grad,
float* input_features_grad) {
if (center_num==0 || kernel_num*channels == 0) {
printf("VoxelSampleGradOp ERROR: Invalid CUDA input dimensions.\n");
return;
}
int blockSize; // The launch configurator returned block size
int minGridSize; // The minimum grid size needed to achieve the maximum occupancy for a full device launch
int gridSize; // The actual grid size needed, based on input size
hipOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, voxel_sampling_feature_grad_gpu_kernel, 0, center_num * kernel_num);
gridSize = (center_num * kernel_num + blockSize - 1) / blockSize;
voxel_sampling_feature_grad_gpu_kernel<<<gridSize, blockSize>>>(center_num, kernel_num, channels,
output_pooling_size,
output_idx,
output_features_grad,
input_features_grad);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf
.globl _Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf
.p2align 8
.type _Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf,@function
_Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x3c
s_load_b64 s[8:9], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mul_i32 s2, s9, s8
s_mul_i32 s2, s2, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_11
s_clause 0x1
s_load_b32 s8, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x28
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_6
s_ashr_i32 s4, s9, 31
v_ashrrev_i32_e32 v5, 31, v1
s_add_i32 s5, s9, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s5, s5, s4
v_add_nc_u32_e32 v4, v1, v5
v_cvt_f32_u32_e32 v0, s5
s_sub_i32 s6, 0, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v6, v4, v5
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v5, s4, v5
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v3, s6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v0, v3
v_add_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v6, v0, 0
v_mul_lo_u32 v0, v4, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v6, v0
v_subrev_nc_u32_e32 v6, s5, v0
v_cmp_le_u32_e32 vcc_lo, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v0, v0, v6 :: v_dual_add_nc_u32 v3, 1, v4
v_cndmask_b32_e32 v3, v4, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s5, v0
v_add_nc_u32_e32 v4, 1, v3
s_load_b128 s[4:7], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v3, v4, vcc_lo
v_xor_b32_e32 v0, v0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v0, v0, v5
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_mul_lo_u32 v3, v0, s8
v_mul_lo_u32 v0, v0, s9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_sub_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[7:8], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v6, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v8, vcc_lo
v_mov_b32_e32 v7, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s6
v_add_co_u32 v5, vcc_lo, v5, 4
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_add_i32 s8, s8, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_7
.LBB0_4:
global_load_b32 v8, v[5:6], off
s_mov_b32 s6, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e32 -1, v8
s_cbranch_execz .LBB0_3
v_mad_u64_u32 v[9:10], null, v8, s9, v[0:1]
v_add_nc_u32_e32 v7, 1, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[8:9], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
global_load_b32 v8, v[8:9], off
global_load_b32 v9, v[3:4], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v8, v8, v9
global_store_b32 v[3:4], v8, off
s_branch .LBB0_3
.LBB0_6:
v_mov_b32_e32 v7, 0
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e32 0, v7
s_cbranch_execz .LBB0_9
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_cvt_f32_i32_e32 v5, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v6, null, v5, v5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v8, v6
s_waitcnt_depctr 0xfff
v_fma_f32 v9, -v6, v8, 1.0
v_fmac_f32_e32 v8, v9, v8
v_div_scale_f32 v9, vcc_lo, v0, v5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v10, v9, v8
v_fma_f32 v11, -v6, v10, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v10, v11, v8
v_fma_f32 v6, -v6, v10, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v6, v6, v8, v10
v_div_fixup_f32 v0, v6, v5, v0
global_store_b32 v[3:4], v0, off
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s4
v_cmp_eq_u32_e32 vcc_lo, 0, v7
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_11
s_load_b32 s0, s[0:1], 0xc
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v2, s0
global_store_b32 v[0:1], v2, off
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf, .Lfunc_end0-_Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf
.globl _Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf
.p2align 8
.type _Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf,@function
_Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_mul_i32 s2, s3, s2
v_mad_u64_u32 v[2:3], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v2
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_13
s_clause 0x1
s_load_b32 s2, s[0:1], 0xc
s_load_b64 s[4:5], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v0, v2, s2
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB1_4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_mov_b32_e32 v5, 0
v_lshlrev_b64 v[3:4], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.LBB1_3:
global_load_b32 v1, v[3:4], off
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
s_waitcnt vmcnt(0)
v_not_b32_e32 v1, v1
v_lshrrev_b32_e32 v1, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v5, v5, v1
s_cbranch_scc0 .LBB1_3
s_branch .LBB1_5
.LBB1_4:
v_mov_b32_e32 v5, 0
.LBB1_5:
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, 0, v5
s_mov_b32 s6, 0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_13
s_clause 0x1
s_load_b32 s7, s[0:1], 0x8
s_load_b128 s[0:3], s[0:1], 0x18
v_cvt_f32_i32_e32 v7, v5
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v6, v2, s7
s_cmp_gt_i32 s7, 0
s_cselect_b32 s8, -1, 0
s_branch .LBB1_8
.LBB1_7:
s_add_i32 s9, s9, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, s9, v5
s_or_b32 s6, vcc_lo, s6
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execz .LBB1_13
.LBB1_8:
s_and_not1_b32 vcc_lo, exec_lo, s8
s_cbranch_vccnz .LBB1_7
v_add_nc_u32_e32 v1, s9, v0
s_mov_b32 s10, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v8, v1, s7
.LBB1_10:
v_add_nc_u32_e32 v1, s10, v6
s_mov_b32 s11, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v3, v[1:2], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v9, null, v7, v7, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v10, v9
s_waitcnt_depctr 0xfff
v_fma_f32 v11, -v9, v10, 1.0
v_dual_fmac_f32 v10, v11, v10 :: v_dual_add_nc_u32 v1, s10, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
v_div_scale_f32 v11, vcc_lo, v3, v7, v3
global_load_b32 v4, v[1:2], off
v_mul_f32_e32 v12, v11, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v13, -v9, v12, v11
v_fmac_f32_e32 v12, v13, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v9, -v9, v12, v11
v_div_fmas_f32 v9, v9, v10, v12
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v9, v9, v7, v3
.LBB1_11:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v3, v4, v9
global_atomic_cmpswap_b32 v3, v[1:2], v[3:4], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v3, v4
v_mov_b32_e32 v4, v3
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB1_11
s_or_b32 exec_lo, exec_lo, s11
s_add_i32 s10, s10, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s10, s7
s_cbranch_scc0 .LBB1_10
s_branch .LBB1_7
.LBB1_13:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf, .Lfunc_end1-_Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* Voxel sampling GPU implementation
* Author Zhaoyu SU
* All Rights Reserved. Sep., 2019.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <float.h>
//__global__ void output_init_gpu_kernel(int center_num, int kernel_num,
// float padding, int channels,
// float* output_features) {
// int thread_id = threadIdx.x + blockIdx.x * blockDim.x;
// if (thread_id < center_num * kernel_num) {
// for (int c=0; c<channels; c++) {
// output_features[thread_id*channels + c] = padding;
// }
// }
//}
__global__ void voxel_sampling_feature_gpu_kernel(int center_num, int channels, int kernel_num, float padding,
int output_pooling_size,
const float* input_features,
const int* output_idx,
float* output_features) {
int thread_id = threadIdx.x + blockIdx.x * blockDim.x;
int c = thread_id % channels;
int voxel_coor = thread_id / channels;
if (thread_id < center_num * kernel_num * channels) {
int pooling_count = 0;
for (int p=0; p<output_pooling_size; p++) {
int point_id = output_idx[voxel_coor*output_pooling_size + p];
if (point_id >= 0) {
output_features[thread_id] += input_features[point_id * channels + c];
pooling_count += 1;
// printf("%f\n", input_features[point_id * channels + c]);
}
}
// if (pooling_count > 1)
// printf("%f\n", output_features[thread_id]);
if (pooling_count > 0)
output_features[thread_id] /= pooling_count;
if (pooling_count == 0)
output_features[thread_id] = padding;
}
}
__global__ void voxel_sampling_feature_grad_gpu_kernel(int center_num, int kernel_num, int channels,
int output_pooling_size,
const int* output_idx,
const float* output_features_grad,
float* input_features_grad) {
int thread_id = threadIdx.x + blockIdx.x * blockDim.x;
if (thread_id < center_num * kernel_num) {
int pooling_count = 0;
for (int p=0; p<output_pooling_size; p++) {
if (output_idx[thread_id*output_pooling_size + p] >= 0)
pooling_count += 1;
}
for (int p=0; p<pooling_count; p++) {
int point_id = output_idx[thread_id*output_pooling_size + p];
for (int c=0; c<channels; c++) {
atomicAdd(&input_features_grad[point_id*channels + c], output_features_grad[thread_id*channels + c] / pooling_count);
}
}
}
}
void voxel_sampling_feature_gpu_launcher(int center_num, int kernel_num, int channels, float padding,
int output_pooling_size,
const float* input_features,
const int* output_idx,
float* output_features) {
if (center_num * channels <= 0) {
printf("VoxelSampleFeatureOp ERROR: Invalid CUDA input dimensions.\n");
return;
}
int blockSize; // The launch configurator returned block size
int minGridSize; // The minimum grid size needed to achieve the maximum occupancy for a full device launch
int gridSize; // The actual grid size needed, based on input size
// cudaOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, output_init_gpu_kernel, 0, center_num * kernel_num);
// gridSize = (center_num * kernel_num + blockSize - 1) / blockSize;
// output_init_gpu_kernel<<<gridSize, blockSize>>>(center_num, kernel_num,
// padding, channels,
// output_features);
hipOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, voxel_sampling_feature_gpu_kernel, 0, center_num * kernel_num * channels);
gridSize = (center_num * kernel_num * channels + blockSize - 1) / blockSize;
voxel_sampling_feature_gpu_kernel<<<gridSize, blockSize>>>(center_num, channels, kernel_num, padding,
output_pooling_size,
input_features,
output_idx,
output_features);
}
void voxel_sampling_feature_grad_gpu_launcher(int center_num, int kernel_num, int channels,
int output_pooling_size,
const int* output_idx,
const float* output_features_grad,
float* input_features_grad) {
if (center_num==0 || kernel_num*channels == 0) {
printf("VoxelSampleGradOp ERROR: Invalid CUDA input dimensions.\n");
return;
}
int blockSize; // The launch configurator returned block size
int minGridSize; // The minimum grid size needed to achieve the maximum occupancy for a full device launch
int gridSize; // The actual grid size needed, based on input size
hipOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, voxel_sampling_feature_grad_gpu_kernel, 0, center_num * kernel_num);
gridSize = (center_num * kernel_num + blockSize - 1) / blockSize;
voxel_sampling_feature_grad_gpu_kernel<<<gridSize, blockSize>>>(center_num, kernel_num, channels,
output_pooling_size,
output_idx,
output_features_grad,
input_features_grad);
} | .text
.file "voxel_sampling_feature.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z48__device_stub__voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf # -- Begin function _Z48__device_stub__voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf
.p2align 4, 0x90
.type _Z48__device_stub__voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf,@function
_Z48__device_stub__voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf: # @_Z48__device_stub__voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movss %xmm0, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 88(%rsp)
movq %r9, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rax
movq %rax, 144(%rsp)
leaq 176(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z48__device_stub__voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf, .Lfunc_end0-_Z48__device_stub__voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf
.cfi_endproc
# -- End function
.globl _Z53__device_stub__voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf # -- Begin function _Z53__device_stub__voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf
.p2align 4, 0x90
.type _Z53__device_stub__voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf,@function
_Z53__device_stub__voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf: # @_Z53__device_stub__voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _Z53__device_stub__voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf, .Lfunc_end1-_Z53__device_stub__voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf
.cfi_endproc
# -- End function
.globl _Z35voxel_sampling_feature_gpu_launcheriiifiPKfPKiPf # -- Begin function _Z35voxel_sampling_feature_gpu_launcheriiifiPKfPKiPf
.p2align 4, 0x90
.type _Z35voxel_sampling_feature_gpu_launcheriiifiPKfPKiPf,@function
_Z35voxel_sampling_feature_gpu_launcheriiifiPKfPKiPf: # @_Z35voxel_sampling_feature_gpu_launcheriiifiPKfPKiPf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
imull %edi, %ebx
testl %ebx, %ebx
jle .LBB2_4
# %bb.1:
movq %r8, %r14
movl %ecx, %ebp
movl %edx, %r12d
movl %esi, %r15d
movl %edi, %r13d
movss %xmm0, 4(%rsp) # 4-byte Spill
movq %r9, 40(%rsp) # 8-byte Spill
movq 256(%rsp), %rax
movq %rax, 32(%rsp) # 8-byte Spill
imull %esi, %ebx
leaq 124(%rsp), %rdi
leaq 8(%rsp), %rsi
movl $_Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf, %edx
xorl %ecx, %ecx
movl %ebx, %r8d
callq hipOccupancyMaxPotentialBlockSize
movl 8(%rsp), %ecx
leal (%rbx,%rcx), %eax
decl %eax
cltd
idivl %ecx
# kill: def $eax killed $eax def $rax
movabsq $4294967296, %rdx # imm = 0x100000000
leaq (%rax,%rdx), %rdi
orq %rdx, %rcx
movl $1, %esi
movq %rcx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_3
# %bb.2:
movl %r13d, 28(%rsp)
movl %r12d, 24(%rsp)
movl %r15d, 20(%rsp)
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 16(%rsp)
movl %ebp, 12(%rsp)
movq %r14, 112(%rsp)
movq 40(%rsp), %rax # 8-byte Reload
movq %rax, 104(%rsp)
movq 32(%rsp), %rax # 8-byte Reload
movq %rax, 96(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rax
movq %rax, 184(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_3:
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_4:
.cfi_def_cfa_offset 256
movl $.Lstr, %edi
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end2:
.size _Z35voxel_sampling_feature_gpu_launcheriiifiPKfPKiPf, .Lfunc_end2-_Z35voxel_sampling_feature_gpu_launcheriiifiPKfPKiPf
.cfi_endproc
# -- End function
.globl _Z40voxel_sampling_feature_grad_gpu_launcheriiiiPKiPKfPf # -- Begin function _Z40voxel_sampling_feature_grad_gpu_launcheriiiiPKiPKfPf
.p2align 4, 0x90
.type _Z40voxel_sampling_feature_grad_gpu_launcheriiiiPKiPKfPf,@function
_Z40voxel_sampling_feature_grad_gpu_launcheriiiiPKiPKfPf: # @_Z40voxel_sampling_feature_grad_gpu_launcheriiiiPKiPKfPf
.cfi_startproc
# %bb.0:
testl %edi, %edi
je .LBB3_5
# %bb.1:
movl %edx, %eax
imull %esi, %eax
testl %eax, %eax
je .LBB3_5
# %bb.2:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r13d
movl %ecx, %ebp
movq %r8, %r12
movq %r9, 40(%rsp) # 8-byte Spill
movq 240(%rsp), %rax
movq %rax, 32(%rsp) # 8-byte Spill
movl %esi, %r14d
movl %esi, %ebx
movl %edi, %r15d
imull %edi, %ebx
leaq 124(%rsp), %rdi
leaq 12(%rsp), %rsi
movl $_Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf, %edx
xorl %ecx, %ecx
movl %ebx, %r8d
callq hipOccupancyMaxPotentialBlockSize
movl 12(%rsp), %ecx
leal (%rbx,%rcx), %eax
decl %eax
cltd
idivl %ecx
# kill: def $eax killed $eax def $rax
movabsq $4294967296, %rdx # imm = 0x100000000
leaq (%rax,%rdx), %rdi
orq %rdx, %rcx
movl $1, %esi
movq %rcx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movl %r15d, 28(%rsp)
movl %r14d, 24(%rsp)
movl %r13d, 20(%rsp)
movl %ebp, 16(%rsp)
movq %r12, 112(%rsp)
movq 40(%rsp), %rax # 8-byte Reload
movq %rax, 104(%rsp)
movq 32(%rsp), %rax # 8-byte Reload
movq %rax, 96(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 112(%rsp), %rax
movq %rax, 160(%rsp)
leaq 104(%rsp), %rax
movq %rax, 168(%rsp)
leaq 96(%rsp), %rax
movq %rax, 176(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_5:
.cfi_restore %rbx
.cfi_restore %rbp
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
movl $.Lstr.1, %edi
jmp puts@PLT # TAILCALL
.Lfunc_end3:
.size _Z40voxel_sampling_feature_grad_gpu_launcheriiiiPKiPKfPf, .Lfunc_end3-_Z40voxel_sampling_feature_grad_gpu_launcheriiiiPKiPKfPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf,@object # @_Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf
.section .rodata,"a",@progbits
.globl _Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf
.p2align 3, 0x0
_Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf:
.quad _Z48__device_stub__voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf
.size _Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf, 8
.type _Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf,@object # @_Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf
.globl _Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf
.p2align 3, 0x0
_Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf:
.quad _Z53__device_stub__voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf
.size _Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf"
.size .L__unnamed_1, 51
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf"
.size .L__unnamed_2, 55
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "VoxelSampleFeatureOp ERROR: Invalid CUDA input dimensions."
.size .Lstr, 59
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "VoxelSampleGradOp ERROR: Invalid CUDA input dimensions."
.size .Lstr.1, 56
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z48__device_stub__voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf
.addrsig_sym _Z53__device_stub__voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf
.addrsig_sym _Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001284da_00000000-6_voxel_sampling_feature.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z64__device_stub__Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPfiiifiPKfPKiPf
.type _Z64__device_stub__Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPfiiifiPKfPKiPf, @function
_Z64__device_stub__Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPfiiifiPKfPKiPf:
.LFB3695:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movss %xmm0, 32(%rsp)
movl %ecx, 28(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq 208(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsp, %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z64__device_stub__Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPfiiifiPKfPKiPf, .-_Z64__device_stub__Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPfiiifiPKfPKiPf
.globl _Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf
.type _Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf, @function
_Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf:
.LFB3696:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z64__device_stub__Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPfiiifiPKfPKiPf
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf, .-_Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "VoxelSampleFeatureOp ERROR: Invalid CUDA input dimensions.\n"
.text
.globl _Z35voxel_sampling_feature_gpu_launcheriiifiPKfPKiPf
.type _Z35voxel_sampling_feature_gpu_launcheriiifiPKfPKiPf, @function
_Z35voxel_sampling_feature_gpu_launcheriiifiPKfPKiPf:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $280, %rsp
.cfi_def_cfa_offset 336
movss %xmm0, 8(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 16(%rsp)
movq %r9, 24(%rsp)
movq 336(%rsp), %r14
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
movl %edi, %eax
imull %edx, %eax
testl %eax, %eax
jle .L27
movl %edi, %ebx
movl %esi, %r15d
movl %edx, %ebp
movl %edi, %r12d
imull %esi, %r12d
imull %edx, %r12d
leaq 72(%rsp), %rdi
call cudaGetDevice@PLT
testl %eax, %eax
je .L28
.L14:
movl %r13d, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
leal -1(%r12,%r13), %eax
cltd
idivl %r13d
movl %eax, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 100(%rsp), %rdx
movl $1, %ecx
movq 88(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L11:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L11
.L28:
leaq 76(%rsp), %rdi
movl 72(%rsp), %edx
movl $39, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L14
leaq 80(%rsp), %rdi
movl 72(%rsp), %edx
movl $10, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L14
leaq 84(%rsp), %rdi
movl 72(%rsp), %edx
movl $1, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L14
leaq 88(%rsp), %rdi
movl 72(%rsp), %edx
movl $16, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L14
leaq 112(%rsp), %rdi
leaq _Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf(%rip), %rsi
call cudaFuncGetAttributes@PLT
testl %eax, %eax
jne .L14
movl 136(%rsp), %eax
movl 76(%rsp), %esi
movl 80(%rsp), %ecx
movl %r12d, %edx
testl %r12d, %r12d
jne .L15
movl 84(%rsp), %edx
.L15:
movl 84(%rsp), %edi
cmpl %edi, %eax
cmovg %edi, %eax
cmpl %edx, %eax
cmovle %eax, %edx
movl %edx, %edi
leal -1(%rcx,%rdx), %eax
cltd
idivl %ecx
imull %ecx, %eax
testl %eax, %eax
jle .L21
movl $0, 32(%rsp)
movl $0, %edx
movl %r12d, 36(%rsp)
movl %edx, %r12d
movl %r13d, 60(%rsp)
movl %edi, %r13d
movl %ebx, 40(%rsp)
movl %eax, %ebx
movl %r15d, 44(%rsp)
movl %ecx, %r15d
movl %ebp, 56(%rsp)
movq %r14, 48(%rsp)
movl %esi, %r14d
jmp .L17
.L16:
cmpl %r12d, %r14d
je .L23
subl %r15d, %ebx
testl %ebx, %ebx
jle .L31
.L17:
cmpl %ebx, %r13d
movl %ebx, %ebp
cmovle %r13d, %ebp
leaq 100(%rsp), %rdi
movl $0, %r8d
movl $0, %ecx
movl %ebp, %edx
leaq _Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf(%rip), %rsi
call cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags@PLT
testl %eax, %eax
jne .L25
movl %ebp, %eax
imull 100(%rsp), %eax
cmpl %eax, %r12d
jge .L16
movl %eax, %r12d
movl %ebp, 32(%rsp)
jmp .L16
.L31:
movl 36(%rsp), %r12d
movl 40(%rsp), %ebx
movl 44(%rsp), %r15d
movl 56(%rsp), %ebp
movq 48(%rsp), %r14
movl 32(%rsp), %r13d
jmp .L14
.L21:
movl $0, %r13d
jmp .L14
.L23:
movl 36(%rsp), %r12d
movl 40(%rsp), %ebx
movl 44(%rsp), %r15d
movl 56(%rsp), %ebp
movq 48(%rsp), %r14
movl 32(%rsp), %r13d
jmp .L14
.L25:
movl 36(%rsp), %r12d
movl 60(%rsp), %r13d
movl 40(%rsp), %ebx
movl 44(%rsp), %r15d
movl 56(%rsp), %ebp
movq 48(%rsp), %r14
jmp .L14
.L29:
subq $8, %rsp
.cfi_def_cfa_offset 344
pushq %r14
.cfi_def_cfa_offset 352
movq 40(%rsp), %r9
movq 32(%rsp), %r8
movl 28(%rsp), %ecx
movss 24(%rsp), %xmm0
movl %r15d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z64__device_stub__Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPfiiifiPKfPKiPf
addq $16, %rsp
.cfi_def_cfa_offset 336
jmp .L11
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z35voxel_sampling_feature_gpu_launcheriiifiPKfPKiPf, .-_Z35voxel_sampling_feature_gpu_launcheriiifiPKfPKiPf
.globl _Z68__device_stub__Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPfiiiiPKiPKfPf
.type _Z68__device_stub__Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPfiiiiPKiPKfPf, @function
_Z68__device_stub__Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPfiiiiPKiPKfPf:
.LFB3697:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movl %ecx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 192(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L36
.L32:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L37
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L32
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z68__device_stub__Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPfiiiiPKiPKfPf, .-_Z68__device_stub__Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPfiiiiPKiPKfPf
.globl _Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf
.type _Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf, @function
_Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf:
.LFB3698:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z68__device_stub__Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPfiiiiPKiPKfPf
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf, .-_Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf
.section .rodata.str1.8
.align 8
.LC1:
.string "VoxelSampleGradOp ERROR: Invalid CUDA input dimensions.\n"
.text
.globl _Z40voxel_sampling_feature_grad_gpu_launcheriiiiPKiPKfPf
.type _Z40voxel_sampling_feature_grad_gpu_launcheriiiiPKiPKfPf, @function
_Z40voxel_sampling_feature_grad_gpu_launcheriiiiPKiPKfPf:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $280, %rsp
.cfi_def_cfa_offset 336
movl %ecx, 12(%rsp)
movq %r8, 16(%rsp)
movq %r9, 24(%rsp)
movq 336(%rsp), %r14
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
testl %edi, %edi
je .L41
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movl %esi, %eax
imull %edx, %eax
testl %eax, %eax
jne .L42
.L41:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L40:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L57
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
movl %edi, %r15d
imull %esi, %r15d
leaq 72(%rsp), %rdi
call cudaGetDevice@PLT
testl %eax, %eax
je .L58
.L44:
movl %r13d, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
leal -1(%r15,%r13), %eax
cltd
idivl %r13d
movl %eax, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 100(%rsp), %rdx
movl $1, %ecx
movq 88(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L40
subq $8, %rsp
.cfi_def_cfa_offset 344
pushq %r14
.cfi_def_cfa_offset 352
movq 40(%rsp), %r9
movq 32(%rsp), %r8
movl 28(%rsp), %ecx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z68__device_stub__Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPfiiiiPKiPKfPf
addq $16, %rsp
.cfi_def_cfa_offset 336
jmp .L40
.L58:
leaq 76(%rsp), %rdi
movl 72(%rsp), %edx
movl $39, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L44
leaq 80(%rsp), %rdi
movl 72(%rsp), %edx
movl $10, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L44
leaq 84(%rsp), %rdi
movl 72(%rsp), %edx
movl $1, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L44
leaq 88(%rsp), %rdi
movl 72(%rsp), %edx
movl $16, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L44
leaq 112(%rsp), %rdi
leaq _Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf(%rip), %rsi
call cudaFuncGetAttributes@PLT
testl %eax, %eax
jne .L44
movl 136(%rsp), %eax
movl 76(%rsp), %ecx
movl %ecx, %edi
movl 80(%rsp), %ecx
movl %r15d, %edx
testl %r15d, %r15d
jne .L45
movl 84(%rsp), %edx
.L45:
movl 84(%rsp), %esi
cmpl %esi, %eax
cmovg %esi, %eax
cmpl %edx, %eax
cmovle %eax, %edx
movl %edx, %esi
leal -1(%rcx,%rdx), %eax
cltd
idivl %ecx
imull %ecx, %eax
testl %eax, %eax
jle .L51
movl $0, 32(%rsp)
movl $0, %edx
movl %r15d, 36(%rsp)
movl %ecx, %r15d
movl %r13d, 60(%rsp)
movl %esi, %r13d
movl %ebx, 40(%rsp)
movl %eax, %ebx
movl %ebp, 44(%rsp)
movl %r12d, 56(%rsp)
movl %edx, %r12d
movq %r14, 48(%rsp)
movl %edi, %r14d
jmp .L47
.L46:
cmpl %r12d, %r14d
je .L53
subl %r15d, %ebx
testl %ebx, %ebx
jle .L59
.L47:
cmpl %ebx, %r13d
movl %ebx, %ebp
cmovle %r13d, %ebp
leaq 100(%rsp), %rdi
movl $0, %r8d
movl $0, %ecx
movl %ebp, %edx
leaq _Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf(%rip), %rsi
call cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags@PLT
testl %eax, %eax
jne .L55
movl %ebp, %eax
imull 100(%rsp), %eax
cmpl %eax, %r12d
jge .L46
movl %eax, %r12d
movl %ebp, 32(%rsp)
jmp .L46
.L59:
movl 36(%rsp), %r15d
movl 40(%rsp), %ebx
movl 44(%rsp), %ebp
movl 56(%rsp), %r12d
movq 48(%rsp), %r14
movl 32(%rsp), %r13d
jmp .L44
.L51:
movl $0, %r13d
jmp .L44
.L53:
movl 36(%rsp), %r15d
movl 40(%rsp), %ebx
movl 44(%rsp), %ebp
movl 56(%rsp), %r12d
movq 48(%rsp), %r14
movl 32(%rsp), %r13d
jmp .L44
.L55:
movl 36(%rsp), %r15d
movl 60(%rsp), %r13d
movl 40(%rsp), %ebx
movl 44(%rsp), %ebp
movl 56(%rsp), %r12d
movq 48(%rsp), %r14
jmp .L44
.L57:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size _Z40voxel_sampling_feature_grad_gpu_launcheriiiiPKiPKfPf, .-_Z40voxel_sampling_feature_grad_gpu_launcheriiiiPKiPKfPf
.section .rodata.str1.8
.align 8
.LC2:
.string "_Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf"
.align 8
.LC3:
.string "_Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "voxel_sampling_feature.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z48__device_stub__voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf # -- Begin function _Z48__device_stub__voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf
.p2align 4, 0x90
.type _Z48__device_stub__voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf,@function
_Z48__device_stub__voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf: # @_Z48__device_stub__voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movss %xmm0, 16(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 88(%rsp)
movq %r9, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rax
movq %rax, 144(%rsp)
leaq 176(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z48__device_stub__voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf, .Lfunc_end0-_Z48__device_stub__voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf
.cfi_endproc
# -- End function
.globl _Z53__device_stub__voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf # -- Begin function _Z53__device_stub__voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf
.p2align 4, 0x90
.type _Z53__device_stub__voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf,@function
_Z53__device_stub__voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf: # @_Z53__device_stub__voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _Z53__device_stub__voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf, .Lfunc_end1-_Z53__device_stub__voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf
.cfi_endproc
# -- End function
.globl _Z35voxel_sampling_feature_gpu_launcheriiifiPKfPKiPf # -- Begin function _Z35voxel_sampling_feature_gpu_launcheriiifiPKfPKiPf
.p2align 4, 0x90
.type _Z35voxel_sampling_feature_gpu_launcheriiifiPKfPKiPf,@function
_Z35voxel_sampling_feature_gpu_launcheriiifiPKfPKiPf: # @_Z35voxel_sampling_feature_gpu_launcheriiifiPKfPKiPf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
imull %edi, %ebx
testl %ebx, %ebx
jle .LBB2_4
# %bb.1:
movq %r8, %r14
movl %ecx, %ebp
movl %edx, %r12d
movl %esi, %r15d
movl %edi, %r13d
movss %xmm0, 4(%rsp) # 4-byte Spill
movq %r9, 40(%rsp) # 8-byte Spill
movq 256(%rsp), %rax
movq %rax, 32(%rsp) # 8-byte Spill
imull %esi, %ebx
leaq 124(%rsp), %rdi
leaq 8(%rsp), %rsi
movl $_Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf, %edx
xorl %ecx, %ecx
movl %ebx, %r8d
callq hipOccupancyMaxPotentialBlockSize
movl 8(%rsp), %ecx
leal (%rbx,%rcx), %eax
decl %eax
cltd
idivl %ecx
# kill: def $eax killed $eax def $rax
movabsq $4294967296, %rdx # imm = 0x100000000
leaq (%rax,%rdx), %rdi
orq %rdx, %rcx
movl $1, %esi
movq %rcx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_3
# %bb.2:
movl %r13d, 28(%rsp)
movl %r12d, 24(%rsp)
movl %r15d, 20(%rsp)
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 16(%rsp)
movl %ebp, 12(%rsp)
movq %r14, 112(%rsp)
movq 40(%rsp), %rax # 8-byte Reload
movq %rax, 104(%rsp)
movq 32(%rsp), %rax # 8-byte Reload
movq %rax, 96(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rax
movq %rax, 184(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_3:
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_4:
.cfi_def_cfa_offset 256
movl $.Lstr, %edi
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end2:
.size _Z35voxel_sampling_feature_gpu_launcheriiifiPKfPKiPf, .Lfunc_end2-_Z35voxel_sampling_feature_gpu_launcheriiifiPKfPKiPf
.cfi_endproc
# -- End function
.globl _Z40voxel_sampling_feature_grad_gpu_launcheriiiiPKiPKfPf # -- Begin function _Z40voxel_sampling_feature_grad_gpu_launcheriiiiPKiPKfPf
.p2align 4, 0x90
.type _Z40voxel_sampling_feature_grad_gpu_launcheriiiiPKiPKfPf,@function
_Z40voxel_sampling_feature_grad_gpu_launcheriiiiPKiPKfPf: # @_Z40voxel_sampling_feature_grad_gpu_launcheriiiiPKiPKfPf
.cfi_startproc
# %bb.0:
testl %edi, %edi
je .LBB3_5
# %bb.1:
movl %edx, %eax
imull %esi, %eax
testl %eax, %eax
je .LBB3_5
# %bb.2:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r13d
movl %ecx, %ebp
movq %r8, %r12
movq %r9, 40(%rsp) # 8-byte Spill
movq 240(%rsp), %rax
movq %rax, 32(%rsp) # 8-byte Spill
movl %esi, %r14d
movl %esi, %ebx
movl %edi, %r15d
imull %edi, %ebx
leaq 124(%rsp), %rdi
leaq 12(%rsp), %rsi
movl $_Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf, %edx
xorl %ecx, %ecx
movl %ebx, %r8d
callq hipOccupancyMaxPotentialBlockSize
movl 12(%rsp), %ecx
leal (%rbx,%rcx), %eax
decl %eax
cltd
idivl %ecx
# kill: def $eax killed $eax def $rax
movabsq $4294967296, %rdx # imm = 0x100000000
leaq (%rax,%rdx), %rdi
orq %rdx, %rcx
movl $1, %esi
movq %rcx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movl %r15d, 28(%rsp)
movl %r14d, 24(%rsp)
movl %r13d, 20(%rsp)
movl %ebp, 16(%rsp)
movq %r12, 112(%rsp)
movq 40(%rsp), %rax # 8-byte Reload
movq %rax, 104(%rsp)
movq 32(%rsp), %rax # 8-byte Reload
movq %rax, 96(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 112(%rsp), %rax
movq %rax, 160(%rsp)
leaq 104(%rsp), %rax
movq %rax, 168(%rsp)
leaq 96(%rsp), %rax
movq %rax, 176(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_5:
.cfi_restore %rbx
.cfi_restore %rbp
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
movl $.Lstr.1, %edi
jmp puts@PLT # TAILCALL
.Lfunc_end3:
.size _Z40voxel_sampling_feature_grad_gpu_launcheriiiiPKiPKfPf, .Lfunc_end3-_Z40voxel_sampling_feature_grad_gpu_launcheriiiiPKiPKfPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf,@object # @_Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf
.section .rodata,"a",@progbits
.globl _Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf
.p2align 3, 0x0
_Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf:
.quad _Z48__device_stub__voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf
.size _Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf, 8
.type _Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf,@object # @_Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf
.globl _Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf
.p2align 3, 0x0
_Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf:
.quad _Z53__device_stub__voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf
.size _Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf"
.size .L__unnamed_1, 51
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf"
.size .L__unnamed_2, 55
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "VoxelSampleFeatureOp ERROR: Invalid CUDA input dimensions."
.size .Lstr, 59
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "VoxelSampleGradOp ERROR: Invalid CUDA input dimensions."
.size .Lstr.1, 56
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z48__device_stub__voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf
.addrsig_sym _Z53__device_stub__voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z33voxel_sampling_feature_gpu_kerneliiifiPKfPKiPf
.addrsig_sym _Z38voxel_sampling_feature_grad_gpu_kerneliiiiPKiPKfPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__ void addElement(int *a,int *b,int *t)
{
int v = threadIdx.y;
int n = v*blockDim.x+threadIdx.x;
t[n] = a[n]+b[n];
}
__global__ void addCol(int *a , int *b , int *t)
{
int lp =0;
int index = threadIdx.x;
for(lp = 0 ;lp<blockDim.x;lp++)
{
t[index] = a[index]+b[index];
index += blockDim.x;
}
}
__global__ void addRow(int *a , int *b , int *t)
{
int lp =0;
int index = threadIdx.x*blockDim.x;
for(lp = 0 ;lp<blockDim.x;lp++)
{
t[index] = a[index] + b[index];
index++;
}
}
int main(void)
{
int *a,*b,*t,n,i,j;
int *d_a,*d_b,*d_t;
printf("Enter the value of n: ");
scanf("%d",&n);
int size = sizeof(int)*n*n;
a = (int*)malloc(n*n*sizeof(int));
b = (int*)malloc(n*n*sizeof(int));
t = (int*)malloc(n*n*sizeof(int));
printf("Enter input matrix 1 : \n");
for(i = 0;i<n*n;i++)
scanf("%d",&a[i]);
printf("Enter input matrix 2 : \n");
for(i = 0;i<n*n;i++)
scanf("%d",&b[i]);
cudaMalloc((void**)&d_a,size);
cudaMalloc((void**)&d_b,size);
cudaMalloc((void**)&d_t,size);
cudaMemcpy(d_a,a,size,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,size,cudaMemcpyHostToDevice);
printf("Enter 1 for Row \n 2 for Column \n 3 for Element \n");
int ch;
scanf("%d",&ch);
if(ch == 1)
{
dim3 block(n,1);
dim3 grid(1,1);
addRow<<<grid,block>>>(d_a,d_b,d_t);
}
if(ch == 2)
{
dim3 block(n,1);
dim3 grid(1,1);
addCol<<<grid,block>>>(d_a,d_b,d_t);
}
if(ch == 3)
{
dim3 block(n,n);
dim3 grid(1,1);
addElement<<<grid,block>>>(d_a,d_b,d_t);
}
cudaMemcpy(t,d_t,size,cudaMemcpyDeviceToHost);
printf("Result vector is :\n");
for(i = 0;i<n;i++)
{
for(j = 0;j<n;j++)
printf("%d ",t[i*n+j]);
printf("\n");
}
getchar();
cudaFree(d_a);
cudaFree(d_t);
return 0;
} | .file "tmpxft_001bc5e9_00000000-6_second.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10addElementPiS_S_PiS_S_
.type _Z34__device_stub__Z10addElementPiS_S_PiS_S_, @function
_Z34__device_stub__Z10addElementPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10addElementPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z10addElementPiS_S_PiS_S_, .-_Z34__device_stub__Z10addElementPiS_S_PiS_S_
.globl _Z10addElementPiS_S_
.type _Z10addElementPiS_S_, @function
_Z10addElementPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10addElementPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10addElementPiS_S_, .-_Z10addElementPiS_S_
.globl _Z29__device_stub__Z6addColPiS_S_PiS_S_
.type _Z29__device_stub__Z6addColPiS_S_PiS_S_, @function
_Z29__device_stub__Z6addColPiS_S_PiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6addColPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z29__device_stub__Z6addColPiS_S_PiS_S_, .-_Z29__device_stub__Z6addColPiS_S_PiS_S_
.globl _Z6addColPiS_S_
.type _Z6addColPiS_S_, @function
_Z6addColPiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6addColPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6addColPiS_S_, .-_Z6addColPiS_S_
.globl _Z29__device_stub__Z6addRowPiS_S_PiS_S_
.type _Z29__device_stub__Z6addRowPiS_S_PiS_S_, @function
_Z29__device_stub__Z6addRowPiS_S_PiS_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6addRowPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z29__device_stub__Z6addRowPiS_S_PiS_S_, .-_Z29__device_stub__Z6addRowPiS_S_PiS_S_
.globl _Z6addRowPiS_S_
.type _Z6addRowPiS_S_, @function
_Z6addRowPiS_S_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6addRowPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z6addRowPiS_S_, .-_Z6addRowPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter the value of n: "
.LC1:
.string "%d"
.LC2:
.string "Enter input matrix 1 : \n"
.LC3:
.string "Enter input matrix 2 : \n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Enter 1 for Row \n 2 for Column \n 3 for Element \n"
.section .rodata.str1.1
.LC5:
.string "Result vector is :\n"
.LC6:
.string "%d "
.LC7:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 16(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 16(%rsp), %eax
movl %eax, %r13d
imull %eax, %r13d
sall $2, %r13d
imull %eax, %eax
movslq %eax, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 16(%rsp), %eax
imull %eax, %eax
testl %eax, %eax
jle .L28
movq %r14, %r12
movl $0, %ebp
leaq .LC1(%rip), %r15
.L29:
movq %r12, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebp
movl 16(%rsp), %eax
addq $4, %r12
imull %eax, %eax
cmpl %ebp, %eax
jg .L29
.L28:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 16(%rsp), %eax
imull %eax, %eax
testl %eax, %eax
jle .L30
movq 8(%rsp), %r12
movl $0, %ebp
leaq .LC1(%rip), %r15
.L31:
movq %r12, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebp
movl 16(%rsp), %eax
addq $4, %r12
imull %eax, %eax
cmpl %ebp, %eax
jg .L31
.L30:
movslq %r13d, %r13
leaq 24(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq 8(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 20(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
cmpl $1, 20(%rsp)
je .L51
.L32:
cmpl $2, 20(%rsp)
je .L52
.L34:
cmpl $3, 20(%rsp)
je .L53
.L36:
movl $2, %ecx
movq %r13, %rdx
movq 40(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r12d
leaq .LC6(%rip), %r13
leaq .LC7(%rip), %r14
cmpl $0, 16(%rsp)
jg .L38
.L39:
movq stdin(%rip), %rdi
call getc@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L54
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
movl 16(%rsp), %eax
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L32
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z29__device_stub__Z6addRowPiS_S_PiS_S_
jmp .L32
.L52:
movl 16(%rsp), %eax
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L34
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z29__device_stub__Z6addColPiS_S_PiS_S_
jmp .L34
.L53:
movl 16(%rsp), %eax
movl %eax, 48(%rsp)
movl %eax, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L36
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z34__device_stub__Z10addElementPiS_S_PiS_S_
jmp .L36
.L40:
imull %r12d, %eax
addl %ebp, %eax
cltq
movl (%rbx,%rax,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
movl 16(%rsp), %eax
cmpl %ebp, %eax
jg .L40
.L41:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r12d
cmpl %r12d, 16(%rsp)
jle .L39
.L38:
movl 16(%rsp), %eax
movl $0, %ebp
testl %eax, %eax
jg .L40
jmp .L41
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z6addRowPiS_S_"
.LC9:
.string "_Z6addColPiS_S_"
.LC10:
.string "_Z10addElementPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z6addRowPiS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z6addColPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z10addElementPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__ void addElement(int *a,int *b,int *t)
{
int v = threadIdx.y;
int n = v*blockDim.x+threadIdx.x;
t[n] = a[n]+b[n];
}
__global__ void addCol(int *a , int *b , int *t)
{
int lp =0;
int index = threadIdx.x;
for(lp = 0 ;lp<blockDim.x;lp++)
{
t[index] = a[index]+b[index];
index += blockDim.x;
}
}
__global__ void addRow(int *a , int *b , int *t)
{
int lp =0;
int index = threadIdx.x*blockDim.x;
for(lp = 0 ;lp<blockDim.x;lp++)
{
t[index] = a[index] + b[index];
index++;
}
}
int main(void)
{
int *a,*b,*t,n,i,j;
int *d_a,*d_b,*d_t;
printf("Enter the value of n: ");
scanf("%d",&n);
int size = sizeof(int)*n*n;
a = (int*)malloc(n*n*sizeof(int));
b = (int*)malloc(n*n*sizeof(int));
t = (int*)malloc(n*n*sizeof(int));
printf("Enter input matrix 1 : \n");
for(i = 0;i<n*n;i++)
scanf("%d",&a[i]);
printf("Enter input matrix 2 : \n");
for(i = 0;i<n*n;i++)
scanf("%d",&b[i]);
cudaMalloc((void**)&d_a,size);
cudaMalloc((void**)&d_b,size);
cudaMalloc((void**)&d_t,size);
cudaMemcpy(d_a,a,size,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,size,cudaMemcpyHostToDevice);
printf("Enter 1 for Row \n 2 for Column \n 3 for Element \n");
int ch;
scanf("%d",&ch);
if(ch == 1)
{
dim3 block(n,1);
dim3 grid(1,1);
addRow<<<grid,block>>>(d_a,d_b,d_t);
}
if(ch == 2)
{
dim3 block(n,1);
dim3 grid(1,1);
addCol<<<grid,block>>>(d_a,d_b,d_t);
}
if(ch == 3)
{
dim3 block(n,n);
dim3 grid(1,1);
addElement<<<grid,block>>>(d_a,d_b,d_t);
}
cudaMemcpy(t,d_t,size,cudaMemcpyDeviceToHost);
printf("Result vector is :\n");
for(i = 0;i<n;i++)
{
for(j = 0;j<n;j++)
printf("%d ",t[i*n+j]);
printf("\n");
}
getchar();
cudaFree(d_a);
cudaFree(d_t);
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__ void addElement(int *a,int *b,int *t)
{
int v = threadIdx.y;
int n = v*blockDim.x+threadIdx.x;
t[n] = a[n]+b[n];
}
__global__ void addCol(int *a , int *b , int *t)
{
int lp =0;
int index = threadIdx.x;
for(lp = 0 ;lp<blockDim.x;lp++)
{
t[index] = a[index]+b[index];
index += blockDim.x;
}
}
__global__ void addRow(int *a , int *b , int *t)
{
int lp =0;
int index = threadIdx.x*blockDim.x;
for(lp = 0 ;lp<blockDim.x;lp++)
{
t[index] = a[index] + b[index];
index++;
}
}
int main(void)
{
int *a,*b,*t,n,i,j;
int *d_a,*d_b,*d_t;
printf("Enter the value of n: ");
scanf("%d",&n);
int size = sizeof(int)*n*n;
a = (int*)malloc(n*n*sizeof(int));
b = (int*)malloc(n*n*sizeof(int));
t = (int*)malloc(n*n*sizeof(int));
printf("Enter input matrix 1 : \n");
for(i = 0;i<n*n;i++)
scanf("%d",&a[i]);
printf("Enter input matrix 2 : \n");
for(i = 0;i<n*n;i++)
scanf("%d",&b[i]);
hipMalloc((void**)&d_a,size);
hipMalloc((void**)&d_b,size);
hipMalloc((void**)&d_t,size);
hipMemcpy(d_a,a,size,hipMemcpyHostToDevice);
hipMemcpy(d_b,b,size,hipMemcpyHostToDevice);
printf("Enter 1 for Row \n 2 for Column \n 3 for Element \n");
int ch;
scanf("%d",&ch);
if(ch == 1)
{
dim3 block(n,1);
dim3 grid(1,1);
addRow<<<grid,block>>>(d_a,d_b,d_t);
}
if(ch == 2)
{
dim3 block(n,1);
dim3 grid(1,1);
addCol<<<grid,block>>>(d_a,d_b,d_t);
}
if(ch == 3)
{
dim3 block(n,n);
dim3 grid(1,1);
addElement<<<grid,block>>>(d_a,d_b,d_t);
}
hipMemcpy(t,d_t,size,hipMemcpyDeviceToHost);
printf("Result vector is :\n");
for(i = 0;i<n;i++)
{
for(j = 0;j<n;j++)
printf("%d ",t[i*n+j]);
printf("\n");
}
getchar();
hipFree(d_a);
hipFree(d_t);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__ void addElement(int *a,int *b,int *t)
{
int v = threadIdx.y;
int n = v*blockDim.x+threadIdx.x;
t[n] = a[n]+b[n];
}
__global__ void addCol(int *a , int *b , int *t)
{
int lp =0;
int index = threadIdx.x;
for(lp = 0 ;lp<blockDim.x;lp++)
{
t[index] = a[index]+b[index];
index += blockDim.x;
}
}
__global__ void addRow(int *a , int *b , int *t)
{
int lp =0;
int index = threadIdx.x*blockDim.x;
for(lp = 0 ;lp<blockDim.x;lp++)
{
t[index] = a[index] + b[index];
index++;
}
}
int main(void)
{
int *a,*b,*t,n,i,j;
int *d_a,*d_b,*d_t;
printf("Enter the value of n: ");
scanf("%d",&n);
int size = sizeof(int)*n*n;
a = (int*)malloc(n*n*sizeof(int));
b = (int*)malloc(n*n*sizeof(int));
t = (int*)malloc(n*n*sizeof(int));
printf("Enter input matrix 1 : \n");
for(i = 0;i<n*n;i++)
scanf("%d",&a[i]);
printf("Enter input matrix 2 : \n");
for(i = 0;i<n*n;i++)
scanf("%d",&b[i]);
hipMalloc((void**)&d_a,size);
hipMalloc((void**)&d_b,size);
hipMalloc((void**)&d_t,size);
hipMemcpy(d_a,a,size,hipMemcpyHostToDevice);
hipMemcpy(d_b,b,size,hipMemcpyHostToDevice);
printf("Enter 1 for Row \n 2 for Column \n 3 for Element \n");
int ch;
scanf("%d",&ch);
if(ch == 1)
{
dim3 block(n,1);
dim3 grid(1,1);
addRow<<<grid,block>>>(d_a,d_b,d_t);
}
if(ch == 2)
{
dim3 block(n,1);
dim3 grid(1,1);
addCol<<<grid,block>>>(d_a,d_b,d_t);
}
if(ch == 3)
{
dim3 block(n,n);
dim3 grid(1,1);
addElement<<<grid,block>>>(d_a,d_b,d_t);
}
hipMemcpy(t,d_t,size,hipMemcpyDeviceToHost);
printf("Result vector is :\n");
for(i = 0;i<n;i++)
{
for(j = 0;j<n;j++)
printf("%d ",t[i*n+j]);
printf("\n");
}
getchar();
hipFree(d_a);
hipFree(d_t);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10addElementPiS_S_
.globl _Z10addElementPiS_S_
.p2align 8
.type _Z10addElementPiS_S_,@function
_Z10addElementPiS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_u32_u24_e32 v1, s2, v1
v_add_lshl_u32 v0, v1, v0, 2
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10addElementPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10addElementPiS_S_, .Lfunc_end0-_Z10addElementPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6addColPiS_S_
.globl _Z6addColPiS_S_
.p2align 8
.type _Z6addColPiS_S_,@function
_Z6addColPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
v_cmp_eq_u16_e64 s3, s2, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB1_3
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_and_b32 s2, 0xffff, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s3, s2
.p2align 6
.LBB1_2:
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s3, 0
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_add_nc_u32_e32 v0, s2, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s0, v1
global_load_b32 v3, v[3:4], off
global_load_b32 v4, v[5:6], off
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
global_store_b32 v[1:2], v3, off
s_cbranch_scc1 .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6addColPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z6addColPiS_S_, .Lfunc_end1-_Z6addColPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6addRowPiS_S_
.globl _Z6addRowPiS_S_
.p2align 8
.type _Z6addRowPiS_S_,@function
_Z6addRowPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
v_cmp_eq_u16_e64 s3, s2, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB2_3
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
s_and_b32 s0, 0xffff, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_u32_u24_e32 v0, s0, v0
v_lshlrev_b32_e32 v4, 2, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s1, s4, v4
v_add_co_ci_u32_e64 v1, null, s5, 0, s1
v_add_co_u32 v2, s1, s6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, null, s7, 0, s1
v_add_co_u32 v4, s1, s8, v4
v_add_co_ci_u32_e64 v5, null, s9, 0, s1
.p2align 6
.LBB2_2:
global_load_b32 v6, v[0:1], off
global_load_b32 v7, v[2:3], off
v_add_co_u32 v0, vcc_lo, v0, 4
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s0, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v6, v7, v6
global_store_b32 v[4:5], v6, off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_cbranch_scc1 .LBB2_2
.LBB2_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6addRowPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z6addRowPiS_S_, .Lfunc_end2-_Z6addRowPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10addElementPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z10addElementPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6addColPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z6addColPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6addRowPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z6addRowPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__ void addElement(int *a,int *b,int *t)
{
int v = threadIdx.y;
int n = v*blockDim.x+threadIdx.x;
t[n] = a[n]+b[n];
}
__global__ void addCol(int *a , int *b , int *t)
{
int lp =0;
int index = threadIdx.x;
for(lp = 0 ;lp<blockDim.x;lp++)
{
t[index] = a[index]+b[index];
index += blockDim.x;
}
}
__global__ void addRow(int *a , int *b , int *t)
{
int lp =0;
int index = threadIdx.x*blockDim.x;
for(lp = 0 ;lp<blockDim.x;lp++)
{
t[index] = a[index] + b[index];
index++;
}
}
int main(void)
{
int *a,*b,*t,n,i,j;
int *d_a,*d_b,*d_t;
printf("Enter the value of n: ");
scanf("%d",&n);
int size = sizeof(int)*n*n;
a = (int*)malloc(n*n*sizeof(int));
b = (int*)malloc(n*n*sizeof(int));
t = (int*)malloc(n*n*sizeof(int));
printf("Enter input matrix 1 : \n");
for(i = 0;i<n*n;i++)
scanf("%d",&a[i]);
printf("Enter input matrix 2 : \n");
for(i = 0;i<n*n;i++)
scanf("%d",&b[i]);
hipMalloc((void**)&d_a,size);
hipMalloc((void**)&d_b,size);
hipMalloc((void**)&d_t,size);
hipMemcpy(d_a,a,size,hipMemcpyHostToDevice);
hipMemcpy(d_b,b,size,hipMemcpyHostToDevice);
printf("Enter 1 for Row \n 2 for Column \n 3 for Element \n");
int ch;
scanf("%d",&ch);
if(ch == 1)
{
dim3 block(n,1);
dim3 grid(1,1);
addRow<<<grid,block>>>(d_a,d_b,d_t);
}
if(ch == 2)
{
dim3 block(n,1);
dim3 grid(1,1);
addCol<<<grid,block>>>(d_a,d_b,d_t);
}
if(ch == 3)
{
dim3 block(n,n);
dim3 grid(1,1);
addElement<<<grid,block>>>(d_a,d_b,d_t);
}
hipMemcpy(t,d_t,size,hipMemcpyDeviceToHost);
printf("Result vector is :\n");
for(i = 0;i<n;i++)
{
for(j = 0;j<n;j++)
printf("%d ",t[i*n+j]);
printf("\n");
}
getchar();
hipFree(d_a);
hipFree(d_t);
return 0;
} | .text
.file "second.hip"
.globl _Z25__device_stub__addElementPiS_S_ # -- Begin function _Z25__device_stub__addElementPiS_S_
.p2align 4, 0x90
.type _Z25__device_stub__addElementPiS_S_,@function
_Z25__device_stub__addElementPiS_S_: # @_Z25__device_stub__addElementPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10addElementPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__addElementPiS_S_, .Lfunc_end0-_Z25__device_stub__addElementPiS_S_
.cfi_endproc
# -- End function
.globl _Z21__device_stub__addColPiS_S_ # -- Begin function _Z21__device_stub__addColPiS_S_
.p2align 4, 0x90
.type _Z21__device_stub__addColPiS_S_,@function
_Z21__device_stub__addColPiS_S_: # @_Z21__device_stub__addColPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6addColPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z21__device_stub__addColPiS_S_, .Lfunc_end1-_Z21__device_stub__addColPiS_S_
.cfi_endproc
# -- End function
.globl _Z21__device_stub__addRowPiS_S_ # -- Begin function _Z21__device_stub__addRowPiS_S_
.p2align 4, 0x90
.type _Z21__device_stub__addRowPiS_S_,@function
_Z21__device_stub__addRowPiS_S_: # @_Z21__device_stub__addRowPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6addRowPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z21__device_stub__addRowPiS_S_, .Lfunc_end2-_Z21__device_stub__addRowPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 8(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 8(%rsp), %ebp
imull %ebp, %ebp
leaq (,%rbp,4), %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r13
movq %rbx, %rdi
callq malloc
movq %rax, %r12
movq %rbx, %rdi
callq malloc
movq %rax, %rbx
movl $.Lstr, %edi
callq puts@PLT
cmpl $0, 8(%rsp)
je .LBB3_3
# %bb.1: # %.lr.ph.preheader
movq %r13, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %r14, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r15
movl 8(%rsp), %eax
imull %eax, %eax
addq $4, %r14
cmpq %rax, %r15
jb .LBB3_2
.LBB3_3: # %._crit_edge
shll $2, %ebp
movl $.Lstr.1, %edi
callq puts@PLT
cmpl $0, 8(%rsp)
je .LBB3_6
# %bb.4: # %.lr.ph77.preheader
movq %r12, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_5: # %.lr.ph77
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %r14, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r15
movl 8(%rsp), %eax
imull %eax, %eax
addq $4, %r14
cmpq %rax, %r15
jb .LBB3_5
.LBB3_6: # %._crit_edge78
movabsq $4294967297, %r15 # imm = 0x100000001
movslq %ebp, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 104(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 104(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
leaq 12(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
cmpl $1, 12(%rsp)
jne .LBB3_9
# %bb.7:
movl 8(%rsp), %eax
leaq (%r15,%rax), %rdx
decq %rdx
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB3_8
.LBB3_9:
cmpl $2, 12(%rsp)
jne .LBB3_12
.LBB3_10:
movl 8(%rsp), %eax
leaq (%r15,%rax), %rdx
decq %rdx
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_12
# %bb.11:
movq 24(%rsp), %rax
movq 104(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rdx, 80(%rsp)
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6addColPiS_S_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_12
.LBB3_8:
movq 24(%rsp), %rax
movq 104(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rdx, 80(%rsp)
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6addRowPiS_S_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
cmpl $2, 12(%rsp)
je .LBB3_10
.LBB3_12:
cmpl $3, 12(%rsp)
jne .LBB3_15
# %bb.13:
movl 8(%rsp), %eax
movq %rax, %rdx
shlq $32, %rdx
orq %rax, %rdx
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_15
# %bb.14:
movq 24(%rsp), %rax
movq 104(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rdx, 80(%rsp)
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10addElementPiS_S_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_15:
movq 16(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.3, %edi
callq puts@PLT
cmpl $0, 8(%rsp)
jle .LBB3_21
# %bb.16: # %.preheader.preheader
xorl %ebp, %ebp
jmp .LBB3_17
.p2align 4, 0x90
.LBB3_20: # %._crit_edge81
# in Loop: Header=BB3_17 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl 8(%rsp), %ebp
jge .LBB3_21
.LBB3_17: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_19 Depth 2
movl 8(%rsp), %eax
testl %eax, %eax
jle .LBB3_20
# %bb.18: # %.lr.ph80.preheader
# in Loop: Header=BB3_17 Depth=1
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_19: # %.lr.ph80
# Parent Loop BB3_17 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %eax
cltq
addq %r14, %rax
movl (%rbx,%rax,4), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl 8(%rsp), %eax
incq %r14
cmpl %eax, %r14d
jl .LBB3_19
jmp .LBB3_20
.LBB3_21: # %._crit_edge83
movq stdin(%rip), %rdi
callq getc
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10addElementPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6addColPiS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6addRowPiS_S_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10addElementPiS_S_,@object # @_Z10addElementPiS_S_
.section .rodata,"a",@progbits
.globl _Z10addElementPiS_S_
.p2align 3, 0x0
_Z10addElementPiS_S_:
.quad _Z25__device_stub__addElementPiS_S_
.size _Z10addElementPiS_S_, 8
.type _Z6addColPiS_S_,@object # @_Z6addColPiS_S_
.globl _Z6addColPiS_S_
.p2align 3, 0x0
_Z6addColPiS_S_:
.quad _Z21__device_stub__addColPiS_S_
.size _Z6addColPiS_S_, 8
.type _Z6addRowPiS_S_,@object # @_Z6addRowPiS_S_
.globl _Z6addRowPiS_S_
.p2align 3, 0x0
_Z6addRowPiS_S_:
.quad _Z21__device_stub__addRowPiS_S_
.size _Z6addRowPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter the value of n: "
.size .L.str, 23
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d "
.size .L.str.6, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10addElementPiS_S_"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z6addColPiS_S_"
.size .L__unnamed_2, 16
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z6addRowPiS_S_"
.size .L__unnamed_3, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Enter input matrix 1 : "
.size .Lstr, 24
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Enter input matrix 2 : "
.size .Lstr.1, 24
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Enter 1 for Row \n 2 for Column \n 3 for Element "
.size .Lstr.2, 48
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Result vector is :"
.size .Lstr.3, 19
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__addElementPiS_S_
.addrsig_sym _Z21__device_stub__addColPiS_S_
.addrsig_sym _Z21__device_stub__addRowPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10addElementPiS_S_
.addrsig_sym _Z6addColPiS_S_
.addrsig_sym _Z6addRowPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001bc5e9_00000000-6_second.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10addElementPiS_S_PiS_S_
.type _Z34__device_stub__Z10addElementPiS_S_PiS_S_, @function
_Z34__device_stub__Z10addElementPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10addElementPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z10addElementPiS_S_PiS_S_, .-_Z34__device_stub__Z10addElementPiS_S_PiS_S_
.globl _Z10addElementPiS_S_
.type _Z10addElementPiS_S_, @function
_Z10addElementPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10addElementPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10addElementPiS_S_, .-_Z10addElementPiS_S_
.globl _Z29__device_stub__Z6addColPiS_S_PiS_S_
.type _Z29__device_stub__Z6addColPiS_S_PiS_S_, @function
_Z29__device_stub__Z6addColPiS_S_PiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6addColPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z29__device_stub__Z6addColPiS_S_PiS_S_, .-_Z29__device_stub__Z6addColPiS_S_PiS_S_
.globl _Z6addColPiS_S_
.type _Z6addColPiS_S_, @function
_Z6addColPiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6addColPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6addColPiS_S_, .-_Z6addColPiS_S_
.globl _Z29__device_stub__Z6addRowPiS_S_PiS_S_
.type _Z29__device_stub__Z6addRowPiS_S_PiS_S_, @function
_Z29__device_stub__Z6addRowPiS_S_PiS_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6addRowPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z29__device_stub__Z6addRowPiS_S_PiS_S_, .-_Z29__device_stub__Z6addRowPiS_S_PiS_S_
.globl _Z6addRowPiS_S_
.type _Z6addRowPiS_S_, @function
_Z6addRowPiS_S_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6addRowPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z6addRowPiS_S_, .-_Z6addRowPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter the value of n: "
.LC1:
.string "%d"
.LC2:
.string "Enter input matrix 1 : \n"
.LC3:
.string "Enter input matrix 2 : \n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Enter 1 for Row \n 2 for Column \n 3 for Element \n"
.section .rodata.str1.1
.LC5:
.string "Result vector is :\n"
.LC6:
.string "%d "
.LC7:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 16(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 16(%rsp), %eax
movl %eax, %r13d
imull %eax, %r13d
sall $2, %r13d
imull %eax, %eax
movslq %eax, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 16(%rsp), %eax
imull %eax, %eax
testl %eax, %eax
jle .L28
movq %r14, %r12
movl $0, %ebp
leaq .LC1(%rip), %r15
.L29:
movq %r12, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebp
movl 16(%rsp), %eax
addq $4, %r12
imull %eax, %eax
cmpl %ebp, %eax
jg .L29
.L28:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 16(%rsp), %eax
imull %eax, %eax
testl %eax, %eax
jle .L30
movq 8(%rsp), %r12
movl $0, %ebp
leaq .LC1(%rip), %r15
.L31:
movq %r12, %rsi
movq %r15, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebp
movl 16(%rsp), %eax
addq $4, %r12
imull %eax, %eax
cmpl %ebp, %eax
jg .L31
.L30:
movslq %r13d, %r13
leaq 24(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq 8(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 20(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
cmpl $1, 20(%rsp)
je .L51
.L32:
cmpl $2, 20(%rsp)
je .L52
.L34:
cmpl $3, 20(%rsp)
je .L53
.L36:
movl $2, %ecx
movq %r13, %rdx
movq 40(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r12d
leaq .LC6(%rip), %r13
leaq .LC7(%rip), %r14
cmpl $0, 16(%rsp)
jg .L38
.L39:
movq stdin(%rip), %rdi
call getc@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L54
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
movl 16(%rsp), %eax
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L32
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z29__device_stub__Z6addRowPiS_S_PiS_S_
jmp .L32
.L52:
movl 16(%rsp), %eax
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L34
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z29__device_stub__Z6addColPiS_S_PiS_S_
jmp .L34
.L53:
movl 16(%rsp), %eax
movl %eax, 48(%rsp)
movl %eax, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L36
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z34__device_stub__Z10addElementPiS_S_PiS_S_
jmp .L36
.L40:
imull %r12d, %eax
addl %ebp, %eax
cltq
movl (%rbx,%rax,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
movl 16(%rsp), %eax
cmpl %ebp, %eax
jg .L40
.L41:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r12d
cmpl %r12d, 16(%rsp)
jle .L39
.L38:
movl 16(%rsp), %eax
movl $0, %ebp
testl %eax, %eax
jg .L40
jmp .L41
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z6addRowPiS_S_"
.LC9:
.string "_Z6addColPiS_S_"
.LC10:
.string "_Z10addElementPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z6addRowPiS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z6addColPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z10addElementPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "second.hip"
.globl _Z25__device_stub__addElementPiS_S_ # -- Begin function _Z25__device_stub__addElementPiS_S_
.p2align 4, 0x90
.type _Z25__device_stub__addElementPiS_S_,@function
_Z25__device_stub__addElementPiS_S_: # @_Z25__device_stub__addElementPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10addElementPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__addElementPiS_S_, .Lfunc_end0-_Z25__device_stub__addElementPiS_S_
.cfi_endproc
# -- End function
.globl _Z21__device_stub__addColPiS_S_ # -- Begin function _Z21__device_stub__addColPiS_S_
.p2align 4, 0x90
.type _Z21__device_stub__addColPiS_S_,@function
_Z21__device_stub__addColPiS_S_: # @_Z21__device_stub__addColPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6addColPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z21__device_stub__addColPiS_S_, .Lfunc_end1-_Z21__device_stub__addColPiS_S_
.cfi_endproc
# -- End function
.globl _Z21__device_stub__addRowPiS_S_ # -- Begin function _Z21__device_stub__addRowPiS_S_
.p2align 4, 0x90
.type _Z21__device_stub__addRowPiS_S_,@function
_Z21__device_stub__addRowPiS_S_: # @_Z21__device_stub__addRowPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6addRowPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z21__device_stub__addRowPiS_S_, .Lfunc_end2-_Z21__device_stub__addRowPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 8(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl 8(%rsp), %ebp
imull %ebp, %ebp
leaq (,%rbp,4), %rbx
movq %rbx, %rdi
callq malloc
movq %rax, %r13
movq %rbx, %rdi
callq malloc
movq %rax, %r12
movq %rbx, %rdi
callq malloc
movq %rax, %rbx
movl $.Lstr, %edi
callq puts@PLT
cmpl $0, 8(%rsp)
je .LBB3_3
# %bb.1: # %.lr.ph.preheader
movq %r13, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %r14, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r15
movl 8(%rsp), %eax
imull %eax, %eax
addq $4, %r14
cmpq %rax, %r15
jb .LBB3_2
.LBB3_3: # %._crit_edge
shll $2, %ebp
movl $.Lstr.1, %edi
callq puts@PLT
cmpl $0, 8(%rsp)
je .LBB3_6
# %bb.4: # %.lr.ph77.preheader
movq %r12, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_5: # %.lr.ph77
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %r14, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r15
movl 8(%rsp), %eax
imull %eax, %eax
addq $4, %r14
cmpq %rax, %r15
jb .LBB3_5
.LBB3_6: # %._crit_edge78
movabsq $4294967297, %r15 # imm = 0x100000001
movslq %ebp, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 104(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 104(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl $.Lstr.2, %edi
callq puts@PLT
leaq 12(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
cmpl $1, 12(%rsp)
jne .LBB3_9
# %bb.7:
movl 8(%rsp), %eax
leaq (%r15,%rax), %rdx
decq %rdx
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB3_8
.LBB3_9:
cmpl $2, 12(%rsp)
jne .LBB3_12
.LBB3_10:
movl 8(%rsp), %eax
leaq (%r15,%rax), %rdx
decq %rdx
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_12
# %bb.11:
movq 24(%rsp), %rax
movq 104(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rdx, 80(%rsp)
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6addColPiS_S_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_12
.LBB3_8:
movq 24(%rsp), %rax
movq 104(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rdx, 80(%rsp)
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6addRowPiS_S_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
cmpl $2, 12(%rsp)
je .LBB3_10
.LBB3_12:
cmpl $3, 12(%rsp)
jne .LBB3_15
# %bb.13:
movl 8(%rsp), %eax
movq %rax, %rdx
shlq $32, %rdx
orq %rax, %rdx
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_15
# %bb.14:
movq 24(%rsp), %rax
movq 104(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movq %rdx, 80(%rsp)
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10addElementPiS_S_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_15:
movq 16(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.3, %edi
callq puts@PLT
cmpl $0, 8(%rsp)
jle .LBB3_21
# %bb.16: # %.preheader.preheader
xorl %ebp, %ebp
jmp .LBB3_17
.p2align 4, 0x90
.LBB3_20: # %._crit_edge81
# in Loop: Header=BB3_17 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl 8(%rsp), %ebp
jge .LBB3_21
.LBB3_17: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_19 Depth 2
movl 8(%rsp), %eax
testl %eax, %eax
jle .LBB3_20
# %bb.18: # %.lr.ph80.preheader
# in Loop: Header=BB3_17 Depth=1
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_19: # %.lr.ph80
# Parent Loop BB3_17 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %eax
cltq
addq %r14, %rax
movl (%rbx,%rax,4), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl 8(%rsp), %eax
incq %r14
cmpl %eax, %r14d
jl .LBB3_19
jmp .LBB3_20
.LBB3_21: # %._crit_edge83
movq stdin(%rip), %rdi
callq getc
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10addElementPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6addColPiS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6addRowPiS_S_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10addElementPiS_S_,@object # @_Z10addElementPiS_S_
.section .rodata,"a",@progbits
.globl _Z10addElementPiS_S_
.p2align 3, 0x0
_Z10addElementPiS_S_:
.quad _Z25__device_stub__addElementPiS_S_
.size _Z10addElementPiS_S_, 8
.type _Z6addColPiS_S_,@object # @_Z6addColPiS_S_
.globl _Z6addColPiS_S_
.p2align 3, 0x0
_Z6addColPiS_S_:
.quad _Z21__device_stub__addColPiS_S_
.size _Z6addColPiS_S_, 8
.type _Z6addRowPiS_S_,@object # @_Z6addRowPiS_S_
.globl _Z6addRowPiS_S_
.p2align 3, 0x0
_Z6addRowPiS_S_:
.quad _Z21__device_stub__addRowPiS_S_
.size _Z6addRowPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter the value of n: "
.size .L.str, 23
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d "
.size .L.str.6, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10addElementPiS_S_"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z6addColPiS_S_"
.size .L__unnamed_2, 16
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z6addRowPiS_S_"
.size .L__unnamed_3, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Enter input matrix 1 : "
.size .Lstr, 24
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Enter input matrix 2 : "
.size .Lstr.1, 24
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Enter 1 for Row \n 2 for Column \n 3 for Element "
.size .Lstr.2, 48
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Result vector is :"
.size .Lstr.3, 19
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__addElementPiS_S_
.addrsig_sym _Z21__device_stub__addColPiS_S_
.addrsig_sym _Z21__device_stub__addRowPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10addElementPiS_S_
.addrsig_sym _Z6addColPiS_S_
.addrsig_sym _Z6addRowPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#define WIDTH 10
#define HEIGHT 10
#define channels 3
#define Mask_width 5
#define Mask_radius Mask_width/2
#define O_TILE_WIDTH 12
#define BLOCK_WIDTH (O_TILE_WIDTH+Mask_width-1)
#define min(x,y) ((x)<(y)?(x):(y))
#define max(x,y) ((x)>(y)?(x):(y))
#define clamp(x) (min(max((x),0.0),1.0))
void imageConvolution(float *input,float *output,const float* __restrict__ M,int width, int height, int ch)
{
int i=0,j=0,k=0,x=0,y=0,xOffset=0,yOffset=0;
float accum =0.0,maskValue =0.0,imagePixel =0.0;
for( i=0 ;i<height;i++){
for( j=0;j< width;j++){
for(k=0;k<ch;k++){
accum = 0;
for(y = 0 ;y< Mask_width;y++){
for(x= 0;x< Mask_width; x++){
xOffset = j + x - Mask_radius;
yOffset = i + y - Mask_radius;
if (xOffset>=0 && xOffset < width && yOffset>=0 && yOffset < height){
imagePixel = input[(yOffset * width + xOffset) * channels + k];
maskValue = M[y*Mask_width+x];
accum += imagePixel * maskValue;
}
else
accum +=0;
}
}
output[(i * width + j)*channels + k] = accum;// (float) clamp(accum);
}
}
}
}
__global__ void imageTiledConvolution_kernel(float *input,float *output,const float * __restrict__ M,int width, int height, int ch)
{
int i=0,j=0;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row_o = blockIdx.y*O_TILE_WIDTH+ty;
int col_o = blockIdx.x*O_TILE_WIDTH+tx;
int row_i = row_o - Mask_radius;
int col_i = col_o - Mask_radius;
float cValue = 0.0f;
__shared__ float Ns[BLOCK_WIDTH][BLOCK_WIDTH][channels];
for(int chIdx=0;chIdx<ch;chIdx++){
if(row_i>=0 && row_i<height && col_i>=0 && col_i<width){
Ns[ty][tx][chIdx] = input[(row_i*width+col_i)*ch+chIdx];
}else{
Ns[ty][tx][chIdx] = 0.0f;
}
__syncthreads();
cValue = 0.0f;
if(ty<O_TILE_WIDTH && tx<O_TILE_WIDTH){
for( i=0;i<Mask_width;i++){
for( j=0;j<Mask_width;j++){
cValue +=M[i*Mask_width+j]*Ns[ty+i][tx+j][chIdx];
}
}
}
__syncthreads();
if(row_o<height && col_o<width && ty<O_TILE_WIDTH && tx<O_TILE_WIDTH)
output[(row_o*width+col_o)*ch+chIdx] = cValue;//min(max(cValue,0),1);
}
}
void loadData(float *input,float *output,float *maskData)
{
int i=0;
for(i=0;i<WIDTH*HEIGHT*channels;i++)
input[i] = 1.0;
for(i=0;i<WIDTH*HEIGHT*channels;i++)
output[i] = 0.0;
for(i=0;i<Mask_width *Mask_width ;i++)
maskData[i] = 1.0;
}
void dispRes(float *arr)
{
int i=0,j=0,k=0;
printf("Results of the calculation\n");
for(k=0;k<channels;k++){
for(i=0;i<HEIGHT;i++){
for(j=0;j<WIDTH;j++){
printf("%2.1f ",arr[(i*WIDTH+j)*channels+k]);
}
printf("\n");
}
printf("k = %d\n",k);system("pause");
}
}
int main(void)
{
int maskRows = Mask_width;
int maskColumns = Mask_width;
int imageChannels = channels;
int imageWidth = WIDTH;
int imageHeight = HEIGHT;
float * hostInputImageData;
float * hostOutputImageData;
float * hostOutputImageDataCPU;
float * hostMaskData;
float * deviceInputImageData;
float * deviceOutputImageData;
float * deviceMaskData;
//allocate Memory on the host
hostInputImageData = (float*)malloc(imageWidth*imageHeight*channels*sizeof(float));
hostOutputImageData = (float*)malloc(imageWidth*imageHeight*channels*sizeof(float));
hostOutputImageDataCPU = (float*)malloc(imageWidth*imageHeight*channels*sizeof(float));
hostMaskData = (float*)malloc(Mask_width*Mask_width*sizeof(float));
//load data to host memory
loadData(hostInputImageData,hostOutputImageData,hostMaskData);
//cuda memory allocation on the device
cudaMalloc((void **) &deviceInputImageData, imageWidth * imageHeight * imageChannels * sizeof(float));
cudaMalloc((void **) &deviceOutputImageData, imageWidth * imageHeight * imageChannels * sizeof(float));
cudaMalloc((void **) &deviceMaskData, maskRows * maskColumns * sizeof(float));
//cuda memory copy from host to device
cudaMemcpy(deviceInputImageData,hostInputImageData,imageWidth * imageHeight * imageChannels * sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(deviceMaskData,hostMaskData,maskRows * maskColumns * sizeof(float),cudaMemcpyHostToDevice);
dim3 DimGrid((imageWidth-1)/O_TILE_WIDTH+1,(imageHeight-1)/O_TILE_WIDTH+1,1);
dim3 DimBlock(BLOCK_WIDTH, BLOCK_WIDTH,1);
imageTiledConvolution_kernel<<<DimGrid,DimBlock>>>(deviceInputImageData,deviceOutputImageData,deviceMaskData,imageWidth,imageHeight,imageChannels);
imageConvolution(hostInputImageData,hostOutputImageDataCPU,hostMaskData,imageWidth,imageHeight,imageChannels);
//cuda memory copy from device to host
cudaMemcpy(hostOutputImageData,deviceOutputImageData,imageWidth * imageHeight * imageChannels * sizeof(float),cudaMemcpyDeviceToHost);
//dispRes(hostOutputImageDataCPU);
dispRes(hostOutputImageData);
free(hostInputImageData);
free(hostOutputImageData);
free(hostOutputImageDataCPU);
free(hostMaskData);
cudaFree(deviceInputImageData);
cudaFree(deviceOutputImageData);
cudaFree(deviceMaskData);
return 0;
} | code for sm_80
Function : _Z28imageTiledConvolution_kernelPfS_PKfiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R0, c[0x0][0x180] ; /* 0x0000600000007a02 */
/* 0x000fc80000000f00 */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002200 */
/*0050*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0080*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e680000002100 */
/*0090*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000ea20000002500 */
/*00a0*/ IMAD R0, R0, 0xc, R5 ; /* 0x0000000c00007824 */
/* 0x001fc800078e0205 */
/*00b0*/ IMAD R3, R0.reuse, c[0x0][0x178], R11 ; /* 0x00005e0000037a24 */
/* 0x042fe200078e020b */
/*00c0*/ IADD3 R2, R0.reuse, -0x2, RZ ; /* 0xfffffffe00027810 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fe20003f26270 */
/*00e0*/ IMAD R3, R6, 0xc, R3 ; /* 0x0000000c06037824 */
/* 0x004fe200078e0203 */
/*00f0*/ ISETP.GE.AND P0, PT, R2.reuse, c[0x0][0x17c], PT ; /* 0x00005f0002007a0c */
/* 0x040fe20003f06270 */
/*0100*/ IMAD R4, R2, c[0x0][0x178], R11.reuse ; /* 0x00005e0002047a24 */
/* 0x100fe200078e020b */
/*0110*/ ISETP.GE.AND P3, PT, R11, 0xc, PT ; /* 0x0000000c0b00780c */
/* 0x000fe20003f66270 */
/*0120*/ IMAD R2, R6, 0xc, R11 ; /* 0x0000000c06027824 */
/* 0x000fe200078e020b */
/*0130*/ ISETP.GT.AND P0, PT, R0, 0x1, !P0 ; /* 0x000000010000780c */
/* 0x000fe20004704270 */
/*0140*/ IMAD R4, R6, 0xc, R4 ; /* 0x0000000c06047824 */
/* 0x000fc400078e0204 */
/*0150*/ IMAD R3, R3, c[0x0][0x180], RZ ; /* 0x0000600003037a24 */
/* 0x000fe200078e02ff */
/*0160*/ ISETP.LT.AND P1, PT, R2, c[0x0][0x178], !P1 ; /* 0x00005e0002007a0c */
/* 0x000fe40004f21270 */
/*0170*/ IADD3 R4, R4, -0x2, RZ ; /* 0xfffffffe04047810 */
/* 0x000fe20007ffe0ff */
/*0180*/ IMAD.WIDE R6, R3, R8.reuse, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x080fe200078e0208 */
/*0190*/ ISETP.GT.AND P2, PT, R2, 0x1, P0 ; /* 0x000000010200780c */
/* 0x000fe40000744270 */
/*01a0*/ ISETP.LT.AND P0, PT, R5.reuse, 0xc, !P3 ; /* 0x0000000c0500780c */
/* 0x040fe20005f01270 */
/*01b0*/ IMAD R4, R4, c[0x0][0x180], RZ ; /* 0x0000600004047a24 */
/* 0x000fe200078e02ff */
/*01c0*/ ISETP.LT.AND P1, PT, R5.reuse, 0xc, P1 ; /* 0x0000000c0500780c */
/* 0x040fe40000f21270 */
/*01d0*/ LEA R5, R5, R11, 0x4 ; /* 0x0000000b05057211 */
/* 0x000fe200078e20ff */
/*01e0*/ IMAD.WIDE R8, R4, R8, c[0x0][0x160] ; /* 0x0000580004087625 */
/* 0x000fe200078e0208 */
/*01f0*/ IADD3 R2, R2, -0x2, RZ ; /* 0xfffffffe02027810 */
/* 0x000fc40007ffe0ff */
/*0200*/ MOV R0, R6 ; /* 0x0000000600007202 */
/* 0x000fe20000000f00 */
/*0210*/ IMAD R10, R5, 0xc, RZ ; /* 0x0000000c050a7824 */
/* 0x000fe200078e02ff */
/*0220*/ MOV R6, R8 ; /* 0x0000000800067202 */
/* 0x000fe20000000f00 */
/*0230*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x000fe200000001ff */
/*0240*/ ISETP.LT.AND P1, PT, R11, 0xc, P1 ; /* 0x0000000c0b00780c */
/* 0x000fe40000f21270 */
/*0250*/ ISETP.LT.AND P2, PT, R2, c[0x0][0x178], P2 ; /* 0x00005e0002007a0c */
/* 0x000fda0001741270 */
/*0260*/ @P2 MOV R2, R6 ; /* 0x0000000600022202 */
/* 0x001fe40000000f00 */
/*0270*/ @P2 MOV R3, R9 ; /* 0x0000000900032202 */
/* 0x000fca0000000f00 */
/*0280*/ @P2 LDG.E R5, [R2.64] ; /* 0x0000000402052981 */
/* 0x0000a2000c1e1900 */
/*0290*/ BSSY B0, 0x7f0 ; /* 0x0000055000007945 */
/* 0x000fe20003800000 */
/*02a0*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fe40000000f00 */
/*02b0*/ @!P2 STS [R10], RZ ; /* 0x000000ff0a00a388 */
/* 0x0003e20000000800 */
/*02c0*/ @P1 MOV R2, R0 ; /* 0x0000000000021202 */
/* 0x001fe40000000f00 */
/*02d0*/ @P1 MOV R3, R7 ; /* 0x0000000700031202 */
/* 0x000fe20000000f00 */
/*02e0*/ @P2 STS [R10], R5 ; /* 0x000000050a002388 */
/* 0x0043e80000000800 */
/*02f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0300*/ @!P0 BRA 0x7e0 ; /* 0x000004d000008947 */
/* 0x000fea0003800000 */
/*0310*/ MOV R4, c[0x0][0x170] ; /* 0x00005c0000047a02 */
/* 0x002fe20000000f00 */
/*0320*/ LDS R28, [R10] ; /* 0x000000000a1c7984 */
/* 0x000e220000000800 */
/*0330*/ MOV R5, c[0x0][0x174] ; /* 0x00005d0000057a02 */
/* 0x000fc60000000f00 */
/*0340*/ LDS R21, [R10+0xc] ; /* 0x00000c000a157984 */
/* 0x000e680000000800 */
/*0350*/ LDG.E.CONSTANT R15, [R4.64] ; /* 0x00000004040f7981 */
/* 0x000e28000c1e9900 */
/*0360*/ LDG.E.CONSTANT R23, [R4.64+0x4] ; /* 0x0000040404177981 */
/* 0x000e68000c1e9900 */
/*0370*/ LDG.E.CONSTANT R16, [R4.64+0x8] ; /* 0x0000080404107981 */
/* 0x000ea8000c1e9900 */
/*0380*/ LDG.E.CONSTANT R17, [R4.64+0xc] ; /* 0x00000c0404117981 */
/* 0x000ee8000c1e9900 */
/*0390*/ LDG.E.CONSTANT R18, [R4.64+0x10] ; /* 0x0000100404127981 */
/* 0x000f28000c1e9900 */
/*03a0*/ LDG.E.CONSTANT R20, [R4.64+0x14] ; /* 0x0000140404147981 */
/* 0x000f28000c1e9900 */
/*03b0*/ LDG.E.CONSTANT R22, [R4.64+0x18] ; /* 0x0000180404167981 */
/* 0x000f28000c1e9900 */
/*03c0*/ LDG.E.CONSTANT R24, [R4.64+0x1c] ; /* 0x00001c0404187981 */
/* 0x000f28000c1e9900 */
/*03d0*/ LDG.E.CONSTANT R11, [R4.64+0x20] ; /* 0x00002004040b7981 */
/* 0x000f28000c1e9900 */
/*03e0*/ LDG.E.CONSTANT R12, [R4.64+0x24] ; /* 0x00002404040c7981 */
/* 0x000f28000c1e9900 */
/*03f0*/ LDG.E.CONSTANT R13, [R4.64+0x28] ; /* 0x00002804040d7981 */
/* 0x000128000c1e9900 */
/*0400*/ LDS R19, [R10+0x18] ; /* 0x000018000a137984 */
/* 0x000ea80000000800 */
/*0410*/ LDG.E.CONSTANT R14, [R4.64+0x2c] ; /* 0x00002c04040e7981 */
/* 0x000128000c1e9900 */
/*0420*/ LDS R26, [R10+0x24] ; /* 0x000024000a1a7984 */
/* 0x000ee80000000800 */
/*0430*/ LDS R27, [R10+0x30] ; /* 0x000030000a1b7984 */
/* 0x000f280000000800 */
/*0440*/ LDS R25, [R10+0xd8] ; /* 0x0000d8000a197984 */
/* 0x000fe20000000800 */
/*0450*/ FFMA R15, R15, R28, RZ ; /* 0x0000001c0f0f7223 */
/* 0x001fc600000000ff */
/*0460*/ LDS R28, [R10+0x1a4] ; /* 0x0001a4000a1c7984 */
/* 0x000fe20000000800 */
/*0470*/ FFMA R23, R21, R23, R15 ; /* 0x0000001715177223 */
/* 0x002fc6000000000f */
/*0480*/ LDG.E.CONSTANT R15, [R4.64+0x30] ; /* 0x00003004040f7981 */
/* 0x000162000c1e9900 */
/*0490*/ FFMA R19, R19, R16, R23 ; /* 0x0000001013137223 */
/* 0x004fc60000000017 */
/*04a0*/ LDS R21, [R10+0xc0] ; /* 0x0000c0000a157984 */
/* 0x000e680000000800 */
/*04b0*/ LDS R23, [R10+0xcc] ; /* 0x0000cc000a177984 */
/* 0x000ea20000000800 */
/*04c0*/ FFMA R19, R26, R17, R19 ; /* 0x000000111a137223 */
/* 0x008fc60000000013 */
/*04d0*/ LDG.E.CONSTANT R16, [R4.64+0x34] ; /* 0x0000340404107981 */
/* 0x0000e8000c1e9900 */
/*04e0*/ LDG.E.CONSTANT R17, [R4.64+0x38] ; /* 0x0000380404117981 */
/* 0x0000e2000c1e9900 */
/*04f0*/ FFMA R27, R27, R18, R19 ; /* 0x000000121b1b7223 */
/* 0x010fc60000000013 */
/*0500*/ LDS R18, [R10+0xe4] ; /* 0x0000e4000a127984 */
/* 0x000f280000000800 */
/*0510*/ LDG.E.CONSTANT R19, [R4.64+0x3c] ; /* 0x00003c0404137981 */
/* 0x0000e2000c1e9900 */
/*0520*/ FFMA R27, R21, R20, R27 ; /* 0x00000014151b7223 */
/* 0x002fc6000000001b */
/*0530*/ LDS R21, [R10+0xf0] ; /* 0x0000f0000a157984 */
/* 0x000e680000000800 */
/*0540*/ LDG.E.CONSTANT R20, [R4.64+0x40] ; /* 0x0000400404147981 */
/* 0x0000e2000c1e9900 */
/*0550*/ FFMA R27, R23, R22, R27 ; /* 0x00000016171b7223 */
/* 0x004fc6000000001b */
/*0560*/ LDG.E.CONSTANT R22, [R4.64+0x44] ; /* 0x0000440404167981 */
/* 0x0000a2000c1e9900 */
/*0570*/ FFMA R27, R25, R24, R27 ; /* 0x00000018191b7223 */
/* 0x000fc6000000001b */
/*0580*/ LDG.E.CONSTANT R23, [R4.64+0x48] ; /* 0x0000480404177981 */
/* 0x0000a8000c1e9900 */
/*0590*/ LDG.E.CONSTANT R25, [R4.64+0x4c] ; /* 0x00004c0404197981 */
/* 0x0000a2000c1e9900 */
/*05a0*/ FFMA R27, R18, R11, R27 ; /* 0x0000000b121b7223 */
/* 0x010fc6000000001b */
/*05b0*/ LDG.E.CONSTANT R24, [R4.64+0x50] ; /* 0x0000500404187981 */
/* 0x000128000c1e9900 */
/*05c0*/ LDG.E.CONSTANT R18, [R4.64+0x54] ; /* 0x0000540404127981 */
/* 0x000128000c1e9900 */
/*05d0*/ LDG.E.CONSTANT R11, [R4.64+0x58] ; /* 0x00005804040b7981 */
/* 0x000122000c1e9900 */
/*05e0*/ FFMA R26, R21, R12, R27 ; /* 0x0000000c151a7223 */
/* 0x002fc6000000001b */
/*05f0*/ LDG.E.CONSTANT R12, [R4.64+0x5c] ; /* 0x00005c04040c7981 */
/* 0x000128000c1e9900 */
/*0600*/ LDG.E.CONSTANT R21, [R4.64+0x60] ; /* 0x0000600404157981 */
/* 0x000128000c1e9900 */
/*0610*/ LDS R27, [R10+0x180] ; /* 0x000180000a1b7984 */
/* 0x000e680000000800 */
/*0620*/ LDS R5, [R10+0x258] ; /* 0x000258000a057984 */
/* 0x001fe80000000800 */
/*0630*/ LDS R4, [R10+0x264] ; /* 0x000264000a047984 */
/* 0x000fe20000000800 */
/*0640*/ FFMA R13, R27, R13, R26 ; /* 0x0000000d1b0d7223 */
/* 0x002fc6000000001a */
/*0650*/ LDS R26, [R10+0x18c] ; /* 0x00018c000a1a7984 */
/* 0x000e280000000800 */
/*0660*/ LDS R27, [R10+0x198] ; /* 0x000198000a1b7984 */
/* 0x000f620000000800 */
/*0670*/ FFMA R26, R26, R14, R13 ; /* 0x0000000e1a1a7223 */
/* 0x001fc6000000000d */
/*0680*/ LDS R14, [R10+0x1b0] ; /* 0x0001b0000a0e7984 */
/* 0x000e280000000800 */
/*0690*/ LDS R13, [R10+0x24c] ; /* 0x00024c000a0d7984 */
/* 0x000fe20000000800 */
/*06a0*/ FFMA R15, R27, R15, R26 ; /* 0x0000000f1b0f7223 */
/* 0x020fc6000000001a */
/*06b0*/ LDS R26, [R10+0x240] ; /* 0x000240000a1a7984 */
/* 0x000e620000000800 */
/*06c0*/ FFMA R15, R28, R16, R15 ; /* 0x000000101c0f7223 */
/* 0x008fc6000000000f */
/*06d0*/ LDS R16, [R10+0x318] ; /* 0x000318000a107984 */
/* 0x000fe20000000800 */
/*06e0*/ FFMA R17, R14, R17, R15 ; /* 0x000000110e117223 */
/* 0x001fc6000000000f */
/*06f0*/ LDS R14, [R10+0x270] ; /* 0x000270000a0e7984 */
/* 0x000e280000000800 */
/*0700*/ LDS R15, [R10+0x300] ; /* 0x000300000a0f7984 */
/* 0x000f220000000800 */
/*0710*/ FFMA R19, R26, R19, R17 ; /* 0x000000131a137223 */
/* 0x002fc60000000011 */
/*0720*/ LDS R17, [R10+0x30c] ; /* 0x00030c000a117984 */
/* 0x000e620000000800 */
/*0730*/ FFMA R19, R13, R20, R19 ; /* 0x000000140d137223 */
/* 0x000fc60000000013 */
/*0740*/ LDS R13, [R10+0x324] ; /* 0x000324000a0d7984 */
/* 0x000ee20000000800 */
/*0750*/ FFMA R5, R5, R22, R19 ; /* 0x0000001605057223 */
/* 0x004fc60000000013 */
/*0760*/ LDS R20, [R10+0x330] ; /* 0x000330000a147984 */
/* 0x000ea20000000800 */
/*0770*/ FFMA R4, R4, R23, R5 ; /* 0x0000001704047223 */
/* 0x000fc80000000005 */
/*0780*/ FFMA R4, R14, R25, R4 ; /* 0x000000190e047223 */
/* 0x001fc80000000004 */
/*0790*/ FFMA R4, R15, R24, R4 ; /* 0x000000180f047223 */
/* 0x010fc80000000004 */
/*07a0*/ FFMA R4, R17, R18, R4 ; /* 0x0000001211047223 */
/* 0x002fc80000000004 */
/*07b0*/ FFMA R4, R16, R11, R4 ; /* 0x0000000b10047223 */
/* 0x000fc80000000004 */
/*07c0*/ FFMA R4, R13, R12, R4 ; /* 0x0000000c0d047223 */
/* 0x008fc80000000004 */
/*07d0*/ FFMA R21, R20, R21, R4 ; /* 0x0000001514157223 */
/* 0x004fe40000000004 */
/*07e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*07f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0800*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe40007ffe0ff */
/*0810*/ IADD3 R0, P3, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x000fe40007f7e0ff */
/*0820*/ ISETP.GE.AND P5, PT, R8, c[0x0][0x180], PT ; /* 0x0000600008007a0c */
/* 0x000fe40003fa6270 */
/*0830*/ IADD3 R6, P4, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007f9e0ff */
/*0840*/ IADD3.X R7, RZ, R7, RZ, P3, !PT ; /* 0x00000007ff077210 */
/* 0x000fe40001ffe4ff */
/*0850*/ IADD3.X R9, RZ, R9, RZ, P4, !PT ; /* 0x00000009ff097210 */
/* 0x000fc400027fe4ff */
/*0860*/ IADD3 R10, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fe20007ffe0ff */
/*0870*/ @P1 STG.E [R2.64], R21 ; /* 0x0000001502001986 */
/* 0x0001e8000c101904 */
/*0880*/ @!P5 BRA 0x260 ; /* 0xfffff9d00000d947 */
/* 0x000fea000383ffff */
/*0890*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08a0*/ BRA 0x8a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#define WIDTH 10
#define HEIGHT 10
#define channels 3
#define Mask_width 5
#define Mask_radius Mask_width/2
#define O_TILE_WIDTH 12
#define BLOCK_WIDTH (O_TILE_WIDTH+Mask_width-1)
#define min(x,y) ((x)<(y)?(x):(y))
#define max(x,y) ((x)>(y)?(x):(y))
#define clamp(x) (min(max((x),0.0),1.0))
void imageConvolution(float *input,float *output,const float* __restrict__ M,int width, int height, int ch)
{
int i=0,j=0,k=0,x=0,y=0,xOffset=0,yOffset=0;
float accum =0.0,maskValue =0.0,imagePixel =0.0;
for( i=0 ;i<height;i++){
for( j=0;j< width;j++){
for(k=0;k<ch;k++){
accum = 0;
for(y = 0 ;y< Mask_width;y++){
for(x= 0;x< Mask_width; x++){
xOffset = j + x - Mask_radius;
yOffset = i + y - Mask_radius;
if (xOffset>=0 && xOffset < width && yOffset>=0 && yOffset < height){
imagePixel = input[(yOffset * width + xOffset) * channels + k];
maskValue = M[y*Mask_width+x];
accum += imagePixel * maskValue;
}
else
accum +=0;
}
}
output[(i * width + j)*channels + k] = accum;// (float) clamp(accum);
}
}
}
}
__global__ void imageTiledConvolution_kernel(float *input,float *output,const float * __restrict__ M,int width, int height, int ch)
{
int i=0,j=0;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row_o = blockIdx.y*O_TILE_WIDTH+ty;
int col_o = blockIdx.x*O_TILE_WIDTH+tx;
int row_i = row_o - Mask_radius;
int col_i = col_o - Mask_radius;
float cValue = 0.0f;
__shared__ float Ns[BLOCK_WIDTH][BLOCK_WIDTH][channels];
for(int chIdx=0;chIdx<ch;chIdx++){
if(row_i>=0 && row_i<height && col_i>=0 && col_i<width){
Ns[ty][tx][chIdx] = input[(row_i*width+col_i)*ch+chIdx];
}else{
Ns[ty][tx][chIdx] = 0.0f;
}
__syncthreads();
cValue = 0.0f;
if(ty<O_TILE_WIDTH && tx<O_TILE_WIDTH){
for( i=0;i<Mask_width;i++){
for( j=0;j<Mask_width;j++){
cValue +=M[i*Mask_width+j]*Ns[ty+i][tx+j][chIdx];
}
}
}
__syncthreads();
if(row_o<height && col_o<width && ty<O_TILE_WIDTH && tx<O_TILE_WIDTH)
output[(row_o*width+col_o)*ch+chIdx] = cValue;//min(max(cValue,0),1);
}
}
void loadData(float *input,float *output,float *maskData)
{
int i=0;
for(i=0;i<WIDTH*HEIGHT*channels;i++)
input[i] = 1.0;
for(i=0;i<WIDTH*HEIGHT*channels;i++)
output[i] = 0.0;
for(i=0;i<Mask_width *Mask_width ;i++)
maskData[i] = 1.0;
}
void dispRes(float *arr)
{
int i=0,j=0,k=0;
printf("Results of the calculation\n");
for(k=0;k<channels;k++){
for(i=0;i<HEIGHT;i++){
for(j=0;j<WIDTH;j++){
printf("%2.1f ",arr[(i*WIDTH+j)*channels+k]);
}
printf("\n");
}
printf("k = %d\n",k);system("pause");
}
}
int main(void)
{
int maskRows = Mask_width;
int maskColumns = Mask_width;
int imageChannels = channels;
int imageWidth = WIDTH;
int imageHeight = HEIGHT;
float * hostInputImageData;
float * hostOutputImageData;
float * hostOutputImageDataCPU;
float * hostMaskData;
float * deviceInputImageData;
float * deviceOutputImageData;
float * deviceMaskData;
//allocate Memory on the host
hostInputImageData = (float*)malloc(imageWidth*imageHeight*channels*sizeof(float));
hostOutputImageData = (float*)malloc(imageWidth*imageHeight*channels*sizeof(float));
hostOutputImageDataCPU = (float*)malloc(imageWidth*imageHeight*channels*sizeof(float));
hostMaskData = (float*)malloc(Mask_width*Mask_width*sizeof(float));
//load data to host memory
loadData(hostInputImageData,hostOutputImageData,hostMaskData);
//cuda memory allocation on the device
cudaMalloc((void **) &deviceInputImageData, imageWidth * imageHeight * imageChannels * sizeof(float));
cudaMalloc((void **) &deviceOutputImageData, imageWidth * imageHeight * imageChannels * sizeof(float));
cudaMalloc((void **) &deviceMaskData, maskRows * maskColumns * sizeof(float));
//cuda memory copy from host to device
cudaMemcpy(deviceInputImageData,hostInputImageData,imageWidth * imageHeight * imageChannels * sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(deviceMaskData,hostMaskData,maskRows * maskColumns * sizeof(float),cudaMemcpyHostToDevice);
dim3 DimGrid((imageWidth-1)/O_TILE_WIDTH+1,(imageHeight-1)/O_TILE_WIDTH+1,1);
dim3 DimBlock(BLOCK_WIDTH, BLOCK_WIDTH,1);
imageTiledConvolution_kernel<<<DimGrid,DimBlock>>>(deviceInputImageData,deviceOutputImageData,deviceMaskData,imageWidth,imageHeight,imageChannels);
imageConvolution(hostInputImageData,hostOutputImageDataCPU,hostMaskData,imageWidth,imageHeight,imageChannels);
//cuda memory copy from device to host
cudaMemcpy(hostOutputImageData,deviceOutputImageData,imageWidth * imageHeight * imageChannels * sizeof(float),cudaMemcpyDeviceToHost);
//dispRes(hostOutputImageDataCPU);
dispRes(hostOutputImageData);
free(hostInputImageData);
free(hostOutputImageData);
free(hostOutputImageDataCPU);
free(hostMaskData);
cudaFree(deviceInputImageData);
cudaFree(deviceOutputImageData);
cudaFree(deviceMaskData);
return 0;
} | .file "tmpxft_00159be7_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16imageConvolutionPfS_PKfiii
.type _Z16imageConvolutionPfS_PKfiii, @function
_Z16imageConvolutionPfS_PKfiii:
.LFB2057:
.cfi_startproc
endbr64
testl %r8d, %r8d
jle .L19
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rdi, %r14
movq %rdx, %rbp
movl %ecx, %r15d
leal (%rcx,%rcx), %eax
negl %eax
movl %eax, %edi
movl $0, %eax
movl $0, %edx
movslq %r9d, %rbx
movq %rbx, -40(%rsp)
pxor %xmm2, %xmm2
movl %edi, %ebx
movq %r14, %r13
movq %rsi, -16(%rsp)
movq %rbp, %r14
movl %r8d, %r12d
movl %r9d, %r10d
jmp .L5
.L6:
addss %xmm2, %xmm0
.L7:
addl $1, %eax
addl $3, %edx
cmpl %esi, %eax
je .L22
.L8:
movl %eax, %edi
orl %ecx, %edi
js .L6
cmpl %eax, %r15d
jle .L6
cmpl %ecx, %r12d
jle .L6
leal (%r8,%rax), %r11d
movslq %r11d, %r11
movslq %edx, %rdi
movss (%r14,%r11,4), %xmm1
mulss 0(%r13,%rdi,4), %xmm1
addss %xmm1, %xmm0
jmp .L7
.L22:
addl %r15d, %r9d
addl $5, %r10d
addl $1, %ecx
cmpl %ebp, %r10d
je .L9
.L11:
leal (%r9,%r9,2), %edx
addl %ebx, %edx
movl -64(%rsp), %eax
leal 2(%r10), %r11d
movl %r11d, %r8d
jmp .L8
.L9:
movq -72(%rsp), %rax
movl -60(%rsp), %edi
movq -56(%rsp), %rbx
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
addl $1, %edi
movq -40(%rsp), %rbx
cmpq %rbx, %rax
je .L16
.L13:
movl -48(%rsp), %r10d
negl %r10d
movl -44(%rsp), %ebx
leal -2(%rbx), %ecx
movl -32(%rsp), %r9d
pxor %xmm0, %xmm0
leal -6(%rdi), %ebx
movq %rax, -72(%rsp)
movl %edi, -60(%rsp)
jmp .L11
.L16:
movl -28(%rsp), %ecx
movl -24(%rsp), %r9d
movl -64(%rsp), %r8d
movl -20(%rsp), %r10d
.L10:
addl $1, %ecx
addl $1, %r9d
addl $1, %esi
addl $1, %r8d
cmpl %ecx, %r15d
je .L17
.L14:
testl %r10d, %r10d
jle .L10
movl %ecx, -48(%rsp)
leal (%rcx,%rcx,2), %edi
movslq %r9d, %rax
leaq (%rax,%rax,2), %rax
movq -16(%rsp), %rdx
leaq (%rdx,%rax,4), %rdx
movl $0, %eax
movl $25, %ebp
subl %ecx, %ebp
movl %ecx, -28(%rsp)
movq %rdx, -56(%rsp)
movl %r9d, -24(%rsp)
movl %r8d, -64(%rsp)
movl %r10d, -20(%rsp)
jmp .L13
.L17:
movl -44(%rsp), %edx
movl -8(%rsp), %eax
movl -4(%rsp), %ebx
.L12:
addl $1, %edx
addl %r15d, %eax
cmpl %edx, %r12d
je .L3
.L5:
testl %r15d, %r15d
jle .L12
leal (%rax,%rbx), %esi
movl %esi, -32(%rsp)
movl %eax, %r9d
movl $-2, %r8d
movl $3, %esi
movl $0, %ecx
movl %edx, -44(%rsp)
movl %eax, -8(%rsp)
movl %ebx, -4(%rsp)
jmp .L14
.L3:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2057:
.size _Z16imageConvolutionPfS_PKfiii, .-_Z16imageConvolutionPfS_PKfiii
.globl _Z8loadDataPfS_S_
.type _Z8loadDataPfS_S_, @function
_Z8loadDataPfS_S_:
.LFB2058:
.cfi_startproc
endbr64
movq %rdi, %rax
leaq 1200(%rdi), %rcx
movss .LC1(%rip), %xmm0
.L24:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L24
movq %rsi, %rax
leaq 1200(%rsi), %rcx
.L25:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L25
movq %rdx, %rax
addq $100, %rdx
movss .LC1(%rip), %xmm0
.L26:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L26
ret
.cfi_endproc
.LFE2058:
.size _Z8loadDataPfS_S_, .-_Z8loadDataPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Results of the calculation\n"
.LC3:
.string "%2.1f "
.LC4:
.string "\n"
.LC5:
.string "k = %d\n"
.LC6:
.string "pause"
.text
.globl _Z7dispResPf
.type _Z7dispResPf, @function
_Z7dispResPf:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 120(%rbx), %rax
movq %rax, (%rsp)
movl $0, %r15d
leaq .LC3(%rip), %r12
leaq .LC4(%rip), %r14
.L31:
movl %r15d, 12(%rsp)
movq (%rsp), %rbp
movl $0, %r13d
.L35:
leaq -120(%rbp), %rbx
.L32:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $12, %rbx
cmpq %rbp, %rbx
jne .L32
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $10, %r13d
addq $120, %rbp
cmpl $100, %r13d
jne .L35
movl 12(%rsp), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC6(%rip), %rdi
call system@PLT
addq $1, %r15
addq $4, (%rsp)
cmpq $3, %r15
jne .L31
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z7dispResPf, .-_Z7dispResPf
.globl _Z56__device_stub__Z28imageTiledConvolution_kernelPfS_PKfiiiPfS_PKfiii
.type _Z56__device_stub__Z28imageTiledConvolution_kernelPfS_PKfiiiPfS_PKfiii, @function
_Z56__device_stub__Z28imageTiledConvolution_kernelPfS_PKfiiiPfS_PKfiii:
.LFB2085:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movq %rdx, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L42
.L38:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L43
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z28imageTiledConvolution_kernelPfS_PKfiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L38
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z56__device_stub__Z28imageTiledConvolution_kernelPfS_PKfiiiPfS_PKfiii, .-_Z56__device_stub__Z28imageTiledConvolution_kernelPfS_PKfiiiPfS_PKfiii
.globl _Z28imageTiledConvolution_kernelPfS_PKfiii
.type _Z28imageTiledConvolution_kernelPfS_PKfiii, @function
_Z28imageTiledConvolution_kernelPfS_PKfiii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z56__device_stub__Z28imageTiledConvolution_kernelPfS_PKfiiiPfS_PKfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z28imageTiledConvolution_kernelPfS_PKfiii, .-_Z28imageTiledConvolution_kernelPfS_PKfiii
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1200, %edi
call malloc@PLT
movq %rax, %r12
movl $1200, %edi
call malloc@PLT
movq %rax, %rbp
movl $1200, %edi
call malloc@PLT
movq %rax, %r13
movl $100, %edi
call malloc@PLT
movq %rax, %rbx
movq %rax, %rdx
movq %rbp, %rsi
movq %r12, %rdi
call _Z8loadDataPfS_S_
leaq 8(%rsp), %rdi
movl $1200, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $1200, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $100, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $1200, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $100, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $16, 44(%rsp)
movl $16, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L47:
movl $3, %r9d
movl $10, %r8d
movl $10, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq %r12, %rdi
call _Z16imageConvolutionPfS_PKfiii
movl $2, %ecx
movl $1200, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq %rbp, %rdi
call _Z7dispResPf
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L51
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
movl $3, %r9d
movl $10, %r8d
movl $10, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z56__device_stub__Z28imageTiledConvolution_kernelPfS_PKfiiiPfS_PKfiii
jmp .L47
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "_Z28imageTiledConvolution_kernelPfS_PKfiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z28imageTiledConvolution_kernelPfS_PKfiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#define WIDTH 10
#define HEIGHT 10
#define channels 3
#define Mask_width 5
#define Mask_radius Mask_width/2
#define O_TILE_WIDTH 12
#define BLOCK_WIDTH (O_TILE_WIDTH+Mask_width-1)
#define min(x,y) ((x)<(y)?(x):(y))
#define max(x,y) ((x)>(y)?(x):(y))
#define clamp(x) (min(max((x),0.0),1.0))
void imageConvolution(float *input,float *output,const float* __restrict__ M,int width, int height, int ch)
{
int i=0,j=0,k=0,x=0,y=0,xOffset=0,yOffset=0;
float accum =0.0,maskValue =0.0,imagePixel =0.0;
for( i=0 ;i<height;i++){
for( j=0;j< width;j++){
for(k=0;k<ch;k++){
accum = 0;
for(y = 0 ;y< Mask_width;y++){
for(x= 0;x< Mask_width; x++){
xOffset = j + x - Mask_radius;
yOffset = i + y - Mask_radius;
if (xOffset>=0 && xOffset < width && yOffset>=0 && yOffset < height){
imagePixel = input[(yOffset * width + xOffset) * channels + k];
maskValue = M[y*Mask_width+x];
accum += imagePixel * maskValue;
}
else
accum +=0;
}
}
output[(i * width + j)*channels + k] = accum;// (float) clamp(accum);
}
}
}
}
__global__ void imageTiledConvolution_kernel(float *input,float *output,const float * __restrict__ M,int width, int height, int ch)
{
int i=0,j=0;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row_o = blockIdx.y*O_TILE_WIDTH+ty;
int col_o = blockIdx.x*O_TILE_WIDTH+tx;
int row_i = row_o - Mask_radius;
int col_i = col_o - Mask_radius;
float cValue = 0.0f;
__shared__ float Ns[BLOCK_WIDTH][BLOCK_WIDTH][channels];
for(int chIdx=0;chIdx<ch;chIdx++){
if(row_i>=0 && row_i<height && col_i>=0 && col_i<width){
Ns[ty][tx][chIdx] = input[(row_i*width+col_i)*ch+chIdx];
}else{
Ns[ty][tx][chIdx] = 0.0f;
}
__syncthreads();
cValue = 0.0f;
if(ty<O_TILE_WIDTH && tx<O_TILE_WIDTH){
for( i=0;i<Mask_width;i++){
for( j=0;j<Mask_width;j++){
cValue +=M[i*Mask_width+j]*Ns[ty+i][tx+j][chIdx];
}
}
}
__syncthreads();
if(row_o<height && col_o<width && ty<O_TILE_WIDTH && tx<O_TILE_WIDTH)
output[(row_o*width+col_o)*ch+chIdx] = cValue;//min(max(cValue,0),1);
}
}
void loadData(float *input,float *output,float *maskData)
{
int i=0;
for(i=0;i<WIDTH*HEIGHT*channels;i++)
input[i] = 1.0;
for(i=0;i<WIDTH*HEIGHT*channels;i++)
output[i] = 0.0;
for(i=0;i<Mask_width *Mask_width ;i++)
maskData[i] = 1.0;
}
void dispRes(float *arr)
{
int i=0,j=0,k=0;
printf("Results of the calculation\n");
for(k=0;k<channels;k++){
for(i=0;i<HEIGHT;i++){
for(j=0;j<WIDTH;j++){
printf("%2.1f ",arr[(i*WIDTH+j)*channels+k]);
}
printf("\n");
}
printf("k = %d\n",k);system("pause");
}
}
int main(void)
{
int maskRows = Mask_width;
int maskColumns = Mask_width;
int imageChannels = channels;
int imageWidth = WIDTH;
int imageHeight = HEIGHT;
float * hostInputImageData;
float * hostOutputImageData;
float * hostOutputImageDataCPU;
float * hostMaskData;
float * deviceInputImageData;
float * deviceOutputImageData;
float * deviceMaskData;
//allocate Memory on the host
hostInputImageData = (float*)malloc(imageWidth*imageHeight*channels*sizeof(float));
hostOutputImageData = (float*)malloc(imageWidth*imageHeight*channels*sizeof(float));
hostOutputImageDataCPU = (float*)malloc(imageWidth*imageHeight*channels*sizeof(float));
hostMaskData = (float*)malloc(Mask_width*Mask_width*sizeof(float));
//load data to host memory
loadData(hostInputImageData,hostOutputImageData,hostMaskData);
//cuda memory allocation on the device
cudaMalloc((void **) &deviceInputImageData, imageWidth * imageHeight * imageChannels * sizeof(float));
cudaMalloc((void **) &deviceOutputImageData, imageWidth * imageHeight * imageChannels * sizeof(float));
cudaMalloc((void **) &deviceMaskData, maskRows * maskColumns * sizeof(float));
//cuda memory copy from host to device
cudaMemcpy(deviceInputImageData,hostInputImageData,imageWidth * imageHeight * imageChannels * sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(deviceMaskData,hostMaskData,maskRows * maskColumns * sizeof(float),cudaMemcpyHostToDevice);
dim3 DimGrid((imageWidth-1)/O_TILE_WIDTH+1,(imageHeight-1)/O_TILE_WIDTH+1,1);
dim3 DimBlock(BLOCK_WIDTH, BLOCK_WIDTH,1);
imageTiledConvolution_kernel<<<DimGrid,DimBlock>>>(deviceInputImageData,deviceOutputImageData,deviceMaskData,imageWidth,imageHeight,imageChannels);
imageConvolution(hostInputImageData,hostOutputImageDataCPU,hostMaskData,imageWidth,imageHeight,imageChannels);
//cuda memory copy from device to host
cudaMemcpy(hostOutputImageData,deviceOutputImageData,imageWidth * imageHeight * imageChannels * sizeof(float),cudaMemcpyDeviceToHost);
//dispRes(hostOutputImageDataCPU);
dispRes(hostOutputImageData);
free(hostInputImageData);
free(hostOutputImageData);
free(hostOutputImageDataCPU);
free(hostMaskData);
cudaFree(deviceInputImageData);
cudaFree(deviceOutputImageData);
cudaFree(deviceMaskData);
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#define WIDTH 10
#define HEIGHT 10
#define channels 3
#define Mask_width 5
#define Mask_radius Mask_width/2
#define O_TILE_WIDTH 12
#define BLOCK_WIDTH (O_TILE_WIDTH+Mask_width-1)
#define min(x,y) ((x)<(y)?(x):(y))
#define max(x,y) ((x)>(y)?(x):(y))
#define clamp(x) (min(max((x),0.0),1.0))
void imageConvolution(float *input,float *output,const float* __restrict__ M,int width, int height, int ch)
{
int i=0,j=0,k=0,x=0,y=0,xOffset=0,yOffset=0;
float accum =0.0,maskValue =0.0,imagePixel =0.0;
for( i=0 ;i<height;i++){
for( j=0;j< width;j++){
for(k=0;k<ch;k++){
accum = 0;
for(y = 0 ;y< Mask_width;y++){
for(x= 0;x< Mask_width; x++){
xOffset = j + x - Mask_radius;
yOffset = i + y - Mask_radius;
if (xOffset>=0 && xOffset < width && yOffset>=0 && yOffset < height){
imagePixel = input[(yOffset * width + xOffset) * channels + k];
maskValue = M[y*Mask_width+x];
accum += imagePixel * maskValue;
}
else
accum +=0;
}
}
output[(i * width + j)*channels + k] = accum;// (float) clamp(accum);
}
}
}
}
__global__ void imageTiledConvolution_kernel(float *input,float *output,const float * __restrict__ M,int width, int height, int ch)
{
int i=0,j=0;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row_o = blockIdx.y*O_TILE_WIDTH+ty;
int col_o = blockIdx.x*O_TILE_WIDTH+tx;
int row_i = row_o - Mask_radius;
int col_i = col_o - Mask_radius;
float cValue = 0.0f;
__shared__ float Ns[BLOCK_WIDTH][BLOCK_WIDTH][channels];
for(int chIdx=0;chIdx<ch;chIdx++){
if(row_i>=0 && row_i<height && col_i>=0 && col_i<width){
Ns[ty][tx][chIdx] = input[(row_i*width+col_i)*ch+chIdx];
}else{
Ns[ty][tx][chIdx] = 0.0f;
}
__syncthreads();
cValue = 0.0f;
if(ty<O_TILE_WIDTH && tx<O_TILE_WIDTH){
for( i=0;i<Mask_width;i++){
for( j=0;j<Mask_width;j++){
cValue +=M[i*Mask_width+j]*Ns[ty+i][tx+j][chIdx];
}
}
}
__syncthreads();
if(row_o<height && col_o<width && ty<O_TILE_WIDTH && tx<O_TILE_WIDTH)
output[(row_o*width+col_o)*ch+chIdx] = cValue;//min(max(cValue,0),1);
}
}
void loadData(float *input,float *output,float *maskData)
{
int i=0;
for(i=0;i<WIDTH*HEIGHT*channels;i++)
input[i] = 1.0;
for(i=0;i<WIDTH*HEIGHT*channels;i++)
output[i] = 0.0;
for(i=0;i<Mask_width *Mask_width ;i++)
maskData[i] = 1.0;
}
void dispRes(float *arr)
{
int i=0,j=0,k=0;
printf("Results of the calculation\n");
for(k=0;k<channels;k++){
for(i=0;i<HEIGHT;i++){
for(j=0;j<WIDTH;j++){
printf("%2.1f ",arr[(i*WIDTH+j)*channels+k]);
}
printf("\n");
}
printf("k = %d\n",k);system("pause");
}
}
int main(void)
{
int maskRows = Mask_width;
int maskColumns = Mask_width;
int imageChannels = channels;
int imageWidth = WIDTH;
int imageHeight = HEIGHT;
float * hostInputImageData;
float * hostOutputImageData;
float * hostOutputImageDataCPU;
float * hostMaskData;
float * deviceInputImageData;
float * deviceOutputImageData;
float * deviceMaskData;
//allocate Memory on the host
hostInputImageData = (float*)malloc(imageWidth*imageHeight*channels*sizeof(float));
hostOutputImageData = (float*)malloc(imageWidth*imageHeight*channels*sizeof(float));
hostOutputImageDataCPU = (float*)malloc(imageWidth*imageHeight*channels*sizeof(float));
hostMaskData = (float*)malloc(Mask_width*Mask_width*sizeof(float));
//load data to host memory
loadData(hostInputImageData,hostOutputImageData,hostMaskData);
//cuda memory allocation on the device
hipMalloc((void **) &deviceInputImageData, imageWidth * imageHeight * imageChannels * sizeof(float));
hipMalloc((void **) &deviceOutputImageData, imageWidth * imageHeight * imageChannels * sizeof(float));
hipMalloc((void **) &deviceMaskData, maskRows * maskColumns * sizeof(float));
//cuda memory copy from host to device
hipMemcpy(deviceInputImageData,hostInputImageData,imageWidth * imageHeight * imageChannels * sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(deviceMaskData,hostMaskData,maskRows * maskColumns * sizeof(float),hipMemcpyHostToDevice);
dim3 DimGrid((imageWidth-1)/O_TILE_WIDTH+1,(imageHeight-1)/O_TILE_WIDTH+1,1);
dim3 DimBlock(BLOCK_WIDTH, BLOCK_WIDTH,1);
imageTiledConvolution_kernel<<<DimGrid,DimBlock>>>(deviceInputImageData,deviceOutputImageData,deviceMaskData,imageWidth,imageHeight,imageChannels);
imageConvolution(hostInputImageData,hostOutputImageDataCPU,hostMaskData,imageWidth,imageHeight,imageChannels);
//cuda memory copy from device to host
hipMemcpy(hostOutputImageData,deviceOutputImageData,imageWidth * imageHeight * imageChannels * sizeof(float),hipMemcpyDeviceToHost);
//dispRes(hostOutputImageDataCPU);
dispRes(hostOutputImageData);
free(hostInputImageData);
free(hostOutputImageData);
free(hostOutputImageDataCPU);
free(hostMaskData);
hipFree(deviceInputImageData);
hipFree(deviceOutputImageData);
hipFree(deviceMaskData);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#define WIDTH 10
#define HEIGHT 10
#define channels 3
#define Mask_width 5
#define Mask_radius Mask_width/2
#define O_TILE_WIDTH 12
#define BLOCK_WIDTH (O_TILE_WIDTH+Mask_width-1)
#define min(x,y) ((x)<(y)?(x):(y))
#define max(x,y) ((x)>(y)?(x):(y))
#define clamp(x) (min(max((x),0.0),1.0))
void imageConvolution(float *input,float *output,const float* __restrict__ M,int width, int height, int ch)
{
int i=0,j=0,k=0,x=0,y=0,xOffset=0,yOffset=0;
float accum =0.0,maskValue =0.0,imagePixel =0.0;
for( i=0 ;i<height;i++){
for( j=0;j< width;j++){
for(k=0;k<ch;k++){
accum = 0;
for(y = 0 ;y< Mask_width;y++){
for(x= 0;x< Mask_width; x++){
xOffset = j + x - Mask_radius;
yOffset = i + y - Mask_radius;
if (xOffset>=0 && xOffset < width && yOffset>=0 && yOffset < height){
imagePixel = input[(yOffset * width + xOffset) * channels + k];
maskValue = M[y*Mask_width+x];
accum += imagePixel * maskValue;
}
else
accum +=0;
}
}
output[(i * width + j)*channels + k] = accum;// (float) clamp(accum);
}
}
}
}
__global__ void imageTiledConvolution_kernel(float *input,float *output,const float * __restrict__ M,int width, int height, int ch)
{
int i=0,j=0;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row_o = blockIdx.y*O_TILE_WIDTH+ty;
int col_o = blockIdx.x*O_TILE_WIDTH+tx;
int row_i = row_o - Mask_radius;
int col_i = col_o - Mask_radius;
float cValue = 0.0f;
__shared__ float Ns[BLOCK_WIDTH][BLOCK_WIDTH][channels];
for(int chIdx=0;chIdx<ch;chIdx++){
if(row_i>=0 && row_i<height && col_i>=0 && col_i<width){
Ns[ty][tx][chIdx] = input[(row_i*width+col_i)*ch+chIdx];
}else{
Ns[ty][tx][chIdx] = 0.0f;
}
__syncthreads();
cValue = 0.0f;
if(ty<O_TILE_WIDTH && tx<O_TILE_WIDTH){
for( i=0;i<Mask_width;i++){
for( j=0;j<Mask_width;j++){
cValue +=M[i*Mask_width+j]*Ns[ty+i][tx+j][chIdx];
}
}
}
__syncthreads();
if(row_o<height && col_o<width && ty<O_TILE_WIDTH && tx<O_TILE_WIDTH)
output[(row_o*width+col_o)*ch+chIdx] = cValue;//min(max(cValue,0),1);
}
}
void loadData(float *input,float *output,float *maskData)
{
int i=0;
for(i=0;i<WIDTH*HEIGHT*channels;i++)
input[i] = 1.0;
for(i=0;i<WIDTH*HEIGHT*channels;i++)
output[i] = 0.0;
for(i=0;i<Mask_width *Mask_width ;i++)
maskData[i] = 1.0;
}
void dispRes(float *arr)
{
int i=0,j=0,k=0;
printf("Results of the calculation\n");
for(k=0;k<channels;k++){
for(i=0;i<HEIGHT;i++){
for(j=0;j<WIDTH;j++){
printf("%2.1f ",arr[(i*WIDTH+j)*channels+k]);
}
printf("\n");
}
printf("k = %d\n",k);system("pause");
}
}
int main(void)
{
int maskRows = Mask_width;
int maskColumns = Mask_width;
int imageChannels = channels;
int imageWidth = WIDTH;
int imageHeight = HEIGHT;
float * hostInputImageData;
float * hostOutputImageData;
float * hostOutputImageDataCPU;
float * hostMaskData;
float * deviceInputImageData;
float * deviceOutputImageData;
float * deviceMaskData;
//allocate Memory on the host
hostInputImageData = (float*)malloc(imageWidth*imageHeight*channels*sizeof(float));
hostOutputImageData = (float*)malloc(imageWidth*imageHeight*channels*sizeof(float));
hostOutputImageDataCPU = (float*)malloc(imageWidth*imageHeight*channels*sizeof(float));
hostMaskData = (float*)malloc(Mask_width*Mask_width*sizeof(float));
//load data to host memory
loadData(hostInputImageData,hostOutputImageData,hostMaskData);
//cuda memory allocation on the device
hipMalloc((void **) &deviceInputImageData, imageWidth * imageHeight * imageChannels * sizeof(float));
hipMalloc((void **) &deviceOutputImageData, imageWidth * imageHeight * imageChannels * sizeof(float));
hipMalloc((void **) &deviceMaskData, maskRows * maskColumns * sizeof(float));
//cuda memory copy from host to device
hipMemcpy(deviceInputImageData,hostInputImageData,imageWidth * imageHeight * imageChannels * sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(deviceMaskData,hostMaskData,maskRows * maskColumns * sizeof(float),hipMemcpyHostToDevice);
dim3 DimGrid((imageWidth-1)/O_TILE_WIDTH+1,(imageHeight-1)/O_TILE_WIDTH+1,1);
dim3 DimBlock(BLOCK_WIDTH, BLOCK_WIDTH,1);
imageTiledConvolution_kernel<<<DimGrid,DimBlock>>>(deviceInputImageData,deviceOutputImageData,deviceMaskData,imageWidth,imageHeight,imageChannels);
imageConvolution(hostInputImageData,hostOutputImageDataCPU,hostMaskData,imageWidth,imageHeight,imageChannels);
//cuda memory copy from device to host
hipMemcpy(hostOutputImageData,deviceOutputImageData,imageWidth * imageHeight * imageChannels * sizeof(float),hipMemcpyDeviceToHost);
//dispRes(hostOutputImageDataCPU);
dispRes(hostOutputImageData);
free(hostInputImageData);
free(hostOutputImageData);
free(hostOutputImageDataCPU);
free(hostMaskData);
hipFree(deviceInputImageData);
hipFree(deviceOutputImageData);
hipFree(deviceMaskData);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z28imageTiledConvolution_kernelPfS_PKfiii
.globl _Z28imageTiledConvolution_kernelPfS_PKfiii
.p2align 8
.type _Z28imageTiledConvolution_kernelPfS_PKfiii,@function
_Z28imageTiledConvolution_kernelPfS_PKfiii:
s_load_b32 s5, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s5, 1
s_cbranch_scc1 .LBB0_12
s_load_b256 s[16:23], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_mov_b32 s7, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s14, 12, v[1:2]
v_mad_u64_u32 v[5:6], null, s15, 12, v[4:5]
v_max_u32_e32 v6, v4, v1
v_mul_u32_u24_e32 v0, 12, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v3, -2, v2
v_cmp_gt_u32_e32 vcc_lo, 12, v6
v_add_nc_u32_e32 v9, -2, v5
v_min_i32_e32 v1, v2, v5
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s1, s22, v3
s_delay_alu instid0(VALU_DEP_3)
v_mad_u64_u32 v[6:7], null, v9, s22, v[3:4]
v_mad_u64_u32 v[7:8], null, v5, s22, v[2:3]
v_cmp_gt_i32_e64 s0, s23, v9
v_cmp_gt_i32_e64 s2, s23, v5
v_cmp_gt_i32_e64 s3, s22, v2
v_cmp_lt_i32_e64 s4, 1, v1
v_mul_lo_u32 v1, v6, s5
v_mad_u32_u24 v3, v4, 0xc0, v0
v_mul_lo_u32 v2, v7, s5
v_mul_u32_u24_e32 v4, 0xc0, v4
s_and_b32 s0, s0, s1
s_and_b32 s1, s3, s2
s_and_b32 s4, s0, s4
s_and_b32 s6, vcc_lo, s1
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v3, 4, v3
s_add_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s7, s5
s_cbranch_scc1 .LBB0_12
.LBB0_3:
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, 0
s_and_saveexec_b32 s1, s4
s_cbranch_execz .LBB0_5
v_add_nc_u32_e32 v6, s7, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s0, s16, v6
v_add_co_ci_u32_e64 v7, s0, s17, v7, s0
global_load_b32 v6, v[6:7], off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b32 s0, s7, 2
s_delay_alu instid0(SALU_CYCLE_1)
v_add3_u32 v7, v4, v0, s0
s_waitcnt vmcnt(0)
ds_store_b32 v7, v6
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s8, vcc_lo
s_cbranch_execz .LBB0_10
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, v3
s_mov_b32 s9, 0
s_mov_b64 s[0:1], s[20:21]
.p2align 6
.LBB0_7:
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b64 s[2:3], s[0:1]
s_mov_b32 s10, 0
.LBB0_8:
s_delay_alu instid0(SALU_CYCLE_1)
v_add_nc_u32_e32 v7, s10, v6
s_load_b32 s11, s[2:3], 0x0
s_add_i32 s10, s10, 12
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
ds_load_b32 v7, v7
s_cmp_lg_u32 s10, 60
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v5, s11, v7
s_cbranch_scc1 .LBB0_8
s_add_i32 s9, s9, 1
v_add_nc_u32_e32 v6, 0xc0, v6
s_add_u32 s0, s0, 20
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s9, 5
s_cbranch_scc1 .LBB0_7
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s8
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s1, s6
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v6, s7, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s0, s18, v6
v_add_co_ci_u32_e64 v7, s0, s19, v7, s0
global_store_b32 v[6:7], v5, off
s_branch .LBB0_2
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z28imageTiledConvolution_kernelPfS_PKfiii
.amdhsa_group_segment_fixed_size 3072
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z28imageTiledConvolution_kernelPfS_PKfiii, .Lfunc_end0-_Z28imageTiledConvolution_kernelPfS_PKfiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 3072
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z28imageTiledConvolution_kernelPfS_PKfiii
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z28imageTiledConvolution_kernelPfS_PKfiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#define WIDTH 10
#define HEIGHT 10
#define channels 3
#define Mask_width 5
#define Mask_radius Mask_width/2
#define O_TILE_WIDTH 12
#define BLOCK_WIDTH (O_TILE_WIDTH+Mask_width-1)
#define min(x,y) ((x)<(y)?(x):(y))
#define max(x,y) ((x)>(y)?(x):(y))
#define clamp(x) (min(max((x),0.0),1.0))
void imageConvolution(float *input,float *output,const float* __restrict__ M,int width, int height, int ch)
{
int i=0,j=0,k=0,x=0,y=0,xOffset=0,yOffset=0;
float accum =0.0,maskValue =0.0,imagePixel =0.0;
for( i=0 ;i<height;i++){
for( j=0;j< width;j++){
for(k=0;k<ch;k++){
accum = 0;
for(y = 0 ;y< Mask_width;y++){
for(x= 0;x< Mask_width; x++){
xOffset = j + x - Mask_radius;
yOffset = i + y - Mask_radius;
if (xOffset>=0 && xOffset < width && yOffset>=0 && yOffset < height){
imagePixel = input[(yOffset * width + xOffset) * channels + k];
maskValue = M[y*Mask_width+x];
accum += imagePixel * maskValue;
}
else
accum +=0;
}
}
output[(i * width + j)*channels + k] = accum;// (float) clamp(accum);
}
}
}
}
__global__ void imageTiledConvolution_kernel(float *input,float *output,const float * __restrict__ M,int width, int height, int ch)
{
int i=0,j=0;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row_o = blockIdx.y*O_TILE_WIDTH+ty;
int col_o = blockIdx.x*O_TILE_WIDTH+tx;
int row_i = row_o - Mask_radius;
int col_i = col_o - Mask_radius;
float cValue = 0.0f;
__shared__ float Ns[BLOCK_WIDTH][BLOCK_WIDTH][channels];
for(int chIdx=0;chIdx<ch;chIdx++){
if(row_i>=0 && row_i<height && col_i>=0 && col_i<width){
Ns[ty][tx][chIdx] = input[(row_i*width+col_i)*ch+chIdx];
}else{
Ns[ty][tx][chIdx] = 0.0f;
}
__syncthreads();
cValue = 0.0f;
if(ty<O_TILE_WIDTH && tx<O_TILE_WIDTH){
for( i=0;i<Mask_width;i++){
for( j=0;j<Mask_width;j++){
cValue +=M[i*Mask_width+j]*Ns[ty+i][tx+j][chIdx];
}
}
}
__syncthreads();
if(row_o<height && col_o<width && ty<O_TILE_WIDTH && tx<O_TILE_WIDTH)
output[(row_o*width+col_o)*ch+chIdx] = cValue;//min(max(cValue,0),1);
}
}
void loadData(float *input,float *output,float *maskData)
{
int i=0;
for(i=0;i<WIDTH*HEIGHT*channels;i++)
input[i] = 1.0;
for(i=0;i<WIDTH*HEIGHT*channels;i++)
output[i] = 0.0;
for(i=0;i<Mask_width *Mask_width ;i++)
maskData[i] = 1.0;
}
void dispRes(float *arr)
{
int i=0,j=0,k=0;
printf("Results of the calculation\n");
for(k=0;k<channels;k++){
for(i=0;i<HEIGHT;i++){
for(j=0;j<WIDTH;j++){
printf("%2.1f ",arr[(i*WIDTH+j)*channels+k]);
}
printf("\n");
}
printf("k = %d\n",k);system("pause");
}
}
int main(void)
{
int maskRows = Mask_width;
int maskColumns = Mask_width;
int imageChannels = channels;
int imageWidth = WIDTH;
int imageHeight = HEIGHT;
float * hostInputImageData;
float * hostOutputImageData;
float * hostOutputImageDataCPU;
float * hostMaskData;
float * deviceInputImageData;
float * deviceOutputImageData;
float * deviceMaskData;
//allocate Memory on the host
hostInputImageData = (float*)malloc(imageWidth*imageHeight*channels*sizeof(float));
hostOutputImageData = (float*)malloc(imageWidth*imageHeight*channels*sizeof(float));
hostOutputImageDataCPU = (float*)malloc(imageWidth*imageHeight*channels*sizeof(float));
hostMaskData = (float*)malloc(Mask_width*Mask_width*sizeof(float));
//load data to host memory
loadData(hostInputImageData,hostOutputImageData,hostMaskData);
//cuda memory allocation on the device
hipMalloc((void **) &deviceInputImageData, imageWidth * imageHeight * imageChannels * sizeof(float));
hipMalloc((void **) &deviceOutputImageData, imageWidth * imageHeight * imageChannels * sizeof(float));
hipMalloc((void **) &deviceMaskData, maskRows * maskColumns * sizeof(float));
//cuda memory copy from host to device
hipMemcpy(deviceInputImageData,hostInputImageData,imageWidth * imageHeight * imageChannels * sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(deviceMaskData,hostMaskData,maskRows * maskColumns * sizeof(float),hipMemcpyHostToDevice);
dim3 DimGrid((imageWidth-1)/O_TILE_WIDTH+1,(imageHeight-1)/O_TILE_WIDTH+1,1);
dim3 DimBlock(BLOCK_WIDTH, BLOCK_WIDTH,1);
imageTiledConvolution_kernel<<<DimGrid,DimBlock>>>(deviceInputImageData,deviceOutputImageData,deviceMaskData,imageWidth,imageHeight,imageChannels);
imageConvolution(hostInputImageData,hostOutputImageDataCPU,hostMaskData,imageWidth,imageHeight,imageChannels);
//cuda memory copy from device to host
hipMemcpy(hostOutputImageData,deviceOutputImageData,imageWidth * imageHeight * imageChannels * sizeof(float),hipMemcpyDeviceToHost);
//dispRes(hostOutputImageDataCPU);
dispRes(hostOutputImageData);
free(hostInputImageData);
free(hostOutputImageData);
free(hostOutputImageDataCPU);
free(hostMaskData);
hipFree(deviceInputImageData);
hipFree(deviceOutputImageData);
hipFree(deviceMaskData);
return 0;
} | .text
.file "kernel.hip"
.globl _Z16imageConvolutionPfS_PKfiii # -- Begin function _Z16imageConvolutionPfS_PKfiii
.p2align 4, 0x90
.type _Z16imageConvolutionPfS_PKfiii,@function
_Z16imageConvolutionPfS_PKfiii: # @_Z16imageConvolutionPfS_PKfiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, -76(%rsp) # 4-byte Spill
movl %ecx, -80(%rsp) # 4-byte Spill
movq %rdx, -24(%rsp) # 8-byte Spill
movq %rsi, -56(%rsp) # 8-byte Spill
movq %rdi, -72(%rsp) # 8-byte Spill
testl %r8d, %r8d
jle .LBB0_18
# %bb.1: # %.preheader53.lr.ph
movslq -80(%rsp), %rax # 4-byte Folded Reload
movl %r8d, %r8d
movl %eax, %ecx
movq %rcx, -40(%rsp) # 8-byte Spill
movl -76(%rsp), %ecx # 4-byte Reload
movq %rcx, -32(%rsp) # 8-byte Spill
leaq (,%rax,8), %rcx
leaq (%rcx,%rcx,2), %rcx
subq %rcx, -72(%rsp) # 8-byte Folded Spill
leaq (,%rax,4), %rcx
leaq (%rcx,%rcx,2), %rbx
xorl %r14d, %r14d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_17: # %._crit_edge60
# in Loop: Header=BB0_2 Depth=1
incq %r14
addq %rbx, -72(%rsp) # 8-byte Folded Spill
cmpq %r8, %r14
je .LBB0_18
.LBB0_2: # %.preheader53
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
# Child Loop BB0_6 Depth 3
# Child Loop BB0_7 Depth 4
# Child Loop BB0_8 Depth 5
cmpl $0, -80(%rsp) # 4-byte Folded Reload
jle .LBB0_17
# %bb.3: # %.preheader52.lr.ph
# in Loop: Header=BB0_2 Depth=1
movq %r14, %rcx
imulq %rax, %rcx
movq %rcx, -48(%rsp) # 8-byte Spill
movq -72(%rsp), %rcx # 8-byte Reload
movq %rcx, -64(%rsp) # 8-byte Spill
xorl %r11d, %r11d
jmp .LBB0_4
.p2align 4, 0x90
.LBB0_16: # %._crit_edge
# in Loop: Header=BB0_4 Depth=2
incq %r11
addq $12, -64(%rsp) # 8-byte Folded Spill
cmpq -40(%rsp), %r11 # 8-byte Folded Reload
je .LBB0_17
.LBB0_4: # %.preheader52
# Parent Loop BB0_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_6 Depth 3
# Child Loop BB0_7 Depth 4
# Child Loop BB0_8 Depth 5
cmpl $0, -76(%rsp) # 4-byte Folded Reload
jle .LBB0_16
# %bb.5: # %.preheader51.lr.ph
# in Loop: Header=BB0_4 Depth=2
movq -48(%rsp), %rcx # 8-byte Reload
addq %r11, %rcx
leaq (%rcx,%rcx,2), %rcx
movq -56(%rsp), %rdx # 8-byte Reload
leaq (%rdx,%rcx,4), %rcx
movq %rcx, -16(%rsp) # 8-byte Spill
movq -64(%rsp), %r12 # 8-byte Reload
xorl %ecx, %ecx
jmp .LBB0_6
.p2align 4, 0x90
.LBB0_15: # in Loop: Header=BB0_6 Depth=3
movq -16(%rsp), %rdx # 8-byte Reload
movss %xmm0, (%rdx,%rcx,4)
incq %rcx
movq -8(%rsp), %r12 # 8-byte Reload
addq $4, %r12
cmpq -32(%rsp), %rcx # 8-byte Folded Reload
je .LBB0_16
.LBB0_6: # %.preheader51
# Parent Loop BB0_2 Depth=1
# Parent Loop BB0_4 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB0_7 Depth 4
# Child Loop BB0_8 Depth 5
xorps %xmm0, %xmm0
movq %r12, -8(%rsp) # 8-byte Spill
movq -24(%rsp), %rbp # 8-byte Reload
xorl %esi, %esi
jmp .LBB0_7
.p2align 4, 0x90
.LBB0_14: # in Loop: Header=BB0_7 Depth=4
incq %rsi
addq $20, %rbp
addq %rbx, %r12
cmpq $5, %rsi
je .LBB0_15
.LBB0_7: # %.preheader
# Parent Loop BB0_2 Depth=1
# Parent Loop BB0_4 Depth=2
# Parent Loop BB0_6 Depth=3
# => This Loop Header: Depth=4
# Child Loop BB0_8 Depth 5
leaq (%rsi,%r14), %r9
leaq (%rsi,%r14), %r15
addq $-2, %r15
movq $-6, %r10
movq %r11, %r13
movq %rbp, %rdx
jmp .LBB0_8
.p2align 4, 0x90
.LBB0_13: # in Loop: Header=BB0_8 Depth=5
addss %xmm1, %xmm0
addq $4, %rdx
incq %r13
addq $3, %r10
cmpq $9, %r10
je .LBB0_14
.LBB0_8: # Parent Loop BB0_2 Depth=1
# Parent Loop BB0_4 Depth=2
# Parent Loop BB0_6 Depth=3
# Parent Loop BB0_7 Depth=4
# => This Inner Loop Header: Depth=5
xorps %xmm1, %xmm1
cmpq $2, %r13
jb .LBB0_13
# %bb.9: # in Loop: Header=BB0_8 Depth=5
leaq -2(%r13), %rdi
cmpq %rax, %rdi
jge .LBB0_13
# %bb.10: # in Loop: Header=BB0_8 Depth=5
cmpq $2, %r9
jb .LBB0_13
# %bb.11: # in Loop: Header=BB0_8 Depth=5
cmpq %r8, %r15
jge .LBB0_13
# %bb.12: # in Loop: Header=BB0_8 Depth=5
movss (%r12,%r10,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rdx), %xmm1
jmp .LBB0_13
.LBB0_18: # %._crit_edge62
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z16imageConvolutionPfS_PKfiii, .Lfunc_end0-_Z16imageConvolutionPfS_PKfiii
.cfi_endproc
# -- End function
.globl _Z43__device_stub__imageTiledConvolution_kernelPfS_PKfiii # -- Begin function _Z43__device_stub__imageTiledConvolution_kernelPfS_PKfiii
.p2align 4, 0x90
.type _Z43__device_stub__imageTiledConvolution_kernelPfS_PKfiii,@function
_Z43__device_stub__imageTiledConvolution_kernelPfS_PKfiii: # @_Z43__device_stub__imageTiledConvolution_kernelPfS_PKfiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z28imageTiledConvolution_kernelPfS_PKfiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z43__device_stub__imageTiledConvolution_kernelPfS_PKfiii, .Lfunc_end1-_Z43__device_stub__imageTiledConvolution_kernelPfS_PKfiii
.cfi_endproc
# -- End function
.globl _Z8loadDataPfS_S_ # -- Begin function _Z8loadDataPfS_S_
.p2align 4, 0x90
.type _Z8loadDataPfS_S_,@function
_Z8loadDataPfS_S_: # @_Z8loadDataPfS_S_
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdx, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rdi,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $300, %rax # imm = 0x12C
jne .LBB2_1
# %bb.2: # %.preheader11.preheader
xorl %r14d, %r14d
movl $1200, %edx # imm = 0x4B0
movq %rsi, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB2_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%r14,4) # imm = 0x3F800000
incq %r14
cmpq $25, %r14
jne .LBB2_3
# %bb.4:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z8loadDataPfS_S_, .Lfunc_end2-_Z8loadDataPfS_S_
.cfi_endproc
# -- End function
.globl _Z7dispResPf # -- Begin function _Z7dispResPf
.p2align 4, 0x90
.type _Z7dispResPf,@function
_Z7dispResPf: # @_Z7dispResPf
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl $.Lstr, %edi
callq puts@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_1: # %.preheader12
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
# Child Loop BB3_3 Depth 3
movq %rbx, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_2: # %.preheader
# Parent Loop BB3_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_3 Depth 3
movq $-120, %r13
.p2align 4, 0x90
.LBB3_3: # Parent Loop BB3_1 Depth=1
# Parent Loop BB3_2 Depth=2
# => This Inner Loop Header: Depth=3
movss 120(%r15,%r13), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
addq $12, %r13
jne .LBB3_3
# %bb.4: # in Loop: Header=BB3_2 Depth=2
movl $10, %edi
callq putchar@PLT
incq %r12
addq $120, %r15
cmpq $10, %r12
jne .LBB3_2
# %bb.5: # in Loop: Header=BB3_1 Depth=1
movl $.L.str.3, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.4, %edi
callq system
incq %r14
addq $4, %rbx
cmpq $3, %r14
jne .LBB3_1
# %bb.6:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z7dispResPf, .Lfunc_end3-_Z7dispResPf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1200, %edi # imm = 0x4B0
callq malloc
movq %rax, %rbx
movl $1200, %edi # imm = 0x4B0
callq malloc
movq %rax, %r12
movl $100, %edi
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $300, %rax # imm = 0x12C
jne .LBB4_1
# %bb.2: # %.preheader11.preheader.i
xorl %r14d, %r14d
movl $1200, %edx # imm = 0x4B0
movq %r12, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB4_3: # %.preheader.i
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%r15,%r14,4) # imm = 0x3F800000
incq %r14
cmpq $25, %r14
jne .LBB4_3
# %bb.4: # %_Z8loadDataPfS_S_.exit
leaq 16(%rsp), %rdi
movl $1200, %esi # imm = 0x4B0
callq hipMalloc
leaq 8(%rsp), %rdi
movl $1200, %esi # imm = 0x4B0
callq hipMalloc
movq %rsp, %rdi
movl $100, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $1200, %edx # imm = 0x4B0
movq %rbx, 48(%rsp) # 8-byte Spill
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $100, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $10, 36(%rsp)
movl $10, 32(%rsp)
movl $3, 28(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 28(%rsp), %rax
movq %rax, 168(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z28imageTiledConvolution_kernelPfS_PKfiii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_6: # %_Z16imageConvolutionPfS_PKfiii.exit
movq 8(%rsp), %rsi
movl $1200, %edx # imm = 0x4B0
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
movq %r12, 40(%rsp) # 8-byte Spill
movq %r12, %r13
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_7: # %.preheader12.i
# =>This Loop Header: Depth=1
# Child Loop BB4_8 Depth 2
# Child Loop BB4_9 Depth 3
movq %r13, %rbp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_8: # %.preheader.i53
# Parent Loop BB4_7 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_9 Depth 3
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_9: # Parent Loop BB4_7 Depth=1
# Parent Loop BB4_8 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rbp,%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
addq $12, %rbx
cmpq $120, %rbx
jne .LBB4_9
# %bb.10: # in Loop: Header=BB4_8 Depth=2
movl $10, %edi
callq putchar@PLT
incq %r14
addq $120, %rbp
cmpq $10, %r14
jne .LBB4_8
# %bb.11: # in Loop: Header=BB4_7 Depth=1
movl $.L.str.3, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.4, %edi
callq system
incq %r12
addq $4, %r13
cmpq $3, %r12
jne .LBB4_7
# %bb.12: # %_Z7dispResPf.exit
movq 48(%rsp), %rdi # 8-byte Reload
callq free
movq 40(%rsp), %rdi # 8-byte Reload
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28imageTiledConvolution_kernelPfS_PKfiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z28imageTiledConvolution_kernelPfS_PKfiii,@object # @_Z28imageTiledConvolution_kernelPfS_PKfiii
.section .rodata,"a",@progbits
.globl _Z28imageTiledConvolution_kernelPfS_PKfiii
.p2align 3, 0x0
_Z28imageTiledConvolution_kernelPfS_PKfiii:
.quad _Z43__device_stub__imageTiledConvolution_kernelPfS_PKfiii
.size _Z28imageTiledConvolution_kernelPfS_PKfiii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%2.1f "
.size .L.str.1, 7
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "k = %d\n"
.size .L.str.3, 8
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "pause"
.size .L.str.4, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z28imageTiledConvolution_kernelPfS_PKfiii"
.size .L__unnamed_1, 43
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Results of the calculation"
.size .Lstr, 27
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z43__device_stub__imageTiledConvolution_kernelPfS_PKfiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z28imageTiledConvolution_kernelPfS_PKfiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z28imageTiledConvolution_kernelPfS_PKfiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R0, c[0x0][0x180] ; /* 0x0000600000007a02 */
/* 0x000fc80000000f00 */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002200 */
/*0050*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0080*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e680000002100 */
/*0090*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000ea20000002500 */
/*00a0*/ IMAD R0, R0, 0xc, R5 ; /* 0x0000000c00007824 */
/* 0x001fc800078e0205 */
/*00b0*/ IMAD R3, R0.reuse, c[0x0][0x178], R11 ; /* 0x00005e0000037a24 */
/* 0x042fe200078e020b */
/*00c0*/ IADD3 R2, R0.reuse, -0x2, RZ ; /* 0xfffffffe00027810 */
/* 0x040fe40007ffe0ff */
/*00d0*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fe20003f26270 */
/*00e0*/ IMAD R3, R6, 0xc, R3 ; /* 0x0000000c06037824 */
/* 0x004fe200078e0203 */
/*00f0*/ ISETP.GE.AND P0, PT, R2.reuse, c[0x0][0x17c], PT ; /* 0x00005f0002007a0c */
/* 0x040fe20003f06270 */
/*0100*/ IMAD R4, R2, c[0x0][0x178], R11.reuse ; /* 0x00005e0002047a24 */
/* 0x100fe200078e020b */
/*0110*/ ISETP.GE.AND P3, PT, R11, 0xc, PT ; /* 0x0000000c0b00780c */
/* 0x000fe20003f66270 */
/*0120*/ IMAD R2, R6, 0xc, R11 ; /* 0x0000000c06027824 */
/* 0x000fe200078e020b */
/*0130*/ ISETP.GT.AND P0, PT, R0, 0x1, !P0 ; /* 0x000000010000780c */
/* 0x000fe20004704270 */
/*0140*/ IMAD R4, R6, 0xc, R4 ; /* 0x0000000c06047824 */
/* 0x000fc400078e0204 */
/*0150*/ IMAD R3, R3, c[0x0][0x180], RZ ; /* 0x0000600003037a24 */
/* 0x000fe200078e02ff */
/*0160*/ ISETP.LT.AND P1, PT, R2, c[0x0][0x178], !P1 ; /* 0x00005e0002007a0c */
/* 0x000fe40004f21270 */
/*0170*/ IADD3 R4, R4, -0x2, RZ ; /* 0xfffffffe04047810 */
/* 0x000fe20007ffe0ff */
/*0180*/ IMAD.WIDE R6, R3, R8.reuse, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x080fe200078e0208 */
/*0190*/ ISETP.GT.AND P2, PT, R2, 0x1, P0 ; /* 0x000000010200780c */
/* 0x000fe40000744270 */
/*01a0*/ ISETP.LT.AND P0, PT, R5.reuse, 0xc, !P3 ; /* 0x0000000c0500780c */
/* 0x040fe20005f01270 */
/*01b0*/ IMAD R4, R4, c[0x0][0x180], RZ ; /* 0x0000600004047a24 */
/* 0x000fe200078e02ff */
/*01c0*/ ISETP.LT.AND P1, PT, R5.reuse, 0xc, P1 ; /* 0x0000000c0500780c */
/* 0x040fe40000f21270 */
/*01d0*/ LEA R5, R5, R11, 0x4 ; /* 0x0000000b05057211 */
/* 0x000fe200078e20ff */
/*01e0*/ IMAD.WIDE R8, R4, R8, c[0x0][0x160] ; /* 0x0000580004087625 */
/* 0x000fe200078e0208 */
/*01f0*/ IADD3 R2, R2, -0x2, RZ ; /* 0xfffffffe02027810 */
/* 0x000fc40007ffe0ff */
/*0200*/ MOV R0, R6 ; /* 0x0000000600007202 */
/* 0x000fe20000000f00 */
/*0210*/ IMAD R10, R5, 0xc, RZ ; /* 0x0000000c050a7824 */
/* 0x000fe200078e02ff */
/*0220*/ MOV R6, R8 ; /* 0x0000000800067202 */
/* 0x000fe20000000f00 */
/*0230*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x000fe200000001ff */
/*0240*/ ISETP.LT.AND P1, PT, R11, 0xc, P1 ; /* 0x0000000c0b00780c */
/* 0x000fe40000f21270 */
/*0250*/ ISETP.LT.AND P2, PT, R2, c[0x0][0x178], P2 ; /* 0x00005e0002007a0c */
/* 0x000fda0001741270 */
/*0260*/ @P2 MOV R2, R6 ; /* 0x0000000600022202 */
/* 0x001fe40000000f00 */
/*0270*/ @P2 MOV R3, R9 ; /* 0x0000000900032202 */
/* 0x000fca0000000f00 */
/*0280*/ @P2 LDG.E R5, [R2.64] ; /* 0x0000000402052981 */
/* 0x0000a2000c1e1900 */
/*0290*/ BSSY B0, 0x7f0 ; /* 0x0000055000007945 */
/* 0x000fe20003800000 */
/*02a0*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fe40000000f00 */
/*02b0*/ @!P2 STS [R10], RZ ; /* 0x000000ff0a00a388 */
/* 0x0003e20000000800 */
/*02c0*/ @P1 MOV R2, R0 ; /* 0x0000000000021202 */
/* 0x001fe40000000f00 */
/*02d0*/ @P1 MOV R3, R7 ; /* 0x0000000700031202 */
/* 0x000fe20000000f00 */
/*02e0*/ @P2 STS [R10], R5 ; /* 0x000000050a002388 */
/* 0x0043e80000000800 */
/*02f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0300*/ @!P0 BRA 0x7e0 ; /* 0x000004d000008947 */
/* 0x000fea0003800000 */
/*0310*/ MOV R4, c[0x0][0x170] ; /* 0x00005c0000047a02 */
/* 0x002fe20000000f00 */
/*0320*/ LDS R28, [R10] ; /* 0x000000000a1c7984 */
/* 0x000e220000000800 */
/*0330*/ MOV R5, c[0x0][0x174] ; /* 0x00005d0000057a02 */
/* 0x000fc60000000f00 */
/*0340*/ LDS R21, [R10+0xc] ; /* 0x00000c000a157984 */
/* 0x000e680000000800 */
/*0350*/ LDG.E.CONSTANT R15, [R4.64] ; /* 0x00000004040f7981 */
/* 0x000e28000c1e9900 */
/*0360*/ LDG.E.CONSTANT R23, [R4.64+0x4] ; /* 0x0000040404177981 */
/* 0x000e68000c1e9900 */
/*0370*/ LDG.E.CONSTANT R16, [R4.64+0x8] ; /* 0x0000080404107981 */
/* 0x000ea8000c1e9900 */
/*0380*/ LDG.E.CONSTANT R17, [R4.64+0xc] ; /* 0x00000c0404117981 */
/* 0x000ee8000c1e9900 */
/*0390*/ LDG.E.CONSTANT R18, [R4.64+0x10] ; /* 0x0000100404127981 */
/* 0x000f28000c1e9900 */
/*03a0*/ LDG.E.CONSTANT R20, [R4.64+0x14] ; /* 0x0000140404147981 */
/* 0x000f28000c1e9900 */
/*03b0*/ LDG.E.CONSTANT R22, [R4.64+0x18] ; /* 0x0000180404167981 */
/* 0x000f28000c1e9900 */
/*03c0*/ LDG.E.CONSTANT R24, [R4.64+0x1c] ; /* 0x00001c0404187981 */
/* 0x000f28000c1e9900 */
/*03d0*/ LDG.E.CONSTANT R11, [R4.64+0x20] ; /* 0x00002004040b7981 */
/* 0x000f28000c1e9900 */
/*03e0*/ LDG.E.CONSTANT R12, [R4.64+0x24] ; /* 0x00002404040c7981 */
/* 0x000f28000c1e9900 */
/*03f0*/ LDG.E.CONSTANT R13, [R4.64+0x28] ; /* 0x00002804040d7981 */
/* 0x000128000c1e9900 */
/*0400*/ LDS R19, [R10+0x18] ; /* 0x000018000a137984 */
/* 0x000ea80000000800 */
/*0410*/ LDG.E.CONSTANT R14, [R4.64+0x2c] ; /* 0x00002c04040e7981 */
/* 0x000128000c1e9900 */
/*0420*/ LDS R26, [R10+0x24] ; /* 0x000024000a1a7984 */
/* 0x000ee80000000800 */
/*0430*/ LDS R27, [R10+0x30] ; /* 0x000030000a1b7984 */
/* 0x000f280000000800 */
/*0440*/ LDS R25, [R10+0xd8] ; /* 0x0000d8000a197984 */
/* 0x000fe20000000800 */
/*0450*/ FFMA R15, R15, R28, RZ ; /* 0x0000001c0f0f7223 */
/* 0x001fc600000000ff */
/*0460*/ LDS R28, [R10+0x1a4] ; /* 0x0001a4000a1c7984 */
/* 0x000fe20000000800 */
/*0470*/ FFMA R23, R21, R23, R15 ; /* 0x0000001715177223 */
/* 0x002fc6000000000f */
/*0480*/ LDG.E.CONSTANT R15, [R4.64+0x30] ; /* 0x00003004040f7981 */
/* 0x000162000c1e9900 */
/*0490*/ FFMA R19, R19, R16, R23 ; /* 0x0000001013137223 */
/* 0x004fc60000000017 */
/*04a0*/ LDS R21, [R10+0xc0] ; /* 0x0000c0000a157984 */
/* 0x000e680000000800 */
/*04b0*/ LDS R23, [R10+0xcc] ; /* 0x0000cc000a177984 */
/* 0x000ea20000000800 */
/*04c0*/ FFMA R19, R26, R17, R19 ; /* 0x000000111a137223 */
/* 0x008fc60000000013 */
/*04d0*/ LDG.E.CONSTANT R16, [R4.64+0x34] ; /* 0x0000340404107981 */
/* 0x0000e8000c1e9900 */
/*04e0*/ LDG.E.CONSTANT R17, [R4.64+0x38] ; /* 0x0000380404117981 */
/* 0x0000e2000c1e9900 */
/*04f0*/ FFMA R27, R27, R18, R19 ; /* 0x000000121b1b7223 */
/* 0x010fc60000000013 */
/*0500*/ LDS R18, [R10+0xe4] ; /* 0x0000e4000a127984 */
/* 0x000f280000000800 */
/*0510*/ LDG.E.CONSTANT R19, [R4.64+0x3c] ; /* 0x00003c0404137981 */
/* 0x0000e2000c1e9900 */
/*0520*/ FFMA R27, R21, R20, R27 ; /* 0x00000014151b7223 */
/* 0x002fc6000000001b */
/*0530*/ LDS R21, [R10+0xf0] ; /* 0x0000f0000a157984 */
/* 0x000e680000000800 */
/*0540*/ LDG.E.CONSTANT R20, [R4.64+0x40] ; /* 0x0000400404147981 */
/* 0x0000e2000c1e9900 */
/*0550*/ FFMA R27, R23, R22, R27 ; /* 0x00000016171b7223 */
/* 0x004fc6000000001b */
/*0560*/ LDG.E.CONSTANT R22, [R4.64+0x44] ; /* 0x0000440404167981 */
/* 0x0000a2000c1e9900 */
/*0570*/ FFMA R27, R25, R24, R27 ; /* 0x00000018191b7223 */
/* 0x000fc6000000001b */
/*0580*/ LDG.E.CONSTANT R23, [R4.64+0x48] ; /* 0x0000480404177981 */
/* 0x0000a8000c1e9900 */
/*0590*/ LDG.E.CONSTANT R25, [R4.64+0x4c] ; /* 0x00004c0404197981 */
/* 0x0000a2000c1e9900 */
/*05a0*/ FFMA R27, R18, R11, R27 ; /* 0x0000000b121b7223 */
/* 0x010fc6000000001b */
/*05b0*/ LDG.E.CONSTANT R24, [R4.64+0x50] ; /* 0x0000500404187981 */
/* 0x000128000c1e9900 */
/*05c0*/ LDG.E.CONSTANT R18, [R4.64+0x54] ; /* 0x0000540404127981 */
/* 0x000128000c1e9900 */
/*05d0*/ LDG.E.CONSTANT R11, [R4.64+0x58] ; /* 0x00005804040b7981 */
/* 0x000122000c1e9900 */
/*05e0*/ FFMA R26, R21, R12, R27 ; /* 0x0000000c151a7223 */
/* 0x002fc6000000001b */
/*05f0*/ LDG.E.CONSTANT R12, [R4.64+0x5c] ; /* 0x00005c04040c7981 */
/* 0x000128000c1e9900 */
/*0600*/ LDG.E.CONSTANT R21, [R4.64+0x60] ; /* 0x0000600404157981 */
/* 0x000128000c1e9900 */
/*0610*/ LDS R27, [R10+0x180] ; /* 0x000180000a1b7984 */
/* 0x000e680000000800 */
/*0620*/ LDS R5, [R10+0x258] ; /* 0x000258000a057984 */
/* 0x001fe80000000800 */
/*0630*/ LDS R4, [R10+0x264] ; /* 0x000264000a047984 */
/* 0x000fe20000000800 */
/*0640*/ FFMA R13, R27, R13, R26 ; /* 0x0000000d1b0d7223 */
/* 0x002fc6000000001a */
/*0650*/ LDS R26, [R10+0x18c] ; /* 0x00018c000a1a7984 */
/* 0x000e280000000800 */
/*0660*/ LDS R27, [R10+0x198] ; /* 0x000198000a1b7984 */
/* 0x000f620000000800 */
/*0670*/ FFMA R26, R26, R14, R13 ; /* 0x0000000e1a1a7223 */
/* 0x001fc6000000000d */
/*0680*/ LDS R14, [R10+0x1b0] ; /* 0x0001b0000a0e7984 */
/* 0x000e280000000800 */
/*0690*/ LDS R13, [R10+0x24c] ; /* 0x00024c000a0d7984 */
/* 0x000fe20000000800 */
/*06a0*/ FFMA R15, R27, R15, R26 ; /* 0x0000000f1b0f7223 */
/* 0x020fc6000000001a */
/*06b0*/ LDS R26, [R10+0x240] ; /* 0x000240000a1a7984 */
/* 0x000e620000000800 */
/*06c0*/ FFMA R15, R28, R16, R15 ; /* 0x000000101c0f7223 */
/* 0x008fc6000000000f */
/*06d0*/ LDS R16, [R10+0x318] ; /* 0x000318000a107984 */
/* 0x000fe20000000800 */
/*06e0*/ FFMA R17, R14, R17, R15 ; /* 0x000000110e117223 */
/* 0x001fc6000000000f */
/*06f0*/ LDS R14, [R10+0x270] ; /* 0x000270000a0e7984 */
/* 0x000e280000000800 */
/*0700*/ LDS R15, [R10+0x300] ; /* 0x000300000a0f7984 */
/* 0x000f220000000800 */
/*0710*/ FFMA R19, R26, R19, R17 ; /* 0x000000131a137223 */
/* 0x002fc60000000011 */
/*0720*/ LDS R17, [R10+0x30c] ; /* 0x00030c000a117984 */
/* 0x000e620000000800 */
/*0730*/ FFMA R19, R13, R20, R19 ; /* 0x000000140d137223 */
/* 0x000fc60000000013 */
/*0740*/ LDS R13, [R10+0x324] ; /* 0x000324000a0d7984 */
/* 0x000ee20000000800 */
/*0750*/ FFMA R5, R5, R22, R19 ; /* 0x0000001605057223 */
/* 0x004fc60000000013 */
/*0760*/ LDS R20, [R10+0x330] ; /* 0x000330000a147984 */
/* 0x000ea20000000800 */
/*0770*/ FFMA R4, R4, R23, R5 ; /* 0x0000001704047223 */
/* 0x000fc80000000005 */
/*0780*/ FFMA R4, R14, R25, R4 ; /* 0x000000190e047223 */
/* 0x001fc80000000004 */
/*0790*/ FFMA R4, R15, R24, R4 ; /* 0x000000180f047223 */
/* 0x010fc80000000004 */
/*07a0*/ FFMA R4, R17, R18, R4 ; /* 0x0000001211047223 */
/* 0x002fc80000000004 */
/*07b0*/ FFMA R4, R16, R11, R4 ; /* 0x0000000b10047223 */
/* 0x000fc80000000004 */
/*07c0*/ FFMA R4, R13, R12, R4 ; /* 0x0000000c0d047223 */
/* 0x008fc80000000004 */
/*07d0*/ FFMA R21, R20, R21, R4 ; /* 0x0000001514157223 */
/* 0x004fe40000000004 */
/*07e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*07f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0800*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fe40007ffe0ff */
/*0810*/ IADD3 R0, P3, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x000fe40007f7e0ff */
/*0820*/ ISETP.GE.AND P5, PT, R8, c[0x0][0x180], PT ; /* 0x0000600008007a0c */
/* 0x000fe40003fa6270 */
/*0830*/ IADD3 R6, P4, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007f9e0ff */
/*0840*/ IADD3.X R7, RZ, R7, RZ, P3, !PT ; /* 0x00000007ff077210 */
/* 0x000fe40001ffe4ff */
/*0850*/ IADD3.X R9, RZ, R9, RZ, P4, !PT ; /* 0x00000009ff097210 */
/* 0x000fc400027fe4ff */
/*0860*/ IADD3 R10, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fe20007ffe0ff */
/*0870*/ @P1 STG.E [R2.64], R21 ; /* 0x0000001502001986 */
/* 0x0001e8000c101904 */
/*0880*/ @!P5 BRA 0x260 ; /* 0xfffff9d00000d947 */
/* 0x000fea000383ffff */
/*0890*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08a0*/ BRA 0x8a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z28imageTiledConvolution_kernelPfS_PKfiii
.globl _Z28imageTiledConvolution_kernelPfS_PKfiii
.p2align 8
.type _Z28imageTiledConvolution_kernelPfS_PKfiii,@function
_Z28imageTiledConvolution_kernelPfS_PKfiii:
s_load_b32 s5, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s5, 1
s_cbranch_scc1 .LBB0_12
s_load_b256 s[16:23], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_mov_b32 s7, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s14, 12, v[1:2]
v_mad_u64_u32 v[5:6], null, s15, 12, v[4:5]
v_max_u32_e32 v6, v4, v1
v_mul_u32_u24_e32 v0, 12, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v3, -2, v2
v_cmp_gt_u32_e32 vcc_lo, 12, v6
v_add_nc_u32_e32 v9, -2, v5
v_min_i32_e32 v1, v2, v5
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s1, s22, v3
s_delay_alu instid0(VALU_DEP_3)
v_mad_u64_u32 v[6:7], null, v9, s22, v[3:4]
v_mad_u64_u32 v[7:8], null, v5, s22, v[2:3]
v_cmp_gt_i32_e64 s0, s23, v9
v_cmp_gt_i32_e64 s2, s23, v5
v_cmp_gt_i32_e64 s3, s22, v2
v_cmp_lt_i32_e64 s4, 1, v1
v_mul_lo_u32 v1, v6, s5
v_mad_u32_u24 v3, v4, 0xc0, v0
v_mul_lo_u32 v2, v7, s5
v_mul_u32_u24_e32 v4, 0xc0, v4
s_and_b32 s0, s0, s1
s_and_b32 s1, s3, s2
s_and_b32 s4, s0, s4
s_and_b32 s6, vcc_lo, s1
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v3, 4, v3
s_add_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s7, s5
s_cbranch_scc1 .LBB0_12
.LBB0_3:
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, 0
s_and_saveexec_b32 s1, s4
s_cbranch_execz .LBB0_5
v_add_nc_u32_e32 v6, s7, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s0, s16, v6
v_add_co_ci_u32_e64 v7, s0, s17, v7, s0
global_load_b32 v6, v[6:7], off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b32 s0, s7, 2
s_delay_alu instid0(SALU_CYCLE_1)
v_add3_u32 v7, v4, v0, s0
s_waitcnt vmcnt(0)
ds_store_b32 v7, v6
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s8, vcc_lo
s_cbranch_execz .LBB0_10
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, v3
s_mov_b32 s9, 0
s_mov_b64 s[0:1], s[20:21]
.p2align 6
.LBB0_7:
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b64 s[2:3], s[0:1]
s_mov_b32 s10, 0
.LBB0_8:
s_delay_alu instid0(SALU_CYCLE_1)
v_add_nc_u32_e32 v7, s10, v6
s_load_b32 s11, s[2:3], 0x0
s_add_i32 s10, s10, 12
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
ds_load_b32 v7, v7
s_cmp_lg_u32 s10, 60
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v5, s11, v7
s_cbranch_scc1 .LBB0_8
s_add_i32 s9, s9, 1
v_add_nc_u32_e32 v6, 0xc0, v6
s_add_u32 s0, s0, 20
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s9, 5
s_cbranch_scc1 .LBB0_7
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s8
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s1, s6
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v6, s7, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v6, s0, s18, v6
v_add_co_ci_u32_e64 v7, s0, s19, v7, s0
global_store_b32 v[6:7], v5, off
s_branch .LBB0_2
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z28imageTiledConvolution_kernelPfS_PKfiii
.amdhsa_group_segment_fixed_size 3072
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z28imageTiledConvolution_kernelPfS_PKfiii, .Lfunc_end0-_Z28imageTiledConvolution_kernelPfS_PKfiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 3072
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z28imageTiledConvolution_kernelPfS_PKfiii
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z28imageTiledConvolution_kernelPfS_PKfiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00159be7_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16imageConvolutionPfS_PKfiii
.type _Z16imageConvolutionPfS_PKfiii, @function
_Z16imageConvolutionPfS_PKfiii:
.LFB2057:
.cfi_startproc
endbr64
testl %r8d, %r8d
jle .L19
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rdi, %r14
movq %rdx, %rbp
movl %ecx, %r15d
leal (%rcx,%rcx), %eax
negl %eax
movl %eax, %edi
movl $0, %eax
movl $0, %edx
movslq %r9d, %rbx
movq %rbx, -40(%rsp)
pxor %xmm2, %xmm2
movl %edi, %ebx
movq %r14, %r13
movq %rsi, -16(%rsp)
movq %rbp, %r14
movl %r8d, %r12d
movl %r9d, %r10d
jmp .L5
.L6:
addss %xmm2, %xmm0
.L7:
addl $1, %eax
addl $3, %edx
cmpl %esi, %eax
je .L22
.L8:
movl %eax, %edi
orl %ecx, %edi
js .L6
cmpl %eax, %r15d
jle .L6
cmpl %ecx, %r12d
jle .L6
leal (%r8,%rax), %r11d
movslq %r11d, %r11
movslq %edx, %rdi
movss (%r14,%r11,4), %xmm1
mulss 0(%r13,%rdi,4), %xmm1
addss %xmm1, %xmm0
jmp .L7
.L22:
addl %r15d, %r9d
addl $5, %r10d
addl $1, %ecx
cmpl %ebp, %r10d
je .L9
.L11:
leal (%r9,%r9,2), %edx
addl %ebx, %edx
movl -64(%rsp), %eax
leal 2(%r10), %r11d
movl %r11d, %r8d
jmp .L8
.L9:
movq -72(%rsp), %rax
movl -60(%rsp), %edi
movq -56(%rsp), %rbx
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
addl $1, %edi
movq -40(%rsp), %rbx
cmpq %rbx, %rax
je .L16
.L13:
movl -48(%rsp), %r10d
negl %r10d
movl -44(%rsp), %ebx
leal -2(%rbx), %ecx
movl -32(%rsp), %r9d
pxor %xmm0, %xmm0
leal -6(%rdi), %ebx
movq %rax, -72(%rsp)
movl %edi, -60(%rsp)
jmp .L11
.L16:
movl -28(%rsp), %ecx
movl -24(%rsp), %r9d
movl -64(%rsp), %r8d
movl -20(%rsp), %r10d
.L10:
addl $1, %ecx
addl $1, %r9d
addl $1, %esi
addl $1, %r8d
cmpl %ecx, %r15d
je .L17
.L14:
testl %r10d, %r10d
jle .L10
movl %ecx, -48(%rsp)
leal (%rcx,%rcx,2), %edi
movslq %r9d, %rax
leaq (%rax,%rax,2), %rax
movq -16(%rsp), %rdx
leaq (%rdx,%rax,4), %rdx
movl $0, %eax
movl $25, %ebp
subl %ecx, %ebp
movl %ecx, -28(%rsp)
movq %rdx, -56(%rsp)
movl %r9d, -24(%rsp)
movl %r8d, -64(%rsp)
movl %r10d, -20(%rsp)
jmp .L13
.L17:
movl -44(%rsp), %edx
movl -8(%rsp), %eax
movl -4(%rsp), %ebx
.L12:
addl $1, %edx
addl %r15d, %eax
cmpl %edx, %r12d
je .L3
.L5:
testl %r15d, %r15d
jle .L12
leal (%rax,%rbx), %esi
movl %esi, -32(%rsp)
movl %eax, %r9d
movl $-2, %r8d
movl $3, %esi
movl $0, %ecx
movl %edx, -44(%rsp)
movl %eax, -8(%rsp)
movl %ebx, -4(%rsp)
jmp .L14
.L3:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2057:
.size _Z16imageConvolutionPfS_PKfiii, .-_Z16imageConvolutionPfS_PKfiii
.globl _Z8loadDataPfS_S_
.type _Z8loadDataPfS_S_, @function
_Z8loadDataPfS_S_:
.LFB2058:
.cfi_startproc
endbr64
movq %rdi, %rax
leaq 1200(%rdi), %rcx
movss .LC1(%rip), %xmm0
.L24:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L24
movq %rsi, %rax
leaq 1200(%rsi), %rcx
.L25:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L25
movq %rdx, %rax
addq $100, %rdx
movss .LC1(%rip), %xmm0
.L26:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L26
ret
.cfi_endproc
.LFE2058:
.size _Z8loadDataPfS_S_, .-_Z8loadDataPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Results of the calculation\n"
.LC3:
.string "%2.1f "
.LC4:
.string "\n"
.LC5:
.string "k = %d\n"
.LC6:
.string "pause"
.text
.globl _Z7dispResPf
.type _Z7dispResPf, @function
_Z7dispResPf:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 120(%rbx), %rax
movq %rax, (%rsp)
movl $0, %r15d
leaq .LC3(%rip), %r12
leaq .LC4(%rip), %r14
.L31:
movl %r15d, 12(%rsp)
movq (%rsp), %rbp
movl $0, %r13d
.L35:
leaq -120(%rbp), %rbx
.L32:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $12, %rbx
cmpq %rbp, %rbx
jne .L32
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $10, %r13d
addq $120, %rbp
cmpl $100, %r13d
jne .L35
movl 12(%rsp), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC6(%rip), %rdi
call system@PLT
addq $1, %r15
addq $4, (%rsp)
cmpq $3, %r15
jne .L31
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z7dispResPf, .-_Z7dispResPf
.globl _Z56__device_stub__Z28imageTiledConvolution_kernelPfS_PKfiiiPfS_PKfiii
.type _Z56__device_stub__Z28imageTiledConvolution_kernelPfS_PKfiiiPfS_PKfiii, @function
_Z56__device_stub__Z28imageTiledConvolution_kernelPfS_PKfiiiPfS_PKfiii:
.LFB2085:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movq %rdx, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L42
.L38:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L43
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z28imageTiledConvolution_kernelPfS_PKfiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L38
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z56__device_stub__Z28imageTiledConvolution_kernelPfS_PKfiiiPfS_PKfiii, .-_Z56__device_stub__Z28imageTiledConvolution_kernelPfS_PKfiiiPfS_PKfiii
.globl _Z28imageTiledConvolution_kernelPfS_PKfiii
.type _Z28imageTiledConvolution_kernelPfS_PKfiii, @function
_Z28imageTiledConvolution_kernelPfS_PKfiii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z56__device_stub__Z28imageTiledConvolution_kernelPfS_PKfiiiPfS_PKfiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z28imageTiledConvolution_kernelPfS_PKfiii, .-_Z28imageTiledConvolution_kernelPfS_PKfiii
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1200, %edi
call malloc@PLT
movq %rax, %r12
movl $1200, %edi
call malloc@PLT
movq %rax, %rbp
movl $1200, %edi
call malloc@PLT
movq %rax, %r13
movl $100, %edi
call malloc@PLT
movq %rax, %rbx
movq %rax, %rdx
movq %rbp, %rsi
movq %r12, %rdi
call _Z8loadDataPfS_S_
leaq 8(%rsp), %rdi
movl $1200, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $1200, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $100, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $1200, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $100, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $16, 44(%rsp)
movl $16, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L47:
movl $3, %r9d
movl $10, %r8d
movl $10, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq %r12, %rdi
call _Z16imageConvolutionPfS_PKfiii
movl $2, %ecx
movl $1200, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq %rbp, %rdi
call _Z7dispResPf
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L51
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
movl $3, %r9d
movl $10, %r8d
movl $10, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z56__device_stub__Z28imageTiledConvolution_kernelPfS_PKfiiiPfS_PKfiii
jmp .L47
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "_Z28imageTiledConvolution_kernelPfS_PKfiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z28imageTiledConvolution_kernelPfS_PKfiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z16imageConvolutionPfS_PKfiii # -- Begin function _Z16imageConvolutionPfS_PKfiii
.p2align 4, 0x90
.type _Z16imageConvolutionPfS_PKfiii,@function
_Z16imageConvolutionPfS_PKfiii: # @_Z16imageConvolutionPfS_PKfiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, -76(%rsp) # 4-byte Spill
movl %ecx, -80(%rsp) # 4-byte Spill
movq %rdx, -24(%rsp) # 8-byte Spill
movq %rsi, -56(%rsp) # 8-byte Spill
movq %rdi, -72(%rsp) # 8-byte Spill
testl %r8d, %r8d
jle .LBB0_18
# %bb.1: # %.preheader53.lr.ph
movslq -80(%rsp), %rax # 4-byte Folded Reload
movl %r8d, %r8d
movl %eax, %ecx
movq %rcx, -40(%rsp) # 8-byte Spill
movl -76(%rsp), %ecx # 4-byte Reload
movq %rcx, -32(%rsp) # 8-byte Spill
leaq (,%rax,8), %rcx
leaq (%rcx,%rcx,2), %rcx
subq %rcx, -72(%rsp) # 8-byte Folded Spill
leaq (,%rax,4), %rcx
leaq (%rcx,%rcx,2), %rbx
xorl %r14d, %r14d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_17: # %._crit_edge60
# in Loop: Header=BB0_2 Depth=1
incq %r14
addq %rbx, -72(%rsp) # 8-byte Folded Spill
cmpq %r8, %r14
je .LBB0_18
.LBB0_2: # %.preheader53
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
# Child Loop BB0_6 Depth 3
# Child Loop BB0_7 Depth 4
# Child Loop BB0_8 Depth 5
cmpl $0, -80(%rsp) # 4-byte Folded Reload
jle .LBB0_17
# %bb.3: # %.preheader52.lr.ph
# in Loop: Header=BB0_2 Depth=1
movq %r14, %rcx
imulq %rax, %rcx
movq %rcx, -48(%rsp) # 8-byte Spill
movq -72(%rsp), %rcx # 8-byte Reload
movq %rcx, -64(%rsp) # 8-byte Spill
xorl %r11d, %r11d
jmp .LBB0_4
.p2align 4, 0x90
.LBB0_16: # %._crit_edge
# in Loop: Header=BB0_4 Depth=2
incq %r11
addq $12, -64(%rsp) # 8-byte Folded Spill
cmpq -40(%rsp), %r11 # 8-byte Folded Reload
je .LBB0_17
.LBB0_4: # %.preheader52
# Parent Loop BB0_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_6 Depth 3
# Child Loop BB0_7 Depth 4
# Child Loop BB0_8 Depth 5
cmpl $0, -76(%rsp) # 4-byte Folded Reload
jle .LBB0_16
# %bb.5: # %.preheader51.lr.ph
# in Loop: Header=BB0_4 Depth=2
movq -48(%rsp), %rcx # 8-byte Reload
addq %r11, %rcx
leaq (%rcx,%rcx,2), %rcx
movq -56(%rsp), %rdx # 8-byte Reload
leaq (%rdx,%rcx,4), %rcx
movq %rcx, -16(%rsp) # 8-byte Spill
movq -64(%rsp), %r12 # 8-byte Reload
xorl %ecx, %ecx
jmp .LBB0_6
.p2align 4, 0x90
.LBB0_15: # in Loop: Header=BB0_6 Depth=3
movq -16(%rsp), %rdx # 8-byte Reload
movss %xmm0, (%rdx,%rcx,4)
incq %rcx
movq -8(%rsp), %r12 # 8-byte Reload
addq $4, %r12
cmpq -32(%rsp), %rcx # 8-byte Folded Reload
je .LBB0_16
.LBB0_6: # %.preheader51
# Parent Loop BB0_2 Depth=1
# Parent Loop BB0_4 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB0_7 Depth 4
# Child Loop BB0_8 Depth 5
xorps %xmm0, %xmm0
movq %r12, -8(%rsp) # 8-byte Spill
movq -24(%rsp), %rbp # 8-byte Reload
xorl %esi, %esi
jmp .LBB0_7
.p2align 4, 0x90
.LBB0_14: # in Loop: Header=BB0_7 Depth=4
incq %rsi
addq $20, %rbp
addq %rbx, %r12
cmpq $5, %rsi
je .LBB0_15
.LBB0_7: # %.preheader
# Parent Loop BB0_2 Depth=1
# Parent Loop BB0_4 Depth=2
# Parent Loop BB0_6 Depth=3
# => This Loop Header: Depth=4
# Child Loop BB0_8 Depth 5
leaq (%rsi,%r14), %r9
leaq (%rsi,%r14), %r15
addq $-2, %r15
movq $-6, %r10
movq %r11, %r13
movq %rbp, %rdx
jmp .LBB0_8
.p2align 4, 0x90
.LBB0_13: # in Loop: Header=BB0_8 Depth=5
addss %xmm1, %xmm0
addq $4, %rdx
incq %r13
addq $3, %r10
cmpq $9, %r10
je .LBB0_14
.LBB0_8: # Parent Loop BB0_2 Depth=1
# Parent Loop BB0_4 Depth=2
# Parent Loop BB0_6 Depth=3
# Parent Loop BB0_7 Depth=4
# => This Inner Loop Header: Depth=5
xorps %xmm1, %xmm1
cmpq $2, %r13
jb .LBB0_13
# %bb.9: # in Loop: Header=BB0_8 Depth=5
leaq -2(%r13), %rdi
cmpq %rax, %rdi
jge .LBB0_13
# %bb.10: # in Loop: Header=BB0_8 Depth=5
cmpq $2, %r9
jb .LBB0_13
# %bb.11: # in Loop: Header=BB0_8 Depth=5
cmpq %r8, %r15
jge .LBB0_13
# %bb.12: # in Loop: Header=BB0_8 Depth=5
movss (%r12,%r10,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rdx), %xmm1
jmp .LBB0_13
.LBB0_18: # %._crit_edge62
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z16imageConvolutionPfS_PKfiii, .Lfunc_end0-_Z16imageConvolutionPfS_PKfiii
.cfi_endproc
# -- End function
.globl _Z43__device_stub__imageTiledConvolution_kernelPfS_PKfiii # -- Begin function _Z43__device_stub__imageTiledConvolution_kernelPfS_PKfiii
.p2align 4, 0x90
.type _Z43__device_stub__imageTiledConvolution_kernelPfS_PKfiii,@function
_Z43__device_stub__imageTiledConvolution_kernelPfS_PKfiii: # @_Z43__device_stub__imageTiledConvolution_kernelPfS_PKfiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z28imageTiledConvolution_kernelPfS_PKfiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z43__device_stub__imageTiledConvolution_kernelPfS_PKfiii, .Lfunc_end1-_Z43__device_stub__imageTiledConvolution_kernelPfS_PKfiii
.cfi_endproc
# -- End function
.globl _Z8loadDataPfS_S_ # -- Begin function _Z8loadDataPfS_S_
.p2align 4, 0x90
.type _Z8loadDataPfS_S_,@function
_Z8loadDataPfS_S_: # @_Z8loadDataPfS_S_
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdx, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rdi,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $300, %rax # imm = 0x12C
jne .LBB2_1
# %bb.2: # %.preheader11.preheader
xorl %r14d, %r14d
movl $1200, %edx # imm = 0x4B0
movq %rsi, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB2_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%r14,4) # imm = 0x3F800000
incq %r14
cmpq $25, %r14
jne .LBB2_3
# %bb.4:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z8loadDataPfS_S_, .Lfunc_end2-_Z8loadDataPfS_S_
.cfi_endproc
# -- End function
.globl _Z7dispResPf # -- Begin function _Z7dispResPf
.p2align 4, 0x90
.type _Z7dispResPf,@function
_Z7dispResPf: # @_Z7dispResPf
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl $.Lstr, %edi
callq puts@PLT
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_1: # %.preheader12
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
# Child Loop BB3_3 Depth 3
movq %rbx, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_2: # %.preheader
# Parent Loop BB3_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_3 Depth 3
movq $-120, %r13
.p2align 4, 0x90
.LBB3_3: # Parent Loop BB3_1 Depth=1
# Parent Loop BB3_2 Depth=2
# => This Inner Loop Header: Depth=3
movss 120(%r15,%r13), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
addq $12, %r13
jne .LBB3_3
# %bb.4: # in Loop: Header=BB3_2 Depth=2
movl $10, %edi
callq putchar@PLT
incq %r12
addq $120, %r15
cmpq $10, %r12
jne .LBB3_2
# %bb.5: # in Loop: Header=BB3_1 Depth=1
movl $.L.str.3, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.4, %edi
callq system
incq %r14
addq $4, %rbx
cmpq $3, %r14
jne .LBB3_1
# %bb.6:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z7dispResPf, .Lfunc_end3-_Z7dispResPf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1200, %edi # imm = 0x4B0
callq malloc
movq %rax, %rbx
movl $1200, %edi # imm = 0x4B0
callq malloc
movq %rax, %r12
movl $100, %edi
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $300, %rax # imm = 0x12C
jne .LBB4_1
# %bb.2: # %.preheader11.preheader.i
xorl %r14d, %r14d
movl $1200, %edx # imm = 0x4B0
movq %r12, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB4_3: # %.preheader.i
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%r15,%r14,4) # imm = 0x3F800000
incq %r14
cmpq $25, %r14
jne .LBB4_3
# %bb.4: # %_Z8loadDataPfS_S_.exit
leaq 16(%rsp), %rdi
movl $1200, %esi # imm = 0x4B0
callq hipMalloc
leaq 8(%rsp), %rdi
movl $1200, %esi # imm = 0x4B0
callq hipMalloc
movq %rsp, %rdi
movl $100, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $1200, %edx # imm = 0x4B0
movq %rbx, 48(%rsp) # 8-byte Spill
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $100, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $10, 36(%rsp)
movl $10, 32(%rsp)
movl $3, 28(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 28(%rsp), %rax
movq %rax, 168(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z28imageTiledConvolution_kernelPfS_PKfiii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_6: # %_Z16imageConvolutionPfS_PKfiii.exit
movq 8(%rsp), %rsi
movl $1200, %edx # imm = 0x4B0
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
movq %r12, 40(%rsp) # 8-byte Spill
movq %r12, %r13
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_7: # %.preheader12.i
# =>This Loop Header: Depth=1
# Child Loop BB4_8 Depth 2
# Child Loop BB4_9 Depth 3
movq %r13, %rbp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_8: # %.preheader.i53
# Parent Loop BB4_7 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_9 Depth 3
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_9: # Parent Loop BB4_7 Depth=1
# Parent Loop BB4_8 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rbp,%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
addq $12, %rbx
cmpq $120, %rbx
jne .LBB4_9
# %bb.10: # in Loop: Header=BB4_8 Depth=2
movl $10, %edi
callq putchar@PLT
incq %r14
addq $120, %rbp
cmpq $10, %r14
jne .LBB4_8
# %bb.11: # in Loop: Header=BB4_7 Depth=1
movl $.L.str.3, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.4, %edi
callq system
incq %r12
addq $4, %r13
cmpq $3, %r12
jne .LBB4_7
# %bb.12: # %_Z7dispResPf.exit
movq 48(%rsp), %rdi # 8-byte Reload
callq free
movq 40(%rsp), %rdi # 8-byte Reload
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28imageTiledConvolution_kernelPfS_PKfiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z28imageTiledConvolution_kernelPfS_PKfiii,@object # @_Z28imageTiledConvolution_kernelPfS_PKfiii
.section .rodata,"a",@progbits
.globl _Z28imageTiledConvolution_kernelPfS_PKfiii
.p2align 3, 0x0
_Z28imageTiledConvolution_kernelPfS_PKfiii:
.quad _Z43__device_stub__imageTiledConvolution_kernelPfS_PKfiii
.size _Z28imageTiledConvolution_kernelPfS_PKfiii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%2.1f "
.size .L.str.1, 7
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "k = %d\n"
.size .L.str.3, 8
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "pause"
.size .L.str.4, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z28imageTiledConvolution_kernelPfS_PKfiii"
.size .L__unnamed_1, 43
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Results of the calculation"
.size .Lstr, 27
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z43__device_stub__imageTiledConvolution_kernelPfS_PKfiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z28imageTiledConvolution_kernelPfS_PKfiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #ifndef GLOBAL_CUBIC_CU
#define GLOBAL_CUBIC_CU
#include <thrust/complex.h>
using namespace thrust;
extern "C" __global__ void cubic(const double* B,
const double* C,
const double* D,
long n,
double* x)
{
long i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < n) {
double b = B[i], c = C[i], d = D[i];
complex<double> delta, u, v, m, n, w, r0, r1, r2;
u = (9 * b * c - 27 * d - 2 * b * b * b) / 54;
delta = 3 * (4 * pow(c, 3) - pow(b, 2) * pow(c, 2) - 18 * b * c * d + 27 * pow(d, 2) + 4 * pow(b, 3) * d);
v = sqrt(delta) / 18;
m = abs(u + v) >= abs(u - v) ? pow(u + v, 1. / 3) : pow(u - v, 1. / 3);
n = abs(m) > 1e-8 ? (pow(b, 2) - 3 * c) / (m * 9) : 0;
w.real(-0.5); w.imag(0.5 * sqrt(3.0));
r0 = m + n - b / 3;
r1 = w * m + w * w * n - b / 3;
r2 = w * w * m + w * n - b / 3;
if (abs(r0.imag()) > 1e-8) r0.real(0);
if (abs(r1.imag()) > 1e-8) r1.real(0);
if (abs(r2.imag()) > 1e-8) r2.real(0);
x[i] = fmax(fmax(r0.real(), r1.real()), r2.real());
}
}
#endif | .file "tmpxft_0001f611_00000000-6_global_cubic.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB5976:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5976:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z5cubicPKdS0_S0_lPdPKdS0_S0_lPd
.type _Z34__device_stub__Z5cubicPKdS0_S0_lPdPKdS0_S0_lPd, @function
_Z34__device_stub__Z5cubicPKdS0_S0_lPdPKdS0_S0_lPd:
.LFB5998:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq cubic(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5998:
.size _Z34__device_stub__Z5cubicPKdS0_S0_lPdPKdS0_S0_lPd, .-_Z34__device_stub__Z5cubicPKdS0_S0_lPdPKdS0_S0_lPd
.globl cubic
.type cubic, @function
cubic:
.LFB5999:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z5cubicPKdS0_S0_lPdPKdS0_S0_lPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5999:
.size cubic, .-cubic
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "cubic"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_ZN43_INTERNAL_31311394_15_global_cubic_cu_cubic4cuda3std3__45__cpo5beginE"
.align 8
.LC2:
.string "_ZN43_INTERNAL_31311394_15_global_cubic_cu_cubic4cuda3std3__45__cpo3endE"
.align 8
.LC3:
.string "_ZN43_INTERNAL_31311394_15_global_cubic_cu_cubic4cuda3std3__45__cpo6cbeginE"
.align 8
.LC4:
.string "_ZN43_INTERNAL_31311394_15_global_cubic_cu_cubic4cuda3std3__45__cpo4cendE"
.align 8
.LC5:
.string "_ZN43_INTERNAL_31311394_15_global_cubic_cu_cubic4cuda3std3__445_GLOBAL__N__31311394_15_global_cubic_cu_cubic6ignoreE"
.align 8
.LC6:
.string "_ZN43_INTERNAL_31311394_15_global_cubic_cu_cubic4cuda3std3__419piecewise_constructE"
.align 8
.LC7:
.string "_ZN43_INTERNAL_31311394_15_global_cubic_cu_cubic4cuda3std3__48in_placeE"
.align 8
.LC8:
.string "_ZN43_INTERNAL_31311394_15_global_cubic_cu_cubic4cuda3std6ranges3__45__cpo4swapE"
.align 8
.LC9:
.string "_ZN43_INTERNAL_31311394_15_global_cubic_cu_cubic4cuda3std6ranges3__45__cpo9iter_moveE"
.align 8
.LC10:
.string "_ZN43_INTERNAL_31311394_15_global_cubic_cu_cubic4cuda3std6ranges3__45__cpo7advanceE"
.align 8
.LC11:
.string "_ZN43_INTERNAL_31311394_15_global_cubic_cu_cubic6thrust20THRUST_200700_800_NS6system6detail10sequential3seqE"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB6001:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq cubic(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__45__cpo5beginE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__45__cpo3endE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__45__cpo6cbeginE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__45__cpo4cendE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__445_GLOBAL__N__31311394_15_global_cubic_cu_cubic6ignoreE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__48in_placeE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo7advanceE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZN6thrust20THRUST_200700_800_NS6system6detail10sequentialL3seqE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6001:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata
.type _ZN6thrust20THRUST_200700_800_NS6system6detail10sequentialL3seqE, @object
.size _ZN6thrust20THRUST_200700_800_NS6system6detail10sequentialL3seqE, 1
_ZN6thrust20THRUST_200700_800_NS6system6detail10sequentialL3seqE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo7advanceE
.section .rodata._ZN4cuda3std6ranges3__45__cpo7advanceE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo7advanceE,comdat
.type _ZN4cuda3std6ranges3__45__cpo7advanceE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo7advanceE, 1
_ZN4cuda3std6ranges3__45__cpo7advanceE:
.zero 1
.hidden _ZN4cuda3std3__445_GLOBAL__N__31311394_15_global_cubic_cu_cubic6ignoreE
.weak _ZN4cuda3std3__445_GLOBAL__N__31311394_15_global_cubic_cu_cubic6ignoreE
.section .rodata._ZN4cuda3std3__445_GLOBAL__N__31311394_15_global_cubic_cu_cubic6ignoreE,"aG",@progbits,_ZN4cuda3std3__445_GLOBAL__N__31311394_15_global_cubic_cu_cubic6ignoreE,comdat
.type _ZN4cuda3std3__445_GLOBAL__N__31311394_15_global_cubic_cu_cubic6ignoreE, @gnu_unique_object
.size _ZN4cuda3std3__445_GLOBAL__N__31311394_15_global_cubic_cu_cubic6ignoreE, 1
_ZN4cuda3std3__445_GLOBAL__N__31311394_15_global_cubic_cu_cubic6ignoreE:
.zero 1
.weak _ZN4cuda3std3__48in_placeE
.section .rodata._ZN4cuda3std3__48in_placeE,"aG",@progbits,_ZN4cuda3std3__48in_placeE,comdat
.type _ZN4cuda3std3__48in_placeE, @gnu_unique_object
.size _ZN4cuda3std3__48in_placeE, 1
_ZN4cuda3std3__48in_placeE:
.zero 1
.weak _ZN4cuda3std3__45__cpo4cendE
.section .rodata._ZN4cuda3std3__45__cpo4cendE,"aG",@progbits,_ZN4cuda3std3__45__cpo4cendE,comdat
.type _ZN4cuda3std3__45__cpo4cendE, @gnu_unique_object
.size _ZN4cuda3std3__45__cpo4cendE, 1
_ZN4cuda3std3__45__cpo4cendE:
.zero 1
.weak _ZN4cuda3std3__45__cpo6cbeginE
.section .rodata._ZN4cuda3std3__45__cpo6cbeginE,"aG",@progbits,_ZN4cuda3std3__45__cpo6cbeginE,comdat
.type _ZN4cuda3std3__45__cpo6cbeginE, @gnu_unique_object
.size _ZN4cuda3std3__45__cpo6cbeginE, 1
_ZN4cuda3std3__45__cpo6cbeginE:
.zero 1
.weak _ZN4cuda3std3__45__cpo3endE
.section .rodata._ZN4cuda3std3__45__cpo3endE,"aG",@progbits,_ZN4cuda3std3__45__cpo3endE,comdat
.type _ZN4cuda3std3__45__cpo3endE, @gnu_unique_object
.size _ZN4cuda3std3__45__cpo3endE, 1
_ZN4cuda3std3__45__cpo3endE:
.zero 1
.weak _ZN4cuda3std3__45__cpo5beginE
.section .rodata._ZN4cuda3std3__45__cpo5beginE,"aG",@progbits,_ZN4cuda3std3__45__cpo5beginE,comdat
.type _ZN4cuda3std3__45__cpo5beginE, @gnu_unique_object
.size _ZN4cuda3std3__45__cpo5beginE, 1
_ZN4cuda3std3__45__cpo5beginE:
.zero 1
.weak _ZN4cuda3std3__419piecewise_constructE
.section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
.type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
.size _ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE
.section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
.type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo4swapE
.section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
.type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
.zero 1
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #ifndef GLOBAL_CUBIC_CU
#define GLOBAL_CUBIC_CU
#include <thrust/complex.h>
using namespace thrust;
extern "C" __global__ void cubic(const double* B,
const double* C,
const double* D,
long n,
double* x)
{
long i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < n) {
double b = B[i], c = C[i], d = D[i];
complex<double> delta, u, v, m, n, w, r0, r1, r2;
u = (9 * b * c - 27 * d - 2 * b * b * b) / 54;
delta = 3 * (4 * pow(c, 3) - pow(b, 2) * pow(c, 2) - 18 * b * c * d + 27 * pow(d, 2) + 4 * pow(b, 3) * d);
v = sqrt(delta) / 18;
m = abs(u + v) >= abs(u - v) ? pow(u + v, 1. / 3) : pow(u - v, 1. / 3);
n = abs(m) > 1e-8 ? (pow(b, 2) - 3 * c) / (m * 9) : 0;
w.real(-0.5); w.imag(0.5 * sqrt(3.0));
r0 = m + n - b / 3;
r1 = w * m + w * w * n - b / 3;
r2 = w * w * m + w * n - b / 3;
if (abs(r0.imag()) > 1e-8) r0.real(0);
if (abs(r1.imag()) > 1e-8) r1.real(0);
if (abs(r2.imag()) > 1e-8) r2.real(0);
x[i] = fmax(fmax(r0.real(), r1.real()), r2.real());
}
}
#endif | #ifndef GLOBAL_CUBIC_CU
#define GLOBAL_CUBIC_CU
#include <thrust/complex.h>
using namespace thrust;
extern "C" __global__ void cubic(const double* B,
const double* C,
const double* D,
long n,
double* x)
{
long i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < n) {
double b = B[i], c = C[i], d = D[i];
complex<double> delta, u, v, m, n, w, r0, r1, r2;
u = (9 * b * c - 27 * d - 2 * b * b * b) / 54;
delta = 3 * (4 * pow(c, 3) - pow(b, 2) * pow(c, 2) - 18 * b * c * d + 27 * pow(d, 2) + 4 * pow(b, 3) * d);
v = sqrt(delta) / 18;
m = abs(u + v) >= abs(u - v) ? pow(u + v, 1. / 3) : pow(u - v, 1. / 3);
n = abs(m) > 1e-8 ? (pow(b, 2) - 3 * c) / (m * 9) : 0;
w.real(-0.5); w.imag(0.5 * sqrt(3.0));
r0 = m + n - b / 3;
r1 = w * m + w * w * n - b / 3;
r2 = w * w * m + w * n - b / 3;
if (abs(r0.imag()) > 1e-8) r0.real(0);
if (abs(r1.imag()) > 1e-8) r1.real(0);
if (abs(r2.imag()) > 1e-8) r2.real(0);
x[i] = fmax(fmax(r0.real(), r1.real()), r2.real());
}
}
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef GLOBAL_CUBIC_CU
#define GLOBAL_CUBIC_CU
#include <thrust/complex.h>
using namespace thrust;
extern "C" __global__ void cubic(const double* B,
const double* C,
const double* D,
long n,
double* x)
{
long i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < n) {
double b = B[i], c = C[i], d = D[i];
complex<double> delta, u, v, m, n, w, r0, r1, r2;
u = (9 * b * c - 27 * d - 2 * b * b * b) / 54;
delta = 3 * (4 * pow(c, 3) - pow(b, 2) * pow(c, 2) - 18 * b * c * d + 27 * pow(d, 2) + 4 * pow(b, 3) * d);
v = sqrt(delta) / 18;
m = abs(u + v) >= abs(u - v) ? pow(u + v, 1. / 3) : pow(u - v, 1. / 3);
n = abs(m) > 1e-8 ? (pow(b, 2) - 3 * c) / (m * 9) : 0;
w.real(-0.5); w.imag(0.5 * sqrt(3.0));
r0 = m + n - b / 3;
r1 = w * m + w * w * n - b / 3;
r2 = w * w * m + w * n - b / 3;
if (abs(r0.imag()) > 1e-8) r0.real(0);
if (abs(r1.imag()) > 1e-8) r1.real(0);
if (abs(r2.imag()) > 1e-8) r2.real(0);
x[i] = fmax(fmax(r0.real(), r1.real()), r2.real());
}
}
#endif | .text
.file "global_cubic.hip"
.globl __device_stub__cubic # -- Begin function __device_stub__cubic
.p2align 4, 0x90
.type __device_stub__cubic,@function
__device_stub__cubic: # @__device_stub__cubic
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $cubic, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size __device_stub__cubic, .Lfunc_end0-__device_stub__cubic
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $cubic, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type cubic,@object # @cubic
.section .rodata,"a",@progbits
.globl cubic
.p2align 3, 0x0
cubic:
.quad __device_stub__cubic
.size cubic, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "cubic"
.size .L__unnamed_1, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__cubic
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym cubic
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001f611_00000000-6_global_cubic.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB5976:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5976:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z5cubicPKdS0_S0_lPdPKdS0_S0_lPd
.type _Z34__device_stub__Z5cubicPKdS0_S0_lPdPKdS0_S0_lPd, @function
_Z34__device_stub__Z5cubicPKdS0_S0_lPdPKdS0_S0_lPd:
.LFB5998:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq cubic(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5998:
.size _Z34__device_stub__Z5cubicPKdS0_S0_lPdPKdS0_S0_lPd, .-_Z34__device_stub__Z5cubicPKdS0_S0_lPdPKdS0_S0_lPd
.globl cubic
.type cubic, @function
cubic:
.LFB5999:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z5cubicPKdS0_S0_lPdPKdS0_S0_lPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5999:
.size cubic, .-cubic
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "cubic"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_ZN43_INTERNAL_31311394_15_global_cubic_cu_cubic4cuda3std3__45__cpo5beginE"
.align 8
.LC2:
.string "_ZN43_INTERNAL_31311394_15_global_cubic_cu_cubic4cuda3std3__45__cpo3endE"
.align 8
.LC3:
.string "_ZN43_INTERNAL_31311394_15_global_cubic_cu_cubic4cuda3std3__45__cpo6cbeginE"
.align 8
.LC4:
.string "_ZN43_INTERNAL_31311394_15_global_cubic_cu_cubic4cuda3std3__45__cpo4cendE"
.align 8
.LC5:
.string "_ZN43_INTERNAL_31311394_15_global_cubic_cu_cubic4cuda3std3__445_GLOBAL__N__31311394_15_global_cubic_cu_cubic6ignoreE"
.align 8
.LC6:
.string "_ZN43_INTERNAL_31311394_15_global_cubic_cu_cubic4cuda3std3__419piecewise_constructE"
.align 8
.LC7:
.string "_ZN43_INTERNAL_31311394_15_global_cubic_cu_cubic4cuda3std3__48in_placeE"
.align 8
.LC8:
.string "_ZN43_INTERNAL_31311394_15_global_cubic_cu_cubic4cuda3std6ranges3__45__cpo4swapE"
.align 8
.LC9:
.string "_ZN43_INTERNAL_31311394_15_global_cubic_cu_cubic4cuda3std6ranges3__45__cpo9iter_moveE"
.align 8
.LC10:
.string "_ZN43_INTERNAL_31311394_15_global_cubic_cu_cubic4cuda3std6ranges3__45__cpo7advanceE"
.align 8
.LC11:
.string "_ZN43_INTERNAL_31311394_15_global_cubic_cu_cubic6thrust20THRUST_200700_800_NS6system6detail10sequential3seqE"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB6001:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq cubic(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__45__cpo5beginE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__45__cpo3endE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__45__cpo6cbeginE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__45__cpo4cendE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__445_GLOBAL__N__31311394_15_global_cubic_cu_cubic6ignoreE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__48in_placeE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo7advanceE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZN6thrust20THRUST_200700_800_NS6system6detail10sequentialL3seqE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6001:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata
.type _ZN6thrust20THRUST_200700_800_NS6system6detail10sequentialL3seqE, @object
.size _ZN6thrust20THRUST_200700_800_NS6system6detail10sequentialL3seqE, 1
_ZN6thrust20THRUST_200700_800_NS6system6detail10sequentialL3seqE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo7advanceE
.section .rodata._ZN4cuda3std6ranges3__45__cpo7advanceE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo7advanceE,comdat
.type _ZN4cuda3std6ranges3__45__cpo7advanceE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo7advanceE, 1
_ZN4cuda3std6ranges3__45__cpo7advanceE:
.zero 1
.hidden _ZN4cuda3std3__445_GLOBAL__N__31311394_15_global_cubic_cu_cubic6ignoreE
.weak _ZN4cuda3std3__445_GLOBAL__N__31311394_15_global_cubic_cu_cubic6ignoreE
.section .rodata._ZN4cuda3std3__445_GLOBAL__N__31311394_15_global_cubic_cu_cubic6ignoreE,"aG",@progbits,_ZN4cuda3std3__445_GLOBAL__N__31311394_15_global_cubic_cu_cubic6ignoreE,comdat
.type _ZN4cuda3std3__445_GLOBAL__N__31311394_15_global_cubic_cu_cubic6ignoreE, @gnu_unique_object
.size _ZN4cuda3std3__445_GLOBAL__N__31311394_15_global_cubic_cu_cubic6ignoreE, 1
_ZN4cuda3std3__445_GLOBAL__N__31311394_15_global_cubic_cu_cubic6ignoreE:
.zero 1
.weak _ZN4cuda3std3__48in_placeE
.section .rodata._ZN4cuda3std3__48in_placeE,"aG",@progbits,_ZN4cuda3std3__48in_placeE,comdat
.type _ZN4cuda3std3__48in_placeE, @gnu_unique_object
.size _ZN4cuda3std3__48in_placeE, 1
_ZN4cuda3std3__48in_placeE:
.zero 1
.weak _ZN4cuda3std3__45__cpo4cendE
.section .rodata._ZN4cuda3std3__45__cpo4cendE,"aG",@progbits,_ZN4cuda3std3__45__cpo4cendE,comdat
.type _ZN4cuda3std3__45__cpo4cendE, @gnu_unique_object
.size _ZN4cuda3std3__45__cpo4cendE, 1
_ZN4cuda3std3__45__cpo4cendE:
.zero 1
.weak _ZN4cuda3std3__45__cpo6cbeginE
.section .rodata._ZN4cuda3std3__45__cpo6cbeginE,"aG",@progbits,_ZN4cuda3std3__45__cpo6cbeginE,comdat
.type _ZN4cuda3std3__45__cpo6cbeginE, @gnu_unique_object
.size _ZN4cuda3std3__45__cpo6cbeginE, 1
_ZN4cuda3std3__45__cpo6cbeginE:
.zero 1
.weak _ZN4cuda3std3__45__cpo3endE
.section .rodata._ZN4cuda3std3__45__cpo3endE,"aG",@progbits,_ZN4cuda3std3__45__cpo3endE,comdat
.type _ZN4cuda3std3__45__cpo3endE, @gnu_unique_object
.size _ZN4cuda3std3__45__cpo3endE, 1
_ZN4cuda3std3__45__cpo3endE:
.zero 1
.weak _ZN4cuda3std3__45__cpo5beginE
.section .rodata._ZN4cuda3std3__45__cpo5beginE,"aG",@progbits,_ZN4cuda3std3__45__cpo5beginE,comdat
.type _ZN4cuda3std3__45__cpo5beginE, @gnu_unique_object
.size _ZN4cuda3std3__45__cpo5beginE, 1
_ZN4cuda3std3__45__cpo5beginE:
.zero 1
.weak _ZN4cuda3std3__419piecewise_constructE
.section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
.type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
.size _ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE
.section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
.type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo4swapE
.section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
.type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
.zero 1
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "global_cubic.hip"
.globl __device_stub__cubic # -- Begin function __device_stub__cubic
.p2align 4, 0x90
.type __device_stub__cubic,@function
__device_stub__cubic: # @__device_stub__cubic
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $cubic, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size __device_stub__cubic, .Lfunc_end0-__device_stub__cubic
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $cubic, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type cubic,@object # @cubic
.section .rodata,"a",@progbits
.globl cubic
.p2align 3, 0x0
cubic:
.quad __device_stub__cubic
.size cubic, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "cubic"
.size .L__unnamed_1, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__cubic
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym cubic
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
using namespace std;
// this amazingly nice error checking function is stolen from:
//https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
__global__ void MatrixMulKernel(double *OutMat, double *Mat1, double *Mat2, int Arows, int Acols, int Bcols) {
// row and column within submatrix
int blockrow = blockIdx.y;//*
int row = threadIdx.y;
int blockcol = blockIdx.x;
int col = threadIdx.x ;
// allocate these arrays only once we can change the values in them later
__shared__ double subAshared[BLOCKSIZE*BLOCKSIZE];
__shared__ double subBshared[BLOCKSIZE*BLOCKSIZE];
double Cvalue=0;
for (int B = 0; B < ceil((double)(Acols / BLOCKSIZE)) + 1; B++) {
// fetch from global memory
// yes, these took a LONG time to figure out. Pencil and Paper FTW!
/* notice:
1) how these indexes are actually offset a multiple of B, *not 1*.
2) threads are offset by col which will be 1 apart for each thread
3) which means that means all threads in the warp are hitting successive global memory cells
*/
int Mat1index = (row + blockrow*BLOCKSIZE)*Acols + col + B*BLOCKSIZE;
int Mat2index = (B*BLOCKSIZE + row)*Bcols + BLOCKSIZE*blockcol + col;
if (Mat1index < Arows*Acols)
subAshared[row*BLOCKSIZE + col] = Mat1[Mat1index];
else
subAshared[row*BLOCKSIZE + col] = 0;
if (Mat2index < Acols*Bcols)
subBshared[row*BLOCKSIZE + col] = Mat2[Mat2index];
else
subBshared[row*BLOCKSIZE + col] = 0;
__syncthreads();
// this computation is all using shared memory (fast)
for (int j = 0; j < BLOCKSIZE; j++)
if ((row*BLOCKSIZE + j < BLOCKSIZE*BLOCKSIZE) && (j*BLOCKSIZE + col < BLOCKSIZE*BLOCKSIZE))
Cvalue += subAshared[row*BLOCKSIZE + j]*subBshared[j*BLOCKSIZE + col];
__syncthreads();
}
if ((row < Arows) && (col < Bcols)) {
int finalmatrow = blockrow*BLOCKSIZE + row;
int finalmatcol = blockcol*BLOCKSIZE + col;
OutMat[finalmatrow*Bcols + finalmatcol] = Cvalue;
}
} | code for sm_80
Function : _Z15MatrixMulKernelPdS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ ULDC UR5, c[0x0][0x17c] ; /* 0x00005f0000057ab9 */
/* 0x000fe20000000800 */
/*0020*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0030*/ USHF.R.S32.HI UR4, URZ, 0x1f, UR5 ; /* 0x0000001f3f047899 */
/* 0x000fe20008011405 */
/*0040*/ CS2R R24, SRZ ; /* 0x0000000000187805 */
/* 0x000fe2000001ff00 */
/*0050*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe40000000a00 */
/*0060*/ ULEA.HI UR4, UR4, UR5, URZ, 0x5 ; /* 0x0000000504047291 */
/* 0x000fc8000f8f283f */
/*0070*/ USHF.R.S32.HI UR4, URZ, 0x5, UR4 ; /* 0x000000053f047899 */
/* 0x000fd20008011404 */
/*0080*/ I2F.F64 R2, UR4 ; /* 0x0000000400027d12 */
/* 0x000e700008201c00 */
/*0090*/ FRND.F64.CEIL R2, R2 ; /* 0x0000000200027313 */
/* 0x002e640000309800 */
/*00a0*/ DADD R26, R2, 1 ; /* 0x3ff00000021a7429 */
/* 0x002e4c0000000000 */
/*00b0*/ DSETP.GT.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00722a */
/* 0x002e5c0003f04000 */
/*00c0*/ @!P0 BRA 0xf30 ; /* 0x00000e6000008947 */
/* 0x002fea0003800000 */
/*00d0*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x001e220000002100 */
/*00e0*/ ISETP.GE.AND P5, PT, R0.reuse, 0x20, PT ; /* 0x000000200000780c */
/* 0x040fe20003fa6270 */
/*00f0*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000800 */
/*0100*/ IMAD.SHL.U32 R2, R0.reuse, 0x100, RZ ; /* 0x0000010000027824 */
/* 0x040fe200078e00ff */
/*0110*/ S2R R25, SR_CTAID.Y ; /* 0x0000000000197919 */
/* 0x000e620000002600 */
/*0120*/ IMAD.MOV.U32 R49, RZ, RZ, RZ ; /* 0x000000ffff317224 */
/* 0x000fe200078e00ff */
/*0130*/ ULDC UR6, c[0x0][0x180] ; /* 0x0000600000067ab9 */
/* 0x000fe40000000800 */
/*0140*/ S2R R46, SR_CTAID.X ; /* 0x00000000002e7919 */
/* 0x000ea20000002500 */
/*0150*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe4000f8e023f */
/*0160*/ UIMAD UR5, UR5, UR6, URZ ; /* 0x00000006050572a4 */
/* 0x000fe2000f8e023f */
/*0170*/ ISETP.LT.AND P1, PT, R3.reuse, 0x400, !P5 ; /* 0x000004000300780c */
/* 0x041fe20006f21270 */
/*0180*/ IMAD R47, R0, 0x20, R3 ; /* 0x00000020002f7824 */
/* 0x000fe200078e0203 */
/*0190*/ ISETP.LT.AND P2, PT, R3, 0x3e0, !P5 ; /* 0x000003e00300780c */
/* 0x000fc40006f41270 */
/*01a0*/ P2R R4, PR, RZ, 0x2 ; /* 0x00000002ff047803 */
/* 0x000fe20000000000 */
/*01b0*/ IMAD R48, R25, 0x20, R0 ; /* 0x0000002019307824 */
/* 0x002fe200078e0200 */
/*01c0*/ P2R R5, PR, RZ, 0x4 ; /* 0x00000004ff057803 */
/* 0x000fe20000000000 */
/*01d0*/ CS2R R24, SRZ ; /* 0x0000000000187805 */
/* 0x000fe2000001ff00 */
/*01e0*/ ISETP.LT.AND P0, PT, R3.reuse, 0x3c0, !P5 ; /* 0x000003c00300780c */
/* 0x040fe20006f01270 */
/*01f0*/ IMAD R46, R46, 0x20, R3.reuse ; /* 0x000000202e2e7824 */
/* 0x104fe200078e0203 */
/*0200*/ ISETP.LT.AND P1, PT, R3.reuse, 0x3a0, !P5 ; /* 0x000003a00300780c */
/* 0x040fe20006f21270 */
/*0210*/ IMAD R48, R48, c[0x0][0x17c], R3 ; /* 0x00005f0030307a24 */
/* 0x000fe200078e0203 */
/*0220*/ ISETP.LT.AND P2, PT, R3, 0x380, !P5 ; /* 0x000003800300780c */
/* 0x000fe40006f41270 */
/*0230*/ P2R R6, PR, RZ, 0x1 ; /* 0x00000001ff067803 */
/* 0x000fc40000000000 */
/*0240*/ P2R R7, PR, RZ, 0x2 ; /* 0x00000002ff077803 */
/* 0x000fe40000000000 */
/*0250*/ P2R R8, PR, RZ, 0x4 ; /* 0x00000004ff087803 */
/* 0x000fe40000000000 */
/*0260*/ ISETP.LT.AND P0, PT, R3.reuse, 0x360, !P5 ; /* 0x000003600300780c */
/* 0x040fe40006f01270 */
/*0270*/ ISETP.LT.AND P1, PT, R3.reuse, 0x340, !P5 ; /* 0x000003400300780c */
/* 0x040fe40006f21270 */
/*0280*/ ISETP.LT.AND P2, PT, R3, 0x320, !P5 ; /* 0x000003200300780c */
/* 0x000fe40006f41270 */
/*0290*/ P2R R9, PR, RZ, 0x1 ; /* 0x00000001ff097803 */
/* 0x000fc40000000000 */
/*02a0*/ P2R R10, PR, RZ, 0x2 ; /* 0x00000002ff0a7803 */
/* 0x000fe40000000000 */
/*02b0*/ P2R R11, PR, RZ, 0x4 ; /* 0x00000004ff0b7803 */
/* 0x000fe40000000000 */
/*02c0*/ ISETP.LT.AND P0, PT, R3.reuse, 0x300, !P5 ; /* 0x000003000300780c */
/* 0x040fe40006f01270 */
/*02d0*/ ISETP.LT.AND P1, PT, R3.reuse, 0x2e0, !P5 ; /* 0x000002e00300780c */
/* 0x040fe40006f21270 */
/*02e0*/ ISETP.LT.AND P2, PT, R3, 0x2c0, !P5 ; /* 0x000002c00300780c */
/* 0x000fe40006f41270 */
/*02f0*/ P2R R12, PR, RZ, 0x1 ; /* 0x00000001ff0c7803 */
/* 0x000fc40000000000 */
/*0300*/ P2R R13, PR, RZ, 0x2 ; /* 0x00000002ff0d7803 */
/* 0x000fe40000000000 */
/*0310*/ P2R R14, PR, RZ, 0x4 ; /* 0x00000004ff0e7803 */
/* 0x000fe40000000000 */
/*0320*/ ISETP.LT.AND P0, PT, R3.reuse, 0x2a0, !P5 ; /* 0x000002a00300780c */
/* 0x040fe40006f01270 */
/*0330*/ ISETP.LT.AND P1, PT, R3.reuse, 0x280, !P5 ; /* 0x000002800300780c */
/* 0x040fe40006f21270 */
/*0340*/ ISETP.LT.AND P2, PT, R3, 0x260, !P5 ; /* 0x000002600300780c */
/* 0x000fe40006f41270 */
/*0350*/ P2R R15, PR, RZ, 0x1 ; /* 0x00000001ff0f7803 */
/* 0x000fc40000000000 */
/*0360*/ P2R R16, PR, RZ, 0x2 ; /* 0x00000002ff107803 */
/* 0x000fe40000000000 */
/*0370*/ P2R R17, PR, RZ, 0x4 ; /* 0x00000004ff117803 */
/* 0x000fe40000000000 */
/*0380*/ ISETP.LT.AND P0, PT, R3.reuse, 0x240, !P5 ; /* 0x000002400300780c */
/* 0x040fe40006f01270 */
/*0390*/ ISETP.LT.AND P1, PT, R3.reuse, 0x220, !P5 ; /* 0x000002200300780c */
/* 0x040fe40006f21270 */
/*03a0*/ ISETP.LT.AND P2, PT, R3, 0x200, !P5 ; /* 0x000002000300780c */
/* 0x000fe40006f41270 */
/*03b0*/ P2R R18, PR, RZ, 0x1 ; /* 0x00000001ff127803 */
/* 0x000fc40000000000 */
/*03c0*/ P2R R19, PR, RZ, 0x2 ; /* 0x00000002ff137803 */
/* 0x000fe40000000000 */
/*03d0*/ P2R R20, PR, RZ, 0x4 ; /* 0x00000004ff147803 */
/* 0x000fe40000000000 */
/*03e0*/ ISETP.LT.AND P0, PT, R3.reuse, 0x1e0, !P5 ; /* 0x000001e00300780c */
/* 0x040fe40006f01270 */
/*03f0*/ ISETP.LT.AND P1, PT, R3.reuse, 0x1c0, !P5 ; /* 0x000001c00300780c */
/* 0x040fe40006f21270 */
/*0400*/ ISETP.LT.AND P2, PT, R3, 0x1a0, !P5 ; /* 0x000001a00300780c */
/* 0x000fe40006f41270 */
/*0410*/ P2R R21, PR, RZ, 0x1 ; /* 0x00000001ff157803 */
/* 0x000fc40000000000 */
/*0420*/ P2R R22, PR, RZ, 0x2 ; /* 0x00000002ff167803 */
/* 0x000fe40000000000 */
/*0430*/ P2R R23, PR, RZ, 0x4 ; /* 0x00000004ff177803 */
/* 0x000fe40000000000 */
/*0440*/ ISETP.LT.AND P0, PT, R3.reuse, 0x180, !P5 ; /* 0x000001800300780c */
/* 0x040fe40006f01270 */
/*0450*/ ISETP.LT.AND P1, PT, R3.reuse, 0x160, !P5 ; /* 0x000001600300780c */
/* 0x040fe40006f21270 */
/*0460*/ ISETP.LT.AND P2, PT, R3, 0x140, !P5 ; /* 0x000001400300780c */
/* 0x000fe40006f41270 */
/*0470*/ P2R R40, PR, RZ, 0x1 ; /* 0x00000001ff287803 */
/* 0x000fc40000000000 */
/*0480*/ P2R R41, PR, RZ, 0x2 ; /* 0x00000002ff297803 */
/* 0x000fe40000000000 */
/*0490*/ P2R R42, PR, RZ, 0x4 ; /* 0x00000004ff2a7803 */
/* 0x000fe40000000000 */
/*04a0*/ ISETP.LT.AND P0, PT, R3.reuse, 0x120, !P5 ; /* 0x000001200300780c */
/* 0x040fe40006f01270 */
/*04b0*/ ISETP.LT.AND P1, PT, R3.reuse, 0x100, !P5 ; /* 0x000001000300780c */
/* 0x040fe40006f21270 */
/*04c0*/ ISETP.LT.AND P2, PT, R3, 0xe0, !P5 ; /* 0x000000e00300780c */
/* 0x000fe40006f41270 */
/*04d0*/ P2R R43, PR, RZ, 0x1 ; /* 0x00000001ff2b7803 */
/* 0x000fc40000000000 */
/*04e0*/ P2R R44, PR, RZ, 0x2 ; /* 0x00000002ff2c7803 */
/* 0x000fe40000000000 */
/*04f0*/ P2R R45, PR, RZ, 0x4 ; /* 0x00000004ff2d7803 */
/* 0x000fe40000000000 */
/*0500*/ ISETP.LT.AND P0, PT, R3.reuse, 0xc0, !P5 ; /* 0x000000c00300780c */
/* 0x040fe40006f01270 */
/*0510*/ ISETP.LT.AND P1, PT, R3.reuse, 0xa0, !P5 ; /* 0x000000a00300780c */
/* 0x040fe40006f21270 */
/*0520*/ ISETP.LT.AND P2, PT, R3.reuse, 0x80, !P5 ; /* 0x000000800300780c */
/* 0x040fe40006f41270 */
/*0530*/ ISETP.LT.AND P3, PT, R3, 0x60, !P5 ; /* 0x000000600300780c */
/* 0x000fc40006f61270 */
/*0540*/ ISETP.LT.AND P4, PT, R3.reuse, 0x40, !P5 ; /* 0x000000400300780c */
/* 0x040fe40006f81270 */
/*0550*/ ISETP.LT.AND P5, PT, R3, 0x20, !P5 ; /* 0x000000200300780c */
/* 0x000fe40006fa1270 */
/*0560*/ IMAD R29, R49.reuse, 0x20, R48 ; /* 0x00000020311d7824 */
/* 0x041fe200078e0230 */
/*0570*/ CS2R R60, SRZ ; /* 0x00000000003c7805 */
/* 0x000fe2000001ff00 */
/*0580*/ P2R R53, PR, RZ, 0x4 ; /* 0x00000004ff357803 */
/* 0x000fe20000000000 */
/*0590*/ IMAD R31, R49, 0x20, R0 ; /* 0x00000020311f7824 */
/* 0x000fe200078e0200 */
/*05a0*/ CS2R R58, SRZ ; /* 0x00000000003a7805 */
/* 0x000fe2000001ff00 */
/*05b0*/ ISETP.GE.AND P6, PT, R29, UR4, PT ; /* 0x000000041d007c0c */
/* 0x000fe4000bfc6270 */
/*05c0*/ IMAD R31, R31, c[0x0][0x180], R46 ; /* 0x000060001f1f7a24 */
/* 0x000fe200078e022e */
/*05d0*/ ISETP.NE.AND P2, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc40003f45270 */
/*05e0*/ P2R R52, PR, RZ, 0x8 ; /* 0x00000008ff347803 */
/* 0x000fe40000000000 */
/*05f0*/ ISETP.NE.AND P3, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f65270 */
/*0600*/ P2R R50, PR, RZ, 0x20 ; /* 0x00000020ff327803 */
/* 0x000fe40000000000 */
/*0610*/ ISETP.NE.AND P5, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003fa5270 */
/*0620*/ @!P6 IMAD.MOV.U32 R28, RZ, RZ, 0x8 ; /* 0x00000008ff1ce424 */
/* 0x000fe200078e00ff */
/*0630*/ P2R R51, PR, RZ, 0x10 ; /* 0x00000010ff337803 */
/* 0x000fe40000000000 */
/*0640*/ ISETP.NE.AND P4, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f85270 */
/*0650*/ @!P6 IMAD.WIDE R28, R29, R28, c[0x0][0x168] ; /* 0x00005a001d1ce625 */
/* 0x000fe200078e021c */
/*0660*/ P2R R55, PR, RZ, 0x1 ; /* 0x00000001ff377803 */
/* 0x000fc40000000000 */
/*0670*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f05270 */
/*0680*/ @!P6 LDG.E.64 R60, [R28.64] ; /* 0x000000081c3ce981 */
/* 0x000ea2000c1e1b00 */
/*0690*/ ISETP.GE.AND P6, PT, R31, UR5, PT ; /* 0x000000051f007c0c */
/* 0x000fe4000bfc6270 */
/*06a0*/ P2R R54, PR, RZ, 0x2 ; /* 0x00000002ff367803 */
/* 0x000fe40000000000 */
/*06b0*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fd20003f25270 */
/*06c0*/ @!P6 IMAD.MOV.U32 R56, RZ, RZ, 0x8 ; /* 0x00000008ff38e424 */
/* 0x000fc800078e00ff */
/*06d0*/ @!P6 IMAD.WIDE R56, R31, R56, c[0x0][0x170] ; /* 0x00005c001f38e625 */
/* 0x000fca00078e0238 */
/*06e0*/ @!P6 LDG.E.64 R58, [R56.64] ; /* 0x00000008383ae981 */
/* 0x000ee2000c1e1b00 */
/*06f0*/ ISETP.NE.AND P6, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc60003fc5270 */
/*0700*/ STS.64 [R47.X8], R60 ; /* 0x0000003c2f007388 */
/* 0x004fe80000008a00 */
/*0710*/ STS.64 [R47.X8+0x2000], R58 ; /* 0x0020003a2f007388 */
/* 0x008fe80000008a00 */
/*0720*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0730*/ @P2 LDS.64 R34, [R2] ; /* 0x0000000002222984 */
/* 0x000fe80000000a00 */
/*0740*/ @P2 LDS.64 R32, [R3.X8+0x2000] ; /* 0x0020000003202984 */
/* 0x000e280000008a00 */
/*0750*/ @P3 LDS.64 R30, [R3.X8+0x2100] ; /* 0x00210000031e3984 */
/* 0x000fe80000008a00 */
/*0760*/ @P3 LDS.64 R28, [R2+0x8] ; /* 0x00000800021c3984 */
/* 0x002e680000000a00 */
/*0770*/ @P5 LDS.64 R38, [R3.X8+0x2200] ; /* 0x0022000003265984 */
/* 0x000fe80000008a00 */
/*0780*/ @P5 LDS.64 R36, [R2+0x10] ; /* 0x0000100002245984 */
/* 0x000ea20000000a00 */
/*0790*/ @P2 DFMA R24, R34, R32, R24 ; /* 0x000000202218222b */
/* 0x0010460000000018 */
/*07a0*/ @P6 LDS.64 R34, [R3.X8+0x2300] ; /* 0x0023000003226984 */
/* 0x001fe80000008a00 */
/*07b0*/ @P6 LDS.64 R32, [R2+0x18] ; /* 0x0000180002206984 */
/* 0x000e220000000a00 */
/*07c0*/ @P3 DFMA R24, R30, R28, R24 ; /* 0x0000001c1e18322b */
/* 0x0022860000000018 */
/*07d0*/ @P4 LDS.64 R30, [R3.X8+0x2400] ; /* 0x00240000031e4984 */
/* 0x002fe80000008a00 */
/*07e0*/ @P4 LDS.64 R28, [R2+0x20] ; /* 0x00002000021c4984 */
/* 0x000e620000000a00 */
/*07f0*/ @P5 DFMA R24, R38, R36, R24 ; /* 0x000000242618522b */
/* 0x0044060000000018 */
/*0800*/ @P0 LDS.64 R38, [R3.X8+0x2500] ; /* 0x0025000003260984 */
/* 0x004fe80000008a00 */
/*0810*/ @P0 LDS.64 R36, [R2+0x28] ; /* 0x0000280002240984 */
/* 0x000ea20000000a00 */
/*0820*/ ISETP.NE.AND P2, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f45270 */
/*0830*/ ISETP.NE.AND P3, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f65270 */
/*0840*/ @P6 DFMA R24, R34, R32, R24 ; /* 0x000000202218622b */
/* 0x0010640000000018 */
/*0850*/ @P1 LDS.64 R34, [R3.X8+0x2600] ; /* 0x0026000003221984 */
/* 0x001fe80000008a00 */
/*0860*/ @P1 LDS.64 R32, [R2+0x30] ; /* 0x0000300002201984 */
/* 0x000e220000000a00 */
/*0870*/ @P4 DFMA R24, R30, R28, R24 ; /* 0x0000001c1e18422b */
/* 0x0022860000000018 */
/*0880*/ @P2 LDS.64 R30, [R3.X8+0x2700] ; /* 0x00270000031e2984 */
/* 0x002fe80000008a00 */
/*0890*/ @P2 LDS.64 R28, [R2+0x38] ; /* 0x00003800021c2984 */
/* 0x000e620000000a00 */
/*08a0*/ @P0 DFMA R24, R38, R36, R24 ; /* 0x000000242618022b */
/* 0x0044060000000018 */
/*08b0*/ @P3 LDS.64 R38, [R3.X8+0x2800] ; /* 0x0028000003263984 */
/* 0x004fe80000008a00 */
/*08c0*/ @P3 LDS.64 R36, [R2+0x40] ; /* 0x0000400002243984 */
/* 0x000ea20000000a00 */
/*08d0*/ ISETP.NE.AND P5, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe40003fa5270 */
/*08e0*/ ISETP.NE.AND P6, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe40003fc5270 */
/*08f0*/ ISETP.NE.AND P4, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe20003f85270 */
/*0900*/ @P1 DFMA R24, R34, R32, R24 ; /* 0x000000202218122b */
/* 0x0010500000000018 */
/*0910*/ @P5 LDS.64 R34, [R3.X8+0x2900] ; /* 0x0029000003225984 */
/* 0x001fe80000008a00 */
/*0920*/ @P5 LDS.64 R32, [R2+0x48] ; /* 0x0000480002205984 */
/* 0x000e220000000a00 */
/*0930*/ @P2 DFMA R24, R30, R28, R24 ; /* 0x0000001c1e18222b */
/* 0x0022860000000018 */
/*0940*/ @P6 LDS.64 R30, [R3.X8+0x2a00] ; /* 0x002a0000031e6984 */
/* 0x002fe80000008a00 */
/*0950*/ @P6 LDS.64 R28, [R2+0x50] ; /* 0x00005000021c6984 */
/* 0x000e620000000a00 */
/*0960*/ @P3 DFMA R24, R38, R36, R24 ; /* 0x000000242618322b */
/* 0x0044060000000018 */
/*0970*/ @P4 LDS.64 R38, [R3.X8+0x2b00] ; /* 0x002b000003264984 */
/* 0x004fe80000008a00 */
/*0980*/ @P4 LDS.64 R36, [R2+0x58] ; /* 0x0000580002244984 */
/* 0x000ea20000000a00 */
/*0990*/ ISETP.NE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe40003f05270 */
/*09a0*/ ISETP.NE.AND P1, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fe40003f25270 */
/*09b0*/ ISETP.NE.AND P2, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fe20003f45270 */
/*09c0*/ @P5 DFMA R24, R34, R32, R24 ; /* 0x000000202218522b */
/* 0x0010500000000018 */
/*09d0*/ @P0 LDS.64 R34, [R3.X8+0x2c00] ; /* 0x002c000003220984 */
/* 0x001fe80000008a00 */
/*09e0*/ @P0 LDS.64 R32, [R2+0x60] ; /* 0x0000600002200984 */
/* 0x000e220000000a00 */
/*09f0*/ @P6 DFMA R24, R30, R28, R24 ; /* 0x0000001c1e18622b */
/* 0x0022860000000018 */
/*0a00*/ @P1 LDS.64 R30, [R3.X8+0x2d00] ; /* 0x002d0000031e1984 */
/* 0x002fe80000008a00 */
/*0a10*/ @P1 LDS.64 R28, [R2+0x68] ; /* 0x00006800021c1984 */
/* 0x000e620000000a00 */
/*0a20*/ @P4 DFMA R24, R38, R36, R24 ; /* 0x000000242618422b */
/* 0x0044060000000018 */
/*0a30*/ @P2 LDS.64 R38, [R3.X8+0x2e00] ; /* 0x002e000003262984 */
/* 0x004fe80000008a00 */
/*0a40*/ @P2 LDS.64 R36, [R2+0x70] ; /* 0x0000700002242984 */
/* 0x000ea20000000a00 */
/*0a50*/ ISETP.NE.AND P3, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fe40003f65270 */
/*0a60*/ ISETP.NE.AND P5, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fe20003fa5270 */
/*0a70*/ @P0 DFMA R24, R34, R32, R24 ; /* 0x000000202218022b */
/* 0x0010540000000018 */
/*0a80*/ @P3 LDS.64 R34, [R3.X8+0x2f00] ; /* 0x002f000003223984 */
/* 0x001fe80000008a00 */
/*0a90*/ @P3 LDS.64 R32, [R2+0x78] ; /* 0x0000780002203984 */
/* 0x000e220000000a00 */
/*0aa0*/ @P1 DFMA R24, R30, R28, R24 ; /* 0x0000001c1e18122b */
/* 0x0022860000000018 */
/*0ab0*/ @P5 LDS.64 R30, [R3.X8+0x3000] ; /* 0x00300000031e5984 */
/* 0x002fe20000008a00 */
/*0ac0*/ ISETP.NE.AND P6, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fc60003fc5270 */
/*0ad0*/ @P5 LDS.64 R28, [R2+0x80] ; /* 0x00008000021c5984 */
/* 0x000e620000000a00 */
/*0ae0*/ @P2 DFMA R24, R38, R36, R24 ; /* 0x000000242618222b */
/* 0x0044220000000018 */
/*0af0*/ ISETP.NE.AND P2, PT, R41, RZ, PT ; /* 0x000000ff2900720c */
/* 0x000fc80003f45270 */
/*0b00*/ P2R R56, PR, RZ, 0x4 ; /* 0x00000004ff387803 */
/* 0x000fe40000000000 */
/*0b10*/ ISETP.NE.AND P2, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fe40003f45270 */
/*0b20*/ @P6 LDS.64 R36, [R3.X8+0x3100] ; /* 0x0031000003246984 */
/* 0x004fe80000008a00 */
/*0b30*/ @P6 LDS.64 R38, [R2+0x88] ; /* 0x0000880002266984 */
/* 0x000ea20000000a00 */
/*0b40*/ ISETP.NE.AND P0, PT, R23, RZ, PT ; /* 0x000000ff1700720c */
/* 0x000fe20003f05270 */
/*0b50*/ @P3 DFMA R24, R34, R32, R24 ; /* 0x000000202218322b */
/* 0x00104a0000000018 */
/*0b60*/ @P2 LDS.64 R34, [R3.X8+0x3200] ; /* 0x0032000003222984 */
/* 0x001fe80000008a00 */
/*0b70*/ @P2 LDS.64 R32, [R2+0x90] ; /* 0x0000900002202984 */
/* 0x000e220000000a00 */
/*0b80*/ @P5 DFMA R24, R30, R28, R24 ; /* 0x0000001c1e18522b */
/* 0x0022860000000018 */
/*0b90*/ @P0 LDS.64 R28, [R3.X8+0x3300] ; /* 0x00330000031c0984 */
/* 0x002fe80000008a00 */
/*0ba0*/ @P0 LDS.64 R30, [R2+0x98] ; /* 0x00009800021e0984 */
/* 0x000e620000000a00 */
/*0bb0*/ ISETP.NE.AND P1, PT, R40, RZ, PT ; /* 0x000000ff2800720c */
/* 0x000fe20003f25270 */
/*0bc0*/ @P6 DFMA R24, R36, R38, R24 ; /* 0x000000262418622b */
/* 0x0044220000000018 */
/*0bd0*/ ISETP.NE.AND P3, PT, R42, RZ, PT ; /* 0x000000ff2a00720c */
/* 0x000fd60003f65270 */
/*0be0*/ @P1 LDS.64 R36, [R3.X8+0x3400] ; /* 0x0034000003241984 */
/* 0x004fe80000008a00 */
/*0bf0*/ @P1 LDS.64 R38, [R2+0xa0] ; /* 0x0000a00002261984 */
/* 0x000ea20000000a00 */
/*0c00*/ @P2 DFMA R24, R34, R32, R24 ; /* 0x000000202218222b */
/* 0x001e620000000018 */
/*0c10*/ ISETP.NE.AND P2, PT, R56, RZ, PT ; /* 0x000000ff3800720c */
/* 0x000fca0003f45270 */
/*0c20*/ @P0 DFMA R24, R28, R30, R24 ; /* 0x0000001e1c18022b */
/* 0x0020a40000000018 */
/*0c30*/ @P3 LDS.64 R30, [R3.X8+0x3600] ; /* 0x00360000031e3984 */
/* 0x001fec0000008a00 */
/*0c40*/ @P2 LDS.64 R34, [R3.X8+0x3500] ; /* 0x0035000003222984 */
/* 0x000fe80000008a00 */
/*0c50*/ @P2 LDS.64 R32, [R2+0xa8] ; /* 0x0000a80002202984 */
/* 0x000e280000000a00 */
/*0c60*/ @P3 LDS.64 R28, [R2+0xb0] ; /* 0x0000b000021c3984 */
/* 0x000e620000000a00 */
/*0c70*/ ISETP.NE.AND P4, PT, R43, RZ, PT ; /* 0x000000ff2b00720c */
/* 0x000fc40003f85270 */
/*0c80*/ ISETP.NE.AND P5, PT, R44, RZ, PT ; /* 0x000000ff2c00720c */
/* 0x000fe20003fa5270 */
/*0c90*/ @P1 DFMA R24, R36, R38, R24 ; /* 0x000000262418122b */
/* 0x0044220000000018 */
/*0ca0*/ ISETP.NE.AND P6, PT, R45, RZ, PT ; /* 0x000000ff2d00720c */
/* 0x000fd20003fc5270 */
/*0cb0*/ @P4 LDS.64 R38, [R3.X8+0x3700] ; /* 0x0037000003264984 */
/* 0x004fe80000008a00 */
/*0cc0*/ @P4 LDS.64 R36, [R2+0xb8] ; /* 0x0000b80002244984 */
/* 0x000ea20000000a00 */
/*0cd0*/ @P2 DFMA R24, R34, R32, R24 ; /* 0x000000202218222b */
/* 0x0010460000000018 */
/*0ce0*/ @P5 LDS.64 R34, [R3.X8+0x3800] ; /* 0x0038000003225984 */
/* 0x001fe80000008a00 */
/*0cf0*/ @P5 LDS.64 R32, [R2+0xc0] ; /* 0x0000c00002205984 */
/* 0x000e220000000a00 */
/*0d00*/ @P3 DFMA R24, R30, R28, R24 ; /* 0x0000001c1e18322b */
/* 0x0022860000000018 */
/*0d10*/ @P6 LDS.64 R30, [R3.X8+0x3900] ; /* 0x00390000031e6984 */
/* 0x002fe80000008a00 */
/*0d20*/ @P6 LDS.64 R28, [R2+0xc8] ; /* 0x0000c800021c6984 */
/* 0x000e620000000a00 */
/*0d30*/ ISETP.NE.AND P0, PT, R55, RZ, PT ; /* 0x000000ff3700720c */
/* 0x000fe40003f05270 */
/*0d40*/ ISETP.NE.AND P1, PT, R54, RZ, PT ; /* 0x000000ff3600720c */
/* 0x000fe40003f25270 */
/*0d50*/ ISETP.NE.AND P2, PT, R53, RZ, PT ; /* 0x000000ff3500720c */
/* 0x000fe20003f45270 */
/*0d60*/ @P4 DFMA R24, R38, R36, R24 ; /* 0x000000242618422b */
/* 0x0044100000000018 */
/*0d70*/ @P0 LDS.64 R38, [R3.X8+0x3a00] ; /* 0x003a000003260984 */
/* 0x004fe80000008a00 */
/*0d80*/ @P0 LDS.64 R36, [R2+0xd0] ; /* 0x0000d00002240984 */
/* 0x000ea20000000a00 */
/*0d90*/ @P5 DFMA R24, R34, R32, R24 ; /* 0x000000202218522b */
/* 0x0010460000000018 */
/*0da0*/ @P1 LDS.64 R34, [R3.X8+0x3b00] ; /* 0x003b000003221984 */
/* 0x001fe80000008a00 */
/*0db0*/ @P1 LDS.64 R32, [R2+0xd8] ; /* 0x0000d80002201984 */
/* 0x000e220000000a00 */
/*0dc0*/ @P6 DFMA R24, R30, R28, R24 ; /* 0x0000001c1e18622b */
/* 0x0022860000000018 */
/*0dd0*/ @P2 LDS.64 R30, [R3.X8+0x3c00] ; /* 0x003c0000031e2984 */
/* 0x002fe80000008a00 */
/*0de0*/ @P2 LDS.64 R28, [R2+0xe0] ; /* 0x0000e000021c2984 */
/* 0x000e620000000a00 */
/*0df0*/ ISETP.NE.AND P3, PT, R52, RZ, PT ; /* 0x000000ff3400720c */
/* 0x000fe40003f65270 */
/*0e00*/ ISETP.NE.AND P4, PT, R51, RZ, PT ; /* 0x000000ff3300720c */
/* 0x000fe40003f85270 */
/*0e10*/ ISETP.NE.AND P5, PT, R50, RZ, PT ; /* 0x000000ff3200720c */
/* 0x000fe20003fa5270 */
/*0e20*/ @P0 DFMA R24, R38, R36, R24 ; /* 0x000000242618022b */
/* 0x0044100000000018 */
/*0e30*/ @P3 LDS.64 R38, [R3.X8+0x3d00] ; /* 0x003d000003263984 */
/* 0x004fe80000008a00 */
/*0e40*/ @P3 LDS.64 R36, [R2+0xe8] ; /* 0x0000e80002243984 */
/* 0x000ea80000000a00 */
/*0e50*/ @P5 LDS.64 R50, [R3.X8+0x3f00] ; /* 0x003f000003325984 */
/* 0x000fe20000008a00 */
/*0e60*/ @P1 DFMA R24, R34, R32, R24 ; /* 0x000000202218122b */
/* 0x0010460000000018 */
/*0e70*/ @P4 LDS.64 R34, [R3.X8+0x3e00] ; /* 0x003e000003224984 */
/* 0x001fe80000008a00 */
/*0e80*/ @P4 LDS.64 R32, [R2+0xf0] ; /* 0x0000f00002204984 */
/* 0x000e220000000a00 */
/*0e90*/ @P2 DFMA R24, R30, R28, R24 ; /* 0x0000001c1e18222b */
/* 0x0022860000000018 */
/*0ea0*/ @P5 LDS.64 R28, [R2+0xf8] ; /* 0x0000f800021c5984 */
/* 0x002e620000000a00 */
/*0eb0*/ IADD3 R49, R49, 0x1, RZ ; /* 0x0000000131317810 */
/* 0x000fc80007ffe0ff */
/*0ec0*/ I2F.F64 R30, R49 ; /* 0x00000031001e7312 */
/* 0x000ee20000201c00 */
/*0ed0*/ @P3 DFMA R24, R38, R36, R24 ; /* 0x000000242618322b */
/* 0x004e220000000018 */
/*0ee0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0ef0*/ DSETP.GT.AND P6, PT, R26, R30, PT ; /* 0x0000001e1a00722a */
/* 0x008fc80003fc4000 */
/*0f00*/ @P4 DFMA R24, R34, R32, R24 ; /* 0x000000202218422b */
/* 0x001e4c0000000018 */
/*0f10*/ @P5 DFMA R24, R50, R28, R24 ; /* 0x0000001c3218522b */
/* 0x0020480000000018 */
/*0f20*/ @P6 BRA 0x560 ; /* 0xfffff63000006947 */
/* 0x000fea000383ffff */
/*0f30*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x001e240000002100 */
/*0f40*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x180], PT ; /* 0x0000600002007a0c */
/* 0x001fc80003f06270 */
/*0f50*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0f60*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0f70*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0f80*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000ea20000002600 */
/*0f90*/ IMAD R3, R3, 0x20, R2 ; /* 0x0000002003037824 */
/* 0x001fe400078e0202 */
/*0fa0*/ IMAD R2, R5, 0x20, R0 ; /* 0x0000002005027824 */
/* 0x004fe400078e0200 */
/*0fb0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe400078e00ff */
/*0fc0*/ IMAD R2, R2, c[0x0][0x180], R3 ; /* 0x0000600002027a24 */
/* 0x000fc800078e0203 */
/*0fd0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0fe0*/ STG.E.64 [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x002fe2000c101b08 */
/*0ff0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1000*/ BRA 0x1000; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
using namespace std;
// this amazingly nice error checking function is stolen from:
//https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
__global__ void MatrixMulKernel(double *OutMat, double *Mat1, double *Mat2, int Arows, int Acols, int Bcols) {
// row and column within submatrix
int blockrow = blockIdx.y;//*
int row = threadIdx.y;
int blockcol = blockIdx.x;
int col = threadIdx.x ;
// allocate these arrays only once we can change the values in them later
__shared__ double subAshared[BLOCKSIZE*BLOCKSIZE];
__shared__ double subBshared[BLOCKSIZE*BLOCKSIZE];
double Cvalue=0;
for (int B = 0; B < ceil((double)(Acols / BLOCKSIZE)) + 1; B++) {
// fetch from global memory
// yes, these took a LONG time to figure out. Pencil and Paper FTW!
/* notice:
1) how these indexes are actually offset a multiple of B, *not 1*.
2) threads are offset by col which will be 1 apart for each thread
3) which means that means all threads in the warp are hitting successive global memory cells
*/
int Mat1index = (row + blockrow*BLOCKSIZE)*Acols + col + B*BLOCKSIZE;
int Mat2index = (B*BLOCKSIZE + row)*Bcols + BLOCKSIZE*blockcol + col;
if (Mat1index < Arows*Acols)
subAshared[row*BLOCKSIZE + col] = Mat1[Mat1index];
else
subAshared[row*BLOCKSIZE + col] = 0;
if (Mat2index < Acols*Bcols)
subBshared[row*BLOCKSIZE + col] = Mat2[Mat2index];
else
subBshared[row*BLOCKSIZE + col] = 0;
__syncthreads();
// this computation is all using shared memory (fast)
for (int j = 0; j < BLOCKSIZE; j++)
if ((row*BLOCKSIZE + j < BLOCKSIZE*BLOCKSIZE) && (j*BLOCKSIZE + col < BLOCKSIZE*BLOCKSIZE))
Cvalue += subAshared[row*BLOCKSIZE + j]*subBshared[j*BLOCKSIZE + col];
__syncthreads();
}
if ((row < Arows) && (col < Bcols)) {
int finalmatrow = blockrow*BLOCKSIZE + row;
int finalmatcol = blockcol*BLOCKSIZE + col;
OutMat[finalmatrow*Bcols + finalmatcol] = Cvalue;
}
} | .file "tmpxft_00112554_00000000-6_MatrixMulKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z15MatrixMulKernelPdS_S_iiiPdS_S_iii
.type _Z42__device_stub__Z15MatrixMulKernelPdS_S_iiiPdS_S_iii, @function
_Z42__device_stub__Z15MatrixMulKernelPdS_S_iiiPdS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15MatrixMulKernelPdS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z15MatrixMulKernelPdS_S_iiiPdS_S_iii, .-_Z42__device_stub__Z15MatrixMulKernelPdS_S_iiiPdS_S_iii
.globl _Z15MatrixMulKernelPdS_S_iii
.type _Z15MatrixMulKernelPdS_S_iii, @function
_Z15MatrixMulKernelPdS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z15MatrixMulKernelPdS_S_iiiPdS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15MatrixMulKernelPdS_S_iii, .-_Z15MatrixMulKernelPdS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15MatrixMulKernelPdS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15MatrixMulKernelPdS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
using namespace std;
// this amazingly nice error checking function is stolen from:
//https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
__global__ void MatrixMulKernel(double *OutMat, double *Mat1, double *Mat2, int Arows, int Acols, int Bcols) {
// row and column within submatrix
int blockrow = blockIdx.y;//*
int row = threadIdx.y;
int blockcol = blockIdx.x;
int col = threadIdx.x ;
// allocate these arrays only once we can change the values in them later
__shared__ double subAshared[BLOCKSIZE*BLOCKSIZE];
__shared__ double subBshared[BLOCKSIZE*BLOCKSIZE];
double Cvalue=0;
for (int B = 0; B < ceil((double)(Acols / BLOCKSIZE)) + 1; B++) {
// fetch from global memory
// yes, these took a LONG time to figure out. Pencil and Paper FTW!
/* notice:
1) how these indexes are actually offset a multiple of B, *not 1*.
2) threads are offset by col which will be 1 apart for each thread
3) which means that means all threads in the warp are hitting successive global memory cells
*/
int Mat1index = (row + blockrow*BLOCKSIZE)*Acols + col + B*BLOCKSIZE;
int Mat2index = (B*BLOCKSIZE + row)*Bcols + BLOCKSIZE*blockcol + col;
if (Mat1index < Arows*Acols)
subAshared[row*BLOCKSIZE + col] = Mat1[Mat1index];
else
subAshared[row*BLOCKSIZE + col] = 0;
if (Mat2index < Acols*Bcols)
subBshared[row*BLOCKSIZE + col] = Mat2[Mat2index];
else
subBshared[row*BLOCKSIZE + col] = 0;
__syncthreads();
// this computation is all using shared memory (fast)
for (int j = 0; j < BLOCKSIZE; j++)
if ((row*BLOCKSIZE + j < BLOCKSIZE*BLOCKSIZE) && (j*BLOCKSIZE + col < BLOCKSIZE*BLOCKSIZE))
Cvalue += subAshared[row*BLOCKSIZE + j]*subBshared[j*BLOCKSIZE + col];
__syncthreads();
}
if ((row < Arows) && (col < Bcols)) {
int finalmatrow = blockrow*BLOCKSIZE + row;
int finalmatcol = blockcol*BLOCKSIZE + col;
OutMat[finalmatrow*Bcols + finalmatcol] = Cvalue;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
using namespace std;
// this amazingly nice error checking function is stolen from:
//https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
__global__ void MatrixMulKernel(double *OutMat, double *Mat1, double *Mat2, int Arows, int Acols, int Bcols) {
// row and column within submatrix
int blockrow = blockIdx.y;//*
int row = threadIdx.y;
int blockcol = blockIdx.x;
int col = threadIdx.x ;
// allocate these arrays only once we can change the values in them later
__shared__ double subAshared[BLOCKSIZE*BLOCKSIZE];
__shared__ double subBshared[BLOCKSIZE*BLOCKSIZE];
double Cvalue=0;
for (int B = 0; B < ceil((double)(Acols / BLOCKSIZE)) + 1; B++) {
// fetch from global memory
// yes, these took a LONG time to figure out. Pencil and Paper FTW!
/* notice:
1) how these indexes are actually offset a multiple of B, *not 1*.
2) threads are offset by col which will be 1 apart for each thread
3) which means that means all threads in the warp are hitting successive global memory cells
*/
int Mat1index = (row + blockrow*BLOCKSIZE)*Acols + col + B*BLOCKSIZE;
int Mat2index = (B*BLOCKSIZE + row)*Bcols + BLOCKSIZE*blockcol + col;
if (Mat1index < Arows*Acols)
subAshared[row*BLOCKSIZE + col] = Mat1[Mat1index];
else
subAshared[row*BLOCKSIZE + col] = 0;
if (Mat2index < Acols*Bcols)
subBshared[row*BLOCKSIZE + col] = Mat2[Mat2index];
else
subBshared[row*BLOCKSIZE + col] = 0;
__syncthreads();
// this computation is all using shared memory (fast)
for (int j = 0; j < BLOCKSIZE; j++)
if ((row*BLOCKSIZE + j < BLOCKSIZE*BLOCKSIZE) && (j*BLOCKSIZE + col < BLOCKSIZE*BLOCKSIZE))
Cvalue += subAshared[row*BLOCKSIZE + j]*subBshared[j*BLOCKSIZE + col];
__syncthreads();
}
if ((row < Arows) && (col < Bcols)) {
int finalmatrow = blockrow*BLOCKSIZE + row;
int finalmatcol = blockcol*BLOCKSIZE + col;
OutMat[finalmatrow*Bcols + finalmatcol] = Cvalue;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
using namespace std;
// this amazingly nice error checking function is stolen from:
//https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
__global__ void MatrixMulKernel(double *OutMat, double *Mat1, double *Mat2, int Arows, int Acols, int Bcols) {
// row and column within submatrix
int blockrow = blockIdx.y;//*
int row = threadIdx.y;
int blockcol = blockIdx.x;
int col = threadIdx.x ;
// allocate these arrays only once we can change the values in them later
__shared__ double subAshared[BLOCKSIZE*BLOCKSIZE];
__shared__ double subBshared[BLOCKSIZE*BLOCKSIZE];
double Cvalue=0;
for (int B = 0; B < ceil((double)(Acols / BLOCKSIZE)) + 1; B++) {
// fetch from global memory
// yes, these took a LONG time to figure out. Pencil and Paper FTW!
/* notice:
1) how these indexes are actually offset a multiple of B, *not 1*.
2) threads are offset by col which will be 1 apart for each thread
3) which means that means all threads in the warp are hitting successive global memory cells
*/
int Mat1index = (row + blockrow*BLOCKSIZE)*Acols + col + B*BLOCKSIZE;
int Mat2index = (B*BLOCKSIZE + row)*Bcols + BLOCKSIZE*blockcol + col;
if (Mat1index < Arows*Acols)
subAshared[row*BLOCKSIZE + col] = Mat1[Mat1index];
else
subAshared[row*BLOCKSIZE + col] = 0;
if (Mat2index < Acols*Bcols)
subBshared[row*BLOCKSIZE + col] = Mat2[Mat2index];
else
subBshared[row*BLOCKSIZE + col] = 0;
__syncthreads();
// this computation is all using shared memory (fast)
for (int j = 0; j < BLOCKSIZE; j++)
if ((row*BLOCKSIZE + j < BLOCKSIZE*BLOCKSIZE) && (j*BLOCKSIZE + col < BLOCKSIZE*BLOCKSIZE))
Cvalue += subAshared[row*BLOCKSIZE + j]*subBshared[j*BLOCKSIZE + col];
__syncthreads();
}
if ((row < Arows) && (col < Bcols)) {
int finalmatrow = blockrow*BLOCKSIZE + row;
int finalmatcol = blockcol*BLOCKSIZE + col;
OutMat[finalmatrow*Bcols + finalmatcol] = Cvalue;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15MatrixMulKernelPdS_S_iii
.globl _Z15MatrixMulKernelPdS_S_iii
.p2align 8
.type _Z15MatrixMulKernelPdS_S_iii,@function
_Z15MatrixMulKernelPdS_S_iii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b32 s8, s[0:1], 0x20
v_mov_b32_e32 v1, 0
v_bfe_u32 v7, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_cmpk_lt_i32 s3, 0xffe1
s_cbranch_scc1 .LBB0_18
s_load_b128 s[4:7], s[0:1], 0x8
v_lshlrev_b32_e32 v8, 5, v7
v_lshl_add_u32 v1, s15, 5, v7
s_ashr_i32 s9, s3, 31
v_lshl_or_b32 v11, v0, 3, 0x2000
s_lshr_b32 s9, s9, 27
v_lshlrev_b32_e32 v12, 8, v7
v_mad_u64_u32 v[3:4], null, v1, s3, v[0:1]
v_mov_b32_e32 v1, 0
v_add_lshl_u32 v9, v8, v0, 3
v_lshl_add_u32 v4, s14, 5, v0
v_mov_b32_e32 v2, 0
s_add_i32 s9, s3, s9
s_mul_i32 s10, s3, s2
v_add_nc_u32_e32 v10, 0x2000, v9
s_ashr_i32 s9, s9, 5
s_mul_i32 s3, s8, s3
s_mov_b32 s11, 0
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_lshl_b32 s12, s11, 5
s_mov_b32 s13, exec_lo
v_add_nc_u32_e32 v5, s12, v3
v_cmpx_le_i32_e64 s10, v5
s_xor_b32 s13, exec_lo, s13
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v6, v5
ds_store_b64 v9, v[5:6]
.LBB0_4:
s_and_not1_saveexec_b32 s13, s13
s_cbranch_execz .LBB0_6
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 3, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b64 v[5:6], v[5:6], off
s_waitcnt vmcnt(0)
ds_store_b64 v9, v[5:6]
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s13
v_add_nc_u32_e32 v13, s12, v7
s_mov_b32 s12, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v13, s8, v[4:5]
v_cmpx_le_i32_e64 s3, v5
s_xor_b32 s12, exec_lo, s12
s_cbranch_execz .LBB0_8
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v6, v5
ds_store_b64 v10, v[5:6]
.LBB0_8:
s_and_not1_saveexec_b32 s12, s12
s_cbranch_execz .LBB0_10
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 3, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s6, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
global_load_b64 v[5:6], v[5:6], off
s_waitcnt vmcnt(0)
ds_store_b64 v10, v[5:6]
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s12
v_mov_b32_e32 v5, v8
v_dual_mov_b32 v6, v0 :: v_dual_mov_b32 v13, v11
s_mov_b32 s12, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_13
.p2align 6
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s16
.LBB0_12:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s13
v_add_nc_u32_e32 v13, 0x100, v13
v_add_nc_u32_e32 v6, 32, v6
v_add_nc_u32_e32 v5, 1, v5
s_add_i32 s12, s12, 8
s_cmpk_eq_i32 s12, 0x100
s_cbranch_scc1 .LBB0_16
.LBB0_13:
s_mov_b32 s13, exec_lo
v_cmpx_gt_u32_e32 0x400, v5
s_cbranch_execz .LBB0_12
s_mov_b32 s16, exec_lo
v_cmpx_gt_u32_e32 0x400, v6
s_cbranch_execz .LBB0_11
v_add_nc_u32_e32 v14, s12, v12
ds_load_b64 v[14:15], v14
ds_load_b64 v[16:17], v13
s_waitcnt lgkmcnt(0)
v_fma_f64 v[1:2], v[14:15], v[16:17], v[1:2]
s_branch .LBB0_11
.LBB0_16:
s_set_inst_prefetch_distance 0x2
s_add_i32 s12, s11, 1
s_cmp_le_i32 s9, s11
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_18
s_mov_b32 s11, s12
s_branch .LBB0_2
.LBB0_18:
v_cmp_gt_i32_e32 vcc_lo, s2, v7
v_cmp_gt_i32_e64 s2, s8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_20
v_lshl_add_u32 v3, s15, 5, v7
s_load_b64 s[0:1], s[0:1], 0x0
s_lshl_b32 s2, s14, 5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v3, s8
v_add3_u32 v3, s2, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 3, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_b64 v[3:4], v[1:2], off
.LBB0_20:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15MatrixMulKernelPdS_S_iii
.amdhsa_group_segment_fixed_size 16384
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15MatrixMulKernelPdS_S_iii, .Lfunc_end0-_Z15MatrixMulKernelPdS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 16384
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15MatrixMulKernelPdS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z15MatrixMulKernelPdS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
using namespace std;
// this amazingly nice error checking function is stolen from:
//https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
__global__ void MatrixMulKernel(double *OutMat, double *Mat1, double *Mat2, int Arows, int Acols, int Bcols) {
// row and column within submatrix
int blockrow = blockIdx.y;//*
int row = threadIdx.y;
int blockcol = blockIdx.x;
int col = threadIdx.x ;
// allocate these arrays only once we can change the values in them later
__shared__ double subAshared[BLOCKSIZE*BLOCKSIZE];
__shared__ double subBshared[BLOCKSIZE*BLOCKSIZE];
double Cvalue=0;
for (int B = 0; B < ceil((double)(Acols / BLOCKSIZE)) + 1; B++) {
// fetch from global memory
// yes, these took a LONG time to figure out. Pencil and Paper FTW!
/* notice:
1) how these indexes are actually offset a multiple of B, *not 1*.
2) threads are offset by col which will be 1 apart for each thread
3) which means that means all threads in the warp are hitting successive global memory cells
*/
int Mat1index = (row + blockrow*BLOCKSIZE)*Acols + col + B*BLOCKSIZE;
int Mat2index = (B*BLOCKSIZE + row)*Bcols + BLOCKSIZE*blockcol + col;
if (Mat1index < Arows*Acols)
subAshared[row*BLOCKSIZE + col] = Mat1[Mat1index];
else
subAshared[row*BLOCKSIZE + col] = 0;
if (Mat2index < Acols*Bcols)
subBshared[row*BLOCKSIZE + col] = Mat2[Mat2index];
else
subBshared[row*BLOCKSIZE + col] = 0;
__syncthreads();
// this computation is all using shared memory (fast)
for (int j = 0; j < BLOCKSIZE; j++)
if ((row*BLOCKSIZE + j < BLOCKSIZE*BLOCKSIZE) && (j*BLOCKSIZE + col < BLOCKSIZE*BLOCKSIZE))
Cvalue += subAshared[row*BLOCKSIZE + j]*subBshared[j*BLOCKSIZE + col];
__syncthreads();
}
if ((row < Arows) && (col < Bcols)) {
int finalmatrow = blockrow*BLOCKSIZE + row;
int finalmatcol = blockcol*BLOCKSIZE + col;
OutMat[finalmatrow*Bcols + finalmatcol] = Cvalue;
}
} | .text
.file "MatrixMulKernel.hip"
.globl _Z30__device_stub__MatrixMulKernelPdS_S_iii # -- Begin function _Z30__device_stub__MatrixMulKernelPdS_S_iii
.p2align 4, 0x90
.type _Z30__device_stub__MatrixMulKernelPdS_S_iii,@function
_Z30__device_stub__MatrixMulKernelPdS_S_iii: # @_Z30__device_stub__MatrixMulKernelPdS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15MatrixMulKernelPdS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z30__device_stub__MatrixMulKernelPdS_S_iii, .Lfunc_end0-_Z30__device_stub__MatrixMulKernelPdS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15MatrixMulKernelPdS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15MatrixMulKernelPdS_S_iii,@object # @_Z15MatrixMulKernelPdS_S_iii
.section .rodata,"a",@progbits
.globl _Z15MatrixMulKernelPdS_S_iii
.p2align 3, 0x0
_Z15MatrixMulKernelPdS_S_iii:
.quad _Z30__device_stub__MatrixMulKernelPdS_S_iii
.size _Z15MatrixMulKernelPdS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15MatrixMulKernelPdS_S_iii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__MatrixMulKernelPdS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15MatrixMulKernelPdS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15MatrixMulKernelPdS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ ULDC UR5, c[0x0][0x17c] ; /* 0x00005f0000057ab9 */
/* 0x000fe20000000800 */
/*0020*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0030*/ USHF.R.S32.HI UR4, URZ, 0x1f, UR5 ; /* 0x0000001f3f047899 */
/* 0x000fe20008011405 */
/*0040*/ CS2R R24, SRZ ; /* 0x0000000000187805 */
/* 0x000fe2000001ff00 */
/*0050*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe40000000a00 */
/*0060*/ ULEA.HI UR4, UR4, UR5, URZ, 0x5 ; /* 0x0000000504047291 */
/* 0x000fc8000f8f283f */
/*0070*/ USHF.R.S32.HI UR4, URZ, 0x5, UR4 ; /* 0x000000053f047899 */
/* 0x000fd20008011404 */
/*0080*/ I2F.F64 R2, UR4 ; /* 0x0000000400027d12 */
/* 0x000e700008201c00 */
/*0090*/ FRND.F64.CEIL R2, R2 ; /* 0x0000000200027313 */
/* 0x002e640000309800 */
/*00a0*/ DADD R26, R2, 1 ; /* 0x3ff00000021a7429 */
/* 0x002e4c0000000000 */
/*00b0*/ DSETP.GT.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00722a */
/* 0x002e5c0003f04000 */
/*00c0*/ @!P0 BRA 0xf30 ; /* 0x00000e6000008947 */
/* 0x002fea0003800000 */
/*00d0*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x001e220000002100 */
/*00e0*/ ISETP.GE.AND P5, PT, R0.reuse, 0x20, PT ; /* 0x000000200000780c */
/* 0x040fe20003fa6270 */
/*00f0*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000800 */
/*0100*/ IMAD.SHL.U32 R2, R0.reuse, 0x100, RZ ; /* 0x0000010000027824 */
/* 0x040fe200078e00ff */
/*0110*/ S2R R25, SR_CTAID.Y ; /* 0x0000000000197919 */
/* 0x000e620000002600 */
/*0120*/ IMAD.MOV.U32 R49, RZ, RZ, RZ ; /* 0x000000ffff317224 */
/* 0x000fe200078e00ff */
/*0130*/ ULDC UR6, c[0x0][0x180] ; /* 0x0000600000067ab9 */
/* 0x000fe40000000800 */
/*0140*/ S2R R46, SR_CTAID.X ; /* 0x00000000002e7919 */
/* 0x000ea20000002500 */
/*0150*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe4000f8e023f */
/*0160*/ UIMAD UR5, UR5, UR6, URZ ; /* 0x00000006050572a4 */
/* 0x000fe2000f8e023f */
/*0170*/ ISETP.LT.AND P1, PT, R3.reuse, 0x400, !P5 ; /* 0x000004000300780c */
/* 0x041fe20006f21270 */
/*0180*/ IMAD R47, R0, 0x20, R3 ; /* 0x00000020002f7824 */
/* 0x000fe200078e0203 */
/*0190*/ ISETP.LT.AND P2, PT, R3, 0x3e0, !P5 ; /* 0x000003e00300780c */
/* 0x000fc40006f41270 */
/*01a0*/ P2R R4, PR, RZ, 0x2 ; /* 0x00000002ff047803 */
/* 0x000fe20000000000 */
/*01b0*/ IMAD R48, R25, 0x20, R0 ; /* 0x0000002019307824 */
/* 0x002fe200078e0200 */
/*01c0*/ P2R R5, PR, RZ, 0x4 ; /* 0x00000004ff057803 */
/* 0x000fe20000000000 */
/*01d0*/ CS2R R24, SRZ ; /* 0x0000000000187805 */
/* 0x000fe2000001ff00 */
/*01e0*/ ISETP.LT.AND P0, PT, R3.reuse, 0x3c0, !P5 ; /* 0x000003c00300780c */
/* 0x040fe20006f01270 */
/*01f0*/ IMAD R46, R46, 0x20, R3.reuse ; /* 0x000000202e2e7824 */
/* 0x104fe200078e0203 */
/*0200*/ ISETP.LT.AND P1, PT, R3.reuse, 0x3a0, !P5 ; /* 0x000003a00300780c */
/* 0x040fe20006f21270 */
/*0210*/ IMAD R48, R48, c[0x0][0x17c], R3 ; /* 0x00005f0030307a24 */
/* 0x000fe200078e0203 */
/*0220*/ ISETP.LT.AND P2, PT, R3, 0x380, !P5 ; /* 0x000003800300780c */
/* 0x000fe40006f41270 */
/*0230*/ P2R R6, PR, RZ, 0x1 ; /* 0x00000001ff067803 */
/* 0x000fc40000000000 */
/*0240*/ P2R R7, PR, RZ, 0x2 ; /* 0x00000002ff077803 */
/* 0x000fe40000000000 */
/*0250*/ P2R R8, PR, RZ, 0x4 ; /* 0x00000004ff087803 */
/* 0x000fe40000000000 */
/*0260*/ ISETP.LT.AND P0, PT, R3.reuse, 0x360, !P5 ; /* 0x000003600300780c */
/* 0x040fe40006f01270 */
/*0270*/ ISETP.LT.AND P1, PT, R3.reuse, 0x340, !P5 ; /* 0x000003400300780c */
/* 0x040fe40006f21270 */
/*0280*/ ISETP.LT.AND P2, PT, R3, 0x320, !P5 ; /* 0x000003200300780c */
/* 0x000fe40006f41270 */
/*0290*/ P2R R9, PR, RZ, 0x1 ; /* 0x00000001ff097803 */
/* 0x000fc40000000000 */
/*02a0*/ P2R R10, PR, RZ, 0x2 ; /* 0x00000002ff0a7803 */
/* 0x000fe40000000000 */
/*02b0*/ P2R R11, PR, RZ, 0x4 ; /* 0x00000004ff0b7803 */
/* 0x000fe40000000000 */
/*02c0*/ ISETP.LT.AND P0, PT, R3.reuse, 0x300, !P5 ; /* 0x000003000300780c */
/* 0x040fe40006f01270 */
/*02d0*/ ISETP.LT.AND P1, PT, R3.reuse, 0x2e0, !P5 ; /* 0x000002e00300780c */
/* 0x040fe40006f21270 */
/*02e0*/ ISETP.LT.AND P2, PT, R3, 0x2c0, !P5 ; /* 0x000002c00300780c */
/* 0x000fe40006f41270 */
/*02f0*/ P2R R12, PR, RZ, 0x1 ; /* 0x00000001ff0c7803 */
/* 0x000fc40000000000 */
/*0300*/ P2R R13, PR, RZ, 0x2 ; /* 0x00000002ff0d7803 */
/* 0x000fe40000000000 */
/*0310*/ P2R R14, PR, RZ, 0x4 ; /* 0x00000004ff0e7803 */
/* 0x000fe40000000000 */
/*0320*/ ISETP.LT.AND P0, PT, R3.reuse, 0x2a0, !P5 ; /* 0x000002a00300780c */
/* 0x040fe40006f01270 */
/*0330*/ ISETP.LT.AND P1, PT, R3.reuse, 0x280, !P5 ; /* 0x000002800300780c */
/* 0x040fe40006f21270 */
/*0340*/ ISETP.LT.AND P2, PT, R3, 0x260, !P5 ; /* 0x000002600300780c */
/* 0x000fe40006f41270 */
/*0350*/ P2R R15, PR, RZ, 0x1 ; /* 0x00000001ff0f7803 */
/* 0x000fc40000000000 */
/*0360*/ P2R R16, PR, RZ, 0x2 ; /* 0x00000002ff107803 */
/* 0x000fe40000000000 */
/*0370*/ P2R R17, PR, RZ, 0x4 ; /* 0x00000004ff117803 */
/* 0x000fe40000000000 */
/*0380*/ ISETP.LT.AND P0, PT, R3.reuse, 0x240, !P5 ; /* 0x000002400300780c */
/* 0x040fe40006f01270 */
/*0390*/ ISETP.LT.AND P1, PT, R3.reuse, 0x220, !P5 ; /* 0x000002200300780c */
/* 0x040fe40006f21270 */
/*03a0*/ ISETP.LT.AND P2, PT, R3, 0x200, !P5 ; /* 0x000002000300780c */
/* 0x000fe40006f41270 */
/*03b0*/ P2R R18, PR, RZ, 0x1 ; /* 0x00000001ff127803 */
/* 0x000fc40000000000 */
/*03c0*/ P2R R19, PR, RZ, 0x2 ; /* 0x00000002ff137803 */
/* 0x000fe40000000000 */
/*03d0*/ P2R R20, PR, RZ, 0x4 ; /* 0x00000004ff147803 */
/* 0x000fe40000000000 */
/*03e0*/ ISETP.LT.AND P0, PT, R3.reuse, 0x1e0, !P5 ; /* 0x000001e00300780c */
/* 0x040fe40006f01270 */
/*03f0*/ ISETP.LT.AND P1, PT, R3.reuse, 0x1c0, !P5 ; /* 0x000001c00300780c */
/* 0x040fe40006f21270 */
/*0400*/ ISETP.LT.AND P2, PT, R3, 0x1a0, !P5 ; /* 0x000001a00300780c */
/* 0x000fe40006f41270 */
/*0410*/ P2R R21, PR, RZ, 0x1 ; /* 0x00000001ff157803 */
/* 0x000fc40000000000 */
/*0420*/ P2R R22, PR, RZ, 0x2 ; /* 0x00000002ff167803 */
/* 0x000fe40000000000 */
/*0430*/ P2R R23, PR, RZ, 0x4 ; /* 0x00000004ff177803 */
/* 0x000fe40000000000 */
/*0440*/ ISETP.LT.AND P0, PT, R3.reuse, 0x180, !P5 ; /* 0x000001800300780c */
/* 0x040fe40006f01270 */
/*0450*/ ISETP.LT.AND P1, PT, R3.reuse, 0x160, !P5 ; /* 0x000001600300780c */
/* 0x040fe40006f21270 */
/*0460*/ ISETP.LT.AND P2, PT, R3, 0x140, !P5 ; /* 0x000001400300780c */
/* 0x000fe40006f41270 */
/*0470*/ P2R R40, PR, RZ, 0x1 ; /* 0x00000001ff287803 */
/* 0x000fc40000000000 */
/*0480*/ P2R R41, PR, RZ, 0x2 ; /* 0x00000002ff297803 */
/* 0x000fe40000000000 */
/*0490*/ P2R R42, PR, RZ, 0x4 ; /* 0x00000004ff2a7803 */
/* 0x000fe40000000000 */
/*04a0*/ ISETP.LT.AND P0, PT, R3.reuse, 0x120, !P5 ; /* 0x000001200300780c */
/* 0x040fe40006f01270 */
/*04b0*/ ISETP.LT.AND P1, PT, R3.reuse, 0x100, !P5 ; /* 0x000001000300780c */
/* 0x040fe40006f21270 */
/*04c0*/ ISETP.LT.AND P2, PT, R3, 0xe0, !P5 ; /* 0x000000e00300780c */
/* 0x000fe40006f41270 */
/*04d0*/ P2R R43, PR, RZ, 0x1 ; /* 0x00000001ff2b7803 */
/* 0x000fc40000000000 */
/*04e0*/ P2R R44, PR, RZ, 0x2 ; /* 0x00000002ff2c7803 */
/* 0x000fe40000000000 */
/*04f0*/ P2R R45, PR, RZ, 0x4 ; /* 0x00000004ff2d7803 */
/* 0x000fe40000000000 */
/*0500*/ ISETP.LT.AND P0, PT, R3.reuse, 0xc0, !P5 ; /* 0x000000c00300780c */
/* 0x040fe40006f01270 */
/*0510*/ ISETP.LT.AND P1, PT, R3.reuse, 0xa0, !P5 ; /* 0x000000a00300780c */
/* 0x040fe40006f21270 */
/*0520*/ ISETP.LT.AND P2, PT, R3.reuse, 0x80, !P5 ; /* 0x000000800300780c */
/* 0x040fe40006f41270 */
/*0530*/ ISETP.LT.AND P3, PT, R3, 0x60, !P5 ; /* 0x000000600300780c */
/* 0x000fc40006f61270 */
/*0540*/ ISETP.LT.AND P4, PT, R3.reuse, 0x40, !P5 ; /* 0x000000400300780c */
/* 0x040fe40006f81270 */
/*0550*/ ISETP.LT.AND P5, PT, R3, 0x20, !P5 ; /* 0x000000200300780c */
/* 0x000fe40006fa1270 */
/*0560*/ IMAD R29, R49.reuse, 0x20, R48 ; /* 0x00000020311d7824 */
/* 0x041fe200078e0230 */
/*0570*/ CS2R R60, SRZ ; /* 0x00000000003c7805 */
/* 0x000fe2000001ff00 */
/*0580*/ P2R R53, PR, RZ, 0x4 ; /* 0x00000004ff357803 */
/* 0x000fe20000000000 */
/*0590*/ IMAD R31, R49, 0x20, R0 ; /* 0x00000020311f7824 */
/* 0x000fe200078e0200 */
/*05a0*/ CS2R R58, SRZ ; /* 0x00000000003a7805 */
/* 0x000fe2000001ff00 */
/*05b0*/ ISETP.GE.AND P6, PT, R29, UR4, PT ; /* 0x000000041d007c0c */
/* 0x000fe4000bfc6270 */
/*05c0*/ IMAD R31, R31, c[0x0][0x180], R46 ; /* 0x000060001f1f7a24 */
/* 0x000fe200078e022e */
/*05d0*/ ISETP.NE.AND P2, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc40003f45270 */
/*05e0*/ P2R R52, PR, RZ, 0x8 ; /* 0x00000008ff347803 */
/* 0x000fe40000000000 */
/*05f0*/ ISETP.NE.AND P3, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f65270 */
/*0600*/ P2R R50, PR, RZ, 0x20 ; /* 0x00000020ff327803 */
/* 0x000fe40000000000 */
/*0610*/ ISETP.NE.AND P5, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003fa5270 */
/*0620*/ @!P6 IMAD.MOV.U32 R28, RZ, RZ, 0x8 ; /* 0x00000008ff1ce424 */
/* 0x000fe200078e00ff */
/*0630*/ P2R R51, PR, RZ, 0x10 ; /* 0x00000010ff337803 */
/* 0x000fe40000000000 */
/*0640*/ ISETP.NE.AND P4, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f85270 */
/*0650*/ @!P6 IMAD.WIDE R28, R29, R28, c[0x0][0x168] ; /* 0x00005a001d1ce625 */
/* 0x000fe200078e021c */
/*0660*/ P2R R55, PR, RZ, 0x1 ; /* 0x00000001ff377803 */
/* 0x000fc40000000000 */
/*0670*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f05270 */
/*0680*/ @!P6 LDG.E.64 R60, [R28.64] ; /* 0x000000081c3ce981 */
/* 0x000ea2000c1e1b00 */
/*0690*/ ISETP.GE.AND P6, PT, R31, UR5, PT ; /* 0x000000051f007c0c */
/* 0x000fe4000bfc6270 */
/*06a0*/ P2R R54, PR, RZ, 0x2 ; /* 0x00000002ff367803 */
/* 0x000fe40000000000 */
/*06b0*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fd20003f25270 */
/*06c0*/ @!P6 IMAD.MOV.U32 R56, RZ, RZ, 0x8 ; /* 0x00000008ff38e424 */
/* 0x000fc800078e00ff */
/*06d0*/ @!P6 IMAD.WIDE R56, R31, R56, c[0x0][0x170] ; /* 0x00005c001f38e625 */
/* 0x000fca00078e0238 */
/*06e0*/ @!P6 LDG.E.64 R58, [R56.64] ; /* 0x00000008383ae981 */
/* 0x000ee2000c1e1b00 */
/*06f0*/ ISETP.NE.AND P6, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc60003fc5270 */
/*0700*/ STS.64 [R47.X8], R60 ; /* 0x0000003c2f007388 */
/* 0x004fe80000008a00 */
/*0710*/ STS.64 [R47.X8+0x2000], R58 ; /* 0x0020003a2f007388 */
/* 0x008fe80000008a00 */
/*0720*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0730*/ @P2 LDS.64 R34, [R2] ; /* 0x0000000002222984 */
/* 0x000fe80000000a00 */
/*0740*/ @P2 LDS.64 R32, [R3.X8+0x2000] ; /* 0x0020000003202984 */
/* 0x000e280000008a00 */
/*0750*/ @P3 LDS.64 R30, [R3.X8+0x2100] ; /* 0x00210000031e3984 */
/* 0x000fe80000008a00 */
/*0760*/ @P3 LDS.64 R28, [R2+0x8] ; /* 0x00000800021c3984 */
/* 0x002e680000000a00 */
/*0770*/ @P5 LDS.64 R38, [R3.X8+0x2200] ; /* 0x0022000003265984 */
/* 0x000fe80000008a00 */
/*0780*/ @P5 LDS.64 R36, [R2+0x10] ; /* 0x0000100002245984 */
/* 0x000ea20000000a00 */
/*0790*/ @P2 DFMA R24, R34, R32, R24 ; /* 0x000000202218222b */
/* 0x0010460000000018 */
/*07a0*/ @P6 LDS.64 R34, [R3.X8+0x2300] ; /* 0x0023000003226984 */
/* 0x001fe80000008a00 */
/*07b0*/ @P6 LDS.64 R32, [R2+0x18] ; /* 0x0000180002206984 */
/* 0x000e220000000a00 */
/*07c0*/ @P3 DFMA R24, R30, R28, R24 ; /* 0x0000001c1e18322b */
/* 0x0022860000000018 */
/*07d0*/ @P4 LDS.64 R30, [R3.X8+0x2400] ; /* 0x00240000031e4984 */
/* 0x002fe80000008a00 */
/*07e0*/ @P4 LDS.64 R28, [R2+0x20] ; /* 0x00002000021c4984 */
/* 0x000e620000000a00 */
/*07f0*/ @P5 DFMA R24, R38, R36, R24 ; /* 0x000000242618522b */
/* 0x0044060000000018 */
/*0800*/ @P0 LDS.64 R38, [R3.X8+0x2500] ; /* 0x0025000003260984 */
/* 0x004fe80000008a00 */
/*0810*/ @P0 LDS.64 R36, [R2+0x28] ; /* 0x0000280002240984 */
/* 0x000ea20000000a00 */
/*0820*/ ISETP.NE.AND P2, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f45270 */
/*0830*/ ISETP.NE.AND P3, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f65270 */
/*0840*/ @P6 DFMA R24, R34, R32, R24 ; /* 0x000000202218622b */
/* 0x0010640000000018 */
/*0850*/ @P1 LDS.64 R34, [R3.X8+0x2600] ; /* 0x0026000003221984 */
/* 0x001fe80000008a00 */
/*0860*/ @P1 LDS.64 R32, [R2+0x30] ; /* 0x0000300002201984 */
/* 0x000e220000000a00 */
/*0870*/ @P4 DFMA R24, R30, R28, R24 ; /* 0x0000001c1e18422b */
/* 0x0022860000000018 */
/*0880*/ @P2 LDS.64 R30, [R3.X8+0x2700] ; /* 0x00270000031e2984 */
/* 0x002fe80000008a00 */
/*0890*/ @P2 LDS.64 R28, [R2+0x38] ; /* 0x00003800021c2984 */
/* 0x000e620000000a00 */
/*08a0*/ @P0 DFMA R24, R38, R36, R24 ; /* 0x000000242618022b */
/* 0x0044060000000018 */
/*08b0*/ @P3 LDS.64 R38, [R3.X8+0x2800] ; /* 0x0028000003263984 */
/* 0x004fe80000008a00 */
/*08c0*/ @P3 LDS.64 R36, [R2+0x40] ; /* 0x0000400002243984 */
/* 0x000ea20000000a00 */
/*08d0*/ ISETP.NE.AND P5, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe40003fa5270 */
/*08e0*/ ISETP.NE.AND P6, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe40003fc5270 */
/*08f0*/ ISETP.NE.AND P4, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe20003f85270 */
/*0900*/ @P1 DFMA R24, R34, R32, R24 ; /* 0x000000202218122b */
/* 0x0010500000000018 */
/*0910*/ @P5 LDS.64 R34, [R3.X8+0x2900] ; /* 0x0029000003225984 */
/* 0x001fe80000008a00 */
/*0920*/ @P5 LDS.64 R32, [R2+0x48] ; /* 0x0000480002205984 */
/* 0x000e220000000a00 */
/*0930*/ @P2 DFMA R24, R30, R28, R24 ; /* 0x0000001c1e18222b */
/* 0x0022860000000018 */
/*0940*/ @P6 LDS.64 R30, [R3.X8+0x2a00] ; /* 0x002a0000031e6984 */
/* 0x002fe80000008a00 */
/*0950*/ @P6 LDS.64 R28, [R2+0x50] ; /* 0x00005000021c6984 */
/* 0x000e620000000a00 */
/*0960*/ @P3 DFMA R24, R38, R36, R24 ; /* 0x000000242618322b */
/* 0x0044060000000018 */
/*0970*/ @P4 LDS.64 R38, [R3.X8+0x2b00] ; /* 0x002b000003264984 */
/* 0x004fe80000008a00 */
/*0980*/ @P4 LDS.64 R36, [R2+0x58] ; /* 0x0000580002244984 */
/* 0x000ea20000000a00 */
/*0990*/ ISETP.NE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe40003f05270 */
/*09a0*/ ISETP.NE.AND P1, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fe40003f25270 */
/*09b0*/ ISETP.NE.AND P2, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fe20003f45270 */
/*09c0*/ @P5 DFMA R24, R34, R32, R24 ; /* 0x000000202218522b */
/* 0x0010500000000018 */
/*09d0*/ @P0 LDS.64 R34, [R3.X8+0x2c00] ; /* 0x002c000003220984 */
/* 0x001fe80000008a00 */
/*09e0*/ @P0 LDS.64 R32, [R2+0x60] ; /* 0x0000600002200984 */
/* 0x000e220000000a00 */
/*09f0*/ @P6 DFMA R24, R30, R28, R24 ; /* 0x0000001c1e18622b */
/* 0x0022860000000018 */
/*0a00*/ @P1 LDS.64 R30, [R3.X8+0x2d00] ; /* 0x002d0000031e1984 */
/* 0x002fe80000008a00 */
/*0a10*/ @P1 LDS.64 R28, [R2+0x68] ; /* 0x00006800021c1984 */
/* 0x000e620000000a00 */
/*0a20*/ @P4 DFMA R24, R38, R36, R24 ; /* 0x000000242618422b */
/* 0x0044060000000018 */
/*0a30*/ @P2 LDS.64 R38, [R3.X8+0x2e00] ; /* 0x002e000003262984 */
/* 0x004fe80000008a00 */
/*0a40*/ @P2 LDS.64 R36, [R2+0x70] ; /* 0x0000700002242984 */
/* 0x000ea20000000a00 */
/*0a50*/ ISETP.NE.AND P3, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fe40003f65270 */
/*0a60*/ ISETP.NE.AND P5, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fe20003fa5270 */
/*0a70*/ @P0 DFMA R24, R34, R32, R24 ; /* 0x000000202218022b */
/* 0x0010540000000018 */
/*0a80*/ @P3 LDS.64 R34, [R3.X8+0x2f00] ; /* 0x002f000003223984 */
/* 0x001fe80000008a00 */
/*0a90*/ @P3 LDS.64 R32, [R2+0x78] ; /* 0x0000780002203984 */
/* 0x000e220000000a00 */
/*0aa0*/ @P1 DFMA R24, R30, R28, R24 ; /* 0x0000001c1e18122b */
/* 0x0022860000000018 */
/*0ab0*/ @P5 LDS.64 R30, [R3.X8+0x3000] ; /* 0x00300000031e5984 */
/* 0x002fe20000008a00 */
/*0ac0*/ ISETP.NE.AND P6, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fc60003fc5270 */
/*0ad0*/ @P5 LDS.64 R28, [R2+0x80] ; /* 0x00008000021c5984 */
/* 0x000e620000000a00 */
/*0ae0*/ @P2 DFMA R24, R38, R36, R24 ; /* 0x000000242618222b */
/* 0x0044220000000018 */
/*0af0*/ ISETP.NE.AND P2, PT, R41, RZ, PT ; /* 0x000000ff2900720c */
/* 0x000fc80003f45270 */
/*0b00*/ P2R R56, PR, RZ, 0x4 ; /* 0x00000004ff387803 */
/* 0x000fe40000000000 */
/*0b10*/ ISETP.NE.AND P2, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fe40003f45270 */
/*0b20*/ @P6 LDS.64 R36, [R3.X8+0x3100] ; /* 0x0031000003246984 */
/* 0x004fe80000008a00 */
/*0b30*/ @P6 LDS.64 R38, [R2+0x88] ; /* 0x0000880002266984 */
/* 0x000ea20000000a00 */
/*0b40*/ ISETP.NE.AND P0, PT, R23, RZ, PT ; /* 0x000000ff1700720c */
/* 0x000fe20003f05270 */
/*0b50*/ @P3 DFMA R24, R34, R32, R24 ; /* 0x000000202218322b */
/* 0x00104a0000000018 */
/*0b60*/ @P2 LDS.64 R34, [R3.X8+0x3200] ; /* 0x0032000003222984 */
/* 0x001fe80000008a00 */
/*0b70*/ @P2 LDS.64 R32, [R2+0x90] ; /* 0x0000900002202984 */
/* 0x000e220000000a00 */
/*0b80*/ @P5 DFMA R24, R30, R28, R24 ; /* 0x0000001c1e18522b */
/* 0x0022860000000018 */
/*0b90*/ @P0 LDS.64 R28, [R3.X8+0x3300] ; /* 0x00330000031c0984 */
/* 0x002fe80000008a00 */
/*0ba0*/ @P0 LDS.64 R30, [R2+0x98] ; /* 0x00009800021e0984 */
/* 0x000e620000000a00 */
/*0bb0*/ ISETP.NE.AND P1, PT, R40, RZ, PT ; /* 0x000000ff2800720c */
/* 0x000fe20003f25270 */
/*0bc0*/ @P6 DFMA R24, R36, R38, R24 ; /* 0x000000262418622b */
/* 0x0044220000000018 */
/*0bd0*/ ISETP.NE.AND P3, PT, R42, RZ, PT ; /* 0x000000ff2a00720c */
/* 0x000fd60003f65270 */
/*0be0*/ @P1 LDS.64 R36, [R3.X8+0x3400] ; /* 0x0034000003241984 */
/* 0x004fe80000008a00 */
/*0bf0*/ @P1 LDS.64 R38, [R2+0xa0] ; /* 0x0000a00002261984 */
/* 0x000ea20000000a00 */
/*0c00*/ @P2 DFMA R24, R34, R32, R24 ; /* 0x000000202218222b */
/* 0x001e620000000018 */
/*0c10*/ ISETP.NE.AND P2, PT, R56, RZ, PT ; /* 0x000000ff3800720c */
/* 0x000fca0003f45270 */
/*0c20*/ @P0 DFMA R24, R28, R30, R24 ; /* 0x0000001e1c18022b */
/* 0x0020a40000000018 */
/*0c30*/ @P3 LDS.64 R30, [R3.X8+0x3600] ; /* 0x00360000031e3984 */
/* 0x001fec0000008a00 */
/*0c40*/ @P2 LDS.64 R34, [R3.X8+0x3500] ; /* 0x0035000003222984 */
/* 0x000fe80000008a00 */
/*0c50*/ @P2 LDS.64 R32, [R2+0xa8] ; /* 0x0000a80002202984 */
/* 0x000e280000000a00 */
/*0c60*/ @P3 LDS.64 R28, [R2+0xb0] ; /* 0x0000b000021c3984 */
/* 0x000e620000000a00 */
/*0c70*/ ISETP.NE.AND P4, PT, R43, RZ, PT ; /* 0x000000ff2b00720c */
/* 0x000fc40003f85270 */
/*0c80*/ ISETP.NE.AND P5, PT, R44, RZ, PT ; /* 0x000000ff2c00720c */
/* 0x000fe20003fa5270 */
/*0c90*/ @P1 DFMA R24, R36, R38, R24 ; /* 0x000000262418122b */
/* 0x0044220000000018 */
/*0ca0*/ ISETP.NE.AND P6, PT, R45, RZ, PT ; /* 0x000000ff2d00720c */
/* 0x000fd20003fc5270 */
/*0cb0*/ @P4 LDS.64 R38, [R3.X8+0x3700] ; /* 0x0037000003264984 */
/* 0x004fe80000008a00 */
/*0cc0*/ @P4 LDS.64 R36, [R2+0xb8] ; /* 0x0000b80002244984 */
/* 0x000ea20000000a00 */
/*0cd0*/ @P2 DFMA R24, R34, R32, R24 ; /* 0x000000202218222b */
/* 0x0010460000000018 */
/*0ce0*/ @P5 LDS.64 R34, [R3.X8+0x3800] ; /* 0x0038000003225984 */
/* 0x001fe80000008a00 */
/*0cf0*/ @P5 LDS.64 R32, [R2+0xc0] ; /* 0x0000c00002205984 */
/* 0x000e220000000a00 */
/*0d00*/ @P3 DFMA R24, R30, R28, R24 ; /* 0x0000001c1e18322b */
/* 0x0022860000000018 */
/*0d10*/ @P6 LDS.64 R30, [R3.X8+0x3900] ; /* 0x00390000031e6984 */
/* 0x002fe80000008a00 */
/*0d20*/ @P6 LDS.64 R28, [R2+0xc8] ; /* 0x0000c800021c6984 */
/* 0x000e620000000a00 */
/*0d30*/ ISETP.NE.AND P0, PT, R55, RZ, PT ; /* 0x000000ff3700720c */
/* 0x000fe40003f05270 */
/*0d40*/ ISETP.NE.AND P1, PT, R54, RZ, PT ; /* 0x000000ff3600720c */
/* 0x000fe40003f25270 */
/*0d50*/ ISETP.NE.AND P2, PT, R53, RZ, PT ; /* 0x000000ff3500720c */
/* 0x000fe20003f45270 */
/*0d60*/ @P4 DFMA R24, R38, R36, R24 ; /* 0x000000242618422b */
/* 0x0044100000000018 */
/*0d70*/ @P0 LDS.64 R38, [R3.X8+0x3a00] ; /* 0x003a000003260984 */
/* 0x004fe80000008a00 */
/*0d80*/ @P0 LDS.64 R36, [R2+0xd0] ; /* 0x0000d00002240984 */
/* 0x000ea20000000a00 */
/*0d90*/ @P5 DFMA R24, R34, R32, R24 ; /* 0x000000202218522b */
/* 0x0010460000000018 */
/*0da0*/ @P1 LDS.64 R34, [R3.X8+0x3b00] ; /* 0x003b000003221984 */
/* 0x001fe80000008a00 */
/*0db0*/ @P1 LDS.64 R32, [R2+0xd8] ; /* 0x0000d80002201984 */
/* 0x000e220000000a00 */
/*0dc0*/ @P6 DFMA R24, R30, R28, R24 ; /* 0x0000001c1e18622b */
/* 0x0022860000000018 */
/*0dd0*/ @P2 LDS.64 R30, [R3.X8+0x3c00] ; /* 0x003c0000031e2984 */
/* 0x002fe80000008a00 */
/*0de0*/ @P2 LDS.64 R28, [R2+0xe0] ; /* 0x0000e000021c2984 */
/* 0x000e620000000a00 */
/*0df0*/ ISETP.NE.AND P3, PT, R52, RZ, PT ; /* 0x000000ff3400720c */
/* 0x000fe40003f65270 */
/*0e00*/ ISETP.NE.AND P4, PT, R51, RZ, PT ; /* 0x000000ff3300720c */
/* 0x000fe40003f85270 */
/*0e10*/ ISETP.NE.AND P5, PT, R50, RZ, PT ; /* 0x000000ff3200720c */
/* 0x000fe20003fa5270 */
/*0e20*/ @P0 DFMA R24, R38, R36, R24 ; /* 0x000000242618022b */
/* 0x0044100000000018 */
/*0e30*/ @P3 LDS.64 R38, [R3.X8+0x3d00] ; /* 0x003d000003263984 */
/* 0x004fe80000008a00 */
/*0e40*/ @P3 LDS.64 R36, [R2+0xe8] ; /* 0x0000e80002243984 */
/* 0x000ea80000000a00 */
/*0e50*/ @P5 LDS.64 R50, [R3.X8+0x3f00] ; /* 0x003f000003325984 */
/* 0x000fe20000008a00 */
/*0e60*/ @P1 DFMA R24, R34, R32, R24 ; /* 0x000000202218122b */
/* 0x0010460000000018 */
/*0e70*/ @P4 LDS.64 R34, [R3.X8+0x3e00] ; /* 0x003e000003224984 */
/* 0x001fe80000008a00 */
/*0e80*/ @P4 LDS.64 R32, [R2+0xf0] ; /* 0x0000f00002204984 */
/* 0x000e220000000a00 */
/*0e90*/ @P2 DFMA R24, R30, R28, R24 ; /* 0x0000001c1e18222b */
/* 0x0022860000000018 */
/*0ea0*/ @P5 LDS.64 R28, [R2+0xf8] ; /* 0x0000f800021c5984 */
/* 0x002e620000000a00 */
/*0eb0*/ IADD3 R49, R49, 0x1, RZ ; /* 0x0000000131317810 */
/* 0x000fc80007ffe0ff */
/*0ec0*/ I2F.F64 R30, R49 ; /* 0x00000031001e7312 */
/* 0x000ee20000201c00 */
/*0ed0*/ @P3 DFMA R24, R38, R36, R24 ; /* 0x000000242618322b */
/* 0x004e220000000018 */
/*0ee0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0ef0*/ DSETP.GT.AND P6, PT, R26, R30, PT ; /* 0x0000001e1a00722a */
/* 0x008fc80003fc4000 */
/*0f00*/ @P4 DFMA R24, R34, R32, R24 ; /* 0x000000202218422b */
/* 0x001e4c0000000018 */
/*0f10*/ @P5 DFMA R24, R50, R28, R24 ; /* 0x0000001c3218522b */
/* 0x0020480000000018 */
/*0f20*/ @P6 BRA 0x560 ; /* 0xfffff63000006947 */
/* 0x000fea000383ffff */
/*0f30*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x001e240000002100 */
/*0f40*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x180], PT ; /* 0x0000600002007a0c */
/* 0x001fc80003f06270 */
/*0f50*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0f60*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0f70*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0f80*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000ea20000002600 */
/*0f90*/ IMAD R3, R3, 0x20, R2 ; /* 0x0000002003037824 */
/* 0x001fe400078e0202 */
/*0fa0*/ IMAD R2, R5, 0x20, R0 ; /* 0x0000002005027824 */
/* 0x004fe400078e0200 */
/*0fb0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x8 ; /* 0x00000008ff057424 */
/* 0x000fe400078e00ff */
/*0fc0*/ IMAD R2, R2, c[0x0][0x180], R3 ; /* 0x0000600002027a24 */
/* 0x000fc800078e0203 */
/*0fd0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0fe0*/ STG.E.64 [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x002fe2000c101b08 */
/*0ff0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1000*/ BRA 0x1000; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15MatrixMulKernelPdS_S_iii
.globl _Z15MatrixMulKernelPdS_S_iii
.p2align 8
.type _Z15MatrixMulKernelPdS_S_iii,@function
_Z15MatrixMulKernelPdS_S_iii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b32 s8, s[0:1], 0x20
v_mov_b32_e32 v1, 0
v_bfe_u32 v7, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_cmpk_lt_i32 s3, 0xffe1
s_cbranch_scc1 .LBB0_18
s_load_b128 s[4:7], s[0:1], 0x8
v_lshlrev_b32_e32 v8, 5, v7
v_lshl_add_u32 v1, s15, 5, v7
s_ashr_i32 s9, s3, 31
v_lshl_or_b32 v11, v0, 3, 0x2000
s_lshr_b32 s9, s9, 27
v_lshlrev_b32_e32 v12, 8, v7
v_mad_u64_u32 v[3:4], null, v1, s3, v[0:1]
v_mov_b32_e32 v1, 0
v_add_lshl_u32 v9, v8, v0, 3
v_lshl_add_u32 v4, s14, 5, v0
v_mov_b32_e32 v2, 0
s_add_i32 s9, s3, s9
s_mul_i32 s10, s3, s2
v_add_nc_u32_e32 v10, 0x2000, v9
s_ashr_i32 s9, s9, 5
s_mul_i32 s3, s8, s3
s_mov_b32 s11, 0
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_lshl_b32 s12, s11, 5
s_mov_b32 s13, exec_lo
v_add_nc_u32_e32 v5, s12, v3
v_cmpx_le_i32_e64 s10, v5
s_xor_b32 s13, exec_lo, s13
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v6, v5
ds_store_b64 v9, v[5:6]
.LBB0_4:
s_and_not1_saveexec_b32 s13, s13
s_cbranch_execz .LBB0_6
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 3, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b64 v[5:6], v[5:6], off
s_waitcnt vmcnt(0)
ds_store_b64 v9, v[5:6]
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s13
v_add_nc_u32_e32 v13, s12, v7
s_mov_b32 s12, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v13, s8, v[4:5]
v_cmpx_le_i32_e64 s3, v5
s_xor_b32 s12, exec_lo, s12
s_cbranch_execz .LBB0_8
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v6, v5
ds_store_b64 v10, v[5:6]
.LBB0_8:
s_and_not1_saveexec_b32 s12, s12
s_cbranch_execz .LBB0_10
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 3, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s6, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
global_load_b64 v[5:6], v[5:6], off
s_waitcnt vmcnt(0)
ds_store_b64 v10, v[5:6]
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s12
v_mov_b32_e32 v5, v8
v_dual_mov_b32 v6, v0 :: v_dual_mov_b32 v13, v11
s_mov_b32 s12, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_13
.p2align 6
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s16
.LBB0_12:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s13
v_add_nc_u32_e32 v13, 0x100, v13
v_add_nc_u32_e32 v6, 32, v6
v_add_nc_u32_e32 v5, 1, v5
s_add_i32 s12, s12, 8
s_cmpk_eq_i32 s12, 0x100
s_cbranch_scc1 .LBB0_16
.LBB0_13:
s_mov_b32 s13, exec_lo
v_cmpx_gt_u32_e32 0x400, v5
s_cbranch_execz .LBB0_12
s_mov_b32 s16, exec_lo
v_cmpx_gt_u32_e32 0x400, v6
s_cbranch_execz .LBB0_11
v_add_nc_u32_e32 v14, s12, v12
ds_load_b64 v[14:15], v14
ds_load_b64 v[16:17], v13
s_waitcnt lgkmcnt(0)
v_fma_f64 v[1:2], v[14:15], v[16:17], v[1:2]
s_branch .LBB0_11
.LBB0_16:
s_set_inst_prefetch_distance 0x2
s_add_i32 s12, s11, 1
s_cmp_le_i32 s9, s11
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_18
s_mov_b32 s11, s12
s_branch .LBB0_2
.LBB0_18:
v_cmp_gt_i32_e32 vcc_lo, s2, v7
v_cmp_gt_i32_e64 s2, s8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_20
v_lshl_add_u32 v3, s15, 5, v7
s_load_b64 s[0:1], s[0:1], 0x0
s_lshl_b32 s2, s14, 5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v3, s8
v_add3_u32 v3, s2, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 3, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_b64 v[3:4], v[1:2], off
.LBB0_20:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15MatrixMulKernelPdS_S_iii
.amdhsa_group_segment_fixed_size 16384
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15MatrixMulKernelPdS_S_iii, .Lfunc_end0-_Z15MatrixMulKernelPdS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 16384
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15MatrixMulKernelPdS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z15MatrixMulKernelPdS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00112554_00000000-6_MatrixMulKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z15MatrixMulKernelPdS_S_iiiPdS_S_iii
.type _Z42__device_stub__Z15MatrixMulKernelPdS_S_iiiPdS_S_iii, @function
_Z42__device_stub__Z15MatrixMulKernelPdS_S_iiiPdS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15MatrixMulKernelPdS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z15MatrixMulKernelPdS_S_iiiPdS_S_iii, .-_Z42__device_stub__Z15MatrixMulKernelPdS_S_iiiPdS_S_iii
.globl _Z15MatrixMulKernelPdS_S_iii
.type _Z15MatrixMulKernelPdS_S_iii, @function
_Z15MatrixMulKernelPdS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z15MatrixMulKernelPdS_S_iiiPdS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15MatrixMulKernelPdS_S_iii, .-_Z15MatrixMulKernelPdS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15MatrixMulKernelPdS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15MatrixMulKernelPdS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "MatrixMulKernel.hip"
.globl _Z30__device_stub__MatrixMulKernelPdS_S_iii # -- Begin function _Z30__device_stub__MatrixMulKernelPdS_S_iii
.p2align 4, 0x90
.type _Z30__device_stub__MatrixMulKernelPdS_S_iii,@function
_Z30__device_stub__MatrixMulKernelPdS_S_iii: # @_Z30__device_stub__MatrixMulKernelPdS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15MatrixMulKernelPdS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z30__device_stub__MatrixMulKernelPdS_S_iii, .Lfunc_end0-_Z30__device_stub__MatrixMulKernelPdS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15MatrixMulKernelPdS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15MatrixMulKernelPdS_S_iii,@object # @_Z15MatrixMulKernelPdS_S_iii
.section .rodata,"a",@progbits
.globl _Z15MatrixMulKernelPdS_S_iii
.p2align 3, 0x0
_Z15MatrixMulKernelPdS_S_iii:
.quad _Z30__device_stub__MatrixMulKernelPdS_S_iii
.size _Z15MatrixMulKernelPdS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15MatrixMulKernelPdS_S_iii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__MatrixMulKernelPdS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15MatrixMulKernelPdS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
void checkCudaError(cudaError_t errorCode)
{
if (errorCode != cudaSuccess)
fprintf(stderr, "Error %d\n", errorCode);
}
int main(void)
{
float *ha, *hb; // host data
float *da, *db; // device data
int N = 10, nbytes, i;
nbytes = N * sizeof(float);
ha = (float *) malloc(nbytes);
hb = (float *) malloc(nbytes);
checkCudaError(cudaMalloc((void **) &da, nbytes));
checkCudaError(cudaMalloc((void **) &db, nbytes));
for (i = 0; i < N; i++)
ha[i] = 100.0 + i;
checkCudaError(cudaMemcpy(da, ha, nbytes, cudaMemcpyHostToDevice));
checkCudaError(cudaMemcpy(db, da, nbytes, cudaMemcpyDeviceToDevice));
checkCudaError(cudaMemcpy(hb, db, nbytes, cudaMemcpyDeviceToHost));
for (i = 0; i < N; i++)
printf("%f %f\n", ha[i], hb[i]);
free(ha);
free(hb);
cudaFree(da);
cudaFree(db);
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
void checkCudaError(cudaError_t errorCode)
{
if (errorCode != cudaSuccess)
fprintf(stderr, "Error %d\n", errorCode);
}
int main(void)
{
float *ha, *hb; // host data
float *da, *db; // device data
int N = 10, nbytes, i;
nbytes = N * sizeof(float);
ha = (float *) malloc(nbytes);
hb = (float *) malloc(nbytes);
checkCudaError(cudaMalloc((void **) &da, nbytes));
checkCudaError(cudaMalloc((void **) &db, nbytes));
for (i = 0; i < N; i++)
ha[i] = 100.0 + i;
checkCudaError(cudaMemcpy(da, ha, nbytes, cudaMemcpyHostToDevice));
checkCudaError(cudaMemcpy(db, da, nbytes, cudaMemcpyDeviceToDevice));
checkCudaError(cudaMemcpy(hb, db, nbytes, cudaMemcpyDeviceToHost));
for (i = 0; i < N; i++)
printf("%f %f\n", ha[i], hb[i]);
free(ha);
free(hb);
cudaFree(da);
cudaFree(db);
return 0;
} | .file "tmpxft_00161543_00000000-6_dataMovement.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Error %d\n"
.text
.globl _Z14checkCudaError9cudaError
.type _Z14checkCudaError9cudaError, @function
_Z14checkCudaError9cudaError:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
subq $8, %rsp
.cfi_def_cfa_offset 16
movl %edi, %ecx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z14checkCudaError9cudaError, .-_Z14checkCudaError9cudaError
.section .rodata.str1.1
.LC2:
.string "%f %f\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $40, %edi
call malloc@PLT
movq %rax, %rbp
movl $40, %edi
call malloc@PLT
movq %rax, %r12
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z14checkCudaError9cudaError
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z14checkCudaError9cudaError
movl $0, %eax
movsd .LC1(%rip), %xmm1
.L11:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L11
movl $1, %ecx
movl $40, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z14checkCudaError9cudaError
movl $3, %ecx
movl $40, %edx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z14checkCudaError9cudaError
movl $2, %ecx
movl $40, %edx
movq 16(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z14checkCudaError9cudaError
movl $0, %ebx
leaq .LC2(%rip), %r13
.L12:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx), %xmm0
pxor %xmm1, %xmm1
cvtss2sd (%r12,%rbx), %xmm1
movq %r13, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $40, %rbx
jne .L12
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L17
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1079574528
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
void checkCudaError(cudaError_t errorCode)
{
if (errorCode != cudaSuccess)
fprintf(stderr, "Error %d\n", errorCode);
}
int main(void)
{
float *ha, *hb; // host data
float *da, *db; // device data
int N = 10, nbytes, i;
nbytes = N * sizeof(float);
ha = (float *) malloc(nbytes);
hb = (float *) malloc(nbytes);
checkCudaError(cudaMalloc((void **) &da, nbytes));
checkCudaError(cudaMalloc((void **) &db, nbytes));
for (i = 0; i < N; i++)
ha[i] = 100.0 + i;
checkCudaError(cudaMemcpy(da, ha, nbytes, cudaMemcpyHostToDevice));
checkCudaError(cudaMemcpy(db, da, nbytes, cudaMemcpyDeviceToDevice));
checkCudaError(cudaMemcpy(hb, db, nbytes, cudaMemcpyDeviceToHost));
for (i = 0; i < N; i++)
printf("%f %f\n", ha[i], hb[i]);
free(ha);
free(hb);
cudaFree(da);
cudaFree(db);
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
void checkCudaError(hipError_t errorCode)
{
if (errorCode != hipSuccess)
fprintf(stderr, "Error %d\n", errorCode);
}
int main(void)
{
float *ha, *hb; // host data
float *da, *db; // device data
int N = 10, nbytes, i;
nbytes = N * sizeof(float);
ha = (float *) malloc(nbytes);
hb = (float *) malloc(nbytes);
checkCudaError(hipMalloc((void **) &da, nbytes));
checkCudaError(hipMalloc((void **) &db, nbytes));
for (i = 0; i < N; i++)
ha[i] = 100.0 + i;
checkCudaError(hipMemcpy(da, ha, nbytes, hipMemcpyHostToDevice));
checkCudaError(hipMemcpy(db, da, nbytes, hipMemcpyDeviceToDevice));
checkCudaError(hipMemcpy(hb, db, nbytes, hipMemcpyDeviceToHost));
for (i = 0; i < N; i++)
printf("%f %f\n", ha[i], hb[i]);
free(ha);
free(hb);
hipFree(da);
hipFree(db);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
void checkCudaError(hipError_t errorCode)
{
if (errorCode != hipSuccess)
fprintf(stderr, "Error %d\n", errorCode);
}
int main(void)
{
float *ha, *hb; // host data
float *da, *db; // device data
int N = 10, nbytes, i;
nbytes = N * sizeof(float);
ha = (float *) malloc(nbytes);
hb = (float *) malloc(nbytes);
checkCudaError(hipMalloc((void **) &da, nbytes));
checkCudaError(hipMalloc((void **) &db, nbytes));
for (i = 0; i < N; i++)
ha[i] = 100.0 + i;
checkCudaError(hipMemcpy(da, ha, nbytes, hipMemcpyHostToDevice));
checkCudaError(hipMemcpy(db, da, nbytes, hipMemcpyDeviceToDevice));
checkCudaError(hipMemcpy(hb, db, nbytes, hipMemcpyDeviceToHost));
for (i = 0; i < N; i++)
printf("%f %f\n", ha[i], hb[i]);
free(ha);
free(hb);
hipFree(da);
hipFree(db);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
void checkCudaError(hipError_t errorCode)
{
if (errorCode != hipSuccess)
fprintf(stderr, "Error %d\n", errorCode);
}
int main(void)
{
float *ha, *hb; // host data
float *da, *db; // device data
int N = 10, nbytes, i;
nbytes = N * sizeof(float);
ha = (float *) malloc(nbytes);
hb = (float *) malloc(nbytes);
checkCudaError(hipMalloc((void **) &da, nbytes));
checkCudaError(hipMalloc((void **) &db, nbytes));
for (i = 0; i < N; i++)
ha[i] = 100.0 + i;
checkCudaError(hipMemcpy(da, ha, nbytes, hipMemcpyHostToDevice));
checkCudaError(hipMemcpy(db, da, nbytes, hipMemcpyDeviceToDevice));
checkCudaError(hipMemcpy(hb, db, nbytes, hipMemcpyDeviceToHost));
for (i = 0; i < N; i++)
printf("%f %f\n", ha[i], hb[i]);
free(ha);
free(hb);
hipFree(da);
hipFree(db);
return 0;
} | .text
.file "dataMovement.hip"
.globl _Z14checkCudaError10hipError_t # -- Begin function _Z14checkCudaError10hipError_t
.p2align 4, 0x90
.type _Z14checkCudaError10hipError_t,@function
_Z14checkCudaError10hipError_t: # @_Z14checkCudaError10hipError_t
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB0_2
# %bb.1:
retq
.LBB0_2:
movl %edi, %edx
movq stderr(%rip), %rdi
movl $.L.str, %esi
xorl %eax, %eax
jmp fprintf # TAILCALL
.Lfunc_end0:
.size _Z14checkCudaError10hipError_t, .Lfunc_end0-_Z14checkCudaError10hipError_t
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $40, %edi
callq malloc
movq %rax, %rbx
movl $40, %edi
callq malloc
movq %rax, %r14
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
.LBB1_2: # %_Z14checkCudaError10hipError_t.exit
movq %rsp, %rdi
movl $40, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_3
.LBB1_4: # %_Z14checkCudaError10hipError_t.exit25.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_5: # %_Z14checkCudaError10hipError_t.exit25
# =>This Inner Loop Header: Depth=1
leal 100(%rax), %ecx
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB1_5
# %bb.6:
movq 8(%rsp), %rdi
movl $40, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_7
.LBB1_8: # %_Z14checkCudaError10hipError_t.exit27
movq (%rsp), %rdi
movq 8(%rsp), %rsi
movl $40, %edx
movl $3, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_9
.LBB1_10: # %_Z14checkCudaError10hipError_t.exit29
movq (%rsp), %rsi
movl $40, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_11
.LBB1_12: # %_Z14checkCudaError10hipError_t.exit31.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_13: # %_Z14checkCudaError10hipError_t.exit31
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss (%r14,%r15,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str.1, %edi
movb $2, %al
callq printf
incq %r15
cmpq $10, %r15
jne .LBB1_13
# %bb.14:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 48
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB1_2
.LBB1_3:
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB1_4
.LBB1_7:
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB1_8
.LBB1_9:
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB1_10
.LBB1_11:
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB1_12
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error %d\n"
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%f %f\n"
.size .L.str.1, 7
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00161543_00000000-6_dataMovement.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Error %d\n"
.text
.globl _Z14checkCudaError9cudaError
.type _Z14checkCudaError9cudaError, @function
_Z14checkCudaError9cudaError:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
subq $8, %rsp
.cfi_def_cfa_offset 16
movl %edi, %ecx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z14checkCudaError9cudaError, .-_Z14checkCudaError9cudaError
.section .rodata.str1.1
.LC2:
.string "%f %f\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $40, %edi
call malloc@PLT
movq %rax, %rbp
movl $40, %edi
call malloc@PLT
movq %rax, %r12
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z14checkCudaError9cudaError
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z14checkCudaError9cudaError
movl $0, %eax
movsd .LC1(%rip), %xmm1
.L11:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L11
movl $1, %ecx
movl $40, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z14checkCudaError9cudaError
movl $3, %ecx
movl $40, %edx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z14checkCudaError9cudaError
movl $2, %ecx
movl $40, %edx
movq 16(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z14checkCudaError9cudaError
movl $0, %ebx
leaq .LC2(%rip), %r13
.L12:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx), %xmm0
pxor %xmm1, %xmm1
cvtss2sd (%r12,%rbx), %xmm1
movq %r13, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $40, %rbx
jne .L12
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L17
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1079574528
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "dataMovement.hip"
.globl _Z14checkCudaError10hipError_t # -- Begin function _Z14checkCudaError10hipError_t
.p2align 4, 0x90
.type _Z14checkCudaError10hipError_t,@function
_Z14checkCudaError10hipError_t: # @_Z14checkCudaError10hipError_t
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB0_2
# %bb.1:
retq
.LBB0_2:
movl %edi, %edx
movq stderr(%rip), %rdi
movl $.L.str, %esi
xorl %eax, %eax
jmp fprintf # TAILCALL
.Lfunc_end0:
.size _Z14checkCudaError10hipError_t, .Lfunc_end0-_Z14checkCudaError10hipError_t
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $40, %edi
callq malloc
movq %rax, %rbx
movl $40, %edi
callq malloc
movq %rax, %r14
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
.LBB1_2: # %_Z14checkCudaError10hipError_t.exit
movq %rsp, %rdi
movl $40, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_3
.LBB1_4: # %_Z14checkCudaError10hipError_t.exit25.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_5: # %_Z14checkCudaError10hipError_t.exit25
# =>This Inner Loop Header: Depth=1
leal 100(%rax), %ecx
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB1_5
# %bb.6:
movq 8(%rsp), %rdi
movl $40, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_7
.LBB1_8: # %_Z14checkCudaError10hipError_t.exit27
movq (%rsp), %rdi
movq 8(%rsp), %rsi
movl $40, %edx
movl $3, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_9
.LBB1_10: # %_Z14checkCudaError10hipError_t.exit29
movq (%rsp), %rsi
movl $40, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_11
.LBB1_12: # %_Z14checkCudaError10hipError_t.exit31.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_13: # %_Z14checkCudaError10hipError_t.exit31
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss (%r14,%r15,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str.1, %edi
movb $2, %al
callq printf
incq %r15
cmpq $10, %r15
jne .LBB1_13
# %bb.14:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 48
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB1_2
.LBB1_3:
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB1_4
.LBB1_7:
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB1_8
.LBB1_9:
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB1_10
.LBB1_11:
movq stderr(%rip), %rdi
movl $.L.str, %esi
movl %eax, %edx
xorl %eax, %eax
callq fprintf
jmp .LBB1_12
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error %d\n"
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%f %f\n"
.size .L.str.1, 7
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
// CUDA to assign a value to each element of the array of integers A[256] using 256 threads.
// Each A[i] is assigned with the value of 2*i, for i = 0 to 255.
#define T 256 // As Threads
// #define n 256
__global__ void vecMultiply(int *A)
{
int i = threadIdx.x;
A[i] = A[i] * 2;
}
int main (int argc, char *argv[])
{
int i;
int size = T*sizeof(int);
int a[T], *devA;
for (i=0; i< T; i++)
{
a[i] = i + 1;
}
cudaMalloc( (void**)&devA,size);
cudaMemcpy( devA, a, size, cudaMemcpyHostToDevice);
vecMultiply<<<1, T>>>(devA);
printf("Before\n");
for (i=0; i< T; i++)
{
printf("%d ", a[i]);
}
printf("\n");
cudaMemcpy(a, devA, size, cudaMemcpyDeviceToHost);
cudaFree(devA);
printf("After\n");
for (i=0; i < T; i++) {
printf("%d ",a[i]);
}
printf("\n");
} | code for sm_80
Function : _Z11vecMultiplyPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fca00078e0203 */
/*0050*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0060*/ SHF.L.U32 R5, R0, 0x1, RZ ; /* 0x0000000100057819 */
/* 0x004fca00000006ff */
/*0070*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
// CUDA to assign a value to each element of the array of integers A[256] using 256 threads.
// Each A[i] is assigned with the value of 2*i, for i = 0 to 255.
#define T 256 // As Threads
// #define n 256
__global__ void vecMultiply(int *A)
{
int i = threadIdx.x;
A[i] = A[i] * 2;
}
int main (int argc, char *argv[])
{
int i;
int size = T*sizeof(int);
int a[T], *devA;
for (i=0; i< T; i++)
{
a[i] = i + 1;
}
cudaMalloc( (void**)&devA,size);
cudaMemcpy( devA, a, size, cudaMemcpyHostToDevice);
vecMultiply<<<1, T>>>(devA);
printf("Before\n");
for (i=0; i< T; i++)
{
printf("%d ", a[i]);
}
printf("\n");
cudaMemcpy(a, devA, size, cudaMemcpyDeviceToHost);
cudaFree(devA);
printf("After\n");
for (i=0; i < T; i++) {
printf("%d ",a[i]);
}
printf("\n");
} | .file "tmpxft_000ab924_00000000-6_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z11vecMultiplyPiPi
.type _Z31__device_stub__Z11vecMultiplyPiPi, @function
_Z31__device_stub__Z11vecMultiplyPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11vecMultiplyPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z11vecMultiplyPiPi, .-_Z31__device_stub__Z11vecMultiplyPiPi
.globl _Z11vecMultiplyPi
.type _Z11vecMultiplyPi, @function
_Z11vecMultiplyPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z11vecMultiplyPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11vecMultiplyPi, .-_Z11vecMultiplyPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Before\n"
.LC1:
.string "%d "
.LC2:
.string "\n"
.LC3:
.string "After\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $1080, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1064(%rsp)
xorl %eax, %eax
movl $1, %eax
.L12:
movl %eax, 28(%rsp,%rax,4)
addq $1, %rax
cmpq $257, %rax
jne .L12
movq %rsp, %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $1024, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L13:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rbx
leaq 1056(%rsp), %r12
movq %rbx, %rbp
leaq .LC1(%rip), %r13
.L14:
movl 0(%rbp), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbp
cmpq %r12, %rbp
jne .L14
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rdi
movl $2, %ecx
movl $1024, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rbp
.L15:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L15
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1064(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $1080, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq (%rsp), %rdi
call _Z31__device_stub__Z11vecMultiplyPiPi
jmp .L13
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z11vecMultiplyPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z11vecMultiplyPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
// CUDA to assign a value to each element of the array of integers A[256] using 256 threads.
// Each A[i] is assigned with the value of 2*i, for i = 0 to 255.
#define T 256 // As Threads
// #define n 256
__global__ void vecMultiply(int *A)
{
int i = threadIdx.x;
A[i] = A[i] * 2;
}
int main (int argc, char *argv[])
{
int i;
int size = T*sizeof(int);
int a[T], *devA;
for (i=0; i< T; i++)
{
a[i] = i + 1;
}
cudaMalloc( (void**)&devA,size);
cudaMemcpy( devA, a, size, cudaMemcpyHostToDevice);
vecMultiply<<<1, T>>>(devA);
printf("Before\n");
for (i=0; i< T; i++)
{
printf("%d ", a[i]);
}
printf("\n");
cudaMemcpy(a, devA, size, cudaMemcpyDeviceToHost);
cudaFree(devA);
printf("After\n");
for (i=0; i < T; i++) {
printf("%d ",a[i]);
}
printf("\n");
} | #include <hip/hip_runtime.h>
#include <stdio.h>
// CUDA to assign a value to each element of the array of integers A[256] using 256 threads.
// Each A[i] is assigned with the value of 2*i, for i = 0 to 255.
#define T 256 // As Threads
// #define n 256
__global__ void vecMultiply(int *A)
{
int i = threadIdx.x;
A[i] = A[i] * 2;
}
int main (int argc, char *argv[])
{
int i;
int size = T*sizeof(int);
int a[T], *devA;
for (i=0; i< T; i++)
{
a[i] = i + 1;
}
hipMalloc( (void**)&devA,size);
hipMemcpy( devA, a, size, hipMemcpyHostToDevice);
vecMultiply<<<1, T>>>(devA);
printf("Before\n");
for (i=0; i< T; i++)
{
printf("%d ", a[i]);
}
printf("\n");
hipMemcpy(a, devA, size, hipMemcpyDeviceToHost);
hipFree(devA);
printf("After\n");
for (i=0; i < T; i++) {
printf("%d ",a[i]);
}
printf("\n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
// CUDA to assign a value to each element of the array of integers A[256] using 256 threads.
// Each A[i] is assigned with the value of 2*i, for i = 0 to 255.
#define T 256 // As Threads
// #define n 256
__global__ void vecMultiply(int *A)
{
int i = threadIdx.x;
A[i] = A[i] * 2;
}
int main (int argc, char *argv[])
{
int i;
int size = T*sizeof(int);
int a[T], *devA;
for (i=0; i< T; i++)
{
a[i] = i + 1;
}
hipMalloc( (void**)&devA,size);
hipMemcpy( devA, a, size, hipMemcpyHostToDevice);
vecMultiply<<<1, T>>>(devA);
printf("Before\n");
for (i=0; i< T; i++)
{
printf("%d ", a[i]);
}
printf("\n");
hipMemcpy(a, devA, size, hipMemcpyDeviceToHost);
hipFree(devA);
printf("After\n");
for (i=0; i < T; i++) {
printf("%d ",a[i]);
}
printf("\n");
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11vecMultiplyPi
.globl _Z11vecMultiplyPi
.p2align 8
.type _Z11vecMultiplyPi,@function
_Z11vecMultiplyPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v1, 1, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11vecMultiplyPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11vecMultiplyPi, .Lfunc_end0-_Z11vecMultiplyPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11vecMultiplyPi
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z11vecMultiplyPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
// CUDA to assign a value to each element of the array of integers A[256] using 256 threads.
// Each A[i] is assigned with the value of 2*i, for i = 0 to 255.
#define T 256 // As Threads
// #define n 256
__global__ void vecMultiply(int *A)
{
int i = threadIdx.x;
A[i] = A[i] * 2;
}
int main (int argc, char *argv[])
{
int i;
int size = T*sizeof(int);
int a[T], *devA;
for (i=0; i< T; i++)
{
a[i] = i + 1;
}
hipMalloc( (void**)&devA,size);
hipMemcpy( devA, a, size, hipMemcpyHostToDevice);
vecMultiply<<<1, T>>>(devA);
printf("Before\n");
for (i=0; i< T; i++)
{
printf("%d ", a[i]);
}
printf("\n");
hipMemcpy(a, devA, size, hipMemcpyDeviceToHost);
hipFree(devA);
printf("After\n");
for (i=0; i < T; i++) {
printf("%d ",a[i]);
}
printf("\n");
} | .text
.file "cuda.hip"
.globl _Z26__device_stub__vecMultiplyPi # -- Begin function _Z26__device_stub__vecMultiplyPi
.p2align 4, 0x90
.type _Z26__device_stub__vecMultiplyPi,@function
_Z26__device_stub__vecMultiplyPi: # @_Z26__device_stub__vecMultiplyPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z11vecMultiplyPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z26__device_stub__vecMultiplyPi, .Lfunc_end0-_Z26__device_stub__vecMultiplyPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1104, %rsp # imm = 0x450
.cfi_def_cfa_offset 1120
.cfi_offset %rbx, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
movl %ecx, 80(%rsp,%rax,4)
movq %rcx, %rax
cmpq $256, %rcx # imm = 0x100
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z11vecMultiplyPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $256, %rbx # imm = 0x100
jne .LBB1_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
movq 8(%rsp), %rsi
leaq 80(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movl $.Lstr.1, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $256, %rbx # imm = 0x100
jne .LBB1_7
# %bb.8:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $1104, %rsp # imm = 0x450
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11vecMultiplyPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11vecMultiplyPi,@object # @_Z11vecMultiplyPi
.section .rodata,"a",@progbits
.globl _Z11vecMultiplyPi
.p2align 3, 0x0
_Z11vecMultiplyPi:
.quad _Z26__device_stub__vecMultiplyPi
.size _Z11vecMultiplyPi, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11vecMultiplyPi"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Before"
.size .Lstr, 7
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "After"
.size .Lstr.1, 6
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__vecMultiplyPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11vecMultiplyPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11vecMultiplyPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fca00078e0203 */
/*0050*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0060*/ SHF.L.U32 R5, R0, 0x1, RZ ; /* 0x0000000100057819 */
/* 0x004fca00000006ff */
/*0070*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11vecMultiplyPi
.globl _Z11vecMultiplyPi
.p2align 8
.type _Z11vecMultiplyPi,@function
_Z11vecMultiplyPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v1, 1, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11vecMultiplyPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11vecMultiplyPi, .Lfunc_end0-_Z11vecMultiplyPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11vecMultiplyPi
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z11vecMultiplyPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ab924_00000000-6_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z11vecMultiplyPiPi
.type _Z31__device_stub__Z11vecMultiplyPiPi, @function
_Z31__device_stub__Z11vecMultiplyPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11vecMultiplyPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z11vecMultiplyPiPi, .-_Z31__device_stub__Z11vecMultiplyPiPi
.globl _Z11vecMultiplyPi
.type _Z11vecMultiplyPi, @function
_Z11vecMultiplyPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z11vecMultiplyPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11vecMultiplyPi, .-_Z11vecMultiplyPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Before\n"
.LC1:
.string "%d "
.LC2:
.string "\n"
.LC3:
.string "After\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $1080, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1064(%rsp)
xorl %eax, %eax
movl $1, %eax
.L12:
movl %eax, 28(%rsp,%rax,4)
addq $1, %rax
cmpq $257, %rax
jne .L12
movq %rsp, %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $1024, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L13:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rbx
leaq 1056(%rsp), %r12
movq %rbx, %rbp
leaq .LC1(%rip), %r13
.L14:
movl 0(%rbp), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbp
cmpq %r12, %rbp
jne .L14
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rdi
movl $2, %ecx
movl $1024, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rbp
.L15:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L15
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1064(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $1080, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq (%rsp), %rdi
call _Z31__device_stub__Z11vecMultiplyPiPi
jmp .L13
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z11vecMultiplyPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z11vecMultiplyPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda.hip"
.globl _Z26__device_stub__vecMultiplyPi # -- Begin function _Z26__device_stub__vecMultiplyPi
.p2align 4, 0x90
.type _Z26__device_stub__vecMultiplyPi,@function
_Z26__device_stub__vecMultiplyPi: # @_Z26__device_stub__vecMultiplyPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z11vecMultiplyPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z26__device_stub__vecMultiplyPi, .Lfunc_end0-_Z26__device_stub__vecMultiplyPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1104, %rsp # imm = 0x450
.cfi_def_cfa_offset 1120
.cfi_offset %rbx, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
movl %ecx, 80(%rsp,%rax,4)
movq %rcx, %rax
cmpq $256, %rcx # imm = 0x100
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z11vecMultiplyPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $256, %rbx # imm = 0x100
jne .LBB1_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
movq 8(%rsp), %rsi
leaq 80(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movl $.Lstr.1, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $256, %rbx # imm = 0x100
jne .LBB1_7
# %bb.8:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $1104, %rsp # imm = 0x450
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11vecMultiplyPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11vecMultiplyPi,@object # @_Z11vecMultiplyPi
.section .rodata,"a",@progbits
.globl _Z11vecMultiplyPi
.p2align 3, 0x0
_Z11vecMultiplyPi:
.quad _Z26__device_stub__vecMultiplyPi
.size _Z11vecMultiplyPi, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11vecMultiplyPi"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Before"
.size .Lstr, 7
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "After"
.size .Lstr.1, 6
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__vecMultiplyPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11vecMultiplyPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
extern "C"
__global__ void wavee(int* tab, unsigned int rowSize, unsigned int centerX, unsigned int centerY, float A, float lambda, float time, float fi, unsigned int N)
{
int index = threadIdx.x + blockDim.x * blockIdx.x;
int w = int(index/rowSize);
int h = index%rowSize;
if ( w*rowSize+h < N ) {
float dx = 0;
if(centerX > w) {
dx = centerX - w;
} else {
dx = w - centerX;
}
float dy = 0;
if(centerY > h) {
dy = centerY - h;
} else {
dy = h - centerY;
}
float distance = pow(dx,2) + pow(dy,2);
distance = sqrt(distance);
float pi = 3.1415f;
float v = 1.0f;
float T = lambda/v;
float ww = 2.0f*pi/T;
float k = 2.0f*pi/lambda;
float f = A * sin( ww*time - k*distance + fi );
float res = f * 127 + 127;
tab[index] = int(res);
}
} | .file "tmpxft_0004ad8b_00000000-6_wavee.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z5waveePijjjffffjPijjjffffj
.type _Z32__device_stub__Z5waveePijjjffffjPijjjffffj, @function
_Z32__device_stub__Z5waveePijjjffffjPijjjffffj:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movl %ecx, 28(%rsp)
movss %xmm0, 24(%rsp)
movss %xmm1, 20(%rsp)
movss %xmm2, 16(%rsp)
movss %xmm3, 12(%rsp)
movl %r8d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq wavee(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z5waveePijjjffffjPijjjffffj, .-_Z32__device_stub__Z5waveePijjjffffjPijjjffffj
.globl wavee
.type wavee, @function
wavee:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z5waveePijjjffffjPijjjffffj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size wavee, .-wavee
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "wavee"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq wavee(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
extern "C"
__global__ void wavee(int* tab, unsigned int rowSize, unsigned int centerX, unsigned int centerY, float A, float lambda, float time, float fi, unsigned int N)
{
int index = threadIdx.x + blockDim.x * blockIdx.x;
int w = int(index/rowSize);
int h = index%rowSize;
if ( w*rowSize+h < N ) {
float dx = 0;
if(centerX > w) {
dx = centerX - w;
} else {
dx = w - centerX;
}
float dy = 0;
if(centerY > h) {
dy = centerY - h;
} else {
dy = h - centerY;
}
float distance = pow(dx,2) + pow(dy,2);
distance = sqrt(distance);
float pi = 3.1415f;
float v = 1.0f;
float T = lambda/v;
float ww = 2.0f*pi/T;
float k = 2.0f*pi/lambda;
float f = A * sin( ww*time - k*distance + fi );
float res = f * 127 + 127;
tab[index] = int(res);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C"
__global__ void wavee(int* tab, unsigned int rowSize, unsigned int centerX, unsigned int centerY, float A, float lambda, float time, float fi, unsigned int N)
{
int index = threadIdx.x + blockDim.x * blockIdx.x;
int w = int(index/rowSize);
int h = index%rowSize;
if ( w*rowSize+h < N ) {
float dx = 0;
if(centerX > w) {
dx = centerX - w;
} else {
dx = w - centerX;
}
float dy = 0;
if(centerY > h) {
dy = centerY - h;
} else {
dy = h - centerY;
}
float distance = pow(dx,2) + pow(dy,2);
distance = sqrt(distance);
float pi = 3.1415f;
float v = 1.0f;
float T = lambda/v;
float ww = 2.0f*pi/T;
float k = 2.0f*pi/lambda;
float f = A * sin( ww*time - k*distance + fi );
float res = f * 127 + 127;
tab[index] = int(res);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C"
__global__ void wavee(int* tab, unsigned int rowSize, unsigned int centerX, unsigned int centerY, float A, float lambda, float time, float fi, unsigned int N)
{
int index = threadIdx.x + blockDim.x * blockIdx.x;
int w = int(index/rowSize);
int h = index%rowSize;
if ( w*rowSize+h < N ) {
float dx = 0;
if(centerX > w) {
dx = centerX - w;
} else {
dx = w - centerX;
}
float dy = 0;
if(centerY > h) {
dy = centerY - h;
} else {
dy = h - centerY;
}
float distance = pow(dx,2) + pow(dy,2);
distance = sqrt(distance);
float pi = 3.1415f;
float v = 1.0f;
float T = lambda/v;
float ww = 2.0f*pi/T;
float k = 2.0f*pi/lambda;
float f = A * sin( ww*time - k*distance + fi );
float res = f * 127 + 127;
tab[index] = int(res);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected wavee
.globl wavee
.p2align 8
.type wavee,@function
wavee:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x8
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s4
s_sub_i32 s5, 0, s4
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, s5, v3
s_mov_b32 s5, exec_lo
v_mul_hi_u32 v4, v3, v1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v4
v_mul_hi_u32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v0, s4
v_sub_nc_u32_e32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v3, s4, v2
v_cmp_le_u32_e64 s2, s4, v2
v_cndmask_b32_e64 v2, v2, v3, s2
s_delay_alu instid0(VALU_DEP_1)
v_cmp_le_u32_e32 vcc_lo, s4, v2
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_6
v_add_nc_u32_e32 v2, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v0, v0, v2, s2
s_load_b64 s[2:3], s[0:1], 0xc
v_add_nc_u32_e32 v2, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
v_mul_lo_u32 v2, v0, s4
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x18
s_load_b32 s6, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_sub_nc_u32_e32 v3, s2, v0
v_subrev_nc_u32_e32 v4, s2, v0
v_cmp_gt_u32_e32 vcc_lo, s2, v0
v_sub_nc_u32_e32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v0, v4, v3, vcc_lo
v_sub_nc_u32_e32 v3, s3, v2
v_subrev_nc_u32_e32 v4, s3, v2
v_cmp_gt_u32_e32 vcc_lo, s3, v2
s_mov_b32 s3, 0x3e76c4e1
v_cvt_f32_u32_e32 v5, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v4, v3, vcc_lo
v_frexp_mant_f32_e32 v3, v5
v_frexp_exp_i32_f32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f32_u32_e32 v4, v2
v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_frexp_mant_f32_e32 v7, v4
v_frexp_exp_i32_f32_e32 v4, v4
v_cndmask_b32_e64 v6, 0, 1, vcc_lo
v_subrev_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
v_cmp_gt_f32_e64 s2, 0x3f2aaaab, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ldexp_f32 v3, v3, v6
v_cvt_f32_i32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v6, 0, 1, s2
v_subrev_co_ci_u32_e64 v4, vcc_lo, 0, v4, s2
v_add_f32_e32 v10, -1.0, v3
v_add_f32_e32 v8, 1.0, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ldexp_f32 v6, v7, v6
v_cvt_f32_i32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v7, v8
v_add_f32_e32 v9, 1.0, v6
v_add_f32_e32 v13, -1.0, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v11, v9
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v12, v10, v7
v_mul_f32_e32 v15, v8, v12
v_add_f32_e32 v14, -1.0, v8
v_mul_f32_e32 v16, v13, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v8, v12, v8, -v15
v_dual_sub_f32 v3, v3, v14 :: v_dual_add_f32 v14, -1.0, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mul_f32 v17, v9, v16 :: v_dual_fmac_f32 v8, v12, v3
v_sub_f32_e32 v3, v6, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, v16, v9, -v17
v_dual_add_f32 v9, v15, v8 :: v_dual_fmac_f32 v6, v16, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v3, v10, v9
v_sub_f32_e32 v15, v9, v15
v_sub_f32_e32 v10, v10, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v8, v15, v8 :: v_dual_sub_f32 v9, v10, v9
v_add_f32_e32 v8, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v3, v3, v8 :: v_dual_add_f32 v14, v17, v6
v_dual_mul_f32 v3, v7, v3 :: v_dual_sub_f32 v18, v13, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, v12, v3
v_dual_sub_f32 v13, v13, v18 :: v_dual_sub_f32 v8, v7, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v10, v14, v17 :: v_dual_sub_f32 v9, v13, v14
v_dual_sub_f32 v3, v3, v8 :: v_dual_sub_f32 v6, v10, v6
v_mul_f32_e32 v10, v7, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v12, v3, v3
v_add_f32_e32 v6, v6, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v18, v6
v_mul_f32_e32 v6, v11, v6
v_fma_f32 v11, v7, v7, -v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v9, v16, v6
v_fmac_f32_e32 v11, v7, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v9, v16
v_dual_mul_f32 v13, v9, v9 :: v_dual_add_f32 v14, v10, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v6, v6, v8
v_fma_f32 v8, v9, v9, -v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v10, v14, v10
v_add_f32_e32 v12, v6, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v10, v11, v10
v_fmac_f32_e32 v8, v9, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmaak_f32 v12, s3, v14, 0x3e91f4c4 :: v_dual_add_f32 v15, v13, v8
v_dual_fmaak_f32 v12, v14, v12, 0x3ecccdef :: v_dual_sub_f32 v13, v15, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v17, v14, v12
v_dual_mul_f32 v23, v9, v15 :: v_dual_sub_f32 v8, v8, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f32 v11, v14, v12, -v17
v_fmaak_f32 v16, s3, v15, 0x3e91f4c4
s_mov_b32 s3, 0x40c90e56
v_fmac_f32_e32 v11, v10, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmaak_f32 v16, v15, v16, 0x3ecccdef :: v_dual_add_f32 v13, v17, v11
v_dual_mul_f32 v18, v15, v16 :: v_dual_add_f32 v19, 0x3f2aaaaa, v13
v_sub_f32_e32 v17, v13, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v12, v15, v16, -v18
v_sub_f32_e32 v11, v11, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_add_f32 v17, 0xbf2aaaaa, v19 :: v_dual_fmac_f32 v12, v8, v16
v_add_f32_e32 v11, 0x31739010, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v13, v13, v17
v_dual_add_f32 v11, v11, v13 :: v_dual_add_f32 v20, v18, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v22, 0x3f2aaaaa, v20
v_sub_f32_e32 v18, v20, v18
v_add_f32_e32 v17, 0xbf2aaaaa, v22
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v16, v7, v14 :: v_dual_sub_f32 v13, v20, v17
v_fma_f32 v21, v14, v7, -v16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v21, v14, v3
v_ldexp_f32 v3, v3, 1
v_fmac_f32_e32 v21, v10, v7
v_ldexp_f32 v7, v7, 1
v_sub_f32_e32 v12, v12, v18
v_fma_f32 v18, v15, v9, -v23
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v12, 0x31739010, v12
v_fmac_f32_e32 v18, v15, v6
v_ldexp_f32 v6, v6, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v12, v12, v13
v_add_f32_e32 v14, v22, v12
v_add_f32_e32 v10, v19, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_sub_f32 v13, v19, v10 :: v_dual_fmac_f32 v18, v8, v9
v_add_f32_e32 v8, v16, v21
v_ldexp_f32 v9, v9, 1
v_add_f32_e32 v11, v11, v13
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_f32_e32 v15, v23, v18
v_mul_f32_e32 v17, v8, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_sub_f32 v16, v8, v16 :: v_dual_mul_f32 v19, v15, v14
v_sub_f32_e32 v13, v22, v14
v_fma_f32 v20, v8, v10, -v17
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_sub_f32 v16, v21, v16 :: v_dual_sub_f32 v21, v15, v23
v_add_f32_e32 v12, v12, v13
v_fma_f32 v13, v15, v14, -v19
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_dual_fmac_f32 v20, v8, v11 :: v_dual_fmac_f32 v13, v15, v12
v_sub_f32_e32 v8, v18, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v13, v8, v14
v_fmac_f32_e32 v20, v16, v10
v_mul_f32_e32 v10, 0x3f317218, v5
v_mul_f32_e32 v14, 0x3f317218, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v11, v5, 0x3f317218, -v10
v_fmac_f32_e32 v11, 0xb102e308, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v5, v10, v11 :: v_dual_add_f32 v8, v17, v20
v_dual_sub_f32 v10, v5, v10 :: v_dual_add_f32 v15, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v16, v8, v17 :: v_dual_sub_f32 v7, v15, v7
v_sub_f32_e32 v16, v20, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_sub_f32_e32 v7, v8, v7
v_fma_f32 v8, v4, 0x3f317218, -v14
v_add_f32_e32 v3, v3, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmac_f32 v8, 0xb102e308, v4 :: v_dual_add_f32 v3, v3, v7
v_dual_add_f32 v7, v14, v8 :: v_dual_add_f32 v12, v19, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v17, v9, v12 :: v_dual_sub_f32 v18, v12, v19
v_sub_f32_e32 v9, v17, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v13, v13, v18
v_sub_f32_e32 v9, v12, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v6, v13
v_add_f32_e32 v4, v6, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v6, v15, v3 :: v_dual_add_f32 v9, v17, v4
v_add_f32_e32 v13, v7, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_sub_f32 v10, v11, v10 :: v_dual_sub_f32 v11, v6, v15
v_dual_sub_f32 v17, v9, v17 :: v_dual_sub_f32 v14, v7, v14
v_sub_f32_e32 v15, v13, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_sub_f32 v3, v3, v11 :: v_dual_add_f32 v12, v5, v6
v_sub_f32_e32 v11, v13, v15
v_sub_f32_e32 v9, v9, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_f32_e32 v7, v7, v11
v_dual_add_f32 v11, v10, v3 :: v_dual_sub_f32 v16, v12, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_sub_f32 v8, v8, v14 :: v_dual_add_f32 v7, v9, v7
v_dual_sub_f32 v9, v11, v10 :: v_dual_sub_f32 v14, v12, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_sub_f32 v6, v6, v16 :: v_dual_sub_f32 v3, v3, v9
v_sub_f32_e32 v5, v5, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v6, v5
v_add_f32_e32 v5, v11, v5
v_sub_f32_e32 v11, v11, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v15, v12, v5
v_sub_f32_e32 v4, v4, v17
v_add_f32_e32 v6, v8, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, v6, v7
v_add_f32_e32 v9, v13, v7
v_dual_sub_f32 v10, v10, v11 :: v_dual_sub_f32 v11, v15, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v3, v3, v10 :: v_dual_sub_f32 v14, v6, v8
v_dual_sub_f32 v5, v5, v11 :: v_dual_sub_f32 v6, v6, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v3, v3, v5 :: v_dual_sub_f32 v4, v4, v14
v_dual_add_f32 v5, v15, v3 :: v_dual_sub_f32 v6, v8, v6
v_sub_f32_e32 v8, v9, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v4, v4, v6
v_dual_sub_f32 v6, v7, v8 :: v_dual_sub_f32 v7, v5, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v4, v4, v6 :: v_dual_sub_f32 v3, v3, v7
v_add_f32_e32 v6, v9, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_add_f32 v8, v5, v5 :: v_dual_add_f32 v7, v6, v6
v_sub_f32_e32 v9, v6, v9
v_mul_f32_e32 v11, 0, v6
v_cmp_class_f32_e64 vcc_lo, v8, 0x204
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_sub_f32_e32 v4, v4, v9
v_mul_f32_e32 v10, 0, v5
v_fma_f32 v5, v5, 2.0, -v8
v_dual_fmac_f32 v11, 2.0, v4 :: v_dual_fmac_f32 v10, 2.0, v3
v_fma_f32 v3, v6, 2.0, -v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v4, v5, v10 :: v_dual_add_f32 v3, v3, v11
v_dual_add_f32 v5, v8, v4 :: v_dual_add_f32 v6, v7, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v9, v5, v8, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v7, 0x204
v_dual_sub_f32 v5, v5, v8 :: v_dual_cndmask_b32 v10, v6, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v9
v_cndmask_b32_e64 v11, 0, 0x37000000, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v13, v9, v11
v_mul_f32_e32 v15, 0x3fb8aa3b, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_rndne_f32_e32 v18, v15
v_fma_f32 v17, v13, 0x3fb8aa3b, -v15
v_sub_f32_e32 v15, v15, v18
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v17, 0x32a5705f, v13
v_sub_f32_e32 v4, v4, v5
v_cndmask_b32_e64 v12, 0, 0x37000000, vcc_lo
v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v9|
v_sub_f32_e32 v14, v10, v12
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v10|
v_mul_f32_e32 v16, 0x3fb8aa3b, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v19, v14, 0x3fb8aa3b, -v16
v_rndne_f32_e32 v20, v16
v_dual_fmac_f32 v19, 0x32a5705f, v14 :: v_dual_sub_f32 v6, v6, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_sub_f32_e32 v16, v16, v20
v_cvt_i32_f32_e32 v7, v18
v_cvt_i32_f32_e32 v9, v20
v_sub_f32_e32 v3, v3, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_add_f32 v8, v15, v17 :: v_dual_add_f32 v15, v16, v19
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_exp_f32_e32 v5, v8
v_exp_f32_e32 v8, v15
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_f32_e32 v3, v12, v3
s_waitcnt_depctr 0xfff
v_ldexp_f32 v5, v5, v7
v_ldexp_f32 v6, v8, v9
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v6, 0, v6, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v13
v_dual_add_f32 v4, v11, v4 :: v_dual_cndmask_b32 v5, 0x7f800000, v5
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f32 v4, v5, v4, v5
v_cndmask_b32_e32 v6, 0x7f800000, v6, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v5
v_fma_f32 v3, v6, v3, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v6
v_cndmask_b32_e32 v3, v3, v6, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v0, 0, |v4|, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v2
v_cndmask_b32_e64 v2, 0, |v3|, vcc_lo
v_div_scale_f32 v6, vcc_lo, s3, s4, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v0, v2
v_div_scale_f32 v2, null, s4, s4, 0x40c90e56
v_rcp_f32_e32 v4, v2
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v2, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v4
v_mul_f32_e32 v7, v6, v4
v_mul_f32_e32 v3, 0x4f800000, v0
v_cmp_gt_f32_e64 s2, 0xf800000, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v10, -v2, v7, v6
v_cndmask_b32_e64 v0, v0, v3, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v7, v10, v4
v_sqrt_f32_e32 v3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v2, -v2, v7, v6
v_div_fmas_f32 v2, v2, v4, v7
v_cmp_class_f32_e64 vcc_lo, v0, 0x260
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v5, -1, v3
v_add_nc_u32_e32 v8, 1, v3
v_div_fixup_f32 v2, v2, s4, 0x40c90e56
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v9, -v5, v3, v0
v_fma_f32 v11, -v8, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s3, 0, v9
v_cndmask_b32_e64 v3, v3, v5, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s3, 0, v11
v_cndmask_b32_e64 v3, v3, v8, s3
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, 0x37800000, v3
v_cndmask_b32_e64 v3, v3, v5, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v3, v0, vcc_lo
v_mul_f32_e32 v0, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v0, v2, s5, -v0
v_add_f32_e32 v0, s6, v0
s_delay_alu instid0(VALU_DEP_1)
v_and_b32_e32 v2, 0x7fffffff, v0
v_cmpx_ngt_f32_e64 0x48000000, |v0|
s_xor_b32 s4, exec_lo, s3
s_cbranch_execz .LBB0_3
s_mov_b32 s2, 0x7fffff
v_mov_b32_e32 v5, 0
v_and_or_b32 v13, v2, s2, 0x800000
v_lshrrev_b32_e32 v10, 23, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, v13, 0xfe5163ab, 0
v_add_nc_u32_e32 v11, 0xffffff88, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_u32_e32 vcc_lo, 63, v11
v_mad_u64_u32 v[6:7], null, v13, 0x3c439041, v[4:5]
v_cndmask_b32_e64 v12, 0, 0xffffffc0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v4, v7
v_add_nc_u32_e32 v12, v12, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[7:8], null, v13, 0xdb629599, v[4:5]
v_cmp_lt_u32_e64 s2, 31, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v14, 0, 0xffffffe0, s2
v_dual_mov_b32 v4, v8 :: v_dual_cndmask_b32 v3, v7, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v14, v14, v12
v_mad_u64_u32 v[8:9], null, v13, 0xf534ddc0, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s3, 31, v14
v_mov_b32_e32 v4, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v6, v8, v6, vcc_lo
v_mad_u64_u32 v[9:10], null, v13, 0xfc2757d1, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v6, v3, s2
v_mov_b32_e32 v4, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[10:11], null, v13, 0x4e441529, v[4:5]
v_mov_b32_e32 v4, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[11:12], null, v13, 0xa2f9836e, v[4:5]
v_cndmask_b32_e64 v4, 0, 0xffffffe0, s3
v_dual_cndmask_b32 v5, v10, v8 :: v_dual_add_nc_u32 v4, v4, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v11, v11, v9 :: v_dual_cndmask_b32 v10, v12, v10
v_cndmask_b32_e32 v9, v9, v7, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v8, v11, v5, s2
v_cndmask_b32_e64 v10, v10, v11, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v5, v5, v9, s2
v_sub_nc_u32_e32 v11, 32, v4
v_cndmask_b32_e64 v9, v9, v6, s2
v_cndmask_b32_e64 v10, v10, v8, s3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v8, v8, v5, s3
v_cndmask_b32_e64 v5, v5, v9, s3
v_cndmask_b32_e64 v3, v9, v3, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v12, v10, v8, v11
v_alignbit_b32 v7, v8, v5, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v4, v12, v10, vcc_lo
v_alignbit_b32 v10, v5, v3, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v6, v7, v8, vcc_lo
v_bfe_u32 v7, v4, 29, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v5, v10, v5, vcc_lo
v_alignbit_b32 v8, v4, v6, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v9, 0, v7
v_alignbit_b32 v6, v6, v5, 30
v_alignbit_b32 v3, v5, v3, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v8, v8, v9
v_xor_b32_e32 v5, v6, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v3, v3, v9
v_clz_i32_u32_e32 v10, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v10, 32, v10
v_sub_nc_u32_e32 v6, 31, v10
v_lshlrev_b32_e32 v12, 23, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_alignbit_b32 v8, v8, v5, v6
v_alignbit_b32 v3, v5, v3, v6
v_lshrrev_b32_e32 v6, 29, v4
v_alignbit_b32 v5, v8, v3, 9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v6, 31, v6
v_lshrrev_b32_e32 v8, 9, v8
v_clz_i32_u32_e32 v9, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v11, 0.5, v6
v_min_u32_e32 v9, 32, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v11, v11, v12
v_sub_nc_u32_e32 v13, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v3, v5, v3, v13
v_or_b32_e32 v5, v8, v11
v_add_lshl_u32 v8, v9, v10, 23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v3, 9, v3
v_mul_f32_e32 v9, 0x3fc90fda, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v3, v8
v_fma_f32 v8, v5, 0x3fc90fda, -v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, 0x33000000, v3
v_fmamk_f32 v5, v5, 0x33a22168, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v3, v3, v6
v_fmac_f32_e32 v5, 0x3fc90fda, v3
v_lshrrev_b32_e32 v4, 30, v4
s_delay_alu instid0(VALU_DEP_1)
v_dual_add_f32 v3, v9, v5 :: v_dual_add_nc_u32 v4, v7, v4
.LBB0_3:
s_and_not1_saveexec_b32 s2, s4
v_mul_f32_e64 v3, 0x3f22f983, |v0|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v4, v3
v_fma_f32 v3, v4, 0xbfc90fda, |v0|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v3, v4, 0xb3a22168, v3
v_fmamk_f32 v3, v4, 0xa7c234c4, v3
v_cvt_i32_f32_e32 v4, v4
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_dual_mul_f32 v5, v3, v3 :: v_dual_and_b32 v8, 1, v4
s_mov_b32 s2, 0xb94c1982
s_mov_b32 s3, 0x37d75334
v_xor_b32_e32 v2, v2, v0
v_fmaak_f32 v6, s2, v5, 0x3c0881c4
s_load_b32 s2, s[0:1], 0x14
v_cmp_eq_u32_e32 vcc_lo, 0, v8
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v4, 30, v4
v_fmaak_f32 v6, v5, v6, 0xbe2aaa9d
v_fmaak_f32 v7, s3, v5, 0xbab64f3b
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_and_b32_e32 v4, 0x80000000, v4
v_mul_f32_e32 v6, v5, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmaak_f32 v7, v5, v7, 0x3d2aabf7
v_fmac_f32_e32 v3, v3, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v7, v5, v7, 0xbf000004
v_fma_f32 v5, v5, v7, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v5, v3, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v0, 0x1f8
v_xor3_b32 v2, v2, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
v_mul_f32_e32 v0, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmaak_f32 v3, 0x42fe0000, v0, 0x42fe0000
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_i32_f32_e32 v2, v3
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel wavee
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 24
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size wavee, .Lfunc_end0-wavee
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: wavee
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: wavee.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 24
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C"
__global__ void wavee(int* tab, unsigned int rowSize, unsigned int centerX, unsigned int centerY, float A, float lambda, float time, float fi, unsigned int N)
{
int index = threadIdx.x + blockDim.x * blockIdx.x;
int w = int(index/rowSize);
int h = index%rowSize;
if ( w*rowSize+h < N ) {
float dx = 0;
if(centerX > w) {
dx = centerX - w;
} else {
dx = w - centerX;
}
float dy = 0;
if(centerY > h) {
dy = centerY - h;
} else {
dy = h - centerY;
}
float distance = pow(dx,2) + pow(dy,2);
distance = sqrt(distance);
float pi = 3.1415f;
float v = 1.0f;
float T = lambda/v;
float ww = 2.0f*pi/T;
float k = 2.0f*pi/lambda;
float f = A * sin( ww*time - k*distance + fi );
float res = f * 127 + 127;
tab[index] = int(res);
}
} | .text
.file "wavee.hip"
.globl __device_stub__wavee # -- Begin function __device_stub__wavee
.p2align 4, 0x90
.type __device_stub__wavee,@function
__device_stub__wavee: # @__device_stub__wavee
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movl %ecx, 28(%rsp)
movss %xmm0, 24(%rsp)
movss %xmm1, 20(%rsp)
movss %xmm2, 16(%rsp)
movss %xmm3, 12(%rsp)
movl %r8d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 36(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rax
movq %rax, 112(%rsp)
leaq 28(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $wavee, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size __device_stub__wavee, .Lfunc_end0-__device_stub__wavee
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $wavee, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type wavee,@object # @wavee
.section .rodata,"a",@progbits
.globl wavee
.p2align 3, 0x0
wavee:
.quad __device_stub__wavee
.size wavee, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "wavee"
.size .L__unnamed_1, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__wavee
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym wavee
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004ad8b_00000000-6_wavee.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z5waveePijjjffffjPijjjffffj
.type _Z32__device_stub__Z5waveePijjjffffjPijjjffffj, @function
_Z32__device_stub__Z5waveePijjjffffjPijjjffffj:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movl %ecx, 28(%rsp)
movss %xmm0, 24(%rsp)
movss %xmm1, 20(%rsp)
movss %xmm2, 16(%rsp)
movss %xmm3, 12(%rsp)
movl %r8d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq wavee(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z5waveePijjjffffjPijjjffffj, .-_Z32__device_stub__Z5waveePijjjffffjPijjjffffj
.globl wavee
.type wavee, @function
wavee:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z5waveePijjjffffjPijjjffffj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size wavee, .-wavee
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "wavee"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq wavee(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "wavee.hip"
.globl __device_stub__wavee # -- Begin function __device_stub__wavee
.p2align 4, 0x90
.type __device_stub__wavee,@function
__device_stub__wavee: # @__device_stub__wavee
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movl %ecx, 28(%rsp)
movss %xmm0, 24(%rsp)
movss %xmm1, 20(%rsp)
movss %xmm2, 16(%rsp)
movss %xmm3, 12(%rsp)
movl %r8d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 36(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rax
movq %rax, 112(%rsp)
leaq 28(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $wavee, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size __device_stub__wavee, .Lfunc_end0-__device_stub__wavee
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $wavee, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type wavee,@object # @wavee
.section .rodata,"a",@progbits
.globl wavee
.p2align 3, 0x0
wavee:
.quad __device_stub__wavee
.size wavee, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "wavee"
.size .L__unnamed_1, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__wavee
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym wavee
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <math.h>
typedef unsigned long ulint;
typedef unsigned long long ulint64;
int banyakdata = 256000;
int dimensigrid = 2000;
int dimensiblok = 128;
void modexp(ulint a, ulint b, ulint c, ulint* res) {
ulint64 s = a;
ulint64 ans = 1;
while (b != 0) {
if (b % 2 == 1) {
ans = ans * s % c;
b--;
}
b /= 2;
if (b != 0) {
s = s * s %c;
}
}
*res = ans;
}
void enkripsi(ulint g, ulint k, ulint p, ulint m, ulint y, ulint *res) {
modexp(g, k, p, res);
modexp(y, k, p, res + 1);
*(res + 1) = *(res + 1) * m % p;
}
void dekripsi(ulint a, ulint b, ulint p, ulint e, ulint *res) {
modexp(a, e, p, res);
*res = *res * b % p;
}
void kernelenk(ulint *m, ulint *k, ulint g, ulint p, ulint y, ulint *res) {
for (int i = 0; i < banyakdata; i++)
{
enkripsi(g, k[i], p, m[i], y, res + 2 * i);
}
}
void kerneldek(ulint *c, ulint p, ulint e, ulint *res) {
for (int i = 0; i < banyakdata; i++)
{
dekripsi(c[2 * i], c[2 * i + 1], p, e, res + i);
}
}
void enkripsiCUDA(ulint *m, ulint *k, ulint g, ulint p, ulint y, ulint *res) {
clock_t begin = clock();
kernelenk(m, k, g, p, y, res);
clock_t end = clock();
double time_spent = (double)(end - begin);
printf("Durasi enkripsi = %f milliseconds\n", time_spent / 1000);
}
void dekripsiCUDA(ulint *c, ulint p, ulint e, ulint *res2) {
clock_t begin = clock();
kerneldek(c, p, e, res2);
clock_t end = clock();
double time_spent = (double)(end - begin);
printf("Durasi dekripsi = %f milliseconds\n", time_spent / 1000);
}
void initenkripsi(ulint *m, ulint *k) {
for (int i = 0; i < banyakdata; i++) {
m[i] = rand() % 3999999978;
k[i] = rand() % 3999999978;
}
}
int main() {
ulint *m, *k, *res, *res2, g, p, y, x, e;
m = (ulint*)malloc(banyakdata * sizeof(ulint));
k = (ulint*)malloc(banyakdata * sizeof(ulint));
res = (ulint*)malloc(banyakdata * 2 * sizeof(ulint));
res2 = (ulint*)malloc(banyakdata * sizeof(ulint));
srand(2018);
g = rand() % 3999999978;
p = 3999999979;
x = rand() % 3999999978;
modexp(g, x, p, &y);
initenkripsi(m, k);
// printf("<<<<<<<<<<<<<<Pesan Asli>>>>>>>>>>>>>>>\n");
// for (int i = 0; i < 4; i++) {
// printf("m[%d] = %lu\n", i, m[i]);
// }
// printf("m[...]\n");
// printf("m[%d] = %lu\n", banyakdata - 1, m[banyakdata - 1]);
enkripsiCUDA(m, k, g, p, y, res);
// printf("<<<<<<<<<<<<<<Hasil Enkripsi>>>>>>>>>>>>>>>\n");
// for (int i = 0; i < 4; i++) {
// printf("c[%d] = %lu c[%d] = %lu\n", 2 * i, res[2 * i], 2 * i + 1, res[2 * i + 1]);
// }
// printf("c ...\n");
// printf("c[%d] = %lu c[%d] = %lu\n", banyakdata * 2 - 2, res[banyakdata * 2 - 2], banyakdata * 2 - 1, res[banyakdata * 2 - 1]);
e = p - x - 1;
dekripsiCUDA(res, p, e, res2);
// printf("<<<<<<<<<<<<<<Hasil Dekripsi>>>>>>>>>>>>>>>\n");
// for (int i = 0; i < 4; i++) {
// printf("m[%d] = %lu\n", i, res2[i]);
// }
// printf("m[...]\n");
// printf("m[%d] = %lu\n", banyakdata - 1, res2[banyakdata - 1]);
free(m);
free(k);
free(res);
free(res2);
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <math.h>
typedef unsigned long ulint;
typedef unsigned long long ulint64;
int banyakdata = 256000;
int dimensigrid = 2000;
int dimensiblok = 128;
void modexp(ulint a, ulint b, ulint c, ulint* res) {
ulint64 s = a;
ulint64 ans = 1;
while (b != 0) {
if (b % 2 == 1) {
ans = ans * s % c;
b--;
}
b /= 2;
if (b != 0) {
s = s * s %c;
}
}
*res = ans;
}
void enkripsi(ulint g, ulint k, ulint p, ulint m, ulint y, ulint *res) {
modexp(g, k, p, res);
modexp(y, k, p, res + 1);
*(res + 1) = *(res + 1) * m % p;
}
void dekripsi(ulint a, ulint b, ulint p, ulint e, ulint *res) {
modexp(a, e, p, res);
*res = *res * b % p;
}
void kernelenk(ulint *m, ulint *k, ulint g, ulint p, ulint y, ulint *res) {
for (int i = 0; i < banyakdata; i++)
{
enkripsi(g, k[i], p, m[i], y, res + 2 * i);
}
}
void kerneldek(ulint *c, ulint p, ulint e, ulint *res) {
for (int i = 0; i < banyakdata; i++)
{
dekripsi(c[2 * i], c[2 * i + 1], p, e, res + i);
}
}
void enkripsiCUDA(ulint *m, ulint *k, ulint g, ulint p, ulint y, ulint *res) {
clock_t begin = clock();
kernelenk(m, k, g, p, y, res);
clock_t end = clock();
double time_spent = (double)(end - begin);
printf("Durasi enkripsi = %f milliseconds\n", time_spent / 1000);
}
void dekripsiCUDA(ulint *c, ulint p, ulint e, ulint *res2) {
clock_t begin = clock();
kerneldek(c, p, e, res2);
clock_t end = clock();
double time_spent = (double)(end - begin);
printf("Durasi dekripsi = %f milliseconds\n", time_spent / 1000);
}
void initenkripsi(ulint *m, ulint *k) {
for (int i = 0; i < banyakdata; i++) {
m[i] = rand() % 3999999978;
k[i] = rand() % 3999999978;
}
}
int main() {
ulint *m, *k, *res, *res2, g, p, y, x, e;
m = (ulint*)malloc(banyakdata * sizeof(ulint));
k = (ulint*)malloc(banyakdata * sizeof(ulint));
res = (ulint*)malloc(banyakdata * 2 * sizeof(ulint));
res2 = (ulint*)malloc(banyakdata * sizeof(ulint));
srand(2018);
g = rand() % 3999999978;
p = 3999999979;
x = rand() % 3999999978;
modexp(g, x, p, &y);
initenkripsi(m, k);
// printf("<<<<<<<<<<<<<<Pesan Asli>>>>>>>>>>>>>>>\n");
// for (int i = 0; i < 4; i++) {
// printf("m[%d] = %lu\n", i, m[i]);
// }
// printf("m[...]\n");
// printf("m[%d] = %lu\n", banyakdata - 1, m[banyakdata - 1]);
enkripsiCUDA(m, k, g, p, y, res);
// printf("<<<<<<<<<<<<<<Hasil Enkripsi>>>>>>>>>>>>>>>\n");
// for (int i = 0; i < 4; i++) {
// printf("c[%d] = %lu c[%d] = %lu\n", 2 * i, res[2 * i], 2 * i + 1, res[2 * i + 1]);
// }
// printf("c ...\n");
// printf("c[%d] = %lu c[%d] = %lu\n", banyakdata * 2 - 2, res[banyakdata * 2 - 2], banyakdata * 2 - 1, res[banyakdata * 2 - 1]);
e = p - x - 1;
dekripsiCUDA(res, p, e, res2);
// printf("<<<<<<<<<<<<<<Hasil Dekripsi>>>>>>>>>>>>>>>\n");
// for (int i = 0; i < 4; i++) {
// printf("m[%d] = %lu\n", i, res2[i]);
// }
// printf("m[...]\n");
// printf("m[%d] = %lu\n", banyakdata - 1, res2[banyakdata - 1]);
free(m);
free(k);
free(res);
free(res2);
return 0;
} | .file "tmpxft_001320db_00000000-6_32.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6modexpmmmPm
.type _Z6modexpmmmPm, @function
_Z6modexpmmmPm:
.LFB2057:
.cfi_startproc
endbr64
movq %rdx, %r9
testq %rsi, %rsi
je .L7
movl $1, %r8d
jmp .L6
.L5:
cmpq $1, %rsi
jbe .L4
shrq %rsi
imulq %rdi, %rdi
movq %rdi, %rax
movl $0, %edx
divq %r9
movq %rdx, %rdi
.L6:
testb $1, %sil
je .L5
movq %r8, %rax
imulq %rdi, %rax
movl $0, %edx
divq %r9
movq %rdx, %r8
subq $1, %rsi
jmp .L5
.L7:
movl $1, %r8d
.L4:
movq %r8, (%rcx)
ret
.cfi_endproc
.LFE2057:
.size _Z6modexpmmmPm, .-_Z6modexpmmmPm
.globl _Z8enkripsimmmmmPm
.type _Z8enkripsimmmmmPm, @function
_Z8enkripsimmmmmPm:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rsi, %r13
movq %rdx, %r12
movq %rcx, %rbx
movq %r8, %r14
movq %r9, %rbp
movq %r9, %rcx
call _Z6modexpmmmPm
leaq 8(%rbp), %rcx
movq %r12, %rdx
movq %r13, %rsi
movq %r14, %rdi
call _Z6modexpmmmPm
movq %rbx, %rax
imulq 8(%rbp), %rax
movl $0, %edx
divq %r12
movq %rdx, 8(%rbp)
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z8enkripsimmmmmPm, .-_Z8enkripsimmmmmPm
.globl _Z8dekripsimmmmPm
.type _Z8dekripsimmmmPm, @function
_Z8dekripsimmmmPm:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %rbx
movq %rdx, %r12
movq %rcx, %rsi
movq %r8, %rbp
movq %r8, %rcx
call _Z6modexpmmmPm
movq %rbx, %rax
imulq 0(%rbp), %rax
movl $0, %edx
divq %r12
movq %rdx, 0(%rbp)
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z8dekripsimmmmPm, .-_Z8dekripsimmmmPm
.globl _Z9kernelenkPmS_mmmS_
.type _Z9kernelenkPmS_mmmS_, @function
_Z9kernelenkPmS_mmmS_:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdx, (%rsp)
movl banyakdata(%rip), %eax
testl %eax, %eax
jle .L12
movq %rdi, %r12
movq %rsi, %rbp
movq %rcx, %r14
movq %r8, %r15
movq %r9, %rbx
cltq
salq $4, %rax
leaq (%r9,%rax), %r13
.L14:
movq (%r12), %rcx
movq 0(%rbp), %rsi
movq %rbx, %r9
movq %r15, %r8
movq %r14, %rdx
movq (%rsp), %rdi
call _Z8enkripsimmmmmPm
addq $8, %r12
addq $8, %rbp
addq $16, %rbx
cmpq %r13, %rbx
jne .L14
.L12:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z9kernelenkPmS_mmmS_, .-_Z9kernelenkPmS_mmmS_
.globl _Z9kerneldekPmmmS_
.type _Z9kerneldekPmmmS_, @function
_Z9kerneldekPmmmS_:
.LFB2061:
.cfi_startproc
endbr64
movl banyakdata(%rip), %eax
testl %eax, %eax
jle .L22
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rsi, %r13
movq %rdx, %r14
movq %rdi, %rbx
movq %rcx, %rbp
cltq
salq $4, %rax
leaq (%rdi,%rax), %r12
.L19:
movq 8(%rbx), %rsi
movq (%rbx), %rdi
movq %rbp, %r8
movq %r14, %rcx
movq %r13, %rdx
call _Z8dekripsimmmmPm
addq $16, %rbx
addq $8, %rbp
cmpq %r12, %rbx
jne .L19
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
ret
.cfi_endproc
.LFE2061:
.size _Z9kerneldekPmmmS_, .-_Z9kerneldekPmmmS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Durasi enkripsi = %f milliseconds\n"
.text
.globl _Z12enkripsiCUDAPmS_mmmS_
.type _Z12enkripsiCUDAPmS_mmmS_, @function
_Z12enkripsiCUDAPmS_mmmS_:
.LFB2062:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 8(%rsp)
movq %rsi, %rbp
movq %rdx, %r12
movq %rcx, %r13
movq %r8, %r14
movq %r9, %r15
call clock@PLT
movq %rax, %rbx
movq %r15, %r9
movq %r14, %r8
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call _Z9kernelenkPmS_mmmS_
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z12enkripsiCUDAPmS_mmmS_, .-_Z12enkripsiCUDAPmS_mmmS_
.section .rodata.str1.8
.align 8
.LC2:
.string "Durasi dekripsi = %f milliseconds\n"
.text
.globl _Z12dekripsiCUDAPmmmS_
.type _Z12dekripsiCUDAPmmmS_, @function
_Z12dekripsiCUDAPmmmS_:
.LFB2063:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %rbp
movq %rsi, %r12
movq %rdx, %r13
movq %rcx, %r14
call clock@PLT
movq %rax, %rbx
movq %r14, %rcx
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _Z9kerneldekPmmmS_
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _Z12dekripsiCUDAPmmmS_, .-_Z12dekripsiCUDAPmmmS_
.globl _Z12initenkripsiPmS_
.type _Z12initenkripsiPmS_, @function
_Z12initenkripsiPmS_:
.LFB2064:
.cfi_startproc
endbr64
cmpl $0, banyakdata(%rip)
jle .L34
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r13
movq %rsi, %r14
movl $0, %ebx
movabsq $2475880092188101057, %r12
movl $3999999978, %ebp
.L31:
call rand@PLT
movslq %eax, %rcx
movq %rcx, %rax
imulq %r12
sarq $29, %rdx
movq %rcx, %rax
sarq $63, %rax
subq %rax, %rdx
imulq %rbp, %rdx
subq %rdx, %rcx
movq %rcx, 0(%r13,%rbx,8)
call rand@PLT
movslq %eax, %rcx
movq %rcx, %rax
imulq %r12
sarq $29, %rdx
movq %rcx, %rax
sarq $63, %rax
subq %rax, %rdx
imulq %rbp, %rdx
subq %rdx, %rcx
movq %rcx, (%r14,%rbx,8)
addq $1, %rbx
cmpl %ebx, banyakdata(%rip)
jg .L31
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
ret
.cfi_endproc
.LFE2064:
.size _Z12initenkripsiPmS_, .-_Z12initenkripsiPmS_
.globl main
.type main, @function
main:
.LFB2065:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl banyakdata(%rip), %ebx
movslq %ebx, %rbp
salq $3, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
leal (%rbx,%rbx), %edi
movslq %edi, %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, (%rsp)
movq %rbp, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movl $2018, %edi
call srand@PLT
call rand@PLT
movslq %eax, %rcx
movabsq $2475880092188101057, %rbx
movq %rcx, %rax
imulq %rbx
sarq $29, %rdx
movq %rcx, %rsi
sarq $63, %rsi
subq %rsi, %rdx
movq %rdx, %rbp
movl $3999999978, %r14d
imulq %r14, %rbp
subq %rbp, %rcx
movq %rcx, %rbp
call rand@PLT
movslq %eax, %rcx
movq %rcx, %rax
imulq %rbx
movq %rdx, %rbx
sarq $29, %rbx
movq %rcx, %rsi
sarq $63, %rsi
subq %rsi, %rbx
imulq %r14, %rbx
subq %rbx, %rcx
movq %rcx, %rbx
leaq 16(%rsp), %rcx
movl $3999999979, %r15d
movq %r15, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z6modexpmmmPm
movq %r12, %rsi
movq %r13, %rdi
call _Z12initenkripsiPmS_
movq (%rsp), %r9
movq 16(%rsp), %r8
movq %r15, %rcx
movq %rbp, %rdx
movq %r12, %rsi
movq %r13, %rdi
call _Z12enkripsiCUDAPmS_mmmS_
movq %r14, %rdx
subq %rbx, %rdx
movq 8(%rsp), %r14
movq %r14, %rcx
movq %r15, %rsi
movq (%rsp), %rbx
movq %rbx, %rdi
call _Z12dekripsiCUDAPmmmS_
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L40
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2065:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl dimensiblok
.data
.align 4
.type dimensiblok, @object
.size dimensiblok, 4
dimensiblok:
.long 128
.globl dimensigrid
.align 4
.type dimensigrid, @object
.size dimensigrid, 4
dimensigrid:
.long 2000
.globl banyakdata
.align 4
.type banyakdata, @object
.size banyakdata, 4
banyakdata:
.long 256000
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <math.h>
typedef unsigned long ulint;
typedef unsigned long long ulint64;
int banyakdata = 256000;
int dimensigrid = 2000;
int dimensiblok = 128;
void modexp(ulint a, ulint b, ulint c, ulint* res) {
ulint64 s = a;
ulint64 ans = 1;
while (b != 0) {
if (b % 2 == 1) {
ans = ans * s % c;
b--;
}
b /= 2;
if (b != 0) {
s = s * s %c;
}
}
*res = ans;
}
void enkripsi(ulint g, ulint k, ulint p, ulint m, ulint y, ulint *res) {
modexp(g, k, p, res);
modexp(y, k, p, res + 1);
*(res + 1) = *(res + 1) * m % p;
}
void dekripsi(ulint a, ulint b, ulint p, ulint e, ulint *res) {
modexp(a, e, p, res);
*res = *res * b % p;
}
void kernelenk(ulint *m, ulint *k, ulint g, ulint p, ulint y, ulint *res) {
for (int i = 0; i < banyakdata; i++)
{
enkripsi(g, k[i], p, m[i], y, res + 2 * i);
}
}
void kerneldek(ulint *c, ulint p, ulint e, ulint *res) {
for (int i = 0; i < banyakdata; i++)
{
dekripsi(c[2 * i], c[2 * i + 1], p, e, res + i);
}
}
void enkripsiCUDA(ulint *m, ulint *k, ulint g, ulint p, ulint y, ulint *res) {
clock_t begin = clock();
kernelenk(m, k, g, p, y, res);
clock_t end = clock();
double time_spent = (double)(end - begin);
printf("Durasi enkripsi = %f milliseconds\n", time_spent / 1000);
}
void dekripsiCUDA(ulint *c, ulint p, ulint e, ulint *res2) {
clock_t begin = clock();
kerneldek(c, p, e, res2);
clock_t end = clock();
double time_spent = (double)(end - begin);
printf("Durasi dekripsi = %f milliseconds\n", time_spent / 1000);
}
void initenkripsi(ulint *m, ulint *k) {
for (int i = 0; i < banyakdata; i++) {
m[i] = rand() % 3999999978;
k[i] = rand() % 3999999978;
}
}
int main() {
ulint *m, *k, *res, *res2, g, p, y, x, e;
m = (ulint*)malloc(banyakdata * sizeof(ulint));
k = (ulint*)malloc(banyakdata * sizeof(ulint));
res = (ulint*)malloc(banyakdata * 2 * sizeof(ulint));
res2 = (ulint*)malloc(banyakdata * sizeof(ulint));
srand(2018);
g = rand() % 3999999978;
p = 3999999979;
x = rand() % 3999999978;
modexp(g, x, p, &y);
initenkripsi(m, k);
// printf("<<<<<<<<<<<<<<Pesan Asli>>>>>>>>>>>>>>>\n");
// for (int i = 0; i < 4; i++) {
// printf("m[%d] = %lu\n", i, m[i]);
// }
// printf("m[...]\n");
// printf("m[%d] = %lu\n", banyakdata - 1, m[banyakdata - 1]);
enkripsiCUDA(m, k, g, p, y, res);
// printf("<<<<<<<<<<<<<<Hasil Enkripsi>>>>>>>>>>>>>>>\n");
// for (int i = 0; i < 4; i++) {
// printf("c[%d] = %lu c[%d] = %lu\n", 2 * i, res[2 * i], 2 * i + 1, res[2 * i + 1]);
// }
// printf("c ...\n");
// printf("c[%d] = %lu c[%d] = %lu\n", banyakdata * 2 - 2, res[banyakdata * 2 - 2], banyakdata * 2 - 1, res[banyakdata * 2 - 1]);
e = p - x - 1;
dekripsiCUDA(res, p, e, res2);
// printf("<<<<<<<<<<<<<<Hasil Dekripsi>>>>>>>>>>>>>>>\n");
// for (int i = 0; i < 4; i++) {
// printf("m[%d] = %lu\n", i, res2[i]);
// }
// printf("m[...]\n");
// printf("m[%d] = %lu\n", banyakdata - 1, res2[banyakdata - 1]);
free(m);
free(k);
free(res);
free(res2);
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <math.h>
typedef unsigned long ulint;
typedef unsigned long long ulint64;
int banyakdata = 256000;
int dimensigrid = 2000;
int dimensiblok = 128;
void modexp(ulint a, ulint b, ulint c, ulint* res) {
ulint64 s = a;
ulint64 ans = 1;
while (b != 0) {
if (b % 2 == 1) {
ans = ans * s % c;
b--;
}
b /= 2;
if (b != 0) {
s = s * s %c;
}
}
*res = ans;
}
void enkripsi(ulint g, ulint k, ulint p, ulint m, ulint y, ulint *res) {
modexp(g, k, p, res);
modexp(y, k, p, res + 1);
*(res + 1) = *(res + 1) * m % p;
}
void dekripsi(ulint a, ulint b, ulint p, ulint e, ulint *res) {
modexp(a, e, p, res);
*res = *res * b % p;
}
void kernelenk(ulint *m, ulint *k, ulint g, ulint p, ulint y, ulint *res) {
for (int i = 0; i < banyakdata; i++)
{
enkripsi(g, k[i], p, m[i], y, res + 2 * i);
}
}
void kerneldek(ulint *c, ulint p, ulint e, ulint *res) {
for (int i = 0; i < banyakdata; i++)
{
dekripsi(c[2 * i], c[2 * i + 1], p, e, res + i);
}
}
void enkripsiCUDA(ulint *m, ulint *k, ulint g, ulint p, ulint y, ulint *res) {
clock_t begin = clock();
kernelenk(m, k, g, p, y, res);
clock_t end = clock();
double time_spent = (double)(end - begin);
printf("Durasi enkripsi = %f milliseconds\n", time_spent / 1000);
}
void dekripsiCUDA(ulint *c, ulint p, ulint e, ulint *res2) {
clock_t begin = clock();
kerneldek(c, p, e, res2);
clock_t end = clock();
double time_spent = (double)(end - begin);
printf("Durasi dekripsi = %f milliseconds\n", time_spent / 1000);
}
void initenkripsi(ulint *m, ulint *k) {
for (int i = 0; i < banyakdata; i++) {
m[i] = rand() % 3999999978;
k[i] = rand() % 3999999978;
}
}
int main() {
ulint *m, *k, *res, *res2, g, p, y, x, e;
m = (ulint*)malloc(banyakdata * sizeof(ulint));
k = (ulint*)malloc(banyakdata * sizeof(ulint));
res = (ulint*)malloc(banyakdata * 2 * sizeof(ulint));
res2 = (ulint*)malloc(banyakdata * sizeof(ulint));
srand(2018);
g = rand() % 3999999978;
p = 3999999979;
x = rand() % 3999999978;
modexp(g, x, p, &y);
initenkripsi(m, k);
// printf("<<<<<<<<<<<<<<Pesan Asli>>>>>>>>>>>>>>>\n");
// for (int i = 0; i < 4; i++) {
// printf("m[%d] = %lu\n", i, m[i]);
// }
// printf("m[...]\n");
// printf("m[%d] = %lu\n", banyakdata - 1, m[banyakdata - 1]);
enkripsiCUDA(m, k, g, p, y, res);
// printf("<<<<<<<<<<<<<<Hasil Enkripsi>>>>>>>>>>>>>>>\n");
// for (int i = 0; i < 4; i++) {
// printf("c[%d] = %lu c[%d] = %lu\n", 2 * i, res[2 * i], 2 * i + 1, res[2 * i + 1]);
// }
// printf("c ...\n");
// printf("c[%d] = %lu c[%d] = %lu\n", banyakdata * 2 - 2, res[banyakdata * 2 - 2], banyakdata * 2 - 1, res[banyakdata * 2 - 1]);
e = p - x - 1;
dekripsiCUDA(res, p, e, res2);
// printf("<<<<<<<<<<<<<<Hasil Dekripsi>>>>>>>>>>>>>>>\n");
// for (int i = 0; i < 4; i++) {
// printf("m[%d] = %lu\n", i, res2[i]);
// }
// printf("m[...]\n");
// printf("m[%d] = %lu\n", banyakdata - 1, res2[banyakdata - 1]);
free(m);
free(k);
free(res);
free(res2);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <math.h>
typedef unsigned long ulint;
typedef unsigned long long ulint64;
int banyakdata = 256000;
int dimensigrid = 2000;
int dimensiblok = 128;
void modexp(ulint a, ulint b, ulint c, ulint* res) {
ulint64 s = a;
ulint64 ans = 1;
while (b != 0) {
if (b % 2 == 1) {
ans = ans * s % c;
b--;
}
b /= 2;
if (b != 0) {
s = s * s %c;
}
}
*res = ans;
}
void enkripsi(ulint g, ulint k, ulint p, ulint m, ulint y, ulint *res) {
modexp(g, k, p, res);
modexp(y, k, p, res + 1);
*(res + 1) = *(res + 1) * m % p;
}
void dekripsi(ulint a, ulint b, ulint p, ulint e, ulint *res) {
modexp(a, e, p, res);
*res = *res * b % p;
}
void kernelenk(ulint *m, ulint *k, ulint g, ulint p, ulint y, ulint *res) {
for (int i = 0; i < banyakdata; i++)
{
enkripsi(g, k[i], p, m[i], y, res + 2 * i);
}
}
void kerneldek(ulint *c, ulint p, ulint e, ulint *res) {
for (int i = 0; i < banyakdata; i++)
{
dekripsi(c[2 * i], c[2 * i + 1], p, e, res + i);
}
}
void enkripsiCUDA(ulint *m, ulint *k, ulint g, ulint p, ulint y, ulint *res) {
clock_t begin = clock();
kernelenk(m, k, g, p, y, res);
clock_t end = clock();
double time_spent = (double)(end - begin);
printf("Durasi enkripsi = %f milliseconds\n", time_spent / 1000);
}
void dekripsiCUDA(ulint *c, ulint p, ulint e, ulint *res2) {
clock_t begin = clock();
kerneldek(c, p, e, res2);
clock_t end = clock();
double time_spent = (double)(end - begin);
printf("Durasi dekripsi = %f milliseconds\n", time_spent / 1000);
}
void initenkripsi(ulint *m, ulint *k) {
for (int i = 0; i < banyakdata; i++) {
m[i] = rand() % 3999999978;
k[i] = rand() % 3999999978;
}
}
int main() {
ulint *m, *k, *res, *res2, g, p, y, x, e;
m = (ulint*)malloc(banyakdata * sizeof(ulint));
k = (ulint*)malloc(banyakdata * sizeof(ulint));
res = (ulint*)malloc(banyakdata * 2 * sizeof(ulint));
res2 = (ulint*)malloc(banyakdata * sizeof(ulint));
srand(2018);
g = rand() % 3999999978;
p = 3999999979;
x = rand() % 3999999978;
modexp(g, x, p, &y);
initenkripsi(m, k);
// printf("<<<<<<<<<<<<<<Pesan Asli>>>>>>>>>>>>>>>\n");
// for (int i = 0; i < 4; i++) {
// printf("m[%d] = %lu\n", i, m[i]);
// }
// printf("m[...]\n");
// printf("m[%d] = %lu\n", banyakdata - 1, m[banyakdata - 1]);
enkripsiCUDA(m, k, g, p, y, res);
// printf("<<<<<<<<<<<<<<Hasil Enkripsi>>>>>>>>>>>>>>>\n");
// for (int i = 0; i < 4; i++) {
// printf("c[%d] = %lu c[%d] = %lu\n", 2 * i, res[2 * i], 2 * i + 1, res[2 * i + 1]);
// }
// printf("c ...\n");
// printf("c[%d] = %lu c[%d] = %lu\n", banyakdata * 2 - 2, res[banyakdata * 2 - 2], banyakdata * 2 - 1, res[banyakdata * 2 - 1]);
e = p - x - 1;
dekripsiCUDA(res, p, e, res2);
// printf("<<<<<<<<<<<<<<Hasil Dekripsi>>>>>>>>>>>>>>>\n");
// for (int i = 0; i < 4; i++) {
// printf("m[%d] = %lu\n", i, res2[i]);
// }
// printf("m[...]\n");
// printf("m[%d] = %lu\n", banyakdata - 1, res2[banyakdata - 1]);
free(m);
free(k);
free(res);
free(res2);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
#include <math.h>
typedef unsigned long ulint;
typedef unsigned long long ulint64;
int banyakdata = 256000;
int dimensigrid = 2000;
int dimensiblok = 128;
void modexp(ulint a, ulint b, ulint c, ulint* res) {
ulint64 s = a;
ulint64 ans = 1;
while (b != 0) {
if (b % 2 == 1) {
ans = ans * s % c;
b--;
}
b /= 2;
if (b != 0) {
s = s * s %c;
}
}
*res = ans;
}
void enkripsi(ulint g, ulint k, ulint p, ulint m, ulint y, ulint *res) {
modexp(g, k, p, res);
modexp(y, k, p, res + 1);
*(res + 1) = *(res + 1) * m % p;
}
void dekripsi(ulint a, ulint b, ulint p, ulint e, ulint *res) {
modexp(a, e, p, res);
*res = *res * b % p;
}
void kernelenk(ulint *m, ulint *k, ulint g, ulint p, ulint y, ulint *res) {
for (int i = 0; i < banyakdata; i++)
{
enkripsi(g, k[i], p, m[i], y, res + 2 * i);
}
}
void kerneldek(ulint *c, ulint p, ulint e, ulint *res) {
for (int i = 0; i < banyakdata; i++)
{
dekripsi(c[2 * i], c[2 * i + 1], p, e, res + i);
}
}
void enkripsiCUDA(ulint *m, ulint *k, ulint g, ulint p, ulint y, ulint *res) {
clock_t begin = clock();
kernelenk(m, k, g, p, y, res);
clock_t end = clock();
double time_spent = (double)(end - begin);
printf("Durasi enkripsi = %f milliseconds\n", time_spent / 1000);
}
void dekripsiCUDA(ulint *c, ulint p, ulint e, ulint *res2) {
clock_t begin = clock();
kerneldek(c, p, e, res2);
clock_t end = clock();
double time_spent = (double)(end - begin);
printf("Durasi dekripsi = %f milliseconds\n", time_spent / 1000);
}
void initenkripsi(ulint *m, ulint *k) {
for (int i = 0; i < banyakdata; i++) {
m[i] = rand() % 3999999978;
k[i] = rand() % 3999999978;
}
}
int main() {
ulint *m, *k, *res, *res2, g, p, y, x, e;
m = (ulint*)malloc(banyakdata * sizeof(ulint));
k = (ulint*)malloc(banyakdata * sizeof(ulint));
res = (ulint*)malloc(banyakdata * 2 * sizeof(ulint));
res2 = (ulint*)malloc(banyakdata * sizeof(ulint));
srand(2018);
g = rand() % 3999999978;
p = 3999999979;
x = rand() % 3999999978;
modexp(g, x, p, &y);
initenkripsi(m, k);
// printf("<<<<<<<<<<<<<<Pesan Asli>>>>>>>>>>>>>>>\n");
// for (int i = 0; i < 4; i++) {
// printf("m[%d] = %lu\n", i, m[i]);
// }
// printf("m[...]\n");
// printf("m[%d] = %lu\n", banyakdata - 1, m[banyakdata - 1]);
enkripsiCUDA(m, k, g, p, y, res);
// printf("<<<<<<<<<<<<<<Hasil Enkripsi>>>>>>>>>>>>>>>\n");
// for (int i = 0; i < 4; i++) {
// printf("c[%d] = %lu c[%d] = %lu\n", 2 * i, res[2 * i], 2 * i + 1, res[2 * i + 1]);
// }
// printf("c ...\n");
// printf("c[%d] = %lu c[%d] = %lu\n", banyakdata * 2 - 2, res[banyakdata * 2 - 2], banyakdata * 2 - 1, res[banyakdata * 2 - 1]);
e = p - x - 1;
dekripsiCUDA(res, p, e, res2);
// printf("<<<<<<<<<<<<<<Hasil Dekripsi>>>>>>>>>>>>>>>\n");
// for (int i = 0; i < 4; i++) {
// printf("m[%d] = %lu\n", i, res2[i]);
// }
// printf("m[...]\n");
// printf("m[%d] = %lu\n", banyakdata - 1, res2[banyakdata - 1]);
free(m);
free(k);
free(res);
free(res2);
return 0;
} | .text
.file "32.hip"
.globl _Z6modexpmmmPm # -- Begin function _Z6modexpmmmPm
.p2align 4, 0x90
.type _Z6modexpmmmPm,@function
_Z6modexpmmmPm: # @_Z6modexpmmmPm
.cfi_startproc
# %bb.0:
testq %rsi, %rsi
je .LBB0_1
# %bb.2: # %.lr.ph.preheader
movq %rdx, %r8
movl $1, %r9d
jmp .LBB0_3
.p2align 4, 0x90
.LBB0_7: # in Loop: Header=BB0_3 Depth=1
movq %rsi, %rax
shrq %rax
cmpq $1, %rsi
movq %rax, %rsi
jbe .LBB0_8
.LBB0_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
testb $1, %sil
je .LBB0_5
# %bb.4: # in Loop: Header=BB0_3 Depth=1
imulq %rdi, %r9
movq %r9, %rax
xorl %edx, %edx
divq %r8
decq %rsi
movq %rdx, %r9
.LBB0_5: # in Loop: Header=BB0_3 Depth=1
cmpq $2, %rsi
jb .LBB0_7
# %bb.6: # in Loop: Header=BB0_3 Depth=1
imulq %rdi, %rdi
movq %rdi, %rax
xorl %edx, %edx
divq %r8
movq %rdx, %rdi
jmp .LBB0_7
.LBB0_8: # %._crit_edge
movq %r9, (%rcx)
retq
.LBB0_1:
movl $1, %r9d
movq %r9, (%rcx)
retq
.Lfunc_end0:
.size _Z6modexpmmmPm, .Lfunc_end0-_Z6modexpmmmPm
.cfi_endproc
# -- End function
.globl _Z8enkripsimmmmmPm # -- Begin function _Z8enkripsimmmmmPm
.p2align 4, 0x90
.type _Z8enkripsimmmmmPm,@function
_Z8enkripsimmmmmPm: # @_Z8enkripsimmmmmPm
.cfi_startproc
# %bb.0:
movq %r8, %r10
movq %rdx, %r8
testq %rsi, %rsi
je .LBB1_14
# %bb.1: # %.lr.ph.i.preheader
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl $1, %r11d
movq %rsi, %rbx
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_6: # in Loop: Header=BB1_2 Depth=1
movq %rbx, %rax
shrq %rax
cmpq $1, %rbx
movq %rax, %rbx
jbe .LBB1_7
.LBB1_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
testb $1, %bl
je .LBB1_4
# %bb.3: # in Loop: Header=BB1_2 Depth=1
imulq %rdi, %r11
movq %r11, %rax
xorl %edx, %edx
divq %r8
decq %rbx
movq %rdx, %r11
.LBB1_4: # in Loop: Header=BB1_2 Depth=1
cmpq $2, %rbx
jb .LBB1_6
# %bb.5: # in Loop: Header=BB1_2 Depth=1
imulq %rdi, %rdi
movq %rdi, %rax
xorl %edx, %edx
divq %r8
movq %rdx, %rdi
jmp .LBB1_6
.LBB1_7: # %_Z6modexpmmmPm.exit
movq %r11, (%r9)
testq %rsi, %rsi
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
je .LBB1_15
# %bb.8: # %.lr.ph.i12.preheader
movl $1, %edi
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_13: # in Loop: Header=BB1_9 Depth=1
movq %rsi, %rax
shrq %rax
cmpq $2, %rsi
movq %rax, %rsi
jb .LBB1_16
.LBB1_9: # %.lr.ph.i12
# =>This Inner Loop Header: Depth=1
testb $1, %sil
je .LBB1_11
# %bb.10: # in Loop: Header=BB1_9 Depth=1
imulq %r10, %rdi
movq %rdi, %rax
xorl %edx, %edx
divq %r8
decq %rsi
movq %rdx, %rdi
.LBB1_11: # in Loop: Header=BB1_9 Depth=1
cmpq $2, %rsi
jb .LBB1_13
# %bb.12: # in Loop: Header=BB1_9 Depth=1
imulq %r10, %r10
movq %r10, %rax
xorl %edx, %edx
divq %r8
movq %rdx, %r10
jmp .LBB1_13
.LBB1_14: # %_Z6modexpmmmPm.exit23.critedge
movq $1, (%r9)
.LBB1_15: # %_Z6modexpmmmPm.exit23
movl $1, %edi
.LBB1_16: # %_Z6modexpmmmPm.exit23
imulq %rcx, %rdi
movq %rdi, %rax
xorl %edx, %edx
divq %r8
movq %rdx, 8(%r9)
retq
.Lfunc_end1:
.size _Z8enkripsimmmmmPm, .Lfunc_end1-_Z8enkripsimmmmmPm
.cfi_endproc
# -- End function
.globl _Z8dekripsimmmmPm # -- Begin function _Z8dekripsimmmmPm
.p2align 4, 0x90
.type _Z8dekripsimmmmPm,@function
_Z8dekripsimmmmPm: # @_Z8dekripsimmmmPm
.cfi_startproc
# %bb.0:
movq %rdx, %r9
testq %rcx, %rcx
je .LBB2_1
# %bb.2: # %.lr.ph.i.preheader
movq %rdi, %r10
movl $1, %edi
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_7: # in Loop: Header=BB2_3 Depth=1
movq %rcx, %rax
shrq %rax
cmpq $1, %rcx
movq %rax, %rcx
jbe .LBB2_8
.LBB2_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
testb $1, %cl
je .LBB2_5
# %bb.4: # in Loop: Header=BB2_3 Depth=1
imulq %r10, %rdi
movq %rdi, %rax
xorl %edx, %edx
divq %r9
decq %rcx
movq %rdx, %rdi
.LBB2_5: # in Loop: Header=BB2_3 Depth=1
cmpq $2, %rcx
jb .LBB2_7
# %bb.6: # in Loop: Header=BB2_3 Depth=1
imulq %r10, %r10
movq %r10, %rax
xorl %edx, %edx
divq %r9
movq %rdx, %r10
jmp .LBB2_7
.LBB2_1:
movl $1, %edi
.LBB2_8: # %_Z6modexpmmmPm.exit
imulq %rsi, %rdi
movq %rdi, %rax
xorl %edx, %edx
divq %r9
movq %rdx, (%r8)
retq
.Lfunc_end2:
.size _Z8dekripsimmmmPm, .Lfunc_end2-_Z8dekripsimmmmPm
.cfi_endproc
# -- End function
.globl _Z9kernelenkPmS_mmmS_ # -- Begin function _Z9kernelenkPmS_mmmS_
.p2align 4, 0x90
.type _Z9kernelenkPmS_mmmS_,@function
_Z9kernelenkPmS_mmmS_: # @_Z9kernelenkPmS_mmmS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, -8(%rsp) # 8-byte Spill
movl banyakdata(%rip), %r14d
testl %r14d, %r14d
jle .LBB3_19
# %bb.1: # %.lr.ph.preheader
movq %rdx, %r8
xorl %r15d, %r15d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_16: # %_Z6modexpmmmPm.exit23.critedge.i
# in Loop: Header=BB3_2 Depth=1
movq $1, (%r9,%r12,8)
.LBB3_17: # %_Z8enkripsimmmmmPm.exit
# in Loop: Header=BB3_2 Depth=1
movl $1, %r11d
.LBB3_18: # %_Z8enkripsimmmmmPm.exit
# in Loop: Header=BB3_2 Depth=1
imulq %r13, %r11
movq %r11, %rax
xorl %edx, %edx
divq %rcx
movq %rdx, 8(%r9,%r12,8)
incq %r15
cmpq %r14, %r15
je .LBB3_19
.LBB3_2: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
# Child Loop BB3_11 Depth 2
movq (%rsi,%r15,8), %r10
movq (%rdi,%r15,8), %r13
leaq (%r15,%r15), %r12
testq %r10, %r10
je .LBB3_16
# %bb.3: # %.lr.ph.i.i.preheader
# in Loop: Header=BB3_2 Depth=1
movl $1, %r11d
movq %r8, %rbx
movq %r10, %rbp
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_8: # in Loop: Header=BB3_4 Depth=2
movq %rbp, %rax
shrq %rax
cmpq $1, %rbp
movq %rax, %rbp
jbe .LBB3_9
.LBB3_4: # %.lr.ph.i.i
# Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
testb $1, %bpl
je .LBB3_6
# %bb.5: # in Loop: Header=BB3_4 Depth=2
imulq %rbx, %r11
movq %r11, %rax
xorl %edx, %edx
divq %rcx
decq %rbp
movq %rdx, %r11
.LBB3_6: # in Loop: Header=BB3_4 Depth=2
cmpq $2, %rbp
jb .LBB3_8
# %bb.7: # in Loop: Header=BB3_4 Depth=2
imulq %rbx, %rbx
movq %rbx, %rax
xorl %edx, %edx
divq %rcx
movq %rdx, %rbx
jmp .LBB3_8
.p2align 4, 0x90
.LBB3_9: # %_Z6modexpmmmPm.exit.i
# in Loop: Header=BB3_2 Depth=1
movq %r11, (%r9,%r12,8)
testq %r10, %r10
je .LBB3_17
# %bb.10: # %.lr.ph.i12.i.preheader
# in Loop: Header=BB3_2 Depth=1
movl $1, %r11d
movq -8(%rsp), %rbx # 8-byte Reload
jmp .LBB3_11
.p2align 4, 0x90
.LBB3_15: # in Loop: Header=BB3_11 Depth=2
movq %r10, %rax
shrq %rax
cmpq $2, %r10
movq %rax, %r10
jb .LBB3_18
.LBB3_11: # %.lr.ph.i12.i
# Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
testb $1, %r10b
je .LBB3_13
# %bb.12: # in Loop: Header=BB3_11 Depth=2
imulq %rbx, %r11
movq %r11, %rax
xorl %edx, %edx
divq %rcx
decq %r10
movq %rdx, %r11
.LBB3_13: # in Loop: Header=BB3_11 Depth=2
cmpq $2, %r10
jb .LBB3_15
# %bb.14: # in Loop: Header=BB3_11 Depth=2
imulq %rbx, %rbx
movq %rbx, %rax
xorl %edx, %edx
divq %rcx
movq %rdx, %rbx
jmp .LBB3_15
.LBB3_19: # %._crit_edge
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z9kernelenkPmS_mmmS_, .Lfunc_end3-_Z9kernelenkPmS_mmmS_
.cfi_endproc
# -- End function
.globl _Z9kerneldekPmmmS_ # -- Begin function _Z9kerneldekPmmmS_
.p2align 4, 0x90
.type _Z9kerneldekPmmmS_,@function
_Z9kerneldekPmmmS_: # @_Z9kerneldekPmmmS_
.cfi_startproc
# %bb.0:
movl banyakdata(%rip), %r11d
testl %r11d, %r11d
jle .LBB4_12
# %bb.1: # %.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %r8
xorl %ebx, %ebx
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_3: # in Loop: Header=BB4_2 Depth=1
movl $1, %r9d
.LBB4_10: # %_Z8dekripsimmmmPm.exit
# in Loop: Header=BB4_2 Depth=1
imulq %r14, %r9
movq %r9, %rax
xorl %edx, %edx
divq %rsi
movq %rdx, (%rcx,%rbx,8)
incq %rbx
cmpq %r11, %rbx
je .LBB4_11
.LBB4_2: # =>This Loop Header: Depth=1
# Child Loop BB4_5 Depth 2
movq %rbx, %rax
shlq $4, %rax
movq 8(%rdi,%rax), %r14
testq %r8, %r8
je .LBB4_3
# %bb.4: # %.lr.ph.i.i.preheader
# in Loop: Header=BB4_2 Depth=1
leaq (%rbx,%rbx), %rax
movq (%rdi,%rax,8), %r10
movl $1, %r9d
movq %r8, %r15
jmp .LBB4_5
.p2align 4, 0x90
.LBB4_9: # in Loop: Header=BB4_5 Depth=2
movq %r15, %rax
shrq %rax
cmpq $1, %r15
movq %rax, %r15
jbe .LBB4_10
.LBB4_5: # %.lr.ph.i.i
# Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
testb $1, %r15b
je .LBB4_7
# %bb.6: # in Loop: Header=BB4_5 Depth=2
imulq %r10, %r9
movq %r9, %rax
xorl %edx, %edx
divq %rsi
decq %r15
movq %rdx, %r9
.LBB4_7: # in Loop: Header=BB4_5 Depth=2
cmpq $2, %r15
jb .LBB4_9
# %bb.8: # in Loop: Header=BB4_5 Depth=2
imulq %r10, %r10
movq %r10, %rax
xorl %edx, %edx
divq %rsi
movq %rdx, %r10
jmp .LBB4_9
.LBB4_11:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB4_12: # %._crit_edge
retq
.Lfunc_end4:
.size _Z9kerneldekPmmmS_, .Lfunc_end4-_Z9kerneldekPmmmS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z12enkripsiCUDAPmS_mmmS_
.LCPI5_0:
.quad 0x408f400000000000 # double 1000
.text
.globl _Z12enkripsiCUDAPmS_mmmS_
.p2align 4, 0x90
.type _Z12enkripsiCUDAPmS_mmmS_,@function
_Z12enkripsiCUDAPmS_mmmS_: # @_Z12enkripsiCUDAPmS_mmmS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, 16(%rsp) # 8-byte Spill
movq %rcx, %r15
movq %rdx, %r13
movq %rsi, %rbp
movq %rdi, %r12
callq clock
movq %rax, 8(%rsp) # 8-byte Spill
movl banyakdata(%rip), %edi
testl %edi, %edi
jle .LBB5_19
# %bb.1: # %.lr.ph.preheader.i
xorl %r8d, %r8d
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_16: # %_Z6modexpmmmPm.exit23.critedge.i.i
# in Loop: Header=BB5_2 Depth=1
movq $1, (%rbx,%r9,8)
.LBB5_17: # %_Z8enkripsimmmmmPm.exit.i
# in Loop: Header=BB5_2 Depth=1
movl $1, %ecx
.LBB5_18: # %_Z8enkripsimmmmmPm.exit.i
# in Loop: Header=BB5_2 Depth=1
imulq %r10, %rcx
movq %rcx, %rax
xorl %edx, %edx
divq %r15
movq %rdx, 8(%rbx,%r9,8)
incq %r8
cmpq %rdi, %r8
je .LBB5_19
.LBB5_2: # %.lr.ph.i
# =>This Loop Header: Depth=1
# Child Loop BB5_4 Depth 2
# Child Loop BB5_11 Depth 2
movq (%rbp,%r8,8), %r14
movq (%r12,%r8,8), %r10
leaq (%r8,%r8), %r9
testq %r14, %r14
je .LBB5_16
# %bb.3: # %.lr.ph.i.i.i.preheader
# in Loop: Header=BB5_2 Depth=1
movl $1, %ecx
movq %r13, %rsi
movq %r14, %r11
jmp .LBB5_4
.p2align 4, 0x90
.LBB5_8: # in Loop: Header=BB5_4 Depth=2
movq %r11, %rax
shrq %rax
cmpq $1, %r11
movq %rax, %r11
jbe .LBB5_9
.LBB5_4: # %.lr.ph.i.i.i
# Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
testb $1, %r11b
je .LBB5_6
# %bb.5: # in Loop: Header=BB5_4 Depth=2
imulq %rsi, %rcx
movq %rcx, %rax
xorl %edx, %edx
divq %r15
decq %r11
movq %rdx, %rcx
.LBB5_6: # in Loop: Header=BB5_4 Depth=2
cmpq $2, %r11
jb .LBB5_8
# %bb.7: # in Loop: Header=BB5_4 Depth=2
imulq %rsi, %rsi
movq %rsi, %rax
xorl %edx, %edx
divq %r15
movq %rdx, %rsi
jmp .LBB5_8
.p2align 4, 0x90
.LBB5_9: # %_Z6modexpmmmPm.exit.i.i
# in Loop: Header=BB5_2 Depth=1
movq %rcx, (%rbx,%r9,8)
testq %r14, %r14
je .LBB5_17
# %bb.10: # %.lr.ph.i12.i.i.preheader
# in Loop: Header=BB5_2 Depth=1
movl $1, %ecx
movq 16(%rsp), %rsi # 8-byte Reload
jmp .LBB5_11
.p2align 4, 0x90
.LBB5_15: # in Loop: Header=BB5_11 Depth=2
movq %r14, %rax
shrq %rax
cmpq $2, %r14
movq %rax, %r14
jb .LBB5_18
.LBB5_11: # %.lr.ph.i12.i.i
# Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
testb $1, %r14b
je .LBB5_13
# %bb.12: # in Loop: Header=BB5_11 Depth=2
imulq %rsi, %rcx
movq %rcx, %rax
xorl %edx, %edx
divq %r15
decq %r14
movq %rdx, %rcx
.LBB5_13: # in Loop: Header=BB5_11 Depth=2
cmpq $2, %r14
jb .LBB5_15
# %bb.14: # in Loop: Header=BB5_11 Depth=2
imulq %rsi, %rsi
movq %rsi, %rax
xorl %edx, %edx
divq %r15
movq %rdx, %rsi
jmp .LBB5_15
.LBB5_19: # %_Z9kernelenkPmS_mmmS_.exit
callq clock
subq 8(%rsp), %rax # 8-byte Folded Reload
cvtsi2sd %rax, %xmm0
divsd .LCPI5_0(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.Lfunc_end5:
.size _Z12enkripsiCUDAPmS_mmmS_, .Lfunc_end5-_Z12enkripsiCUDAPmS_mmmS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z12dekripsiCUDAPmmmS_
.LCPI6_0:
.quad 0x408f400000000000 # double 1000
.text
.globl _Z12dekripsiCUDAPmmmS_
.p2align 4, 0x90
.type _Z12dekripsiCUDAPmmmS_,@function
_Z12dekripsiCUDAPmmmS_: # @_Z12dekripsiCUDAPmmmS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %rbx
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %r13
callq clock
movq %rax, %r14
movl banyakdata(%rip), %edi
testl %edi, %edi
jle .LBB6_11
# %bb.1: # %.lr.ph.i
xorl %r8d, %r8d
jmp .LBB6_2
.p2align 4, 0x90
.LBB6_3: # in Loop: Header=BB6_2 Depth=1
movl $1, %ecx
.LBB6_10: # %_Z8dekripsimmmmPm.exit.i
# in Loop: Header=BB6_2 Depth=1
imulq %r9, %rcx
movq %rcx, %rax
xorl %edx, %edx
divq %r12
movq %rdx, (%rbx,%r8,8)
incq %r8
cmpq %rdi, %r8
je .LBB6_11
.LBB6_2: # =>This Loop Header: Depth=1
# Child Loop BB6_5 Depth 2
movq %r8, %rax
shlq $4, %rax
movq 8(%r13,%rax), %r9
testq %r15, %r15
je .LBB6_3
# %bb.4: # %.lr.ph.i.i.preheader.i
# in Loop: Header=BB6_2 Depth=1
leaq (%r8,%r8), %rax
movq (%r13,%rax,8), %rsi
movl $1, %ecx
movq %r15, %r10
jmp .LBB6_5
.p2align 4, 0x90
.LBB6_9: # in Loop: Header=BB6_5 Depth=2
movq %r10, %rax
shrq %rax
cmpq $1, %r10
movq %rax, %r10
jbe .LBB6_10
.LBB6_5: # %.lr.ph.i.i.i
# Parent Loop BB6_2 Depth=1
# => This Inner Loop Header: Depth=2
testb $1, %r10b
je .LBB6_7
# %bb.6: # in Loop: Header=BB6_5 Depth=2
imulq %rsi, %rcx
movq %rcx, %rax
xorl %edx, %edx
divq %r12
decq %r10
movq %rdx, %rcx
.LBB6_7: # in Loop: Header=BB6_5 Depth=2
cmpq $2, %r10
jb .LBB6_9
# %bb.8: # in Loop: Header=BB6_5 Depth=2
imulq %rsi, %rsi
movq %rsi, %rax
xorl %edx, %edx
divq %r12
movq %rdx, %rsi
jmp .LBB6_9
.LBB6_11: # %_Z9kerneldekPmmmS_.exit
callq clock
subq %r14, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI6_0(%rip), %xmm0
movl $.L.str.1, %edi
movb $1, %al
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.Lfunc_end6:
.size _Z12dekripsiCUDAPmmmS_, .Lfunc_end6-_Z12dekripsiCUDAPmmmS_
.cfi_endproc
# -- End function
.globl _Z12initenkripsiPmS_ # -- Begin function _Z12initenkripsiPmS_
.p2align 4, 0x90
.type _Z12initenkripsiPmS_,@function
_Z12initenkripsiPmS_: # @_Z12initenkripsiPmS_
.cfi_startproc
# %bb.0:
cmpl $0, banyakdata(%rip)
jle .LBB7_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB7_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
movq %rax, (%r14,%r15,8)
callq rand
cltq
movq %rax, (%rbx,%r15,8)
incq %r15
movslq banyakdata(%rip), %rax
cmpq %rax, %r15
jl .LBB7_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB7_4: # %._crit_edge
retq
.Lfunc_end7:
.size _Z12initenkripsiPmS_, .Lfunc_end7-_Z12initenkripsiPmS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI8_0:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movslq banyakdata(%rip), %r15
leaq (,%r15,8), %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movq %r14, %rdi
callq malloc
movq %rax, %r14
shlq $4, %r15
movq %r15, %rdi
callq malloc
movq %rax, %r15
movl $2018, %edi # imm = 0x7E2
callq srand
callq rand
movslq %eax, %r12
callq rand
testl %eax, %eax
je .LBB8_1
# %bb.2: # %.lr.ph.i.preheader
movslq %eax, %r8
movl $1, %r13d
movabsq $1360296658843496629, %rsi # imm = 0x12E0BE9AA38470B5
movl $3999999979, %edi # imm = 0xEE6B27EB
movq %r12, %rcx
jmp .LBB8_3
.p2align 4, 0x90
.LBB8_7: # in Loop: Header=BB8_3 Depth=1
movq %r8, %rax
shrq %rax
cmpq $1, %r8
movq %rax, %r8
jbe .LBB8_8
.LBB8_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
testb $1, %r8b
je .LBB8_5
# %bb.4: # in Loop: Header=BB8_3 Depth=1
imulq %rcx, %r13
movq %r13, %rax
mulq %rsi
movq %r13, %rax
subq %rdx, %rax
shrq %rax
addq %rdx, %rax
shrq $31, %rax
imulq %rdi, %rax
subq %rax, %r13
decq %r8
.LBB8_5: # in Loop: Header=BB8_3 Depth=1
cmpq $2, %r8
jb .LBB8_7
# %bb.6: # in Loop: Header=BB8_3 Depth=1
imulq %rcx, %rcx
movq %rcx, %rax
mulq %rsi
movq %rcx, %rax
subq %rdx, %rax
shrq %rax
addq %rdx, %rax
shrq $31, %rax
imulq %rdi, %rax
subq %rax, %rcx
jmp .LBB8_7
.LBB8_1:
movl $1, %r13d
.LBB8_8: # %_Z6modexpmmmPm.exit
cmpl $0, banyakdata(%rip)
jle .LBB8_11
# %bb.9: # %.lr.ph.i19.preheader
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB8_10: # %.lr.ph.i19
# =>This Inner Loop Header: Depth=1
callq rand
cltq
movq %rax, (%rbx,%rbp,8)
callq rand
cltq
movq %rax, (%r14,%rbp,8)
incq %rbp
movslq banyakdata(%rip), %rax
cmpq %rax, %rbp
jl .LBB8_10
.LBB8_11: # %_Z12initenkripsiPmS_.exit
movl $3999999979, %ecx # imm = 0xEE6B27EB
movq %rbx, %rdi
movq %r14, %rsi
movq %r12, %rdx
movq %r13, %r8
movq %r15, %r9
callq _Z12enkripsiCUDAPmS_mmmS_
callq clock
movq %rax, %r12
callq clock
subq %r12, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI8_0(%rip), %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size main, .Lfunc_end8-main
.cfi_endproc
# -- End function
.type banyakdata,@object # @banyakdata
.data
.globl banyakdata
.p2align 2, 0x0
banyakdata:
.long 256000 # 0x3e800
.size banyakdata, 4
.type dimensigrid,@object # @dimensigrid
.globl dimensigrid
.p2align 2, 0x0
dimensigrid:
.long 2000 # 0x7d0
.size dimensigrid, 4
.type dimensiblok,@object # @dimensiblok
.globl dimensiblok
.p2align 2, 0x0
dimensiblok:
.long 128 # 0x80
.size dimensiblok, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Durasi enkripsi = %f milliseconds\n"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Durasi dekripsi = %f milliseconds\n"
.size .L.str.1, 35
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001320db_00000000-6_32.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6modexpmmmPm
.type _Z6modexpmmmPm, @function
_Z6modexpmmmPm:
.LFB2057:
.cfi_startproc
endbr64
movq %rdx, %r9
testq %rsi, %rsi
je .L7
movl $1, %r8d
jmp .L6
.L5:
cmpq $1, %rsi
jbe .L4
shrq %rsi
imulq %rdi, %rdi
movq %rdi, %rax
movl $0, %edx
divq %r9
movq %rdx, %rdi
.L6:
testb $1, %sil
je .L5
movq %r8, %rax
imulq %rdi, %rax
movl $0, %edx
divq %r9
movq %rdx, %r8
subq $1, %rsi
jmp .L5
.L7:
movl $1, %r8d
.L4:
movq %r8, (%rcx)
ret
.cfi_endproc
.LFE2057:
.size _Z6modexpmmmPm, .-_Z6modexpmmmPm
.globl _Z8enkripsimmmmmPm
.type _Z8enkripsimmmmmPm, @function
_Z8enkripsimmmmmPm:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rsi, %r13
movq %rdx, %r12
movq %rcx, %rbx
movq %r8, %r14
movq %r9, %rbp
movq %r9, %rcx
call _Z6modexpmmmPm
leaq 8(%rbp), %rcx
movq %r12, %rdx
movq %r13, %rsi
movq %r14, %rdi
call _Z6modexpmmmPm
movq %rbx, %rax
imulq 8(%rbp), %rax
movl $0, %edx
divq %r12
movq %rdx, 8(%rbp)
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z8enkripsimmmmmPm, .-_Z8enkripsimmmmmPm
.globl _Z8dekripsimmmmPm
.type _Z8dekripsimmmmPm, @function
_Z8dekripsimmmmPm:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %rbx
movq %rdx, %r12
movq %rcx, %rsi
movq %r8, %rbp
movq %r8, %rcx
call _Z6modexpmmmPm
movq %rbx, %rax
imulq 0(%rbp), %rax
movl $0, %edx
divq %r12
movq %rdx, 0(%rbp)
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z8dekripsimmmmPm, .-_Z8dekripsimmmmPm
.globl _Z9kernelenkPmS_mmmS_
.type _Z9kernelenkPmS_mmmS_, @function
_Z9kernelenkPmS_mmmS_:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdx, (%rsp)
movl banyakdata(%rip), %eax
testl %eax, %eax
jle .L12
movq %rdi, %r12
movq %rsi, %rbp
movq %rcx, %r14
movq %r8, %r15
movq %r9, %rbx
cltq
salq $4, %rax
leaq (%r9,%rax), %r13
.L14:
movq (%r12), %rcx
movq 0(%rbp), %rsi
movq %rbx, %r9
movq %r15, %r8
movq %r14, %rdx
movq (%rsp), %rdi
call _Z8enkripsimmmmmPm
addq $8, %r12
addq $8, %rbp
addq $16, %rbx
cmpq %r13, %rbx
jne .L14
.L12:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z9kernelenkPmS_mmmS_, .-_Z9kernelenkPmS_mmmS_
.globl _Z9kerneldekPmmmS_
.type _Z9kerneldekPmmmS_, @function
_Z9kerneldekPmmmS_:
.LFB2061:
.cfi_startproc
endbr64
movl banyakdata(%rip), %eax
testl %eax, %eax
jle .L22
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rsi, %r13
movq %rdx, %r14
movq %rdi, %rbx
movq %rcx, %rbp
cltq
salq $4, %rax
leaq (%rdi,%rax), %r12
.L19:
movq 8(%rbx), %rsi
movq (%rbx), %rdi
movq %rbp, %r8
movq %r14, %rcx
movq %r13, %rdx
call _Z8dekripsimmmmPm
addq $16, %rbx
addq $8, %rbp
cmpq %r12, %rbx
jne .L19
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
ret
.cfi_endproc
.LFE2061:
.size _Z9kerneldekPmmmS_, .-_Z9kerneldekPmmmS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Durasi enkripsi = %f milliseconds\n"
.text
.globl _Z12enkripsiCUDAPmS_mmmS_
.type _Z12enkripsiCUDAPmS_mmmS_, @function
_Z12enkripsiCUDAPmS_mmmS_:
.LFB2062:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 8(%rsp)
movq %rsi, %rbp
movq %rdx, %r12
movq %rcx, %r13
movq %r8, %r14
movq %r9, %r15
call clock@PLT
movq %rax, %rbx
movq %r15, %r9
movq %r14, %r8
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call _Z9kernelenkPmS_mmmS_
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z12enkripsiCUDAPmS_mmmS_, .-_Z12enkripsiCUDAPmS_mmmS_
.section .rodata.str1.8
.align 8
.LC2:
.string "Durasi dekripsi = %f milliseconds\n"
.text
.globl _Z12dekripsiCUDAPmmmS_
.type _Z12dekripsiCUDAPmmmS_, @function
_Z12dekripsiCUDAPmmmS_:
.LFB2063:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %rbp
movq %rsi, %r12
movq %rdx, %r13
movq %rcx, %r14
call clock@PLT
movq %rax, %rbx
movq %r14, %rcx
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _Z9kerneldekPmmmS_
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _Z12dekripsiCUDAPmmmS_, .-_Z12dekripsiCUDAPmmmS_
.globl _Z12initenkripsiPmS_
.type _Z12initenkripsiPmS_, @function
_Z12initenkripsiPmS_:
.LFB2064:
.cfi_startproc
endbr64
cmpl $0, banyakdata(%rip)
jle .L34
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r13
movq %rsi, %r14
movl $0, %ebx
movabsq $2475880092188101057, %r12
movl $3999999978, %ebp
.L31:
call rand@PLT
movslq %eax, %rcx
movq %rcx, %rax
imulq %r12
sarq $29, %rdx
movq %rcx, %rax
sarq $63, %rax
subq %rax, %rdx
imulq %rbp, %rdx
subq %rdx, %rcx
movq %rcx, 0(%r13,%rbx,8)
call rand@PLT
movslq %eax, %rcx
movq %rcx, %rax
imulq %r12
sarq $29, %rdx
movq %rcx, %rax
sarq $63, %rax
subq %rax, %rdx
imulq %rbp, %rdx
subq %rdx, %rcx
movq %rcx, (%r14,%rbx,8)
addq $1, %rbx
cmpl %ebx, banyakdata(%rip)
jg .L31
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
ret
.cfi_endproc
.LFE2064:
.size _Z12initenkripsiPmS_, .-_Z12initenkripsiPmS_
.globl main
.type main, @function
main:
.LFB2065:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl banyakdata(%rip), %ebx
movslq %ebx, %rbp
salq $3, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
leal (%rbx,%rbx), %edi
movslq %edi, %rdi
salq $3, %rdi
call malloc@PLT
movq %rax, (%rsp)
movq %rbp, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movl $2018, %edi
call srand@PLT
call rand@PLT
movslq %eax, %rcx
movabsq $2475880092188101057, %rbx
movq %rcx, %rax
imulq %rbx
sarq $29, %rdx
movq %rcx, %rsi
sarq $63, %rsi
subq %rsi, %rdx
movq %rdx, %rbp
movl $3999999978, %r14d
imulq %r14, %rbp
subq %rbp, %rcx
movq %rcx, %rbp
call rand@PLT
movslq %eax, %rcx
movq %rcx, %rax
imulq %rbx
movq %rdx, %rbx
sarq $29, %rbx
movq %rcx, %rsi
sarq $63, %rsi
subq %rsi, %rbx
imulq %r14, %rbx
subq %rbx, %rcx
movq %rcx, %rbx
leaq 16(%rsp), %rcx
movl $3999999979, %r15d
movq %r15, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z6modexpmmmPm
movq %r12, %rsi
movq %r13, %rdi
call _Z12initenkripsiPmS_
movq (%rsp), %r9
movq 16(%rsp), %r8
movq %r15, %rcx
movq %rbp, %rdx
movq %r12, %rsi
movq %r13, %rdi
call _Z12enkripsiCUDAPmS_mmmS_
movq %r14, %rdx
subq %rbx, %rdx
movq 8(%rsp), %r14
movq %r14, %rcx
movq %r15, %rsi
movq (%rsp), %rbx
movq %rbx, %rdi
call _Z12dekripsiCUDAPmmmS_
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L40
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2065:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl dimensiblok
.data
.align 4
.type dimensiblok, @object
.size dimensiblok, 4
dimensiblok:
.long 128
.globl dimensigrid
.align 4
.type dimensigrid, @object
.size dimensigrid, 4
dimensigrid:
.long 2000
.globl banyakdata
.align 4
.type banyakdata, @object
.size banyakdata, 4
banyakdata:
.long 256000
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "32.hip"
.globl _Z6modexpmmmPm # -- Begin function _Z6modexpmmmPm
.p2align 4, 0x90
.type _Z6modexpmmmPm,@function
_Z6modexpmmmPm: # @_Z6modexpmmmPm
.cfi_startproc
# %bb.0:
testq %rsi, %rsi
je .LBB0_1
# %bb.2: # %.lr.ph.preheader
movq %rdx, %r8
movl $1, %r9d
jmp .LBB0_3
.p2align 4, 0x90
.LBB0_7: # in Loop: Header=BB0_3 Depth=1
movq %rsi, %rax
shrq %rax
cmpq $1, %rsi
movq %rax, %rsi
jbe .LBB0_8
.LBB0_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
testb $1, %sil
je .LBB0_5
# %bb.4: # in Loop: Header=BB0_3 Depth=1
imulq %rdi, %r9
movq %r9, %rax
xorl %edx, %edx
divq %r8
decq %rsi
movq %rdx, %r9
.LBB0_5: # in Loop: Header=BB0_3 Depth=1
cmpq $2, %rsi
jb .LBB0_7
# %bb.6: # in Loop: Header=BB0_3 Depth=1
imulq %rdi, %rdi
movq %rdi, %rax
xorl %edx, %edx
divq %r8
movq %rdx, %rdi
jmp .LBB0_7
.LBB0_8: # %._crit_edge
movq %r9, (%rcx)
retq
.LBB0_1:
movl $1, %r9d
movq %r9, (%rcx)
retq
.Lfunc_end0:
.size _Z6modexpmmmPm, .Lfunc_end0-_Z6modexpmmmPm
.cfi_endproc
# -- End function
.globl _Z8enkripsimmmmmPm # -- Begin function _Z8enkripsimmmmmPm
.p2align 4, 0x90
.type _Z8enkripsimmmmmPm,@function
_Z8enkripsimmmmmPm: # @_Z8enkripsimmmmmPm
.cfi_startproc
# %bb.0:
movq %r8, %r10
movq %rdx, %r8
testq %rsi, %rsi
je .LBB1_14
# %bb.1: # %.lr.ph.i.preheader
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl $1, %r11d
movq %rsi, %rbx
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_6: # in Loop: Header=BB1_2 Depth=1
movq %rbx, %rax
shrq %rax
cmpq $1, %rbx
movq %rax, %rbx
jbe .LBB1_7
.LBB1_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
testb $1, %bl
je .LBB1_4
# %bb.3: # in Loop: Header=BB1_2 Depth=1
imulq %rdi, %r11
movq %r11, %rax
xorl %edx, %edx
divq %r8
decq %rbx
movq %rdx, %r11
.LBB1_4: # in Loop: Header=BB1_2 Depth=1
cmpq $2, %rbx
jb .LBB1_6
# %bb.5: # in Loop: Header=BB1_2 Depth=1
imulq %rdi, %rdi
movq %rdi, %rax
xorl %edx, %edx
divq %r8
movq %rdx, %rdi
jmp .LBB1_6
.LBB1_7: # %_Z6modexpmmmPm.exit
movq %r11, (%r9)
testq %rsi, %rsi
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
je .LBB1_15
# %bb.8: # %.lr.ph.i12.preheader
movl $1, %edi
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_13: # in Loop: Header=BB1_9 Depth=1
movq %rsi, %rax
shrq %rax
cmpq $2, %rsi
movq %rax, %rsi
jb .LBB1_16
.LBB1_9: # %.lr.ph.i12
# =>This Inner Loop Header: Depth=1
testb $1, %sil
je .LBB1_11
# %bb.10: # in Loop: Header=BB1_9 Depth=1
imulq %r10, %rdi
movq %rdi, %rax
xorl %edx, %edx
divq %r8
decq %rsi
movq %rdx, %rdi
.LBB1_11: # in Loop: Header=BB1_9 Depth=1
cmpq $2, %rsi
jb .LBB1_13
# %bb.12: # in Loop: Header=BB1_9 Depth=1
imulq %r10, %r10
movq %r10, %rax
xorl %edx, %edx
divq %r8
movq %rdx, %r10
jmp .LBB1_13
.LBB1_14: # %_Z6modexpmmmPm.exit23.critedge
movq $1, (%r9)
.LBB1_15: # %_Z6modexpmmmPm.exit23
movl $1, %edi
.LBB1_16: # %_Z6modexpmmmPm.exit23
imulq %rcx, %rdi
movq %rdi, %rax
xorl %edx, %edx
divq %r8
movq %rdx, 8(%r9)
retq
.Lfunc_end1:
.size _Z8enkripsimmmmmPm, .Lfunc_end1-_Z8enkripsimmmmmPm
.cfi_endproc
# -- End function
.globl _Z8dekripsimmmmPm # -- Begin function _Z8dekripsimmmmPm
.p2align 4, 0x90
.type _Z8dekripsimmmmPm,@function
_Z8dekripsimmmmPm: # @_Z8dekripsimmmmPm
.cfi_startproc
# %bb.0:
movq %rdx, %r9
testq %rcx, %rcx
je .LBB2_1
# %bb.2: # %.lr.ph.i.preheader
movq %rdi, %r10
movl $1, %edi
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_7: # in Loop: Header=BB2_3 Depth=1
movq %rcx, %rax
shrq %rax
cmpq $1, %rcx
movq %rax, %rcx
jbe .LBB2_8
.LBB2_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
testb $1, %cl
je .LBB2_5
# %bb.4: # in Loop: Header=BB2_3 Depth=1
imulq %r10, %rdi
movq %rdi, %rax
xorl %edx, %edx
divq %r9
decq %rcx
movq %rdx, %rdi
.LBB2_5: # in Loop: Header=BB2_3 Depth=1
cmpq $2, %rcx
jb .LBB2_7
# %bb.6: # in Loop: Header=BB2_3 Depth=1
imulq %r10, %r10
movq %r10, %rax
xorl %edx, %edx
divq %r9
movq %rdx, %r10
jmp .LBB2_7
.LBB2_1:
movl $1, %edi
.LBB2_8: # %_Z6modexpmmmPm.exit
imulq %rsi, %rdi
movq %rdi, %rax
xorl %edx, %edx
divq %r9
movq %rdx, (%r8)
retq
.Lfunc_end2:
.size _Z8dekripsimmmmPm, .Lfunc_end2-_Z8dekripsimmmmPm
.cfi_endproc
# -- End function
.globl _Z9kernelenkPmS_mmmS_ # -- Begin function _Z9kernelenkPmS_mmmS_
.p2align 4, 0x90
.type _Z9kernelenkPmS_mmmS_,@function
_Z9kernelenkPmS_mmmS_: # @_Z9kernelenkPmS_mmmS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, -8(%rsp) # 8-byte Spill
movl banyakdata(%rip), %r14d
testl %r14d, %r14d
jle .LBB3_19
# %bb.1: # %.lr.ph.preheader
movq %rdx, %r8
xorl %r15d, %r15d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_16: # %_Z6modexpmmmPm.exit23.critedge.i
# in Loop: Header=BB3_2 Depth=1
movq $1, (%r9,%r12,8)
.LBB3_17: # %_Z8enkripsimmmmmPm.exit
# in Loop: Header=BB3_2 Depth=1
movl $1, %r11d
.LBB3_18: # %_Z8enkripsimmmmmPm.exit
# in Loop: Header=BB3_2 Depth=1
imulq %r13, %r11
movq %r11, %rax
xorl %edx, %edx
divq %rcx
movq %rdx, 8(%r9,%r12,8)
incq %r15
cmpq %r14, %r15
je .LBB3_19
.LBB3_2: # %.lr.ph
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
# Child Loop BB3_11 Depth 2
movq (%rsi,%r15,8), %r10
movq (%rdi,%r15,8), %r13
leaq (%r15,%r15), %r12
testq %r10, %r10
je .LBB3_16
# %bb.3: # %.lr.ph.i.i.preheader
# in Loop: Header=BB3_2 Depth=1
movl $1, %r11d
movq %r8, %rbx
movq %r10, %rbp
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_8: # in Loop: Header=BB3_4 Depth=2
movq %rbp, %rax
shrq %rax
cmpq $1, %rbp
movq %rax, %rbp
jbe .LBB3_9
.LBB3_4: # %.lr.ph.i.i
# Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
testb $1, %bpl
je .LBB3_6
# %bb.5: # in Loop: Header=BB3_4 Depth=2
imulq %rbx, %r11
movq %r11, %rax
xorl %edx, %edx
divq %rcx
decq %rbp
movq %rdx, %r11
.LBB3_6: # in Loop: Header=BB3_4 Depth=2
cmpq $2, %rbp
jb .LBB3_8
# %bb.7: # in Loop: Header=BB3_4 Depth=2
imulq %rbx, %rbx
movq %rbx, %rax
xorl %edx, %edx
divq %rcx
movq %rdx, %rbx
jmp .LBB3_8
.p2align 4, 0x90
.LBB3_9: # %_Z6modexpmmmPm.exit.i
# in Loop: Header=BB3_2 Depth=1
movq %r11, (%r9,%r12,8)
testq %r10, %r10
je .LBB3_17
# %bb.10: # %.lr.ph.i12.i.preheader
# in Loop: Header=BB3_2 Depth=1
movl $1, %r11d
movq -8(%rsp), %rbx # 8-byte Reload
jmp .LBB3_11
.p2align 4, 0x90
.LBB3_15: # in Loop: Header=BB3_11 Depth=2
movq %r10, %rax
shrq %rax
cmpq $2, %r10
movq %rax, %r10
jb .LBB3_18
.LBB3_11: # %.lr.ph.i12.i
# Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
testb $1, %r10b
je .LBB3_13
# %bb.12: # in Loop: Header=BB3_11 Depth=2
imulq %rbx, %r11
movq %r11, %rax
xorl %edx, %edx
divq %rcx
decq %r10
movq %rdx, %r11
.LBB3_13: # in Loop: Header=BB3_11 Depth=2
cmpq $2, %r10
jb .LBB3_15
# %bb.14: # in Loop: Header=BB3_11 Depth=2
imulq %rbx, %rbx
movq %rbx, %rax
xorl %edx, %edx
divq %rcx
movq %rdx, %rbx
jmp .LBB3_15
.LBB3_19: # %._crit_edge
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z9kernelenkPmS_mmmS_, .Lfunc_end3-_Z9kernelenkPmS_mmmS_
.cfi_endproc
# -- End function
.globl _Z9kerneldekPmmmS_ # -- Begin function _Z9kerneldekPmmmS_
.p2align 4, 0x90
.type _Z9kerneldekPmmmS_,@function
_Z9kerneldekPmmmS_: # @_Z9kerneldekPmmmS_
.cfi_startproc
# %bb.0:
movl banyakdata(%rip), %r11d
testl %r11d, %r11d
jle .LBB4_12
# %bb.1: # %.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %r8
xorl %ebx, %ebx
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_3: # in Loop: Header=BB4_2 Depth=1
movl $1, %r9d
.LBB4_10: # %_Z8dekripsimmmmPm.exit
# in Loop: Header=BB4_2 Depth=1
imulq %r14, %r9
movq %r9, %rax
xorl %edx, %edx
divq %rsi
movq %rdx, (%rcx,%rbx,8)
incq %rbx
cmpq %r11, %rbx
je .LBB4_11
.LBB4_2: # =>This Loop Header: Depth=1
# Child Loop BB4_5 Depth 2
movq %rbx, %rax
shlq $4, %rax
movq 8(%rdi,%rax), %r14
testq %r8, %r8
je .LBB4_3
# %bb.4: # %.lr.ph.i.i.preheader
# in Loop: Header=BB4_2 Depth=1
leaq (%rbx,%rbx), %rax
movq (%rdi,%rax,8), %r10
movl $1, %r9d
movq %r8, %r15
jmp .LBB4_5
.p2align 4, 0x90
.LBB4_9: # in Loop: Header=BB4_5 Depth=2
movq %r15, %rax
shrq %rax
cmpq $1, %r15
movq %rax, %r15
jbe .LBB4_10
.LBB4_5: # %.lr.ph.i.i
# Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
testb $1, %r15b
je .LBB4_7
# %bb.6: # in Loop: Header=BB4_5 Depth=2
imulq %r10, %r9
movq %r9, %rax
xorl %edx, %edx
divq %rsi
decq %r15
movq %rdx, %r9
.LBB4_7: # in Loop: Header=BB4_5 Depth=2
cmpq $2, %r15
jb .LBB4_9
# %bb.8: # in Loop: Header=BB4_5 Depth=2
imulq %r10, %r10
movq %r10, %rax
xorl %edx, %edx
divq %rsi
movq %rdx, %r10
jmp .LBB4_9
.LBB4_11:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB4_12: # %._crit_edge
retq
.Lfunc_end4:
.size _Z9kerneldekPmmmS_, .Lfunc_end4-_Z9kerneldekPmmmS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z12enkripsiCUDAPmS_mmmS_
.LCPI5_0:
.quad 0x408f400000000000 # double 1000
.text
.globl _Z12enkripsiCUDAPmS_mmmS_
.p2align 4, 0x90
.type _Z12enkripsiCUDAPmS_mmmS_,@function
_Z12enkripsiCUDAPmS_mmmS_: # @_Z12enkripsiCUDAPmS_mmmS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, 16(%rsp) # 8-byte Spill
movq %rcx, %r15
movq %rdx, %r13
movq %rsi, %rbp
movq %rdi, %r12
callq clock
movq %rax, 8(%rsp) # 8-byte Spill
movl banyakdata(%rip), %edi
testl %edi, %edi
jle .LBB5_19
# %bb.1: # %.lr.ph.preheader.i
xorl %r8d, %r8d
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_16: # %_Z6modexpmmmPm.exit23.critedge.i.i
# in Loop: Header=BB5_2 Depth=1
movq $1, (%rbx,%r9,8)
.LBB5_17: # %_Z8enkripsimmmmmPm.exit.i
# in Loop: Header=BB5_2 Depth=1
movl $1, %ecx
.LBB5_18: # %_Z8enkripsimmmmmPm.exit.i
# in Loop: Header=BB5_2 Depth=1
imulq %r10, %rcx
movq %rcx, %rax
xorl %edx, %edx
divq %r15
movq %rdx, 8(%rbx,%r9,8)
incq %r8
cmpq %rdi, %r8
je .LBB5_19
.LBB5_2: # %.lr.ph.i
# =>This Loop Header: Depth=1
# Child Loop BB5_4 Depth 2
# Child Loop BB5_11 Depth 2
movq (%rbp,%r8,8), %r14
movq (%r12,%r8,8), %r10
leaq (%r8,%r8), %r9
testq %r14, %r14
je .LBB5_16
# %bb.3: # %.lr.ph.i.i.i.preheader
# in Loop: Header=BB5_2 Depth=1
movl $1, %ecx
movq %r13, %rsi
movq %r14, %r11
jmp .LBB5_4
.p2align 4, 0x90
.LBB5_8: # in Loop: Header=BB5_4 Depth=2
movq %r11, %rax
shrq %rax
cmpq $1, %r11
movq %rax, %r11
jbe .LBB5_9
.LBB5_4: # %.lr.ph.i.i.i
# Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
testb $1, %r11b
je .LBB5_6
# %bb.5: # in Loop: Header=BB5_4 Depth=2
imulq %rsi, %rcx
movq %rcx, %rax
xorl %edx, %edx
divq %r15
decq %r11
movq %rdx, %rcx
.LBB5_6: # in Loop: Header=BB5_4 Depth=2
cmpq $2, %r11
jb .LBB5_8
# %bb.7: # in Loop: Header=BB5_4 Depth=2
imulq %rsi, %rsi
movq %rsi, %rax
xorl %edx, %edx
divq %r15
movq %rdx, %rsi
jmp .LBB5_8
.p2align 4, 0x90
.LBB5_9: # %_Z6modexpmmmPm.exit.i.i
# in Loop: Header=BB5_2 Depth=1
movq %rcx, (%rbx,%r9,8)
testq %r14, %r14
je .LBB5_17
# %bb.10: # %.lr.ph.i12.i.i.preheader
# in Loop: Header=BB5_2 Depth=1
movl $1, %ecx
movq 16(%rsp), %rsi # 8-byte Reload
jmp .LBB5_11
.p2align 4, 0x90
.LBB5_15: # in Loop: Header=BB5_11 Depth=2
movq %r14, %rax
shrq %rax
cmpq $2, %r14
movq %rax, %r14
jb .LBB5_18
.LBB5_11: # %.lr.ph.i12.i.i
# Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
testb $1, %r14b
je .LBB5_13
# %bb.12: # in Loop: Header=BB5_11 Depth=2
imulq %rsi, %rcx
movq %rcx, %rax
xorl %edx, %edx
divq %r15
decq %r14
movq %rdx, %rcx
.LBB5_13: # in Loop: Header=BB5_11 Depth=2
cmpq $2, %r14
jb .LBB5_15
# %bb.14: # in Loop: Header=BB5_11 Depth=2
imulq %rsi, %rsi
movq %rsi, %rax
xorl %edx, %edx
divq %r15
movq %rdx, %rsi
jmp .LBB5_15
.LBB5_19: # %_Z9kernelenkPmS_mmmS_.exit
callq clock
subq 8(%rsp), %rax # 8-byte Folded Reload
cvtsi2sd %rax, %xmm0
divsd .LCPI5_0(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.Lfunc_end5:
.size _Z12enkripsiCUDAPmS_mmmS_, .Lfunc_end5-_Z12enkripsiCUDAPmS_mmmS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z12dekripsiCUDAPmmmS_
.LCPI6_0:
.quad 0x408f400000000000 # double 1000
.text
.globl _Z12dekripsiCUDAPmmmS_
.p2align 4, 0x90
.type _Z12dekripsiCUDAPmmmS_,@function
_Z12dekripsiCUDAPmmmS_: # @_Z12dekripsiCUDAPmmmS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %rbx
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %r13
callq clock
movq %rax, %r14
movl banyakdata(%rip), %edi
testl %edi, %edi
jle .LBB6_11
# %bb.1: # %.lr.ph.i
xorl %r8d, %r8d
jmp .LBB6_2
.p2align 4, 0x90
.LBB6_3: # in Loop: Header=BB6_2 Depth=1
movl $1, %ecx
.LBB6_10: # %_Z8dekripsimmmmPm.exit.i
# in Loop: Header=BB6_2 Depth=1
imulq %r9, %rcx
movq %rcx, %rax
xorl %edx, %edx
divq %r12
movq %rdx, (%rbx,%r8,8)
incq %r8
cmpq %rdi, %r8
je .LBB6_11
.LBB6_2: # =>This Loop Header: Depth=1
# Child Loop BB6_5 Depth 2
movq %r8, %rax
shlq $4, %rax
movq 8(%r13,%rax), %r9
testq %r15, %r15
je .LBB6_3
# %bb.4: # %.lr.ph.i.i.preheader.i
# in Loop: Header=BB6_2 Depth=1
leaq (%r8,%r8), %rax
movq (%r13,%rax,8), %rsi
movl $1, %ecx
movq %r15, %r10
jmp .LBB6_5
.p2align 4, 0x90
.LBB6_9: # in Loop: Header=BB6_5 Depth=2
movq %r10, %rax
shrq %rax
cmpq $1, %r10
movq %rax, %r10
jbe .LBB6_10
.LBB6_5: # %.lr.ph.i.i.i
# Parent Loop BB6_2 Depth=1
# => This Inner Loop Header: Depth=2
testb $1, %r10b
je .LBB6_7
# %bb.6: # in Loop: Header=BB6_5 Depth=2
imulq %rsi, %rcx
movq %rcx, %rax
xorl %edx, %edx
divq %r12
decq %r10
movq %rdx, %rcx
.LBB6_7: # in Loop: Header=BB6_5 Depth=2
cmpq $2, %r10
jb .LBB6_9
# %bb.8: # in Loop: Header=BB6_5 Depth=2
imulq %rsi, %rsi
movq %rsi, %rax
xorl %edx, %edx
divq %r12
movq %rdx, %rsi
jmp .LBB6_9
.LBB6_11: # %_Z9kerneldekPmmmS_.exit
callq clock
subq %r14, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI6_0(%rip), %xmm0
movl $.L.str.1, %edi
movb $1, %al
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.Lfunc_end6:
.size _Z12dekripsiCUDAPmmmS_, .Lfunc_end6-_Z12dekripsiCUDAPmmmS_
.cfi_endproc
# -- End function
.globl _Z12initenkripsiPmS_ # -- Begin function _Z12initenkripsiPmS_
.p2align 4, 0x90
.type _Z12initenkripsiPmS_,@function
_Z12initenkripsiPmS_: # @_Z12initenkripsiPmS_
.cfi_startproc
# %bb.0:
cmpl $0, banyakdata(%rip)
jle .LBB7_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB7_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
movq %rax, (%r14,%r15,8)
callq rand
cltq
movq %rax, (%rbx,%r15,8)
incq %r15
movslq banyakdata(%rip), %rax
cmpq %rax, %r15
jl .LBB7_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB7_4: # %._crit_edge
retq
.Lfunc_end7:
.size _Z12initenkripsiPmS_, .Lfunc_end7-_Z12initenkripsiPmS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI8_0:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movslq banyakdata(%rip), %r15
leaq (,%r15,8), %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movq %r14, %rdi
callq malloc
movq %rax, %r14
shlq $4, %r15
movq %r15, %rdi
callq malloc
movq %rax, %r15
movl $2018, %edi # imm = 0x7E2
callq srand
callq rand
movslq %eax, %r12
callq rand
testl %eax, %eax
je .LBB8_1
# %bb.2: # %.lr.ph.i.preheader
movslq %eax, %r8
movl $1, %r13d
movabsq $1360296658843496629, %rsi # imm = 0x12E0BE9AA38470B5
movl $3999999979, %edi # imm = 0xEE6B27EB
movq %r12, %rcx
jmp .LBB8_3
.p2align 4, 0x90
.LBB8_7: # in Loop: Header=BB8_3 Depth=1
movq %r8, %rax
shrq %rax
cmpq $1, %r8
movq %rax, %r8
jbe .LBB8_8
.LBB8_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
testb $1, %r8b
je .LBB8_5
# %bb.4: # in Loop: Header=BB8_3 Depth=1
imulq %rcx, %r13
movq %r13, %rax
mulq %rsi
movq %r13, %rax
subq %rdx, %rax
shrq %rax
addq %rdx, %rax
shrq $31, %rax
imulq %rdi, %rax
subq %rax, %r13
decq %r8
.LBB8_5: # in Loop: Header=BB8_3 Depth=1
cmpq $2, %r8
jb .LBB8_7
# %bb.6: # in Loop: Header=BB8_3 Depth=1
imulq %rcx, %rcx
movq %rcx, %rax
mulq %rsi
movq %rcx, %rax
subq %rdx, %rax
shrq %rax
addq %rdx, %rax
shrq $31, %rax
imulq %rdi, %rax
subq %rax, %rcx
jmp .LBB8_7
.LBB8_1:
movl $1, %r13d
.LBB8_8: # %_Z6modexpmmmPm.exit
cmpl $0, banyakdata(%rip)
jle .LBB8_11
# %bb.9: # %.lr.ph.i19.preheader
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB8_10: # %.lr.ph.i19
# =>This Inner Loop Header: Depth=1
callq rand
cltq
movq %rax, (%rbx,%rbp,8)
callq rand
cltq
movq %rax, (%r14,%rbp,8)
incq %rbp
movslq banyakdata(%rip), %rax
cmpq %rax, %rbp
jl .LBB8_10
.LBB8_11: # %_Z12initenkripsiPmS_.exit
movl $3999999979, %ecx # imm = 0xEE6B27EB
movq %rbx, %rdi
movq %r14, %rsi
movq %r12, %rdx
movq %r13, %r8
movq %r15, %r9
callq _Z12enkripsiCUDAPmS_mmmS_
callq clock
movq %rax, %r12
callq clock
subq %r12, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI8_0(%rip), %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size main, .Lfunc_end8-main
.cfi_endproc
# -- End function
.type banyakdata,@object # @banyakdata
.data
.globl banyakdata
.p2align 2, 0x0
banyakdata:
.long 256000 # 0x3e800
.size banyakdata, 4
.type dimensigrid,@object # @dimensigrid
.globl dimensigrid
.p2align 2, 0x0
dimensigrid:
.long 2000 # 0x7d0
.size dimensigrid, 4
.type dimensiblok,@object # @dimensiblok
.globl dimensiblok
.p2align 2, 0x0
dimensiblok:
.long 128 # 0x80
.size dimensiblok, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Durasi enkripsi = %f milliseconds\n"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Durasi dekripsi = %f milliseconds\n"
.size .L.str.1, 35
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cuda.h>
// includes CUDA Runtime
#include <cuda_runtime.h>
#include <cuda_profiler_api.h>
/*
written by George Strauch on 4/21/2020
c++ program to sort an array with bubblesort on gpu
Execution syntax:
$ ./exec {int num of elements}
Example run:
$ nvcc gpu_bubble.cu -arch='sm_35' -rdc=true -lineinfo -lcudadevrt -o gpu_bs
$ time ./gpu_bs 10
$ time ./gpu_bs 20000
*/
__host__ // used for debug
void print_array (int *array, int n, int tag_index)
{
for (size_t i = 0; i < n; i++) {
if (i == tag_index+1) {
std::cout << " > ";
}
std::cout << array[i] << ' ';
}
std::cout << '\n';
}
__host__
int* allocate_shared_array(int n_elements)
{
int *a;
cudaMallocManaged(&a, n_elements*sizeof(int));
return a;
}
__host__ // makes and returns unsorted array with random elements
int* make_unsorted_array(int n_elements)
{
int *a = allocate_shared_array(n_elements);
for (size_t j = 0; j < n_elements; j++) {
a[j] = rand()%(2*n_elements);
}
return a;
}
__host__
bool go_again(int* array, int n)
{
for (size_t i = 0; i < n-1; i++) {
if(array[i] > array[i+1])
{
return true;
}
}
return false;
}
__global__
void sort(int* array, int n, int offset, int k)
{
int id = 2*(blockIdx.x*blockDim.x + threadIdx.x) + offset + k;
if (id >= n) {
return;
}
int tmp;
if (array[id] > array[id+1]) {
tmp = array[id+1];
array[id+1] = array[id];
array[id] = tmp;
}
__syncthreads();
}
__host__
void fill_array(int* a, int n) {
for (size_t i = 0; i < n; i++) {
a[i] = 0;
}
}
__host__ // returns element index if any element larger than i+1 element, else -1
int verify_in_order(int* array, int n)
{
for (size_t i = 0; i < n-1; i++) {
if (array[i+1] < array[i]) {
return i;
}
}
return -1;
}
__host__
void entry_point(int* array, int n)
{
int t = 512;
int b = 512;
int count = 0;
int total = t*b;
dim3 threads(t);
dim3 blocks(b);
// fill_array(array, n);
while (go_again(array, n)) {
cudaDeviceSynchronize();
for (size_t i = 0; i < (n/(2*total)) +1; i++) {
sort<<<blocks, threads>>>(array, n, 0, i*total);
cudaDeviceSynchronize();
sort<<<blocks, threads>>>(array, n, 1, i*total);
}
cudaDeviceSynchronize();
count++;
if (count > 1.5*n) {
break;
}
}
}
int main(int argc, char const *argv[])
{
int N = atoi(argv[1]);
std::cout << "N = " << N << '\n';
int* a = make_unsorted_array(N);
cudaProfilerStart();
// while (go_again(a, N)) {
// sort<<<1, N/2>>>(a, N, 0);
// sort<<<1, N/2>>>(a, N, 1);
// cudaDeviceSynchronize();
// }
entry_point(a, N);
cudaProfilerStop();
int order = verify_in_order(a, N);
if (order == -1) {
std::cout << "array is in order" << '\n';
}
else {
std::cout << "not in order" << '\n';
print_array(a, N, order);
}
cudaFree(a);
return 0;
}
// | code for sm_80
Function : _Z4sortPiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ LEA R0, R0, c[0x0][0x16c], 0x1 ; /* 0x00005b0000007a11 */
/* 0x000fc800078e08ff */
/*0050*/ IADD3 R0, R0, c[0x0][0x170], RZ ; /* 0x00005c0000007a10 */
/* 0x000fc80007ffe0ff */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00b0*/ LDG.E R5, [R2.64+0x4] ; /* 0x0000040402057981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00d0*/ ISETP.GT.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x004fda0003f04270 */
/*00e0*/ @P0 STG.E [R2.64+0x4], R0 ; /* 0x0000040002000986 */
/* 0x000fe8000c101904 */
/*00f0*/ @P0 STG.E [R2.64], R5 ; /* 0x0000000502000986 */
/* 0x000fe8000c101904 */
/*0100*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cuda.h>
// includes CUDA Runtime
#include <cuda_runtime.h>
#include <cuda_profiler_api.h>
/*
written by George Strauch on 4/21/2020
c++ program to sort an array with bubblesort on gpu
Execution syntax:
$ ./exec {int num of elements}
Example run:
$ nvcc gpu_bubble.cu -arch='sm_35' -rdc=true -lineinfo -lcudadevrt -o gpu_bs
$ time ./gpu_bs 10
$ time ./gpu_bs 20000
*/
__host__ // used for debug
void print_array (int *array, int n, int tag_index)
{
for (size_t i = 0; i < n; i++) {
if (i == tag_index+1) {
std::cout << " > ";
}
std::cout << array[i] << ' ';
}
std::cout << '\n';
}
__host__
int* allocate_shared_array(int n_elements)
{
int *a;
cudaMallocManaged(&a, n_elements*sizeof(int));
return a;
}
__host__ // makes and returns unsorted array with random elements
int* make_unsorted_array(int n_elements)
{
int *a = allocate_shared_array(n_elements);
for (size_t j = 0; j < n_elements; j++) {
a[j] = rand()%(2*n_elements);
}
return a;
}
__host__
bool go_again(int* array, int n)
{
for (size_t i = 0; i < n-1; i++) {
if(array[i] > array[i+1])
{
return true;
}
}
return false;
}
__global__
void sort(int* array, int n, int offset, int k)
{
int id = 2*(blockIdx.x*blockDim.x + threadIdx.x) + offset + k;
if (id >= n) {
return;
}
int tmp;
if (array[id] > array[id+1]) {
tmp = array[id+1];
array[id+1] = array[id];
array[id] = tmp;
}
__syncthreads();
}
__host__
void fill_array(int* a, int n) {
for (size_t i = 0; i < n; i++) {
a[i] = 0;
}
}
__host__ // returns element index if any element larger than i+1 element, else -1
int verify_in_order(int* array, int n)
{
for (size_t i = 0; i < n-1; i++) {
if (array[i+1] < array[i]) {
return i;
}
}
return -1;
}
__host__
void entry_point(int* array, int n)
{
int t = 512;
int b = 512;
int count = 0;
int total = t*b;
dim3 threads(t);
dim3 blocks(b);
// fill_array(array, n);
while (go_again(array, n)) {
cudaDeviceSynchronize();
for (size_t i = 0; i < (n/(2*total)) +1; i++) {
sort<<<blocks, threads>>>(array, n, 0, i*total);
cudaDeviceSynchronize();
sort<<<blocks, threads>>>(array, n, 1, i*total);
}
cudaDeviceSynchronize();
count++;
if (count > 1.5*n) {
break;
}
}
}
int main(int argc, char const *argv[])
{
int N = atoi(argv[1]);
std::cout << "N = " << N << '\n';
int* a = make_unsorted_array(N);
cudaProfilerStart();
// while (go_again(a, N)) {
// sort<<<1, N/2>>>(a, N, 0);
// sort<<<1, N/2>>>(a, N, 1);
// cudaDeviceSynchronize();
// }
entry_point(a, N);
cudaProfilerStop();
int order = verify_in_order(a, N);
if (order == -1) {
std::cout << "array is in order" << '\n';
}
else {
std::cout << "not in order" << '\n';
print_array(a, N, order);
}
cudaFree(a);
return 0;
}
// | .file "tmpxft_001aed6d_00000000-6_gpu_bubble.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3679:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3679:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " > "
.text
.globl _Z11print_arrayPiii
.type _Z11print_arrayPiii, @function
_Z11print_arrayPiii:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
testl %esi, %esi
je .L4
movq %rdi, %r12
movslq %esi, %r14
movl $0, %ebx
addl $1, %edx
movslq %edx, %rbp
leaq _ZSt4cout(%rip), %r13
leaq 7(%rsp), %r15
jmp .L8
.L14:
movl $3, %edx
leaq .LC0(%rip), %rsi
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L5
.L6:
movl $32, %esi
call _ZNSo3putEc@PLT
.L7:
addq $1, %rbx
cmpq %r14, %rbx
je .L4
.L8:
cmpq %rbx, %rbp
je .L14
.L5:
movl (%r12,%rbx,4), %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movb $32, 7(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L6
movl $1, %edx
movq %r15, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L7
.L4:
movb $10, 7(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
cmpq $0, 16(%rdx,%rax)
je .L9
leaq 7(%rsp), %rsi
movl $1, %edx
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L3:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
movl $10, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
jmp .L3
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z11print_arrayPiii, .-_Z11print_arrayPiii
.globl _Z21allocate_shared_arrayi
.type _Z21allocate_shared_arrayi, @function
_Z21allocate_shared_arrayi:
.LFB3670:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movslq %edi, %rsi
salq $2, %rsi
movq %rsp, %rdi
movl $1, %edx
call cudaMallocManaged@PLT
movq (%rsp), %rax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L19
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size _Z21allocate_shared_arrayi, .-_Z21allocate_shared_arrayi
.globl _Z19make_unsorted_arrayi
.type _Z19make_unsorted_arrayi, @function
_Z19make_unsorted_arrayi:
.LFB3671:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebp
call _Z21allocate_shared_arrayi
movq %rax, %r12
testl %ebp, %ebp
je .L20
movslq %ebp, %r13
addl %ebp, %ebp
movl $0, %ebx
.L22:
call rand@PLT
cltd
idivl %ebp
movl %edx, (%r12,%rbx,4)
addq $1, %rbx
cmpq %r13, %rbx
jne .L22
.L20:
movq %r12, %rax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3671:
.size _Z19make_unsorted_arrayi, .-_Z19make_unsorted_arrayi
.globl _Z8go_againPii
.type _Z8go_againPii, @function
_Z8go_againPii:
.LFB3672:
.cfi_startproc
endbr64
movslq %esi, %rsi
subq $1, %rsi
movl $0, %eax
.L26:
cmpq %rsi, %rax
je .L30
movl (%rdi,%rax,4), %edx
addq $1, %rax
cmpl (%rdi,%rax,4), %edx
jle .L26
movl $1, %eax
ret
.L30:
movl $0, %eax
ret
.cfi_endproc
.LFE3672:
.size _Z8go_againPii, .-_Z8go_againPii
.globl _Z10fill_arrayPii
.type _Z10fill_arrayPii, @function
_Z10fill_arrayPii:
.LFB3673:
.cfi_startproc
endbr64
movslq %esi, %rdx
testl %esi, %esi
je .L31
movq %rdi, %rax
leaq (%rdi,%rdx,4), %rdx
.L33:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L33
.L31:
ret
.cfi_endproc
.LFE3673:
.size _Z10fill_arrayPii, .-_Z10fill_arrayPii
.globl _Z15verify_in_orderPii
.type _Z15verify_in_orderPii, @function
_Z15verify_in_orderPii:
.LFB3674:
.cfi_startproc
endbr64
movslq %esi, %rsi
subq $1, %rsi
movl $0, %eax
.L36:
cmpq %rsi, %rax
je .L40
leaq 1(%rax), %rdx
movl (%rdi,%rax,4), %ecx
cmpl %ecx, 4(%rdi,%rax,4)
jl .L35
movq %rdx, %rax
jmp .L36
.L40:
movl $-1, %eax
.L35:
ret
.cfi_endproc
.LFE3674:
.size _Z15verify_in_orderPii, .-_Z15verify_in_orderPii
.globl _Z26__device_stub__Z4sortPiiiiPiiii
.type _Z26__device_stub__Z4sortPiiiiPiiii, @function
_Z26__device_stub__Z4sortPiiiiPiiii:
.LFB3701:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4sortPiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3701:
.size _Z26__device_stub__Z4sortPiiiiPiiii, .-_Z26__device_stub__Z4sortPiiiiPiiii
.globl _Z4sortPiiii
.type _Z4sortPiiii, @function
_Z4sortPiiii:
.LFB3702:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z4sortPiiiiPiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _Z4sortPiiii, .-_Z4sortPiiii
.globl _Z11entry_pointPii
.type _Z11entry_pointPii, @function
_Z11entry_pointPii:
.LFB3675:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r13
movl %esi, %r12d
movl $512, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
leal 524287(%rsi), %ebp
testl %esi, %esi
cmovns %esi, %ebp
sarl $19, %ebp
addl $1, %ebp
movslq %ebp, %rbp
movl $0, %r14d
jmp .L50
.L59:
movl %ebx, %ecx
sall $18, %ecx
movl $0, %edx
movl %r12d, %esi
movq %r13, %rdi
call _Z26__device_stub__Z4sortPiiiiPiiii
jmp .L52
.L53:
addq $1, %rbx
cmpq %rbp, %rbx
jnb .L51
.L54:
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl 28(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L59
.L52:
call cudaDeviceSynchronize@PLT
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl 28(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L53
movl %ebx, %ecx
sall $18, %ecx
movl $1, %edx
movl %r12d, %esi
movq %r13, %rdi
call _Z26__device_stub__Z4sortPiiiiPiiii
jmp .L53
.L51:
call cudaDeviceSynchronize@PLT
addl $1, %r14d
pxor %xmm1, %xmm1
cvtsi2sdl %r14d, %xmm1
pxor %xmm0, %xmm0
cvtsi2sdl %r12d, %xmm0
mulsd .LC1(%rip), %xmm0
comisd %xmm0, %xmm1
ja .L49
.L50:
movl %r12d, %esi
movq %r13, %rdi
call _Z8go_againPii
testb %al, %al
je .L49
call cudaDeviceSynchronize@PLT
leal 1048575(%r12), %eax
cmpl $524287, %eax
jbe .L51
movl $0, %ebx
jmp .L54
.L49:
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _Z11entry_pointPii, .-_Z11entry_pointPii
.section .rodata.str1.1
.LC2:
.string "N = "
.LC3:
.string "array is in order"
.LC4:
.string "not in order"
.text
.globl main
.type main, @function
main:
.LFB3676:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movl %ebx, %edi
call _Z19make_unsorted_arrayi
movq %rax, %rbp
call cudaProfilerStart@PLT
movl %ebx, %esi
movq %rbp, %rdi
call _Z11entry_pointPii
call cudaProfilerStop@PLT
movl %ebx, %esi
movq %rbp, %rdi
call _Z15verify_in_orderPii
cmpl $-1, %eax
je .L64
movl %eax, %r12d
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movl %r12d, %edx
movl %ebx, %esi
movq %rbp, %rdi
call _Z11print_arrayPiii
.L62:
movq %rbp, %rdi
call cudaFree@PLT
movl $0, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L64:
.cfi_restore_state
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
jmp .L62
.cfi_endproc
.LFE3676:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z4sortPiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3704:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z4sortPiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3704:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1073217536
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cuda.h>
// includes CUDA Runtime
#include <cuda_runtime.h>
#include <cuda_profiler_api.h>
/*
written by George Strauch on 4/21/2020
c++ program to sort an array with bubblesort on gpu
Execution syntax:
$ ./exec {int num of elements}
Example run:
$ nvcc gpu_bubble.cu -arch='sm_35' -rdc=true -lineinfo -lcudadevrt -o gpu_bs
$ time ./gpu_bs 10
$ time ./gpu_bs 20000
*/
__host__ // used for debug
void print_array (int *array, int n, int tag_index)
{
for (size_t i = 0; i < n; i++) {
if (i == tag_index+1) {
std::cout << " > ";
}
std::cout << array[i] << ' ';
}
std::cout << '\n';
}
__host__
int* allocate_shared_array(int n_elements)
{
int *a;
cudaMallocManaged(&a, n_elements*sizeof(int));
return a;
}
__host__ // makes and returns unsorted array with random elements
int* make_unsorted_array(int n_elements)
{
int *a = allocate_shared_array(n_elements);
for (size_t j = 0; j < n_elements; j++) {
a[j] = rand()%(2*n_elements);
}
return a;
}
__host__
bool go_again(int* array, int n)
{
for (size_t i = 0; i < n-1; i++) {
if(array[i] > array[i+1])
{
return true;
}
}
return false;
}
__global__
void sort(int* array, int n, int offset, int k)
{
int id = 2*(blockIdx.x*blockDim.x + threadIdx.x) + offset + k;
if (id >= n) {
return;
}
int tmp;
if (array[id] > array[id+1]) {
tmp = array[id+1];
array[id+1] = array[id];
array[id] = tmp;
}
__syncthreads();
}
__host__
void fill_array(int* a, int n) {
for (size_t i = 0; i < n; i++) {
a[i] = 0;
}
}
__host__ // returns element index if any element larger than i+1 element, else -1
int verify_in_order(int* array, int n)
{
for (size_t i = 0; i < n-1; i++) {
if (array[i+1] < array[i]) {
return i;
}
}
return -1;
}
__host__
void entry_point(int* array, int n)
{
int t = 512;
int b = 512;
int count = 0;
int total = t*b;
dim3 threads(t);
dim3 blocks(b);
// fill_array(array, n);
while (go_again(array, n)) {
cudaDeviceSynchronize();
for (size_t i = 0; i < (n/(2*total)) +1; i++) {
sort<<<blocks, threads>>>(array, n, 0, i*total);
cudaDeviceSynchronize();
sort<<<blocks, threads>>>(array, n, 1, i*total);
}
cudaDeviceSynchronize();
count++;
if (count > 1.5*n) {
break;
}
}
}
int main(int argc, char const *argv[])
{
int N = atoi(argv[1]);
std::cout << "N = " << N << '\n';
int* a = make_unsorted_array(N);
cudaProfilerStart();
// while (go_again(a, N)) {
// sort<<<1, N/2>>>(a, N, 0);
// sort<<<1, N/2>>>(a, N, 1);
// cudaDeviceSynchronize();
// }
entry_point(a, N);
cudaProfilerStop();
int order = verify_in_order(a, N);
if (order == -1) {
std::cout << "array is in order" << '\n';
}
else {
std::cout << "not in order" << '\n';
print_array(a, N, order);
}
cudaFree(a);
return 0;
}
// | #include <iostream>
#include <hip/hip_runtime.h>
// includes CUDA Runtime
#include <hip/hip_runtime_api.h>
/*
written by George Strauch on 4/21/2020
c++ program to sort an array with bubblesort on gpu
Execution syntax:
$ ./exec {int num of elements}
Example run:
$ nvcc gpu_bubble.cu -arch='sm_35' -rdc=true -lineinfo -lcudadevrt -o gpu_bs
$ time ./gpu_bs 10
$ time ./gpu_bs 20000
*/
__host__ // used for debug
void print_array (int *array, int n, int tag_index)
{
for (size_t i = 0; i < n; i++) {
if (i == tag_index+1) {
std::cout << " > ";
}
std::cout << array[i] << ' ';
}
std::cout << '\n';
}
__host__
int* allocate_shared_array(int n_elements)
{
int *a;
hipMallocManaged(&a, n_elements*sizeof(int));
return a;
}
__host__ // makes and returns unsorted array with random elements
int* make_unsorted_array(int n_elements)
{
int *a = allocate_shared_array(n_elements);
for (size_t j = 0; j < n_elements; j++) {
a[j] = rand()%(2*n_elements);
}
return a;
}
__host__
bool go_again(int* array, int n)
{
for (size_t i = 0; i < n-1; i++) {
if(array[i] > array[i+1])
{
return true;
}
}
return false;
}
__global__
void sort(int* array, int n, int offset, int k)
{
int id = 2*(blockIdx.x*blockDim.x + threadIdx.x) + offset + k;
if (id >= n) {
return;
}
int tmp;
if (array[id] > array[id+1]) {
tmp = array[id+1];
array[id+1] = array[id];
array[id] = tmp;
}
__syncthreads();
}
__host__
void fill_array(int* a, int n) {
for (size_t i = 0; i < n; i++) {
a[i] = 0;
}
}
__host__ // returns element index if any element larger than i+1 element, else -1
int verify_in_order(int* array, int n)
{
for (size_t i = 0; i < n-1; i++) {
if (array[i+1] < array[i]) {
return i;
}
}
return -1;
}
__host__
void entry_point(int* array, int n)
{
int t = 512;
int b = 512;
int count = 0;
int total = t*b;
dim3 threads(t);
dim3 blocks(b);
// fill_array(array, n);
while (go_again(array, n)) {
hipDeviceSynchronize();
for (size_t i = 0; i < (n/(2*total)) +1; i++) {
sort<<<blocks, threads>>>(array, n, 0, i*total);
hipDeviceSynchronize();
sort<<<blocks, threads>>>(array, n, 1, i*total);
}
hipDeviceSynchronize();
count++;
if (count > 1.5*n) {
break;
}
}
}
int main(int argc, char const *argv[])
{
int N = atoi(argv[1]);
std::cout << "N = " << N << '\n';
int* a = make_unsorted_array(N);
hipProfilerStart();
// while (go_again(a, N)) {
// sort<<<1, N/2>>>(a, N, 0);
// sort<<<1, N/2>>>(a, N, 1);
// cudaDeviceSynchronize();
// }
entry_point(a, N);
hipProfilerStop();
int order = verify_in_order(a, N);
if (order == -1) {
std::cout << "array is in order" << '\n';
}
else {
std::cout << "not in order" << '\n';
print_array(a, N, order);
}
hipFree(a);
return 0;
}
// |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <hip/hip_runtime.h>
// includes CUDA Runtime
#include <hip/hip_runtime_api.h>
/*
written by George Strauch on 4/21/2020
c++ program to sort an array with bubblesort on gpu
Execution syntax:
$ ./exec {int num of elements}
Example run:
$ nvcc gpu_bubble.cu -arch='sm_35' -rdc=true -lineinfo -lcudadevrt -o gpu_bs
$ time ./gpu_bs 10
$ time ./gpu_bs 20000
*/
__host__ // used for debug
void print_array (int *array, int n, int tag_index)
{
for (size_t i = 0; i < n; i++) {
if (i == tag_index+1) {
std::cout << " > ";
}
std::cout << array[i] << ' ';
}
std::cout << '\n';
}
__host__
int* allocate_shared_array(int n_elements)
{
int *a;
hipMallocManaged(&a, n_elements*sizeof(int));
return a;
}
__host__ // makes and returns unsorted array with random elements
int* make_unsorted_array(int n_elements)
{
int *a = allocate_shared_array(n_elements);
for (size_t j = 0; j < n_elements; j++) {
a[j] = rand()%(2*n_elements);
}
return a;
}
__host__
bool go_again(int* array, int n)
{
for (size_t i = 0; i < n-1; i++) {
if(array[i] > array[i+1])
{
return true;
}
}
return false;
}
__global__
void sort(int* array, int n, int offset, int k)
{
int id = 2*(blockIdx.x*blockDim.x + threadIdx.x) + offset + k;
if (id >= n) {
return;
}
int tmp;
if (array[id] > array[id+1]) {
tmp = array[id+1];
array[id+1] = array[id];
array[id] = tmp;
}
__syncthreads();
}
__host__
void fill_array(int* a, int n) {
for (size_t i = 0; i < n; i++) {
a[i] = 0;
}
}
__host__ // returns element index if any element larger than i+1 element, else -1
int verify_in_order(int* array, int n)
{
for (size_t i = 0; i < n-1; i++) {
if (array[i+1] < array[i]) {
return i;
}
}
return -1;
}
__host__
void entry_point(int* array, int n)
{
int t = 512;
int b = 512;
int count = 0;
int total = t*b;
dim3 threads(t);
dim3 blocks(b);
// fill_array(array, n);
while (go_again(array, n)) {
hipDeviceSynchronize();
for (size_t i = 0; i < (n/(2*total)) +1; i++) {
sort<<<blocks, threads>>>(array, n, 0, i*total);
hipDeviceSynchronize();
sort<<<blocks, threads>>>(array, n, 1, i*total);
}
hipDeviceSynchronize();
count++;
if (count > 1.5*n) {
break;
}
}
}
int main(int argc, char const *argv[])
{
int N = atoi(argv[1]);
std::cout << "N = " << N << '\n';
int* a = make_unsorted_array(N);
hipProfilerStart();
// while (go_again(a, N)) {
// sort<<<1, N/2>>>(a, N, 0);
// sort<<<1, N/2>>>(a, N, 1);
// cudaDeviceSynchronize();
// }
entry_point(a, N);
hipProfilerStop();
int order = verify_in_order(a, N);
if (order == -1) {
std::cout << "array is in order" << '\n';
}
else {
std::cout << "not in order" << '\n';
print_array(a, N, order);
}
hipFree(a);
return 0;
}
// | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4sortPiiii
.globl _Z4sortPiiii
.p2align 8
.type _Z4sortPiiii,@function
_Z4sortPiiii:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s5, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s4
v_add_lshl_u32 v0, s15, v0, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s5, s3, v0
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_4
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v2, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
v_mov_b32_e32 v4, v2
global_store_b64 v[0:1], v[3:4], off
.LBB0_3:
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB0_4:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4sortPiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4sortPiiii, .Lfunc_end0-_Z4sortPiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4sortPiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4sortPiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <hip/hip_runtime.h>
// includes CUDA Runtime
#include <hip/hip_runtime_api.h>
/*
written by George Strauch on 4/21/2020
c++ program to sort an array with bubblesort on gpu
Execution syntax:
$ ./exec {int num of elements}
Example run:
$ nvcc gpu_bubble.cu -arch='sm_35' -rdc=true -lineinfo -lcudadevrt -o gpu_bs
$ time ./gpu_bs 10
$ time ./gpu_bs 20000
*/
__host__ // used for debug
void print_array (int *array, int n, int tag_index)
{
for (size_t i = 0; i < n; i++) {
if (i == tag_index+1) {
std::cout << " > ";
}
std::cout << array[i] << ' ';
}
std::cout << '\n';
}
__host__
int* allocate_shared_array(int n_elements)
{
int *a;
hipMallocManaged(&a, n_elements*sizeof(int));
return a;
}
__host__ // makes and returns unsorted array with random elements
int* make_unsorted_array(int n_elements)
{
int *a = allocate_shared_array(n_elements);
for (size_t j = 0; j < n_elements; j++) {
a[j] = rand()%(2*n_elements);
}
return a;
}
__host__
bool go_again(int* array, int n)
{
for (size_t i = 0; i < n-1; i++) {
if(array[i] > array[i+1])
{
return true;
}
}
return false;
}
__global__
void sort(int* array, int n, int offset, int k)
{
int id = 2*(blockIdx.x*blockDim.x + threadIdx.x) + offset + k;
if (id >= n) {
return;
}
int tmp;
if (array[id] > array[id+1]) {
tmp = array[id+1];
array[id+1] = array[id];
array[id] = tmp;
}
__syncthreads();
}
__host__
void fill_array(int* a, int n) {
for (size_t i = 0; i < n; i++) {
a[i] = 0;
}
}
__host__ // returns element index if any element larger than i+1 element, else -1
int verify_in_order(int* array, int n)
{
for (size_t i = 0; i < n-1; i++) {
if (array[i+1] < array[i]) {
return i;
}
}
return -1;
}
__host__
void entry_point(int* array, int n)
{
int t = 512;
int b = 512;
int count = 0;
int total = t*b;
dim3 threads(t);
dim3 blocks(b);
// fill_array(array, n);
while (go_again(array, n)) {
hipDeviceSynchronize();
for (size_t i = 0; i < (n/(2*total)) +1; i++) {
sort<<<blocks, threads>>>(array, n, 0, i*total);
hipDeviceSynchronize();
sort<<<blocks, threads>>>(array, n, 1, i*total);
}
hipDeviceSynchronize();
count++;
if (count > 1.5*n) {
break;
}
}
}
int main(int argc, char const *argv[])
{
int N = atoi(argv[1]);
std::cout << "N = " << N << '\n';
int* a = make_unsorted_array(N);
hipProfilerStart();
// while (go_again(a, N)) {
// sort<<<1, N/2>>>(a, N, 0);
// sort<<<1, N/2>>>(a, N, 1);
// cudaDeviceSynchronize();
// }
entry_point(a, N);
hipProfilerStop();
int order = verify_in_order(a, N);
if (order == -1) {
std::cout << "array is in order" << '\n';
}
else {
std::cout << "not in order" << '\n';
print_array(a, N, order);
}
hipFree(a);
return 0;
}
// | .text
.file "gpu_bubble.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z11print_arrayPiii # -- Begin function _Z11print_arrayPiii
.p2align 4, 0x90
.type _Z11print_arrayPiii,@function
_Z11print_arrayPiii: # @_Z11print_arrayPiii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
testl %esi, %esi
je .LBB0_6
# %bb.1: # %.lr.ph
movq %rdi, %rbx
movslq %esi, %r15
incl %edx
movslq %edx, %r12
xorl %r13d, %r13d
leaq 15(%rsp), %r14
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_10: # in Loop: Header=BB0_2 Depth=1
movq %rax, %rdi
movl $32, %esi
callq _ZNSo3putEc
.LBB0_11: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit8
# in Loop: Header=BB0_2 Depth=1
incq %r13
cmpq %r13, %r15
je .LBB0_6
.LBB0_2: # =>This Inner Loop Header: Depth=1
cmpq %r13, %r12
jne .LBB0_4
# %bb.3: # in Loop: Header=BB0_2 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB0_4: # in Loop: Header=BB0_2 Depth=1
movl (%rbx,%r13,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movb $32, 15(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB0_10
# %bb.5: # in Loop: Header=BB0_2 Depth=1
movl $1, %edx
movq %rax, %rdi
movq %r14, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_11
.LBB0_6: # %._crit_edge
movb $10, 14(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB0_8
# %bb.7:
leaq 14(%rsp), %rsi
movl $_ZSt4cout, %edi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_9
.LBB0_8:
movl $_ZSt4cout, %edi
movl $10, %esi
callq _ZNSo3putEc
.LBB0_9: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z11print_arrayPiii, .Lfunc_end0-_Z11print_arrayPiii
.cfi_endproc
# -- End function
.globl _Z21allocate_shared_arrayi # -- Begin function _Z21allocate_shared_arrayi
.p2align 4, 0x90
.type _Z21allocate_shared_arrayi,@function
_Z21allocate_shared_arrayi: # @_Z21allocate_shared_arrayi
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movslq %edi, %rsi
shlq $2, %rsi
movq %rsp, %rdi
movl $1, %edx
callq hipMallocManaged
movq (%rsp), %rax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z21allocate_shared_arrayi, .Lfunc_end1-_Z21allocate_shared_arrayi
.cfi_endproc
# -- End function
.globl _Z19make_unsorted_arrayi # -- Begin function _Z19make_unsorted_arrayi
.p2align 4, 0x90
.type _Z19make_unsorted_arrayi,@function
_Z19make_unsorted_arrayi: # @_Z19make_unsorted_arrayi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edi, %ebx
movslq %edi, %r15
leaq (,%r15,4), %rsi
movq %rsp, %rdi
movl $1, %edx
callq hipMallocManaged
movq (%rsp), %r14
testl %r15d, %r15d
je .LBB2_3
# %bb.1: # %.lr.ph
addl %ebx, %ebx
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_2: # =>This Inner Loop Header: Depth=1
callq rand
cltd
idivl %ebx
movl %edx, (%r14,%r12,4)
incq %r12
cmpq %r12, %r15
jne .LBB2_2
.LBB2_3: # %._crit_edge
movq %r14, %rax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z19make_unsorted_arrayi, .Lfunc_end2-_Z19make_unsorted_arrayi
.cfi_endproc
# -- End function
.globl _Z8go_againPii # -- Begin function _Z8go_againPii
.p2align 4, 0x90
.type _Z8go_againPii,@function
_Z8go_againPii: # @_Z8go_againPii
.cfi_startproc
# %bb.0:
decl %esi
movslq %esi, %rax
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movq %rdx, %rcx
cmpq %rdx, %rax
je .LBB3_3
# %bb.2: # in Loop: Header=BB3_1 Depth=1
movl (%rdi,%rcx,4), %esi
leaq 1(%rcx), %rdx
cmpl 4(%rdi,%rcx,4), %esi
jle .LBB3_1
.LBB3_3:
cmpq %rax, %rcx
setb %al
retq
.Lfunc_end3:
.size _Z8go_againPii, .Lfunc_end3-_Z8go_againPii
.cfi_endproc
# -- End function
.globl _Z19__device_stub__sortPiiii # -- Begin function _Z19__device_stub__sortPiiii
.p2align 4, 0x90
.type _Z19__device_stub__sortPiiii,@function
_Z19__device_stub__sortPiiii: # @_Z19__device_stub__sortPiiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4sortPiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z19__device_stub__sortPiiii, .Lfunc_end4-_Z19__device_stub__sortPiiii
.cfi_endproc
# -- End function
.globl _Z10fill_arrayPii # -- Begin function _Z10fill_arrayPii
.p2align 4, 0x90
.type _Z10fill_arrayPii,@function
_Z10fill_arrayPii: # @_Z10fill_arrayPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB5_1
# %bb.2: # %.lr.ph.preheader
movslq %esi, %rdx
shlq $2, %rdx
xorl %esi, %esi
jmp memset@PLT # TAILCALL
.LBB5_1: # %._crit_edge
retq
.Lfunc_end5:
.size _Z10fill_arrayPii, .Lfunc_end5-_Z10fill_arrayPii
.cfi_endproc
# -- End function
.globl _Z15verify_in_orderPii # -- Begin function _Z15verify_in_orderPii
.p2align 4, 0x90
.type _Z15verify_in_orderPii,@function
_Z15verify_in_orderPii: # @_Z15verify_in_orderPii
.cfi_startproc
# %bb.0:
decl %esi
movslq %esi, %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB6_1: # =>This Inner Loop Header: Depth=1
cmpq %rdx, %rcx
je .LBB6_2
# %bb.3: # in Loop: Header=BB6_1 Depth=1
leaq 1(%rdx), %rax
movl 4(%rdi,%rdx,4), %esi
cmpl (%rdi,%rdx,4), %esi
movq %rax, %rdx
jge .LBB6_1
# %bb.4:
decl %eax
# kill: def $eax killed $eax killed $rax
retq
.LBB6_2:
movl $-1, %eax
# kill: def $eax killed $eax killed $rax
retq
.Lfunc_end6:
.size _Z15verify_in_orderPii, .Lfunc_end6-_Z15verify_in_orderPii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z11entry_pointPii
.LCPI7_0:
.quad 0x3ff8000000000000 # double 1.5
.text
.globl _Z11entry_pointPii
.p2align 4, 0x90
.type _Z11entry_pointPii,@function
_Z11entry_pointPii: # @_Z11entry_pointPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebx
movq %rdi, %r14
movabsq $4294967808, %r15 # imm = 0x100000200
leal -1(%rbx), %eax
leal 524287(%rbx), %ecx
testl %esi, %esi
cmovnsl %esi, %ecx
cltq
movq %rax, 88(%rsp) # 8-byte Spill
sarl $19, %ecx
cvtsi2sd %esi, %xmm0
leal 1(%rcx), %eax
mulsd .LCPI7_0(%rip), %xmm0
movsd %xmm0, 136(%rsp) # 8-byte Spill
movl %eax, 84(%rsp) # 4-byte Spill
cmpl $1, %eax
adcl $1, %ecx
movslq %ecx, %rax
movq %rax, 128(%rsp) # 8-byte Spill
movslq %esi, %rax
movl $1, %ebp
subq %rax, %rbp
xorl %esi, %esi
jmp .LBB7_1
.p2align 4, 0x90
.LBB7_13: # %._crit_edge
# in Loop: Header=BB7_1 Depth=1
callq hipDeviceSynchronize
movq 144(%rsp), %rsi # 8-byte Reload
incl %esi
xorps %xmm0, %xmm0
cvtsi2sd %esi, %xmm0
ucomisd 136(%rsp), %xmm0 # 8-byte Folded Reload
ja .LBB7_14
.LBB7_1: # =>This Loop Header: Depth=1
# Child Loop BB7_2 Depth 2
# Child Loop BB7_8 Depth 2
movq $-1, %rax
.p2align 4, 0x90
.LBB7_2: # Parent Loop BB7_1 Depth=1
# => This Inner Loop Header: Depth=2
leaq (%rax,%rbp), %rcx
cmpq $-1, %rcx
je .LBB7_3
# %bb.4: # in Loop: Header=BB7_2 Depth=2
movl 4(%r14,%rax,4), %edx
leaq 1(%rax), %rcx
cmpl 8(%r14,%rax,4), %edx
movq %rcx, %rax
jle .LBB7_2
# %bb.5: # %_Z8go_againPii.exit
# in Loop: Header=BB7_1 Depth=1
cmpq 88(%rsp), %rcx # 8-byte Folded Reload
jb .LBB7_6
jmp .LBB7_14
.p2align 4, 0x90
.LBB7_3: # in Loop: Header=BB7_1 Depth=1
movq 88(%rsp), %rcx # 8-byte Reload
cmpq 88(%rsp), %rcx # 8-byte Folded Reload
jae .LBB7_14
.LBB7_6: # in Loop: Header=BB7_1 Depth=1
movq %rsi, 144(%rsp) # 8-byte Spill
callq hipDeviceSynchronize
cmpl $0, 84(%rsp) # 4-byte Folded Reload
je .LBB7_13
# %bb.7: # %.lr.ph.preheader
# in Loop: Header=BB7_1 Depth=1
xorl %r12d, %r12d
movq 128(%rsp), %r13 # 8-byte Reload
jmp .LBB7_8
.p2align 4, 0x90
.LBB7_12: # in Loop: Header=BB7_8 Depth=2
addl $262144, %r12d # imm = 0x40000
decq %r13
je .LBB7_13
.LBB7_8: # %.lr.ph
# Parent Loop BB7_1 Depth=1
# => This Inner Loop Header: Depth=2
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_10
# %bb.9: # in Loop: Header=BB7_8 Depth=2
movq %r14, 72(%rsp)
movl %ebx, 20(%rsp)
movl $0, 16(%rsp)
movl %r12d, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z4sortPiiii, %edi
leaq 96(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_10: # in Loop: Header=BB7_8 Depth=2
callq hipDeviceSynchronize
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_12
# %bb.11: # in Loop: Header=BB7_8 Depth=2
movq %r14, 72(%rsp)
movl %ebx, 20(%rsp)
movl $1, 16(%rsp)
movl %r12d, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z4sortPiiii, %edi
leaq 96(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB7_12
.LBB7_14:
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _Z11entry_pointPii, .Lfunc_end7-_Z11entry_pointPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movb $10, 5(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB8_2
# %bb.1:
leaq 5(%rsp), %rsi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB8_3
.LBB8_2:
movq %rax, %rdi
movl $10, %esi
callq _ZNSo3putEc
.LBB8_3: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
movslq %ebx, %r15
leaq (,%r15,4), %rsi
leaq 8(%rsp), %rdi
movl $1, %edx
callq hipMallocManaged
movq 8(%rsp), %r14
testl %ebx, %ebx
je .LBB8_6
# %bb.4: # %.lr.ph.i
leal (%rbx,%rbx), %ebp
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB8_5: # =>This Inner Loop Header: Depth=1
callq rand
cltd
idivl %ebp
movl %edx, (%r14,%r12,4)
incq %r12
cmpq %r12, %r15
jne .LBB8_5
.LBB8_6: # %_Z19make_unsorted_arrayi.exit
callq hipProfilerStart
movq %r14, %rdi
movl %ebx, %esi
callq _Z11entry_pointPii
callq hipProfilerStop
leal -1(%rbx), %eax
cltq
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB8_7: # =>This Inner Loop Header: Depth=1
cmpq %rcx, %rax
je .LBB8_8
# %bb.9: # in Loop: Header=BB8_7 Depth=1
leaq 1(%rcx), %r15
movl 4(%r14,%rcx,4), %edx
cmpl (%r14,%rcx,4), %edx
movq %r15, %rcx
jge .LBB8_7
# %bb.10:
decl %r15d
jmp .LBB8_11
.LBB8_8:
movl $-1, %r15d
.LBB8_11: # %_Z15verify_in_orderPii.exit
movl $_ZSt4cout, %edi
cmpl $-1, %r15d
je .LBB8_12
# %bb.15:
movl $.L.str.3, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movb $10, 7(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB8_17
# %bb.16:
leaq 7(%rsp), %rsi
movl $_ZSt4cout, %edi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB8_18
.LBB8_12:
movl $.L.str.2, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movb $10, 6(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB8_14
# %bb.13:
leaq 6(%rsp), %rsi
movl $_ZSt4cout, %edi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB8_19
.LBB8_17:
movl $_ZSt4cout, %edi
movl $10, %esi
callq _ZNSo3putEc
.LBB8_18: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit18
movq %r14, %rdi
movl %ebx, %esi
movl %r15d, %edx
callq _Z11print_arrayPiii
.LBB8_19:
movq %r14, %rdi
callq hipFree
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB8_14:
.cfi_def_cfa_offset 64
movl $_ZSt4cout, %edi
movl $10, %esi
callq _ZNSo3putEc
jmp .LBB8_19
.Lfunc_end8:
.size main, .Lfunc_end8-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB9_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB9_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4sortPiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end9:
.size __hip_module_ctor, .Lfunc_end9-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB10_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB10_2:
retq
.Lfunc_end10:
.size __hip_module_dtor, .Lfunc_end10-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " > "
.size .L.str, 4
.type _Z4sortPiiii,@object # @_Z4sortPiiii
.section .rodata,"a",@progbits
.globl _Z4sortPiiii
.p2align 3, 0x0
_Z4sortPiiii:
.quad _Z19__device_stub__sortPiiii
.size _Z4sortPiiii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "N = "
.size .L.str.1, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "array is in order"
.size .L.str.2, 18
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "not in order"
.size .L.str.3, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4sortPiiii"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__sortPiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _Z4sortPiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4sortPiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ LEA R0, R0, c[0x0][0x16c], 0x1 ; /* 0x00005b0000007a11 */
/* 0x000fc800078e08ff */
/*0050*/ IADD3 R0, R0, c[0x0][0x170], RZ ; /* 0x00005c0000007a10 */
/* 0x000fc80007ffe0ff */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00b0*/ LDG.E R5, [R2.64+0x4] ; /* 0x0000040402057981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00d0*/ ISETP.GT.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x004fda0003f04270 */
/*00e0*/ @P0 STG.E [R2.64+0x4], R0 ; /* 0x0000040002000986 */
/* 0x000fe8000c101904 */
/*00f0*/ @P0 STG.E [R2.64], R5 ; /* 0x0000000502000986 */
/* 0x000fe8000c101904 */
/*0100*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4sortPiiii
.globl _Z4sortPiiii
.p2align 8
.type _Z4sortPiiii,@function
_Z4sortPiiii:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x8
s_load_b32 s5, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s4
v_add_lshl_u32 v0, s15, v0, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s5, s3, v0
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_4
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v2, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
v_mov_b32_e32 v4, v2
global_store_b64 v[0:1], v[3:4], off
.LBB0_3:
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB0_4:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4sortPiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4sortPiiii, .Lfunc_end0-_Z4sortPiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4sortPiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4sortPiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001aed6d_00000000-6_gpu_bubble.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3679:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3679:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " > "
.text
.globl _Z11print_arrayPiii
.type _Z11print_arrayPiii, @function
_Z11print_arrayPiii:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
testl %esi, %esi
je .L4
movq %rdi, %r12
movslq %esi, %r14
movl $0, %ebx
addl $1, %edx
movslq %edx, %rbp
leaq _ZSt4cout(%rip), %r13
leaq 7(%rsp), %r15
jmp .L8
.L14:
movl $3, %edx
leaq .LC0(%rip), %rsi
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L5
.L6:
movl $32, %esi
call _ZNSo3putEc@PLT
.L7:
addq $1, %rbx
cmpq %r14, %rbx
je .L4
.L8:
cmpq %rbx, %rbp
je .L14
.L5:
movl (%r12,%rbx,4), %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movb $32, 7(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .L6
movl $1, %edx
movq %r15, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L7
.L4:
movb $10, 7(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
cmpq $0, 16(%rdx,%rax)
je .L9
leaq 7(%rsp), %rsi
movl $1, %edx
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L3:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L15
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
movl $10, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
jmp .L3
.L15:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z11print_arrayPiii, .-_Z11print_arrayPiii
.globl _Z21allocate_shared_arrayi
.type _Z21allocate_shared_arrayi, @function
_Z21allocate_shared_arrayi:
.LFB3670:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movslq %edi, %rsi
salq $2, %rsi
movq %rsp, %rdi
movl $1, %edx
call cudaMallocManaged@PLT
movq (%rsp), %rax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L19
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size _Z21allocate_shared_arrayi, .-_Z21allocate_shared_arrayi
.globl _Z19make_unsorted_arrayi
.type _Z19make_unsorted_arrayi, @function
_Z19make_unsorted_arrayi:
.LFB3671:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebp
call _Z21allocate_shared_arrayi
movq %rax, %r12
testl %ebp, %ebp
je .L20
movslq %ebp, %r13
addl %ebp, %ebp
movl $0, %ebx
.L22:
call rand@PLT
cltd
idivl %ebp
movl %edx, (%r12,%rbx,4)
addq $1, %rbx
cmpq %r13, %rbx
jne .L22
.L20:
movq %r12, %rax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3671:
.size _Z19make_unsorted_arrayi, .-_Z19make_unsorted_arrayi
.globl _Z8go_againPii
.type _Z8go_againPii, @function
_Z8go_againPii:
.LFB3672:
.cfi_startproc
endbr64
movslq %esi, %rsi
subq $1, %rsi
movl $0, %eax
.L26:
cmpq %rsi, %rax
je .L30
movl (%rdi,%rax,4), %edx
addq $1, %rax
cmpl (%rdi,%rax,4), %edx
jle .L26
movl $1, %eax
ret
.L30:
movl $0, %eax
ret
.cfi_endproc
.LFE3672:
.size _Z8go_againPii, .-_Z8go_againPii
.globl _Z10fill_arrayPii
.type _Z10fill_arrayPii, @function
_Z10fill_arrayPii:
.LFB3673:
.cfi_startproc
endbr64
movslq %esi, %rdx
testl %esi, %esi
je .L31
movq %rdi, %rax
leaq (%rdi,%rdx,4), %rdx
.L33:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L33
.L31:
ret
.cfi_endproc
.LFE3673:
.size _Z10fill_arrayPii, .-_Z10fill_arrayPii
.globl _Z15verify_in_orderPii
.type _Z15verify_in_orderPii, @function
_Z15verify_in_orderPii:
.LFB3674:
.cfi_startproc
endbr64
movslq %esi, %rsi
subq $1, %rsi
movl $0, %eax
.L36:
cmpq %rsi, %rax
je .L40
leaq 1(%rax), %rdx
movl (%rdi,%rax,4), %ecx
cmpl %ecx, 4(%rdi,%rax,4)
jl .L35
movq %rdx, %rax
jmp .L36
.L40:
movl $-1, %eax
.L35:
ret
.cfi_endproc
.LFE3674:
.size _Z15verify_in_orderPii, .-_Z15verify_in_orderPii
.globl _Z26__device_stub__Z4sortPiiiiPiiii
.type _Z26__device_stub__Z4sortPiiiiPiiii, @function
_Z26__device_stub__Z4sortPiiiiPiiii:
.LFB3701:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4sortPiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3701:
.size _Z26__device_stub__Z4sortPiiiiPiiii, .-_Z26__device_stub__Z4sortPiiiiPiiii
.globl _Z4sortPiiii
.type _Z4sortPiiii, @function
_Z4sortPiiii:
.LFB3702:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z4sortPiiiiPiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _Z4sortPiiii, .-_Z4sortPiiii
.globl _Z11entry_pointPii
.type _Z11entry_pointPii, @function
_Z11entry_pointPii:
.LFB3675:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r13
movl %esi, %r12d
movl $512, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
leal 524287(%rsi), %ebp
testl %esi, %esi
cmovns %esi, %ebp
sarl $19, %ebp
addl $1, %ebp
movslq %ebp, %rbp
movl $0, %r14d
jmp .L50
.L59:
movl %ebx, %ecx
sall $18, %ecx
movl $0, %edx
movl %r12d, %esi
movq %r13, %rdi
call _Z26__device_stub__Z4sortPiiiiPiiii
jmp .L52
.L53:
addq $1, %rbx
cmpq %rbp, %rbx
jnb .L51
.L54:
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl 28(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L59
.L52:
call cudaDeviceSynchronize@PLT
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl 28(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L53
movl %ebx, %ecx
sall $18, %ecx
movl $1, %edx
movl %r12d, %esi
movq %r13, %rdi
call _Z26__device_stub__Z4sortPiiiiPiiii
jmp .L53
.L51:
call cudaDeviceSynchronize@PLT
addl $1, %r14d
pxor %xmm1, %xmm1
cvtsi2sdl %r14d, %xmm1
pxor %xmm0, %xmm0
cvtsi2sdl %r12d, %xmm0
mulsd .LC1(%rip), %xmm0
comisd %xmm0, %xmm1
ja .L49
.L50:
movl %r12d, %esi
movq %r13, %rdi
call _Z8go_againPii
testb %al, %al
je .L49
call cudaDeviceSynchronize@PLT
leal 1048575(%r12), %eax
cmpl $524287, %eax
jbe .L51
movl $0, %ebx
jmp .L54
.L49:
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _Z11entry_pointPii, .-_Z11entry_pointPii
.section .rodata.str1.1
.LC2:
.string "N = "
.LC3:
.string "array is in order"
.LC4:
.string "not in order"
.text
.globl main
.type main, @function
main:
.LFB3676:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movl %ebx, %edi
call _Z19make_unsorted_arrayi
movq %rax, %rbp
call cudaProfilerStart@PLT
movl %ebx, %esi
movq %rbp, %rdi
call _Z11entry_pointPii
call cudaProfilerStop@PLT
movl %ebx, %esi
movq %rbp, %rdi
call _Z15verify_in_orderPii
cmpl $-1, %eax
je .L64
movl %eax, %r12d
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movl %r12d, %edx
movl %ebx, %esi
movq %rbp, %rdi
call _Z11print_arrayPiii
.L62:
movq %rbp, %rdi
call cudaFree@PLT
movl $0, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L64:
.cfi_restore_state
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
jmp .L62
.cfi_endproc
.LFE3676:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z4sortPiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3704:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z4sortPiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3704:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1073217536
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpu_bubble.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z11print_arrayPiii # -- Begin function _Z11print_arrayPiii
.p2align 4, 0x90
.type _Z11print_arrayPiii,@function
_Z11print_arrayPiii: # @_Z11print_arrayPiii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
testl %esi, %esi
je .LBB0_6
# %bb.1: # %.lr.ph
movq %rdi, %rbx
movslq %esi, %r15
incl %edx
movslq %edx, %r12
xorl %r13d, %r13d
leaq 15(%rsp), %r14
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_10: # in Loop: Header=BB0_2 Depth=1
movq %rax, %rdi
movl $32, %esi
callq _ZNSo3putEc
.LBB0_11: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit8
# in Loop: Header=BB0_2 Depth=1
incq %r13
cmpq %r13, %r15
je .LBB0_6
.LBB0_2: # =>This Inner Loop Header: Depth=1
cmpq %r13, %r12
jne .LBB0_4
# %bb.3: # in Loop: Header=BB0_2 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB0_4: # in Loop: Header=BB0_2 Depth=1
movl (%rbx,%r13,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movb $32, 15(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB0_10
# %bb.5: # in Loop: Header=BB0_2 Depth=1
movl $1, %edx
movq %rax, %rdi
movq %r14, %rsi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_11
.LBB0_6: # %._crit_edge
movb $10, 14(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB0_8
# %bb.7:
leaq 14(%rsp), %rsi
movl $_ZSt4cout, %edi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB0_9
.LBB0_8:
movl $_ZSt4cout, %edi
movl $10, %esi
callq _ZNSo3putEc
.LBB0_9: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z11print_arrayPiii, .Lfunc_end0-_Z11print_arrayPiii
.cfi_endproc
# -- End function
.globl _Z21allocate_shared_arrayi # -- Begin function _Z21allocate_shared_arrayi
.p2align 4, 0x90
.type _Z21allocate_shared_arrayi,@function
_Z21allocate_shared_arrayi: # @_Z21allocate_shared_arrayi
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movslq %edi, %rsi
shlq $2, %rsi
movq %rsp, %rdi
movl $1, %edx
callq hipMallocManaged
movq (%rsp), %rax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z21allocate_shared_arrayi, .Lfunc_end1-_Z21allocate_shared_arrayi
.cfi_endproc
# -- End function
.globl _Z19make_unsorted_arrayi # -- Begin function _Z19make_unsorted_arrayi
.p2align 4, 0x90
.type _Z19make_unsorted_arrayi,@function
_Z19make_unsorted_arrayi: # @_Z19make_unsorted_arrayi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edi, %ebx
movslq %edi, %r15
leaq (,%r15,4), %rsi
movq %rsp, %rdi
movl $1, %edx
callq hipMallocManaged
movq (%rsp), %r14
testl %r15d, %r15d
je .LBB2_3
# %bb.1: # %.lr.ph
addl %ebx, %ebx
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_2: # =>This Inner Loop Header: Depth=1
callq rand
cltd
idivl %ebx
movl %edx, (%r14,%r12,4)
incq %r12
cmpq %r12, %r15
jne .LBB2_2
.LBB2_3: # %._crit_edge
movq %r14, %rax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z19make_unsorted_arrayi, .Lfunc_end2-_Z19make_unsorted_arrayi
.cfi_endproc
# -- End function
.globl _Z8go_againPii # -- Begin function _Z8go_againPii
.p2align 4, 0x90
.type _Z8go_againPii,@function
_Z8go_againPii: # @_Z8go_againPii
.cfi_startproc
# %bb.0:
decl %esi
movslq %esi, %rax
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movq %rdx, %rcx
cmpq %rdx, %rax
je .LBB3_3
# %bb.2: # in Loop: Header=BB3_1 Depth=1
movl (%rdi,%rcx,4), %esi
leaq 1(%rcx), %rdx
cmpl 4(%rdi,%rcx,4), %esi
jle .LBB3_1
.LBB3_3:
cmpq %rax, %rcx
setb %al
retq
.Lfunc_end3:
.size _Z8go_againPii, .Lfunc_end3-_Z8go_againPii
.cfi_endproc
# -- End function
.globl _Z19__device_stub__sortPiiii # -- Begin function _Z19__device_stub__sortPiiii
.p2align 4, 0x90
.type _Z19__device_stub__sortPiiii,@function
_Z19__device_stub__sortPiiii: # @_Z19__device_stub__sortPiiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4sortPiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z19__device_stub__sortPiiii, .Lfunc_end4-_Z19__device_stub__sortPiiii
.cfi_endproc
# -- End function
.globl _Z10fill_arrayPii # -- Begin function _Z10fill_arrayPii
.p2align 4, 0x90
.type _Z10fill_arrayPii,@function
_Z10fill_arrayPii: # @_Z10fill_arrayPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB5_1
# %bb.2: # %.lr.ph.preheader
movslq %esi, %rdx
shlq $2, %rdx
xorl %esi, %esi
jmp memset@PLT # TAILCALL
.LBB5_1: # %._crit_edge
retq
.Lfunc_end5:
.size _Z10fill_arrayPii, .Lfunc_end5-_Z10fill_arrayPii
.cfi_endproc
# -- End function
.globl _Z15verify_in_orderPii # -- Begin function _Z15verify_in_orderPii
.p2align 4, 0x90
.type _Z15verify_in_orderPii,@function
_Z15verify_in_orderPii: # @_Z15verify_in_orderPii
.cfi_startproc
# %bb.0:
decl %esi
movslq %esi, %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB6_1: # =>This Inner Loop Header: Depth=1
cmpq %rdx, %rcx
je .LBB6_2
# %bb.3: # in Loop: Header=BB6_1 Depth=1
leaq 1(%rdx), %rax
movl 4(%rdi,%rdx,4), %esi
cmpl (%rdi,%rdx,4), %esi
movq %rax, %rdx
jge .LBB6_1
# %bb.4:
decl %eax
# kill: def $eax killed $eax killed $rax
retq
.LBB6_2:
movl $-1, %eax
# kill: def $eax killed $eax killed $rax
retq
.Lfunc_end6:
.size _Z15verify_in_orderPii, .Lfunc_end6-_Z15verify_in_orderPii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z11entry_pointPii
.LCPI7_0:
.quad 0x3ff8000000000000 # double 1.5
.text
.globl _Z11entry_pointPii
.p2align 4, 0x90
.type _Z11entry_pointPii,@function
_Z11entry_pointPii: # @_Z11entry_pointPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebx
movq %rdi, %r14
movabsq $4294967808, %r15 # imm = 0x100000200
leal -1(%rbx), %eax
leal 524287(%rbx), %ecx
testl %esi, %esi
cmovnsl %esi, %ecx
cltq
movq %rax, 88(%rsp) # 8-byte Spill
sarl $19, %ecx
cvtsi2sd %esi, %xmm0
leal 1(%rcx), %eax
mulsd .LCPI7_0(%rip), %xmm0
movsd %xmm0, 136(%rsp) # 8-byte Spill
movl %eax, 84(%rsp) # 4-byte Spill
cmpl $1, %eax
adcl $1, %ecx
movslq %ecx, %rax
movq %rax, 128(%rsp) # 8-byte Spill
movslq %esi, %rax
movl $1, %ebp
subq %rax, %rbp
xorl %esi, %esi
jmp .LBB7_1
.p2align 4, 0x90
.LBB7_13: # %._crit_edge
# in Loop: Header=BB7_1 Depth=1
callq hipDeviceSynchronize
movq 144(%rsp), %rsi # 8-byte Reload
incl %esi
xorps %xmm0, %xmm0
cvtsi2sd %esi, %xmm0
ucomisd 136(%rsp), %xmm0 # 8-byte Folded Reload
ja .LBB7_14
.LBB7_1: # =>This Loop Header: Depth=1
# Child Loop BB7_2 Depth 2
# Child Loop BB7_8 Depth 2
movq $-1, %rax
.p2align 4, 0x90
.LBB7_2: # Parent Loop BB7_1 Depth=1
# => This Inner Loop Header: Depth=2
leaq (%rax,%rbp), %rcx
cmpq $-1, %rcx
je .LBB7_3
# %bb.4: # in Loop: Header=BB7_2 Depth=2
movl 4(%r14,%rax,4), %edx
leaq 1(%rax), %rcx
cmpl 8(%r14,%rax,4), %edx
movq %rcx, %rax
jle .LBB7_2
# %bb.5: # %_Z8go_againPii.exit
# in Loop: Header=BB7_1 Depth=1
cmpq 88(%rsp), %rcx # 8-byte Folded Reload
jb .LBB7_6
jmp .LBB7_14
.p2align 4, 0x90
.LBB7_3: # in Loop: Header=BB7_1 Depth=1
movq 88(%rsp), %rcx # 8-byte Reload
cmpq 88(%rsp), %rcx # 8-byte Folded Reload
jae .LBB7_14
.LBB7_6: # in Loop: Header=BB7_1 Depth=1
movq %rsi, 144(%rsp) # 8-byte Spill
callq hipDeviceSynchronize
cmpl $0, 84(%rsp) # 4-byte Folded Reload
je .LBB7_13
# %bb.7: # %.lr.ph.preheader
# in Loop: Header=BB7_1 Depth=1
xorl %r12d, %r12d
movq 128(%rsp), %r13 # 8-byte Reload
jmp .LBB7_8
.p2align 4, 0x90
.LBB7_12: # in Loop: Header=BB7_8 Depth=2
addl $262144, %r12d # imm = 0x40000
decq %r13
je .LBB7_13
.LBB7_8: # %.lr.ph
# Parent Loop BB7_1 Depth=1
# => This Inner Loop Header: Depth=2
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_10
# %bb.9: # in Loop: Header=BB7_8 Depth=2
movq %r14, 72(%rsp)
movl %ebx, 20(%rsp)
movl $0, 16(%rsp)
movl %r12d, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z4sortPiiii, %edi
leaq 96(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_10: # in Loop: Header=BB7_8 Depth=2
callq hipDeviceSynchronize
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_12
# %bb.11: # in Loop: Header=BB7_8 Depth=2
movq %r14, 72(%rsp)
movl %ebx, 20(%rsp)
movl $1, 16(%rsp)
movl %r12d, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z4sortPiiii, %edi
leaq 96(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB7_12
.LBB7_14:
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _Z11entry_pointPii, .Lfunc_end7-_Z11entry_pointPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movb $10, 5(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB8_2
# %bb.1:
leaq 5(%rsp), %rsi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB8_3
.LBB8_2:
movq %rax, %rdi
movl $10, %esi
callq _ZNSo3putEc
.LBB8_3: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
movslq %ebx, %r15
leaq (,%r15,4), %rsi
leaq 8(%rsp), %rdi
movl $1, %edx
callq hipMallocManaged
movq 8(%rsp), %r14
testl %ebx, %ebx
je .LBB8_6
# %bb.4: # %.lr.ph.i
leal (%rbx,%rbx), %ebp
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB8_5: # =>This Inner Loop Header: Depth=1
callq rand
cltd
idivl %ebp
movl %edx, (%r14,%r12,4)
incq %r12
cmpq %r12, %r15
jne .LBB8_5
.LBB8_6: # %_Z19make_unsorted_arrayi.exit
callq hipProfilerStart
movq %r14, %rdi
movl %ebx, %esi
callq _Z11entry_pointPii
callq hipProfilerStop
leal -1(%rbx), %eax
cltq
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB8_7: # =>This Inner Loop Header: Depth=1
cmpq %rcx, %rax
je .LBB8_8
# %bb.9: # in Loop: Header=BB8_7 Depth=1
leaq 1(%rcx), %r15
movl 4(%r14,%rcx,4), %edx
cmpl (%r14,%rcx,4), %edx
movq %r15, %rcx
jge .LBB8_7
# %bb.10:
decl %r15d
jmp .LBB8_11
.LBB8_8:
movl $-1, %r15d
.LBB8_11: # %_Z15verify_in_orderPii.exit
movl $_ZSt4cout, %edi
cmpl $-1, %r15d
je .LBB8_12
# %bb.15:
movl $.L.str.3, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movb $10, 7(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB8_17
# %bb.16:
leaq 7(%rsp), %rsi
movl $_ZSt4cout, %edi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB8_18
.LBB8_12:
movl $.L.str.2, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movb $10, 6(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB8_14
# %bb.13:
leaq 6(%rsp), %rsi
movl $_ZSt4cout, %edi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB8_19
.LBB8_17:
movl $_ZSt4cout, %edi
movl $10, %esi
callq _ZNSo3putEc
.LBB8_18: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit18
movq %r14, %rdi
movl %ebx, %esi
movl %r15d, %edx
callq _Z11print_arrayPiii
.LBB8_19:
movq %r14, %rdi
callq hipFree
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB8_14:
.cfi_def_cfa_offset 64
movl $_ZSt4cout, %edi
movl $10, %esi
callq _ZNSo3putEc
jmp .LBB8_19
.Lfunc_end8:
.size main, .Lfunc_end8-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB9_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB9_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4sortPiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end9:
.size __hip_module_ctor, .Lfunc_end9-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB10_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB10_2:
retq
.Lfunc_end10:
.size __hip_module_dtor, .Lfunc_end10-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " > "
.size .L.str, 4
.type _Z4sortPiiii,@object # @_Z4sortPiiii
.section .rodata,"a",@progbits
.globl _Z4sortPiiii
.p2align 3, 0x0
_Z4sortPiiii:
.quad _Z19__device_stub__sortPiiii
.size _Z4sortPiiii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "N = "
.size .L.str.1, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "array is in order"
.size .L.str.2, 18
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "not in order"
.size .L.str.3, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4sortPiiii"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__sortPiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _Z4sortPiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/**
* C file for parallel QR factorization program usign CUDA
* See header for more infos.
*
* 2016 Marco Tieghi - marco01.tieghi@student.unife.it
*
*/
#define THREADS_PER_BLOCK 512 //I'll use 512 threads for each block (as required in the assignment)
__global__ void r1_update(double *A, int m, int n, int lda, double *col, int ldc, double *row) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
//A(:,ii+1:n−1)=A(:,ii+1:n−1)−A(:,ii)*R(ii,ii+1:n−1)
if (idx < m && idy < m) {
for (int ii=0; ii < n-1; ii++) {
A[idx*lda + ii+1] = A[idx*lda + ii+1] - col[idy*ldc] * row[ii+1];
}
}
} | code for sm_80
Function : _Z9r1_updatePdiiiS_iS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff097624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R2, R2, c[0x0][0x4], R5 ; /* 0x0000010002027a24 */
/* 0x001fca00078e0205 */
/*0070*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fe20003f06270 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*0090*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x168], P0 ; /* 0x00005a0000007a0c */
/* 0x000fc80000706670 */
/*00a0*/ ISETP.LT.OR P0, PT, R9, 0x2, P0 ; /* 0x000000020900780c */
/* 0x000fda0000701670 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R3, R9.reuse, -0x2, RZ ; /* 0xfffffffe09037810 */
/* 0x040fe20007ffe0ff */
/*00d0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x8 ; /* 0x00000008ff087424 */
/* 0x000fe200078e00ff */
/*00e0*/ IADD3 R9, R9, -0x1, RZ ; /* 0xffffffff09097810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD R5, R2, c[0x0][0x180], RZ ; /* 0x0000600002057a24 */
/* 0x000fe200078e02ff */
/*0100*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe20003f06070 */
/*0110*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0120*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*0130*/ LOP3.LUT R9, R9, 0x3, RZ, 0xc0, !PT ; /* 0x0000000309097812 */
/* 0x000fe200078ec0ff */
/*0140*/ IMAD.WIDE R4, R5, R8, c[0x0][0x178] ; /* 0x00005e0005047625 */
/* 0x000fd200078e0208 */
/*0150*/ @!P0 BRA 0xd60 ; /* 0x00000c0000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R10, -R9, c[0x0][0x16c], RZ ; /* 0x00005b00090a7a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff037624 */
/* 0x000fe400078e00ff */
/*0180*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*0190*/ ISETP.GT.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fe20003f04270 */
/*01a0*/ IMAD R3, R0, R3, 0x1 ; /* 0x0000000100037424 */
/* 0x000fe400078e0203 */
/*01b0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff067624 */
/* 0x000fe400078e00ff */
/*01c0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff077624 */
/* 0x000fe400078e00ff */
/*01d0*/ IMAD.WIDE R2, R3, R8, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e0208 */
/*01e0*/ @!P0 BRA 0xb60 ; /* 0x0000097000008947 */
/* 0x000fea0003800000 */
/*01f0*/ IADD3 R12, R10, -0x1, RZ ; /* 0xffffffff0a0c7810 */
/* 0x000fe40007ffe0ff */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0210*/ ISETP.GT.AND P1, PT, R12, 0xc, PT ; /* 0x0000000c0c00780c */
/* 0x000fda0003f24270 */
/*0220*/ @!P1 BRA 0x800 ; /* 0x000005d000009947 */
/* 0x000fea0003800000 */
/*0230*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0240*/ LDG.E.64 R12, [R6.64+0x8] ; /* 0x00000804060c7981 */
/* 0x000ea8000c1e1b00 */
/*0250*/ LDG.E.64 R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea8000c1e1b00 */
/*0260*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea8000c1e1b00 */
/*0270*/ LDG.E.64 R18, [R2.64+0x8] ; /* 0x0000080402127981 */
/* 0x000ee8000c1e1b00 */
/*0280*/ LDG.E.64 R20, [R2.64+0x10] ; /* 0x0000100402147981 */
/* 0x000f22000c1e1b00 */
/*0290*/ DFMA R12, R12, -R14, R16 ; /* 0x8000000e0c0c722b */
/* 0x004e0e0000000010 */
/*02a0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*02b0*/ LDG.E.64 R14, [R6.64+0x10] ; /* 0x00001004060e7981 */
/* 0x000ee8000c1e1b00 */
/*02c0*/ LDG.E.64 R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000ee4000c1e1b00 */
/*02d0*/ DFMA R14, R14, -R16, R18 ; /* 0x800000100e0e722b */
/* 0x008e4e0000000012 */
/*02e0*/ STG.E.64 [R2.64+0x8], R14 ; /* 0x0000080e02007986 */
/* 0x0023e8000c101b04 */
/*02f0*/ LDG.E.64 R16, [R6.64+0x18] ; /* 0x0000180406107981 */
/* 0x000f28000c1e1b00 */
/*0300*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000f24000c1e1b00 */
/*0310*/ DFMA R16, R16, -R18, R20 ; /* 0x800000121010722b */
/* 0x0104c40000000014 */
/*0320*/ LDG.E.64 R20, [R2.64+0x18] ; /* 0x0000180402147981 */
/* 0x004eaa000c1e1b00 */
/*0330*/ STG.E.64 [R2.64+0x10], R16 ; /* 0x0000101002007986 */
/* 0x0087e8000c101b04 */
/*0340*/ LDG.E.64 R12, [R6.64+0x20] ; /* 0x00002004060c7981 */
/* 0x001ea8000c1e1b00 */
/*0350*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000ea4000c1e1b00 */
/*0360*/ DFMA R12, R12, -R18, R20 ; /* 0x800000120c0c722b */
/* 0x0040840000000014 */
/*0370*/ LDG.E.64 R20, [R2.64+0x20] ; /* 0x0000200402147981 */
/* 0x001f2a000c1e1b00 */
/*0380*/ STG.E.64 [R2.64+0x18], R12 ; /* 0x0000180c02007986 */
/* 0x0041e8000c101b04 */
/*0390*/ LDG.E.64 R14, [R6.64+0x28] ; /* 0x00002804060e7981 */
/* 0x002f28000c1e1b00 */
/*03a0*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000f24000c1e1b00 */
/*03b0*/ DFMA R14, R14, -R18, R20 ; /* 0x800000120e0e722b */
/* 0x0102840000000014 */
/*03c0*/ LDG.E.64 R20, [R2.64+0x28] ; /* 0x0000280402147981 */
/* 0x002f2a000c1e1b00 */
/*03d0*/ STG.E.64 [R2.64+0x20], R14 ; /* 0x0000200e02007986 */
/* 0x0043e8000c101b04 */
/*03e0*/ LDG.E.64 R16, [R6.64+0x30] ; /* 0x0000300406107981 */
/* 0x008f28000c1e1b00 */
/*03f0*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000f24000c1e1b00 */
/*0400*/ DFMA R16, R16, -R18, R20 ; /* 0x800000121010722b */
/* 0x0104c40000000014 */
/*0410*/ LDG.E.64 R20, [R2.64+0x30] ; /* 0x0000300402147981 */
/* 0x004eaa000c1e1b00 */
/*0420*/ STG.E.64 [R2.64+0x28], R16 ; /* 0x0000281002007986 */
/* 0x0087e8000c101b04 */
/*0430*/ LDG.E.64 R12, [R6.64+0x38] ; /* 0x00003804060c7981 */
/* 0x001ea8000c1e1b00 */
/*0440*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000ea4000c1e1b00 */
/*0450*/ DFMA R12, R12, -R18, R20 ; /* 0x800000120c0c722b */
/* 0x0040840000000014 */
/*0460*/ LDG.E.64 R20, [R2.64+0x38] ; /* 0x0000380402147981 */
/* 0x001f2a000c1e1b00 */
/*0470*/ STG.E.64 [R2.64+0x30], R12 ; /* 0x0000300c02007986 */
/* 0x0041e8000c101b04 */
/*0480*/ LDG.E.64 R14, [R6.64+0x40] ; /* 0x00004004060e7981 */
/* 0x002f28000c1e1b00 */
/*0490*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000f24000c1e1b00 */
/*04a0*/ DFMA R14, R14, -R18, R20 ; /* 0x800000120e0e722b */
/* 0x0102840000000014 */
/*04b0*/ LDG.E.64 R20, [R2.64+0x40] ; /* 0x0000400402147981 */
/* 0x002f2a000c1e1b00 */
/*04c0*/ STG.E.64 [R2.64+0x38], R14 ; /* 0x0000380e02007986 */
/* 0x0043e8000c101b04 */
/*04d0*/ LDG.E.64 R16, [R6.64+0x48] ; /* 0x0000480406107981 */
/* 0x008f28000c1e1b00 */
/*04e0*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000f24000c1e1b00 */
/*04f0*/ DFMA R16, R16, -R18, R20 ; /* 0x800000121010722b */
/* 0x0104c40000000014 */
/*0500*/ LDG.E.64 R20, [R2.64+0x48] ; /* 0x0000480402147981 */
/* 0x004eaa000c1e1b00 */
/*0510*/ STG.E.64 [R2.64+0x40], R16 ; /* 0x0000401002007986 */
/* 0x0087e8000c101b04 */
/*0520*/ LDG.E.64 R12, [R6.64+0x50] ; /* 0x00005004060c7981 */
/* 0x001ea8000c1e1b00 */
/*0530*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000ea4000c1e1b00 */
/*0540*/ DFMA R12, R12, -R18, R20 ; /* 0x800000120c0c722b */
/* 0x0040840000000014 */
/*0550*/ LDG.E.64 R20, [R2.64+0x50] ; /* 0x0000500402147981 */
/* 0x001f2a000c1e1b00 */
/*0560*/ STG.E.64 [R2.64+0x48], R12 ; /* 0x0000480c02007986 */
/* 0x0041e8000c101b04 */
/*0570*/ LDG.E.64 R14, [R6.64+0x58] ; /* 0x00005804060e7981 */
/* 0x002f28000c1e1b00 */
/*0580*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000f24000c1e1b00 */
/*0590*/ DFMA R14, R14, -R18, R20 ; /* 0x800000120e0e722b */
/* 0x0102840000000014 */
/*05a0*/ LDG.E.64 R20, [R2.64+0x58] ; /* 0x0000580402147981 */
/* 0x002f2a000c1e1b00 */
/*05b0*/ STG.E.64 [R2.64+0x50], R14 ; /* 0x0000500e02007986 */
/* 0x0043e8000c101b04 */
/*05c0*/ LDG.E.64 R16, [R6.64+0x60] ; /* 0x0000600406107981 */
/* 0x008f28000c1e1b00 */
/*05d0*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000f24000c1e1b00 */
/*05e0*/ DFMA R16, R16, -R18, R20 ; /* 0x800000121010722b */
/* 0x0104c40000000014 */
/*05f0*/ LDG.E.64 R20, [R2.64+0x60] ; /* 0x0000600402147981 */
/* 0x004eaa000c1e1b00 */
/*0600*/ STG.E.64 [R2.64+0x58], R16 ; /* 0x0000581002007986 */
/* 0x0087e8000c101b04 */
/*0610*/ LDG.E.64 R12, [R6.64+0x68] ; /* 0x00006804060c7981 */
/* 0x001ea8000c1e1b00 */
/*0620*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000ea4000c1e1b00 */
/*0630*/ DFMA R12, R12, -R18, R20 ; /* 0x800000120c0c722b */
/* 0x0040840000000014 */
/*0640*/ LDG.E.64 R20, [R2.64+0x68] ; /* 0x0000680402147981 */
/* 0x001f2a000c1e1b00 */
/*0650*/ STG.E.64 [R2.64+0x60], R12 ; /* 0x0000600c02007986 */
/* 0x0041e8000c101b04 */
/*0660*/ LDG.E.64 R14, [R6.64+0x70] ; /* 0x00007004060e7981 */
/* 0x002f28000c1e1b00 */
/*0670*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000f24000c1e1b00 */
/*0680*/ DFMA R14, R14, -R18, R20 ; /* 0x800000120e0e722b */
/* 0x0102840000000014 */
/*0690*/ LDG.E.64 R20, [R2.64+0x70] ; /* 0x0000700402147981 */
/* 0x002f2a000c1e1b00 */
/*06a0*/ STG.E.64 [R2.64+0x68], R14 ; /* 0x0000680e02007986 */
/* 0x0043e8000c101b04 */
/*06b0*/ LDG.E.64 R16, [R6.64+0x78] ; /* 0x0000780406107981 */
/* 0x008f28000c1e1b00 */
/*06c0*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000f22000c1e1b00 */
/*06d0*/ IADD3 R10, R10, -0x10, RZ ; /* 0xfffffff00a0a7810 */
/* 0x000fe20007ffe0ff */
/*06e0*/ DFMA R16, R16, -R18, R20 ; /* 0x800000121010722b */
/* 0x0104c40000000014 */
/*06f0*/ LDG.E.64 R20, [R2.64+0x78] ; /* 0x0000780402147981 */
/* 0x004eaa000c1e1b00 */
/*0700*/ STG.E.64 [R2.64+0x70], R16 ; /* 0x0000701002007986 */
/* 0x008fe8000c101b04 */
/*0710*/ LDG.E.64 R12, [R6.64+0x80] ; /* 0x00008004060c7981 */
/* 0x001ea8000c1e1b00 */
/*0720*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000ea2000c1e1b00 */
/*0730*/ ISETP.GT.AND P1, PT, R10, 0xd, PT ; /* 0x0000000d0a00780c */
/* 0x000fc40003f24270 */
/*0740*/ IADD3 R14, P3, R2, 0x80, RZ ; /* 0x00000080020e7810 */
/* 0x002fca0007f7e0ff */
/*0750*/ IMAD.X R15, RZ, RZ, R3, P3 ; /* 0x000000ffff0f7224 */
/* 0x000fe200018e0603 */
/*0760*/ IADD3 R11, R11, 0x10, RZ ; /* 0x000000100b0b7810 */
/* 0x000fe20007ffe0ff */
/*0770*/ DFMA R12, R12, -R18, R20 ; /* 0x800000120c0c722b */
/* 0x0040640000000014 */
/*0780*/ IADD3 R18, P2, R6, 0x80, RZ ; /* 0x0000008006127810 */
/* 0x001fca0007f5e0ff */
/*0790*/ IMAD.X R19, RZ, RZ, R7, P2 ; /* 0x000000ffff137224 */
/* 0x000fe200010e0607 */
/*07a0*/ STG.E.64 [R2.64+0x78], R12 ; /* 0x0000780c02007986 */
/* 0x0021e2000c101b04 */
/*07b0*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0012 */
/*07c0*/ IMAD.MOV.U32 R7, RZ, RZ, R19 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0013 */
/*07d0*/ IMAD.MOV.U32 R2, RZ, RZ, R14 ; /* 0x000000ffff027224 */
/* 0x001fe400078e000e */
/*07e0*/ IMAD.MOV.U32 R3, RZ, RZ, R15 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000f */
/*07f0*/ @P1 BRA 0x240 ; /* 0xfffffa4000001947 */
/* 0x000fea000383ffff */
/*0800*/ IADD3 R12, R10, -0x1, RZ ; /* 0xffffffff0a0c7810 */
/* 0x000fc80007ffe0ff */
/*0810*/ ISETP.GT.AND P1, PT, R12, 0x4, PT ; /* 0x000000040c00780c */
/* 0x000fda0003f24270 */
/*0820*/ @!P1 BRA 0xb40 ; /* 0x0000031000009947 */
/* 0x000fea0003800000 */
/*0830*/ LDG.E.64 R12, [R6.64+0x8] ; /* 0x00000804060c7981 */
/* 0x000ea8000c1e1b00 */
/*0840*/ LDG.E.64 R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea8000c1e1b00 */
/*0850*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea8000c1e1b00 */
/*0860*/ LDG.E.64 R18, [R2.64+0x8] ; /* 0x0000080402127981 */
/* 0x000ee8000c1e1b00 */
/*0870*/ LDG.E.64 R20, [R2.64+0x10] ; /* 0x0000100402147981 */
/* 0x000f22000c1e1b00 */
/*0880*/ DFMA R12, R12, -R14, R16 ; /* 0x8000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0890*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*08a0*/ LDG.E.64 R14, [R6.64+0x10] ; /* 0x00001004060e7981 */
/* 0x000ee8000c1e1b00 */
/*08b0*/ LDG.E.64 R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000ee4000c1e1b00 */
/*08c0*/ DFMA R14, R14, -R16, R18 ; /* 0x800000100e0e722b */
/* 0x008e4e0000000012 */
/*08d0*/ STG.E.64 [R2.64+0x8], R14 ; /* 0x0000080e02007986 */
/* 0x0023e8000c101b04 */
/*08e0*/ LDG.E.64 R16, [R6.64+0x18] ; /* 0x0000180406107981 */
/* 0x000f28000c1e1b00 */
/*08f0*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000f24000c1e1b00 */
/*0900*/ DFMA R16, R16, -R18, R20 ; /* 0x800000121010722b */
/* 0x0104c40000000014 */
/*0910*/ LDG.E.64 R20, [R2.64+0x18] ; /* 0x0000180402147981 */
/* 0x004eaa000c1e1b00 */
/*0920*/ STG.E.64 [R2.64+0x10], R16 ; /* 0x0000101002007986 */
/* 0x0087e8000c101b04 */
/*0930*/ LDG.E.64 R12, [R6.64+0x20] ; /* 0x00002004060c7981 */
/* 0x001ea8000c1e1b00 */
/*0940*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000ea4000c1e1b00 */
/*0950*/ DFMA R12, R12, -R18, R20 ; /* 0x800000120c0c722b */
/* 0x0040840000000014 */
/*0960*/ LDG.E.64 R20, [R2.64+0x20] ; /* 0x0000200402147981 */
/* 0x001f2a000c1e1b00 */
/*0970*/ STG.E.64 [R2.64+0x18], R12 ; /* 0x0000180c02007986 */
/* 0x0041e8000c101b04 */
/*0980*/ LDG.E.64 R14, [R6.64+0x28] ; /* 0x00002804060e7981 */
/* 0x002f28000c1e1b00 */
/*0990*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000f24000c1e1b00 */
/*09a0*/ DFMA R14, R14, -R18, R20 ; /* 0x800000120e0e722b */
/* 0x0102840000000014 */
/*09b0*/ LDG.E.64 R20, [R2.64+0x28] ; /* 0x0000280402147981 */
/* 0x002f2a000c1e1b00 */
/*09c0*/ STG.E.64 [R2.64+0x20], R14 ; /* 0x0000200e02007986 */
/* 0x0043e8000c101b04 */
/*09d0*/ LDG.E.64 R16, [R6.64+0x30] ; /* 0x0000300406107981 */
/* 0x008f28000c1e1b00 */
/*09e0*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000f24000c1e1b00 */
/*09f0*/ DFMA R16, R16, -R18, R20 ; /* 0x800000121010722b */
/* 0x0104c40000000014 */
/*0a00*/ LDG.E.64 R20, [R2.64+0x30] ; /* 0x0000300402147981 */
/* 0x004eaa000c1e1b00 */
/*0a10*/ STG.E.64 [R2.64+0x28], R16 ; /* 0x0000281002007986 */
/* 0x0087e8000c101b04 */
/*0a20*/ LDG.E.64 R12, [R6.64+0x38] ; /* 0x00003804060c7981 */
/* 0x001ea8000c1e1b00 */
/*0a30*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000ea4000c1e1b00 */
/*0a40*/ DFMA R12, R12, -R18, R20 ; /* 0x800000120c0c722b */
/* 0x0040840000000014 */
/*0a50*/ LDG.E.64 R20, [R2.64+0x38] ; /* 0x0000380402147981 */
/* 0x001f2a000c1e1b00 */
/*0a60*/ STG.E.64 [R2.64+0x30], R12 ; /* 0x0000300c02007986 */
/* 0x004fe8000c101b04 */
/*0a70*/ LDG.E.64 R14, [R6.64+0x40] ; /* 0x00004004060e7981 */
/* 0x002128000c1e1b00 */
/*0a80*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000f22000c1e1b00 */
/*0a90*/ IADD3 R16, P2, R2, 0x40, RZ ; /* 0x0000004002107810 */
/* 0x008fc40007f5e0ff */
/*0aa0*/ IADD3 R6, P1, R6, 0x40, RZ ; /* 0x0000004006067810 */
/* 0x001fc60007f3e0ff */
/*0ab0*/ IMAD.X R17, RZ, RZ, R3, P2 ; /* 0x000000ffff117224 */
/* 0x000fe200010e0603 */
/*0ac0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0ad0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe40000ffe4ff */
/*0ae0*/ IADD3 R11, R11, 0x8, RZ ; /* 0x000000080b0b7810 */
/* 0x000fe40007ffe0ff */
/*0af0*/ IADD3 R10, R10, -0x8, RZ ; /* 0xfffffff80a0a7810 */
/* 0x000fe20007ffe0ff */
/*0b00*/ DFMA R14, R14, -R18, R20 ; /* 0x800000120e0e722b */
/* 0x010e0e0000000014 */
/*0b10*/ STG.E.64 [R2.64+0x38], R14 ; /* 0x0000380e02007986 */
/* 0x0011e4000c101b04 */
/*0b20*/ IMAD.MOV.U32 R2, RZ, RZ, R16 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0010 */
/*0b30*/ IMAD.MOV.U32 R3, RZ, RZ, R17 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0011 */
/*0b40*/ ISETP.NE.OR P0, PT, R10, 0x1, P0 ; /* 0x000000010a00780c */
/* 0x000fda0000705670 */
/*0b50*/ @!P0 BRA 0xd60 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0b60*/ LDG.E.64 R12, [R6.64+0x8] ; /* 0x00000804060c7981 */
/* 0x000ea8000c1e1b00 */
/*0b70*/ LDG.E.64 R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea8000c1e1b00 */
/*0b80*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea8000c1e1b00 */
/*0b90*/ LDG.E.64 R18, [R2.64+0x8] ; /* 0x0000080402127981 */
/* 0x000ee8000c1e1b00 */
/*0ba0*/ LDG.E.64 R20, [R2.64+0x10] ; /* 0x0000100402147981 */
/* 0x000f22000c1e1b00 */
/*0bb0*/ DFMA R12, R12, -R14, R16 ; /* 0x8000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0bc0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*0bd0*/ LDG.E.64 R14, [R6.64+0x10] ; /* 0x00001004060e7981 */
/* 0x000ee8000c1e1b00 */
/*0be0*/ LDG.E.64 R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000ee4000c1e1b00 */
/*0bf0*/ DFMA R14, R14, -R16, R18 ; /* 0x800000100e0e722b */
/* 0x008e4e0000000012 */
/*0c00*/ STG.E.64 [R2.64+0x8], R14 ; /* 0x0000080e02007986 */
/* 0x0023e8000c101b04 */
/*0c10*/ LDG.E.64 R16, [R6.64+0x18] ; /* 0x0000180406107981 */
/* 0x000f28000c1e1b00 */
/*0c20*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000f22000c1e1b00 */
/*0c30*/ IADD3 R10, R10, -0x4, RZ ; /* 0xfffffffc0a0a7810 */
/* 0x000fe20007ffe0ff */
/*0c40*/ DFMA R16, R16, -R18, R20 ; /* 0x800000121010722b */
/* 0x0104c40000000014 */
/*0c50*/ LDG.E.64 R20, [R2.64+0x18] ; /* 0x0000180402147981 */
/* 0x004eaa000c1e1b00 */
/*0c60*/ STG.E.64 [R2.64+0x10], R16 ; /* 0x0000101002007986 */
/* 0x008fe8000c101b04 */
/*0c70*/ LDG.E.64 R12, [R6.64+0x20] ; /* 0x00002004060c7981 */
/* 0x001ea8000c1e1b00 */
/*0c80*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000ea2000c1e1b00 */
/*0c90*/ ISETP.NE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fc40003f05270 */
/*0ca0*/ IADD3 R14, P2, R2, 0x20, RZ ; /* 0x00000020020e7810 */
/* 0x002fca0007f5e0ff */
/*0cb0*/ IMAD.X R15, RZ, RZ, R3, P2 ; /* 0x000000ffff0f7224 */
/* 0x000fe200010e0603 */
/*0cc0*/ IADD3 R11, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fe20007ffe0ff */
/*0cd0*/ DFMA R12, R12, -R18, R20 ; /* 0x800000120c0c722b */
/* 0x0040640000000014 */
/*0ce0*/ IADD3 R18, P1, R6, 0x20, RZ ; /* 0x0000002006127810 */
/* 0x001fca0007f3e0ff */
/*0cf0*/ IMAD.X R19, RZ, RZ, R7, P1 ; /* 0x000000ffff137224 */
/* 0x000fe200008e0607 */
/*0d00*/ STG.E.64 [R2.64+0x18], R12 ; /* 0x0000180c02007986 */
/* 0x0021e2000c101b04 */
/*0d10*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0012 */
/*0d20*/ IMAD.MOV.U32 R7, RZ, RZ, R19 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0013 */
/*0d30*/ IMAD.MOV.U32 R2, RZ, RZ, R14 ; /* 0x000000ffff027224 */
/* 0x001fe400078e000e */
/*0d40*/ IMAD.MOV.U32 R3, RZ, RZ, R15 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000f */
/*0d50*/ @P0 BRA 0xb60 ; /* 0xfffffe0000000947 */
/* 0x000fea000383ffff */
/*0d60*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f05270 */
/*0d70*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0d80*/ IMAD R0, R0, c[0x0][0x170], R11 ; /* 0x00005c0000007a24 */
/* 0x000fe200078e020b */
/*0d90*/ IADD3 R3, R11, 0x1, RZ ; /* 0x000000010b037810 */
/* 0x000fc80007ffe0ff */
/*0da0*/ IADD3 R7, R0, 0x1, RZ ; /* 0x0000000100077810 */
/* 0x000fe20007ffe0ff */
/*0db0*/ IMAD.WIDE R2, R3, R8, c[0x0][0x188] ; /* 0x0000620003027625 */
/* 0x000fc800078e0208 */
/*0dc0*/ IMAD.WIDE R6, R7, R8, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fe200078e0208 */
/*0dd0*/ MOV R0, R2 ; /* 0x0000000200007202 */
/* 0x000fc60000000f00 */
/*0de0*/ IMAD.MOV.U32 R15, RZ, RZ, R3 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e0003 */
/*0df0*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x001fe400078e0006 */
/*0e00*/ IMAD.MOV.U32 R13, RZ, RZ, R7 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0007 */
/*0e10*/ IMAD.MOV.U32 R14, RZ, RZ, R0 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0000 */
/*0e20*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1b00 */
/*0e30*/ LDG.E.64 R2, [R14.64] ; /* 0x000000040e027981 */
/* 0x0000a8000c1e1b00 */
/*0e40*/ LDG.E.64 R10, [R12.64] ; /* 0x000000040c0a7981 */
/* 0x000ea2000c1e1b00 */
/*0e50*/ IADD3 R9, R9, -0x1, RZ ; /* 0xffffffff09097810 */
/* 0x000fc40007ffe0ff */
/*0e60*/ IADD3 R0, P1, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x000fe40007f3e0ff */
/*0e70*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fc60003f05270 */
/*0e80*/ IMAD.X R15, RZ, RZ, R15, P1 ; /* 0x000000ffff0f7224 */
/* 0x001fe200008e060f */
/*0e90*/ DFMA R2, R2, -R6, R10 ; /* 0x800000060202722b */
/* 0x004064000000000a */
/*0ea0*/ IADD3 R6, P2, R12, 0x8, RZ ; /* 0x000000080c067810 */
/* 0x001fca0007f5e0ff */
/*0eb0*/ STG.E.64 [R12.64], R2 ; /* 0x000000020c007986 */
/* 0x0021e2000c101b04 */
/*0ec0*/ IMAD.X R7, RZ, RZ, R13, P2 ; /* 0x000000ffff077224 */
/* 0x000fe200010e060d */
/*0ed0*/ @P0 BRA 0xdf0 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*0ee0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ef0*/ BRA 0xef0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0f00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/**
* C file for parallel QR factorization program usign CUDA
* See header for more infos.
*
* 2016 Marco Tieghi - marco01.tieghi@student.unife.it
*
*/
#define THREADS_PER_BLOCK 512 //I'll use 512 threads for each block (as required in the assignment)
__global__ void r1_update(double *A, int m, int n, int lda, double *col, int ldc, double *row) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
//A(:,ii+1:n−1)=A(:,ii+1:n−1)−A(:,ii)*R(ii,ii+1:n−1)
if (idx < m && idy < m) {
for (int ii=0; ii < n-1; ii++) {
A[idx*lda + ii+1] = A[idx*lda + ii+1] - col[idy*ldc] * row[ii+1];
}
}
} | .file "tmpxft_001849e4_00000000-6_r1_update.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z9r1_updatePdiiiS_iS_PdiiiS_iS_
.type _Z36__device_stub__Z9r1_updatePdiiiS_iS_PdiiiS_iS_, @function
_Z36__device_stub__Z9r1_updatePdiiiS_iS_PdiiiS_iS_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movl %ecx, 28(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 24(%rsp)
movq 192(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9r1_updatePdiiiS_iS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z9r1_updatePdiiiS_iS_PdiiiS_iS_, .-_Z36__device_stub__Z9r1_updatePdiiiS_iS_PdiiiS_iS_
.globl _Z9r1_updatePdiiiS_iS_
.type _Z9r1_updatePdiiiS_iS_, @function
_Z9r1_updatePdiiiS_iS_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z36__device_stub__Z9r1_updatePdiiiS_iS_PdiiiS_iS_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9r1_updatePdiiiS_iS_, .-_Z9r1_updatePdiiiS_iS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9r1_updatePdiiiS_iS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9r1_updatePdiiiS_iS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/**
* C file for parallel QR factorization program usign CUDA
* See header for more infos.
*
* 2016 Marco Tieghi - marco01.tieghi@student.unife.it
*
*/
#define THREADS_PER_BLOCK 512 //I'll use 512 threads for each block (as required in the assignment)
__global__ void r1_update(double *A, int m, int n, int lda, double *col, int ldc, double *row) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
//A(:,ii+1:n−1)=A(:,ii+1:n−1)−A(:,ii)*R(ii,ii+1:n−1)
if (idx < m && idy < m) {
for (int ii=0; ii < n-1; ii++) {
A[idx*lda + ii+1] = A[idx*lda + ii+1] - col[idy*ldc] * row[ii+1];
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
/**
* C file for parallel QR factorization program usign CUDA
* See header for more infos.
*
* 2016 Marco Tieghi - marco01.tieghi@student.unife.it
*
*/
#define THREADS_PER_BLOCK 512 //I'll use 512 threads for each block (as required in the assignment)
__global__ void r1_update(double *A, int m, int n, int lda, double *col, int ldc, double *row) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
//A(:,ii+1:n−1)=A(:,ii+1:n−1)−A(:,ii)*R(ii,ii+1:n−1)
if (idx < m && idy < m) {
for (int ii=0; ii < n-1; ii++) {
A[idx*lda + ii+1] = A[idx*lda + ii+1] - col[idy*ldc] * row[ii+1];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/**
* C file for parallel QR factorization program usign CUDA
* See header for more infos.
*
* 2016 Marco Tieghi - marco01.tieghi@student.unife.it
*
*/
#define THREADS_PER_BLOCK 512 //I'll use 512 threads for each block (as required in the assignment)
__global__ void r1_update(double *A, int m, int n, int lda, double *col, int ldc, double *row) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
//A(:,ii+1:n−1)=A(:,ii+1:n−1)−A(:,ii)*R(ii,ii+1:n−1)
if (idx < m && idy < m) {
for (int ii=0; ii < n-1; ii++) {
A[idx*lda + ii+1] = A[idx*lda + ii+1] - col[idy*ldc] * row[ii+1];
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9r1_updatePdiiiS_iS_
.globl _Z9r1_updatePdiiiS_iS_
.p2align 8
.type _Z9r1_updatePdiiiS_iS_,@function
_Z9r1_updatePdiiiS_iS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v2
s_cbranch_execz .LBB0_4
s_load_b32 s2, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 2
s_cbranch_scc1 .LBB0_4
s_clause 0x4
s_load_b32 s3, s[0:1], 0x10
s_load_b32 s8, s[0:1], 0x20
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b64 s[6:7], s[0:1], 0x18
s_load_b64 s[0:1], s[0:1], 0x28
s_add_i32 s2, s2, -1
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v0, v0, s3
v_mul_lo_u32 v2, v1, s8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 3, v[0:1]
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v0, s4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, v4, 8
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v5, vcc_lo
v_mov_b32_e32 v4, 0
.p2align 6
.LBB0_3:
global_load_b64 v[5:6], v[2:3], off
global_load_b64 v[7:8], v[0:1], off
global_load_b64 v[9:10], v4, s[0:1]
s_add_i32 s2, s2, -1
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s2, 0
s_waitcnt vmcnt(0)
v_fma_f64 v[5:6], -v[7:8], v[9:10], v[5:6]
global_store_b64 v[2:3], v[5:6], off
v_add_co_u32 v2, vcc_lo, v2, 8
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9r1_updatePdiiiS_iS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9r1_updatePdiiiS_iS_, .Lfunc_end0-_Z9r1_updatePdiiiS_iS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9r1_updatePdiiiS_iS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9r1_updatePdiiiS_iS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/**
* C file for parallel QR factorization program usign CUDA
* See header for more infos.
*
* 2016 Marco Tieghi - marco01.tieghi@student.unife.it
*
*/
#define THREADS_PER_BLOCK 512 //I'll use 512 threads for each block (as required in the assignment)
__global__ void r1_update(double *A, int m, int n, int lda, double *col, int ldc, double *row) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
//A(:,ii+1:n−1)=A(:,ii+1:n−1)−A(:,ii)*R(ii,ii+1:n−1)
if (idx < m && idy < m) {
for (int ii=0; ii < n-1; ii++) {
A[idx*lda + ii+1] = A[idx*lda + ii+1] - col[idy*ldc] * row[ii+1];
}
}
} | .text
.file "r1_update.hip"
.globl _Z24__device_stub__r1_updatePdiiiS_iS_ # -- Begin function _Z24__device_stub__r1_updatePdiiiS_iS_
.p2align 4, 0x90
.type _Z24__device_stub__r1_updatePdiiiS_iS_,@function
_Z24__device_stub__r1_updatePdiiiS_iS_: # @_Z24__device_stub__r1_updatePdiiiS_iS_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9r1_updatePdiiiS_iS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z24__device_stub__r1_updatePdiiiS_iS_, .Lfunc_end0-_Z24__device_stub__r1_updatePdiiiS_iS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9r1_updatePdiiiS_iS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9r1_updatePdiiiS_iS_,@object # @_Z9r1_updatePdiiiS_iS_
.section .rodata,"a",@progbits
.globl _Z9r1_updatePdiiiS_iS_
.p2align 3, 0x0
_Z9r1_updatePdiiiS_iS_:
.quad _Z24__device_stub__r1_updatePdiiiS_iS_
.size _Z9r1_updatePdiiiS_iS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9r1_updatePdiiiS_iS_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__r1_updatePdiiiS_iS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9r1_updatePdiiiS_iS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9r1_updatePdiiiS_iS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff097624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R2, R2, c[0x0][0x4], R5 ; /* 0x0000010002027a24 */
/* 0x001fca00078e0205 */
/*0070*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fe20003f06270 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*0090*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x168], P0 ; /* 0x00005a0000007a0c */
/* 0x000fc80000706670 */
/*00a0*/ ISETP.LT.OR P0, PT, R9, 0x2, P0 ; /* 0x000000020900780c */
/* 0x000fda0000701670 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R3, R9.reuse, -0x2, RZ ; /* 0xfffffffe09037810 */
/* 0x040fe20007ffe0ff */
/*00d0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x8 ; /* 0x00000008ff087424 */
/* 0x000fe200078e00ff */
/*00e0*/ IADD3 R9, R9, -0x1, RZ ; /* 0xffffffff09097810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD R5, R2, c[0x0][0x180], RZ ; /* 0x0000600002057a24 */
/* 0x000fe200078e02ff */
/*0100*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe20003f06070 */
/*0110*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0120*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*0130*/ LOP3.LUT R9, R9, 0x3, RZ, 0xc0, !PT ; /* 0x0000000309097812 */
/* 0x000fe200078ec0ff */
/*0140*/ IMAD.WIDE R4, R5, R8, c[0x0][0x178] ; /* 0x00005e0005047625 */
/* 0x000fd200078e0208 */
/*0150*/ @!P0 BRA 0xd60 ; /* 0x00000c0000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R10, -R9, c[0x0][0x16c], RZ ; /* 0x00005b00090a7a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff037624 */
/* 0x000fe400078e00ff */
/*0180*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e00ff */
/*0190*/ ISETP.GT.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fe20003f04270 */
/*01a0*/ IMAD R3, R0, R3, 0x1 ; /* 0x0000000100037424 */
/* 0x000fe400078e0203 */
/*01b0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff067624 */
/* 0x000fe400078e00ff */
/*01c0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff077624 */
/* 0x000fe400078e00ff */
/*01d0*/ IMAD.WIDE R2, R3, R8, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e0208 */
/*01e0*/ @!P0 BRA 0xb60 ; /* 0x0000097000008947 */
/* 0x000fea0003800000 */
/*01f0*/ IADD3 R12, R10, -0x1, RZ ; /* 0xffffffff0a0c7810 */
/* 0x000fe40007ffe0ff */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0210*/ ISETP.GT.AND P1, PT, R12, 0xc, PT ; /* 0x0000000c0c00780c */
/* 0x000fda0003f24270 */
/*0220*/ @!P1 BRA 0x800 ; /* 0x000005d000009947 */
/* 0x000fea0003800000 */
/*0230*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0240*/ LDG.E.64 R12, [R6.64+0x8] ; /* 0x00000804060c7981 */
/* 0x000ea8000c1e1b00 */
/*0250*/ LDG.E.64 R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea8000c1e1b00 */
/*0260*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea8000c1e1b00 */
/*0270*/ LDG.E.64 R18, [R2.64+0x8] ; /* 0x0000080402127981 */
/* 0x000ee8000c1e1b00 */
/*0280*/ LDG.E.64 R20, [R2.64+0x10] ; /* 0x0000100402147981 */
/* 0x000f22000c1e1b00 */
/*0290*/ DFMA R12, R12, -R14, R16 ; /* 0x8000000e0c0c722b */
/* 0x004e0e0000000010 */
/*02a0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*02b0*/ LDG.E.64 R14, [R6.64+0x10] ; /* 0x00001004060e7981 */
/* 0x000ee8000c1e1b00 */
/*02c0*/ LDG.E.64 R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000ee4000c1e1b00 */
/*02d0*/ DFMA R14, R14, -R16, R18 ; /* 0x800000100e0e722b */
/* 0x008e4e0000000012 */
/*02e0*/ STG.E.64 [R2.64+0x8], R14 ; /* 0x0000080e02007986 */
/* 0x0023e8000c101b04 */
/*02f0*/ LDG.E.64 R16, [R6.64+0x18] ; /* 0x0000180406107981 */
/* 0x000f28000c1e1b00 */
/*0300*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000f24000c1e1b00 */
/*0310*/ DFMA R16, R16, -R18, R20 ; /* 0x800000121010722b */
/* 0x0104c40000000014 */
/*0320*/ LDG.E.64 R20, [R2.64+0x18] ; /* 0x0000180402147981 */
/* 0x004eaa000c1e1b00 */
/*0330*/ STG.E.64 [R2.64+0x10], R16 ; /* 0x0000101002007986 */
/* 0x0087e8000c101b04 */
/*0340*/ LDG.E.64 R12, [R6.64+0x20] ; /* 0x00002004060c7981 */
/* 0x001ea8000c1e1b00 */
/*0350*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000ea4000c1e1b00 */
/*0360*/ DFMA R12, R12, -R18, R20 ; /* 0x800000120c0c722b */
/* 0x0040840000000014 */
/*0370*/ LDG.E.64 R20, [R2.64+0x20] ; /* 0x0000200402147981 */
/* 0x001f2a000c1e1b00 */
/*0380*/ STG.E.64 [R2.64+0x18], R12 ; /* 0x0000180c02007986 */
/* 0x0041e8000c101b04 */
/*0390*/ LDG.E.64 R14, [R6.64+0x28] ; /* 0x00002804060e7981 */
/* 0x002f28000c1e1b00 */
/*03a0*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000f24000c1e1b00 */
/*03b0*/ DFMA R14, R14, -R18, R20 ; /* 0x800000120e0e722b */
/* 0x0102840000000014 */
/*03c0*/ LDG.E.64 R20, [R2.64+0x28] ; /* 0x0000280402147981 */
/* 0x002f2a000c1e1b00 */
/*03d0*/ STG.E.64 [R2.64+0x20], R14 ; /* 0x0000200e02007986 */
/* 0x0043e8000c101b04 */
/*03e0*/ LDG.E.64 R16, [R6.64+0x30] ; /* 0x0000300406107981 */
/* 0x008f28000c1e1b00 */
/*03f0*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000f24000c1e1b00 */
/*0400*/ DFMA R16, R16, -R18, R20 ; /* 0x800000121010722b */
/* 0x0104c40000000014 */
/*0410*/ LDG.E.64 R20, [R2.64+0x30] ; /* 0x0000300402147981 */
/* 0x004eaa000c1e1b00 */
/*0420*/ STG.E.64 [R2.64+0x28], R16 ; /* 0x0000281002007986 */
/* 0x0087e8000c101b04 */
/*0430*/ LDG.E.64 R12, [R6.64+0x38] ; /* 0x00003804060c7981 */
/* 0x001ea8000c1e1b00 */
/*0440*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000ea4000c1e1b00 */
/*0450*/ DFMA R12, R12, -R18, R20 ; /* 0x800000120c0c722b */
/* 0x0040840000000014 */
/*0460*/ LDG.E.64 R20, [R2.64+0x38] ; /* 0x0000380402147981 */
/* 0x001f2a000c1e1b00 */
/*0470*/ STG.E.64 [R2.64+0x30], R12 ; /* 0x0000300c02007986 */
/* 0x0041e8000c101b04 */
/*0480*/ LDG.E.64 R14, [R6.64+0x40] ; /* 0x00004004060e7981 */
/* 0x002f28000c1e1b00 */
/*0490*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000f24000c1e1b00 */
/*04a0*/ DFMA R14, R14, -R18, R20 ; /* 0x800000120e0e722b */
/* 0x0102840000000014 */
/*04b0*/ LDG.E.64 R20, [R2.64+0x40] ; /* 0x0000400402147981 */
/* 0x002f2a000c1e1b00 */
/*04c0*/ STG.E.64 [R2.64+0x38], R14 ; /* 0x0000380e02007986 */
/* 0x0043e8000c101b04 */
/*04d0*/ LDG.E.64 R16, [R6.64+0x48] ; /* 0x0000480406107981 */
/* 0x008f28000c1e1b00 */
/*04e0*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000f24000c1e1b00 */
/*04f0*/ DFMA R16, R16, -R18, R20 ; /* 0x800000121010722b */
/* 0x0104c40000000014 */
/*0500*/ LDG.E.64 R20, [R2.64+0x48] ; /* 0x0000480402147981 */
/* 0x004eaa000c1e1b00 */
/*0510*/ STG.E.64 [R2.64+0x40], R16 ; /* 0x0000401002007986 */
/* 0x0087e8000c101b04 */
/*0520*/ LDG.E.64 R12, [R6.64+0x50] ; /* 0x00005004060c7981 */
/* 0x001ea8000c1e1b00 */
/*0530*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000ea4000c1e1b00 */
/*0540*/ DFMA R12, R12, -R18, R20 ; /* 0x800000120c0c722b */
/* 0x0040840000000014 */
/*0550*/ LDG.E.64 R20, [R2.64+0x50] ; /* 0x0000500402147981 */
/* 0x001f2a000c1e1b00 */
/*0560*/ STG.E.64 [R2.64+0x48], R12 ; /* 0x0000480c02007986 */
/* 0x0041e8000c101b04 */
/*0570*/ LDG.E.64 R14, [R6.64+0x58] ; /* 0x00005804060e7981 */
/* 0x002f28000c1e1b00 */
/*0580*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000f24000c1e1b00 */
/*0590*/ DFMA R14, R14, -R18, R20 ; /* 0x800000120e0e722b */
/* 0x0102840000000014 */
/*05a0*/ LDG.E.64 R20, [R2.64+0x58] ; /* 0x0000580402147981 */
/* 0x002f2a000c1e1b00 */
/*05b0*/ STG.E.64 [R2.64+0x50], R14 ; /* 0x0000500e02007986 */
/* 0x0043e8000c101b04 */
/*05c0*/ LDG.E.64 R16, [R6.64+0x60] ; /* 0x0000600406107981 */
/* 0x008f28000c1e1b00 */
/*05d0*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000f24000c1e1b00 */
/*05e0*/ DFMA R16, R16, -R18, R20 ; /* 0x800000121010722b */
/* 0x0104c40000000014 */
/*05f0*/ LDG.E.64 R20, [R2.64+0x60] ; /* 0x0000600402147981 */
/* 0x004eaa000c1e1b00 */
/*0600*/ STG.E.64 [R2.64+0x58], R16 ; /* 0x0000581002007986 */
/* 0x0087e8000c101b04 */
/*0610*/ LDG.E.64 R12, [R6.64+0x68] ; /* 0x00006804060c7981 */
/* 0x001ea8000c1e1b00 */
/*0620*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000ea4000c1e1b00 */
/*0630*/ DFMA R12, R12, -R18, R20 ; /* 0x800000120c0c722b */
/* 0x0040840000000014 */
/*0640*/ LDG.E.64 R20, [R2.64+0x68] ; /* 0x0000680402147981 */
/* 0x001f2a000c1e1b00 */
/*0650*/ STG.E.64 [R2.64+0x60], R12 ; /* 0x0000600c02007986 */
/* 0x0041e8000c101b04 */
/*0660*/ LDG.E.64 R14, [R6.64+0x70] ; /* 0x00007004060e7981 */
/* 0x002f28000c1e1b00 */
/*0670*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000f24000c1e1b00 */
/*0680*/ DFMA R14, R14, -R18, R20 ; /* 0x800000120e0e722b */
/* 0x0102840000000014 */
/*0690*/ LDG.E.64 R20, [R2.64+0x70] ; /* 0x0000700402147981 */
/* 0x002f2a000c1e1b00 */
/*06a0*/ STG.E.64 [R2.64+0x68], R14 ; /* 0x0000680e02007986 */
/* 0x0043e8000c101b04 */
/*06b0*/ LDG.E.64 R16, [R6.64+0x78] ; /* 0x0000780406107981 */
/* 0x008f28000c1e1b00 */
/*06c0*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000f22000c1e1b00 */
/*06d0*/ IADD3 R10, R10, -0x10, RZ ; /* 0xfffffff00a0a7810 */
/* 0x000fe20007ffe0ff */
/*06e0*/ DFMA R16, R16, -R18, R20 ; /* 0x800000121010722b */
/* 0x0104c40000000014 */
/*06f0*/ LDG.E.64 R20, [R2.64+0x78] ; /* 0x0000780402147981 */
/* 0x004eaa000c1e1b00 */
/*0700*/ STG.E.64 [R2.64+0x70], R16 ; /* 0x0000701002007986 */
/* 0x008fe8000c101b04 */
/*0710*/ LDG.E.64 R12, [R6.64+0x80] ; /* 0x00008004060c7981 */
/* 0x001ea8000c1e1b00 */
/*0720*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000ea2000c1e1b00 */
/*0730*/ ISETP.GT.AND P1, PT, R10, 0xd, PT ; /* 0x0000000d0a00780c */
/* 0x000fc40003f24270 */
/*0740*/ IADD3 R14, P3, R2, 0x80, RZ ; /* 0x00000080020e7810 */
/* 0x002fca0007f7e0ff */
/*0750*/ IMAD.X R15, RZ, RZ, R3, P3 ; /* 0x000000ffff0f7224 */
/* 0x000fe200018e0603 */
/*0760*/ IADD3 R11, R11, 0x10, RZ ; /* 0x000000100b0b7810 */
/* 0x000fe20007ffe0ff */
/*0770*/ DFMA R12, R12, -R18, R20 ; /* 0x800000120c0c722b */
/* 0x0040640000000014 */
/*0780*/ IADD3 R18, P2, R6, 0x80, RZ ; /* 0x0000008006127810 */
/* 0x001fca0007f5e0ff */
/*0790*/ IMAD.X R19, RZ, RZ, R7, P2 ; /* 0x000000ffff137224 */
/* 0x000fe200010e0607 */
/*07a0*/ STG.E.64 [R2.64+0x78], R12 ; /* 0x0000780c02007986 */
/* 0x0021e2000c101b04 */
/*07b0*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0012 */
/*07c0*/ IMAD.MOV.U32 R7, RZ, RZ, R19 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0013 */
/*07d0*/ IMAD.MOV.U32 R2, RZ, RZ, R14 ; /* 0x000000ffff027224 */
/* 0x001fe400078e000e */
/*07e0*/ IMAD.MOV.U32 R3, RZ, RZ, R15 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000f */
/*07f0*/ @P1 BRA 0x240 ; /* 0xfffffa4000001947 */
/* 0x000fea000383ffff */
/*0800*/ IADD3 R12, R10, -0x1, RZ ; /* 0xffffffff0a0c7810 */
/* 0x000fc80007ffe0ff */
/*0810*/ ISETP.GT.AND P1, PT, R12, 0x4, PT ; /* 0x000000040c00780c */
/* 0x000fda0003f24270 */
/*0820*/ @!P1 BRA 0xb40 ; /* 0x0000031000009947 */
/* 0x000fea0003800000 */
/*0830*/ LDG.E.64 R12, [R6.64+0x8] ; /* 0x00000804060c7981 */
/* 0x000ea8000c1e1b00 */
/*0840*/ LDG.E.64 R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea8000c1e1b00 */
/*0850*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea8000c1e1b00 */
/*0860*/ LDG.E.64 R18, [R2.64+0x8] ; /* 0x0000080402127981 */
/* 0x000ee8000c1e1b00 */
/*0870*/ LDG.E.64 R20, [R2.64+0x10] ; /* 0x0000100402147981 */
/* 0x000f22000c1e1b00 */
/*0880*/ DFMA R12, R12, -R14, R16 ; /* 0x8000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0890*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*08a0*/ LDG.E.64 R14, [R6.64+0x10] ; /* 0x00001004060e7981 */
/* 0x000ee8000c1e1b00 */
/*08b0*/ LDG.E.64 R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000ee4000c1e1b00 */
/*08c0*/ DFMA R14, R14, -R16, R18 ; /* 0x800000100e0e722b */
/* 0x008e4e0000000012 */
/*08d0*/ STG.E.64 [R2.64+0x8], R14 ; /* 0x0000080e02007986 */
/* 0x0023e8000c101b04 */
/*08e0*/ LDG.E.64 R16, [R6.64+0x18] ; /* 0x0000180406107981 */
/* 0x000f28000c1e1b00 */
/*08f0*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000f24000c1e1b00 */
/*0900*/ DFMA R16, R16, -R18, R20 ; /* 0x800000121010722b */
/* 0x0104c40000000014 */
/*0910*/ LDG.E.64 R20, [R2.64+0x18] ; /* 0x0000180402147981 */
/* 0x004eaa000c1e1b00 */
/*0920*/ STG.E.64 [R2.64+0x10], R16 ; /* 0x0000101002007986 */
/* 0x0087e8000c101b04 */
/*0930*/ LDG.E.64 R12, [R6.64+0x20] ; /* 0x00002004060c7981 */
/* 0x001ea8000c1e1b00 */
/*0940*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000ea4000c1e1b00 */
/*0950*/ DFMA R12, R12, -R18, R20 ; /* 0x800000120c0c722b */
/* 0x0040840000000014 */
/*0960*/ LDG.E.64 R20, [R2.64+0x20] ; /* 0x0000200402147981 */
/* 0x001f2a000c1e1b00 */
/*0970*/ STG.E.64 [R2.64+0x18], R12 ; /* 0x0000180c02007986 */
/* 0x0041e8000c101b04 */
/*0980*/ LDG.E.64 R14, [R6.64+0x28] ; /* 0x00002804060e7981 */
/* 0x002f28000c1e1b00 */
/*0990*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000f24000c1e1b00 */
/*09a0*/ DFMA R14, R14, -R18, R20 ; /* 0x800000120e0e722b */
/* 0x0102840000000014 */
/*09b0*/ LDG.E.64 R20, [R2.64+0x28] ; /* 0x0000280402147981 */
/* 0x002f2a000c1e1b00 */
/*09c0*/ STG.E.64 [R2.64+0x20], R14 ; /* 0x0000200e02007986 */
/* 0x0043e8000c101b04 */
/*09d0*/ LDG.E.64 R16, [R6.64+0x30] ; /* 0x0000300406107981 */
/* 0x008f28000c1e1b00 */
/*09e0*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000f24000c1e1b00 */
/*09f0*/ DFMA R16, R16, -R18, R20 ; /* 0x800000121010722b */
/* 0x0104c40000000014 */
/*0a00*/ LDG.E.64 R20, [R2.64+0x30] ; /* 0x0000300402147981 */
/* 0x004eaa000c1e1b00 */
/*0a10*/ STG.E.64 [R2.64+0x28], R16 ; /* 0x0000281002007986 */
/* 0x0087e8000c101b04 */
/*0a20*/ LDG.E.64 R12, [R6.64+0x38] ; /* 0x00003804060c7981 */
/* 0x001ea8000c1e1b00 */
/*0a30*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000ea4000c1e1b00 */
/*0a40*/ DFMA R12, R12, -R18, R20 ; /* 0x800000120c0c722b */
/* 0x0040840000000014 */
/*0a50*/ LDG.E.64 R20, [R2.64+0x38] ; /* 0x0000380402147981 */
/* 0x001f2a000c1e1b00 */
/*0a60*/ STG.E.64 [R2.64+0x30], R12 ; /* 0x0000300c02007986 */
/* 0x004fe8000c101b04 */
/*0a70*/ LDG.E.64 R14, [R6.64+0x40] ; /* 0x00004004060e7981 */
/* 0x002128000c1e1b00 */
/*0a80*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000f22000c1e1b00 */
/*0a90*/ IADD3 R16, P2, R2, 0x40, RZ ; /* 0x0000004002107810 */
/* 0x008fc40007f5e0ff */
/*0aa0*/ IADD3 R6, P1, R6, 0x40, RZ ; /* 0x0000004006067810 */
/* 0x001fc60007f3e0ff */
/*0ab0*/ IMAD.X R17, RZ, RZ, R3, P2 ; /* 0x000000ffff117224 */
/* 0x000fe200010e0603 */
/*0ac0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0ad0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe40000ffe4ff */
/*0ae0*/ IADD3 R11, R11, 0x8, RZ ; /* 0x000000080b0b7810 */
/* 0x000fe40007ffe0ff */
/*0af0*/ IADD3 R10, R10, -0x8, RZ ; /* 0xfffffff80a0a7810 */
/* 0x000fe20007ffe0ff */
/*0b00*/ DFMA R14, R14, -R18, R20 ; /* 0x800000120e0e722b */
/* 0x010e0e0000000014 */
/*0b10*/ STG.E.64 [R2.64+0x38], R14 ; /* 0x0000380e02007986 */
/* 0x0011e4000c101b04 */
/*0b20*/ IMAD.MOV.U32 R2, RZ, RZ, R16 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0010 */
/*0b30*/ IMAD.MOV.U32 R3, RZ, RZ, R17 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0011 */
/*0b40*/ ISETP.NE.OR P0, PT, R10, 0x1, P0 ; /* 0x000000010a00780c */
/* 0x000fda0000705670 */
/*0b50*/ @!P0 BRA 0xd60 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0b60*/ LDG.E.64 R12, [R6.64+0x8] ; /* 0x00000804060c7981 */
/* 0x000ea8000c1e1b00 */
/*0b70*/ LDG.E.64 R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea8000c1e1b00 */
/*0b80*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea8000c1e1b00 */
/*0b90*/ LDG.E.64 R18, [R2.64+0x8] ; /* 0x0000080402127981 */
/* 0x000ee8000c1e1b00 */
/*0ba0*/ LDG.E.64 R20, [R2.64+0x10] ; /* 0x0000100402147981 */
/* 0x000f22000c1e1b00 */
/*0bb0*/ DFMA R12, R12, -R14, R16 ; /* 0x8000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0bc0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*0bd0*/ LDG.E.64 R14, [R6.64+0x10] ; /* 0x00001004060e7981 */
/* 0x000ee8000c1e1b00 */
/*0be0*/ LDG.E.64 R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000ee4000c1e1b00 */
/*0bf0*/ DFMA R14, R14, -R16, R18 ; /* 0x800000100e0e722b */
/* 0x008e4e0000000012 */
/*0c00*/ STG.E.64 [R2.64+0x8], R14 ; /* 0x0000080e02007986 */
/* 0x0023e8000c101b04 */
/*0c10*/ LDG.E.64 R16, [R6.64+0x18] ; /* 0x0000180406107981 */
/* 0x000f28000c1e1b00 */
/*0c20*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000f22000c1e1b00 */
/*0c30*/ IADD3 R10, R10, -0x4, RZ ; /* 0xfffffffc0a0a7810 */
/* 0x000fe20007ffe0ff */
/*0c40*/ DFMA R16, R16, -R18, R20 ; /* 0x800000121010722b */
/* 0x0104c40000000014 */
/*0c50*/ LDG.E.64 R20, [R2.64+0x18] ; /* 0x0000180402147981 */
/* 0x004eaa000c1e1b00 */
/*0c60*/ STG.E.64 [R2.64+0x10], R16 ; /* 0x0000101002007986 */
/* 0x008fe8000c101b04 */
/*0c70*/ LDG.E.64 R12, [R6.64+0x20] ; /* 0x00002004060c7981 */
/* 0x001ea8000c1e1b00 */
/*0c80*/ LDG.E.64 R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000ea2000c1e1b00 */
/*0c90*/ ISETP.NE.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fc40003f05270 */
/*0ca0*/ IADD3 R14, P2, R2, 0x20, RZ ; /* 0x00000020020e7810 */
/* 0x002fca0007f5e0ff */
/*0cb0*/ IMAD.X R15, RZ, RZ, R3, P2 ; /* 0x000000ffff0f7224 */
/* 0x000fe200010e0603 */
/*0cc0*/ IADD3 R11, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fe20007ffe0ff */
/*0cd0*/ DFMA R12, R12, -R18, R20 ; /* 0x800000120c0c722b */
/* 0x0040640000000014 */
/*0ce0*/ IADD3 R18, P1, R6, 0x20, RZ ; /* 0x0000002006127810 */
/* 0x001fca0007f3e0ff */
/*0cf0*/ IMAD.X R19, RZ, RZ, R7, P1 ; /* 0x000000ffff137224 */
/* 0x000fe200008e0607 */
/*0d00*/ STG.E.64 [R2.64+0x18], R12 ; /* 0x0000180c02007986 */
/* 0x0021e2000c101b04 */
/*0d10*/ IMAD.MOV.U32 R6, RZ, RZ, R18 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0012 */
/*0d20*/ IMAD.MOV.U32 R7, RZ, RZ, R19 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0013 */
/*0d30*/ IMAD.MOV.U32 R2, RZ, RZ, R14 ; /* 0x000000ffff027224 */
/* 0x001fe400078e000e */
/*0d40*/ IMAD.MOV.U32 R3, RZ, RZ, R15 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000f */
/*0d50*/ @P0 BRA 0xb60 ; /* 0xfffffe0000000947 */
/* 0x000fea000383ffff */
/*0d60*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f05270 */
/*0d70*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0d80*/ IMAD R0, R0, c[0x0][0x170], R11 ; /* 0x00005c0000007a24 */
/* 0x000fe200078e020b */
/*0d90*/ IADD3 R3, R11, 0x1, RZ ; /* 0x000000010b037810 */
/* 0x000fc80007ffe0ff */
/*0da0*/ IADD3 R7, R0, 0x1, RZ ; /* 0x0000000100077810 */
/* 0x000fe20007ffe0ff */
/*0db0*/ IMAD.WIDE R2, R3, R8, c[0x0][0x188] ; /* 0x0000620003027625 */
/* 0x000fc800078e0208 */
/*0dc0*/ IMAD.WIDE R6, R7, R8, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fe200078e0208 */
/*0dd0*/ MOV R0, R2 ; /* 0x0000000200007202 */
/* 0x000fc60000000f00 */
/*0de0*/ IMAD.MOV.U32 R15, RZ, RZ, R3 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e0003 */
/*0df0*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x001fe400078e0006 */
/*0e00*/ IMAD.MOV.U32 R13, RZ, RZ, R7 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0007 */
/*0e10*/ IMAD.MOV.U32 R14, RZ, RZ, R0 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0000 */
/*0e20*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1b00 */
/*0e30*/ LDG.E.64 R2, [R14.64] ; /* 0x000000040e027981 */
/* 0x0000a8000c1e1b00 */
/*0e40*/ LDG.E.64 R10, [R12.64] ; /* 0x000000040c0a7981 */
/* 0x000ea2000c1e1b00 */
/*0e50*/ IADD3 R9, R9, -0x1, RZ ; /* 0xffffffff09097810 */
/* 0x000fc40007ffe0ff */
/*0e60*/ IADD3 R0, P1, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x000fe40007f3e0ff */
/*0e70*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fc60003f05270 */
/*0e80*/ IMAD.X R15, RZ, RZ, R15, P1 ; /* 0x000000ffff0f7224 */
/* 0x001fe200008e060f */
/*0e90*/ DFMA R2, R2, -R6, R10 ; /* 0x800000060202722b */
/* 0x004064000000000a */
/*0ea0*/ IADD3 R6, P2, R12, 0x8, RZ ; /* 0x000000080c067810 */
/* 0x001fca0007f5e0ff */
/*0eb0*/ STG.E.64 [R12.64], R2 ; /* 0x000000020c007986 */
/* 0x0021e2000c101b04 */
/*0ec0*/ IMAD.X R7, RZ, RZ, R13, P2 ; /* 0x000000ffff077224 */
/* 0x000fe200010e060d */
/*0ed0*/ @P0 BRA 0xdf0 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*0ee0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ef0*/ BRA 0xef0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0f00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9r1_updatePdiiiS_iS_
.globl _Z9r1_updatePdiiiS_iS_
.p2align 8
.type _Z9r1_updatePdiiiS_iS_,@function
_Z9r1_updatePdiiiS_iS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s3, v2
s_cbranch_execz .LBB0_4
s_load_b32 s2, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 2
s_cbranch_scc1 .LBB0_4
s_clause 0x4
s_load_b32 s3, s[0:1], 0x10
s_load_b32 s8, s[0:1], 0x20
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b64 s[6:7], s[0:1], 0x18
s_load_b64 s[0:1], s[0:1], 0x28
s_add_i32 s2, s2, -1
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v0, v0, s3
v_mul_lo_u32 v2, v1, s8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 3, v[0:1]
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v0, s4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, v4, 8
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v5, vcc_lo
v_mov_b32_e32 v4, 0
.p2align 6
.LBB0_3:
global_load_b64 v[5:6], v[2:3], off
global_load_b64 v[7:8], v[0:1], off
global_load_b64 v[9:10], v4, s[0:1]
s_add_i32 s2, s2, -1
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s2, 0
s_waitcnt vmcnt(0)
v_fma_f64 v[5:6], -v[7:8], v[9:10], v[5:6]
global_store_b64 v[2:3], v[5:6], off
v_add_co_u32 v2, vcc_lo, v2, 8
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9r1_updatePdiiiS_iS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9r1_updatePdiiiS_iS_, .Lfunc_end0-_Z9r1_updatePdiiiS_iS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9r1_updatePdiiiS_iS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9r1_updatePdiiiS_iS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001849e4_00000000-6_r1_update.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z9r1_updatePdiiiS_iS_PdiiiS_iS_
.type _Z36__device_stub__Z9r1_updatePdiiiS_iS_PdiiiS_iS_, @function
_Z36__device_stub__Z9r1_updatePdiiiS_iS_PdiiiS_iS_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movl %ecx, 28(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 24(%rsp)
movq 192(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9r1_updatePdiiiS_iS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z9r1_updatePdiiiS_iS_PdiiiS_iS_, .-_Z36__device_stub__Z9r1_updatePdiiiS_iS_PdiiiS_iS_
.globl _Z9r1_updatePdiiiS_iS_
.type _Z9r1_updatePdiiiS_iS_, @function
_Z9r1_updatePdiiiS_iS_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z36__device_stub__Z9r1_updatePdiiiS_iS_PdiiiS_iS_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9r1_updatePdiiiS_iS_, .-_Z9r1_updatePdiiiS_iS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9r1_updatePdiiiS_iS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9r1_updatePdiiiS_iS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "r1_update.hip"
.globl _Z24__device_stub__r1_updatePdiiiS_iS_ # -- Begin function _Z24__device_stub__r1_updatePdiiiS_iS_
.p2align 4, 0x90
.type _Z24__device_stub__r1_updatePdiiiS_iS_,@function
_Z24__device_stub__r1_updatePdiiiS_iS_: # @_Z24__device_stub__r1_updatePdiiiS_iS_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %r8, 64(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9r1_updatePdiiiS_iS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z24__device_stub__r1_updatePdiiiS_iS_, .Lfunc_end0-_Z24__device_stub__r1_updatePdiiiS_iS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9r1_updatePdiiiS_iS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9r1_updatePdiiiS_iS_,@object # @_Z9r1_updatePdiiiS_iS_
.section .rodata,"a",@progbits
.globl _Z9r1_updatePdiiiS_iS_
.p2align 3, 0x0
_Z9r1_updatePdiiiS_iS_:
.quad _Z24__device_stub__r1_updatePdiiiS_iS_
.size _Z9r1_updatePdiiiS_iS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9r1_updatePdiiiS_iS_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__r1_updatePdiiiS_iS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9r1_updatePdiiiS_iS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#include <time.h>
#include <math.h>
#include <string.h>
#define EPSILON 1E-9
#define BLOCK_SIZE_F 512 //Work with blocks of 512 threads due to double precision - shared memory
#define BLOCK_SIZE_VP 1024 //Work with blocks of 512 threads due to double precision - shared memory
/*Declarando as structs de particula e forca*/
struct stCoord{
double x,
y,
z;
};
typedef struct stCoord tpCoord;
struct stParticle
{
tpCoord p,
v,
f;
};
typedef struct stParticle tpParticle;
//--------------------------------------------------------------------------------------------------------
__device__ double distance( double* dx,
double* dy,
double* dz,
const tpParticle A,
const tpParticle B){
double x = A.p.x - B.p.x;
double y = A.p.y - B.p.y;
double z = A.p.z - B.p.z;
*dx = x; *dy = y; *dz = z;
x *= x; y *= y; z *= z;
return 1.0 / sqrt((double)x + y + z + EPSILON);
}
__global__ void particleParticleForces_k(tpParticle *particles, const double dt){
extern __shared__ tpParticle subParticles[];
int i = blockDim.x * blockIdx.x + threadIdx.x;
// __shared__ tpParticle subParticles[BLOCK_SIZE];
for (int blk = 0; blk < gridDim.x; blk++){
subParticles[threadIdx.x] = particles[ blockDim.x * blk + threadIdx.x];
__syncthreads();
for (int j = 0; j < blockDim.x; j++){
double dx = 0.0f, dy = 0.0f, dz = 0.0f;
double d = distance(&dx, &dy, &dz, particles[i], subParticles[j]);
particles[i].f.x += dx * d;
particles[i].f.y += dy * d;
particles[i].f.z += dz * d;
}//end-for (int j = 0; j < blockDim.x; j++){
__syncthreads();
}//end-for (int blk = 0; blk < gridDim.x; blk++){
}
__global__ void particleParticleVelocityPosition_k(tpParticle *particles, const double dt){
int i = blockDim.x * blockIdx.x + threadIdx.x;
particles[i].v.x += dt * particles[i].f.x;
particles[i].v.y += dt * particles[i].f.y;
particles[i].v.z += dt * particles[i].f.z;
particles[i].p.x += dt * particles[i].v.x;
particles[i].p.y += dt * particles[i].v.y;
particles[i].p.z += dt * particles[i].v.z;
}
void particleParticle (tpParticle *h_particles, int nParticles, int timesteps, double dt){
int threadsF = BLOCK_SIZE_F,
blocksF = nParticles / BLOCK_SIZE_F,
threadsVP = BLOCK_SIZE_VP,
blocksVP = nParticles / BLOCK_SIZE_VP;
tpParticle *d_particles;
if (nParticles < BLOCK_SIZE_F){
blocksF = 1;
threadsF = nParticles;
}
if (nParticles < BLOCK_SIZE_VP){
blocksVP = 1;
threadsVP = nParticles;
}
assert(cudaDeviceReset()== cudaSuccess);
assert(cudaMalloc((void**) &d_particles, nParticles * sizeof(tpParticle)) == cudaSuccess);
assert(cudaMemcpy(d_particles, h_particles, nParticles * sizeof(tpParticle), cudaMemcpyHostToDevice) == cudaSuccess);
assert( ((nParticles % threadsF) == 0) && ((nParticles % threadsVP) == 0) );
//fprintf(stdout, "\n B(%d) T(%d) \n", blocks, threads);
//fprintf(stdout, "Shared memory allocated %d\n", threads * sizeof(tpParticle));
for (int t = 0; t < timesteps; t++){
//setup_kernel<<<blocos, threads,0, mStreams[i] >>>(time (NULL) + offset, mStates+offset);
particleParticleForces_k<<<blocksF, threadsF, threadsF * sizeof(tpParticle)>>>(d_particles, dt);
//assert( cudaDeviceSynchronize() == cudaSuccess);
particleParticleVelocityPosition_k<<<blocksVP, threadsVP>>>(d_particles, dt);
//assert( cudaDeviceSynchronize() == cudaSuccess);
}//end-for (int t = 0; t < timesteps; t++){
assert(cudaMemcpy(h_particles, d_particles, nParticles * sizeof(tpParticle), cudaMemcpyDeviceToHost) == cudaSuccess);
cudaFree(d_particles);
}
//--------------------------------------------------------------------------------------------------------
void printLog(tpParticle *particles, int nParticles, int timestep);
void initialCondition(tpParticle *particles, int nParticles);
int main (int ac, char **av){
int timesteps = atoi(av[1]),
nParticles = atoi(av[2]),
flagSave = atoi(av[3]);
double dt = 0.00001f;
tpParticle *particles = NULL;
fprintf(stdout, "\nParcile system particle to particle \n");
fprintf(stdout, "Memory used %lu bytes \n", nParticles * sizeof(tpParticle));
particles = (tpParticle *) malloc ( nParticles * sizeof(tpParticle));
assert(particles != NULL);
initialCondition(particles, nParticles);
particleParticle(particles, nParticles, timesteps, dt);
if (flagSave == 1)
printLog(particles, nParticles, timesteps);
free(particles);
}
void printLog(tpParticle *particles, int nParticles, int timestep){
char fileName[128];
sprintf(fileName, "%s-%d-log.bin", __FILE__, timestep);
fprintf(stdout, "Saving file [%s] ", fileName); fflush(stdout);
FILE *ptr = fopen(fileName, "wb+");
//fwrite ((const void*)particles , sizeof(tpParticle), nParticles, ptr);
for(int i = 0; i < nParticles; i++)
fprintf(ptr, "%d \t %.10f %.10f %.10f \t %.10f %.10f %.10f \t %.10f %.10f %.10f \n", i, particles[i].p.x, particles[i].p.y, particles[i].p.z, particles[i].v.x, particles[i].v.y, particles[i].v.z, particles[i].f.x, particles[i].f.y, particles[i].f.z);
fclose(ptr);
fprintf(stdout, "[OK]\n"); fflush(stdout);
}
void initialCondition(tpParticle *particles, int nParticles){
srand(42);
memset(particles, 0x00, nParticles * sizeof(tpParticle));
for (int i = 0; i < nParticles ; i++){
particles[i].p.x = 2.0 * (rand() / (double)RAND_MAX) - 1.0;
particles[i].p.y = 2.0 * (rand() / (double)RAND_MAX) - 1.0;
particles[i].p.z = 2.0 * (rand() / (double)RAND_MAX) - 1.0;
}
} | .file "tmpxft_0002eb84_00000000-6_main-n-bodies.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8distancePdS_S_10stParticleS0_
.type _Z8distancePdS_S_10stParticleS0_, @function
_Z8distancePdS_S_10stParticleS0_:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z8distancePdS_S_10stParticleS0_, .-_Z8distancePdS_S_10stParticleS0_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/marzam/HPC-Aula/main/exemplos/problems-profile/nbody-cuda-profile/main-n-bodies.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%s-%d-log.bin"
.LC2:
.string "Saving file [%s] "
.LC3:
.string "wb+"
.section .rodata.str1.8
.align 8
.LC4:
.string "%d \t %.10f %.10f %.10f \t %.10f %.10f %.10f \t %.10f %.10f %.10f \n"
.section .rodata.str1.1
.LC5:
.string "[OK]\n"
.text
.globl _Z8printLogP10stParticleii
.type _Z8printLogP10stParticleii, @function
_Z8printLogP10stParticleii:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $144, %rsp
.cfi_def_cfa_offset 192
movq %rdi, %rbx
movl %esi, %r13d
movl %edx, %r9d
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movq %rsp, %rbp
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rcx
movl $128, %edx
movl $2, %esi
movq %rbp, %rdi
call __sprintf_chk@PLT
movq %rbp, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
leaq .LC3(%rip), %rsi
movq %rbp, %rdi
call fopen@PLT
movq %rax, %r12
testl %r13d, %r13d
jle .L6
movl $0, %ebp
leaq .LC4(%rip), %r14
.L7:
movsd 56(%rbx), %xmm7
movsd 48(%rbx), %xmm6
movsd 40(%rbx), %xmm5
movsd 32(%rbx), %xmm4
movsd 24(%rbx), %xmm3
movsd 16(%rbx), %xmm2
movsd 8(%rbx), %xmm1
movsd (%rbx), %xmm0
subq $8, %rsp
.cfi_def_cfa_offset 200
pushq 64(%rbx)
.cfi_def_cfa_offset 208
movl %ebp, %ecx
movq %r14, %rdx
movl $2, %esi
movq %r12, %rdi
movl $8, %eax
call __fprintf_chk@PLT
addl $1, %ebp
addq $72, %rbx
addq $16, %rsp
.cfi_def_cfa_offset 192
cmpl %ebp, %r13d
jne .L7
.L6:
movq %r12, %rdi
call fclose@PLT
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z8printLogP10stParticleii, .-_Z8printLogP10stParticleii
.globl _Z16initialConditionP10stParticlei
.type _Z16initialConditionP10stParticlei, @function
_Z16initialConditionP10stParticlei:
.LFB2061:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbp
movl %esi, %ebx
movl $42, %edi
call srand@PLT
movslq %ebx, %rax
leaq (%rax,%rax,8), %r12
salq $3, %r12
movq %r12, %rdx
movl $0, %esi
movq %rbp, %rdi
call memset@PLT
testl %ebx, %ebx
jle .L12
movq %rbp, %rbx
addq %r12, %rbp
.L14:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC6(%rip), %xmm0
addsd %xmm0, %xmm0
subsd .LC7(%rip), %xmm0
movsd %xmm0, (%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC6(%rip), %xmm0
addsd %xmm0, %xmm0
subsd .LC7(%rip), %xmm0
movsd %xmm0, 8(%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC6(%rip), %xmm0
addsd %xmm0, %xmm0
subsd .LC7(%rip), %xmm0
movsd %xmm0, 16(%rbx)
addq $72, %rbx
cmpq %rbp, %rbx
jne .L14
.L12:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z16initialConditionP10stParticlei, .-_Z16initialConditionP10stParticlei
.globl _Z56__device_stub__Z24particleParticleForces_kP10stParticledP10stParticled
.type _Z56__device_stub__Z24particleParticleForces_kP10stParticledP10stParticled, @function
_Z56__device_stub__Z24particleParticleForces_kP10stParticledP10stParticled:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movsd %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z24particleParticleForces_kP10stParticled(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z56__device_stub__Z24particleParticleForces_kP10stParticledP10stParticled, .-_Z56__device_stub__Z24particleParticleForces_kP10stParticledP10stParticled
.globl _Z24particleParticleForces_kP10stParticled
.type _Z24particleParticleForces_kP10stParticled, @function
_Z24particleParticleForces_kP10stParticled:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z56__device_stub__Z24particleParticleForces_kP10stParticledP10stParticled
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z24particleParticleForces_kP10stParticled, .-_Z24particleParticleForces_kP10stParticled
.globl _Z66__device_stub__Z34particleParticleVelocityPosition_kP10stParticledP10stParticled
.type _Z66__device_stub__Z34particleParticleVelocityPosition_kP10stParticledP10stParticled, @function
_Z66__device_stub__Z34particleParticleVelocityPosition_kP10stParticledP10stParticled:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movsd %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z34particleParticleVelocityPosition_kP10stParticled(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z66__device_stub__Z34particleParticleVelocityPosition_kP10stParticledP10stParticled, .-_Z66__device_stub__Z34particleParticleVelocityPosition_kP10stParticledP10stParticled
.globl _Z34particleParticleVelocityPosition_kP10stParticled
.type _Z34particleParticleVelocityPosition_kP10stParticled, @function
_Z34particleParticleVelocityPosition_kP10stParticled:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z66__device_stub__Z34particleParticleVelocityPosition_kP10stParticledP10stParticled
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z34particleParticleVelocityPosition_kP10stParticled, .-_Z34particleParticleVelocityPosition_kP10stParticled
.globl _Z16particleParticleP10stParticleiid
.type _Z16particleParticleP10stParticleiid, @function
_Z16particleParticleP10stParticleiid:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %esi, %ebp
movl %edx, %r13d
movsd %xmm0, 8(%rsp)
leal 511(%rsi), %r12d
testl %esi, %esi
cmovns %esi, %r12d
sarl $9, %r12d
cmpl $511, %esi
jle .L39
cmpl $1023, %esi
jle .L40
leal 1023(%rsi), %r14d
testl %esi, %esi
cmovns %esi, %r14d
sarl $10, %r14d
movl $512, %r15d
movl $1024, %ebp
.L34:
testl %r13d, %r13d
jle .L35
movslq %r15d, %rax
leaq (%rax,%rax,8), %rax
salq $3, %rax
movq %rax, (%rsp)
movl $0, %ebx
jmp .L38
.L39:
movl %esi, %r15d
movl $1, %r12d
movl $1, %r14d
jmp .L34
.L40:
movl $512, %r15d
movl $1, %r14d
jmp .L34
.L43:
movsd 8(%rsp), %xmm0
movl $0, %edi
call _Z56__device_stub__Z24particleParticleForces_kP10stParticledP10stParticled
jmp .L36
.L37:
addl $1, %ebx
cmpl %ebx, %r13d
je .L35
.L38:
movl %r15d, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl %r12d, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movq (%rsp), %r8
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L43
.L36:
movl %ebp, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl %r14d, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L37
movsd 8(%rsp), %xmm0
movl $0, %edi
call _Z66__device_stub__Z34particleParticleVelocityPosition_kP10stParticledP10stParticled
jmp .L37
.L35:
movl $0, %edi
call cudaFree@PLT
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z16particleParticleP10stParticleiid, .-_Z16particleParticleP10stParticleiid
.section .rodata.str1.8
.align 8
.LC8:
.string "\nParcile system particle to particle \n"
.section .rodata.str1.1
.LC9:
.string "Memory used %lu bytes \n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rsi, %r12
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebp
movq 16(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %r13d
movq 24(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movslq %ebx, %rbx
leaq (%rbx,%rbx,8), %rbx
salq $3, %rbx
movq %rbx, %rcx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbx
movl %r13d, %esi
movq %rax, %rdi
call _Z16initialConditionP10stParticlei
movsd .LC10(%rip), %xmm0
movl %ebp, %edx
movl %r13d, %esi
movq %rbx, %rdi
call _Z16particleParticleP10stParticleiid
cmpl $1, %r12d
je .L47
.L45:
movq %rbx, %rdi
call free@PLT
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
movl %ebp, %edx
movl %r13d, %esi
movq %rbx, %rdi
call _Z8printLogP10stParticleii
jmp .L45
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC11:
.string "_Z34particleParticleVelocityPosition_kP10stParticled"
.align 8
.LC12:
.string "_Z24particleParticleForces_kP10stParticled"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z34particleParticleVelocityPosition_kP10stParticled(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z24particleParticleForces_kP10stParticled(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long -4194304
.long 1105199103
.align 8
.LC7:
.long 0
.long 1072693248
.align 8
.LC10:
.long -2147483648
.long 1055193269
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#include <time.h>
#include <math.h>
#include <string.h>
#define EPSILON 1E-9
#define BLOCK_SIZE_F 512 //Work with blocks of 512 threads due to double precision - shared memory
#define BLOCK_SIZE_VP 1024 //Work with blocks of 512 threads due to double precision - shared memory
/*Declarando as structs de particula e forca*/
struct stCoord{
double x,
y,
z;
};
typedef struct stCoord tpCoord;
struct stParticle
{
tpCoord p,
v,
f;
};
typedef struct stParticle tpParticle;
//--------------------------------------------------------------------------------------------------------
__device__ double distance( double* dx,
double* dy,
double* dz,
const tpParticle A,
const tpParticle B){
double x = A.p.x - B.p.x;
double y = A.p.y - B.p.y;
double z = A.p.z - B.p.z;
*dx = x; *dy = y; *dz = z;
x *= x; y *= y; z *= z;
return 1.0 / sqrt((double)x + y + z + EPSILON);
}
__global__ void particleParticleForces_k(tpParticle *particles, const double dt){
extern __shared__ tpParticle subParticles[];
int i = blockDim.x * blockIdx.x + threadIdx.x;
// __shared__ tpParticle subParticles[BLOCK_SIZE];
for (int blk = 0; blk < gridDim.x; blk++){
subParticles[threadIdx.x] = particles[ blockDim.x * blk + threadIdx.x];
__syncthreads();
for (int j = 0; j < blockDim.x; j++){
double dx = 0.0f, dy = 0.0f, dz = 0.0f;
double d = distance(&dx, &dy, &dz, particles[i], subParticles[j]);
particles[i].f.x += dx * d;
particles[i].f.y += dy * d;
particles[i].f.z += dz * d;
}//end-for (int j = 0; j < blockDim.x; j++){
__syncthreads();
}//end-for (int blk = 0; blk < gridDim.x; blk++){
}
__global__ void particleParticleVelocityPosition_k(tpParticle *particles, const double dt){
int i = blockDim.x * blockIdx.x + threadIdx.x;
particles[i].v.x += dt * particles[i].f.x;
particles[i].v.y += dt * particles[i].f.y;
particles[i].v.z += dt * particles[i].f.z;
particles[i].p.x += dt * particles[i].v.x;
particles[i].p.y += dt * particles[i].v.y;
particles[i].p.z += dt * particles[i].v.z;
}
void particleParticle (tpParticle *h_particles, int nParticles, int timesteps, double dt){
int threadsF = BLOCK_SIZE_F,
blocksF = nParticles / BLOCK_SIZE_F,
threadsVP = BLOCK_SIZE_VP,
blocksVP = nParticles / BLOCK_SIZE_VP;
tpParticle *d_particles;
if (nParticles < BLOCK_SIZE_F){
blocksF = 1;
threadsF = nParticles;
}
if (nParticles < BLOCK_SIZE_VP){
blocksVP = 1;
threadsVP = nParticles;
}
assert(cudaDeviceReset()== cudaSuccess);
assert(cudaMalloc((void**) &d_particles, nParticles * sizeof(tpParticle)) == cudaSuccess);
assert(cudaMemcpy(d_particles, h_particles, nParticles * sizeof(tpParticle), cudaMemcpyHostToDevice) == cudaSuccess);
assert( ((nParticles % threadsF) == 0) && ((nParticles % threadsVP) == 0) );
//fprintf(stdout, "\n B(%d) T(%d) \n", blocks, threads);
//fprintf(stdout, "Shared memory allocated %d\n", threads * sizeof(tpParticle));
for (int t = 0; t < timesteps; t++){
//setup_kernel<<<blocos, threads,0, mStreams[i] >>>(time (NULL) + offset, mStates+offset);
particleParticleForces_k<<<blocksF, threadsF, threadsF * sizeof(tpParticle)>>>(d_particles, dt);
//assert( cudaDeviceSynchronize() == cudaSuccess);
particleParticleVelocityPosition_k<<<blocksVP, threadsVP>>>(d_particles, dt);
//assert( cudaDeviceSynchronize() == cudaSuccess);
}//end-for (int t = 0; t < timesteps; t++){
assert(cudaMemcpy(h_particles, d_particles, nParticles * sizeof(tpParticle), cudaMemcpyDeviceToHost) == cudaSuccess);
cudaFree(d_particles);
}
//--------------------------------------------------------------------------------------------------------
void printLog(tpParticle *particles, int nParticles, int timestep);
void initialCondition(tpParticle *particles, int nParticles);
int main (int ac, char **av){
int timesteps = atoi(av[1]),
nParticles = atoi(av[2]),
flagSave = atoi(av[3]);
double dt = 0.00001f;
tpParticle *particles = NULL;
fprintf(stdout, "\nParcile system particle to particle \n");
fprintf(stdout, "Memory used %lu bytes \n", nParticles * sizeof(tpParticle));
particles = (tpParticle *) malloc ( nParticles * sizeof(tpParticle));
assert(particles != NULL);
initialCondition(particles, nParticles);
particleParticle(particles, nParticles, timesteps, dt);
if (flagSave == 1)
printLog(particles, nParticles, timesteps);
free(particles);
}
void printLog(tpParticle *particles, int nParticles, int timestep){
char fileName[128];
sprintf(fileName, "%s-%d-log.bin", __FILE__, timestep);
fprintf(stdout, "Saving file [%s] ", fileName); fflush(stdout);
FILE *ptr = fopen(fileName, "wb+");
//fwrite ((const void*)particles , sizeof(tpParticle), nParticles, ptr);
for(int i = 0; i < nParticles; i++)
fprintf(ptr, "%d \t %.10f %.10f %.10f \t %.10f %.10f %.10f \t %.10f %.10f %.10f \n", i, particles[i].p.x, particles[i].p.y, particles[i].p.z, particles[i].v.x, particles[i].v.y, particles[i].v.z, particles[i].f.x, particles[i].f.y, particles[i].f.z);
fclose(ptr);
fprintf(stdout, "[OK]\n"); fflush(stdout);
}
void initialCondition(tpParticle *particles, int nParticles){
srand(42);
memset(particles, 0x00, nParticles * sizeof(tpParticle));
for (int i = 0; i < nParticles ; i++){
particles[i].p.x = 2.0 * (rand() / (double)RAND_MAX) - 1.0;
particles[i].p.y = 2.0 * (rand() / (double)RAND_MAX) - 1.0;
particles[i].p.z = 2.0 * (rand() / (double)RAND_MAX) - 1.0;
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#include <time.h>
#include <math.h>
#include <string.h>
#define EPSILON 1E-9
#define BLOCK_SIZE_F 512 //Work with blocks of 512 threads due to double precision - shared memory
#define BLOCK_SIZE_VP 1024 //Work with blocks of 512 threads due to double precision - shared memory
/*Declarando as structs de particula e forca*/
struct stCoord{
double x,
y,
z;
};
typedef struct stCoord tpCoord;
struct stParticle
{
tpCoord p,
v,
f;
};
typedef struct stParticle tpParticle;
//--------------------------------------------------------------------------------------------------------
__device__ double distance( double* dx,
double* dy,
double* dz,
const tpParticle A,
const tpParticle B){
double x = A.p.x - B.p.x;
double y = A.p.y - B.p.y;
double z = A.p.z - B.p.z;
*dx = x; *dy = y; *dz = z;
x *= x; y *= y; z *= z;
return 1.0 / sqrt((double)x + y + z + EPSILON);
}
__global__ void particleParticleForces_k(tpParticle *particles, const double dt){
extern __shared__ tpParticle subParticles[];
int i = blockDim.x * blockIdx.x + threadIdx.x;
// __shared__ tpParticle subParticles[BLOCK_SIZE];
for (int blk = 0; blk < gridDim.x; blk++){
subParticles[threadIdx.x] = particles[ blockDim.x * blk + threadIdx.x];
__syncthreads();
for (int j = 0; j < blockDim.x; j++){
double dx = 0.0f, dy = 0.0f, dz = 0.0f;
double d = distance(&dx, &dy, &dz, particles[i], subParticles[j]);
particles[i].f.x += dx * d;
particles[i].f.y += dy * d;
particles[i].f.z += dz * d;
}//end-for (int j = 0; j < blockDim.x; j++){
__syncthreads();
}//end-for (int blk = 0; blk < gridDim.x; blk++){
}
__global__ void particleParticleVelocityPosition_k(tpParticle *particles, const double dt){
int i = blockDim.x * blockIdx.x + threadIdx.x;
particles[i].v.x += dt * particles[i].f.x;
particles[i].v.y += dt * particles[i].f.y;
particles[i].v.z += dt * particles[i].f.z;
particles[i].p.x += dt * particles[i].v.x;
particles[i].p.y += dt * particles[i].v.y;
particles[i].p.z += dt * particles[i].v.z;
}
void particleParticle (tpParticle *h_particles, int nParticles, int timesteps, double dt){
int threadsF = BLOCK_SIZE_F,
blocksF = nParticles / BLOCK_SIZE_F,
threadsVP = BLOCK_SIZE_VP,
blocksVP = nParticles / BLOCK_SIZE_VP;
tpParticle *d_particles;
if (nParticles < BLOCK_SIZE_F){
blocksF = 1;
threadsF = nParticles;
}
if (nParticles < BLOCK_SIZE_VP){
blocksVP = 1;
threadsVP = nParticles;
}
assert(hipDeviceReset()== hipSuccess);
assert(hipMalloc((void**) &d_particles, nParticles * sizeof(tpParticle)) == hipSuccess);
assert(hipMemcpy(d_particles, h_particles, nParticles * sizeof(tpParticle), hipMemcpyHostToDevice) == hipSuccess);
assert( ((nParticles % threadsF) == 0) && ((nParticles % threadsVP) == 0) );
//fprintf(stdout, "\n B(%d) T(%d) \n", blocks, threads);
//fprintf(stdout, "Shared memory allocated %d\n", threads * sizeof(tpParticle));
for (int t = 0; t < timesteps; t++){
//setup_kernel<<<blocos, threads,0, mStreams[i] >>>(time (NULL) + offset, mStates+offset);
particleParticleForces_k<<<blocksF, threadsF, threadsF * sizeof(tpParticle)>>>(d_particles, dt);
//assert( cudaDeviceSynchronize() == cudaSuccess);
particleParticleVelocityPosition_k<<<blocksVP, threadsVP>>>(d_particles, dt);
//assert( cudaDeviceSynchronize() == cudaSuccess);
}//end-for (int t = 0; t < timesteps; t++){
assert(hipMemcpy(h_particles, d_particles, nParticles * sizeof(tpParticle), hipMemcpyDeviceToHost) == hipSuccess);
hipFree(d_particles);
}
//--------------------------------------------------------------------------------------------------------
void printLog(tpParticle *particles, int nParticles, int timestep);
void initialCondition(tpParticle *particles, int nParticles);
int main (int ac, char **av){
int timesteps = atoi(av[1]),
nParticles = atoi(av[2]),
flagSave = atoi(av[3]);
double dt = 0.00001f;
tpParticle *particles = NULL;
fprintf(stdout, "\nParcile system particle to particle \n");
fprintf(stdout, "Memory used %lu bytes \n", nParticles * sizeof(tpParticle));
particles = (tpParticle *) malloc ( nParticles * sizeof(tpParticle));
assert(particles != NULL);
initialCondition(particles, nParticles);
particleParticle(particles, nParticles, timesteps, dt);
if (flagSave == 1)
printLog(particles, nParticles, timesteps);
free(particles);
}
void printLog(tpParticle *particles, int nParticles, int timestep){
char fileName[128];
sprintf(fileName, "%s-%d-log.bin", __FILE__, timestep);
fprintf(stdout, "Saving file [%s] ", fileName); fflush(stdout);
FILE *ptr = fopen(fileName, "wb+");
//fwrite ((const void*)particles , sizeof(tpParticle), nParticles, ptr);
for(int i = 0; i < nParticles; i++)
fprintf(ptr, "%d \t %.10f %.10f %.10f \t %.10f %.10f %.10f \t %.10f %.10f %.10f \n", i, particles[i].p.x, particles[i].p.y, particles[i].p.z, particles[i].v.x, particles[i].v.y, particles[i].v.z, particles[i].f.x, particles[i].f.y, particles[i].f.z);
fclose(ptr);
fprintf(stdout, "[OK]\n"); fflush(stdout);
}
void initialCondition(tpParticle *particles, int nParticles){
srand(42);
memset(particles, 0x00, nParticles * sizeof(tpParticle));
for (int i = 0; i < nParticles ; i++){
particles[i].p.x = 2.0 * (rand() / (double)RAND_MAX) - 1.0;
particles[i].p.y = 2.0 * (rand() / (double)RAND_MAX) - 1.0;
particles[i].p.z = 2.0 * (rand() / (double)RAND_MAX) - 1.0;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#include <time.h>
#include <math.h>
#include <string.h>
#define EPSILON 1E-9
#define BLOCK_SIZE_F 512 //Work with blocks of 512 threads due to double precision - shared memory
#define BLOCK_SIZE_VP 1024 //Work with blocks of 512 threads due to double precision - shared memory
/*Declarando as structs de particula e forca*/
struct stCoord{
double x,
y,
z;
};
typedef struct stCoord tpCoord;
struct stParticle
{
tpCoord p,
v,
f;
};
typedef struct stParticle tpParticle;
//--------------------------------------------------------------------------------------------------------
__device__ double distance( double* dx,
double* dy,
double* dz,
const tpParticle A,
const tpParticle B){
double x = A.p.x - B.p.x;
double y = A.p.y - B.p.y;
double z = A.p.z - B.p.z;
*dx = x; *dy = y; *dz = z;
x *= x; y *= y; z *= z;
return 1.0 / sqrt((double)x + y + z + EPSILON);
}
__global__ void particleParticleForces_k(tpParticle *particles, const double dt){
extern __shared__ tpParticle subParticles[];
int i = blockDim.x * blockIdx.x + threadIdx.x;
// __shared__ tpParticle subParticles[BLOCK_SIZE];
for (int blk = 0; blk < gridDim.x; blk++){
subParticles[threadIdx.x] = particles[ blockDim.x * blk + threadIdx.x];
__syncthreads();
for (int j = 0; j < blockDim.x; j++){
double dx = 0.0f, dy = 0.0f, dz = 0.0f;
double d = distance(&dx, &dy, &dz, particles[i], subParticles[j]);
particles[i].f.x += dx * d;
particles[i].f.y += dy * d;
particles[i].f.z += dz * d;
}//end-for (int j = 0; j < blockDim.x; j++){
__syncthreads();
}//end-for (int blk = 0; blk < gridDim.x; blk++){
}
__global__ void particleParticleVelocityPosition_k(tpParticle *particles, const double dt){
int i = blockDim.x * blockIdx.x + threadIdx.x;
particles[i].v.x += dt * particles[i].f.x;
particles[i].v.y += dt * particles[i].f.y;
particles[i].v.z += dt * particles[i].f.z;
particles[i].p.x += dt * particles[i].v.x;
particles[i].p.y += dt * particles[i].v.y;
particles[i].p.z += dt * particles[i].v.z;
}
void particleParticle (tpParticle *h_particles, int nParticles, int timesteps, double dt){
int threadsF = BLOCK_SIZE_F,
blocksF = nParticles / BLOCK_SIZE_F,
threadsVP = BLOCK_SIZE_VP,
blocksVP = nParticles / BLOCK_SIZE_VP;
tpParticle *d_particles;
if (nParticles < BLOCK_SIZE_F){
blocksF = 1;
threadsF = nParticles;
}
if (nParticles < BLOCK_SIZE_VP){
blocksVP = 1;
threadsVP = nParticles;
}
assert(hipDeviceReset()== hipSuccess);
assert(hipMalloc((void**) &d_particles, nParticles * sizeof(tpParticle)) == hipSuccess);
assert(hipMemcpy(d_particles, h_particles, nParticles * sizeof(tpParticle), hipMemcpyHostToDevice) == hipSuccess);
assert( ((nParticles % threadsF) == 0) && ((nParticles % threadsVP) == 0) );
//fprintf(stdout, "\n B(%d) T(%d) \n", blocks, threads);
//fprintf(stdout, "Shared memory allocated %d\n", threads * sizeof(tpParticle));
for (int t = 0; t < timesteps; t++){
//setup_kernel<<<blocos, threads,0, mStreams[i] >>>(time (NULL) + offset, mStates+offset);
particleParticleForces_k<<<blocksF, threadsF, threadsF * sizeof(tpParticle)>>>(d_particles, dt);
//assert( cudaDeviceSynchronize() == cudaSuccess);
particleParticleVelocityPosition_k<<<blocksVP, threadsVP>>>(d_particles, dt);
//assert( cudaDeviceSynchronize() == cudaSuccess);
}//end-for (int t = 0; t < timesteps; t++){
assert(hipMemcpy(h_particles, d_particles, nParticles * sizeof(tpParticle), hipMemcpyDeviceToHost) == hipSuccess);
hipFree(d_particles);
}
//--------------------------------------------------------------------------------------------------------
void printLog(tpParticle *particles, int nParticles, int timestep);
void initialCondition(tpParticle *particles, int nParticles);
int main (int ac, char **av){
int timesteps = atoi(av[1]),
nParticles = atoi(av[2]),
flagSave = atoi(av[3]);
double dt = 0.00001f;
tpParticle *particles = NULL;
fprintf(stdout, "\nParcile system particle to particle \n");
fprintf(stdout, "Memory used %lu bytes \n", nParticles * sizeof(tpParticle));
particles = (tpParticle *) malloc ( nParticles * sizeof(tpParticle));
assert(particles != NULL);
initialCondition(particles, nParticles);
particleParticle(particles, nParticles, timesteps, dt);
if (flagSave == 1)
printLog(particles, nParticles, timesteps);
free(particles);
}
void printLog(tpParticle *particles, int nParticles, int timestep){
char fileName[128];
sprintf(fileName, "%s-%d-log.bin", __FILE__, timestep);
fprintf(stdout, "Saving file [%s] ", fileName); fflush(stdout);
FILE *ptr = fopen(fileName, "wb+");
//fwrite ((const void*)particles , sizeof(tpParticle), nParticles, ptr);
for(int i = 0; i < nParticles; i++)
fprintf(ptr, "%d \t %.10f %.10f %.10f \t %.10f %.10f %.10f \t %.10f %.10f %.10f \n", i, particles[i].p.x, particles[i].p.y, particles[i].p.z, particles[i].v.x, particles[i].v.y, particles[i].v.z, particles[i].f.x, particles[i].f.y, particles[i].f.z);
fclose(ptr);
fprintf(stdout, "[OK]\n"); fflush(stdout);
}
void initialCondition(tpParticle *particles, int nParticles){
srand(42);
memset(particles, 0x00, nParticles * sizeof(tpParticle));
for (int i = 0; i < nParticles ; i++){
particles[i].p.x = 2.0 * (rand() / (double)RAND_MAX) - 1.0;
particles[i].p.y = 2.0 * (rand() / (double)RAND_MAX) - 1.0;
particles[i].p.z = 2.0 * (rand() / (double)RAND_MAX) - 1.0;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24particleParticleForces_kP10stParticled
.globl _Z24particleParticleForces_kP10stParticled
.p2align 8
.type _Z24particleParticleForces_kP10stParticled,@function
_Z24particleParticleForces_kP10stParticled:
s_load_b32 s6, s[0:1], 0x10
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s6, 0
s_cbranch_scc1 .LBB0_7
s_load_b32 s4, s[2:3], 0xc
s_load_b64 s[2:3], s[0:1], 0x0
v_mad_u32_u24 v15, v0, 0x48, 0
s_mov_b32 s5, 0x3e112e0b
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s4, 0xffff
s_mov_b32 s4, 0xe826d695
v_mad_u64_u32 v[1:2], null, s15, s1, v[0:1]
s_cmp_lg_u32 s1, 0
s_cselect_b32 s0, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v2, 0, 1, s0
v_mad_i64_i32 v[9:10], null, v1, 0x48, s[2:3]
s_delay_alu instid0(VALU_DEP_2)
v_cmp_ne_u32_e64 s0, 1, v2
s_branch .LBB0_3
.LBB0_2:
s_add_i32 s7, s7, 1
s_waitcnt_vscnt null, 0x0
s_cmp_eq_u32 s7, s6
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
.LBB0_3:
v_mad_u64_u32 v[1:2], null, s7, s1, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s0
v_mad_u64_u32 v[20:21], null, v1, 0x48, s[2:3]
s_clause 0x4
global_load_b128 v[1:4], v[20:21], off offset:56
global_load_b128 v[5:8], v[20:21], off offset:48
global_load_b128 v[11:14], v[20:21], off offset:32
global_load_b128 v[16:19], v[20:21], off offset:16
global_load_b128 v[20:23], v[20:21], off
s_waitcnt vmcnt(4)
ds_store_2addr_b64 v15, v[1:2], v[3:4] offset0:7 offset1:8
s_waitcnt vmcnt(3)
ds_store_2addr_b64 v15, v[5:6], v[7:8] offset0:6 offset1:7
s_waitcnt vmcnt(2)
ds_store_2addr_b64 v15, v[11:12], v[13:14] offset0:4 offset1:5
s_waitcnt vmcnt(1)
ds_store_2addr_b64 v15, v[16:17], v[18:19] offset0:2 offset1:3
s_waitcnt vmcnt(0)
ds_store_2addr_b64 v15, v[20:21], v[22:23] offset1:1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB0_2
v_add_co_u32 v5, vcc_lo, v9, 64
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v10, vcc_lo
s_mov_b32 s8, 0
s_mov_b32 s9, s1
s_clause 0x3
global_load_b128 v[1:4], v[5:6], off offset:-16
global_load_b64 v[11:12], v[5:6], off
global_load_b128 v[5:8], v[9:10], off
global_load_b64 v[13:14], v[9:10], off offset:16
.LBB0_5:
v_mov_b32_e32 v20, s8
s_add_i32 s9, s9, -1
s_addk_i32 s8, 0x48
s_cmp_eq_u32 s9, 0
ds_load_2addr_b64 v[16:19], v20 offset1:1
ds_load_b64 v[20:21], v20 offset:16
s_waitcnt vmcnt(1) lgkmcnt(1)
v_add_f64 v[18:19], v[7:8], -v[18:19]
v_add_f64 v[16:17], v[5:6], -v[16:17]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f64 v[20:21], v[13:14], -v[20:21]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[22:23], v[18:19], v[18:19]
v_fma_f64 v[22:23], v[16:17], v[16:17], v[22:23]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[22:23], v[20:21], v[20:21], v[22:23]
v_add_f64 v[22:23], v[22:23], s[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[22:23]
v_cndmask_b32_e64 v24, 0, 1, vcc_lo
v_lshlrev_b32_e32 v24, 8, v24
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[22:23], v[22:23], v24
v_rsq_f64_e32 v[24:25], v[22:23]
s_waitcnt_depctr 0xfff
v_mul_f64 v[26:27], v[22:23], v[24:25]
v_mul_f64 v[24:25], v[24:25], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[28:29], -v[24:25], v[26:27], 0.5
v_fma_f64 v[26:27], v[26:27], v[28:29], v[26:27]
v_fma_f64 v[24:25], v[24:25], v[28:29], v[24:25]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[28:29], -v[26:27], v[26:27], v[22:23]
v_fma_f64 v[26:27], v[28:29], v[24:25], v[26:27]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[28:29], -v[26:27], v[26:27], v[22:23]
v_fma_f64 v[24:25], v[28:29], v[24:25], v[26:27]
v_cndmask_b32_e64 v26, 0, 0xffffff80, vcc_lo
v_cmp_class_f64_e64 vcc_lo, v[22:23], 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[24:25], v[24:25], v26
v_dual_cndmask_b32 v23, v25, v23 :: v_dual_cndmask_b32 v22, v24, v22
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[24:25], null, v[22:23], v[22:23], 1.0
v_div_scale_f64 v[30:31], vcc_lo, 1.0, v[22:23], 1.0
v_rcp_f64_e32 v[26:27], v[24:25]
s_waitcnt_depctr 0xfff
v_fma_f64 v[28:29], -v[24:25], v[26:27], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[26:27], v[26:27], v[28:29], v[26:27]
v_fma_f64 v[28:29], -v[24:25], v[26:27], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[26:27], v[26:27], v[28:29], v[26:27]
v_mul_f64 v[28:29], v[30:31], v[26:27]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[24:25], -v[24:25], v[28:29], v[30:31]
v_div_fmas_f64 v[24:25], v[24:25], v[26:27], v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[22:23], v[24:25], v[22:23], 1.0
v_fma_f64 v[1:2], v[16:17], v[22:23], v[1:2]
v_fma_f64 v[3:4], v[18:19], v[22:23], v[3:4]
v_fma_f64 v[11:12], v[20:21], v[22:23], v[11:12]
s_cbranch_scc0 .LBB0_5
v_add_co_u32 v5, vcc_lo, v9, 64
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v10, vcc_lo
s_clause 0x1
global_store_b128 v[5:6], v[1:4], off offset:-16
global_store_b64 v[5:6], v[11:12], off
s_branch .LBB0_2
.LBB0_7:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24particleParticleForces_kP10stParticled
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24particleParticleForces_kP10stParticled, .Lfunc_end0-_Z24particleParticleForces_kP10stParticled
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z34particleParticleVelocityPosition_kP10stParticled
.globl _Z34particleParticleVelocityPosition_kP10stParticled
.p2align 8
.type _Z34particleParticleVelocityPosition_kP10stParticled,@function
_Z34particleParticleVelocityPosition_kP10stParticled:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mad_i64_i32 v[16:17], null, v1, 0x48, s[0:1]
s_clause 0x4
global_load_b128 v[0:3], v[16:17], off offset:16
global_load_b128 v[4:7], v[16:17], off offset:48
global_load_b128 v[8:11], v[16:17], off offset:32
global_load_b64 v[18:19], v[16:17], off offset:64
global_load_b128 v[12:15], v[16:17], off
s_waitcnt vmcnt(3)
v_fma_f64 v[2:3], v[4:5], s[2:3], v[2:3]
s_waitcnt vmcnt(2)
v_fma_f64 v[4:5], v[6:7], s[2:3], v[8:9]
s_waitcnt vmcnt(1)
v_fma_f64 v[6:7], v[18:19], s[2:3], v[10:11]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[8:9], v[2:3], s[2:3], v[12:13]
v_fma_f64 v[10:11], v[4:5], s[2:3], v[14:15]
s_delay_alu instid0(VALU_DEP_3)
v_fma_f64 v[0:1], v[6:7], s[2:3], v[0:1]
s_clause 0x2
global_store_b128 v[16:17], v[4:7], off offset:32
global_store_b128 v[16:17], v[8:11], off
global_store_b128 v[16:17], v[0:3], off offset:16
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z34particleParticleVelocityPosition_kP10stParticled
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z34particleParticleVelocityPosition_kP10stParticled, .Lfunc_end1-_Z34particleParticleVelocityPosition_kP10stParticled
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24particleParticleForces_kP10stParticled
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24particleParticleForces_kP10stParticled.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z34particleParticleVelocityPosition_kP10stParticled
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z34particleParticleVelocityPosition_kP10stParticled.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#include <time.h>
#include <math.h>
#include <string.h>
#define EPSILON 1E-9
#define BLOCK_SIZE_F 512 //Work with blocks of 512 threads due to double precision - shared memory
#define BLOCK_SIZE_VP 1024 //Work with blocks of 512 threads due to double precision - shared memory
/*Declarando as structs de particula e forca*/
struct stCoord{
double x,
y,
z;
};
typedef struct stCoord tpCoord;
struct stParticle
{
tpCoord p,
v,
f;
};
typedef struct stParticle tpParticle;
//--------------------------------------------------------------------------------------------------------
__device__ double distance( double* dx,
double* dy,
double* dz,
const tpParticle A,
const tpParticle B){
double x = A.p.x - B.p.x;
double y = A.p.y - B.p.y;
double z = A.p.z - B.p.z;
*dx = x; *dy = y; *dz = z;
x *= x; y *= y; z *= z;
return 1.0 / sqrt((double)x + y + z + EPSILON);
}
__global__ void particleParticleForces_k(tpParticle *particles, const double dt){
extern __shared__ tpParticle subParticles[];
int i = blockDim.x * blockIdx.x + threadIdx.x;
// __shared__ tpParticle subParticles[BLOCK_SIZE];
for (int blk = 0; blk < gridDim.x; blk++){
subParticles[threadIdx.x] = particles[ blockDim.x * blk + threadIdx.x];
__syncthreads();
for (int j = 0; j < blockDim.x; j++){
double dx = 0.0f, dy = 0.0f, dz = 0.0f;
double d = distance(&dx, &dy, &dz, particles[i], subParticles[j]);
particles[i].f.x += dx * d;
particles[i].f.y += dy * d;
particles[i].f.z += dz * d;
}//end-for (int j = 0; j < blockDim.x; j++){
__syncthreads();
}//end-for (int blk = 0; blk < gridDim.x; blk++){
}
__global__ void particleParticleVelocityPosition_k(tpParticle *particles, const double dt){
int i = blockDim.x * blockIdx.x + threadIdx.x;
particles[i].v.x += dt * particles[i].f.x;
particles[i].v.y += dt * particles[i].f.y;
particles[i].v.z += dt * particles[i].f.z;
particles[i].p.x += dt * particles[i].v.x;
particles[i].p.y += dt * particles[i].v.y;
particles[i].p.z += dt * particles[i].v.z;
}
void particleParticle (tpParticle *h_particles, int nParticles, int timesteps, double dt){
int threadsF = BLOCK_SIZE_F,
blocksF = nParticles / BLOCK_SIZE_F,
threadsVP = BLOCK_SIZE_VP,
blocksVP = nParticles / BLOCK_SIZE_VP;
tpParticle *d_particles;
if (nParticles < BLOCK_SIZE_F){
blocksF = 1;
threadsF = nParticles;
}
if (nParticles < BLOCK_SIZE_VP){
blocksVP = 1;
threadsVP = nParticles;
}
assert(hipDeviceReset()== hipSuccess);
assert(hipMalloc((void**) &d_particles, nParticles * sizeof(tpParticle)) == hipSuccess);
assert(hipMemcpy(d_particles, h_particles, nParticles * sizeof(tpParticle), hipMemcpyHostToDevice) == hipSuccess);
assert( ((nParticles % threadsF) == 0) && ((nParticles % threadsVP) == 0) );
//fprintf(stdout, "\n B(%d) T(%d) \n", blocks, threads);
//fprintf(stdout, "Shared memory allocated %d\n", threads * sizeof(tpParticle));
for (int t = 0; t < timesteps; t++){
//setup_kernel<<<blocos, threads,0, mStreams[i] >>>(time (NULL) + offset, mStates+offset);
particleParticleForces_k<<<blocksF, threadsF, threadsF * sizeof(tpParticle)>>>(d_particles, dt);
//assert( cudaDeviceSynchronize() == cudaSuccess);
particleParticleVelocityPosition_k<<<blocksVP, threadsVP>>>(d_particles, dt);
//assert( cudaDeviceSynchronize() == cudaSuccess);
}//end-for (int t = 0; t < timesteps; t++){
assert(hipMemcpy(h_particles, d_particles, nParticles * sizeof(tpParticle), hipMemcpyDeviceToHost) == hipSuccess);
hipFree(d_particles);
}
//--------------------------------------------------------------------------------------------------------
void printLog(tpParticle *particles, int nParticles, int timestep);
void initialCondition(tpParticle *particles, int nParticles);
int main (int ac, char **av){
int timesteps = atoi(av[1]),
nParticles = atoi(av[2]),
flagSave = atoi(av[3]);
double dt = 0.00001f;
tpParticle *particles = NULL;
fprintf(stdout, "\nParcile system particle to particle \n");
fprintf(stdout, "Memory used %lu bytes \n", nParticles * sizeof(tpParticle));
particles = (tpParticle *) malloc ( nParticles * sizeof(tpParticle));
assert(particles != NULL);
initialCondition(particles, nParticles);
particleParticle(particles, nParticles, timesteps, dt);
if (flagSave == 1)
printLog(particles, nParticles, timesteps);
free(particles);
}
void printLog(tpParticle *particles, int nParticles, int timestep){
char fileName[128];
sprintf(fileName, "%s-%d-log.bin", __FILE__, timestep);
fprintf(stdout, "Saving file [%s] ", fileName); fflush(stdout);
FILE *ptr = fopen(fileName, "wb+");
//fwrite ((const void*)particles , sizeof(tpParticle), nParticles, ptr);
for(int i = 0; i < nParticles; i++)
fprintf(ptr, "%d \t %.10f %.10f %.10f \t %.10f %.10f %.10f \t %.10f %.10f %.10f \n", i, particles[i].p.x, particles[i].p.y, particles[i].p.z, particles[i].v.x, particles[i].v.y, particles[i].v.z, particles[i].f.x, particles[i].f.y, particles[i].f.z);
fclose(ptr);
fprintf(stdout, "[OK]\n"); fflush(stdout);
}
void initialCondition(tpParticle *particles, int nParticles){
srand(42);
memset(particles, 0x00, nParticles * sizeof(tpParticle));
for (int i = 0; i < nParticles ; i++){
particles[i].p.x = 2.0 * (rand() / (double)RAND_MAX) - 1.0;
particles[i].p.y = 2.0 * (rand() / (double)RAND_MAX) - 1.0;
particles[i].p.z = 2.0 * (rand() / (double)RAND_MAX) - 1.0;
}
} | .text
.file "main-n-bodies.hip"
.globl _Z39__device_stub__particleParticleForces_kP10stParticled # -- Begin function _Z39__device_stub__particleParticleForces_kP10stParticled
.p2align 4, 0x90
.type _Z39__device_stub__particleParticleForces_kP10stParticled,@function
_Z39__device_stub__particleParticleForces_kP10stParticled: # @_Z39__device_stub__particleParticleForces_kP10stParticled
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movsd %xmm0, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z24particleParticleForces_kP10stParticled, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z39__device_stub__particleParticleForces_kP10stParticled, .Lfunc_end0-_Z39__device_stub__particleParticleForces_kP10stParticled
.cfi_endproc
# -- End function
.globl _Z49__device_stub__particleParticleVelocityPosition_kP10stParticled # -- Begin function _Z49__device_stub__particleParticleVelocityPosition_kP10stParticled
.p2align 4, 0x90
.type _Z49__device_stub__particleParticleVelocityPosition_kP10stParticled,@function
_Z49__device_stub__particleParticleVelocityPosition_kP10stParticled: # @_Z49__device_stub__particleParticleVelocityPosition_kP10stParticled
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movsd %xmm0, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z34particleParticleVelocityPosition_kP10stParticled, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z49__device_stub__particleParticleVelocityPosition_kP10stParticled, .Lfunc_end1-_Z49__device_stub__particleParticleVelocityPosition_kP10stParticled
.cfi_endproc
# -- End function
.globl _Z16particleParticleP10stParticleiid # -- Begin function _Z16particleParticleP10stParticleiid
.p2align 4, 0x90
.type _Z16particleParticleP10stParticleiid,@function
_Z16particleParticleP10stParticleiid: # @_Z16particleParticleP10stParticleiid
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movsd %xmm0, 88(%rsp) # 8-byte Spill
# kill: def $esi killed $esi def $rsi
testl %edx, %edx
jle .LBB2_11
# %bb.1: # %.lr.ph
movl %edx, %ebx
movl $1024, %eax # imm = 0x400
movl $1, %edi
movl $1, %ecx
cmpl $1024, %esi # imm = 0x400
cmovll %esi, %eax
jl .LBB2_3
# %bb.2: # %select.false.sink
leal 1023(%rsi), %ecx
testl %esi, %esi
cmovnsl %esi, %ecx
sarl $10, %ecx
.LBB2_3: # %select.end
movabsq $4294967296, %rdx # imm = 0x100000000
movl $512, %r8d # imm = 0x200
cmpl $512, %esi # imm = 0x200
cmovll %esi, %r8d
jl .LBB2_5
# %bb.4: # %select.false.sink53
leal 511(%rsi), %edi
testl %esi, %esi
cmovnsl %esi, %edi
sarl $9, %edi
.LBB2_5: # %select.end52
movslq %r8d, %rsi
leaq (,%rsi,8), %r8
leaq (%r8,%r8,8), %r14
movl %edi, %r15d
orq %rdx, %r15
movl %esi, %r12d
orq %rdx, %r12
movl %ecx, %r13d
orq %rdx, %r13
movl %eax, %ebp
orq %rdx, %rbp
jmp .LBB2_6
.p2align 4, 0x90
.LBB2_10: # in Loop: Header=BB2_6 Depth=1
decl %ebx
je .LBB2_11
.LBB2_6: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
movq %r14, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7: # in Loop: Header=BB2_6 Depth=1
movsd 88(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 56(%rsp)
leaq 96(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z24particleParticleForces_kP10stParticled, %edi
leaq 64(%rsp), %r9
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8: # in Loop: Header=BB2_6 Depth=1
movq %r13, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9: # in Loop: Header=BB2_6 Depth=1
movsd 88(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 56(%rsp)
leaq 96(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z34particleParticleVelocityPosition_kP10stParticled, %edi
leaq 64(%rsp), %r9
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_10
.LBB2_11: # %._crit_edge
callq hipFree
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z16particleParticleP10stParticleiid, .Lfunc_end2-_Z16particleParticleP10stParticleiid
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI3_1:
.quad 0xbff0000000000000 # double -1
.LCPI3_2:
.quad 0x3ee4f8b580000000 # double 9.9999997473787516E-6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r15
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 16(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 24(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq stdout(%rip), %rcx
movl $.L.str, %edi
movl $38, %esi
movl $1, %edx
callq fwrite@PLT
movq stdout(%rip), %rdi
movslq %r14d, %rbp
leaq (,%rbp,8), %rax
leaq (%rax,%rax,8), %r13
movl $.L.str.1, %esi
movq %r13, %rdx
xorl %eax, %eax
callq fprintf
movq %r13, %rdi
callq malloc
movq %rax, %r12
movl $42, %edi
callq srand
movq %r12, %rdi
xorl %esi, %esi
movq %r13, %rdx
callq memset@PLT
testl %ebp, %ebp
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader.i
movl %r14d, %eax
shlq $3, %rax
leaq (%rax,%rax,8), %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
addsd %xmm0, %xmm0
movsd .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm1, %xmm0
movsd %xmm0, (%r12,%rbp)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
addsd %xmm0, %xmm0
addsd .LCPI3_1(%rip), %xmm0
movsd %xmm0, 8(%r12,%rbp)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
addsd %xmm0, %xmm0
addsd .LCPI3_1(%rip), %xmm0
movsd %xmm0, 16(%r12,%rbp)
addq $72, %rbp
cmpq %rbp, %r13
jne .LBB3_2
.LBB3_3: # %_Z16initialConditionP10stParticlei.exit
movsd .LCPI3_2(%rip), %xmm0 # xmm0 = mem[0],zero
movl %r14d, %esi
movl %ebx, %edx
callq _Z16particleParticleP10stParticleiid
cmpl $1, %r15d
jne .LBB3_5
# %bb.4:
movq %r12, %rdi
movl %r14d, %esi
movl %ebx, %edx
callq _Z8printLogP10stParticleii
.LBB3_5:
movq %r12, %rdi
callq free
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z16initialConditionP10stParticlei
.LCPI4_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI4_1:
.quad 0xbff0000000000000 # double -1
.text
.globl _Z16initialConditionP10stParticlei
.p2align 4, 0x90
.type _Z16initialConditionP10stParticlei,@function
_Z16initialConditionP10stParticlei: # @_Z16initialConditionP10stParticlei
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movl $42, %edi
callq srand
movslq %ebp, %r14
leaq (,%r14,8), %rax
leaq (%rax,%rax,8), %rdx
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
testl %r14d, %r14d
jle .LBB4_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %eax
shlq $3, %rax
leaq (%rax,%rax,8), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd .LCPI4_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
addsd %xmm0, %xmm0
movsd .LCPI4_1(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm1, %xmm0
movsd %xmm0, (%rbx,%r15)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI4_0(%rip), %xmm0
addsd %xmm0, %xmm0
addsd .LCPI4_1(%rip), %xmm0
movsd %xmm0, 8(%rbx,%r15)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI4_0(%rip), %xmm0
addsd %xmm0, %xmm0
addsd .LCPI4_1(%rip), %xmm0
movsd %xmm0, 16(%rbx,%r15)
addq $72, %r15
cmpq %r15, %r14
jne .LBB4_2
.LBB4_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z16initialConditionP10stParticlei, .Lfunc_end4-_Z16initialConditionP10stParticlei
.cfi_endproc
# -- End function
.globl _Z8printLogP10stParticleii # -- Begin function _Z8printLogP10stParticleii
.p2align 4, 0x90
.type _Z8printLogP10stParticleii,@function
_Z8printLogP10stParticleii: # @_Z8printLogP10stParticleii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ecx
movl %esi, %ebp
movq %rdi, %rbx
leaq 16(%rsp), %r14
movl $.L.str.2, %esi
movl $.L.str.3, %edx
movq %r14, %rdi
xorl %eax, %eax
callq sprintf
movq stdout(%rip), %rdi
movl $.L.str.4, %esi
movq %r14, %rdx
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
callq fflush
movl $.L.str.5, %esi
movq %r14, %rdi
callq fopen
movq %rax, %r14
testl %ebp, %ebp
jle .LBB5_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r12d
addq $64, %rbx
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB5_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd -64(%rbx), %xmm0 # xmm0 = mem[0],zero
movsd -56(%rbx), %xmm1 # xmm1 = mem[0],zero
movsd -48(%rbx), %xmm2 # xmm2 = mem[0],zero
movsd -40(%rbx), %xmm3 # xmm3 = mem[0],zero
movsd -32(%rbx), %xmm4 # xmm4 = mem[0],zero
movsd -24(%rbx), %xmm5 # xmm5 = mem[0],zero
movsd -16(%rbx), %xmm6 # xmm6 = mem[0],zero
movsd -8(%rbx), %xmm7 # xmm7 = mem[0],zero
movsd (%rbx), %xmm8 # xmm8 = mem[0],zero
movsd %xmm8, (%rsp)
movl $.L.str.6, %esi
movq %r14, %rdi
movl %r15d, %edx
movb $8, %al
callq fprintf
incq %r15
addq $72, %rbx
cmpq %r15, %r12
jne .LBB5_2
.LBB5_3: # %._crit_edge
movq %r14, %rdi
callq fclose
movq stdout(%rip), %rcx
movl $.L.str.7, %edi
movl $5, %esi
movl $1, %edx
callq fwrite@PLT
movq stdout(%rip), %rdi
callq fflush
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z8printLogP10stParticleii, .Lfunc_end5-_Z8printLogP10stParticleii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24particleParticleForces_kP10stParticled, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z34particleParticleVelocityPosition_kP10stParticled, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24particleParticleForces_kP10stParticled,@object # @_Z24particleParticleForces_kP10stParticled
.section .rodata,"a",@progbits
.globl _Z24particleParticleForces_kP10stParticled
.p2align 3, 0x0
_Z24particleParticleForces_kP10stParticled:
.quad _Z39__device_stub__particleParticleForces_kP10stParticled
.size _Z24particleParticleForces_kP10stParticled, 8
.type _Z34particleParticleVelocityPosition_kP10stParticled,@object # @_Z34particleParticleVelocityPosition_kP10stParticled
.globl _Z34particleParticleVelocityPosition_kP10stParticled
.p2align 3, 0x0
_Z34particleParticleVelocityPosition_kP10stParticled:
.quad _Z49__device_stub__particleParticleVelocityPosition_kP10stParticled
.size _Z34particleParticleVelocityPosition_kP10stParticled, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nParcile system particle to particle \n"
.size .L.str, 39
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Memory used %lu bytes \n"
.size .L.str.1, 24
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%s-%d-log.bin"
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/marzam/HPC-Aula/main/exemplos/problems-profile/nbody-cuda-profile/main-n-bodies.hip"
.size .L.str.3, 141
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Saving file [%s] "
.size .L.str.4, 18
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "wb+"
.size .L.str.5, 4
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d \t %.10f %.10f %.10f \t %.10f %.10f %.10f \t %.10f %.10f %.10f \n"
.size .L.str.6, 65
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "[OK]\n"
.size .L.str.7, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z24particleParticleForces_kP10stParticled"
.size .L__unnamed_1, 43
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z34particleParticleVelocityPosition_kP10stParticled"
.size .L__unnamed_2, 53
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__particleParticleForces_kP10stParticled
.addrsig_sym _Z49__device_stub__particleParticleVelocityPosition_kP10stParticled
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24particleParticleForces_kP10stParticled
.addrsig_sym _Z34particleParticleVelocityPosition_kP10stParticled
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002eb84_00000000-6_main-n-bodies.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z8distancePdS_S_10stParticleS0_
.type _Z8distancePdS_S_10stParticleS0_, @function
_Z8distancePdS_S_10stParticleS0_:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z8distancePdS_S_10stParticleS0_, .-_Z8distancePdS_S_10stParticleS0_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/marzam/HPC-Aula/main/exemplos/problems-profile/nbody-cuda-profile/main-n-bodies.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%s-%d-log.bin"
.LC2:
.string "Saving file [%s] "
.LC3:
.string "wb+"
.section .rodata.str1.8
.align 8
.LC4:
.string "%d \t %.10f %.10f %.10f \t %.10f %.10f %.10f \t %.10f %.10f %.10f \n"
.section .rodata.str1.1
.LC5:
.string "[OK]\n"
.text
.globl _Z8printLogP10stParticleii
.type _Z8printLogP10stParticleii, @function
_Z8printLogP10stParticleii:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $144, %rsp
.cfi_def_cfa_offset 192
movq %rdi, %rbx
movl %esi, %r13d
movl %edx, %r9d
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movq %rsp, %rbp
leaq .LC0(%rip), %r8
leaq .LC1(%rip), %rcx
movl $128, %edx
movl $2, %esi
movq %rbp, %rdi
call __sprintf_chk@PLT
movq %rbp, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
leaq .LC3(%rip), %rsi
movq %rbp, %rdi
call fopen@PLT
movq %rax, %r12
testl %r13d, %r13d
jle .L6
movl $0, %ebp
leaq .LC4(%rip), %r14
.L7:
movsd 56(%rbx), %xmm7
movsd 48(%rbx), %xmm6
movsd 40(%rbx), %xmm5
movsd 32(%rbx), %xmm4
movsd 24(%rbx), %xmm3
movsd 16(%rbx), %xmm2
movsd 8(%rbx), %xmm1
movsd (%rbx), %xmm0
subq $8, %rsp
.cfi_def_cfa_offset 200
pushq 64(%rbx)
.cfi_def_cfa_offset 208
movl %ebp, %ecx
movq %r14, %rdx
movl $2, %esi
movq %r12, %rdi
movl $8, %eax
call __fprintf_chk@PLT
addl $1, %ebp
addq $72, %rbx
addq $16, %rsp
.cfi_def_cfa_offset 192
cmpl %ebp, %r13d
jne .L7
.L6:
movq %r12, %rdi
call fclose@PLT
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z8printLogP10stParticleii, .-_Z8printLogP10stParticleii
.globl _Z16initialConditionP10stParticlei
.type _Z16initialConditionP10stParticlei, @function
_Z16initialConditionP10stParticlei:
.LFB2061:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbp
movl %esi, %ebx
movl $42, %edi
call srand@PLT
movslq %ebx, %rax
leaq (%rax,%rax,8), %r12
salq $3, %r12
movq %r12, %rdx
movl $0, %esi
movq %rbp, %rdi
call memset@PLT
testl %ebx, %ebx
jle .L12
movq %rbp, %rbx
addq %r12, %rbp
.L14:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC6(%rip), %xmm0
addsd %xmm0, %xmm0
subsd .LC7(%rip), %xmm0
movsd %xmm0, (%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC6(%rip), %xmm0
addsd %xmm0, %xmm0
subsd .LC7(%rip), %xmm0
movsd %xmm0, 8(%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC6(%rip), %xmm0
addsd %xmm0, %xmm0
subsd .LC7(%rip), %xmm0
movsd %xmm0, 16(%rbx)
addq $72, %rbx
cmpq %rbp, %rbx
jne .L14
.L12:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z16initialConditionP10stParticlei, .-_Z16initialConditionP10stParticlei
.globl _Z56__device_stub__Z24particleParticleForces_kP10stParticledP10stParticled
.type _Z56__device_stub__Z24particleParticleForces_kP10stParticledP10stParticled, @function
_Z56__device_stub__Z24particleParticleForces_kP10stParticledP10stParticled:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movsd %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z24particleParticleForces_kP10stParticled(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z56__device_stub__Z24particleParticleForces_kP10stParticledP10stParticled, .-_Z56__device_stub__Z24particleParticleForces_kP10stParticledP10stParticled
.globl _Z24particleParticleForces_kP10stParticled
.type _Z24particleParticleForces_kP10stParticled, @function
_Z24particleParticleForces_kP10stParticled:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z56__device_stub__Z24particleParticleForces_kP10stParticledP10stParticled
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z24particleParticleForces_kP10stParticled, .-_Z24particleParticleForces_kP10stParticled
.globl _Z66__device_stub__Z34particleParticleVelocityPosition_kP10stParticledP10stParticled
.type _Z66__device_stub__Z34particleParticleVelocityPosition_kP10stParticledP10stParticled, @function
_Z66__device_stub__Z34particleParticleVelocityPosition_kP10stParticledP10stParticled:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movsd %xmm0, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z34particleParticleVelocityPosition_kP10stParticled(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z66__device_stub__Z34particleParticleVelocityPosition_kP10stParticledP10stParticled, .-_Z66__device_stub__Z34particleParticleVelocityPosition_kP10stParticledP10stParticled
.globl _Z34particleParticleVelocityPosition_kP10stParticled
.type _Z34particleParticleVelocityPosition_kP10stParticled, @function
_Z34particleParticleVelocityPosition_kP10stParticled:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z66__device_stub__Z34particleParticleVelocityPosition_kP10stParticledP10stParticled
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z34particleParticleVelocityPosition_kP10stParticled, .-_Z34particleParticleVelocityPosition_kP10stParticled
.globl _Z16particleParticleP10stParticleiid
.type _Z16particleParticleP10stParticleiid, @function
_Z16particleParticleP10stParticleiid:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %esi, %ebp
movl %edx, %r13d
movsd %xmm0, 8(%rsp)
leal 511(%rsi), %r12d
testl %esi, %esi
cmovns %esi, %r12d
sarl $9, %r12d
cmpl $511, %esi
jle .L39
cmpl $1023, %esi
jle .L40
leal 1023(%rsi), %r14d
testl %esi, %esi
cmovns %esi, %r14d
sarl $10, %r14d
movl $512, %r15d
movl $1024, %ebp
.L34:
testl %r13d, %r13d
jle .L35
movslq %r15d, %rax
leaq (%rax,%rax,8), %rax
salq $3, %rax
movq %rax, (%rsp)
movl $0, %ebx
jmp .L38
.L39:
movl %esi, %r15d
movl $1, %r12d
movl $1, %r14d
jmp .L34
.L40:
movl $512, %r15d
movl $1, %r14d
jmp .L34
.L43:
movsd 8(%rsp), %xmm0
movl $0, %edi
call _Z56__device_stub__Z24particleParticleForces_kP10stParticledP10stParticled
jmp .L36
.L37:
addl $1, %ebx
cmpl %ebx, %r13d
je .L35
.L38:
movl %r15d, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl %r12d, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movq (%rsp), %r8
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L43
.L36:
movl %ebp, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl %r14d, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L37
movsd 8(%rsp), %xmm0
movl $0, %edi
call _Z66__device_stub__Z34particleParticleVelocityPosition_kP10stParticledP10stParticled
jmp .L37
.L35:
movl $0, %edi
call cudaFree@PLT
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z16particleParticleP10stParticleiid, .-_Z16particleParticleP10stParticleiid
.section .rodata.str1.8
.align 8
.LC8:
.string "\nParcile system particle to particle \n"
.section .rodata.str1.1
.LC9:
.string "Memory used %lu bytes \n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rsi, %r12
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebp
movq 16(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %r13d
movq 24(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movslq %ebx, %rbx
leaq (%rbx,%rbx,8), %rbx
salq $3, %rbx
movq %rbx, %rcx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbx
movl %r13d, %esi
movq %rax, %rdi
call _Z16initialConditionP10stParticlei
movsd .LC10(%rip), %xmm0
movl %ebp, %edx
movl %r13d, %esi
movq %rbx, %rdi
call _Z16particleParticleP10stParticleiid
cmpl $1, %r12d
je .L47
.L45:
movq %rbx, %rdi
call free@PLT
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
movl %ebp, %edx
movl %r13d, %esi
movq %rbx, %rdi
call _Z8printLogP10stParticleii
jmp .L45
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC11:
.string "_Z34particleParticleVelocityPosition_kP10stParticled"
.align 8
.LC12:
.string "_Z24particleParticleForces_kP10stParticled"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z34particleParticleVelocityPosition_kP10stParticled(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z24particleParticleForces_kP10stParticled(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long -4194304
.long 1105199103
.align 8
.LC7:
.long 0
.long 1072693248
.align 8
.LC10:
.long -2147483648
.long 1055193269
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main-n-bodies.hip"
.globl _Z39__device_stub__particleParticleForces_kP10stParticled # -- Begin function _Z39__device_stub__particleParticleForces_kP10stParticled
.p2align 4, 0x90
.type _Z39__device_stub__particleParticleForces_kP10stParticled,@function
_Z39__device_stub__particleParticleForces_kP10stParticled: # @_Z39__device_stub__particleParticleForces_kP10stParticled
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movsd %xmm0, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z24particleParticleForces_kP10stParticled, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z39__device_stub__particleParticleForces_kP10stParticled, .Lfunc_end0-_Z39__device_stub__particleParticleForces_kP10stParticled
.cfi_endproc
# -- End function
.globl _Z49__device_stub__particleParticleVelocityPosition_kP10stParticled # -- Begin function _Z49__device_stub__particleParticleVelocityPosition_kP10stParticled
.p2align 4, 0x90
.type _Z49__device_stub__particleParticleVelocityPosition_kP10stParticled,@function
_Z49__device_stub__particleParticleVelocityPosition_kP10stParticled: # @_Z49__device_stub__particleParticleVelocityPosition_kP10stParticled
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movsd %xmm0, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z34particleParticleVelocityPosition_kP10stParticled, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z49__device_stub__particleParticleVelocityPosition_kP10stParticled, .Lfunc_end1-_Z49__device_stub__particleParticleVelocityPosition_kP10stParticled
.cfi_endproc
# -- End function
.globl _Z16particleParticleP10stParticleiid # -- Begin function _Z16particleParticleP10stParticleiid
.p2align 4, 0x90
.type _Z16particleParticleP10stParticleiid,@function
_Z16particleParticleP10stParticleiid: # @_Z16particleParticleP10stParticleiid
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movsd %xmm0, 88(%rsp) # 8-byte Spill
# kill: def $esi killed $esi def $rsi
testl %edx, %edx
jle .LBB2_11
# %bb.1: # %.lr.ph
movl %edx, %ebx
movl $1024, %eax # imm = 0x400
movl $1, %edi
movl $1, %ecx
cmpl $1024, %esi # imm = 0x400
cmovll %esi, %eax
jl .LBB2_3
# %bb.2: # %select.false.sink
leal 1023(%rsi), %ecx
testl %esi, %esi
cmovnsl %esi, %ecx
sarl $10, %ecx
.LBB2_3: # %select.end
movabsq $4294967296, %rdx # imm = 0x100000000
movl $512, %r8d # imm = 0x200
cmpl $512, %esi # imm = 0x200
cmovll %esi, %r8d
jl .LBB2_5
# %bb.4: # %select.false.sink53
leal 511(%rsi), %edi
testl %esi, %esi
cmovnsl %esi, %edi
sarl $9, %edi
.LBB2_5: # %select.end52
movslq %r8d, %rsi
leaq (,%rsi,8), %r8
leaq (%r8,%r8,8), %r14
movl %edi, %r15d
orq %rdx, %r15
movl %esi, %r12d
orq %rdx, %r12
movl %ecx, %r13d
orq %rdx, %r13
movl %eax, %ebp
orq %rdx, %rbp
jmp .LBB2_6
.p2align 4, 0x90
.LBB2_10: # in Loop: Header=BB2_6 Depth=1
decl %ebx
je .LBB2_11
.LBB2_6: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
movq %r14, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7: # in Loop: Header=BB2_6 Depth=1
movsd 88(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 56(%rsp)
leaq 96(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z24particleParticleForces_kP10stParticled, %edi
leaq 64(%rsp), %r9
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8: # in Loop: Header=BB2_6 Depth=1
movq %r13, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9: # in Loop: Header=BB2_6 Depth=1
movsd 88(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 56(%rsp)
leaq 96(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movl $_Z34particleParticleVelocityPosition_kP10stParticled, %edi
leaq 64(%rsp), %r9
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_10
.LBB2_11: # %._crit_edge
callq hipFree
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z16particleParticleP10stParticleiid, .Lfunc_end2-_Z16particleParticleP10stParticleiid
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI3_1:
.quad 0xbff0000000000000 # double -1
.LCPI3_2:
.quad 0x3ee4f8b580000000 # double 9.9999997473787516E-6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r15
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 16(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 24(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq stdout(%rip), %rcx
movl $.L.str, %edi
movl $38, %esi
movl $1, %edx
callq fwrite@PLT
movq stdout(%rip), %rdi
movslq %r14d, %rbp
leaq (,%rbp,8), %rax
leaq (%rax,%rax,8), %r13
movl $.L.str.1, %esi
movq %r13, %rdx
xorl %eax, %eax
callq fprintf
movq %r13, %rdi
callq malloc
movq %rax, %r12
movl $42, %edi
callq srand
movq %r12, %rdi
xorl %esi, %esi
movq %r13, %rdx
callq memset@PLT
testl %ebp, %ebp
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader.i
movl %r14d, %eax
shlq $3, %rax
leaq (%rax,%rax,8), %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_2: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
addsd %xmm0, %xmm0
movsd .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm1, %xmm0
movsd %xmm0, (%r12,%rbp)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
addsd %xmm0, %xmm0
addsd .LCPI3_1(%rip), %xmm0
movsd %xmm0, 8(%r12,%rbp)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
addsd %xmm0, %xmm0
addsd .LCPI3_1(%rip), %xmm0
movsd %xmm0, 16(%r12,%rbp)
addq $72, %rbp
cmpq %rbp, %r13
jne .LBB3_2
.LBB3_3: # %_Z16initialConditionP10stParticlei.exit
movsd .LCPI3_2(%rip), %xmm0 # xmm0 = mem[0],zero
movl %r14d, %esi
movl %ebx, %edx
callq _Z16particleParticleP10stParticleiid
cmpl $1, %r15d
jne .LBB3_5
# %bb.4:
movq %r12, %rdi
movl %r14d, %esi
movl %ebx, %edx
callq _Z8printLogP10stParticleii
.LBB3_5:
movq %r12, %rdi
callq free
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z16initialConditionP10stParticlei
.LCPI4_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI4_1:
.quad 0xbff0000000000000 # double -1
.text
.globl _Z16initialConditionP10stParticlei
.p2align 4, 0x90
.type _Z16initialConditionP10stParticlei,@function
_Z16initialConditionP10stParticlei: # @_Z16initialConditionP10stParticlei
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movl $42, %edi
callq srand
movslq %ebp, %r14
leaq (,%r14,8), %rax
leaq (%rax,%rax,8), %rdx
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
testl %r14d, %r14d
jle .LBB4_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %eax
shlq $3, %rax
leaq (%rax,%rax,8), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd .LCPI4_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
addsd %xmm0, %xmm0
movsd .LCPI4_1(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm1, %xmm0
movsd %xmm0, (%rbx,%r15)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI4_0(%rip), %xmm0
addsd %xmm0, %xmm0
addsd .LCPI4_1(%rip), %xmm0
movsd %xmm0, 8(%rbx,%r15)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI4_0(%rip), %xmm0
addsd %xmm0, %xmm0
addsd .LCPI4_1(%rip), %xmm0
movsd %xmm0, 16(%rbx,%r15)
addq $72, %r15
cmpq %r15, %r14
jne .LBB4_2
.LBB4_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z16initialConditionP10stParticlei, .Lfunc_end4-_Z16initialConditionP10stParticlei
.cfi_endproc
# -- End function
.globl _Z8printLogP10stParticleii # -- Begin function _Z8printLogP10stParticleii
.p2align 4, 0x90
.type _Z8printLogP10stParticleii,@function
_Z8printLogP10stParticleii: # @_Z8printLogP10stParticleii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ecx
movl %esi, %ebp
movq %rdi, %rbx
leaq 16(%rsp), %r14
movl $.L.str.2, %esi
movl $.L.str.3, %edx
movq %r14, %rdi
xorl %eax, %eax
callq sprintf
movq stdout(%rip), %rdi
movl $.L.str.4, %esi
movq %r14, %rdx
xorl %eax, %eax
callq fprintf
movq stdout(%rip), %rdi
callq fflush
movl $.L.str.5, %esi
movq %r14, %rdi
callq fopen
movq %rax, %r14
testl %ebp, %ebp
jle .LBB5_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r12d
addq $64, %rbx
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB5_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd -64(%rbx), %xmm0 # xmm0 = mem[0],zero
movsd -56(%rbx), %xmm1 # xmm1 = mem[0],zero
movsd -48(%rbx), %xmm2 # xmm2 = mem[0],zero
movsd -40(%rbx), %xmm3 # xmm3 = mem[0],zero
movsd -32(%rbx), %xmm4 # xmm4 = mem[0],zero
movsd -24(%rbx), %xmm5 # xmm5 = mem[0],zero
movsd -16(%rbx), %xmm6 # xmm6 = mem[0],zero
movsd -8(%rbx), %xmm7 # xmm7 = mem[0],zero
movsd (%rbx), %xmm8 # xmm8 = mem[0],zero
movsd %xmm8, (%rsp)
movl $.L.str.6, %esi
movq %r14, %rdi
movl %r15d, %edx
movb $8, %al
callq fprintf
incq %r15
addq $72, %rbx
cmpq %r15, %r12
jne .LBB5_2
.LBB5_3: # %._crit_edge
movq %r14, %rdi
callq fclose
movq stdout(%rip), %rcx
movl $.L.str.7, %edi
movl $5, %esi
movl $1, %edx
callq fwrite@PLT
movq stdout(%rip), %rdi
callq fflush
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z8printLogP10stParticleii, .Lfunc_end5-_Z8printLogP10stParticleii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24particleParticleForces_kP10stParticled, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z34particleParticleVelocityPosition_kP10stParticled, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24particleParticleForces_kP10stParticled,@object # @_Z24particleParticleForces_kP10stParticled
.section .rodata,"a",@progbits
.globl _Z24particleParticleForces_kP10stParticled
.p2align 3, 0x0
_Z24particleParticleForces_kP10stParticled:
.quad _Z39__device_stub__particleParticleForces_kP10stParticled
.size _Z24particleParticleForces_kP10stParticled, 8
.type _Z34particleParticleVelocityPosition_kP10stParticled,@object # @_Z34particleParticleVelocityPosition_kP10stParticled
.globl _Z34particleParticleVelocityPosition_kP10stParticled
.p2align 3, 0x0
_Z34particleParticleVelocityPosition_kP10stParticled:
.quad _Z49__device_stub__particleParticleVelocityPosition_kP10stParticled
.size _Z34particleParticleVelocityPosition_kP10stParticled, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nParcile system particle to particle \n"
.size .L.str, 39
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Memory used %lu bytes \n"
.size .L.str.1, 24
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%s-%d-log.bin"
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/marzam/HPC-Aula/main/exemplos/problems-profile/nbody-cuda-profile/main-n-bodies.hip"
.size .L.str.3, 141
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Saving file [%s] "
.size .L.str.4, 18
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "wb+"
.size .L.str.5, 4
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d \t %.10f %.10f %.10f \t %.10f %.10f %.10f \t %.10f %.10f %.10f \n"
.size .L.str.6, 65
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "[OK]\n"
.size .L.str.7, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z24particleParticleForces_kP10stParticled"
.size .L__unnamed_1, 43
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z34particleParticleVelocityPosition_kP10stParticled"
.size .L__unnamed_2, 53
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__particleParticleForces_kP10stParticled
.addrsig_sym _Z49__device_stub__particleParticleVelocityPosition_kP10stParticled
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24particleParticleForces_kP10stParticled
.addrsig_sym _Z34particleParticleVelocityPosition_kP10stParticled
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<cstdio>
extern "C" {
__global__
void HelloWorld(){
int thid = (blockIdx.x * blockDim.x) + threadIdx.x;
printf("Hello World! thread #%d\n", thid);
}
} | code for sm_80
Function : HelloWorld
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0070*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fca0007f1e0ff */
/*0080*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe400000e06ff */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*00a0*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e260000000a00 */
/*00b0*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0003e40000100800 */
/*00c0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*00d0*/ MOV R11, 0x140 ; /* 0x00000140000b7802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R20, 0xc0 ; /* 0x000000c000147802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fc40000000f00 */
/*0100*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x002fe40000000f00 */
/*0110*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0120*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0130*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x001fea0003c00000 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<cstdio>
extern "C" {
__global__
void HelloWorld(){
int thid = (blockIdx.x * blockDim.x) + threadIdx.x;
printf("Hello World! thread #%d\n", thid);
}
} | .file "tmpxft_0011f832_00000000-6_helloWorldDriverAPI.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10HelloWorldvv
.type _Z29__device_stub__Z10HelloWorldvv, @function
_Z29__device_stub__Z10HelloWorldvv:
.LFB2081:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq HelloWorld(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z29__device_stub__Z10HelloWorldvv, .-_Z29__device_stub__Z10HelloWorldvv
.globl HelloWorld
.type HelloWorld, @function
HelloWorld:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10HelloWorldvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size HelloWorld, .-HelloWorld
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "HelloWorld"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq HelloWorld(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<cstdio>
extern "C" {
__global__
void HelloWorld(){
int thid = (blockIdx.x * blockDim.x) + threadIdx.x;
printf("Hello World! thread #%d\n", thid);
}
} | #include <hip/hip_runtime.h>
#include<cstdio>
extern "C" {
__global__
void HelloWorld(){
int thid = (blockIdx.x * blockDim.x) + threadIdx.x;
printf("Hello World! thread #%d\n", thid);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<cstdio>
extern "C" {
__global__
void HelloWorld(){
int thid = (blockIdx.x * blockDim.x) + threadIdx.x;
printf("Hello World! thread #%d\n", thid);
}
} | .text
.file "helloWorldDriverAPI.hip"
.globl __device_stub__HelloWorld # -- Begin function __device_stub__HelloWorld
.p2align 4, 0x90
.type __device_stub__HelloWorld,@function
__device_stub__HelloWorld: # @__device_stub__HelloWorld
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $HelloWorld, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size __device_stub__HelloWorld, .Lfunc_end0-__device_stub__HelloWorld
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $HelloWorld, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type HelloWorld,@object # @HelloWorld
.section .rodata,"a",@progbits
.globl HelloWorld
.p2align 3, 0x0
HelloWorld:
.quad __device_stub__HelloWorld
.size HelloWorld, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "HelloWorld"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__HelloWorld
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym HelloWorld
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011f832_00000000-6_helloWorldDriverAPI.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10HelloWorldvv
.type _Z29__device_stub__Z10HelloWorldvv, @function
_Z29__device_stub__Z10HelloWorldvv:
.LFB2081:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq HelloWorld(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z29__device_stub__Z10HelloWorldvv, .-_Z29__device_stub__Z10HelloWorldvv
.globl HelloWorld
.type HelloWorld, @function
HelloWorld:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10HelloWorldvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size HelloWorld, .-HelloWorld
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "HelloWorld"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq HelloWorld(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "helloWorldDriverAPI.hip"
.globl __device_stub__HelloWorld # -- Begin function __device_stub__HelloWorld
.p2align 4, 0x90
.type __device_stub__HelloWorld,@function
__device_stub__HelloWorld: # @__device_stub__HelloWorld
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $HelloWorld, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size __device_stub__HelloWorld, .Lfunc_end0-__device_stub__HelloWorld
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $HelloWorld, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type HelloWorld,@object # @HelloWorld
.section .rodata,"a",@progbits
.globl HelloWorld
.p2align 3, 0x0
HelloWorld:
.quad __device_stub__HelloWorld
.size HelloWorld, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "HelloWorld"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__HelloWorld
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym HelloWorld
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //Referred Dr.Swenson's Sample code and Nvidia PDF for some code syntaxes and Excerpts. File read logic reference taken from online sources
//like geeks for geeks and cplusplus.com.
/*
Akshaya Nagarajan
ECE 6122 P2
GTID: 903319262
*/
#include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <vector>
#include <string>
#include <fstream>
#include <sstream>
#define T_P_B 1024 //Threads per block for cuda kernel
//struct to store values from conf file
struct init_values {
std::string dimension;
float k;
int timesteps, width, height, depth;
float default_temp;
std::vector<int> heatsource;
std::vector<float> fixed_temp;
};
struct init_values init;
//Logic to read conf file
void init_readconf(std::string conf)
{
std::ifstream conf_file(conf.c_str());
std::string line;
std::vector<std::string> conf_vector;
while (std::getline(conf_file, line)) {
conf_vector.push_back(line);
}
std::vector<std::string> temp;
std::vector<int> temp2;
std::vector<float> temp3;
for (int i = 0; i < conf_vector.size(); ++i)
{
if ((conf_vector[i].empty() == 0) && (conf_vector[i].find("#") != 0))
{
temp.push_back(conf_vector[i]);
}
}
//initialize values non comma separated
std::stringstream dim0(temp[0]);
dim0 >> init.dimension;
std::stringstream dim1(temp[1]);
dim1 >> init.k;
std::stringstream dim2(temp[2]);
dim2 >> init.timesteps;
std::stringstream dim3(temp[4]);
dim3 >> init.default_temp;
//initialize values comma separated
if (init.dimension == "2D")
{
std::stringstream dim4;
dim4 << temp[3];
int a;
//First get the total grid size
while(dim4 >> a)
{
if (dim4.peek() == ',')
{
dim4.ignore();
}
temp2.push_back(a);
}
init.width = temp2[0];
init.height = temp2[1];
for (int i = 5; i < temp.size(); ++i)
{
std::stringstream dim5;
dim5 << temp[i];
float b;
//Get the heat source values
while(dim5 >> b)
{
if (dim5.peek() == ',')
{
dim5.ignore();
}
temp3.push_back(b);
}
}
//Put heat source values into vectors
for (int i = 0; i < temp3.size(); ++i)
{
init.heatsource.push_back(temp3[i]);
}
for (int i = 4; i < temp3.size(); i= i+5)
{
init.fixed_temp.push_back(temp3[i]);
}
for (int i = 4; i < init.heatsource.size(); i= i+4)
{
init.heatsource.erase(init.heatsource.begin() + i);
}
}
else {
std::stringstream dim4;
dim4 << temp[3];
int a;
//First get the total grid size
while(dim4 >> a)
{
if (dim4.peek() == ',')
{
dim4.ignore();
}
temp2.push_back(a);
}
init.width = temp2[0];
init.height = temp2[1];
init.depth = temp2[2];
for (int i = 5; i < temp.size(); ++i)
{
std::stringstream dim5;
dim5 << temp[i];
float b;
//Get the heat source values
while(dim5 >> b)
{
if (dim5.peek() == ',')
{
dim5.ignore();
}
temp3.push_back(b);
}
}
//Put heat source values into vectors
for (int i = 0; i < temp3.size(); ++i)
{
init.heatsource.push_back(temp3[i]);
}
for (int i = 6; i < temp3.size(); i= i+7)
{
init.fixed_temp.push_back(temp3[i]);
}
for (int i = 6; i < init.heatsource.size(); i= i+6)
{
init.heatsource.erase(init.heatsource.begin() + i);
}
}
}
//kernel function for 2D
__global__ void twodfunc(float *arraymain, float *arraytemp, float *arraybool, float k, int width, int height, int N) {
int idx = threadIdx.x + blockIdx.x * blockDim.x; //Get thread Ids
if (idx < N)
{
float top = arraymain[idx + width];
float bottom = arraymain[idx - width];
float left = arraymain[idx -1];
float right = arraymain[idx +1];
//Heat Diffusion formula for 8 corner and 1 general case in 2D
//for 1st element
if (idx == 0)
{
arraytemp[idx] = arraymain[idx] + arraybool[idx]*(k*(arraymain[idx] + top + arraymain[idx] + right - 4*arraymain[idx]));
}
//for last element
else if (idx == (width*height -1))
{
arraytemp[idx] = arraymain[idx] + arraybool[idx]*(k*(arraymain[idx] + bottom + arraymain[idx] + left - 4*arraymain[idx]));
}
//for leftcorner top
else if ((idx + width == width*height) && (idx%width == 0))
{
arraytemp[idx] = arraymain[idx] + arraybool[idx]*(k*(arraymain[idx] + bottom + arraymain[idx] + right - 4*arraymain[idx]));
}
//for rightcorner bottom
else if ((idx - width < 0) && (idx%width == (width-1)))
{
arraytemp[idx] = arraymain[idx] + arraybool[idx]*(k*(arraymain[idx] + top + arraymain[idx] + left - 4*arraymain[idx]));
}
//for top
else if (idx + width > width*height)
{
arraytemp[idx] = arraymain[idx] + arraybool[idx]*(k*(arraymain[idx] + bottom + left + right - 4*arraymain[idx]));
}
//for bottom
else if (idx - width < 0)
{
arraytemp[idx] = arraymain[idx] + arraybool[idx]*(k*(arraymain[idx] + top + left + right - 4*arraymain[idx]));
}
//for left
else if (idx%width == 0)
{
arraytemp[idx] = arraymain[idx] + arraybool[idx]*(k*(arraymain[idx] + top + bottom + right - 4*arraymain[idx]));
}
//for right
else if (idx%width == (width-1))
{
arraytemp[idx] = arraymain[idx] + arraybool[idx]*(k*(arraymain[idx] + top + left + bottom - 4*arraymain[idx]));
}
//general cases
else
{
arraytemp[idx] = arraymain[idx] + arraybool[idx]*(k*(top + bottom + left + right - 4*arraymain[idx]));
}
}
}
//kernel function for 3D
__global__ void threedfunc(float *arraymain, float *arraytemp, float *arraybool, float k, int width, int height, int depth, int N) {
int idx = threadIdx.x + blockIdx.x * blockDim.x; //Get thread Ids
if (idx < N)
{
//Setting by default to its own values for corner cases
float top = arraymain[idx];
float bottom = arraymain[idx];
float left = arraymain[idx];
float right = arraymain[idx];
float front = arraymain[idx];
float back = arraymain[idx];
//index computation for non corner cases (in order to avoid many loops covering the individual cases)
int index;
//for top
index = idx + width*depth;
if (index < N)
{
top = arraymain[index];
}
//for bottom
index = idx - width*depth;
if (index >= 0)
{
bottom = arraymain[index];
}
//for front
index = idx%(width*depth);
index = index/width;
if (index != 0)
{
front = arraymain[idx - width];
}
//for back
if (index != (depth-1))
{
back = arraymain[idx + width];
}
//for left
index = idx%width;
if (index != 0)
{
left = arraymain[idx-1];
}
//for right
if (index != width-1)
{
right = arraymain[idx+1];
}
//general formula for heat diffusion 3D with calculated indexes
arraytemp[idx] = arraymain[idx] + arraybool[idx]*(k*(front + back + top + bottom + left + right - 6*arraymain[idx]));
}
}
//main
int main(int argc, char* argv[]) {
init_readconf(argv[1]);
//For 2D
if (init.dimension == "2D")
{
char *filename = (char *)"heatOutput.csv";
FILE *fp;
fp = fopen(filename, "w");
float size = (init.width*init.height) * sizeof(float);
int N = init.width*init.height;
float a[N], b[N], c[N];
float *d_a, *d_b, *d_c;
for (int i = 0; i < N; ++i)
{
a[i] = init.default_temp;
b[i] = 0;
c[i] = 1;
}
//logic for conf file and array integration 2D
int index = 0;
for (int i = 0; i < init.heatsource.size(); i=i+4)
{
for (int j = init.heatsource[i+1]; j < init.heatsource[i+1]+init.heatsource[i+3]; j++)
{
for (int k = init.heatsource[i]; k < init.heatsource[i]+init.heatsource[i+2]; k++)
{
a[j*init.width + k] = init.fixed_temp[index];
c[j*init.width + k] = 0;
}
}
index++;
}
//initialize array for device
cudaMalloc((void **)&d_a, size);
cudaMalloc((void **)&d_b, size);
cudaMalloc((void **)&d_c, size);
//copy to device from host
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_c, c, size, cudaMemcpyHostToDevice);
float *swap;
//Looping timesteps number of times to get the final grid
for (int i = 0; i < init.timesteps; i++)
{
twodfunc<<<(N + T_P_B-1) / T_P_B, T_P_B>>>(d_a, d_b, d_c, init.k, init.width, init.height, N); //Call kernel function
cudaDeviceSynchronize();
swap = d_a;
d_a = d_b;
d_b = swap;
}
//copy to host from device
cudaMemcpy(a, d_a, size, cudaMemcpyDeviceToHost);
cudaMemcpy(b, d_b, size, cudaMemcpyDeviceToHost);
// //Print the Final Grid to CSV file
for(int i = 0; i < N; i++) {
if(i!=N-1 && i%init.width == init.width-1 && i != 0)
fprintf(fp, "%f\n", a[i]);
else if ((i==0) || (i!=N-1 && i%init.width !=init.width-1))
fprintf(fp, "%f, ", a[i]);
else fprintf(fp, "%f\n", a[i]);
}
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
fclose(fp);
}
//For 3D
else
{
char *filename = (char *)"heatOutput.csv";
FILE *fp;
fp = fopen(filename, "w");
float size = (init.width*init.height*init.depth) * sizeof(float);
int N = init.width*init.height*init.depth;
float a[N], b[N], c[N];
float *d_a, *d_b, *d_c;
for (int i = 0; i < N; ++i)
{
a[i] = init.default_temp;
b[i] = 0;
c[i] = 1;
}
//logic for conf file and array integration 3D
int index = 0;
for (int i = 0; i < init.heatsource.size(); i=i+6)
{
for (int p = init.heatsource[i+1]; p < init.heatsource[i+1]+init.heatsource[i+4]; p++)
{
for (int k = init.heatsource[i+2]; k < init.heatsource[i+2]+init.heatsource[i+5]; k++)
{
for (int j = init.heatsource[i]; j < init.heatsource[i]+init.heatsource[i+3]; j++)
{
a[p*init.width*init.depth + j + k*init.width] = init.fixed_temp[index];
c[p*init.width*init.depth + j + k*init.width] = 0;
}
}
}
index++;
}
//initialize array for device
cudaMalloc((void **)&d_a, size);
cudaMalloc((void **)&d_b, size);
cudaMalloc((void **)&d_c, size);
//copy to device from host
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_c, c, size, cudaMemcpyHostToDevice);
float *swap;
//Looping timesteps number of times to get the final grid
for (int i = 0; i < init.timesteps; i++)
{
threedfunc<<<(N + T_P_B-1) / T_P_B, T_P_B>>>(d_a, d_b, d_c, init.k, init.width, init.height, init.depth, N); //Call kernel function
cudaDeviceSynchronize();
swap = d_a;
d_a = d_b;
d_b = swap;
}
//copy to host from device
cudaMemcpy(a, d_a, size, cudaMemcpyDeviceToHost);
cudaMemcpy(b, d_b, size, cudaMemcpyDeviceToHost);
//Print the Final Grid to CSV file
for (int k = 0; k < init.depth; k++)
{
for (int p = 0; p < init.height; p++)
{
for (int j = 0; j < init.width; j++)
{
if (j == init.width-1)
fprintf(fp, "%f\n", a[p*init.width*init.depth + j + k*init.width]);
else fprintf(fp, "%f, ", a[p*init.width*init.depth + j + k*init.width]);
}
}
fprintf(fp, "\n");
}
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
fclose(fp);
}
return 0;
} | //Referred Dr.Swenson's Sample code and Nvidia PDF for some code syntaxes and Excerpts. File read logic reference taken from online sources
//like geeks for geeks and cplusplus.com.
/*
Akshaya Nagarajan
ECE 6122 P2
GTID: 903319262
*/
#include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <vector>
#include <string>
#include <fstream>
#include <sstream>
#define T_P_B 1024 //Threads per block for cuda kernel
//struct to store values from conf file
struct init_values {
std::string dimension;
float k;
int timesteps, width, height, depth;
float default_temp;
std::vector<int> heatsource;
std::vector<float> fixed_temp;
};
struct init_values init;
//Logic to read conf file
void init_readconf(std::string conf)
{
std::ifstream conf_file(conf.c_str());
std::string line;
std::vector<std::string> conf_vector;
while (std::getline(conf_file, line)) {
conf_vector.push_back(line);
}
std::vector<std::string> temp;
std::vector<int> temp2;
std::vector<float> temp3;
for (int i = 0; i < conf_vector.size(); ++i)
{
if ((conf_vector[i].empty() == 0) && (conf_vector[i].find("#") != 0))
{
temp.push_back(conf_vector[i]);
}
}
//initialize values non comma separated
std::stringstream dim0(temp[0]);
dim0 >> init.dimension;
std::stringstream dim1(temp[1]);
dim1 >> init.k;
std::stringstream dim2(temp[2]);
dim2 >> init.timesteps;
std::stringstream dim3(temp[4]);
dim3 >> init.default_temp;
//initialize values comma separated
if (init.dimension == "2D")
{
std::stringstream dim4;
dim4 << temp[3];
int a;
//First get the total grid size
while(dim4 >> a)
{
if (dim4.peek() == ',')
{
dim4.ignore();
}
temp2.push_back(a);
}
init.width = temp2[0];
init.height = temp2[1];
for (int i = 5; i < temp.size(); ++i)
{
std::stringstream dim5;
dim5 << temp[i];
float b;
//Get the heat source values
while(dim5 >> b)
{
if (dim5.peek() == ',')
{
dim5.ignore();
}
temp3.push_back(b);
}
}
//Put heat source values into vectors
for (int i = 0; i < temp3.size(); ++i)
{
init.heatsource.push_back(temp3[i]);
}
for (int i = 4; i < temp3.size(); i= i+5)
{
init.fixed_temp.push_back(temp3[i]);
}
for (int i = 4; i < init.heatsource.size(); i= i+4)
{
init.heatsource.erase(init.heatsource.begin() + i);
}
}
else {
std::stringstream dim4;
dim4 << temp[3];
int a;
//First get the total grid size
while(dim4 >> a)
{
if (dim4.peek() == ',')
{
dim4.ignore();
}
temp2.push_back(a);
}
init.width = temp2[0];
init.height = temp2[1];
init.depth = temp2[2];
for (int i = 5; i < temp.size(); ++i)
{
std::stringstream dim5;
dim5 << temp[i];
float b;
//Get the heat source values
while(dim5 >> b)
{
if (dim5.peek() == ',')
{
dim5.ignore();
}
temp3.push_back(b);
}
}
//Put heat source values into vectors
for (int i = 0; i < temp3.size(); ++i)
{
init.heatsource.push_back(temp3[i]);
}
for (int i = 6; i < temp3.size(); i= i+7)
{
init.fixed_temp.push_back(temp3[i]);
}
for (int i = 6; i < init.heatsource.size(); i= i+6)
{
init.heatsource.erase(init.heatsource.begin() + i);
}
}
}
//kernel function for 2D
__global__ void twodfunc(float *arraymain, float *arraytemp, float *arraybool, float k, int width, int height, int N) {
int idx = threadIdx.x + blockIdx.x * blockDim.x; //Get thread Ids
if (idx < N)
{
float top = arraymain[idx + width];
float bottom = arraymain[idx - width];
float left = arraymain[idx -1];
float right = arraymain[idx +1];
//Heat Diffusion formula for 8 corner and 1 general case in 2D
//for 1st element
if (idx == 0)
{
arraytemp[idx] = arraymain[idx] + arraybool[idx]*(k*(arraymain[idx] + top + arraymain[idx] + right - 4*arraymain[idx]));
}
//for last element
else if (idx == (width*height -1))
{
arraytemp[idx] = arraymain[idx] + arraybool[idx]*(k*(arraymain[idx] + bottom + arraymain[idx] + left - 4*arraymain[idx]));
}
//for leftcorner top
else if ((idx + width == width*height) && (idx%width == 0))
{
arraytemp[idx] = arraymain[idx] + arraybool[idx]*(k*(arraymain[idx] + bottom + arraymain[idx] + right - 4*arraymain[idx]));
}
//for rightcorner bottom
else if ((idx - width < 0) && (idx%width == (width-1)))
{
arraytemp[idx] = arraymain[idx] + arraybool[idx]*(k*(arraymain[idx] + top + arraymain[idx] + left - 4*arraymain[idx]));
}
//for top
else if (idx + width > width*height)
{
arraytemp[idx] = arraymain[idx] + arraybool[idx]*(k*(arraymain[idx] + bottom + left + right - 4*arraymain[idx]));
}
//for bottom
else if (idx - width < 0)
{
arraytemp[idx] = arraymain[idx] + arraybool[idx]*(k*(arraymain[idx] + top + left + right - 4*arraymain[idx]));
}
//for left
else if (idx%width == 0)
{
arraytemp[idx] = arraymain[idx] + arraybool[idx]*(k*(arraymain[idx] + top + bottom + right - 4*arraymain[idx]));
}
//for right
else if (idx%width == (width-1))
{
arraytemp[idx] = arraymain[idx] + arraybool[idx]*(k*(arraymain[idx] + top + left + bottom - 4*arraymain[idx]));
}
//general cases
else
{
arraytemp[idx] = arraymain[idx] + arraybool[idx]*(k*(top + bottom + left + right - 4*arraymain[idx]));
}
}
}
//kernel function for 3D
__global__ void threedfunc(float *arraymain, float *arraytemp, float *arraybool, float k, int width, int height, int depth, int N) {
int idx = threadIdx.x + blockIdx.x * blockDim.x; //Get thread Ids
if (idx < N)
{
//Setting by default to its own values for corner cases
float top = arraymain[idx];
float bottom = arraymain[idx];
float left = arraymain[idx];
float right = arraymain[idx];
float front = arraymain[idx];
float back = arraymain[idx];
//index computation for non corner cases (in order to avoid many loops covering the individual cases)
int index;
//for top
index = idx + width*depth;
if (index < N)
{
top = arraymain[index];
}
//for bottom
index = idx - width*depth;
if (index >= 0)
{
bottom = arraymain[index];
}
//for front
index = idx%(width*depth);
index = index/width;
if (index != 0)
{
front = arraymain[idx - width];
}
//for back
if (index != (depth-1))
{
back = arraymain[idx + width];
}
//for left
index = idx%width;
if (index != 0)
{
left = arraymain[idx-1];
}
//for right
if (index != width-1)
{
right = arraymain[idx+1];
}
//general formula for heat diffusion 3D with calculated indexes
arraytemp[idx] = arraymain[idx] + arraybool[idx]*(k*(front + back + top + bottom + left + right - 6*arraymain[idx]));
}
}
//main
int main(int argc, char* argv[]) {
init_readconf(argv[1]);
//For 2D
if (init.dimension == "2D")
{
char *filename = (char *)"heatOutput.csv";
FILE *fp;
fp = fopen(filename, "w");
float size = (init.width*init.height) * sizeof(float);
int N = init.width*init.height;
float a[N], b[N], c[N];
float *d_a, *d_b, *d_c;
for (int i = 0; i < N; ++i)
{
a[i] = init.default_temp;
b[i] = 0;
c[i] = 1;
}
//logic for conf file and array integration 2D
int index = 0;
for (int i = 0; i < init.heatsource.size(); i=i+4)
{
for (int j = init.heatsource[i+1]; j < init.heatsource[i+1]+init.heatsource[i+3]; j++)
{
for (int k = init.heatsource[i]; k < init.heatsource[i]+init.heatsource[i+2]; k++)
{
a[j*init.width + k] = init.fixed_temp[index];
c[j*init.width + k] = 0;
}
}
index++;
}
//initialize array for device
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
hipMalloc((void **)&d_c, size);
//copy to device from host
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
hipMemcpy(d_c, c, size, hipMemcpyHostToDevice);
float *swap;
//Looping timesteps number of times to get the final grid
for (int i = 0; i < init.timesteps; i++)
{
twodfunc<<<(N + T_P_B-1) / T_P_B, T_P_B>>>(d_a, d_b, d_c, init.k, init.width, init.height, N); //Call kernel function
hipDeviceSynchronize();
swap = d_a;
d_a = d_b;
d_b = swap;
}
//copy to host from device
hipMemcpy(a, d_a, size, hipMemcpyDeviceToHost);
hipMemcpy(b, d_b, size, hipMemcpyDeviceToHost);
// //Print the Final Grid to CSV file
for(int i = 0; i < N; i++) {
if(i!=N-1 && i%init.width == init.width-1 && i != 0)
fprintf(fp, "%f\n", a[i]);
else if ((i==0) || (i!=N-1 && i%init.width !=init.width-1))
fprintf(fp, "%f, ", a[i]);
else fprintf(fp, "%f\n", a[i]);
}
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
fclose(fp);
}
//For 3D
else
{
char *filename = (char *)"heatOutput.csv";
FILE *fp;
fp = fopen(filename, "w");
float size = (init.width*init.height*init.depth) * sizeof(float);
int N = init.width*init.height*init.depth;
float a[N], b[N], c[N];
float *d_a, *d_b, *d_c;
for (int i = 0; i < N; ++i)
{
a[i] = init.default_temp;
b[i] = 0;
c[i] = 1;
}
//logic for conf file and array integration 3D
int index = 0;
for (int i = 0; i < init.heatsource.size(); i=i+6)
{
for (int p = init.heatsource[i+1]; p < init.heatsource[i+1]+init.heatsource[i+4]; p++)
{
for (int k = init.heatsource[i+2]; k < init.heatsource[i+2]+init.heatsource[i+5]; k++)
{
for (int j = init.heatsource[i]; j < init.heatsource[i]+init.heatsource[i+3]; j++)
{
a[p*init.width*init.depth + j + k*init.width] = init.fixed_temp[index];
c[p*init.width*init.depth + j + k*init.width] = 0;
}
}
}
index++;
}
//initialize array for device
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
hipMalloc((void **)&d_c, size);
//copy to device from host
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
hipMemcpy(d_c, c, size, hipMemcpyHostToDevice);
float *swap;
//Looping timesteps number of times to get the final grid
for (int i = 0; i < init.timesteps; i++)
{
threedfunc<<<(N + T_P_B-1) / T_P_B, T_P_B>>>(d_a, d_b, d_c, init.k, init.width, init.height, init.depth, N); //Call kernel function
hipDeviceSynchronize();
swap = d_a;
d_a = d_b;
d_b = swap;
}
//copy to host from device
hipMemcpy(a, d_a, size, hipMemcpyDeviceToHost);
hipMemcpy(b, d_b, size, hipMemcpyDeviceToHost);
//Print the Final Grid to CSV file
for (int k = 0; k < init.depth; k++)
{
for (int p = 0; p < init.height; p++)
{
for (int j = 0; j < init.width; j++)
{
if (j == init.width-1)
fprintf(fp, "%f\n", a[p*init.width*init.depth + j + k*init.width]);
else fprintf(fp, "%f, ", a[p*init.width*init.depth + j + k*init.width]);
}
}
fprintf(fp, "\n");
}
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
fclose(fp);
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //Referred Dr.Swenson's Sample code and Nvidia PDF for some code syntaxes and Excerpts. File read logic reference taken from online sources
//like geeks for geeks and cplusplus.com.
/*
Akshaya Nagarajan
ECE 6122 P2
GTID: 903319262
*/
#include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <vector>
#include <string>
#include <fstream>
#include <sstream>
#define T_P_B 1024 //Threads per block for cuda kernel
//struct to store values from conf file
struct init_values {
std::string dimension;
float k;
int timesteps, width, height, depth;
float default_temp;
std::vector<int> heatsource;
std::vector<float> fixed_temp;
};
struct init_values init;
//Logic to read conf file
void init_readconf(std::string conf)
{
std::ifstream conf_file(conf.c_str());
std::string line;
std::vector<std::string> conf_vector;
while (std::getline(conf_file, line)) {
conf_vector.push_back(line);
}
std::vector<std::string> temp;
std::vector<int> temp2;
std::vector<float> temp3;
for (int i = 0; i < conf_vector.size(); ++i)
{
if ((conf_vector[i].empty() == 0) && (conf_vector[i].find("#") != 0))
{
temp.push_back(conf_vector[i]);
}
}
//initialize values non comma separated
std::stringstream dim0(temp[0]);
dim0 >> init.dimension;
std::stringstream dim1(temp[1]);
dim1 >> init.k;
std::stringstream dim2(temp[2]);
dim2 >> init.timesteps;
std::stringstream dim3(temp[4]);
dim3 >> init.default_temp;
//initialize values comma separated
if (init.dimension == "2D")
{
std::stringstream dim4;
dim4 << temp[3];
int a;
//First get the total grid size
while(dim4 >> a)
{
if (dim4.peek() == ',')
{
dim4.ignore();
}
temp2.push_back(a);
}
init.width = temp2[0];
init.height = temp2[1];
for (int i = 5; i < temp.size(); ++i)
{
std::stringstream dim5;
dim5 << temp[i];
float b;
//Get the heat source values
while(dim5 >> b)
{
if (dim5.peek() == ',')
{
dim5.ignore();
}
temp3.push_back(b);
}
}
//Put heat source values into vectors
for (int i = 0; i < temp3.size(); ++i)
{
init.heatsource.push_back(temp3[i]);
}
for (int i = 4; i < temp3.size(); i= i+5)
{
init.fixed_temp.push_back(temp3[i]);
}
for (int i = 4; i < init.heatsource.size(); i= i+4)
{
init.heatsource.erase(init.heatsource.begin() + i);
}
}
else {
std::stringstream dim4;
dim4 << temp[3];
int a;
//First get the total grid size
while(dim4 >> a)
{
if (dim4.peek() == ',')
{
dim4.ignore();
}
temp2.push_back(a);
}
init.width = temp2[0];
init.height = temp2[1];
init.depth = temp2[2];
for (int i = 5; i < temp.size(); ++i)
{
std::stringstream dim5;
dim5 << temp[i];
float b;
//Get the heat source values
while(dim5 >> b)
{
if (dim5.peek() == ',')
{
dim5.ignore();
}
temp3.push_back(b);
}
}
//Put heat source values into vectors
for (int i = 0; i < temp3.size(); ++i)
{
init.heatsource.push_back(temp3[i]);
}
for (int i = 6; i < temp3.size(); i= i+7)
{
init.fixed_temp.push_back(temp3[i]);
}
for (int i = 6; i < init.heatsource.size(); i= i+6)
{
init.heatsource.erase(init.heatsource.begin() + i);
}
}
}
//kernel function for 2D
__global__ void twodfunc(float *arraymain, float *arraytemp, float *arraybool, float k, int width, int height, int N) {
int idx = threadIdx.x + blockIdx.x * blockDim.x; //Get thread Ids
if (idx < N)
{
float top = arraymain[idx + width];
float bottom = arraymain[idx - width];
float left = arraymain[idx -1];
float right = arraymain[idx +1];
//Heat Diffusion formula for 8 corner and 1 general case in 2D
//for 1st element
if (idx == 0)
{
arraytemp[idx] = arraymain[idx] + arraybool[idx]*(k*(arraymain[idx] + top + arraymain[idx] + right - 4*arraymain[idx]));
}
//for last element
else if (idx == (width*height -1))
{
arraytemp[idx] = arraymain[idx] + arraybool[idx]*(k*(arraymain[idx] + bottom + arraymain[idx] + left - 4*arraymain[idx]));
}
//for leftcorner top
else if ((idx + width == width*height) && (idx%width == 0))
{
arraytemp[idx] = arraymain[idx] + arraybool[idx]*(k*(arraymain[idx] + bottom + arraymain[idx] + right - 4*arraymain[idx]));
}
//for rightcorner bottom
else if ((idx - width < 0) && (idx%width == (width-1)))
{
arraytemp[idx] = arraymain[idx] + arraybool[idx]*(k*(arraymain[idx] + top + arraymain[idx] + left - 4*arraymain[idx]));
}
//for top
else if (idx + width > width*height)
{
arraytemp[idx] = arraymain[idx] + arraybool[idx]*(k*(arraymain[idx] + bottom + left + right - 4*arraymain[idx]));
}
//for bottom
else if (idx - width < 0)
{
arraytemp[idx] = arraymain[idx] + arraybool[idx]*(k*(arraymain[idx] + top + left + right - 4*arraymain[idx]));
}
//for left
else if (idx%width == 0)
{
arraytemp[idx] = arraymain[idx] + arraybool[idx]*(k*(arraymain[idx] + top + bottom + right - 4*arraymain[idx]));
}
//for right
else if (idx%width == (width-1))
{
arraytemp[idx] = arraymain[idx] + arraybool[idx]*(k*(arraymain[idx] + top + left + bottom - 4*arraymain[idx]));
}
//general cases
else
{
arraytemp[idx] = arraymain[idx] + arraybool[idx]*(k*(top + bottom + left + right - 4*arraymain[idx]));
}
}
}
//kernel function for 3D
__global__ void threedfunc(float *arraymain, float *arraytemp, float *arraybool, float k, int width, int height, int depth, int N) {
int idx = threadIdx.x + blockIdx.x * blockDim.x; //Get thread Ids
if (idx < N)
{
//Setting by default to its own values for corner cases
float top = arraymain[idx];
float bottom = arraymain[idx];
float left = arraymain[idx];
float right = arraymain[idx];
float front = arraymain[idx];
float back = arraymain[idx];
//index computation for non corner cases (in order to avoid many loops covering the individual cases)
int index;
//for top
index = idx + width*depth;
if (index < N)
{
top = arraymain[index];
}
//for bottom
index = idx - width*depth;
if (index >= 0)
{
bottom = arraymain[index];
}
//for front
index = idx%(width*depth);
index = index/width;
if (index != 0)
{
front = arraymain[idx - width];
}
//for back
if (index != (depth-1))
{
back = arraymain[idx + width];
}
//for left
index = idx%width;
if (index != 0)
{
left = arraymain[idx-1];
}
//for right
if (index != width-1)
{
right = arraymain[idx+1];
}
//general formula for heat diffusion 3D with calculated indexes
arraytemp[idx] = arraymain[idx] + arraybool[idx]*(k*(front + back + top + bottom + left + right - 6*arraymain[idx]));
}
}
//main
int main(int argc, char* argv[]) {
init_readconf(argv[1]);
//For 2D
if (init.dimension == "2D")
{
char *filename = (char *)"heatOutput.csv";
FILE *fp;
fp = fopen(filename, "w");
float size = (init.width*init.height) * sizeof(float);
int N = init.width*init.height;
float a[N], b[N], c[N];
float *d_a, *d_b, *d_c;
for (int i = 0; i < N; ++i)
{
a[i] = init.default_temp;
b[i] = 0;
c[i] = 1;
}
//logic for conf file and array integration 2D
int index = 0;
for (int i = 0; i < init.heatsource.size(); i=i+4)
{
for (int j = init.heatsource[i+1]; j < init.heatsource[i+1]+init.heatsource[i+3]; j++)
{
for (int k = init.heatsource[i]; k < init.heatsource[i]+init.heatsource[i+2]; k++)
{
a[j*init.width + k] = init.fixed_temp[index];
c[j*init.width + k] = 0;
}
}
index++;
}
//initialize array for device
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
hipMalloc((void **)&d_c, size);
//copy to device from host
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
hipMemcpy(d_c, c, size, hipMemcpyHostToDevice);
float *swap;
//Looping timesteps number of times to get the final grid
for (int i = 0; i < init.timesteps; i++)
{
twodfunc<<<(N + T_P_B-1) / T_P_B, T_P_B>>>(d_a, d_b, d_c, init.k, init.width, init.height, N); //Call kernel function
hipDeviceSynchronize();
swap = d_a;
d_a = d_b;
d_b = swap;
}
//copy to host from device
hipMemcpy(a, d_a, size, hipMemcpyDeviceToHost);
hipMemcpy(b, d_b, size, hipMemcpyDeviceToHost);
// //Print the Final Grid to CSV file
for(int i = 0; i < N; i++) {
if(i!=N-1 && i%init.width == init.width-1 && i != 0)
fprintf(fp, "%f\n", a[i]);
else if ((i==0) || (i!=N-1 && i%init.width !=init.width-1))
fprintf(fp, "%f, ", a[i]);
else fprintf(fp, "%f\n", a[i]);
}
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
fclose(fp);
}
//For 3D
else
{
char *filename = (char *)"heatOutput.csv";
FILE *fp;
fp = fopen(filename, "w");
float size = (init.width*init.height*init.depth) * sizeof(float);
int N = init.width*init.height*init.depth;
float a[N], b[N], c[N];
float *d_a, *d_b, *d_c;
for (int i = 0; i < N; ++i)
{
a[i] = init.default_temp;
b[i] = 0;
c[i] = 1;
}
//logic for conf file and array integration 3D
int index = 0;
for (int i = 0; i < init.heatsource.size(); i=i+6)
{
for (int p = init.heatsource[i+1]; p < init.heatsource[i+1]+init.heatsource[i+4]; p++)
{
for (int k = init.heatsource[i+2]; k < init.heatsource[i+2]+init.heatsource[i+5]; k++)
{
for (int j = init.heatsource[i]; j < init.heatsource[i]+init.heatsource[i+3]; j++)
{
a[p*init.width*init.depth + j + k*init.width] = init.fixed_temp[index];
c[p*init.width*init.depth + j + k*init.width] = 0;
}
}
}
index++;
}
//initialize array for device
hipMalloc((void **)&d_a, size);
hipMalloc((void **)&d_b, size);
hipMalloc((void **)&d_c, size);
//copy to device from host
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
hipMemcpy(d_c, c, size, hipMemcpyHostToDevice);
float *swap;
//Looping timesteps number of times to get the final grid
for (int i = 0; i < init.timesteps; i++)
{
threedfunc<<<(N + T_P_B-1) / T_P_B, T_P_B>>>(d_a, d_b, d_c, init.k, init.width, init.height, init.depth, N); //Call kernel function
hipDeviceSynchronize();
swap = d_a;
d_a = d_b;
d_b = swap;
}
//copy to host from device
hipMemcpy(a, d_a, size, hipMemcpyDeviceToHost);
hipMemcpy(b, d_b, size, hipMemcpyDeviceToHost);
//Print the Final Grid to CSV file
for (int k = 0; k < init.depth; k++)
{
for (int p = 0; p < init.height; p++)
{
for (int j = 0; j < init.width; j++)
{
if (j == init.width-1)
fprintf(fp, "%f\n", a[p*init.width*init.depth + j + k*init.width]);
else fprintf(fp, "%f, ", a[p*init.width*init.depth + j + k*init.width]);
}
}
fprintf(fp, "\n");
}
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
fclose(fp);
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8twodfuncPfS_S_fiii
.globl _Z8twodfuncPfS_S_fiii
.p2align 8
.type _Z8twodfuncPfS_S_fiii,@function
_Z8twodfuncPfS_S_fiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_37
s_load_b256 s[4:11], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v5, s11, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[3:4], 2, v[5:6]
v_lshlrev_b64 v[6:7], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v8, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v7, vcc_lo
s_clause 0x1
global_load_b32 v8, v[8:9], off
global_load_b32 v0, v[3:4], off offset:4
v_cmpx_ne_u32_e32 0, v1
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_35
v_subrev_nc_u32_e32 v6, s11, v1
s_load_b32 s0, s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[9:10], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
s_clause 0x1
global_load_b32 v7, v[9:10], off
global_load_b32 v9, v[3:4], off offset:-4
s_waitcnt lgkmcnt(0)
s_mul_i32 s0, s0, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s1, s0, -1
v_cmp_ne_u32_e32 vcc_lo, s1, v1
s_and_saveexec_b32 s1, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB0_32
v_cmp_ne_u32_e64 s12, s0, v5
s_mov_b32 s3, 0
s_mov_b32 s13, exec_lo
v_cmpx_eq_u32_e64 s0, v5
s_cbranch_execz .LBB0_5
s_ashr_i32 s14, s11, 31
v_ashrrev_i32_e32 v12, 31, v1
s_add_i32 s15, s11, s14
s_and_not1_b32 s12, s12, exec_lo
s_xor_b32 s14, s15, s14
s_mov_b32 s3, exec_lo
v_cvt_f32_u32_e32 v10, s14
s_sub_i32 s15, 0, s14
v_add_nc_u32_e32 v13, v1, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v10, v10
v_xor_b32_e32 v13, v13, v12
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v10, 0x4f7ffffe, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v10, v10
v_mul_lo_u32 v11, s15, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v11, v10, v11
v_add_nc_u32_e32 v10, v10, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v10, v13, v10
v_mul_lo_u32 v10, v10, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v10, v13, v10
v_subrev_nc_u32_e32 v11, s14, v10
v_cmp_le_u32_e32 vcc_lo, s14, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v10, v10, v11, vcc_lo
v_subrev_nc_u32_e32 v11, s14, v10
v_cmp_le_u32_e32 vcc_lo, s14, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v10, v10, v11, vcc_lo
v_xor_b32_e32 v10, v10, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v10, v10, v12
v_cmp_ne_u32_e32 vcc_lo, 0, v10
s_and_b32 s14, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s12, s12, s14
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s13
s_and_saveexec_b32 s13, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s12, exec_lo, s13
s_cbranch_execz .LBB0_29
v_cmp_lt_i32_e64 s16, -1, v6
s_mov_b32 s13, 0
s_mov_b32 s14, exec_lo
s_delay_alu instid0(VALU_DEP_1)
s_mov_b32 s15, s16
v_cmpx_gt_i32_e32 0, v6
s_cbranch_execz .LBB0_8
s_ashr_i32 s15, s11, 31
v_ashrrev_i32_e32 v11, 31, v1
s_add_i32 s17, s11, s15
s_mov_b32 s13, exec_lo
s_xor_b32 s15, s17, s15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v12, v1, v11
v_cvt_f32_u32_e32 v6, s15
s_sub_i32 s17, 0, s15
v_xor_b32_e32 v12, v12, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v6, v6
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v6, 0x4f7ffffe, v6
v_cvt_u32_f32_e32 v6, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v10, s17, v6
v_mul_hi_u32 v10, v6, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v6, v6, v10
v_mul_hi_u32 v6, v12, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v6, v6, s15
v_sub_nc_u32_e32 v6, v12, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v10, s15, v6
v_cmp_le_u32_e32 vcc_lo, s15, v6
v_cndmask_b32_e32 v6, v6, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v10, s15, v6
v_cmp_le_u32_e32 vcc_lo, s15, v6
s_add_i32 s15, s11, -1
v_cndmask_b32_e32 v6, v6, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v6, v6, v11
v_sub_nc_u32_e32 v6, v6, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_ne_u32_e32 vcc_lo, s15, v6
s_and_not1_b32 s15, s16, exec_lo
s_and_b32 s17, vcc_lo, exec_lo
s_or_b32 s15, s15, s17
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s14
s_and_saveexec_b32 s14, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s14, exec_lo, s14
s_cbranch_execz .LBB0_26
v_cmp_ge_i32_e32 vcc_lo, s0, v5
s_and_saveexec_b32 s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s15, exec_lo, s0
s_cbranch_execz .LBB0_23
s_and_saveexec_b32 s0, s16
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s16, exec_lo, s0
s_cbranch_execz .LBB0_20
s_ashr_i32 s0, s11, 31
v_ashrrev_i32_e32 v10, 31, v1
s_add_i32 s17, s11, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s0, s17, s0
v_add_nc_u32_e32 v11, v1, v10
v_cvt_f32_u32_e32 v5, s0
s_sub_i32 s17, 0, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v11, v11, v10
v_rcp_iflag_f32_e32 v5, v5
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v5, 0x4f7ffffe, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v5, v5
v_mul_lo_u32 v6, s17, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v6, v5, v6
v_add_nc_u32_e32 v5, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v11, v5
v_mul_lo_u32 v5, v5, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v11, v5
v_subrev_nc_u32_e32 v6, s0, v5
v_cmp_le_u32_e32 vcc_lo, s0, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
v_subrev_nc_u32_e32 v6, s0, v5
v_cmp_le_u32_e32 vcc_lo, s0, v5
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
v_xor_b32_e32 v5, v5, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v5, v10
v_cmpx_ne_u32_e32 0, v5
s_xor_b32 s17, exec_lo, s0
s_cbranch_execz .LBB0_17
v_lshlrev_b64 v[13:14], 2, v[1:2]
global_load_b32 v10, v[3:4], off
s_add_i32 s0, s11, -1
v_add_co_u32 v11, vcc_lo, s8, v13
v_add_co_ci_u32_e32 v12, vcc_lo, s9, v14, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, s0, v5
v_add_co_u32 v5, s0, s6, v13
global_load_b32 v11, v[11:12], off
v_add_co_ci_u32_e64 v6, s0, s7, v14, s0
s_waitcnt vmcnt(1)
v_mul_f32_e32 v12, 4.0, v10
s_and_saveexec_b32 s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_14
v_add_f32_e32 v13, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v13, v13, v9
v_add_f32_e32 v13, v13, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v12, v13, v12
v_mul_f32_e32 v12, s10, v12
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v10, v11, v12
global_store_b32 v[5:6], v10, off
.LBB0_14:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_16
v_add_f32_e32 v13, v8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v13, v9, v13
v_add_f32_e32 v13, v7, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v12, v13, v12
v_mul_f32_e32 v12, s10, v12
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v10, v11, v12
global_store_b32 v[5:6], v10, off
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_17:
s_and_not1_saveexec_b32 s0, s17
s_cbranch_execz .LBB0_19
global_load_b32 v12, v[3:4], off
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, s8, v5
s_waitcnt vmcnt(1)
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
global_load_b32 v10, v[10:11], off
s_waitcnt vmcnt(1)
v_add_f32_e32 v11, v8, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v11, v7, v11
v_add_f32_e32 v11, v0, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v11, -4.0, v12
v_mul_f32_e32 v11, s10, v11
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v12, v10, v11
global_store_b32 v[5:6], v12, off
.LBB0_19:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_20:
s_and_not1_saveexec_b32 s0, s16
s_cbranch_execz .LBB0_22
global_load_b32 v12, v[3:4], off
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, s8, v5
s_waitcnt vmcnt(1)
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
global_load_b32 v10, v[10:11], off
s_waitcnt vmcnt(1)
v_add_f32_e32 v11, v8, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v11, v9, v11
v_add_f32_e32 v11, v0, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v11, -4.0, v12
v_mul_f32_e32 v11, s10, v11
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v12, v10, v11
global_store_b32 v[5:6], v12, off
.LBB0_22:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_23:
s_and_not1_saveexec_b32 s0, s15
s_cbranch_execz .LBB0_25
global_load_b32 v12, v[3:4], off
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, s8, v5
s_waitcnt vmcnt(1)
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
global_load_b32 v10, v[10:11], off
s_waitcnt vmcnt(1)
v_add_f32_e32 v11, v7, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v11, v9, v11
v_add_f32_e32 v11, v0, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v11, -4.0, v12
v_mul_f32_e32 v11, s10, v11
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v12, v10, v11
global_store_b32 v[5:6], v12, off
.LBB0_25:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 s13, s13, exec_lo
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s14
s_and_saveexec_b32 s0, s13
s_cbranch_execz .LBB0_28
global_load_b32 v12, v[3:4], off
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, s8, v5
s_waitcnt vmcnt(1)
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
global_load_b32 v10, v[10:11], off
s_waitcnt vmcnt(1)
v_add_f32_e32 v8, v8, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v8, v12, v8
v_add_f32_e32 v8, v9, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v8, -4.0, v12
v_mul_f32_e32 v8, s10, v8
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v12, v10, v8
global_store_b32 v[5:6], v12, off
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 s3, s3, exec_lo
.LBB0_29:
s_or_b32 exec_lo, exec_lo, s12
s_and_saveexec_b32 s0, s3
s_cbranch_execz .LBB0_31
global_load_b32 v5, v[3:4], off
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v2, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(1)
v_add_f32_e32 v4, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v5, v4
v_add_f32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v0, -4.0, v5
v_mul_f32_e32 v0, s10, v0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v5, v3, v0
v_add_co_u32 v0, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v2, vcc_lo
global_store_b32 v[0:1], v5, off
.LBB0_31:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_32:
s_and_not1_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_34
global_load_b32 v4, v[3:4], off
s_waitcnt vmcnt(3)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_add_f32_e32 v3, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v4, v3
v_add_f32_e32 v3, v9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, -4.0, v4
v_mul_f32_e32 v3, s10, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v4, v2, v3
global_store_b32 v[0:1], v4, off
.LBB0_34:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_35:
s_and_not1_saveexec_b32 s0, s2
s_cbranch_execz .LBB0_37
v_mov_b32_e32 v1, 0
s_clause 0x1
global_load_b32 v2, v1, s[4:5]
global_load_b32 v3, v1, s[8:9]
s_waitcnt vmcnt(1)
v_add_f32_e32 v4, v8, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v2, v4
v_add_f32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v0, -4.0, v2
v_mul_f32_e32 v0, s10, v0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, v3, v0
global_store_b32 v1, v2, s[6:7]
.LBB0_37:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8twodfuncPfS_S_fiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8twodfuncPfS_S_fiii, .Lfunc_end0-_Z8twodfuncPfS_S_fiii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10threedfuncPfS_S_fiiii
.globl _Z10threedfuncPfS_S_fiiii
.p2align 8
.type _Z10threedfuncPfS_S_fiiii,@function
_Z10threedfuncPfS_S_fiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s7, s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s7, v1
s_cbranch_execz .LBB1_14
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b32 s5, s[0:1], 0x24
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_mul_i32 s6, s5, s4
v_add_nc_u32_e32 v5, s6, v1
global_load_b32 v0, v[3:4], off
v_cmp_gt_i32_e32 vcc_lo, s7, v5
s_waitcnt vmcnt(0)
v_mov_b32_e32 v7, v0
s_and_saveexec_b32 s7, vcc_lo
s_cbranch_execz .LBB1_3
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v7, v[5:6], off
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s7
v_subrev_nc_u32_e32 v5, s6, v1
v_mov_b32_e32 v6, v0
s_mov_b32 s7, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_lt_i32_e32 -1, v5
s_cbranch_execz .LBB1_5
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v6, v[5:6], off
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s7
s_ashr_i32 s7, s6, 31
v_ashrrev_i32_e32 v9, 31, v1
s_add_i32 s6, s6, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s6, s6, s7
v_add_nc_u32_e32 v10, v1, v9
v_cvt_f32_u32_e32 v5, s6
s_sub_i32 s7, 0, s6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v10, v10, v9
v_rcp_iflag_f32_e32 v5, v5
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v5, 0x4f7ffffe, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v5, v5
v_mul_lo_u32 v8, s7, v5
s_ashr_i32 s7, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s8, s4, s7
s_xor_b32 s8, s8, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v8, v5, v8
v_add_nc_u32_e32 v5, v5, v8
v_cvt_f32_u32_e32 v8, s8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v10, v5
v_rcp_iflag_f32_e32 v8, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v5, s6
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v8, 0x4f7ffffe, v8
v_cvt_u32_f32_e32 v8, v8
v_sub_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v10, s6, v5
v_cmp_le_u32_e32 vcc_lo, s6, v5
v_cndmask_b32_e32 v5, v5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v10, s6, v5
v_cmp_le_u32_e32 vcc_lo, s6, v5
s_sub_i32 s6, 0, s8
v_cndmask_b32_e32 v5, v5, v10, vcc_lo
v_mul_lo_u32 v10, s6, v8
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v5, v5, v9
v_mul_hi_u32 v10, v8, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v5, v9
v_ashrrev_i32_e32 v9, 31, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v8, v8, v10
v_add_nc_u32_e32 v5, v5, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v5, v5, v9
v_xor_b32_e32 v9, s7, v9
v_mul_hi_u32 v8, v5, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v10, v8, s8
v_sub_nc_u32_e32 v5, v5, v10
v_add_nc_u32_e32 v10, 1, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v11, s8, v5
v_cmp_le_u32_e32 vcc_lo, s8, v5
v_dual_cndmask_b32 v5, v5, v11 :: v_dual_cndmask_b32 v8, v8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s8, v5
v_add_nc_u32_e32 v10, 1, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, v8, v10, vcc_lo
v_xor_b32_e32 v5, v5, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v8, v5, v9
v_mov_b32_e32 v5, v0
v_cmpx_ne_u32_e32 0, v8
s_cbranch_execz .LBB1_7
v_subrev_nc_u32_e32 v9, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s2, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
global_load_b32 v5, v[9:10], off
.LBB1_7:
s_or_b32 exec_lo, exec_lo, s6
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_ne_u32_e32 vcc_lo, s5, v8
v_mov_b32_e32 v8, v0
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB1_9
v_add_nc_u32_e32 v8, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s2, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
global_load_b32 v8, v[8:9], off
.LBB1_9:
s_or_b32 exec_lo, exec_lo, s5
s_ashr_i32 s2, s4, 31
v_ashrrev_i32_e32 v11, 31, v1
s_add_i32 s3, s4, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s2, s3, s2
v_cvt_f32_u32_e32 v9, s2
s_sub_i32 s3, 0, s2
v_add_nc_u32_e32 v12, v1, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v9, v9
v_xor_b32_e32 v12, v12, v11
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v9, 0x4f7ffffe, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v9, v9
v_mul_lo_u32 v10, s3, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v10, v9, v10
v_add_nc_u32_e32 v9, v9, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v9, v12, v9
v_mul_lo_u32 v9, v9, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v9, v12, v9
v_subrev_nc_u32_e32 v10, s2, v9
v_cmp_le_u32_e32 vcc_lo, s2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v9, v9, v10, vcc_lo
v_subrev_nc_u32_e32 v10, s2, v9
v_cmp_le_u32_e32 vcc_lo, s2, v9
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v9, v9, v10, vcc_lo
v_xor_b32_e32 v9, v9, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v10, v9, v11
v_mov_b32_e32 v9, v0
v_cmpx_ne_u32_e32 0, v10
s_cbranch_execz .LBB1_11
global_load_b32 v9, v[3:4], off offset:-4
.LBB1_11:
s_or_b32 exec_lo, exec_lo, s2
s_add_i32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_ne_u32_e32 vcc_lo, s4, v10
v_mov_b32_e32 v10, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_13
global_load_b32 v10, v[3:4], off offset:4
.LBB1_13:
s_or_b32 exec_lo, exec_lo, s2
s_load_b128 s[4:7], s[0:1], 0x8
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_load_b32 s0, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(1)
v_add_f32_e32 v4, v5, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v7, v4
v_add_f32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v4, v9
v_add_f32_e32 v4, v4, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v4, v0, 0xc0c00000, v4
v_mul_f32_e32 v4, s0, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v0, v3, v4
global_store_b32 v[1:2], v0, off
.LBB1_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10threedfuncPfS_S_fiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10threedfuncPfS_S_fiiii, .Lfunc_end1-_Z10threedfuncPfS_S_fiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8twodfuncPfS_S_fiii
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z8twodfuncPfS_S_fiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10threedfuncPfS_S_fiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10threedfuncPfS_S_fiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | namespace {
__global__ void kernel(long long int sleep_cycles) {
auto start = clock64();
while (true) {
auto now = clock64();
if (now - start > sleep_cycles) {
break;
}
}
return;
}
}
void spin_device(cudaStream_t st, int giga_cycles) {
kernel<<<1, 1, 0, st>>>((long long int)(1) * 1000 * 1000 * 1000
* giga_cycles);
} | code for sm_80
Function : _ZN50_GLOBAL__N__28c506d3_17_test_util_cuda_cu_1cace4236kernelEx
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ CS2R R2, SR_CLOCKLO ; /* 0x0000000000027805 */
/* 0x000fca0000015000 */
/*0020*/ CS2R R4, SR_CLOCKLO ; /* 0x0000000000047805 */
/* 0x000fcc0000015000 */
/*0030*/ IADD3 R0, P0, -R2, R4, RZ ; /* 0x0000000402007210 */
/* 0x000fca0007f1e1ff */
/*0040*/ IMAD.X R4, R5, 0x1, ~R3, P0 ; /* 0x0000000105047824 */
/* 0x000fe200000e0e03 */
/*0050*/ ISETP.GT.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fc80003f04070 */
/*0060*/ ISETP.GT.AND.EX P0, PT, R4, c[0x0][0x164], PT, P0 ; /* 0x0000590004007a0c */
/* 0x000fda0003f04300 */
/*0070*/ @!P0 BRA 0x20 ; /* 0xffffffa000008947 */
/* 0x000fea000383ffff */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | namespace {
__global__ void kernel(long long int sleep_cycles) {
auto start = clock64();
while (true) {
auto now = clock64();
if (now - start > sleep_cycles) {
break;
}
}
return;
}
}
void spin_device(cudaStream_t st, int giga_cycles) {
kernel<<<1, 1, 0, st>>>((long long int)(1) * 1000 * 1000 * 1000
* giga_cycles);
} | .file "tmpxft_000122e7_00000000-6_test_util_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z78__device_stub__ZN50_GLOBAL__N__28c506d3_17_test_util_cuda_cu_1cace4236kernelExx
.hidden _Z78__device_stub__ZN50_GLOBAL__N__28c506d3_17_test_util_cuda_cu_1cace4236kernelExx
.type _Z78__device_stub__ZN50_GLOBAL__N__28c506d3_17_test_util_cuda_cu_1cace4236kernelExx, @function
_Z78__device_stub__ZN50_GLOBAL__N__28c506d3_17_test_util_cuda_cu_1cace4236kernelExx:
.LFB2052:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _ZN50_GLOBAL__N__28c506d3_17_test_util_cuda_cu_1cace4236kernelEx(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z78__device_stub__ZN50_GLOBAL__N__28c506d3_17_test_util_cuda_cu_1cace4236kernelExx, .-_Z78__device_stub__ZN50_GLOBAL__N__28c506d3_17_test_util_cuda_cu_1cace4236kernelExx
.globl _ZN50_GLOBAL__N__28c506d3_17_test_util_cuda_cu_1cace4236kernelEx
.hidden _ZN50_GLOBAL__N__28c506d3_17_test_util_cuda_cu_1cace4236kernelEx
.type _ZN50_GLOBAL__N__28c506d3_17_test_util_cuda_cu_1cace4236kernelEx, @function
_ZN50_GLOBAL__N__28c506d3_17_test_util_cuda_cu_1cace4236kernelEx:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z78__device_stub__ZN50_GLOBAL__N__28c506d3_17_test_util_cuda_cu_1cace4236kernelExx
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZN50_GLOBAL__N__28c506d3_17_test_util_cuda_cu_1cace4236kernelEx, .-_ZN50_GLOBAL__N__28c506d3_17_test_util_cuda_cu_1cace4236kernelEx
.globl _Z11spin_deviceP11CUstream_sti
.type _Z11spin_deviceP11CUstream_sti, @function
_Z11spin_deviceP11CUstream_sti:
.LFB2027:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r9
movl %esi, %ebx
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movslq %ebx, %rsi
imulq $1000000000, %rsi, %rdi
call _Z78__device_stub__ZN50_GLOBAL__N__28c506d3_17_test_util_cuda_cu_1cace4236kernelExx
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z11spin_deviceP11CUstream_sti, .-_Z11spin_deviceP11CUstream_sti
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_ZN50_GLOBAL__N__28c506d3_17_test_util_cuda_cu_1cace4236kernelEx"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZN50_GLOBAL__N__28c506d3_17_test_util_cuda_cu_1cace4236kernelEx(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.