system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00017926_00000000-6_Task1CPUdp.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14cpu_matrixmultPdS_PS_iii
.type _Z14cpu_matrixmultPdS_PS_iii, @function
_Z14cpu_matrixmultPdS_PS_iii:
.LFB2057:
.cfi_startproc
endbr64
testl %r9d, %r9d
jle .L14
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rdi, %rax
movq %rsi, %rbp
movq %rdx, %rdi
movl %ecx, %r12d
movl %r8d, %r11d
movq %rax, %rsi
movslq %r9d, %r13
salq $3, %r13
movl $0, %edx
movl $0, %eax
movslq %r8d, %r14
movq %rsi, %rcx
movl %r9d, %r8d
jmp .L5
.L9:
movslq %edx, %r15
salq $3, %r15
movq %rcx, %r10
movl $0, %ebx
movl $0, %r9d
movl %eax, -8(%rsp)
movq %rcx, -16(%rsp)
movl %edx, -4(%rsp)
.L8:
movsd (%r10), %xmm1
testl %r11d, %r11d
jle .L6
movslq %ebx, %rdx
leaq 0(,%rdx,8), %rax
leaq (%r14,%rdx), %rsi
salq $3, %rsi
negq %rdx
leaq (%r15,%rdx,8), %rcx
addq %rbp, %rcx
.L7:
movq %rax, %rdx
addq (%rdi), %rdx
movapd %xmm1, %xmm0
mulsd (%rcx,%rax), %xmm0
addsd (%rdx), %xmm0
movsd %xmm0, (%rdx)
addq $8, %rax
cmpq %rsi, %rax
jne .L7
.L6:
addl $1, %r9d
addq %r13, %r10
addl %r11d, %ebx
cmpl %r9d, %r12d
jne .L8
movl -8(%rsp), %eax
movq -16(%rsp), %rcx
movl -4(%rsp), %edx
.L10:
addl $1, %eax
addq $8, %rcx
addl %r11d, %edx
cmpl %eax, %r8d
je .L3
.L5:
testl %r12d, %r12d
jg .L9
jmp .L10
.L3:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2057:
.size _Z14cpu_matrixmultPdS_PS_iii, .-_Z14cpu_matrixmultPdS_PS_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Usage: Task1GPUsp <n> <m> <p>\n"
.align 8
.LC2:
.string "Time to calculate results on CPU: %f ms.\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "%.2f "
.LC4:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
cmpl $3, %edi
jle .L41
movq %rsi, %rbp
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, (%rsp)
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movl %eax, 4(%rsp)
movq 24(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movq %rax, 8(%rsp)
movl %eax, %r12d
movl %eax, %edi
imull %ebx, %edi
sall $3, %edi
movslq %edi, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rax, 48(%rsp)
movl %r15d, %edi
imull %r13d, %edi
sall $3, %edi
movslq %edi, %rdi
call malloc@PLT
movq %rax, 40(%rsp)
movl %ebx, %edi
imull %r13d, %edi
sall $3, %edi
movslq %edi, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
movq %rax, 80(%rsp)
movl $12345, %edi
call srand@PLT
testl %ebx, %ebx
jle .L19
movl %r15d, 24(%rsp)
movl $0, %r15d
movl $0, %r14d
movq %r13, 32(%rsp)
movq %rbp, %r13
movq %rbx, 56(%rsp)
jmp .L20
.L41:
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L22:
movslq %r15d, %rdx
leaq 0(%r13,%rdx,8), %rbx
movq 8(%rsp), %rax
leal -1(%rax), %eax
addq %rdx, %rax
leaq 8(%r13,%rax,8), %rbp
.L21:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC1(%rip), %xmm0
movsd %xmm0, (%rbx)
addq $8, %rbx
cmpq %rbp, %rbx
jne .L21
.L23:
addl $1, %r14d
movl 24(%rsp), %eax
addl %eax, %r15d
movl (%rsp), %eax
cmpl %eax, %r14d
je .L38
.L20:
testl %r12d, %r12d
jg .L22
jmp .L23
.L38:
movq 32(%rsp), %r13
movq 56(%rsp), %rbx
.L19:
cmpl $0, 8(%rsp)
jle .L24
movl %r13d, 24(%rsp)
movl $0, %r15d
movl $0, %r14d
movq %r13, 32(%rsp)
movl %r12d, %r13d
movq 40(%rsp), %r12
movq %rbx, 56(%rsp)
jmp .L25
.L27:
movslq %r15d, %rdx
leaq (%r12,%rdx,8), %rbx
movq 32(%rsp), %rax
leal -1(%rax), %eax
addq %rdx, %rax
leaq 8(%r12,%rax,8), %rbp
.L26:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC1(%rip), %xmm0
movsd %xmm0, (%rbx)
addq $8, %rbx
cmpq %rbp, %rbx
jne .L26
.L28:
addl $1, %r14d
movl 24(%rsp), %eax
addl %eax, %r15d
cmpl %r13d, %r14d
je .L39
.L25:
cmpl $0, 4(%rsp)
jg .L27
jmp .L28
.L39:
movq 32(%rsp), %r13
movq 56(%rsp), %rbx
.L24:
leaq 88(%rsp), %rdi
call cudaEventCreate@PLT
leaq 96(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 88(%rsp), %rdi
call cudaEventRecord@PLT
leaq 80(%rsp), %rdx
movl 8(%rsp), %r9d
movl %r13d, %r8d
movl (%rsp), %ecx
movq 40(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z14cpu_matrixmultPdS_PS_iii
movl $0, %esi
movq 96(%rsp), %rdi
call cudaEventRecord@PLT
movq 96(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 76(%rsp), %rdi
movq 96(%rsp), %rdx
movq 88(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 76(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jle .L29
movl %r13d, %r15d
movl $0, %r14d
movl $0, %r12d
leal -1(%r13), %eax
movl %eax, 8(%rsp)
movq 16(%rsp), %rax
addq $8, %rax
movq %rax, 24(%rsp)
leaq .LC3(%rip), %r13
jmp .L30
.L32:
movslq %r14d, %rdx
movq 16(%rsp), %rax
leaq (%rax,%rdx,8), %rbx
movl 8(%rsp), %eax
addq %rdx, %rax
movq 24(%rsp), %rcx
leaq (%rcx,%rax,8), %rbp
.L31:
movsd (%rbx), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L31
.L33:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r12d
addl %r15d, %r14d
movl (%rsp), %eax
cmpl %eax, %r12d
je .L29
.L30:
cmpl $0, 4(%rsp)
jg .L32
jmp .L33
.L29:
movq 48(%rsp), %rdi
call free@PLT
movq 40(%rsp), %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L42
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -4194304
.long 1105199103
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Task1CPUdp.hip"
.globl _Z14cpu_matrixmultPdS_PS_iii # -- Begin function _Z14cpu_matrixmultPdS_PS_iii
.p2align 4, 0x90
.type _Z14cpu_matrixmultPdS_PS_iii,@function
_Z14cpu_matrixmultPdS_PS_iii: # @_Z14cpu_matrixmultPdS_PS_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, -8(%rsp) # 8-byte Spill
testl %r9d, %r9d
jle .LBB0_9
# %bb.1: # %.preheader.lr.ph
movl %r9d, %eax
movl %ecx, %r9d
movl %r8d, %r10d
xorl %esi, %esi
xorl %ebx, %ebx
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_8: # %._crit_edge28
# in Loop: Header=BB0_2 Depth=1
incq %rbx
addl %r8d, %esi
cmpq %rax, %rbx
je .LBB0_9
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
# Child Loop BB0_6 Depth 3
testl %ecx, %ecx
jle .LBB0_8
# %bb.3: # %.lr.ph27
# in Loop: Header=BB0_2 Depth=1
movl %esi, %r11d
movq -8(%rsp), %r14 # 8-byte Reload
leaq (%r14,%r11,8), %r14
leaq (%rdi,%rbx,8), %r15
xorl %r12d, %r12d
xorl %r13d, %r13d
jmp .LBB0_4
.p2align 4, 0x90
.LBB0_7: # %._crit_edge
# in Loop: Header=BB0_4 Depth=2
incq %r13
addl %r8d, %r12d
cmpq %r9, %r13
je .LBB0_8
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_6 Depth 3
testl %r8d, %r8d
jle .LBB0_7
# %bb.5: # %.lr.ph
# in Loop: Header=BB0_4 Depth=2
movl %r12d, %ebp
shlq $3, %rbp
movq %r13, %r11
imulq %rax, %r11
movsd (%r15,%r11,8), %xmm0 # xmm0 = mem[0],zero
addq (%rdx), %rbp
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB0_6: # Parent Loop BB0_2 Depth=1
# Parent Loop BB0_4 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%r14,%r11,8), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm0, %xmm1
addsd (%rbp,%r11,8), %xmm1
movsd %xmm1, (%rbp,%r11,8)
incq %r11
cmpq %r11, %r10
jne .LBB0_6
jmp .LBB0_7
.LBB0_9: # %._crit_edge30
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z14cpu_matrixmultPdS_PS_iii, .Lfunc_end0-_Z14cpu_matrixmultPdS_PS_iii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x41dfffffffc00000 # double 2147483647
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $3, %edi
jle .LBB1_29
# %bb.1:
movq %rsi, %r15
movq 8(%rsi), %rdi
xorl %r14d, %r14d
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movq 16(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 24(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
leal (,%r12,8), %ebp
movl %ebp, %eax
imull %r13d, %eax
movl %ebx, %r15d
imull %r13d, %r15d
shll $3, %r15d
imull %ebx, %ebp
movslq %eax, %rdi
callq malloc
movq %rax, 32(%rsp) # 8-byte Spill
movslq %r15d, %rdi
callq malloc
movq %rax, 24(%rsp) # 8-byte Spill
movslq %ebp, %rdi
callq malloc
movq %rax, 8(%rsp) # 8-byte Spill
movl $12345, %edi # imm = 0x3039
callq srand
movq %r13, %rax
movq %r12, 56(%rsp) # 8-byte Spill
testl %r12d, %r12d
movq %r13, (%rsp) # 8-byte Spill
jle .LBB1_7
# %bb.2: # %.preheader60.lr.ph
movl 56(%rsp), %ecx # 4-byte Reload
movq %rcx, 16(%rsp) # 8-byte Spill
movl %eax, %r13d
xorl %ebp, %ebp
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_6: # %._crit_edge
# in Loop: Header=BB1_3 Depth=1
incq %rbp
movq (%rsp), %rax # 8-byte Reload
addl %eax, %r14d
cmpq 16(%rsp), %rbp # 8-byte Folded Reload
je .LBB1_7
.LBB1_3: # %.preheader60
# =>This Loop Header: Depth=1
# Child Loop BB1_5 Depth 2
testl %eax, %eax
jle .LBB1_6
# %bb.4: # %.lr.ph
# in Loop: Header=BB1_3 Depth=1
movl %r14d, %eax
movq 32(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd %xmm1, %xmm0
movsd %xmm0, (%r15,%r12,8)
incq %r12
cmpq %r12, %r13
jne .LBB1_5
jmp .LBB1_6
.LBB1_7: # %.preheader59
testl %eax, %eax
jle .LBB1_13
# %bb.8: # %.preheader58.lr.ph
movl (%rsp), %eax # 4-byte Reload
movq %rax, 16(%rsp) # 8-byte Spill
movl %ebx, %r15d
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_12: # %._crit_edge65
# in Loop: Header=BB1_9 Depth=1
incq %rbp
addl %ebx, %r13d
cmpq 16(%rsp), %rbp # 8-byte Folded Reload
je .LBB1_13
.LBB1_9: # %.preheader58
# =>This Loop Header: Depth=1
# Child Loop BB1_11 Depth 2
testl %ebx, %ebx
jle .LBB1_12
# %bb.10: # %.lr.ph64
# in Loop: Header=BB1_9 Depth=1
movl %r13d, %eax
movq 24(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %r14
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_11: # Parent Loop BB1_9 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd %xmm1, %xmm0
movsd %xmm0, (%r14,%r12,8)
incq %r12
cmpq %r12, %r15
jne .LBB1_11
jmp .LBB1_12
.LBB1_13: # %._crit_edge67
leaq 64(%rsp), %rdi
callq hipEventCreate
leaq 40(%rsp), %rdi
callq hipEventCreate
movq 64(%rsp), %rdi
xorl %r14d, %r14d
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rax # 8-byte Reload
testl %eax, %eax
movq 8(%rsp), %r12 # 8-byte Reload
movq 56(%rsp), %r13 # 8-byte Reload
jle .LBB1_22
# %bb.14: # %.preheader.lr.ph.i
movl %eax, %eax
movl %r13d, %ecx
movl %ebx, %edx
xorl %esi, %esi
jmp .LBB1_15
.p2align 4, 0x90
.LBB1_21: # %._crit_edge28.i
# in Loop: Header=BB1_15 Depth=1
incq %rsi
addl %ebx, %r14d
cmpq %rax, %rsi
je .LBB1_22
.LBB1_15: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB1_17 Depth 2
# Child Loop BB1_19 Depth 3
testl %r13d, %r13d
jle .LBB1_21
# %bb.16: # %.lr.ph27.i
# in Loop: Header=BB1_15 Depth=1
movl %r14d, %edi
movq 24(%rsp), %r8 # 8-byte Reload
leaq (%r8,%rdi,8), %rdi
movq 32(%rsp), %r8 # 8-byte Reload
leaq (%r8,%rsi,8), %r8
xorl %r9d, %r9d
xorl %r10d, %r10d
jmp .LBB1_17
.p2align 4, 0x90
.LBB1_20: # %._crit_edge.i
# in Loop: Header=BB1_17 Depth=2
incq %r10
addl %ebx, %r9d
cmpq %rcx, %r10
je .LBB1_21
.LBB1_17: # Parent Loop BB1_15 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_19 Depth 3
testl %ebx, %ebx
jle .LBB1_20
# %bb.18: # %.lr.ph.i
# in Loop: Header=BB1_17 Depth=2
movq %r10, %r15
imulq %rax, %r15
movl %r9d, %r11d
leaq (%r12,%r11,8), %r11
movsd (%r8,%r15,8), %xmm0 # xmm0 = mem[0],zero
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_19: # Parent Loop BB1_15 Depth=1
# Parent Loop BB1_17 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%rdi,%r15,8), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm0, %xmm1
addsd (%r11,%r15,8), %xmm1
movsd %xmm1, (%r11,%r15,8)
incq %r15
cmpq %r15, %rdx
jne .LBB1_19
jmp .LBB1_20
.LBB1_22: # %_Z14cpu_matrixmultPdS_PS_iii.exit
movq 40(%rsp), %rdi
xorl %r14d, %r14d
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rdi
callq hipEventSynchronize
movq 64(%rsp), %rsi
movq 40(%rsp), %rdx
leaq 52(%rsp), %rdi
callq hipEventElapsedTime
movss 52(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
testl %r13d, %r13d
jle .LBB1_28
# %bb.23: # %.preheader.lr.ph
movl %r13d, %eax
movq %rax, (%rsp) # 8-byte Spill
movl %ebx, %ebp
xorl %r15d, %r15d
jmp .LBB1_24
.p2align 4, 0x90
.LBB1_27: # %._crit_edge74
# in Loop: Header=BB1_24 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r15
addl %ebx, %r14d
cmpq (%rsp), %r15 # 8-byte Folded Reload
je .LBB1_28
.LBB1_24: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_26 Depth 2
testl %ebx, %ebx
jle .LBB1_27
# %bb.25: # %.lr.ph73
# in Loop: Header=BB1_24 Depth=1
movl %r14d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,8), %r13
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_26: # Parent Loop BB1_24 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r13,%r12,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r12
cmpq %r12, %rbp
jne .LBB1_26
jmp .LBB1_27
.LBB1_28: # %._crit_edge76
movq 32(%rsp), %rdi # 8-byte Reload
callq free
movq 24(%rsp), %rdi # 8-byte Reload
callq free
movq 8(%rsp), %rdi # 8-byte Reload
callq free
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_29:
.cfi_def_cfa_offset 128
movl $.Lstr, %edi
callq puts@PLT
movl $-1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Time to calculate results on CPU: %f ms.\n"
.size .L.str.1, 42
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%.2f "
.size .L.str.2, 7
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Usage: Task1GPUsp <n> <m> <p>"
.size .Lstr, 30
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <time.h>
__global__
void bin_search(int* a, int* l, int* r, int* e, int* searchValue) {
int idx = threadIdx.x;
int lm = l[0];
int rm = r[0];
int gap = (int)ceil((float)(rm-lm+1)/(float)(256));
int num_proc = (int)ceil((float)(rm - lm + 1)/(float)gap);
int currl = idx*gap + lm;
if(currl > rm) return;
int currr = min((idx+1)*gap + lm,rm+1) - 1;
if(searchValue[0] >= a[currl] && searchValue[0] <= a[currr]) {
l[0] = currl;
r[0] = currr;
}
}
int main(int argc, char* argv[]) {
int n;
scanf("%d",&n);
int *a;
int *searchValue;
cudaMallocManaged(&a, n*sizeof(int));
cudaMallocManaged(&searchValue, sizeof(int));
scanf("%d",&searchValue[0]);
for(int i=0;i<n;i++) scanf("%d",&a[i]);
int *l, *r;
int *e;
cudaMallocManaged(&l, sizeof(int));
cudaMallocManaged(&r, sizeof(int));
cudaMallocManaged(&e, sizeof(int));
l[0] = 0; r[0] = (n-1);
while(l[0] < r[0]) {
bin_search<<<1,256>>>(a,l,r,e,searchValue);
cudaDeviceSynchronize();
}
printf("%d\n",l[0]);
cudaFree(a);
cudaFree(l);
cudaFree(r);
cudaFree(e);
cudaFree(searchValue);
return 0;
} | code for sm_80
Function : _Z10bin_searchPiS_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fe20000000f00 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0060*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea8000c1e1900 */
/*0080*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0090*/ IADD3 R6, R11, 0x1, -R0 ; /* 0x000000010b067810 */
/* 0x004fcc0007ffe800 */
/*00a0*/ I2F R6, R6 ; /* 0x0000000600067306 */
/* 0x000e640000201400 */
/*00b0*/ FMUL R7, R6, 0.00390625 ; /* 0x3b80000006077820 */
/* 0x002fcc0000400000 */
/*00c0*/ F2I.CEIL.NTZ R13, R7 ; /* 0x00000007000d7305 */
/* 0x000e24000020b100 */
/*00d0*/ IMAD R0, R13, R8, R0 ; /* 0x000000080d007224 */
/* 0x001fca00078e0200 */
/*00e0*/ ISETP.GT.AND P0, PT, R0, R11, PT ; /* 0x0000000b0000720c */
/* 0x000fda0003f04270 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ IMAD.MOV.U32 R12, RZ, RZ, 0x4 ; /* 0x00000004ff0c7424 */
/* 0x000fe200078e00ff */
/*0110*/ MOV R8, c[0x0][0x180] ; /* 0x0000600000087a02 */
/* 0x000fe20000000f00 */
/*0120*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff097624 */
/* 0x000fe400078e00ff */
/*0130*/ IMAD.WIDE R6, R0, R12, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fc600078e020c */
/*0140*/ LDG.E R15, [R8.64] ; /* 0x00000004080f7981 */
/* 0x000ea8000c1e1900 */
/*0150*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*0160*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fe40007ffe0ff */
/*0170*/ IADD3 R10, R13, R0, RZ ; /* 0x000000000d0a7210 */
/* 0x000fc80007ffe0ff */
/*0180*/ IMNMX R10, R11, R10, PT ; /* 0x0000000a0b0a7217 */
/* 0x000fe40003800200 */
/*0190*/ ISETP.GE.AND P0, PT, R15, R6, PT ; /* 0x000000060f00720c */
/* 0x004fda0003f06270 */
/*01a0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01b0*/ IADD3 R9, R10, -0x1, RZ ; /* 0xffffffff0a097810 */
/* 0x000fca0007ffe0ff */
/*01c0*/ IMAD.WIDE R6, R9, R12, c[0x0][0x160] ; /* 0x0000580009067625 */
/* 0x000fcc00078e020c */
/*01d0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1900 */
/*01e0*/ ISETP.GT.AND P0, PT, R15, R6, PT ; /* 0x000000060f00720c */
/* 0x004fda0003f04270 */
/*01f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0200*/ STG.E [R4.64], R0 ; /* 0x0000000004007986 */
/* 0x000fe8000c101904 */
/*0210*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <time.h>
__global__
void bin_search(int* a, int* l, int* r, int* e, int* searchValue) {
int idx = threadIdx.x;
int lm = l[0];
int rm = r[0];
int gap = (int)ceil((float)(rm-lm+1)/(float)(256));
int num_proc = (int)ceil((float)(rm - lm + 1)/(float)gap);
int currl = idx*gap + lm;
if(currl > rm) return;
int currr = min((idx+1)*gap + lm,rm+1) - 1;
if(searchValue[0] >= a[currl] && searchValue[0] <= a[currr]) {
l[0] = currl;
r[0] = currr;
}
}
int main(int argc, char* argv[]) {
int n;
scanf("%d",&n);
int *a;
int *searchValue;
cudaMallocManaged(&a, n*sizeof(int));
cudaMallocManaged(&searchValue, sizeof(int));
scanf("%d",&searchValue[0]);
for(int i=0;i<n;i++) scanf("%d",&a[i]);
int *l, *r;
int *e;
cudaMallocManaged(&l, sizeof(int));
cudaMallocManaged(&r, sizeof(int));
cudaMallocManaged(&e, sizeof(int));
l[0] = 0; r[0] = (n-1);
while(l[0] < r[0]) {
bin_search<<<1,256>>>(a,l,r,e,searchValue);
cudaDeviceSynchronize();
}
printf("%d\n",l[0]);
cudaFree(a);
cudaFree(l);
cudaFree(r);
cudaFree(e);
cudaFree(searchValue);
return 0;
} | .file "tmpxft_0001c103_00000000-6_bin_search_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z10bin_searchPiS_S_S_S_PiS_S_S_S_
.type _Z38__device_stub__Z10bin_searchPiS_S_S_S_PiS_S_S_S_, @function
_Z38__device_stub__Z10bin_searchPiS_S_S_S_PiS_S_S_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10bin_searchPiS_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z38__device_stub__Z10bin_searchPiS_S_S_S_PiS_S_S_S_, .-_Z38__device_stub__Z10bin_searchPiS_S_S_S_PiS_S_S_S_
.globl _Z10bin_searchPiS_S_S_S_
.type _Z10bin_searchPiS_S_S_S_, @function
_Z10bin_searchPiS_S_S_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z10bin_searchPiS_S_S_S_PiS_S_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10bin_searchPiS_S_S_S_, .-_Z10bin_searchPiS_S_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d"
.LC1:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rsi
leaq .LC0(%rip), %rbx
movq %rbx, %rdi
call __isoc23_scanf@PLT
movslq 4(%rsp), %rsi
salq $2, %rsi
leaq 8(%rsp), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
movq 16(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
cmpl $0, 4(%rsp)
jle .L12
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L13:
movq 8(%rsp), %rax
leaq (%rax,%rbx,4), %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addq $1, %rbx
cmpl %ebx, 4(%rsp)
jg .L13
.L12:
leaq 24(%rsp), %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
leaq 32(%rsp), %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
leaq 40(%rsp), %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
movq 24(%rsp), %rax
movl $0, (%rax)
movl 4(%rsp), %eax
subl $1, %eax
movq 32(%rsp), %rdx
movl %eax, (%rdx)
movq 24(%rsp), %rax
movl (%rax), %edx
movq 32(%rsp), %rax
cmpl (%rax), %edx
jl .L16
.L14:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call cudaDeviceSynchronize@PLT
movq 24(%rsp), %rax
movl (%rax), %edx
movq 32(%rsp), %rax
cmpl (%rax), %edx
jge .L14
.L16:
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L15
movq 16(%rsp), %r8
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z38__device_stub__Z10bin_searchPiS_S_S_S_PiS_S_S_S_
jmp .L15
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z10bin_searchPiS_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10bin_searchPiS_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <time.h>
__global__
void bin_search(int* a, int* l, int* r, int* e, int* searchValue) {
int idx = threadIdx.x;
int lm = l[0];
int rm = r[0];
int gap = (int)ceil((float)(rm-lm+1)/(float)(256));
int num_proc = (int)ceil((float)(rm - lm + 1)/(float)gap);
int currl = idx*gap + lm;
if(currl > rm) return;
int currr = min((idx+1)*gap + lm,rm+1) - 1;
if(searchValue[0] >= a[currl] && searchValue[0] <= a[currr]) {
l[0] = currl;
r[0] = currr;
}
}
int main(int argc, char* argv[]) {
int n;
scanf("%d",&n);
int *a;
int *searchValue;
cudaMallocManaged(&a, n*sizeof(int));
cudaMallocManaged(&searchValue, sizeof(int));
scanf("%d",&searchValue[0]);
for(int i=0;i<n;i++) scanf("%d",&a[i]);
int *l, *r;
int *e;
cudaMallocManaged(&l, sizeof(int));
cudaMallocManaged(&r, sizeof(int));
cudaMallocManaged(&e, sizeof(int));
l[0] = 0; r[0] = (n-1);
while(l[0] < r[0]) {
bin_search<<<1,256>>>(a,l,r,e,searchValue);
cudaDeviceSynchronize();
}
printf("%d\n",l[0]);
cudaFree(a);
cudaFree(l);
cudaFree(r);
cudaFree(e);
cudaFree(searchValue);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
__global__
void bin_search(int* a, int* l, int* r, int* e, int* searchValue) {
int idx = threadIdx.x;
int lm = l[0];
int rm = r[0];
int gap = (int)ceil((float)(rm-lm+1)/(float)(256));
int num_proc = (int)ceil((float)(rm - lm + 1)/(float)gap);
int currl = idx*gap + lm;
if(currl > rm) return;
int currr = min((idx+1)*gap + lm,rm+1) - 1;
if(searchValue[0] >= a[currl] && searchValue[0] <= a[currr]) {
l[0] = currl;
r[0] = currr;
}
}
int main(int argc, char* argv[]) {
int n;
scanf("%d",&n);
int *a;
int *searchValue;
hipMallocManaged(&a, n*sizeof(int));
hipMallocManaged(&searchValue, sizeof(int));
scanf("%d",&searchValue[0]);
for(int i=0;i<n;i++) scanf("%d",&a[i]);
int *l, *r;
int *e;
hipMallocManaged(&l, sizeof(int));
hipMallocManaged(&r, sizeof(int));
hipMallocManaged(&e, sizeof(int));
l[0] = 0; r[0] = (n-1);
while(l[0] < r[0]) {
bin_search<<<1,256>>>(a,l,r,e,searchValue);
hipDeviceSynchronize();
}
printf("%d\n",l[0]);
hipFree(a);
hipFree(l);
hipFree(r);
hipFree(e);
hipFree(searchValue);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
__global__
void bin_search(int* a, int* l, int* r, int* e, int* searchValue) {
int idx = threadIdx.x;
int lm = l[0];
int rm = r[0];
int gap = (int)ceil((float)(rm-lm+1)/(float)(256));
int num_proc = (int)ceil((float)(rm - lm + 1)/(float)gap);
int currl = idx*gap + lm;
if(currl > rm) return;
int currr = min((idx+1)*gap + lm,rm+1) - 1;
if(searchValue[0] >= a[currl] && searchValue[0] <= a[currr]) {
l[0] = currl;
r[0] = currr;
}
}
int main(int argc, char* argv[]) {
int n;
scanf("%d",&n);
int *a;
int *searchValue;
hipMallocManaged(&a, n*sizeof(int));
hipMallocManaged(&searchValue, sizeof(int));
scanf("%d",&searchValue[0]);
for(int i=0;i<n;i++) scanf("%d",&a[i]);
int *l, *r;
int *e;
hipMallocManaged(&l, sizeof(int));
hipMallocManaged(&r, sizeof(int));
hipMallocManaged(&e, sizeof(int));
l[0] = 0; r[0] = (n-1);
while(l[0] < r[0]) {
bin_search<<<1,256>>>(a,l,r,e,searchValue);
hipDeviceSynchronize();
}
printf("%d\n",l[0]);
hipFree(a);
hipFree(l);
hipFree(r);
hipFree(e);
hipFree(searchValue);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10bin_searchPiS_S_S_S_
.globl _Z10bin_searchPiS_S_S_S_
.p2align 8
.type _Z10bin_searchPiS_S_S_S_,@function
_Z10bin_searchPiS_S_S_S_:
s_load_b128 s[4:7], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_load_b32 s3, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_sub_i32 s8, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s8, s8, 1
v_cvt_f32_i32_e32 v1, s8
s_mov_b32 s8, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v1, 0x3b800000, v1
v_ceil_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, v0, v3, s[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ge_i32_e64 s3, v1
s_cbranch_execz .LBB0_4
s_load_b64 s[8:9], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s8, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
s_load_b32 s0, s[0:1], 0x0
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_ge_i32_e32 vcc_lo, s0, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_4
v_mul_lo_u32 v0, v3, v0
s_add_i32 s3, s3, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s2, v3, v0
v_min_i32_e32 v0, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, -1, v0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_add_co_u32 v3, vcc_lo, s8, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_le_i32_e32 vcc_lo, s0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
v_mov_b32_e32 v0, 0
s_clause 0x1
global_store_b32 v0, v1, s[4:5]
global_store_b32 v0, v2, s[6:7]
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10bin_searchPiS_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10bin_searchPiS_S_S_S_, .Lfunc_end0-_Z10bin_searchPiS_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10bin_searchPiS_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z10bin_searchPiS_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
__global__
void bin_search(int* a, int* l, int* r, int* e, int* searchValue) {
int idx = threadIdx.x;
int lm = l[0];
int rm = r[0];
int gap = (int)ceil((float)(rm-lm+1)/(float)(256));
int num_proc = (int)ceil((float)(rm - lm + 1)/(float)gap);
int currl = idx*gap + lm;
if(currl > rm) return;
int currr = min((idx+1)*gap + lm,rm+1) - 1;
if(searchValue[0] >= a[currl] && searchValue[0] <= a[currr]) {
l[0] = currl;
r[0] = currr;
}
}
int main(int argc, char* argv[]) {
int n;
scanf("%d",&n);
int *a;
int *searchValue;
hipMallocManaged(&a, n*sizeof(int));
hipMallocManaged(&searchValue, sizeof(int));
scanf("%d",&searchValue[0]);
for(int i=0;i<n;i++) scanf("%d",&a[i]);
int *l, *r;
int *e;
hipMallocManaged(&l, sizeof(int));
hipMallocManaged(&r, sizeof(int));
hipMallocManaged(&e, sizeof(int));
l[0] = 0; r[0] = (n-1);
while(l[0] < r[0]) {
bin_search<<<1,256>>>(a,l,r,e,searchValue);
hipDeviceSynchronize();
}
printf("%d\n",l[0]);
hipFree(a);
hipFree(l);
hipFree(r);
hipFree(e);
hipFree(searchValue);
return 0;
} | .text
.file "bin_search_cuda.hip"
.globl _Z25__device_stub__bin_searchPiS_S_S_S_ # -- Begin function _Z25__device_stub__bin_searchPiS_S_S_S_
.p2align 4, 0x90
.type _Z25__device_stub__bin_searchPiS_S_S_S_,@function
_Z25__device_stub__bin_searchPiS_S_S_S_: # @_Z25__device_stub__bin_searchPiS_S_S_S_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10bin_searchPiS_S_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z25__device_stub__bin_searchPiS_S_S_S_, .Lfunc_end0-_Z25__device_stub__bin_searchPiS_S_S_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 12(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 12(%rsp), %rsi
shlq $2, %rsi
leaq 40(%rsp), %rdi
movl $1, %edx
callq hipMallocManaged
leaq 32(%rsp), %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
movq 32(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
cmpl $0, 12(%rsp)
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %ebx, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq 40(%rsp), %rsi
addq %rbx, %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
incq %r14
movslq 12(%rsp), %rax
addq $4, %rbx
cmpq %rax, %r14
jl .LBB1_2
.LBB1_3: # %._crit_edge
leaq 24(%rsp), %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
leaq 48(%rsp), %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
movq 24(%rsp), %rax
movl $0, (%rax)
movl 12(%rsp), %ecx
decl %ecx
movq 16(%rsp), %rdx
movl %ecx, (%rdx)
movl (%rax), %esi
cmpl %ecx, %esi
jge .LBB1_8
# %bb.4: # %.lr.ph11
movabsq $4294967297, %rbx # imm = 0x100000001
leaq 255(%rbx), %r14
leaq 72(%rsp), %r12
leaq 64(%rsp), %r13
leaq 56(%rsp), %rbp
leaq 144(%rsp), %r15
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_5 Depth=1
callq hipDeviceSynchronize
movq 24(%rsp), %rax
movl (%rax), %esi
movq 16(%rsp), %rax
cmpl (%rax), %esi
jge .LBB1_8
.LBB1_5: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=1
movq 40(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 48(%rsp), %rsi
movq 32(%rsp), %rdi
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movq %rsi, 112(%rsp)
movq %rdi, 104(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 88(%rsp), %rdi
movq %r12, %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
movl $_Z10bin_searchPiS_S_S_S_, %edi
movq %r15, %r9
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_7
.LBB1_8: # %._crit_edge12
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movq 40(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10bin_searchPiS_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10bin_searchPiS_S_S_S_,@object # @_Z10bin_searchPiS_S_S_S_
.section .rodata,"a",@progbits
.globl _Z10bin_searchPiS_S_S_S_
.p2align 3, 0x0
_Z10bin_searchPiS_S_S_S_:
.quad _Z25__device_stub__bin_searchPiS_S_S_S_
.size _Z10bin_searchPiS_S_S_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d\n"
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10bin_searchPiS_S_S_S_"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__bin_searchPiS_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10bin_searchPiS_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10bin_searchPiS_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fe20000000f00 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0060*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea8000c1e1900 */
/*0080*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0090*/ IADD3 R6, R11, 0x1, -R0 ; /* 0x000000010b067810 */
/* 0x004fcc0007ffe800 */
/*00a0*/ I2F R6, R6 ; /* 0x0000000600067306 */
/* 0x000e640000201400 */
/*00b0*/ FMUL R7, R6, 0.00390625 ; /* 0x3b80000006077820 */
/* 0x002fcc0000400000 */
/*00c0*/ F2I.CEIL.NTZ R13, R7 ; /* 0x00000007000d7305 */
/* 0x000e24000020b100 */
/*00d0*/ IMAD R0, R13, R8, R0 ; /* 0x000000080d007224 */
/* 0x001fca00078e0200 */
/*00e0*/ ISETP.GT.AND P0, PT, R0, R11, PT ; /* 0x0000000b0000720c */
/* 0x000fda0003f04270 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ IMAD.MOV.U32 R12, RZ, RZ, 0x4 ; /* 0x00000004ff0c7424 */
/* 0x000fe200078e00ff */
/*0110*/ MOV R8, c[0x0][0x180] ; /* 0x0000600000087a02 */
/* 0x000fe20000000f00 */
/*0120*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff097624 */
/* 0x000fe400078e00ff */
/*0130*/ IMAD.WIDE R6, R0, R12, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fc600078e020c */
/*0140*/ LDG.E R15, [R8.64] ; /* 0x00000004080f7981 */
/* 0x000ea8000c1e1900 */
/*0150*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*0160*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fe40007ffe0ff */
/*0170*/ IADD3 R10, R13, R0, RZ ; /* 0x000000000d0a7210 */
/* 0x000fc80007ffe0ff */
/*0180*/ IMNMX R10, R11, R10, PT ; /* 0x0000000a0b0a7217 */
/* 0x000fe40003800200 */
/*0190*/ ISETP.GE.AND P0, PT, R15, R6, PT ; /* 0x000000060f00720c */
/* 0x004fda0003f06270 */
/*01a0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01b0*/ IADD3 R9, R10, -0x1, RZ ; /* 0xffffffff0a097810 */
/* 0x000fca0007ffe0ff */
/*01c0*/ IMAD.WIDE R6, R9, R12, c[0x0][0x160] ; /* 0x0000580009067625 */
/* 0x000fcc00078e020c */
/*01d0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1900 */
/*01e0*/ ISETP.GT.AND P0, PT, R15, R6, PT ; /* 0x000000060f00720c */
/* 0x004fda0003f04270 */
/*01f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0200*/ STG.E [R4.64], R0 ; /* 0x0000000004007986 */
/* 0x000fe8000c101904 */
/*0210*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10bin_searchPiS_S_S_S_
.globl _Z10bin_searchPiS_S_S_S_
.p2align 8
.type _Z10bin_searchPiS_S_S_S_,@function
_Z10bin_searchPiS_S_S_S_:
s_load_b128 s[4:7], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_load_b32 s3, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_sub_i32 s8, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s8, s8, 1
v_cvt_f32_i32_e32 v1, s8
s_mov_b32 s8, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v1, 0x3b800000, v1
v_ceil_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, v0, v3, s[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ge_i32_e64 s3, v1
s_cbranch_execz .LBB0_4
s_load_b64 s[8:9], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s8, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
s_load_b32 s0, s[0:1], 0x0
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_ge_i32_e32 vcc_lo, s0, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_4
v_mul_lo_u32 v0, v3, v0
s_add_i32 s3, s3, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s2, v3, v0
v_min_i32_e32 v0, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, -1, v0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_add_co_u32 v3, vcc_lo, s8, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_le_i32_e32 vcc_lo, s0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
v_mov_b32_e32 v0, 0
s_clause 0x1
global_store_b32 v0, v1, s[4:5]
global_store_b32 v0, v2, s[6:7]
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10bin_searchPiS_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10bin_searchPiS_S_S_S_, .Lfunc_end0-_Z10bin_searchPiS_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10bin_searchPiS_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z10bin_searchPiS_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001c103_00000000-6_bin_search_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z10bin_searchPiS_S_S_S_PiS_S_S_S_
.type _Z38__device_stub__Z10bin_searchPiS_S_S_S_PiS_S_S_S_, @function
_Z38__device_stub__Z10bin_searchPiS_S_S_S_PiS_S_S_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10bin_searchPiS_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z38__device_stub__Z10bin_searchPiS_S_S_S_PiS_S_S_S_, .-_Z38__device_stub__Z10bin_searchPiS_S_S_S_PiS_S_S_S_
.globl _Z10bin_searchPiS_S_S_S_
.type _Z10bin_searchPiS_S_S_S_, @function
_Z10bin_searchPiS_S_S_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z10bin_searchPiS_S_S_S_PiS_S_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10bin_searchPiS_S_S_S_, .-_Z10bin_searchPiS_S_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d"
.LC1:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rsi
leaq .LC0(%rip), %rbx
movq %rbx, %rdi
call __isoc23_scanf@PLT
movslq 4(%rsp), %rsi
salq $2, %rsi
leaq 8(%rsp), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
movq 16(%rsp), %rsi
movq %rbx, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
cmpl $0, 4(%rsp)
jle .L12
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L13:
movq 8(%rsp), %rax
leaq (%rax,%rbx,4), %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addq $1, %rbx
cmpl %ebx, 4(%rsp)
jg .L13
.L12:
leaq 24(%rsp), %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
leaq 32(%rsp), %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
leaq 40(%rsp), %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
movq 24(%rsp), %rax
movl $0, (%rax)
movl 4(%rsp), %eax
subl $1, %eax
movq 32(%rsp), %rdx
movl %eax, (%rdx)
movq 24(%rsp), %rax
movl (%rax), %edx
movq 32(%rsp), %rax
cmpl (%rax), %edx
jl .L16
.L14:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call cudaDeviceSynchronize@PLT
movq 24(%rsp), %rax
movl (%rax), %edx
movq 32(%rsp), %rax
cmpl (%rax), %edx
jge .L14
.L16:
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L15
movq 16(%rsp), %r8
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z38__device_stub__Z10bin_searchPiS_S_S_S_PiS_S_S_S_
jmp .L15
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z10bin_searchPiS_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10bin_searchPiS_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "bin_search_cuda.hip"
.globl _Z25__device_stub__bin_searchPiS_S_S_S_ # -- Begin function _Z25__device_stub__bin_searchPiS_S_S_S_
.p2align 4, 0x90
.type _Z25__device_stub__bin_searchPiS_S_S_S_,@function
_Z25__device_stub__bin_searchPiS_S_S_S_: # @_Z25__device_stub__bin_searchPiS_S_S_S_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10bin_searchPiS_S_S_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z25__device_stub__bin_searchPiS_S_S_S_, .Lfunc_end0-_Z25__device_stub__bin_searchPiS_S_S_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 12(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 12(%rsp), %rsi
shlq $2, %rsi
leaq 40(%rsp), %rdi
movl $1, %edx
callq hipMallocManaged
leaq 32(%rsp), %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
movq 32(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
cmpl $0, 12(%rsp)
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %ebx, %ebx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq 40(%rsp), %rsi
addq %rbx, %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
incq %r14
movslq 12(%rsp), %rax
addq $4, %rbx
cmpq %rax, %r14
jl .LBB1_2
.LBB1_3: # %._crit_edge
leaq 24(%rsp), %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
leaq 48(%rsp), %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
movq 24(%rsp), %rax
movl $0, (%rax)
movl 12(%rsp), %ecx
decl %ecx
movq 16(%rsp), %rdx
movl %ecx, (%rdx)
movl (%rax), %esi
cmpl %ecx, %esi
jge .LBB1_8
# %bb.4: # %.lr.ph11
movabsq $4294967297, %rbx # imm = 0x100000001
leaq 255(%rbx), %r14
leaq 72(%rsp), %r12
leaq 64(%rsp), %r13
leaq 56(%rsp), %rbp
leaq 144(%rsp), %r15
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_5 Depth=1
callq hipDeviceSynchronize
movq 24(%rsp), %rax
movl (%rax), %esi
movq 16(%rsp), %rax
cmpl (%rax), %esi
jge .LBB1_8
.LBB1_5: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=1
movq 40(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 48(%rsp), %rsi
movq 32(%rsp), %rdi
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movq %rsi, 112(%rsp)
movq %rdi, 104(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 88(%rsp), %rdi
movq %r12, %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
movl $_Z10bin_searchPiS_S_S_S_, %edi
movq %r15, %r9
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_7
.LBB1_8: # %._crit_edge12
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movq 40(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10bin_searchPiS_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10bin_searchPiS_S_S_S_,@object # @_Z10bin_searchPiS_S_S_S_
.section .rodata,"a",@progbits
.globl _Z10bin_searchPiS_S_S_S_
.p2align 3, 0x0
_Z10bin_searchPiS_S_S_S_:
.quad _Z25__device_stub__bin_searchPiS_S_S_S_
.size _Z10bin_searchPiS_S_S_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d\n"
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10bin_searchPiS_S_S_S_"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__bin_searchPiS_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10bin_searchPiS_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "tensor_gpu.cuh"
#include <cuda_runtime.h>
tensor_gpu::tensor_gpu(const int p_size) : _size(p_size)
{
_data = init_data(_size);
}
tensor_gpu::tensor_gpu(const tensor_gpu& p_copy)
{
_size = p_copy._size;
_data = init_data(_size);
cudaMemcpy(_data, p_copy._data, sizeof(float) * p_copy._size, cudaMemcpyDeviceToDevice);
}
tensor_gpu& tensor_gpu::operator=(const tensor_gpu& p_copy)
{
if (_size != p_copy._size)
{
cudaFree(_data);
_data = init_data(_size);
}
cudaMemcpy(_data, p_copy._data, sizeof(float) * p_copy._size, cudaMemcpyDeviceToDevice);
_size = p_copy._size;
return *this;
}
tensor_gpu::~tensor_gpu()
{
_size = 0;
cudaFree(_data);
}
void tensor_gpu::to_gpu(float* p_cpu_data) const
{
cudaError_t error = cudaMemcpy(_data, p_cpu_data, sizeof(float) * _size, cudaMemcpyHostToDevice);
}
void tensor_gpu::to_cpu(float* p_cpu_data) const
{
cudaError_t error = cudaMemcpy(p_cpu_data, _data, sizeof(float) * _size, cudaMemcpyDeviceToHost);
}
float* tensor_gpu::init_data(int& p_size)
{
float* result;
cudaError_t error = cudaMalloc(reinterpret_cast<void**>(&result), sizeof(float) * p_size);
return result;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "tensor_gpu.cuh"
#include <cuda_runtime.h>
tensor_gpu::tensor_gpu(const int p_size) : _size(p_size)
{
_data = init_data(_size);
}
tensor_gpu::tensor_gpu(const tensor_gpu& p_copy)
{
_size = p_copy._size;
_data = init_data(_size);
cudaMemcpy(_data, p_copy._data, sizeof(float) * p_copy._size, cudaMemcpyDeviceToDevice);
}
tensor_gpu& tensor_gpu::operator=(const tensor_gpu& p_copy)
{
if (_size != p_copy._size)
{
cudaFree(_data);
_data = init_data(_size);
}
cudaMemcpy(_data, p_copy._data, sizeof(float) * p_copy._size, cudaMemcpyDeviceToDevice);
_size = p_copy._size;
return *this;
}
tensor_gpu::~tensor_gpu()
{
_size = 0;
cudaFree(_data);
}
void tensor_gpu::to_gpu(float* p_cpu_data) const
{
cudaError_t error = cudaMemcpy(_data, p_cpu_data, sizeof(float) * _size, cudaMemcpyHostToDevice);
}
void tensor_gpu::to_cpu(float* p_cpu_data) const
{
cudaError_t error = cudaMemcpy(p_cpu_data, _data, sizeof(float) * _size, cudaMemcpyDeviceToHost);
}
float* tensor_gpu::init_data(int& p_size)
{
float* result;
cudaError_t error = cudaMalloc(reinterpret_cast<void**>(&result), sizeof(float) * p_size);
return result;
} | .file "tmpxft_00004cfb_00000000-6_tensor_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2042:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2042:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.align 2
.globl _ZN10tensor_gpuD2Ev
.type _ZN10tensor_gpuD2Ev, @function
_ZN10tensor_gpuD2Ev:
.LFB2035:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA2035
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $0, (%rdi)
movq 8(%rdi), %rdi
call cudaFree@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2035:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA2035:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE2035-.LLSDACSB2035
.LLSDACSB2035:
.LLSDACSE2035:
.text
.size _ZN10tensor_gpuD2Ev, .-_ZN10tensor_gpuD2Ev
.globl _ZN10tensor_gpuD1Ev
.set _ZN10tensor_gpuD1Ev,_ZN10tensor_gpuD2Ev
.align 2
.globl _ZNK10tensor_gpu6to_gpuEPf
.type _ZNK10tensor_gpu6to_gpuEPf, @function
_ZNK10tensor_gpu6to_gpuEPf:
.LFB2037:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movslq (%rdi), %rdx
salq $2, %rdx
movq 8(%rdi), %rdi
movl $1, %ecx
call cudaMemcpy@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2037:
.size _ZNK10tensor_gpu6to_gpuEPf, .-_ZNK10tensor_gpu6to_gpuEPf
.align 2
.globl _ZNK10tensor_gpu6to_cpuEPf
.type _ZNK10tensor_gpu6to_cpuEPf, @function
_ZNK10tensor_gpu6to_cpuEPf:
.LFB2038:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rdi, %rax
movq %rsi, %rdi
movslq (%rax), %rdx
salq $2, %rdx
movq 8(%rax), %rsi
movl $2, %ecx
call cudaMemcpy@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2038:
.size _ZNK10tensor_gpu6to_cpuEPf, .-_ZNK10tensor_gpu6to_cpuEPf
.align 2
.globl _ZN10tensor_gpu9init_dataERi
.type _ZN10tensor_gpu9init_dataERi, @function
_ZN10tensor_gpu9init_dataERi:
.LFB2039:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movslq (%rdi), %rsi
salq $2, %rsi
movq %rsp, %rdi
call cudaMalloc@PLT
movq (%rsp), %rax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L12
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2039:
.size _ZN10tensor_gpu9init_dataERi, .-_ZN10tensor_gpu9init_dataERi
.align 2
.globl _ZN10tensor_gpuC2Ei
.type _ZN10tensor_gpuC2Ei, @function
_ZN10tensor_gpuC2Ei:
.LFB2028:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movl %esi, (%rdi)
call _ZN10tensor_gpu9init_dataERi
movq %rax, 8(%rbx)
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2028:
.size _ZN10tensor_gpuC2Ei, .-_ZN10tensor_gpuC2Ei
.globl _ZN10tensor_gpuC1Ei
.set _ZN10tensor_gpuC1Ei,_ZN10tensor_gpuC2Ei
.align 2
.globl _ZN10tensor_gpuC2ERKS_
.type _ZN10tensor_gpuC2ERKS_, @function
_ZN10tensor_gpuC2ERKS_:
.LFB2031:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
movq %rsi, %rbx
movl (%rsi), %eax
movl %eax, (%rdi)
call _ZN10tensor_gpu9init_dataERi
movq %rax, %rdi
movq %rax, 8(%rbp)
movslq (%rbx), %rdx
salq $2, %rdx
movq 8(%rbx), %rsi
movl $3, %ecx
call cudaMemcpy@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZN10tensor_gpuC2ERKS_, .-_ZN10tensor_gpuC2ERKS_
.globl _ZN10tensor_gpuC1ERKS_
.set _ZN10tensor_gpuC1ERKS_,_ZN10tensor_gpuC2ERKS_
.align 2
.globl _ZN10tensor_gpuaSERKS_
.type _ZN10tensor_gpuaSERKS_, @function
_ZN10tensor_gpuaSERKS_:
.LFB2033:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movq %rsi, %rbp
movl (%rsi), %eax
cmpl %eax, (%rdi)
jne .L20
.L18:
movslq 0(%rbp), %rdx
salq $2, %rdx
movq 8(%rbp), %rsi
movq 8(%rbx), %rdi
movl $3, %ecx
call cudaMemcpy@PLT
movl 0(%rbp), %eax
movl %eax, (%rbx)
movq %rbx, %rax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movq 8(%rdi), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call _ZN10tensor_gpu9init_dataERi
movq %rax, 8(%rbx)
jmp .L18
.cfi_endproc
.LFE2033:
.size _ZN10tensor_gpuaSERKS_, .-_ZN10tensor_gpuaSERKS_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "tensor_gpu.cuh"
#include <cuda_runtime.h>
tensor_gpu::tensor_gpu(const int p_size) : _size(p_size)
{
_data = init_data(_size);
}
tensor_gpu::tensor_gpu(const tensor_gpu& p_copy)
{
_size = p_copy._size;
_data = init_data(_size);
cudaMemcpy(_data, p_copy._data, sizeof(float) * p_copy._size, cudaMemcpyDeviceToDevice);
}
tensor_gpu& tensor_gpu::operator=(const tensor_gpu& p_copy)
{
if (_size != p_copy._size)
{
cudaFree(_data);
_data = init_data(_size);
}
cudaMemcpy(_data, p_copy._data, sizeof(float) * p_copy._size, cudaMemcpyDeviceToDevice);
_size = p_copy._size;
return *this;
}
tensor_gpu::~tensor_gpu()
{
_size = 0;
cudaFree(_data);
}
void tensor_gpu::to_gpu(float* p_cpu_data) const
{
cudaError_t error = cudaMemcpy(_data, p_cpu_data, sizeof(float) * _size, cudaMemcpyHostToDevice);
}
void tensor_gpu::to_cpu(float* p_cpu_data) const
{
cudaError_t error = cudaMemcpy(p_cpu_data, _data, sizeof(float) * _size, cudaMemcpyDeviceToHost);
}
float* tensor_gpu::init_data(int& p_size)
{
float* result;
cudaError_t error = cudaMalloc(reinterpret_cast<void**>(&result), sizeof(float) * p_size);
return result;
} | #pragma once
#include <hip/hip_runtime.h>
#ifdef _WIN64
#define COEUS_DLL_API __declspec(dllexport)
#else
#define COEUS_DLL_API
#endif
class COEUS_DLL_API tensor_gpu
{
friend class tensor;
private:
tensor_gpu(int p_size);
tensor_gpu(const tensor_gpu& p_copy);
tensor_gpu& operator=(const tensor_gpu& p_copy);
~tensor_gpu();
void to_gpu(float* p_cpu_data) const;
void to_cpu(float* p_cpu_data) const;
static float* init_data(int &p_size);
int _size;
float* _data;
}; |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #pragma once
#include <hip/hip_runtime.h>
#ifdef _WIN64
#define COEUS_DLL_API __declspec(dllexport)
#else
#define COEUS_DLL_API
#endif
class COEUS_DLL_API tensor_gpu
{
friend class tensor;
private:
tensor_gpu(int p_size);
tensor_gpu(const tensor_gpu& p_copy);
tensor_gpu& operator=(const tensor_gpu& p_copy);
~tensor_gpu();
void to_gpu(float* p_cpu_data) const;
void to_cpu(float* p_cpu_data) const;
static float* init_data(int &p_size);
int _size;
float* _data;
}; | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #pragma once
#include <hip/hip_runtime.h>
#ifdef _WIN64
#define COEUS_DLL_API __declspec(dllexport)
#else
#define COEUS_DLL_API
#endif
class COEUS_DLL_API tensor_gpu
{
friend class tensor;
private:
tensor_gpu(int p_size);
tensor_gpu(const tensor_gpu& p_copy);
tensor_gpu& operator=(const tensor_gpu& p_copy);
~tensor_gpu();
void to_gpu(float* p_cpu_data) const;
void to_cpu(float* p_cpu_data) const;
static float* init_data(int &p_size);
int _size;
float* _data;
}; | .text
.file "tensor_gpu.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00004cfb_00000000-6_tensor_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2042:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2042:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.align 2
.globl _ZN10tensor_gpuD2Ev
.type _ZN10tensor_gpuD2Ev, @function
_ZN10tensor_gpuD2Ev:
.LFB2035:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA2035
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $0, (%rdi)
movq 8(%rdi), %rdi
call cudaFree@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2035:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA2035:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE2035-.LLSDACSB2035
.LLSDACSB2035:
.LLSDACSE2035:
.text
.size _ZN10tensor_gpuD2Ev, .-_ZN10tensor_gpuD2Ev
.globl _ZN10tensor_gpuD1Ev
.set _ZN10tensor_gpuD1Ev,_ZN10tensor_gpuD2Ev
.align 2
.globl _ZNK10tensor_gpu6to_gpuEPf
.type _ZNK10tensor_gpu6to_gpuEPf, @function
_ZNK10tensor_gpu6to_gpuEPf:
.LFB2037:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movslq (%rdi), %rdx
salq $2, %rdx
movq 8(%rdi), %rdi
movl $1, %ecx
call cudaMemcpy@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2037:
.size _ZNK10tensor_gpu6to_gpuEPf, .-_ZNK10tensor_gpu6to_gpuEPf
.align 2
.globl _ZNK10tensor_gpu6to_cpuEPf
.type _ZNK10tensor_gpu6to_cpuEPf, @function
_ZNK10tensor_gpu6to_cpuEPf:
.LFB2038:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rdi, %rax
movq %rsi, %rdi
movslq (%rax), %rdx
salq $2, %rdx
movq 8(%rax), %rsi
movl $2, %ecx
call cudaMemcpy@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2038:
.size _ZNK10tensor_gpu6to_cpuEPf, .-_ZNK10tensor_gpu6to_cpuEPf
.align 2
.globl _ZN10tensor_gpu9init_dataERi
.type _ZN10tensor_gpu9init_dataERi, @function
_ZN10tensor_gpu9init_dataERi:
.LFB2039:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movslq (%rdi), %rsi
salq $2, %rsi
movq %rsp, %rdi
call cudaMalloc@PLT
movq (%rsp), %rax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L12
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2039:
.size _ZN10tensor_gpu9init_dataERi, .-_ZN10tensor_gpu9init_dataERi
.align 2
.globl _ZN10tensor_gpuC2Ei
.type _ZN10tensor_gpuC2Ei, @function
_ZN10tensor_gpuC2Ei:
.LFB2028:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movl %esi, (%rdi)
call _ZN10tensor_gpu9init_dataERi
movq %rax, 8(%rbx)
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2028:
.size _ZN10tensor_gpuC2Ei, .-_ZN10tensor_gpuC2Ei
.globl _ZN10tensor_gpuC1Ei
.set _ZN10tensor_gpuC1Ei,_ZN10tensor_gpuC2Ei
.align 2
.globl _ZN10tensor_gpuC2ERKS_
.type _ZN10tensor_gpuC2ERKS_, @function
_ZN10tensor_gpuC2ERKS_:
.LFB2031:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
movq %rsi, %rbx
movl (%rsi), %eax
movl %eax, (%rdi)
call _ZN10tensor_gpu9init_dataERi
movq %rax, %rdi
movq %rax, 8(%rbp)
movslq (%rbx), %rdx
salq $2, %rdx
movq 8(%rbx), %rsi
movl $3, %ecx
call cudaMemcpy@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZN10tensor_gpuC2ERKS_, .-_ZN10tensor_gpuC2ERKS_
.globl _ZN10tensor_gpuC1ERKS_
.set _ZN10tensor_gpuC1ERKS_,_ZN10tensor_gpuC2ERKS_
.align 2
.globl _ZN10tensor_gpuaSERKS_
.type _ZN10tensor_gpuaSERKS_, @function
_ZN10tensor_gpuaSERKS_:
.LFB2033:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movq %rsi, %rbp
movl (%rsi), %eax
cmpl %eax, (%rdi)
jne .L20
.L18:
movslq 0(%rbp), %rdx
salq $2, %rdx
movq 8(%rbp), %rsi
movq 8(%rbx), %rdi
movl $3, %ecx
call cudaMemcpy@PLT
movl 0(%rbp), %eax
movl %eax, (%rbx)
movq %rbx, %rax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movq 8(%rdi), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call _ZN10tensor_gpu9init_dataERi
movq %rax, 8(%rbx)
jmp .L18
.cfi_endproc
.LFE2033:
.size _ZN10tensor_gpuaSERKS_, .-_ZN10tensor_gpuaSERKS_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "tensor_gpu.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <time.h>
#include <unistd.h>
#include <stdio.h>
#include <stdlib.h>
// cache size constant for convenience/readability
const size_t CACHESIZE = 1.5 * (1<<20);
// function to handle CUDA API call error val returns
void check_error(cudaError_t cudaerr) {
if (cudaerr != cudaSuccess) {
printf("FAILED WITH ERROR: \"%s\".\n", cudaGetErrorString(cudaerr));
exit(-1);
}
}
// hammer attempt test kernel
__global__ void hammer_attempt(int* data, int* indices, int* eviction, int iterations, int numvals, int stride) {
uint tid = threadIdx.x + blockIdx.x * blockDim.x;
uint nthreads = blockDim.x * gridDim.x;
int sum;
for (int j = 0; j < iterations; j++) {
if (tid < 8) {
int index = indices[tid];
int n = data[index];
sum += (n << 1);
}
/*
if (tid == 0) {
int n1 = data[1413];
int n2 = data[56102];
int n3 = data[101336];
int n4 = data[169659];
int n5 = data[199685];
int n6 = data[272110];
int n7 = data[309174];
int n8 = data[368505];
sum = sum + n1 - n2 + n3 - n4 + n5 - n6 + n7 - n8;
}
*/
//__syncthreads();
for (int i = (tid * stride) + 393216; i < 393216*2.5; i += (nthreads * stride)) {
int n = data[i];
sum -= (n >> 1);
// __syncthreads();
}
/*
for (int i = 393216; i < 393216*3; i+=8) {
int n = data[i];
sum -= (n >> 1);
}
*/
/*
for (int i = tid; i < numvals; i += nthreads) {
int n = data[eviction[i]];
sum -= (n >> 1);
}
*/
}
}
int main(int argc, char** argv) {
// command line params, seed rand
int blocks = atoi(argv[1]);
int threads = atoi(argv[2]);
int stride = atoi(argv[3]);
int iterations = atoi(argv[4]);
srand(time(NULL));
// host array of random vals
int* data_host = (int*) malloc(2.5*CACHESIZE);
for (int i = 0; i < (2.5*CACHESIZE)/4; i++) {
data_host[i] = rand();
}
// copy to device
int* data_device;
check_error(cudaMalloc((void**)&data_device, 2.5*CACHESIZE));
check_error(cudaMemcpy(data_device, data_host, 2.5*CACHESIZE, cudaMemcpyHostToDevice));
// host array for addresses
// pick addresses in first 1.5MB of data
// - explanation of values -
// 393216: number of integers containted in 1.5MB cache
// 49512: number of integers in a 1/8 slice of cache
// 24576: number of integers in a 1/16 slice of cache
// address choosing process: pick address in first 1/16, skip next 1/16, pick address in next 1/16...
int* indices_host = (int*)malloc(sizeof(int)*8);
for (int i = 0; i < 8; i++) {
int sector_start = i * 49512;
indices_host[i] = (rand() % 24576) + sector_start;
printf("%d\n", indices_host[i]);
}
// copy to device
int* indices_device;
check_error(cudaMalloc((void**)&indices_device, sizeof(int)*8));
check_error(cudaMemcpy(indices_device, indices_host, sizeof(int)*8, cudaMemcpyHostToDevice));
// host array of indices for eviction purposes
int numvals = (393216*2) / stride;
int* eviction_host = (int*)malloc(sizeof(int)*numvals);
for (int i = 0; i < numvals; i++) {
eviction_host[i] = 393216 + (i * stride);
}
// copy to device
int* eviction_device;
check_error(cudaMalloc((void**)&eviction_device, sizeof(int)*numvals));
check_error(cudaMemcpy(eviction_device, eviction_host, sizeof(int)*numvals, cudaMemcpyHostToDevice));
// launch kernel
hammer_attempt<<<blocks, threads>>>(data_device, indices_device, eviction_device, iterations, numvals, stride);
check_error(cudaDeviceSynchronize());
} | code for sm_80
Function : _Z14hammer_attemptPiS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fc80000000f00 */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0050*/ BRA 0x50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <time.h>
#include <unistd.h>
#include <stdio.h>
#include <stdlib.h>
// cache size constant for convenience/readability
const size_t CACHESIZE = 1.5 * (1<<20);
// function to handle CUDA API call error val returns
void check_error(cudaError_t cudaerr) {
if (cudaerr != cudaSuccess) {
printf("FAILED WITH ERROR: \"%s\".\n", cudaGetErrorString(cudaerr));
exit(-1);
}
}
// hammer attempt test kernel
__global__ void hammer_attempt(int* data, int* indices, int* eviction, int iterations, int numvals, int stride) {
uint tid = threadIdx.x + blockIdx.x * blockDim.x;
uint nthreads = blockDim.x * gridDim.x;
int sum;
for (int j = 0; j < iterations; j++) {
if (tid < 8) {
int index = indices[tid];
int n = data[index];
sum += (n << 1);
}
/*
if (tid == 0) {
int n1 = data[1413];
int n2 = data[56102];
int n3 = data[101336];
int n4 = data[169659];
int n5 = data[199685];
int n6 = data[272110];
int n7 = data[309174];
int n8 = data[368505];
sum = sum + n1 - n2 + n3 - n4 + n5 - n6 + n7 - n8;
}
*/
//__syncthreads();
for (int i = (tid * stride) + 393216; i < 393216*2.5; i += (nthreads * stride)) {
int n = data[i];
sum -= (n >> 1);
// __syncthreads();
}
/*
for (int i = 393216; i < 393216*3; i+=8) {
int n = data[i];
sum -= (n >> 1);
}
*/
/*
for (int i = tid; i < numvals; i += nthreads) {
int n = data[eviction[i]];
sum -= (n >> 1);
}
*/
}
}
int main(int argc, char** argv) {
// command line params, seed rand
int blocks = atoi(argv[1]);
int threads = atoi(argv[2]);
int stride = atoi(argv[3]);
int iterations = atoi(argv[4]);
srand(time(NULL));
// host array of random vals
int* data_host = (int*) malloc(2.5*CACHESIZE);
for (int i = 0; i < (2.5*CACHESIZE)/4; i++) {
data_host[i] = rand();
}
// copy to device
int* data_device;
check_error(cudaMalloc((void**)&data_device, 2.5*CACHESIZE));
check_error(cudaMemcpy(data_device, data_host, 2.5*CACHESIZE, cudaMemcpyHostToDevice));
// host array for addresses
// pick addresses in first 1.5MB of data
// - explanation of values -
// 393216: number of integers containted in 1.5MB cache
// 49512: number of integers in a 1/8 slice of cache
// 24576: number of integers in a 1/16 slice of cache
// address choosing process: pick address in first 1/16, skip next 1/16, pick address in next 1/16...
int* indices_host = (int*)malloc(sizeof(int)*8);
for (int i = 0; i < 8; i++) {
int sector_start = i * 49512;
indices_host[i] = (rand() % 24576) + sector_start;
printf("%d\n", indices_host[i]);
}
// copy to device
int* indices_device;
check_error(cudaMalloc((void**)&indices_device, sizeof(int)*8));
check_error(cudaMemcpy(indices_device, indices_host, sizeof(int)*8, cudaMemcpyHostToDevice));
// host array of indices for eviction purposes
int numvals = (393216*2) / stride;
int* eviction_host = (int*)malloc(sizeof(int)*numvals);
for (int i = 0; i < numvals; i++) {
eviction_host[i] = 393216 + (i * stride);
}
// copy to device
int* eviction_device;
check_error(cudaMalloc((void**)&eviction_device, sizeof(int)*numvals));
check_error(cudaMemcpy(eviction_device, eviction_host, sizeof(int)*numvals, cudaMemcpyHostToDevice));
// launch kernel
hammer_attempt<<<blocks, threads>>>(data_device, indices_device, eviction_device, iterations, numvals, stride);
check_error(cudaDeviceSynchronize());
} | .file "tmpxft_0016a511_00000000-6_indirect_hammer.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "FAILED WITH ERROR: \"%s\".\n"
.text
.globl _Z11check_error9cudaError
.type _Z11check_error9cudaError, @function
_Z11check_error9cudaError:
.LFB2070:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2070:
.size _Z11check_error9cudaError, .-_Z11check_error9cudaError
.globl _Z41__device_stub__Z14hammer_attemptPiS_S_iiiPiS_S_iii
.type _Z41__device_stub__Z14hammer_attemptPiS_S_iiiPiS_S_iii, @function
_Z41__device_stub__Z14hammer_attemptPiS_S_iiiPiS_S_iii:
.LFB2096:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14hammer_attemptPiS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2096:
.size _Z41__device_stub__Z14hammer_attemptPiS_S_iiiPiS_S_iii, .-_Z41__device_stub__Z14hammer_attemptPiS_S_iiiPiS_S_iii
.globl _Z14hammer_attemptPiS_S_iii
.type _Z14hammer_attemptPiS_S_iii, @function
_Z14hammer_attemptPiS_S_iii:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z14hammer_attemptPiS_S_iiiPiS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _Z14hammer_attemptPiS_S_iii, .-_Z14hammer_attemptPiS_S_iii
.section .rodata.str1.1
.LC1:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB2071:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 16(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movl %eax, 12(%rsp)
movq 32(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 24(%rsp)
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $3932160, %edi
call malloc@PLT
movq %rax, %r12
movq %rax, %rbx
leaq 3932160(%rax), %rbp
.L18:
call rand@PLT
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L18
leaq 40(%rsp), %rdi
movl $3932160, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z11check_error9cudaError
movl $1, %ecx
movl $3932160, %edx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z11check_error9cudaError
movl $32, %edi
call malloc@PLT
movq %rax, %r14
movq %rax, %rbp
movl $0, %ebx
leaq .LC1(%rip), %r12
.L19:
call rand@PLT
movslq %eax, %rdx
imulq $715827883, %rdx, %rdx
sarq $44, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,2), %edx
sall $13, %edx
subl %edx, %eax
leal (%rax,%rbx), %edx
movl %edx, 0(%rbp)
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $49512, %ebx
addq $4, %rbp
cmpl $396096, %ebx
jne .L19
leaq 48(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z11check_error9cudaError
movl $1, %ecx
movl $32, %edx
movq %r14, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z11check_error9cudaError
movl $786432, %eax
movl $0, %edx
idivl 12(%rsp)
movl %eax, %ebp
movslq %eax, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
testl %ebp, %ebp
jle .L20
movl %r13d, %esi
leaq (%rbx,%rax), %rcx
movl $393216, %edx
.L21:
movl %edx, (%rax)
addl %esi, %edx
addq $4, %rax
cmpq %rcx, %rax
jne .L21
.L20:
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call _Z11check_error9cudaError
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z11check_error9cudaError
movl %r15d, 76(%rsp)
movl $1, 80(%rsp)
movl 16(%rsp), %eax
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L22:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
call _Z11check_error9cudaError
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movl %r13d, %r9d
movl %ebp, %r8d
movl 24(%rsp), %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z41__device_stub__Z14hammer_attemptPiS_S_iiiPiS_S_iii
jmp .L22
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2071:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z14hammer_attemptPiS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z14hammer_attemptPiS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <time.h>
#include <unistd.h>
#include <stdio.h>
#include <stdlib.h>
// cache size constant for convenience/readability
const size_t CACHESIZE = 1.5 * (1<<20);
// function to handle CUDA API call error val returns
void check_error(cudaError_t cudaerr) {
if (cudaerr != cudaSuccess) {
printf("FAILED WITH ERROR: \"%s\".\n", cudaGetErrorString(cudaerr));
exit(-1);
}
}
// hammer attempt test kernel
__global__ void hammer_attempt(int* data, int* indices, int* eviction, int iterations, int numvals, int stride) {
uint tid = threadIdx.x + blockIdx.x * blockDim.x;
uint nthreads = blockDim.x * gridDim.x;
int sum;
for (int j = 0; j < iterations; j++) {
if (tid < 8) {
int index = indices[tid];
int n = data[index];
sum += (n << 1);
}
/*
if (tid == 0) {
int n1 = data[1413];
int n2 = data[56102];
int n3 = data[101336];
int n4 = data[169659];
int n5 = data[199685];
int n6 = data[272110];
int n7 = data[309174];
int n8 = data[368505];
sum = sum + n1 - n2 + n3 - n4 + n5 - n6 + n7 - n8;
}
*/
//__syncthreads();
for (int i = (tid * stride) + 393216; i < 393216*2.5; i += (nthreads * stride)) {
int n = data[i];
sum -= (n >> 1);
// __syncthreads();
}
/*
for (int i = 393216; i < 393216*3; i+=8) {
int n = data[i];
sum -= (n >> 1);
}
*/
/*
for (int i = tid; i < numvals; i += nthreads) {
int n = data[eviction[i]];
sum -= (n >> 1);
}
*/
}
}
int main(int argc, char** argv) {
// command line params, seed rand
int blocks = atoi(argv[1]);
int threads = atoi(argv[2]);
int stride = atoi(argv[3]);
int iterations = atoi(argv[4]);
srand(time(NULL));
// host array of random vals
int* data_host = (int*) malloc(2.5*CACHESIZE);
for (int i = 0; i < (2.5*CACHESIZE)/4; i++) {
data_host[i] = rand();
}
// copy to device
int* data_device;
check_error(cudaMalloc((void**)&data_device, 2.5*CACHESIZE));
check_error(cudaMemcpy(data_device, data_host, 2.5*CACHESIZE, cudaMemcpyHostToDevice));
// host array for addresses
// pick addresses in first 1.5MB of data
// - explanation of values -
// 393216: number of integers containted in 1.5MB cache
// 49512: number of integers in a 1/8 slice of cache
// 24576: number of integers in a 1/16 slice of cache
// address choosing process: pick address in first 1/16, skip next 1/16, pick address in next 1/16...
int* indices_host = (int*)malloc(sizeof(int)*8);
for (int i = 0; i < 8; i++) {
int sector_start = i * 49512;
indices_host[i] = (rand() % 24576) + sector_start;
printf("%d\n", indices_host[i]);
}
// copy to device
int* indices_device;
check_error(cudaMalloc((void**)&indices_device, sizeof(int)*8));
check_error(cudaMemcpy(indices_device, indices_host, sizeof(int)*8, cudaMemcpyHostToDevice));
// host array of indices for eviction purposes
int numvals = (393216*2) / stride;
int* eviction_host = (int*)malloc(sizeof(int)*numvals);
for (int i = 0; i < numvals; i++) {
eviction_host[i] = 393216 + (i * stride);
}
// copy to device
int* eviction_device;
check_error(cudaMalloc((void**)&eviction_device, sizeof(int)*numvals));
check_error(cudaMemcpy(eviction_device, eviction_host, sizeof(int)*numvals, cudaMemcpyHostToDevice));
// launch kernel
hammer_attempt<<<blocks, threads>>>(data_device, indices_device, eviction_device, iterations, numvals, stride);
check_error(cudaDeviceSynchronize());
} | #include <hip/hip_runtime.h>
#include <time.h>
#include <unistd.h>
#include <stdio.h>
#include <stdlib.h>
// cache size constant for convenience/readability
const size_t CACHESIZE = 1.5 * (1<<20);
// function to handle CUDA API call error val returns
void check_error(hipError_t cudaerr) {
if (cudaerr != hipSuccess) {
printf("FAILED WITH ERROR: \"%s\".\n", hipGetErrorString(cudaerr));
exit(-1);
}
}
// hammer attempt test kernel
__global__ void hammer_attempt(int* data, int* indices, int* eviction, int iterations, int numvals, int stride) {
uint tid = threadIdx.x + blockIdx.x * blockDim.x;
uint nthreads = blockDim.x * gridDim.x;
int sum;
for (int j = 0; j < iterations; j++) {
if (tid < 8) {
int index = indices[tid];
int n = data[index];
sum += (n << 1);
}
/*
if (tid == 0) {
int n1 = data[1413];
int n2 = data[56102];
int n3 = data[101336];
int n4 = data[169659];
int n5 = data[199685];
int n6 = data[272110];
int n7 = data[309174];
int n8 = data[368505];
sum = sum + n1 - n2 + n3 - n4 + n5 - n6 + n7 - n8;
}
*/
//__syncthreads();
for (int i = (tid * stride) + 393216; i < 393216*2.5; i += (nthreads * stride)) {
int n = data[i];
sum -= (n >> 1);
// __syncthreads();
}
/*
for (int i = 393216; i < 393216*3; i+=8) {
int n = data[i];
sum -= (n >> 1);
}
*/
/*
for (int i = tid; i < numvals; i += nthreads) {
int n = data[eviction[i]];
sum -= (n >> 1);
}
*/
}
}
int main(int argc, char** argv) {
// command line params, seed rand
int blocks = atoi(argv[1]);
int threads = atoi(argv[2]);
int stride = atoi(argv[3]);
int iterations = atoi(argv[4]);
srand(time(NULL));
// host array of random vals
int* data_host = (int*) malloc(2.5*CACHESIZE);
for (int i = 0; i < (2.5*CACHESIZE)/4; i++) {
data_host[i] = rand();
}
// copy to device
int* data_device;
check_error(hipMalloc((void**)&data_device, 2.5*CACHESIZE));
check_error(hipMemcpy(data_device, data_host, 2.5*CACHESIZE, hipMemcpyHostToDevice));
// host array for addresses
// pick addresses in first 1.5MB of data
// - explanation of values -
// 393216: number of integers containted in 1.5MB cache
// 49512: number of integers in a 1/8 slice of cache
// 24576: number of integers in a 1/16 slice of cache
// address choosing process: pick address in first 1/16, skip next 1/16, pick address in next 1/16...
int* indices_host = (int*)malloc(sizeof(int)*8);
for (int i = 0; i < 8; i++) {
int sector_start = i * 49512;
indices_host[i] = (rand() % 24576) + sector_start;
printf("%d\n", indices_host[i]);
}
// copy to device
int* indices_device;
check_error(hipMalloc((void**)&indices_device, sizeof(int)*8));
check_error(hipMemcpy(indices_device, indices_host, sizeof(int)*8, hipMemcpyHostToDevice));
// host array of indices for eviction purposes
int numvals = (393216*2) / stride;
int* eviction_host = (int*)malloc(sizeof(int)*numvals);
for (int i = 0; i < numvals; i++) {
eviction_host[i] = 393216 + (i * stride);
}
// copy to device
int* eviction_device;
check_error(hipMalloc((void**)&eviction_device, sizeof(int)*numvals));
check_error(hipMemcpy(eviction_device, eviction_host, sizeof(int)*numvals, hipMemcpyHostToDevice));
// launch kernel
hammer_attempt<<<blocks, threads>>>(data_device, indices_device, eviction_device, iterations, numvals, stride);
check_error(hipDeviceSynchronize());
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <time.h>
#include <unistd.h>
#include <stdio.h>
#include <stdlib.h>
// cache size constant for convenience/readability
const size_t CACHESIZE = 1.5 * (1<<20);
// function to handle CUDA API call error val returns
void check_error(hipError_t cudaerr) {
if (cudaerr != hipSuccess) {
printf("FAILED WITH ERROR: \"%s\".\n", hipGetErrorString(cudaerr));
exit(-1);
}
}
// hammer attempt test kernel
__global__ void hammer_attempt(int* data, int* indices, int* eviction, int iterations, int numvals, int stride) {
uint tid = threadIdx.x + blockIdx.x * blockDim.x;
uint nthreads = blockDim.x * gridDim.x;
int sum;
for (int j = 0; j < iterations; j++) {
if (tid < 8) {
int index = indices[tid];
int n = data[index];
sum += (n << 1);
}
/*
if (tid == 0) {
int n1 = data[1413];
int n2 = data[56102];
int n3 = data[101336];
int n4 = data[169659];
int n5 = data[199685];
int n6 = data[272110];
int n7 = data[309174];
int n8 = data[368505];
sum = sum + n1 - n2 + n3 - n4 + n5 - n6 + n7 - n8;
}
*/
//__syncthreads();
for (int i = (tid * stride) + 393216; i < 393216*2.5; i += (nthreads * stride)) {
int n = data[i];
sum -= (n >> 1);
// __syncthreads();
}
/*
for (int i = 393216; i < 393216*3; i+=8) {
int n = data[i];
sum -= (n >> 1);
}
*/
/*
for (int i = tid; i < numvals; i += nthreads) {
int n = data[eviction[i]];
sum -= (n >> 1);
}
*/
}
}
int main(int argc, char** argv) {
// command line params, seed rand
int blocks = atoi(argv[1]);
int threads = atoi(argv[2]);
int stride = atoi(argv[3]);
int iterations = atoi(argv[4]);
srand(time(NULL));
// host array of random vals
int* data_host = (int*) malloc(2.5*CACHESIZE);
for (int i = 0; i < (2.5*CACHESIZE)/4; i++) {
data_host[i] = rand();
}
// copy to device
int* data_device;
check_error(hipMalloc((void**)&data_device, 2.5*CACHESIZE));
check_error(hipMemcpy(data_device, data_host, 2.5*CACHESIZE, hipMemcpyHostToDevice));
// host array for addresses
// pick addresses in first 1.5MB of data
// - explanation of values -
// 393216: number of integers containted in 1.5MB cache
// 49512: number of integers in a 1/8 slice of cache
// 24576: number of integers in a 1/16 slice of cache
// address choosing process: pick address in first 1/16, skip next 1/16, pick address in next 1/16...
int* indices_host = (int*)malloc(sizeof(int)*8);
for (int i = 0; i < 8; i++) {
int sector_start = i * 49512;
indices_host[i] = (rand() % 24576) + sector_start;
printf("%d\n", indices_host[i]);
}
// copy to device
int* indices_device;
check_error(hipMalloc((void**)&indices_device, sizeof(int)*8));
check_error(hipMemcpy(indices_device, indices_host, sizeof(int)*8, hipMemcpyHostToDevice));
// host array of indices for eviction purposes
int numvals = (393216*2) / stride;
int* eviction_host = (int*)malloc(sizeof(int)*numvals);
for (int i = 0; i < numvals; i++) {
eviction_host[i] = 393216 + (i * stride);
}
// copy to device
int* eviction_device;
check_error(hipMalloc((void**)&eviction_device, sizeof(int)*numvals));
check_error(hipMemcpy(eviction_device, eviction_host, sizeof(int)*numvals, hipMemcpyHostToDevice));
// launch kernel
hammer_attempt<<<blocks, threads>>>(data_device, indices_device, eviction_device, iterations, numvals, stride);
check_error(hipDeviceSynchronize());
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14hammer_attemptPiS_S_iii
.globl _Z14hammer_attemptPiS_S_iii
.p2align 8
.type _Z14hammer_attemptPiS_S_iii,@function
_Z14hammer_attemptPiS_S_iii:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14hammer_attemptPiS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14hammer_attemptPiS_S_iii, .Lfunc_end0-_Z14hammer_attemptPiS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14hammer_attemptPiS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z14hammer_attemptPiS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <time.h>
#include <unistd.h>
#include <stdio.h>
#include <stdlib.h>
// cache size constant for convenience/readability
const size_t CACHESIZE = 1.5 * (1<<20);
// function to handle CUDA API call error val returns
void check_error(hipError_t cudaerr) {
if (cudaerr != hipSuccess) {
printf("FAILED WITH ERROR: \"%s\".\n", hipGetErrorString(cudaerr));
exit(-1);
}
}
// hammer attempt test kernel
__global__ void hammer_attempt(int* data, int* indices, int* eviction, int iterations, int numvals, int stride) {
uint tid = threadIdx.x + blockIdx.x * blockDim.x;
uint nthreads = blockDim.x * gridDim.x;
int sum;
for (int j = 0; j < iterations; j++) {
if (tid < 8) {
int index = indices[tid];
int n = data[index];
sum += (n << 1);
}
/*
if (tid == 0) {
int n1 = data[1413];
int n2 = data[56102];
int n3 = data[101336];
int n4 = data[169659];
int n5 = data[199685];
int n6 = data[272110];
int n7 = data[309174];
int n8 = data[368505];
sum = sum + n1 - n2 + n3 - n4 + n5 - n6 + n7 - n8;
}
*/
//__syncthreads();
for (int i = (tid * stride) + 393216; i < 393216*2.5; i += (nthreads * stride)) {
int n = data[i];
sum -= (n >> 1);
// __syncthreads();
}
/*
for (int i = 393216; i < 393216*3; i+=8) {
int n = data[i];
sum -= (n >> 1);
}
*/
/*
for (int i = tid; i < numvals; i += nthreads) {
int n = data[eviction[i]];
sum -= (n >> 1);
}
*/
}
}
int main(int argc, char** argv) {
// command line params, seed rand
int blocks = atoi(argv[1]);
int threads = atoi(argv[2]);
int stride = atoi(argv[3]);
int iterations = atoi(argv[4]);
srand(time(NULL));
// host array of random vals
int* data_host = (int*) malloc(2.5*CACHESIZE);
for (int i = 0; i < (2.5*CACHESIZE)/4; i++) {
data_host[i] = rand();
}
// copy to device
int* data_device;
check_error(hipMalloc((void**)&data_device, 2.5*CACHESIZE));
check_error(hipMemcpy(data_device, data_host, 2.5*CACHESIZE, hipMemcpyHostToDevice));
// host array for addresses
// pick addresses in first 1.5MB of data
// - explanation of values -
// 393216: number of integers containted in 1.5MB cache
// 49512: number of integers in a 1/8 slice of cache
// 24576: number of integers in a 1/16 slice of cache
// address choosing process: pick address in first 1/16, skip next 1/16, pick address in next 1/16...
int* indices_host = (int*)malloc(sizeof(int)*8);
for (int i = 0; i < 8; i++) {
int sector_start = i * 49512;
indices_host[i] = (rand() % 24576) + sector_start;
printf("%d\n", indices_host[i]);
}
// copy to device
int* indices_device;
check_error(hipMalloc((void**)&indices_device, sizeof(int)*8));
check_error(hipMemcpy(indices_device, indices_host, sizeof(int)*8, hipMemcpyHostToDevice));
// host array of indices for eviction purposes
int numvals = (393216*2) / stride;
int* eviction_host = (int*)malloc(sizeof(int)*numvals);
for (int i = 0; i < numvals; i++) {
eviction_host[i] = 393216 + (i * stride);
}
// copy to device
int* eviction_device;
check_error(hipMalloc((void**)&eviction_device, sizeof(int)*numvals));
check_error(hipMemcpy(eviction_device, eviction_host, sizeof(int)*numvals, hipMemcpyHostToDevice));
// launch kernel
hammer_attempt<<<blocks, threads>>>(data_device, indices_device, eviction_device, iterations, numvals, stride);
check_error(hipDeviceSynchronize());
} | .text
.file "indirect_hammer.hip"
.globl _Z11check_error10hipError_t # -- Begin function _Z11check_error10hipError_t
.p2align 4, 0x90
.type _Z11check_error10hipError_t,@function
_Z11check_error10hipError_t: # @_Z11check_error10hipError_t
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB0_2
# %bb.1:
retq
.LBB0_2:
pushq %rax
.cfi_def_cfa_offset 16
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end0:
.size _Z11check_error10hipError_t, .Lfunc_end0-_Z11check_error10hipError_t
.cfi_endproc
# -- End function
.globl _Z29__device_stub__hammer_attemptPiS_S_iii # -- Begin function _Z29__device_stub__hammer_attemptPiS_S_iii
.p2align 4, 0x90
.type _Z29__device_stub__hammer_attemptPiS_S_iii,@function
_Z29__device_stub__hammer_attemptPiS_S_iii: # @_Z29__device_stub__hammer_attemptPiS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14hammer_attemptPiS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z29__device_stub__hammer_attemptPiS_S_iii, .Lfunc_end1-_Z29__device_stub__hammer_attemptPiS_S_iii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %r13d, %r13d
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movq 24(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 32(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $3932160, %edi # imm = 0x3C0000
callq malloc
movq %rax, %r14
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
callq rand
movl %eax, (%r14,%r13,4)
incq %r13
cmpq $983040, %r13 # imm = 0xF0000
jne .LBB2_1
# %bb.2:
leaq 40(%rsp), %rdi
movl $3932160, %esi # imm = 0x3C0000
callq hipMalloc
testl %eax, %eax
jne .LBB2_17
# %bb.3: # %_Z11check_error10hipError_t.exit
movq %rbp, 48(%rsp) # 8-byte Spill
movq 40(%rsp), %rdi
movl $3932160, %edx # imm = 0x3C0000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_17
# %bb.4: # %_Z11check_error10hipError_t.exit41
movl $32, %edi
callq malloc
movq %rax, %r13
movq %rax, %r14
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
callq rand
movslq %eax, %rsi
imulq $715827883, %rsi, %rax # imm = 0x2AAAAAAB
movq %rax, %rcx
shrq $63, %rcx
shrq $44, %rax
addl %ecx, %eax
shll $13, %eax
leal (%rax,%rax,2), %eax
subl %eax, %esi
addl %ebp, %esi
movl %esi, (%r14)
movl $.L.str.1, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
addq $49512, %rbp # imm = 0xC168
addq $4, %r14
cmpq $396096, %rbp # imm = 0x60B40
jne .LBB2_5
# %bb.6:
leaq 32(%rsp), %rdi
movl $32, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB2_17
# %bb.7: # %_Z11check_error10hipError_t.exit43
movq 32(%rsp), %rdi
movl $32, %edx
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_17
# %bb.8: # %_Z11check_error10hipError_t.exit45
movl $786432, %eax # imm = 0xC0000
xorl %edx, %edx
idivl %ebx
movl %eax, %ebp
movslq %eax, %r13
shlq $2, %r13
movq %r13, %rdi
callq malloc
movq %rax, %r14
testl %ebp, %ebp
jle .LBB2_11
# %bb.9: # %.lr.ph.preheader
movl %ebp, %eax
movl $393216, %ecx # imm = 0x60000
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_10: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ecx, (%r14,%rdx,4)
incq %rdx
addl %ebx, %ecx
cmpq %rdx, %rax
jne .LBB2_10
.LBB2_11: # %._crit_edge
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_17
# %bb.12: # %_Z11check_error10hipError_t.exit47
movq 24(%rsp), %rdi
movq %r14, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_17
# %bb.13: # %_Z11check_error10hipError_t.exit49
movl %r15d, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %r12d, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_15
# %bb.14:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movq 48(%rsp), %rax # 8-byte Reload
movl %eax, 20(%rsp)
movl %ebp, 16(%rsp)
movl %ebx, 12(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z14hammer_attemptPiS_S_iii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_15:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_17
# %bb.16: # %_Z11check_error10hipError_t.exit51
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_17:
.cfi_def_cfa_offset 240
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14hammer_attemptPiS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "FAILED WITH ERROR: \"%s\".\n"
.size .L.str, 26
.type _Z14hammer_attemptPiS_S_iii,@object # @_Z14hammer_attemptPiS_S_iii
.section .rodata,"a",@progbits
.globl _Z14hammer_attemptPiS_S_iii
.p2align 3, 0x0
_Z14hammer_attemptPiS_S_iii:
.quad _Z29__device_stub__hammer_attemptPiS_S_iii
.size _Z14hammer_attemptPiS_S_iii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d\n"
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14hammer_attemptPiS_S_iii"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__hammer_attemptPiS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14hammer_attemptPiS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14hammer_attemptPiS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fc80000000f00 */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0050*/ BRA 0x50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14hammer_attemptPiS_S_iii
.globl _Z14hammer_attemptPiS_S_iii
.p2align 8
.type _Z14hammer_attemptPiS_S_iii,@function
_Z14hammer_attemptPiS_S_iii:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14hammer_attemptPiS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14hammer_attemptPiS_S_iii, .Lfunc_end0-_Z14hammer_attemptPiS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14hammer_attemptPiS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z14hammer_attemptPiS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016a511_00000000-6_indirect_hammer.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "FAILED WITH ERROR: \"%s\".\n"
.text
.globl _Z11check_error9cudaError
.type _Z11check_error9cudaError, @function
_Z11check_error9cudaError:
.LFB2070:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
subq $8, %rsp
.cfi_def_cfa_offset 16
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE2070:
.size _Z11check_error9cudaError, .-_Z11check_error9cudaError
.globl _Z41__device_stub__Z14hammer_attemptPiS_S_iiiPiS_S_iii
.type _Z41__device_stub__Z14hammer_attemptPiS_S_iiiPiS_S_iii, @function
_Z41__device_stub__Z14hammer_attemptPiS_S_iiiPiS_S_iii:
.LFB2096:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14hammer_attemptPiS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2096:
.size _Z41__device_stub__Z14hammer_attemptPiS_S_iiiPiS_S_iii, .-_Z41__device_stub__Z14hammer_attemptPiS_S_iiiPiS_S_iii
.globl _Z14hammer_attemptPiS_S_iii
.type _Z14hammer_attemptPiS_S_iii, @function
_Z14hammer_attemptPiS_S_iii:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z14hammer_attemptPiS_S_iiiPiS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _Z14hammer_attemptPiS_S_iii, .-_Z14hammer_attemptPiS_S_iii
.section .rodata.str1.1
.LC1:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB2071:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 16(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movl %eax, 12(%rsp)
movq 32(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 24(%rsp)
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $3932160, %edi
call malloc@PLT
movq %rax, %r12
movq %rax, %rbx
leaq 3932160(%rax), %rbp
.L18:
call rand@PLT
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L18
leaq 40(%rsp), %rdi
movl $3932160, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z11check_error9cudaError
movl $1, %ecx
movl $3932160, %edx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z11check_error9cudaError
movl $32, %edi
call malloc@PLT
movq %rax, %r14
movq %rax, %rbp
movl $0, %ebx
leaq .LC1(%rip), %r12
.L19:
call rand@PLT
movslq %eax, %rdx
imulq $715827883, %rdx, %rdx
sarq $44, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,2), %edx
sall $13, %edx
subl %edx, %eax
leal (%rax,%rbx), %edx
movl %edx, 0(%rbp)
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $49512, %ebx
addq $4, %rbp
cmpl $396096, %ebx
jne .L19
leaq 48(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
movl %eax, %edi
call _Z11check_error9cudaError
movl $1, %ecx
movl $32, %edx
movq %r14, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z11check_error9cudaError
movl $786432, %eax
movl $0, %edx
idivl 12(%rsp)
movl %eax, %ebp
movslq %eax, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
testl %ebp, %ebp
jle .L20
movl %r13d, %esi
leaq (%rbx,%rax), %rcx
movl $393216, %edx
.L21:
movl %edx, (%rax)
addl %esi, %edx
addq $4, %rax
cmpq %rcx, %rax
jne .L21
.L20:
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
call _Z11check_error9cudaError
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
call _Z11check_error9cudaError
movl %r15d, 76(%rsp)
movl $1, 80(%rsp)
movl 16(%rsp), %eax
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L22:
call cudaDeviceSynchronize@PLT
movl %eax, %edi
call _Z11check_error9cudaError
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movl %r13d, %r9d
movl %ebp, %r8d
movl 24(%rsp), %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z41__device_stub__Z14hammer_attemptPiS_S_iiiPiS_S_iii
jmp .L22
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2071:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z14hammer_attemptPiS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z14hammer_attemptPiS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "indirect_hammer.hip"
.globl _Z11check_error10hipError_t # -- Begin function _Z11check_error10hipError_t
.p2align 4, 0x90
.type _Z11check_error10hipError_t,@function
_Z11check_error10hipError_t: # @_Z11check_error10hipError_t
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB0_2
# %bb.1:
retq
.LBB0_2:
pushq %rax
.cfi_def_cfa_offset 16
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end0:
.size _Z11check_error10hipError_t, .Lfunc_end0-_Z11check_error10hipError_t
.cfi_endproc
# -- End function
.globl _Z29__device_stub__hammer_attemptPiS_S_iii # -- Begin function _Z29__device_stub__hammer_attemptPiS_S_iii
.p2align 4, 0x90
.type _Z29__device_stub__hammer_attemptPiS_S_iii,@function
_Z29__device_stub__hammer_attemptPiS_S_iii: # @_Z29__device_stub__hammer_attemptPiS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14hammer_attemptPiS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z29__device_stub__hammer_attemptPiS_S_iii, .Lfunc_end1-_Z29__device_stub__hammer_attemptPiS_S_iii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %r13d, %r13d
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movq 24(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 32(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $3932160, %edi # imm = 0x3C0000
callq malloc
movq %rax, %r14
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
callq rand
movl %eax, (%r14,%r13,4)
incq %r13
cmpq $983040, %r13 # imm = 0xF0000
jne .LBB2_1
# %bb.2:
leaq 40(%rsp), %rdi
movl $3932160, %esi # imm = 0x3C0000
callq hipMalloc
testl %eax, %eax
jne .LBB2_17
# %bb.3: # %_Z11check_error10hipError_t.exit
movq %rbp, 48(%rsp) # 8-byte Spill
movq 40(%rsp), %rdi
movl $3932160, %edx # imm = 0x3C0000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_17
# %bb.4: # %_Z11check_error10hipError_t.exit41
movl $32, %edi
callq malloc
movq %rax, %r13
movq %rax, %r14
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
callq rand
movslq %eax, %rsi
imulq $715827883, %rsi, %rax # imm = 0x2AAAAAAB
movq %rax, %rcx
shrq $63, %rcx
shrq $44, %rax
addl %ecx, %eax
shll $13, %eax
leal (%rax,%rax,2), %eax
subl %eax, %esi
addl %ebp, %esi
movl %esi, (%r14)
movl $.L.str.1, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
addq $49512, %rbp # imm = 0xC168
addq $4, %r14
cmpq $396096, %rbp # imm = 0x60B40
jne .LBB2_5
# %bb.6:
leaq 32(%rsp), %rdi
movl $32, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB2_17
# %bb.7: # %_Z11check_error10hipError_t.exit43
movq 32(%rsp), %rdi
movl $32, %edx
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_17
# %bb.8: # %_Z11check_error10hipError_t.exit45
movl $786432, %eax # imm = 0xC0000
xorl %edx, %edx
idivl %ebx
movl %eax, %ebp
movslq %eax, %r13
shlq $2, %r13
movq %r13, %rdi
callq malloc
movq %rax, %r14
testl %ebp, %ebp
jle .LBB2_11
# %bb.9: # %.lr.ph.preheader
movl %ebp, %eax
movl $393216, %ecx # imm = 0x60000
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_10: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ecx, (%r14,%rdx,4)
incq %rdx
addl %ebx, %ecx
cmpq %rdx, %rax
jne .LBB2_10
.LBB2_11: # %._crit_edge
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_17
# %bb.12: # %_Z11check_error10hipError_t.exit47
movq 24(%rsp), %rdi
movq %r14, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_17
# %bb.13: # %_Z11check_error10hipError_t.exit49
movl %r15d, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %r12d, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_15
# %bb.14:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movq 48(%rsp), %rax # 8-byte Reload
movl %eax, 20(%rsp)
movl %ebp, 16(%rsp)
movl %ebx, 12(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z14hammer_attemptPiS_S_iii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_15:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_17
# %bb.16: # %_Z11check_error10hipError_t.exit51
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_17:
.cfi_def_cfa_offset 240
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14hammer_attemptPiS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "FAILED WITH ERROR: \"%s\".\n"
.size .L.str, 26
.type _Z14hammer_attemptPiS_S_iii,@object # @_Z14hammer_attemptPiS_S_iii
.section .rodata,"a",@progbits
.globl _Z14hammer_attemptPiS_S_iii
.p2align 3, 0x0
_Z14hammer_attemptPiS_S_iii:
.quad _Z29__device_stub__hammer_attemptPiS_S_iii
.size _Z14hammer_attemptPiS_S_iii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d\n"
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14hammer_attemptPiS_S_iii"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__hammer_attemptPiS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14hammer_attemptPiS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
typedef unsigned long long ul;
typedef unsigned int uint;
int banyakdata = 256;
int dimensigrid = 2;
int dimensiblok = 128;
typedef struct {
char size;
uint* value;
}big;
typedef struct {
short size;
char* value;
}stringnumber;
__host__ __device__ short ukuranbit(big *a);
__host__ __device__ char getbit(big* a, short count);
__host__ __device__ uint getShiftedBlock(big *num, char noblok, char geser);
__host__ __device__ void kali(big *a, big *b, big* res);
__host__ __device__ void modulo(big* a, big* b, big* res, uint* minbuff);
__host__ __device__ void modexp(big* a, big* b, big* c, big* res, uint* minbuff, big* mulbuff);
void enkripsi(big *m, big *k, big *g, big *p, big *y, big *res, big *minbuff, big *mulbuff);
void dekripsi(big *c1, big *c2, big *e, big *p, big *res, big *minbuff, big *mulbuff);
void kernelenk(big *m, big *k, big *g, big *p, big *y, big *res, big *minbuff, big *mulbuff);
void kerneldek(big *c, big *e, big *p, big *res, big *minbuff, big *mulbuff);
void CUDAenk(big *m, big *k, big* g, big* p, big* y, big *res);
void CUDAdek(big *c, big *e, big* p, big *res);
void mainenkripsi(big *m, big *k, big *res, big *g, big *p, big *y);
void maindekripsi(big* c,big* x,big* p,big* res2);
void tambah(big* a, char b, big* res);
void kurang(big* a, big *b, big* res);
void divandmod(big* a, big* &b, big* divres, big* modres, uint* minbuff);
void carikunciy(big *g, big *x, big *p, big *y, uint *minbuff, big *mulbuff);
void init(big *p, big *g, big *x, big*e, big *y, big *m, big *k, big *res, big *res2);
void copybig(big* a, big* res);
void stringtobig(stringnumber* sn, big* res, big* mulbuff, big* ten);
void bigtostring(big* x, stringnumber* sn, big* ten, big* xbuff, big* divbuff, big* modbuff, uint* minbuff);
void printsn(stringnumber* sn);
void teskonversi();
void enkripsi(big *m, big *k, big *g, big *p, big *y, big *res, big *minbuff, big *mulbuff) {
// BLok 1 Cipher
modexp(g,k,p,res,minbuff->value,mulbuff);
// Blok 2 Cipher
modexp(y, k, p, res + 1,minbuff->value,mulbuff);
kali(res + 1, m, mulbuff);
modulo(mulbuff, p, res+1, minbuff->value);
}
void dekripsi(big *c1, big *c2, big *e, big *p, big *res, big *minbuff, big *mulbuff) {
modexp(c1,e,p,res,minbuff->value,mulbuff);
kali(res, c2, mulbuff);
modulo(mulbuff, p, res, minbuff->value);
}
void kernelenk(big *m, big *k, big *g, big *p, big *y, big *res, big *minbuff, big *mulbuff){
for (int i = 0; i < banyakdata; i++)
{
enkripsi(m + i, k + i, g, p, y, res + 2 * i, minbuff+i, mulbuff+i);
}
}
void kerneldek(big *c, big *e, big *p, big *res, big *minbuff, big *mulbuff){
for (int i = 0; i < banyakdata; i++)
{
dekripsi(c + 2*i, c + 2*i+1, e, p, res+i, minbuff+i, mulbuff+i);
}
}
void CUDAenk(big *m, big *k, big* g, big* p, big* y, big *res) {
big *minbuff, *mulbuff;
minbuff = (big*) malloc(banyakdata * sizeof(big));
mulbuff = (big*) malloc(banyakdata * sizeof(big));
for (int i = 0; i < banyakdata; i++) {
minbuff[i].value = (uint*) malloc(sizeof(uint) * p->size * 2);
mulbuff[i].value = (uint*) malloc(sizeof(uint) * p->size * 2);
}
clock_t begin = clock();
kernelenk(m, k, g, p, y, res, minbuff, mulbuff);
clock_t end = clock();
double time_spent = (double)(end - begin) / 1000;
printf("Durasi : %f ms\n", time_spent);
}
void CUDAdek(big *c, big *e, big* p, big *res) {
big *minbuff, *mulbuff;
minbuff = (big*) malloc(banyakdata * sizeof(big));
mulbuff = (big*) malloc(banyakdata * sizeof(big));
for (int i = 0; i < banyakdata; i++) {
minbuff[i].value = (uint*) malloc(sizeof(uint) * p->size * 2);
mulbuff[i].value = (uint*) malloc(sizeof(uint) * p->size * 2);
}
clock_t begin = clock();
kerneldek(c, e, p, res, minbuff, mulbuff);
clock_t end = clock();
double time_spent = (double)(end - begin) / 1000;
printf("Durasi : %f ms\n", time_spent);
}
void mainenkripsi(big *m, big *k, big *res, big *g, big *p, big *y){
printf("Encrypting...\n");
CUDAenk(m, k, g, p, y, res);
for (int i = 0; i < 5; i++)
{
printf("Cipher %d size %d : %u\n",i, res[i].size, res[i].value[0]);
}
printf("Cipher ... : ...\n");
printf("Cipher %d size %d : %u\n",banyakdata*2-2, res[banyakdata*2-2].size, res[banyakdata*2-2].value[0]);
printf("Cipher %d size %d : %u\n",banyakdata*2-1, res[banyakdata*2-2].size, res[banyakdata*2-1].value[0]);
}
void maindekripsi(big* c, big* e,big* p,big* res2){
printf("Decrypting...\n");
CUDAdek(c, e, p, res2);
for (int i = 0; i < 5; i++)
{
printf("Plain %d size %d : %u\n",i, res2[i].size, res2[i].value[0]);
printf("Plain %d size %d : %u\n",i, res2[i].size, res2[i].value[1]);
}
printf("Plain ... : ...\n");
printf("Plain %d size %d : %u\n",banyakdata-1, res2[banyakdata-1].size, res2[banyakdata-1].value[0]);
}
void carikunciy(big *g, big *x, big *p, big *y, uint *minbuff, big *mulbuff){
modexp(g,x,p,y,minbuff,mulbuff);
}
void init(big *p, big *g, big *x, big*e, big *y, big *m, big *k, big *res, big *res2){
// Kunci publik p
p->size = 16;
p->value = (uint*) malloc(p->size * sizeof(uint));
p->value[0] = UINT_MAX;
for (int i = 1; i < p->size; i++)
{
//p->value[i] = 2357;
p->value[i] = rand() % UINT_MAX;
}
// p->value[0] = UINT_MAX-4;
// p->value[0] = 2387;
// p->value[1] = 2357;
// Kunci publik g
g->size = 16;
g->value = (uint*) malloc(g->size * sizeof(uint));
for (int i = 0; i < g->size; i++)
{
// g->value[i] = 2;
g->value[i] = rand() % UINT_MAX;
}
// Kunci privat x
x->size = 16;
x->value = (uint*) malloc(x->size * sizeof(uint));
for (int i = 0; i < x->size; i++)
{
// x->value[i] = 1751;
x->value[i] = rand() % UINT_MAX;
}
// Cari nilai eksponen e = (p-x-1) untuk dekripsi
big *xplus1 = (big*) malloc(sizeof(big));
xplus1->value = (uint*) malloc(p->size * sizeof(uint));
e->value = (uint*) malloc(p->size * sizeof(uint));
tambah(x, 1, xplus1);
kurang(p,xplus1,e);
// printf("e adalah %u\n", e->value[0]);
free(xplus1->value);
free(xplus1);
// Cari nilai kunci publik y = (g^x) mod p
big* mulbuff = (big*) malloc(sizeof(big));
mulbuff->value = (uint*) malloc(sizeof(uint) * p->size * 2);
uint* minbuff = (uint*) malloc(sizeof(uint) * p->size * 2);
y->value = (uint*) malloc(p->size * 2 * sizeof(uint));
carikunciy(g,x,p,y,minbuff,mulbuff);
// printf("y adalah %u\n",y->value[0]);
//========================================================//
// Blok plainteks
for(int i = 0 ; i < banyakdata ; i++){
m[i].size = 16;
m[i].value = (uint*) malloc(m[i].size * sizeof(uint));
for (int j = 0; j < m[i].size; j++)
{
// m[i].value[j] = 1001;
m[i].value[j] = rand() % UINT_MAX;
}
// Nilai k masing-masing blok
k[i].size = 16;
k[i].value = (uint*) malloc(k[i].size * sizeof(uint));
for (int j = 0; j < k[i].size; j++)
{
// k[i].value[j] = 77;
k[i].value[j] = rand() % UINT_MAX;
}
}
// Alokasi memori untuk result
for (int i = 0; i < banyakdata*2; i++)
{
res[i].value = (uint*) malloc(sizeof(uint) * p->size *2);
}
// Alokasi memori untuk result 2
for (int i = 0; i < banyakdata; i++)
{
res2[i].value = (uint*) malloc(sizeof(uint) * p->size * 2);
}
}
int main(){
big *p, *g, *x, *e, *y, *m, *k, *res, *res2;
p = (big*)malloc(sizeof(big));
g = (big*)malloc(sizeof(big));
x = (big*)malloc(sizeof(big));
e = (big*)malloc(sizeof(big));
y = (big*)malloc(sizeof(big));
m = (big*)malloc(banyakdata * sizeof(big));
k = (big*)malloc(banyakdata * sizeof(big));
res = (big*)malloc(banyakdata * 2 * sizeof(big));
res2 = (big*)malloc(banyakdata * sizeof(big));
init(p,g,x,e,y,m,k,res,res2);
mainenkripsi(m,k,res,g,p,y);
printf(" ========================= \n");
maindekripsi(res,e,p,res2);
free(p->value);
free(p);
free(g->value);
free(g);
free(x->value);
free(x);
free(e->value);
free(e);
free(y->value);
free(y);
free(m->value);
free(m);
free(k->value);
free(k);
free(res->value);
free(res);
free(res2->value);
free(res2);
//teskonversi();
return 0;
}
__host__ __device__ short ukuranbit(big *a) {
uint lastval = a->value[a->size-1];
short res = 0;
while (lastval != 0) {
lastval >>= 1;
res++;
}
return res + (a->size - 1) * 32;
}
__host__ __device__ char getbit(big* a, short count) {
return (a->value[count / 32] & ((uint) 1 << (count % 32))) != 0;
}
__host__ __device__ uint getShiftedBlock(big *num, char noblok, char geser) {
uint part1 = (noblok == 0 || geser == 0) ? 0 : (num->value[noblok - 1] >> (32-geser));
uint part2 = (noblok == num->size) ? 0 : (num->value[noblok] << geser);
return part1 | part2;
}
__host__ __device__ void kali(big *a, big *b, big* res) {
if (a->size == 0 || b->size == 0) {
res->size = 0;
return ;
}
char ukurana = a->size;
char ukuranb = b->size;
char ukuranres = ukurana + ukuranb;
res->size = ukuranres;
for (char i = 0; i < ukuranres; i++) {
res->value[i] = 0;
}
for (char i = 0; i < ukurana; i++) {
uint aval = a->value[i];
if (aval==0){
continue;
}
uint lebih = 0;
for (char j = 0, lebih = 0; j < ukuranb; j++) {
uint bval = b->value[j];
ul temp = res->value[i+j] + aval * bval + lebih;
res->value[i+j] = temp % UINT_MAX;
lebih = temp / UINT_MAX;
}
res->value[i+ukuranb] = lebih;
}
if (res->value[res->size - 1] == 0){
res->size--;
}
}
__host__ __device__ void modexp(big* a, big* b, big* c, big* res, uint* minbuff, big* mulbuff){
res->size = 1;
res->value[0] = 1;
short i = ukuranbit(b);
while (i > 0) {
i--;
kali(res,res,mulbuff);
modulo(mulbuff,c,res,minbuff);
if (getbit(b,i)) {
kali(res, a, mulbuff);
modulo(mulbuff, c, res, minbuff);
}
}
}
__host__ __device__ void modulo(big* a, big* b, big* res, uint* minbuff) {
res->size = a->size;
for(char i = 0 ; i < res->size ;i++){
res->value[i] = a->value[i];
}
if (a->size < b->size) {
return ;
}
char i, j, k;
char i2;
uint temp ;
char borrowIn, borrowOut;
char ukurana = a->size;
char ukuranb = b->size;
res->value[res->size] = 0;
res->size++;
i = ukurana - ukuranb + 1;
while (i > 0) {
i--;
i2 = 32;
while (i2 > 0) {
i2--;
for (j = 0, k = i, borrowIn = 0; j <= ukuranb; j++, k++) {
temp = res->value[k] - getShiftedBlock(b, j, i2);
borrowOut = (temp > res->value[k]);
if (borrowIn) {
borrowOut |= (temp == 0);
temp--;
}
minbuff[k] = temp;
borrowIn = borrowOut;
}
for (; k < ukurana && borrowIn; k++) {
borrowIn = (res->value[k] == 0);
minbuff[k] = res->value[k] - 1;
}
if (!borrowIn) {
while (k > i) {
k--;
res->value[k] = minbuff[k];
}
}
}
}
while (res->size > 0 && res->value[res->size - 1] == 0)
res->size--;
}
void divandmod(big* a, big* &b, big* divres, big* modres, uint* minbuff) {
modres->size = a->size;
for(char i = 0 ; i < modres->size ;i++){
modres->value[i] = a->value[i];
}
if (a->size < b->size) {
return ;
}
char i, j, k;
char i2;
uint temp ;
char borrowIn, borrowOut;
char ukurana = a->size;
char ukuranb = b->size;
modres->value[modres->size] = 0;
modres->size++;
divres->size = ukurana - ukuranb + 1;
for (i = 0; i < divres->size; i++)
divres->value[i] = 0;
i = ukurana - ukuranb + 1;
while (i > 0) {
i--;
divres->value[i] = 0;
i2 = 32;
while (i2 > 0) {
i2--;
for (j = 0, k = i, borrowIn = 0; j <= ukuranb; j++, k++) {
temp = modres->value[k] - getShiftedBlock(b, j, i2);
borrowOut = (temp > modres->value[k]);
if (borrowIn) {
borrowOut |= (temp == 0);
temp--;
}
minbuff[k] = temp;
borrowIn = borrowOut;
}
for (; k < ukurana && borrowIn; k++) {
borrowIn = (modres->value[k] == 0);
minbuff[k] = modres->value[k] - 1;
}
if (!borrowIn) {
divres->value[i] |= ((uint) 1 << i2);
while (k > i) {
k--;
modres->value[k] = minbuff[k];
}
}
}
}
if (divres->value[divres->size - 1] == 0)
divres->size--;
while (modres->size > 0 && modres->value[modres->size - 1] == 0)
modres->size--;
}
void tambah(big* a, char b, big* res) {
if (a->size == 0) {
res->size = 1;
res->value[0] = uint(b);
return;
}
char carryIn = 0;
uint temp;
res->size = a->size + 1;
res->value[0] = a->value[0] + (uint)b;
carryIn = (res->value[0] < a->value[0]);
char i = 1;
for (; i < a->size && carryIn; i++) {
temp = a->value[i] + (uint)1;
carryIn = (temp == 0);
res->value[i] = temp;
}
for (; i < a->size; i++)
res->value[i] = a->value[i];
if (carryIn)
res->value[i] = 1;
else
res->size--;
}
void kurang(big* a, big *b, big* res) {
res->size = a->size;
for (int i = 0; i < res->size; i++){
res->value[i] = 0;
}
if (b->size == 0) {
return;
}
char borrowIn, borrowOut;
uint temp;
char i;
for (i = 0, borrowIn = 0; i < b->size; i++) {
temp = a->value[i] - b->value[i];
borrowOut = (temp > a->value[i]);
if (borrowIn) {
borrowOut |= (temp == 0);
temp--;
}
res->value[i] = temp;
borrowIn = borrowOut;
}
for (; i < a->size && borrowIn; i++) {
borrowIn = (a->value[i] == 0);
res->value[i] = a->value[i] - 1;
}
for (; i < a->size; i++)
res->value[i] = a->value[i];
if (res->value[res->size - 1] == 0){
res->size--;
}
}
void copybig(big* a, big* res){
res->size = a->size;
for (int i = 0; i < res->size; i++){
res->value[i] = a->value[i];
}
}
void stringtobig(stringnumber* sn, big* res, big* mulbuff, big* ten){
res->size = 0;
for (int i = sn->size-1; i >= 0; i--){
kali(res, ten, mulbuff);
tambah(mulbuff, sn->value[i], res);
}
}
void bigtostring(big* x, stringnumber* sn, big* ten, big* xbuff, big* divbuff, big* modbuff, uint* minbuff) {
copybig(x,xbuff);
short snlength = 0;
while (xbuff->size != 0 ) {
divandmod(xbuff,ten,divbuff,modbuff,minbuff);
sn->value[snlength] = (char) modbuff->value[0];
snlength++;
copybig(divbuff,xbuff);
}
sn->size = snlength;
}
void printsn(stringnumber* sn){
for (int i = 0; i < sn->size; ++i){
printf("%d", sn->value[sn->size-i-1]);
}
printf("\n");
}
void teskonversi(){
int seed = time(NULL);
srand(seed);
stringnumber *sn = (stringnumber*) malloc(sizeof(stringnumber));
sn->size = 25;
sn->value = (char *) malloc(sn->size);
for (int i = 0; i < sn->size; i++)
{
sn->value[i] = rand() % 10;
}
big* konversi = (big*) malloc(sizeof(big));
big* mulbuff = (big*) malloc(sizeof(big));
big* ten = (big*) malloc(sizeof(big));
konversi->value = (uint*) malloc(sizeof(10));
mulbuff->value = (uint*) malloc(sizeof(10));
ten->value = (uint*) malloc(sizeof(1));
ten->size = 1;
ten->value[0] = 10;
printf("Stringnumber awal : ");
printsn(sn);
stringtobig(sn, konversi, mulbuff, ten);
printf("konversi size %d\n", konversi->size);
printf("konversi value 0 %u\n", konversi->value[0]);
printf("konversi value 0 %u\n", konversi->value[1]);
stringnumber *sn2 = (stringnumber*) malloc(sizeof(stringnumber));
big* xbuff = (big*) malloc(sizeof(big));
big* divbuff = (big*) malloc(sizeof(big));
big* modbuff = (big*) malloc(sizeof(big));
sn2->value = (char *) malloc(100);
xbuff->value = (uint *) malloc(sizeof(uint) * 10);
divbuff->value = (uint *) malloc(sizeof(uint) * 10);
modbuff->value = (uint *) malloc(sizeof(uint) * 10);
uint* minbuff = (uint*) malloc(sizeof(uint) * 10);
bigtostring(konversi,sn2,ten,xbuff,divbuff,modbuff,minbuff);
printf("Stringnumber akhir : ");
printsn(sn2);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
typedef unsigned long long ul;
typedef unsigned int uint;
int banyakdata = 256;
int dimensigrid = 2;
int dimensiblok = 128;
typedef struct {
char size;
uint* value;
}big;
typedef struct {
short size;
char* value;
}stringnumber;
__host__ __device__ short ukuranbit(big *a);
__host__ __device__ char getbit(big* a, short count);
__host__ __device__ uint getShiftedBlock(big *num, char noblok, char geser);
__host__ __device__ void kali(big *a, big *b, big* res);
__host__ __device__ void modulo(big* a, big* b, big* res, uint* minbuff);
__host__ __device__ void modexp(big* a, big* b, big* c, big* res, uint* minbuff, big* mulbuff);
void enkripsi(big *m, big *k, big *g, big *p, big *y, big *res, big *minbuff, big *mulbuff);
void dekripsi(big *c1, big *c2, big *e, big *p, big *res, big *minbuff, big *mulbuff);
void kernelenk(big *m, big *k, big *g, big *p, big *y, big *res, big *minbuff, big *mulbuff);
void kerneldek(big *c, big *e, big *p, big *res, big *minbuff, big *mulbuff);
void CUDAenk(big *m, big *k, big* g, big* p, big* y, big *res);
void CUDAdek(big *c, big *e, big* p, big *res);
void mainenkripsi(big *m, big *k, big *res, big *g, big *p, big *y);
void maindekripsi(big* c,big* x,big* p,big* res2);
void tambah(big* a, char b, big* res);
void kurang(big* a, big *b, big* res);
void divandmod(big* a, big* &b, big* divres, big* modres, uint* minbuff);
void carikunciy(big *g, big *x, big *p, big *y, uint *minbuff, big *mulbuff);
void init(big *p, big *g, big *x, big*e, big *y, big *m, big *k, big *res, big *res2);
void copybig(big* a, big* res);
void stringtobig(stringnumber* sn, big* res, big* mulbuff, big* ten);
void bigtostring(big* x, stringnumber* sn, big* ten, big* xbuff, big* divbuff, big* modbuff, uint* minbuff);
void printsn(stringnumber* sn);
void teskonversi();
void enkripsi(big *m, big *k, big *g, big *p, big *y, big *res, big *minbuff, big *mulbuff) {
// BLok 1 Cipher
modexp(g,k,p,res,minbuff->value,mulbuff);
// Blok 2 Cipher
modexp(y, k, p, res + 1,minbuff->value,mulbuff);
kali(res + 1, m, mulbuff);
modulo(mulbuff, p, res+1, minbuff->value);
}
void dekripsi(big *c1, big *c2, big *e, big *p, big *res, big *minbuff, big *mulbuff) {
modexp(c1,e,p,res,minbuff->value,mulbuff);
kali(res, c2, mulbuff);
modulo(mulbuff, p, res, minbuff->value);
}
void kernelenk(big *m, big *k, big *g, big *p, big *y, big *res, big *minbuff, big *mulbuff){
for (int i = 0; i < banyakdata; i++)
{
enkripsi(m + i, k + i, g, p, y, res + 2 * i, minbuff+i, mulbuff+i);
}
}
void kerneldek(big *c, big *e, big *p, big *res, big *minbuff, big *mulbuff){
for (int i = 0; i < banyakdata; i++)
{
dekripsi(c + 2*i, c + 2*i+1, e, p, res+i, minbuff+i, mulbuff+i);
}
}
void CUDAenk(big *m, big *k, big* g, big* p, big* y, big *res) {
big *minbuff, *mulbuff;
minbuff = (big*) malloc(banyakdata * sizeof(big));
mulbuff = (big*) malloc(banyakdata * sizeof(big));
for (int i = 0; i < banyakdata; i++) {
minbuff[i].value = (uint*) malloc(sizeof(uint) * p->size * 2);
mulbuff[i].value = (uint*) malloc(sizeof(uint) * p->size * 2);
}
clock_t begin = clock();
kernelenk(m, k, g, p, y, res, minbuff, mulbuff);
clock_t end = clock();
double time_spent = (double)(end - begin) / 1000;
printf("Durasi : %f ms\n", time_spent);
}
void CUDAdek(big *c, big *e, big* p, big *res) {
big *minbuff, *mulbuff;
minbuff = (big*) malloc(banyakdata * sizeof(big));
mulbuff = (big*) malloc(banyakdata * sizeof(big));
for (int i = 0; i < banyakdata; i++) {
minbuff[i].value = (uint*) malloc(sizeof(uint) * p->size * 2);
mulbuff[i].value = (uint*) malloc(sizeof(uint) * p->size * 2);
}
clock_t begin = clock();
kerneldek(c, e, p, res, minbuff, mulbuff);
clock_t end = clock();
double time_spent = (double)(end - begin) / 1000;
printf("Durasi : %f ms\n", time_spent);
}
void mainenkripsi(big *m, big *k, big *res, big *g, big *p, big *y){
printf("Encrypting...\n");
CUDAenk(m, k, g, p, y, res);
for (int i = 0; i < 5; i++)
{
printf("Cipher %d size %d : %u\n",i, res[i].size, res[i].value[0]);
}
printf("Cipher ... : ...\n");
printf("Cipher %d size %d : %u\n",banyakdata*2-2, res[banyakdata*2-2].size, res[banyakdata*2-2].value[0]);
printf("Cipher %d size %d : %u\n",banyakdata*2-1, res[banyakdata*2-2].size, res[banyakdata*2-1].value[0]);
}
void maindekripsi(big* c, big* e,big* p,big* res2){
printf("Decrypting...\n");
CUDAdek(c, e, p, res2);
for (int i = 0; i < 5; i++)
{
printf("Plain %d size %d : %u\n",i, res2[i].size, res2[i].value[0]);
printf("Plain %d size %d : %u\n",i, res2[i].size, res2[i].value[1]);
}
printf("Plain ... : ...\n");
printf("Plain %d size %d : %u\n",banyakdata-1, res2[banyakdata-1].size, res2[banyakdata-1].value[0]);
}
void carikunciy(big *g, big *x, big *p, big *y, uint *minbuff, big *mulbuff){
modexp(g,x,p,y,minbuff,mulbuff);
}
void init(big *p, big *g, big *x, big*e, big *y, big *m, big *k, big *res, big *res2){
// Kunci publik p
p->size = 16;
p->value = (uint*) malloc(p->size * sizeof(uint));
p->value[0] = UINT_MAX;
for (int i = 1; i < p->size; i++)
{
//p->value[i] = 2357;
p->value[i] = rand() % UINT_MAX;
}
// p->value[0] = UINT_MAX-4;
// p->value[0] = 2387;
// p->value[1] = 2357;
// Kunci publik g
g->size = 16;
g->value = (uint*) malloc(g->size * sizeof(uint));
for (int i = 0; i < g->size; i++)
{
// g->value[i] = 2;
g->value[i] = rand() % UINT_MAX;
}
// Kunci privat x
x->size = 16;
x->value = (uint*) malloc(x->size * sizeof(uint));
for (int i = 0; i < x->size; i++)
{
// x->value[i] = 1751;
x->value[i] = rand() % UINT_MAX;
}
// Cari nilai eksponen e = (p-x-1) untuk dekripsi
big *xplus1 = (big*) malloc(sizeof(big));
xplus1->value = (uint*) malloc(p->size * sizeof(uint));
e->value = (uint*) malloc(p->size * sizeof(uint));
tambah(x, 1, xplus1);
kurang(p,xplus1,e);
// printf("e adalah %u\n", e->value[0]);
free(xplus1->value);
free(xplus1);
// Cari nilai kunci publik y = (g^x) mod p
big* mulbuff = (big*) malloc(sizeof(big));
mulbuff->value = (uint*) malloc(sizeof(uint) * p->size * 2);
uint* minbuff = (uint*) malloc(sizeof(uint) * p->size * 2);
y->value = (uint*) malloc(p->size * 2 * sizeof(uint));
carikunciy(g,x,p,y,minbuff,mulbuff);
// printf("y adalah %u\n",y->value[0]);
//========================================================//
// Blok plainteks
for(int i = 0 ; i < banyakdata ; i++){
m[i].size = 16;
m[i].value = (uint*) malloc(m[i].size * sizeof(uint));
for (int j = 0; j < m[i].size; j++)
{
// m[i].value[j] = 1001;
m[i].value[j] = rand() % UINT_MAX;
}
// Nilai k masing-masing blok
k[i].size = 16;
k[i].value = (uint*) malloc(k[i].size * sizeof(uint));
for (int j = 0; j < k[i].size; j++)
{
// k[i].value[j] = 77;
k[i].value[j] = rand() % UINT_MAX;
}
}
// Alokasi memori untuk result
for (int i = 0; i < banyakdata*2; i++)
{
res[i].value = (uint*) malloc(sizeof(uint) * p->size *2);
}
// Alokasi memori untuk result 2
for (int i = 0; i < banyakdata; i++)
{
res2[i].value = (uint*) malloc(sizeof(uint) * p->size * 2);
}
}
int main(){
big *p, *g, *x, *e, *y, *m, *k, *res, *res2;
p = (big*)malloc(sizeof(big));
g = (big*)malloc(sizeof(big));
x = (big*)malloc(sizeof(big));
e = (big*)malloc(sizeof(big));
y = (big*)malloc(sizeof(big));
m = (big*)malloc(banyakdata * sizeof(big));
k = (big*)malloc(banyakdata * sizeof(big));
res = (big*)malloc(banyakdata * 2 * sizeof(big));
res2 = (big*)malloc(banyakdata * sizeof(big));
init(p,g,x,e,y,m,k,res,res2);
mainenkripsi(m,k,res,g,p,y);
printf(" ========================= \n");
maindekripsi(res,e,p,res2);
free(p->value);
free(p);
free(g->value);
free(g);
free(x->value);
free(x);
free(e->value);
free(e);
free(y->value);
free(y);
free(m->value);
free(m);
free(k->value);
free(k);
free(res->value);
free(res);
free(res2->value);
free(res2);
//teskonversi();
return 0;
}
__host__ __device__ short ukuranbit(big *a) {
uint lastval = a->value[a->size-1];
short res = 0;
while (lastval != 0) {
lastval >>= 1;
res++;
}
return res + (a->size - 1) * 32;
}
__host__ __device__ char getbit(big* a, short count) {
return (a->value[count / 32] & ((uint) 1 << (count % 32))) != 0;
}
__host__ __device__ uint getShiftedBlock(big *num, char noblok, char geser) {
uint part1 = (noblok == 0 || geser == 0) ? 0 : (num->value[noblok - 1] >> (32-geser));
uint part2 = (noblok == num->size) ? 0 : (num->value[noblok] << geser);
return part1 | part2;
}
__host__ __device__ void kali(big *a, big *b, big* res) {
if (a->size == 0 || b->size == 0) {
res->size = 0;
return ;
}
char ukurana = a->size;
char ukuranb = b->size;
char ukuranres = ukurana + ukuranb;
res->size = ukuranres;
for (char i = 0; i < ukuranres; i++) {
res->value[i] = 0;
}
for (char i = 0; i < ukurana; i++) {
uint aval = a->value[i];
if (aval==0){
continue;
}
uint lebih = 0;
for (char j = 0, lebih = 0; j < ukuranb; j++) {
uint bval = b->value[j];
ul temp = res->value[i+j] + aval * bval + lebih;
res->value[i+j] = temp % UINT_MAX;
lebih = temp / UINT_MAX;
}
res->value[i+ukuranb] = lebih;
}
if (res->value[res->size - 1] == 0){
res->size--;
}
}
__host__ __device__ void modexp(big* a, big* b, big* c, big* res, uint* minbuff, big* mulbuff){
res->size = 1;
res->value[0] = 1;
short i = ukuranbit(b);
while (i > 0) {
i--;
kali(res,res,mulbuff);
modulo(mulbuff,c,res,minbuff);
if (getbit(b,i)) {
kali(res, a, mulbuff);
modulo(mulbuff, c, res, minbuff);
}
}
}
__host__ __device__ void modulo(big* a, big* b, big* res, uint* minbuff) {
res->size = a->size;
for(char i = 0 ; i < res->size ;i++){
res->value[i] = a->value[i];
}
if (a->size < b->size) {
return ;
}
char i, j, k;
char i2;
uint temp ;
char borrowIn, borrowOut;
char ukurana = a->size;
char ukuranb = b->size;
res->value[res->size] = 0;
res->size++;
i = ukurana - ukuranb + 1;
while (i > 0) {
i--;
i2 = 32;
while (i2 > 0) {
i2--;
for (j = 0, k = i, borrowIn = 0; j <= ukuranb; j++, k++) {
temp = res->value[k] - getShiftedBlock(b, j, i2);
borrowOut = (temp > res->value[k]);
if (borrowIn) {
borrowOut |= (temp == 0);
temp--;
}
minbuff[k] = temp;
borrowIn = borrowOut;
}
for (; k < ukurana && borrowIn; k++) {
borrowIn = (res->value[k] == 0);
minbuff[k] = res->value[k] - 1;
}
if (!borrowIn) {
while (k > i) {
k--;
res->value[k] = minbuff[k];
}
}
}
}
while (res->size > 0 && res->value[res->size - 1] == 0)
res->size--;
}
void divandmod(big* a, big* &b, big* divres, big* modres, uint* minbuff) {
modres->size = a->size;
for(char i = 0 ; i < modres->size ;i++){
modres->value[i] = a->value[i];
}
if (a->size < b->size) {
return ;
}
char i, j, k;
char i2;
uint temp ;
char borrowIn, borrowOut;
char ukurana = a->size;
char ukuranb = b->size;
modres->value[modres->size] = 0;
modres->size++;
divres->size = ukurana - ukuranb + 1;
for (i = 0; i < divres->size; i++)
divres->value[i] = 0;
i = ukurana - ukuranb + 1;
while (i > 0) {
i--;
divres->value[i] = 0;
i2 = 32;
while (i2 > 0) {
i2--;
for (j = 0, k = i, borrowIn = 0; j <= ukuranb; j++, k++) {
temp = modres->value[k] - getShiftedBlock(b, j, i2);
borrowOut = (temp > modres->value[k]);
if (borrowIn) {
borrowOut |= (temp == 0);
temp--;
}
minbuff[k] = temp;
borrowIn = borrowOut;
}
for (; k < ukurana && borrowIn; k++) {
borrowIn = (modres->value[k] == 0);
minbuff[k] = modres->value[k] - 1;
}
if (!borrowIn) {
divres->value[i] |= ((uint) 1 << i2);
while (k > i) {
k--;
modres->value[k] = minbuff[k];
}
}
}
}
if (divres->value[divres->size - 1] == 0)
divres->size--;
while (modres->size > 0 && modres->value[modres->size - 1] == 0)
modres->size--;
}
void tambah(big* a, char b, big* res) {
if (a->size == 0) {
res->size = 1;
res->value[0] = uint(b);
return;
}
char carryIn = 0;
uint temp;
res->size = a->size + 1;
res->value[0] = a->value[0] + (uint)b;
carryIn = (res->value[0] < a->value[0]);
char i = 1;
for (; i < a->size && carryIn; i++) {
temp = a->value[i] + (uint)1;
carryIn = (temp == 0);
res->value[i] = temp;
}
for (; i < a->size; i++)
res->value[i] = a->value[i];
if (carryIn)
res->value[i] = 1;
else
res->size--;
}
void kurang(big* a, big *b, big* res) {
res->size = a->size;
for (int i = 0; i < res->size; i++){
res->value[i] = 0;
}
if (b->size == 0) {
return;
}
char borrowIn, borrowOut;
uint temp;
char i;
for (i = 0, borrowIn = 0; i < b->size; i++) {
temp = a->value[i] - b->value[i];
borrowOut = (temp > a->value[i]);
if (borrowIn) {
borrowOut |= (temp == 0);
temp--;
}
res->value[i] = temp;
borrowIn = borrowOut;
}
for (; i < a->size && borrowIn; i++) {
borrowIn = (a->value[i] == 0);
res->value[i] = a->value[i] - 1;
}
for (; i < a->size; i++)
res->value[i] = a->value[i];
if (res->value[res->size - 1] == 0){
res->size--;
}
}
void copybig(big* a, big* res){
res->size = a->size;
for (int i = 0; i < res->size; i++){
res->value[i] = a->value[i];
}
}
void stringtobig(stringnumber* sn, big* res, big* mulbuff, big* ten){
res->size = 0;
for (int i = sn->size-1; i >= 0; i--){
kali(res, ten, mulbuff);
tambah(mulbuff, sn->value[i], res);
}
}
void bigtostring(big* x, stringnumber* sn, big* ten, big* xbuff, big* divbuff, big* modbuff, uint* minbuff) {
copybig(x,xbuff);
short snlength = 0;
while (xbuff->size != 0 ) {
divandmod(xbuff,ten,divbuff,modbuff,minbuff);
sn->value[snlength] = (char) modbuff->value[0];
snlength++;
copybig(divbuff,xbuff);
}
sn->size = snlength;
}
void printsn(stringnumber* sn){
for (int i = 0; i < sn->size; ++i){
printf("%d", sn->value[sn->size-i-1]);
}
printf("\n");
}
void teskonversi(){
int seed = time(NULL);
srand(seed);
stringnumber *sn = (stringnumber*) malloc(sizeof(stringnumber));
sn->size = 25;
sn->value = (char *) malloc(sn->size);
for (int i = 0; i < sn->size; i++)
{
sn->value[i] = rand() % 10;
}
big* konversi = (big*) malloc(sizeof(big));
big* mulbuff = (big*) malloc(sizeof(big));
big* ten = (big*) malloc(sizeof(big));
konversi->value = (uint*) malloc(sizeof(10));
mulbuff->value = (uint*) malloc(sizeof(10));
ten->value = (uint*) malloc(sizeof(1));
ten->size = 1;
ten->value[0] = 10;
printf("Stringnumber awal : ");
printsn(sn);
stringtobig(sn, konversi, mulbuff, ten);
printf("konversi size %d\n", konversi->size);
printf("konversi value 0 %u\n", konversi->value[0]);
printf("konversi value 0 %u\n", konversi->value[1]);
stringnumber *sn2 = (stringnumber*) malloc(sizeof(stringnumber));
big* xbuff = (big*) malloc(sizeof(big));
big* divbuff = (big*) malloc(sizeof(big));
big* modbuff = (big*) malloc(sizeof(big));
sn2->value = (char *) malloc(100);
xbuff->value = (uint *) malloc(sizeof(uint) * 10);
divbuff->value = (uint *) malloc(sizeof(uint) * 10);
modbuff->value = (uint *) malloc(sizeof(uint) * 10);
uint* minbuff = (uint*) malloc(sizeof(uint) * 10);
bigtostring(konversi,sn2,ten,xbuff,divbuff,modbuff,minbuff);
printf("Stringnumber akhir : ");
printsn(sn2);
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
typedef unsigned long long ul;
typedef unsigned int uint;
int banyakdata = 256;
int dimensigrid = 2;
int dimensiblok = 128;
typedef struct {
char size;
uint* value;
}big;
typedef struct {
short size;
char* value;
}stringnumber;
__host__ __device__ short ukuranbit(big *a);
__host__ __device__ char getbit(big* a, short count);
__host__ __device__ uint getShiftedBlock(big *num, char noblok, char geser);
__host__ __device__ void kali(big *a, big *b, big* res);
__host__ __device__ void modulo(big* a, big* b, big* res, uint* minbuff);
__host__ __device__ void modexp(big* a, big* b, big* c, big* res, uint* minbuff, big* mulbuff);
void enkripsi(big *m, big *k, big *g, big *p, big *y, big *res, big *minbuff, big *mulbuff);
void dekripsi(big *c1, big *c2, big *e, big *p, big *res, big *minbuff, big *mulbuff);
void kernelenk(big *m, big *k, big *g, big *p, big *y, big *res, big *minbuff, big *mulbuff);
void kerneldek(big *c, big *e, big *p, big *res, big *minbuff, big *mulbuff);
void CUDAenk(big *m, big *k, big* g, big* p, big* y, big *res);
void CUDAdek(big *c, big *e, big* p, big *res);
void mainenkripsi(big *m, big *k, big *res, big *g, big *p, big *y);
void maindekripsi(big* c,big* x,big* p,big* res2);
void tambah(big* a, char b, big* res);
void kurang(big* a, big *b, big* res);
void divandmod(big* a, big* &b, big* divres, big* modres, uint* minbuff);
void carikunciy(big *g, big *x, big *p, big *y, uint *minbuff, big *mulbuff);
void init(big *p, big *g, big *x, big*e, big *y, big *m, big *k, big *res, big *res2);
void copybig(big* a, big* res);
void stringtobig(stringnumber* sn, big* res, big* mulbuff, big* ten);
void bigtostring(big* x, stringnumber* sn, big* ten, big* xbuff, big* divbuff, big* modbuff, uint* minbuff);
void printsn(stringnumber* sn);
void teskonversi();
void enkripsi(big *m, big *k, big *g, big *p, big *y, big *res, big *minbuff, big *mulbuff) {
// BLok 1 Cipher
modexp(g,k,p,res,minbuff->value,mulbuff);
// Blok 2 Cipher
modexp(y, k, p, res + 1,minbuff->value,mulbuff);
kali(res + 1, m, mulbuff);
modulo(mulbuff, p, res+1, minbuff->value);
}
void dekripsi(big *c1, big *c2, big *e, big *p, big *res, big *minbuff, big *mulbuff) {
modexp(c1,e,p,res,minbuff->value,mulbuff);
kali(res, c2, mulbuff);
modulo(mulbuff, p, res, minbuff->value);
}
void kernelenk(big *m, big *k, big *g, big *p, big *y, big *res, big *minbuff, big *mulbuff){
for (int i = 0; i < banyakdata; i++)
{
enkripsi(m + i, k + i, g, p, y, res + 2 * i, minbuff+i, mulbuff+i);
}
}
void kerneldek(big *c, big *e, big *p, big *res, big *minbuff, big *mulbuff){
for (int i = 0; i < banyakdata; i++)
{
dekripsi(c + 2*i, c + 2*i+1, e, p, res+i, minbuff+i, mulbuff+i);
}
}
void CUDAenk(big *m, big *k, big* g, big* p, big* y, big *res) {
big *minbuff, *mulbuff;
minbuff = (big*) malloc(banyakdata * sizeof(big));
mulbuff = (big*) malloc(banyakdata * sizeof(big));
for (int i = 0; i < banyakdata; i++) {
minbuff[i].value = (uint*) malloc(sizeof(uint) * p->size * 2);
mulbuff[i].value = (uint*) malloc(sizeof(uint) * p->size * 2);
}
clock_t begin = clock();
kernelenk(m, k, g, p, y, res, minbuff, mulbuff);
clock_t end = clock();
double time_spent = (double)(end - begin) / 1000;
printf("Durasi : %f ms\n", time_spent);
}
void CUDAdek(big *c, big *e, big* p, big *res) {
big *minbuff, *mulbuff;
minbuff = (big*) malloc(banyakdata * sizeof(big));
mulbuff = (big*) malloc(banyakdata * sizeof(big));
for (int i = 0; i < banyakdata; i++) {
minbuff[i].value = (uint*) malloc(sizeof(uint) * p->size * 2);
mulbuff[i].value = (uint*) malloc(sizeof(uint) * p->size * 2);
}
clock_t begin = clock();
kerneldek(c, e, p, res, minbuff, mulbuff);
clock_t end = clock();
double time_spent = (double)(end - begin) / 1000;
printf("Durasi : %f ms\n", time_spent);
}
void mainenkripsi(big *m, big *k, big *res, big *g, big *p, big *y){
printf("Encrypting...\n");
CUDAenk(m, k, g, p, y, res);
for (int i = 0; i < 5; i++)
{
printf("Cipher %d size %d : %u\n",i, res[i].size, res[i].value[0]);
}
printf("Cipher ... : ...\n");
printf("Cipher %d size %d : %u\n",banyakdata*2-2, res[banyakdata*2-2].size, res[banyakdata*2-2].value[0]);
printf("Cipher %d size %d : %u\n",banyakdata*2-1, res[banyakdata*2-2].size, res[banyakdata*2-1].value[0]);
}
void maindekripsi(big* c, big* e,big* p,big* res2){
printf("Decrypting...\n");
CUDAdek(c, e, p, res2);
for (int i = 0; i < 5; i++)
{
printf("Plain %d size %d : %u\n",i, res2[i].size, res2[i].value[0]);
printf("Plain %d size %d : %u\n",i, res2[i].size, res2[i].value[1]);
}
printf("Plain ... : ...\n");
printf("Plain %d size %d : %u\n",banyakdata-1, res2[banyakdata-1].size, res2[banyakdata-1].value[0]);
}
void carikunciy(big *g, big *x, big *p, big *y, uint *minbuff, big *mulbuff){
modexp(g,x,p,y,minbuff,mulbuff);
}
void init(big *p, big *g, big *x, big*e, big *y, big *m, big *k, big *res, big *res2){
// Kunci publik p
p->size = 16;
p->value = (uint*) malloc(p->size * sizeof(uint));
p->value[0] = UINT_MAX;
for (int i = 1; i < p->size; i++)
{
//p->value[i] = 2357;
p->value[i] = rand() % UINT_MAX;
}
// p->value[0] = UINT_MAX-4;
// p->value[0] = 2387;
// p->value[1] = 2357;
// Kunci publik g
g->size = 16;
g->value = (uint*) malloc(g->size * sizeof(uint));
for (int i = 0; i < g->size; i++)
{
// g->value[i] = 2;
g->value[i] = rand() % UINT_MAX;
}
// Kunci privat x
x->size = 16;
x->value = (uint*) malloc(x->size * sizeof(uint));
for (int i = 0; i < x->size; i++)
{
// x->value[i] = 1751;
x->value[i] = rand() % UINT_MAX;
}
// Cari nilai eksponen e = (p-x-1) untuk dekripsi
big *xplus1 = (big*) malloc(sizeof(big));
xplus1->value = (uint*) malloc(p->size * sizeof(uint));
e->value = (uint*) malloc(p->size * sizeof(uint));
tambah(x, 1, xplus1);
kurang(p,xplus1,e);
// printf("e adalah %u\n", e->value[0]);
free(xplus1->value);
free(xplus1);
// Cari nilai kunci publik y = (g^x) mod p
big* mulbuff = (big*) malloc(sizeof(big));
mulbuff->value = (uint*) malloc(sizeof(uint) * p->size * 2);
uint* minbuff = (uint*) malloc(sizeof(uint) * p->size * 2);
y->value = (uint*) malloc(p->size * 2 * sizeof(uint));
carikunciy(g,x,p,y,minbuff,mulbuff);
// printf("y adalah %u\n",y->value[0]);
//========================================================//
// Blok plainteks
for(int i = 0 ; i < banyakdata ; i++){
m[i].size = 16;
m[i].value = (uint*) malloc(m[i].size * sizeof(uint));
for (int j = 0; j < m[i].size; j++)
{
// m[i].value[j] = 1001;
m[i].value[j] = rand() % UINT_MAX;
}
// Nilai k masing-masing blok
k[i].size = 16;
k[i].value = (uint*) malloc(k[i].size * sizeof(uint));
for (int j = 0; j < k[i].size; j++)
{
// k[i].value[j] = 77;
k[i].value[j] = rand() % UINT_MAX;
}
}
// Alokasi memori untuk result
for (int i = 0; i < banyakdata*2; i++)
{
res[i].value = (uint*) malloc(sizeof(uint) * p->size *2);
}
// Alokasi memori untuk result 2
for (int i = 0; i < banyakdata; i++)
{
res2[i].value = (uint*) malloc(sizeof(uint) * p->size * 2);
}
}
int main(){
big *p, *g, *x, *e, *y, *m, *k, *res, *res2;
p = (big*)malloc(sizeof(big));
g = (big*)malloc(sizeof(big));
x = (big*)malloc(sizeof(big));
e = (big*)malloc(sizeof(big));
y = (big*)malloc(sizeof(big));
m = (big*)malloc(banyakdata * sizeof(big));
k = (big*)malloc(banyakdata * sizeof(big));
res = (big*)malloc(banyakdata * 2 * sizeof(big));
res2 = (big*)malloc(banyakdata * sizeof(big));
init(p,g,x,e,y,m,k,res,res2);
mainenkripsi(m,k,res,g,p,y);
printf(" ========================= \n");
maindekripsi(res,e,p,res2);
free(p->value);
free(p);
free(g->value);
free(g);
free(x->value);
free(x);
free(e->value);
free(e);
free(y->value);
free(y);
free(m->value);
free(m);
free(k->value);
free(k);
free(res->value);
free(res);
free(res2->value);
free(res2);
//teskonversi();
return 0;
}
__host__ __device__ short ukuranbit(big *a) {
uint lastval = a->value[a->size-1];
short res = 0;
while (lastval != 0) {
lastval >>= 1;
res++;
}
return res + (a->size - 1) * 32;
}
__host__ __device__ char getbit(big* a, short count) {
return (a->value[count / 32] & ((uint) 1 << (count % 32))) != 0;
}
__host__ __device__ uint getShiftedBlock(big *num, char noblok, char geser) {
uint part1 = (noblok == 0 || geser == 0) ? 0 : (num->value[noblok - 1] >> (32-geser));
uint part2 = (noblok == num->size) ? 0 : (num->value[noblok] << geser);
return part1 | part2;
}
__host__ __device__ void kali(big *a, big *b, big* res) {
if (a->size == 0 || b->size == 0) {
res->size = 0;
return ;
}
char ukurana = a->size;
char ukuranb = b->size;
char ukuranres = ukurana + ukuranb;
res->size = ukuranres;
for (char i = 0; i < ukuranres; i++) {
res->value[i] = 0;
}
for (char i = 0; i < ukurana; i++) {
uint aval = a->value[i];
if (aval==0){
continue;
}
uint lebih = 0;
for (char j = 0, lebih = 0; j < ukuranb; j++) {
uint bval = b->value[j];
ul temp = res->value[i+j] + aval * bval + lebih;
res->value[i+j] = temp % UINT_MAX;
lebih = temp / UINT_MAX;
}
res->value[i+ukuranb] = lebih;
}
if (res->value[res->size - 1] == 0){
res->size--;
}
}
__host__ __device__ void modexp(big* a, big* b, big* c, big* res, uint* minbuff, big* mulbuff){
res->size = 1;
res->value[0] = 1;
short i = ukuranbit(b);
while (i > 0) {
i--;
kali(res,res,mulbuff);
modulo(mulbuff,c,res,minbuff);
if (getbit(b,i)) {
kali(res, a, mulbuff);
modulo(mulbuff, c, res, minbuff);
}
}
}
__host__ __device__ void modulo(big* a, big* b, big* res, uint* minbuff) {
res->size = a->size;
for(char i = 0 ; i < res->size ;i++){
res->value[i] = a->value[i];
}
if (a->size < b->size) {
return ;
}
char i, j, k;
char i2;
uint temp ;
char borrowIn, borrowOut;
char ukurana = a->size;
char ukuranb = b->size;
res->value[res->size] = 0;
res->size++;
i = ukurana - ukuranb + 1;
while (i > 0) {
i--;
i2 = 32;
while (i2 > 0) {
i2--;
for (j = 0, k = i, borrowIn = 0; j <= ukuranb; j++, k++) {
temp = res->value[k] - getShiftedBlock(b, j, i2);
borrowOut = (temp > res->value[k]);
if (borrowIn) {
borrowOut |= (temp == 0);
temp--;
}
minbuff[k] = temp;
borrowIn = borrowOut;
}
for (; k < ukurana && borrowIn; k++) {
borrowIn = (res->value[k] == 0);
minbuff[k] = res->value[k] - 1;
}
if (!borrowIn) {
while (k > i) {
k--;
res->value[k] = minbuff[k];
}
}
}
}
while (res->size > 0 && res->value[res->size - 1] == 0)
res->size--;
}
void divandmod(big* a, big* &b, big* divres, big* modres, uint* minbuff) {
modres->size = a->size;
for(char i = 0 ; i < modres->size ;i++){
modres->value[i] = a->value[i];
}
if (a->size < b->size) {
return ;
}
char i, j, k;
char i2;
uint temp ;
char borrowIn, borrowOut;
char ukurana = a->size;
char ukuranb = b->size;
modres->value[modres->size] = 0;
modres->size++;
divres->size = ukurana - ukuranb + 1;
for (i = 0; i < divres->size; i++)
divres->value[i] = 0;
i = ukurana - ukuranb + 1;
while (i > 0) {
i--;
divres->value[i] = 0;
i2 = 32;
while (i2 > 0) {
i2--;
for (j = 0, k = i, borrowIn = 0; j <= ukuranb; j++, k++) {
temp = modres->value[k] - getShiftedBlock(b, j, i2);
borrowOut = (temp > modres->value[k]);
if (borrowIn) {
borrowOut |= (temp == 0);
temp--;
}
minbuff[k] = temp;
borrowIn = borrowOut;
}
for (; k < ukurana && borrowIn; k++) {
borrowIn = (modres->value[k] == 0);
minbuff[k] = modres->value[k] - 1;
}
if (!borrowIn) {
divres->value[i] |= ((uint) 1 << i2);
while (k > i) {
k--;
modres->value[k] = minbuff[k];
}
}
}
}
if (divres->value[divres->size - 1] == 0)
divres->size--;
while (modres->size > 0 && modres->value[modres->size - 1] == 0)
modres->size--;
}
void tambah(big* a, char b, big* res) {
if (a->size == 0) {
res->size = 1;
res->value[0] = uint(b);
return;
}
char carryIn = 0;
uint temp;
res->size = a->size + 1;
res->value[0] = a->value[0] + (uint)b;
carryIn = (res->value[0] < a->value[0]);
char i = 1;
for (; i < a->size && carryIn; i++) {
temp = a->value[i] + (uint)1;
carryIn = (temp == 0);
res->value[i] = temp;
}
for (; i < a->size; i++)
res->value[i] = a->value[i];
if (carryIn)
res->value[i] = 1;
else
res->size--;
}
void kurang(big* a, big *b, big* res) {
res->size = a->size;
for (int i = 0; i < res->size; i++){
res->value[i] = 0;
}
if (b->size == 0) {
return;
}
char borrowIn, borrowOut;
uint temp;
char i;
for (i = 0, borrowIn = 0; i < b->size; i++) {
temp = a->value[i] - b->value[i];
borrowOut = (temp > a->value[i]);
if (borrowIn) {
borrowOut |= (temp == 0);
temp--;
}
res->value[i] = temp;
borrowIn = borrowOut;
}
for (; i < a->size && borrowIn; i++) {
borrowIn = (a->value[i] == 0);
res->value[i] = a->value[i] - 1;
}
for (; i < a->size; i++)
res->value[i] = a->value[i];
if (res->value[res->size - 1] == 0){
res->size--;
}
}
void copybig(big* a, big* res){
res->size = a->size;
for (int i = 0; i < res->size; i++){
res->value[i] = a->value[i];
}
}
void stringtobig(stringnumber* sn, big* res, big* mulbuff, big* ten){
res->size = 0;
for (int i = sn->size-1; i >= 0; i--){
kali(res, ten, mulbuff);
tambah(mulbuff, sn->value[i], res);
}
}
void bigtostring(big* x, stringnumber* sn, big* ten, big* xbuff, big* divbuff, big* modbuff, uint* minbuff) {
copybig(x,xbuff);
short snlength = 0;
while (xbuff->size != 0 ) {
divandmod(xbuff,ten,divbuff,modbuff,minbuff);
sn->value[snlength] = (char) modbuff->value[0];
snlength++;
copybig(divbuff,xbuff);
}
sn->size = snlength;
}
void printsn(stringnumber* sn){
for (int i = 0; i < sn->size; ++i){
printf("%d", sn->value[sn->size-i-1]);
}
printf("\n");
}
void teskonversi(){
int seed = time(NULL);
srand(seed);
stringnumber *sn = (stringnumber*) malloc(sizeof(stringnumber));
sn->size = 25;
sn->value = (char *) malloc(sn->size);
for (int i = 0; i < sn->size; i++)
{
sn->value[i] = rand() % 10;
}
big* konversi = (big*) malloc(sizeof(big));
big* mulbuff = (big*) malloc(sizeof(big));
big* ten = (big*) malloc(sizeof(big));
konversi->value = (uint*) malloc(sizeof(10));
mulbuff->value = (uint*) malloc(sizeof(10));
ten->value = (uint*) malloc(sizeof(1));
ten->size = 1;
ten->value[0] = 10;
printf("Stringnumber awal : ");
printsn(sn);
stringtobig(sn, konversi, mulbuff, ten);
printf("konversi size %d\n", konversi->size);
printf("konversi value 0 %u\n", konversi->value[0]);
printf("konversi value 0 %u\n", konversi->value[1]);
stringnumber *sn2 = (stringnumber*) malloc(sizeof(stringnumber));
big* xbuff = (big*) malloc(sizeof(big));
big* divbuff = (big*) malloc(sizeof(big));
big* modbuff = (big*) malloc(sizeof(big));
sn2->value = (char *) malloc(100);
xbuff->value = (uint *) malloc(sizeof(uint) * 10);
divbuff->value = (uint *) malloc(sizeof(uint) * 10);
modbuff->value = (uint *) malloc(sizeof(uint) * 10);
uint* minbuff = (uint*) malloc(sizeof(uint) * 10);
bigtostring(konversi,sn2,ten,xbuff,divbuff,modbuff,minbuff);
printf("Stringnumber akhir : ");
printsn(sn2);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <time.h>
typedef unsigned long long ul;
typedef unsigned int uint;
int banyakdata = 256;
int dimensigrid = 2;
int dimensiblok = 128;
typedef struct {
char size;
uint* value;
}big;
typedef struct {
short size;
char* value;
}stringnumber;
__host__ __device__ short ukuranbit(big *a);
__host__ __device__ char getbit(big* a, short count);
__host__ __device__ uint getShiftedBlock(big *num, char noblok, char geser);
__host__ __device__ void kali(big *a, big *b, big* res);
__host__ __device__ void modulo(big* a, big* b, big* res, uint* minbuff);
__host__ __device__ void modexp(big* a, big* b, big* c, big* res, uint* minbuff, big* mulbuff);
void enkripsi(big *m, big *k, big *g, big *p, big *y, big *res, big *minbuff, big *mulbuff);
void dekripsi(big *c1, big *c2, big *e, big *p, big *res, big *minbuff, big *mulbuff);
void kernelenk(big *m, big *k, big *g, big *p, big *y, big *res, big *minbuff, big *mulbuff);
void kerneldek(big *c, big *e, big *p, big *res, big *minbuff, big *mulbuff);
void CUDAenk(big *m, big *k, big* g, big* p, big* y, big *res);
void CUDAdek(big *c, big *e, big* p, big *res);
void mainenkripsi(big *m, big *k, big *res, big *g, big *p, big *y);
void maindekripsi(big* c,big* x,big* p,big* res2);
void tambah(big* a, char b, big* res);
void kurang(big* a, big *b, big* res);
void divandmod(big* a, big* &b, big* divres, big* modres, uint* minbuff);
void carikunciy(big *g, big *x, big *p, big *y, uint *minbuff, big *mulbuff);
void init(big *p, big *g, big *x, big*e, big *y, big *m, big *k, big *res, big *res2);
void copybig(big* a, big* res);
void stringtobig(stringnumber* sn, big* res, big* mulbuff, big* ten);
void bigtostring(big* x, stringnumber* sn, big* ten, big* xbuff, big* divbuff, big* modbuff, uint* minbuff);
void printsn(stringnumber* sn);
void teskonversi();
void enkripsi(big *m, big *k, big *g, big *p, big *y, big *res, big *minbuff, big *mulbuff) {
// BLok 1 Cipher
modexp(g,k,p,res,minbuff->value,mulbuff);
// Blok 2 Cipher
modexp(y, k, p, res + 1,minbuff->value,mulbuff);
kali(res + 1, m, mulbuff);
modulo(mulbuff, p, res+1, minbuff->value);
}
void dekripsi(big *c1, big *c2, big *e, big *p, big *res, big *minbuff, big *mulbuff) {
modexp(c1,e,p,res,minbuff->value,mulbuff);
kali(res, c2, mulbuff);
modulo(mulbuff, p, res, minbuff->value);
}
void kernelenk(big *m, big *k, big *g, big *p, big *y, big *res, big *minbuff, big *mulbuff){
for (int i = 0; i < banyakdata; i++)
{
enkripsi(m + i, k + i, g, p, y, res + 2 * i, minbuff+i, mulbuff+i);
}
}
void kerneldek(big *c, big *e, big *p, big *res, big *minbuff, big *mulbuff){
for (int i = 0; i < banyakdata; i++)
{
dekripsi(c + 2*i, c + 2*i+1, e, p, res+i, minbuff+i, mulbuff+i);
}
}
void CUDAenk(big *m, big *k, big* g, big* p, big* y, big *res) {
big *minbuff, *mulbuff;
minbuff = (big*) malloc(banyakdata * sizeof(big));
mulbuff = (big*) malloc(banyakdata * sizeof(big));
for (int i = 0; i < banyakdata; i++) {
minbuff[i].value = (uint*) malloc(sizeof(uint) * p->size * 2);
mulbuff[i].value = (uint*) malloc(sizeof(uint) * p->size * 2);
}
clock_t begin = clock();
kernelenk(m, k, g, p, y, res, minbuff, mulbuff);
clock_t end = clock();
double time_spent = (double)(end - begin) / 1000;
printf("Durasi : %f ms\n", time_spent);
}
void CUDAdek(big *c, big *e, big* p, big *res) {
big *minbuff, *mulbuff;
minbuff = (big*) malloc(banyakdata * sizeof(big));
mulbuff = (big*) malloc(banyakdata * sizeof(big));
for (int i = 0; i < banyakdata; i++) {
minbuff[i].value = (uint*) malloc(sizeof(uint) * p->size * 2);
mulbuff[i].value = (uint*) malloc(sizeof(uint) * p->size * 2);
}
clock_t begin = clock();
kerneldek(c, e, p, res, minbuff, mulbuff);
clock_t end = clock();
double time_spent = (double)(end - begin) / 1000;
printf("Durasi : %f ms\n", time_spent);
}
void mainenkripsi(big *m, big *k, big *res, big *g, big *p, big *y){
printf("Encrypting...\n");
CUDAenk(m, k, g, p, y, res);
for (int i = 0; i < 5; i++)
{
printf("Cipher %d size %d : %u\n",i, res[i].size, res[i].value[0]);
}
printf("Cipher ... : ...\n");
printf("Cipher %d size %d : %u\n",banyakdata*2-2, res[banyakdata*2-2].size, res[banyakdata*2-2].value[0]);
printf("Cipher %d size %d : %u\n",banyakdata*2-1, res[banyakdata*2-2].size, res[banyakdata*2-1].value[0]);
}
void maindekripsi(big* c, big* e,big* p,big* res2){
printf("Decrypting...\n");
CUDAdek(c, e, p, res2);
for (int i = 0; i < 5; i++)
{
printf("Plain %d size %d : %u\n",i, res2[i].size, res2[i].value[0]);
printf("Plain %d size %d : %u\n",i, res2[i].size, res2[i].value[1]);
}
printf("Plain ... : ...\n");
printf("Plain %d size %d : %u\n",banyakdata-1, res2[banyakdata-1].size, res2[banyakdata-1].value[0]);
}
void carikunciy(big *g, big *x, big *p, big *y, uint *minbuff, big *mulbuff){
modexp(g,x,p,y,minbuff,mulbuff);
}
void init(big *p, big *g, big *x, big*e, big *y, big *m, big *k, big *res, big *res2){
// Kunci publik p
p->size = 16;
p->value = (uint*) malloc(p->size * sizeof(uint));
p->value[0] = UINT_MAX;
for (int i = 1; i < p->size; i++)
{
//p->value[i] = 2357;
p->value[i] = rand() % UINT_MAX;
}
// p->value[0] = UINT_MAX-4;
// p->value[0] = 2387;
// p->value[1] = 2357;
// Kunci publik g
g->size = 16;
g->value = (uint*) malloc(g->size * sizeof(uint));
for (int i = 0; i < g->size; i++)
{
// g->value[i] = 2;
g->value[i] = rand() % UINT_MAX;
}
// Kunci privat x
x->size = 16;
x->value = (uint*) malloc(x->size * sizeof(uint));
for (int i = 0; i < x->size; i++)
{
// x->value[i] = 1751;
x->value[i] = rand() % UINT_MAX;
}
// Cari nilai eksponen e = (p-x-1) untuk dekripsi
big *xplus1 = (big*) malloc(sizeof(big));
xplus1->value = (uint*) malloc(p->size * sizeof(uint));
e->value = (uint*) malloc(p->size * sizeof(uint));
tambah(x, 1, xplus1);
kurang(p,xplus1,e);
// printf("e adalah %u\n", e->value[0]);
free(xplus1->value);
free(xplus1);
// Cari nilai kunci publik y = (g^x) mod p
big* mulbuff = (big*) malloc(sizeof(big));
mulbuff->value = (uint*) malloc(sizeof(uint) * p->size * 2);
uint* minbuff = (uint*) malloc(sizeof(uint) * p->size * 2);
y->value = (uint*) malloc(p->size * 2 * sizeof(uint));
carikunciy(g,x,p,y,minbuff,mulbuff);
// printf("y adalah %u\n",y->value[0]);
//========================================================//
// Blok plainteks
for(int i = 0 ; i < banyakdata ; i++){
m[i].size = 16;
m[i].value = (uint*) malloc(m[i].size * sizeof(uint));
for (int j = 0; j < m[i].size; j++)
{
// m[i].value[j] = 1001;
m[i].value[j] = rand() % UINT_MAX;
}
// Nilai k masing-masing blok
k[i].size = 16;
k[i].value = (uint*) malloc(k[i].size * sizeof(uint));
for (int j = 0; j < k[i].size; j++)
{
// k[i].value[j] = 77;
k[i].value[j] = rand() % UINT_MAX;
}
}
// Alokasi memori untuk result
for (int i = 0; i < banyakdata*2; i++)
{
res[i].value = (uint*) malloc(sizeof(uint) * p->size *2);
}
// Alokasi memori untuk result 2
for (int i = 0; i < banyakdata; i++)
{
res2[i].value = (uint*) malloc(sizeof(uint) * p->size * 2);
}
}
int main(){
big *p, *g, *x, *e, *y, *m, *k, *res, *res2;
p = (big*)malloc(sizeof(big));
g = (big*)malloc(sizeof(big));
x = (big*)malloc(sizeof(big));
e = (big*)malloc(sizeof(big));
y = (big*)malloc(sizeof(big));
m = (big*)malloc(banyakdata * sizeof(big));
k = (big*)malloc(banyakdata * sizeof(big));
res = (big*)malloc(banyakdata * 2 * sizeof(big));
res2 = (big*)malloc(banyakdata * sizeof(big));
init(p,g,x,e,y,m,k,res,res2);
mainenkripsi(m,k,res,g,p,y);
printf(" ========================= \n");
maindekripsi(res,e,p,res2);
free(p->value);
free(p);
free(g->value);
free(g);
free(x->value);
free(x);
free(e->value);
free(e);
free(y->value);
free(y);
free(m->value);
free(m);
free(k->value);
free(k);
free(res->value);
free(res);
free(res2->value);
free(res2);
//teskonversi();
return 0;
}
__host__ __device__ short ukuranbit(big *a) {
uint lastval = a->value[a->size-1];
short res = 0;
while (lastval != 0) {
lastval >>= 1;
res++;
}
return res + (a->size - 1) * 32;
}
__host__ __device__ char getbit(big* a, short count) {
return (a->value[count / 32] & ((uint) 1 << (count % 32))) != 0;
}
__host__ __device__ uint getShiftedBlock(big *num, char noblok, char geser) {
uint part1 = (noblok == 0 || geser == 0) ? 0 : (num->value[noblok - 1] >> (32-geser));
uint part2 = (noblok == num->size) ? 0 : (num->value[noblok] << geser);
return part1 | part2;
}
__host__ __device__ void kali(big *a, big *b, big* res) {
if (a->size == 0 || b->size == 0) {
res->size = 0;
return ;
}
char ukurana = a->size;
char ukuranb = b->size;
char ukuranres = ukurana + ukuranb;
res->size = ukuranres;
for (char i = 0; i < ukuranres; i++) {
res->value[i] = 0;
}
for (char i = 0; i < ukurana; i++) {
uint aval = a->value[i];
if (aval==0){
continue;
}
uint lebih = 0;
for (char j = 0, lebih = 0; j < ukuranb; j++) {
uint bval = b->value[j];
ul temp = res->value[i+j] + aval * bval + lebih;
res->value[i+j] = temp % UINT_MAX;
lebih = temp / UINT_MAX;
}
res->value[i+ukuranb] = lebih;
}
if (res->value[res->size - 1] == 0){
res->size--;
}
}
__host__ __device__ void modexp(big* a, big* b, big* c, big* res, uint* minbuff, big* mulbuff){
res->size = 1;
res->value[0] = 1;
short i = ukuranbit(b);
while (i > 0) {
i--;
kali(res,res,mulbuff);
modulo(mulbuff,c,res,minbuff);
if (getbit(b,i)) {
kali(res, a, mulbuff);
modulo(mulbuff, c, res, minbuff);
}
}
}
__host__ __device__ void modulo(big* a, big* b, big* res, uint* minbuff) {
res->size = a->size;
for(char i = 0 ; i < res->size ;i++){
res->value[i] = a->value[i];
}
if (a->size < b->size) {
return ;
}
char i, j, k;
char i2;
uint temp ;
char borrowIn, borrowOut;
char ukurana = a->size;
char ukuranb = b->size;
res->value[res->size] = 0;
res->size++;
i = ukurana - ukuranb + 1;
while (i > 0) {
i--;
i2 = 32;
while (i2 > 0) {
i2--;
for (j = 0, k = i, borrowIn = 0; j <= ukuranb; j++, k++) {
temp = res->value[k] - getShiftedBlock(b, j, i2);
borrowOut = (temp > res->value[k]);
if (borrowIn) {
borrowOut |= (temp == 0);
temp--;
}
minbuff[k] = temp;
borrowIn = borrowOut;
}
for (; k < ukurana && borrowIn; k++) {
borrowIn = (res->value[k] == 0);
minbuff[k] = res->value[k] - 1;
}
if (!borrowIn) {
while (k > i) {
k--;
res->value[k] = minbuff[k];
}
}
}
}
while (res->size > 0 && res->value[res->size - 1] == 0)
res->size--;
}
void divandmod(big* a, big* &b, big* divres, big* modres, uint* minbuff) {
modres->size = a->size;
for(char i = 0 ; i < modres->size ;i++){
modres->value[i] = a->value[i];
}
if (a->size < b->size) {
return ;
}
char i, j, k;
char i2;
uint temp ;
char borrowIn, borrowOut;
char ukurana = a->size;
char ukuranb = b->size;
modres->value[modres->size] = 0;
modres->size++;
divres->size = ukurana - ukuranb + 1;
for (i = 0; i < divres->size; i++)
divres->value[i] = 0;
i = ukurana - ukuranb + 1;
while (i > 0) {
i--;
divres->value[i] = 0;
i2 = 32;
while (i2 > 0) {
i2--;
for (j = 0, k = i, borrowIn = 0; j <= ukuranb; j++, k++) {
temp = modres->value[k] - getShiftedBlock(b, j, i2);
borrowOut = (temp > modres->value[k]);
if (borrowIn) {
borrowOut |= (temp == 0);
temp--;
}
minbuff[k] = temp;
borrowIn = borrowOut;
}
for (; k < ukurana && borrowIn; k++) {
borrowIn = (modres->value[k] == 0);
minbuff[k] = modres->value[k] - 1;
}
if (!borrowIn) {
divres->value[i] |= ((uint) 1 << i2);
while (k > i) {
k--;
modres->value[k] = minbuff[k];
}
}
}
}
if (divres->value[divres->size - 1] == 0)
divres->size--;
while (modres->size > 0 && modres->value[modres->size - 1] == 0)
modres->size--;
}
void tambah(big* a, char b, big* res) {
if (a->size == 0) {
res->size = 1;
res->value[0] = uint(b);
return;
}
char carryIn = 0;
uint temp;
res->size = a->size + 1;
res->value[0] = a->value[0] + (uint)b;
carryIn = (res->value[0] < a->value[0]);
char i = 1;
for (; i < a->size && carryIn; i++) {
temp = a->value[i] + (uint)1;
carryIn = (temp == 0);
res->value[i] = temp;
}
for (; i < a->size; i++)
res->value[i] = a->value[i];
if (carryIn)
res->value[i] = 1;
else
res->size--;
}
void kurang(big* a, big *b, big* res) {
res->size = a->size;
for (int i = 0; i < res->size; i++){
res->value[i] = 0;
}
if (b->size == 0) {
return;
}
char borrowIn, borrowOut;
uint temp;
char i;
for (i = 0, borrowIn = 0; i < b->size; i++) {
temp = a->value[i] - b->value[i];
borrowOut = (temp > a->value[i]);
if (borrowIn) {
borrowOut |= (temp == 0);
temp--;
}
res->value[i] = temp;
borrowIn = borrowOut;
}
for (; i < a->size && borrowIn; i++) {
borrowIn = (a->value[i] == 0);
res->value[i] = a->value[i] - 1;
}
for (; i < a->size; i++)
res->value[i] = a->value[i];
if (res->value[res->size - 1] == 0){
res->size--;
}
}
void copybig(big* a, big* res){
res->size = a->size;
for (int i = 0; i < res->size; i++){
res->value[i] = a->value[i];
}
}
void stringtobig(stringnumber* sn, big* res, big* mulbuff, big* ten){
res->size = 0;
for (int i = sn->size-1; i >= 0; i--){
kali(res, ten, mulbuff);
tambah(mulbuff, sn->value[i], res);
}
}
void bigtostring(big* x, stringnumber* sn, big* ten, big* xbuff, big* divbuff, big* modbuff, uint* minbuff) {
copybig(x,xbuff);
short snlength = 0;
while (xbuff->size != 0 ) {
divandmod(xbuff,ten,divbuff,modbuff,minbuff);
sn->value[snlength] = (char) modbuff->value[0];
snlength++;
copybig(divbuff,xbuff);
}
sn->size = snlength;
}
void printsn(stringnumber* sn){
for (int i = 0; i < sn->size; ++i){
printf("%d", sn->value[sn->size-i-1]);
}
printf("\n");
}
void teskonversi(){
int seed = time(NULL);
srand(seed);
stringnumber *sn = (stringnumber*) malloc(sizeof(stringnumber));
sn->size = 25;
sn->value = (char *) malloc(sn->size);
for (int i = 0; i < sn->size; i++)
{
sn->value[i] = rand() % 10;
}
big* konversi = (big*) malloc(sizeof(big));
big* mulbuff = (big*) malloc(sizeof(big));
big* ten = (big*) malloc(sizeof(big));
konversi->value = (uint*) malloc(sizeof(10));
mulbuff->value = (uint*) malloc(sizeof(10));
ten->value = (uint*) malloc(sizeof(1));
ten->size = 1;
ten->value[0] = 10;
printf("Stringnumber awal : ");
printsn(sn);
stringtobig(sn, konversi, mulbuff, ten);
printf("konversi size %d\n", konversi->size);
printf("konversi value 0 %u\n", konversi->value[0]);
printf("konversi value 0 %u\n", konversi->value[1]);
stringnumber *sn2 = (stringnumber*) malloc(sizeof(stringnumber));
big* xbuff = (big*) malloc(sizeof(big));
big* divbuff = (big*) malloc(sizeof(big));
big* modbuff = (big*) malloc(sizeof(big));
sn2->value = (char *) malloc(100);
xbuff->value = (uint *) malloc(sizeof(uint) * 10);
divbuff->value = (uint *) malloc(sizeof(uint) * 10);
modbuff->value = (uint *) malloc(sizeof(uint) * 10);
uint* minbuff = (uint*) malloc(sizeof(uint) * 10);
bigtostring(konversi,sn2,ten,xbuff,divbuff,modbuff,minbuff);
printf("Stringnumber akhir : ");
printsn(sn2);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void counting_sort(int* array, int *temp, int size) {
int i, j, count;
i = threadIdx.x + (blockIdx.x * blockDim.x);
if (i < size) {
count = 0;
for(j = 0; j < size; j++) {
if(array[j] < array[i]) {
count++;
} else if(array[i] == array[j] && j < i) {
count++;
}
}
temp[count] = array[i];
}
} | code for sm_80
Function : _Z13counting_sortPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc600078e00ff */
/*0090*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe20003f06270 */
/*00a0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0205 */
/*00b0*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000162000c1e1900 */
/*00c0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fcc00078e00ff */
/*00d0*/ @!P0 BRA 0x1060 ; /* 0x00000f8000008947 */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R2, R6.reuse, -0x1, RZ ; /* 0xffffffff06027810 */
/* 0x041fe20007ffe0ff */
/*00f0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe200078e00ff */
/*0100*/ LOP3.LUT R6, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306067812 */
/* 0x000fe200078ec0ff */
/*0110*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0130*/ @!P0 BRA 0xf40 ; /* 0x00000e0000008947 */
/* 0x000fea0003800000 */
/*0140*/ IADD3 R16, -R6, c[0x0][0x170], RZ ; /* 0x00005c0006107a10 */
/* 0x000fe20007ffe1ff */
/*0150*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe400078e00ff */
/*0160*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0170*/ ISETP.GT.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe20003f04270 */
/*0180*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fd800078e00ff */
/*0190*/ @!P0 BRA 0xd30 ; /* 0x00000b9000008947 */
/* 0x000fea0003800000 */
/*01a0*/ ISETP.GT.AND P1, PT, R16, 0xc, PT ; /* 0x0000000c1000780c */
/* 0x000fe40003f24270 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01c0*/ @!P1 BRA 0x930 ; /* 0x0000076000009947 */
/* 0x000fea0003800000 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01e0*/ LDG.E R14, [R2.64] ; /* 0x00000004020e7981 */
/* 0x000ea8000c1e1900 */
/*01f0*/ LDG.E R18, [R2.64+0x4] ; /* 0x0000040402127981 */
/* 0x000ee8000c1e1900 */
/*0200*/ LDG.E R20, [R2.64+0x8] ; /* 0x0000080402147981 */
/* 0x000f28000c1e1900 */
/*0210*/ LDG.E R12, [R2.64+0xc] ; /* 0x00000c04020c7981 */
/* 0x000f28000c1e1900 */
/*0220*/ LDG.E R10, [R2.64+0x10] ; /* 0x00001004020a7981 */
/* 0x000f28000c1e1900 */
/*0230*/ LDG.E R27, [R2.64+0x14] ; /* 0x00001404021b7981 */
/* 0x000f28000c1e1900 */
/*0240*/ LDG.E R29, [R2.64+0x18] ; /* 0x00001804021d7981 */
/* 0x000f28000c1e1900 */
/*0250*/ LDG.E R23, [R2.64+0x1c] ; /* 0x00001c0402177981 */
/* 0x000f28000c1e1900 */
/*0260*/ LDG.E R25, [R2.64+0x20] ; /* 0x0000200402197981 */
/* 0x000f28000c1e1900 */
/*0270*/ LDG.E R19, [R2.64+0x24] ; /* 0x0000240402137981 */
/* 0x000f28000c1e1900 */
/*0280*/ LDG.E R21, [R2.64+0x28] ; /* 0x0000280402157981 */
/* 0x000f28000c1e1900 */
/*0290*/ LDG.E R15, [R2.64+0x2c] ; /* 0x00002c04020f7981 */
/* 0x000f28000c1e1900 */
/*02a0*/ LDG.E R17, [R2.64+0x30] ; /* 0x0000300402117981 */
/* 0x000f28000c1e1900 */
/*02b0*/ LDG.E R9, [R2.64+0x34] ; /* 0x0000340402097981 */
/* 0x000f28000c1e1900 */
/*02c0*/ LDG.E R13, [R2.64+0x38] ; /* 0x00003804020d7981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R11, [R2.64+0x3c] ; /* 0x00003c04020b7981 */
/* 0x000f22000c1e1900 */
/*02e0*/ IADD3 R22, R7, 0x2, RZ ; /* 0x0000000207167810 */
/* 0x000fc40007ffe0ff */
/*02f0*/ IADD3 R16, R16, -0x10, RZ ; /* 0xfffffff010107810 */
/* 0x000fe40007ffe0ff */
/*0300*/ ISETP.NE.AND P1, PT, R4, R14, PT ; /* 0x0000000e0400720c */
/* 0x024fc80003f25270 */
/*0310*/ ISETP.LT.AND P1, PT, R7.reuse, R0, !P1 ; /* 0x000000000700720c */
/* 0x040fe40004f21270 */
/*0320*/ ISETP.NE.AND P2, PT, R4, R18, PT ; /* 0x000000120400720c */
/* 0x008fe40003f45270 */
/*0330*/ ISETP.LT.OR P1, PT, R14, R4, P1 ; /* 0x000000040e00720c */
/* 0x000fe40000f21670 */
/*0340*/ IADD3 R14, R7, 0x1, RZ ; /* 0x00000001070e7810 */
/* 0x000fe40007ffe0ff */
/*0350*/ ISETP.NE.AND P3, PT, R4, R20, PT ; /* 0x000000140400720c */
/* 0x010fe40003f65270 */
/*0360*/ ISETP.LT.AND P2, PT, R14, R0, !P2 ; /* 0x000000000e00720c */
/* 0x000fc40005741270 */
/*0370*/ ISETP.LT.AND P3, PT, R22, R0, !P3 ; /* 0x000000001600720c */
/* 0x000fe40005f61270 */
/*0380*/ ISETP.LT.OR P2, PT, R18, R4.reuse, P2 ; /* 0x000000041200720c */
/* 0x080fe40001741670 */
/*0390*/ IADD3 R14, R8, 0x1, RZ ; /* 0x00000001080e7810 */
/* 0x000fe20007ffe0ff */
/*03a0*/ @!P1 IMAD.MOV R14, RZ, RZ, R8 ; /* 0x000000ffff0e9224 */
/* 0x000fe200078e0208 */
/*03b0*/ ISETP.LT.OR P1, PT, R20, R4, P3 ; /* 0x000000041400720c */
/* 0x000fe40001f21670 */
/*03c0*/ IADD3 R8, R7, 0x3, RZ ; /* 0x0000000307087810 */
/* 0x000fe40007ffe0ff */
/*03d0*/ ISETP.NE.AND P3, PT, R4, R12, PT ; /* 0x0000000c0400720c */
/* 0x000fc40003f65270 */
/*03e0*/ IADD3 R18, R14, 0x1, RZ ; /* 0x000000010e127810 */
/* 0x000fe40007ffe0ff */
/*03f0*/ ISETP.LT.AND P3, PT, R8, R0, !P3 ; /* 0x000000000800720c */
/* 0x000fe20005f61270 */
/*0400*/ @!P2 IMAD.MOV R18, RZ, RZ, R14 ; /* 0x000000ffff12a224 */
/* 0x000fe200078e020e */
/*0410*/ IADD3 R8, R7, 0x4, RZ ; /* 0x0000000407087810 */
/* 0x000fe40007ffe0ff */
/*0420*/ ISETP.LT.OR P3, PT, R12, R4, P3 ; /* 0x000000040c00720c */
/* 0x000fe40001f61670 */
/*0430*/ ISETP.NE.AND P2, PT, R4, R10, PT ; /* 0x0000000a0400720c */
/* 0x000fe40003f45270 */
/*0440*/ IADD3 R12, R18, 0x1, RZ ; /* 0x00000001120c7810 */
/* 0x000fe20007ffe0ff */
/*0450*/ @!P1 IMAD.MOV R12, RZ, RZ, R18 ; /* 0x000000ffff0c9224 */
/* 0x000fe200078e0212 */
/*0460*/ ISETP.LT.AND P2, PT, R8, R0, !P2 ; /* 0x000000000800720c */
/* 0x000fc40005741270 */
/*0470*/ IADD3 R8, R7.reuse, 0x5, RZ ; /* 0x0000000507087810 */
/* 0x040fe40007ffe0ff */
/*0480*/ ISETP.LT.OR P1, PT, R10, R4, P2 ; /* 0x000000040a00720c */
/* 0x000fe40001721670 */
/*0490*/ ISETP.NE.AND P2, PT, R4, R27, PT ; /* 0x0000001b0400720c */
/* 0x000fe40003f45270 */
/*04a0*/ IADD3 R10, R12, 0x1, RZ ; /* 0x000000010c0a7810 */
/* 0x000fe20007ffe0ff */
/*04b0*/ @!P3 IMAD.MOV R10, RZ, RZ, R12 ; /* 0x000000ffff0ab224 */
/* 0x000fe200078e020c */
/*04c0*/ ISETP.LT.AND P3, PT, R8, R0, !P2 ; /* 0x000000000800720c */
/* 0x000fe40005761270 */
/*04d0*/ IADD3 R8, R7, 0x6, RZ ; /* 0x0000000607087810 */
/* 0x000fc40007ffe0ff */
/*04e0*/ ISETP.NE.AND P2, PT, R4, R29, PT ; /* 0x0000001d0400720c */
/* 0x000fe40003f45270 */
/*04f0*/ ISETP.LT.OR P3, PT, R27, R4, P3 ; /* 0x000000041b00720c */
/* 0x000fe40001f61670 */
/*0500*/ ISETP.LT.AND P2, PT, R8, R0, !P2 ; /* 0x000000000800720c */
/* 0x000fe40005741270 */
/*0510*/ IADD3 R12, R10, 0x1, RZ ; /* 0x000000010a0c7810 */
/* 0x000fe20007ffe0ff */
/*0520*/ @!P1 IMAD.MOV R12, RZ, RZ, R10 ; /* 0x000000ffff0c9224 */
/* 0x000fe200078e020a */
/*0530*/ ISETP.LT.OR P1, PT, R29, R4, P2 ; /* 0x000000041d00720c */
/* 0x000fe40001721670 */
/*0540*/ IADD3 R27, R7, 0x7, RZ ; /* 0x00000007071b7810 */
/* 0x000fc40007ffe0ff */
/*0550*/ ISETP.NE.AND P2, PT, R4, R23, PT ; /* 0x000000170400720c */
/* 0x000fe40003f45270 */
/*0560*/ IADD3 R8, R12, 0x1, RZ ; /* 0x000000010c087810 */
/* 0x000fe20007ffe0ff */
/*0570*/ @!P3 IMAD.MOV R8, RZ, RZ, R12 ; /* 0x000000ffff08b224 */
/* 0x000fe200078e020c */
/*0580*/ ISETP.LT.AND P2, PT, R27, R0, !P2 ; /* 0x000000001b00720c */
/* 0x000fe40005741270 */
/*0590*/ IADD3 R27, R7, 0x8, RZ ; /* 0x00000008071b7810 */
/* 0x000fe40007ffe0ff */
/*05a0*/ ISETP.NE.AND P3, PT, R4, R25, PT ; /* 0x000000190400720c */
/* 0x000fe40003f65270 */
/*05b0*/ ISETP.LT.OR P2, PT, R23, R4, P2 ; /* 0x000000041700720c */
/* 0x000fc40001741670 */
/*05c0*/ ISETP.LT.AND P3, PT, R27, R0, !P3 ; /* 0x000000001b00720c */
/* 0x000fe40005f61270 */
/*05d0*/ IADD3 R10, R8, 0x1, RZ ; /* 0x00000001080a7810 */
/* 0x000fe20007ffe0ff */
/*05e0*/ @!P1 IMAD.MOV R10, RZ, RZ, R8 ; /* 0x000000ffff0a9224 */
/* 0x000fe200078e0208 */
/*05f0*/ ISETP.LT.OR P1, PT, R25, R4, P3 ; /* 0x000000041900720c */
/* 0x000fe40001f21670 */
/*0600*/ IADD3 R23, R7, 0x9, RZ ; /* 0x0000000907177810 */
/* 0x000fe40007ffe0ff */
/*0610*/ ISETP.NE.AND P3, PT, R4, R19, PT ; /* 0x000000130400720c */
/* 0x000fe40003f65270 */
/*0620*/ IADD3 R8, R10, 0x1, RZ ; /* 0x000000010a087810 */
/* 0x000fe20007ffe0ff */
/*0630*/ @!P2 IMAD.MOV R8, RZ, RZ, R10 ; /* 0x000000ffff08a224 */
/* 0x000fe200078e020a */
/*0640*/ ISETP.LT.AND P3, PT, R23, R0, !P3 ; /* 0x000000001700720c */
/* 0x000fc40005f61270 */
/*0650*/ IADD3 R23, R7, 0xa, RZ ; /* 0x0000000a07177810 */
/* 0x000fe40007ffe0ff */
/*0660*/ ISETP.NE.AND P2, PT, R4, R21, PT ; /* 0x000000150400720c */
/* 0x000fe40003f45270 */
/*0670*/ ISETP.LT.OR P3, PT, R19, R4, P3 ; /* 0x000000041300720c */
/* 0x000fe40001f61670 */
/*0680*/ ISETP.LT.AND P2, PT, R23, R0, !P2 ; /* 0x000000001700720c */
/* 0x000fe40005741270 */
/*0690*/ IADD3 R10, R8, 0x1, RZ ; /* 0x00000001080a7810 */
/* 0x000fe20007ffe0ff */
/*06a0*/ @!P1 IMAD.MOV R10, RZ, RZ, R8 ; /* 0x000000ffff0a9224 */
/* 0x000fe200078e0208 */
/*06b0*/ ISETP.LT.OR P1, PT, R21, R4, P2 ; /* 0x000000041500720c */
/* 0x000fc40001721670 */
/*06c0*/ IADD3 R19, R7, 0xb, RZ ; /* 0x0000000b07137810 */
/* 0x000fe40007ffe0ff */
/*06d0*/ ISETP.NE.AND P2, PT, R4, R15, PT ; /* 0x0000000f0400720c */
/* 0x000fe40003f45270 */
/*06e0*/ IADD3 R8, R10, 0x1, RZ ; /* 0x000000010a087810 */
/* 0x000fe20007ffe0ff */
/*06f0*/ @!P3 IMAD.MOV R8, RZ, RZ, R10 ; /* 0x000000ffff08b224 */
/* 0x000fe200078e020a */
/*0700*/ ISETP.LT.AND P2, PT, R19, R0, !P2 ; /* 0x000000001300720c */
/* 0x000fe40005741270 */
/*0710*/ IADD3 R19, R7, 0xc, RZ ; /* 0x0000000c07137810 */
/* 0x000fe40007ffe0ff */
/*0720*/ ISETP.LT.OR P2, PT, R15, R4, P2 ; /* 0x000000040f00720c */
/* 0x000fc40001741670 */
/*0730*/ ISETP.NE.AND P3, PT, R4, R17, PT ; /* 0x000000110400720c */
/* 0x000fe40003f65270 */
/*0740*/ IADD3 R10, R8, 0x1, RZ ; /* 0x00000001080a7810 */
/* 0x000fe20007ffe0ff */
/*0750*/ @!P1 IMAD.MOV R10, RZ, RZ, R8 ; /* 0x000000ffff0a9224 */
/* 0x000fe200078e0208 */
/*0760*/ ISETP.LT.AND P3, PT, R19, R0, !P3 ; /* 0x000000001300720c */
/* 0x000fe40005f61270 */
/*0770*/ IADD3 R15, R7, 0xd, RZ ; /* 0x0000000d070f7810 */
/* 0x000fe40007ffe0ff */
/*0780*/ ISETP.LT.OR P1, PT, R17, R4, P3 ; /* 0x000000041100720c */
/* 0x000fe40001f21670 */
/*0790*/ ISETP.NE.AND P3, PT, R4, R9, PT ; /* 0x000000090400720c */
/* 0x000fc40003f65270 */
/*07a0*/ IADD3 R8, R10, 0x1, RZ ; /* 0x000000010a087810 */
/* 0x000fe20007ffe0ff */
/*07b0*/ @!P2 IMAD.MOV R8, RZ, RZ, R10 ; /* 0x000000ffff08a224 */
/* 0x000fe200078e020a */
/*07c0*/ ISETP.LT.AND P2, PT, R15, R0, !P3 ; /* 0x000000000f00720c */
/* 0x000fe40005f41270 */
/*07d0*/ IADD3 R15, R7, 0xe, RZ ; /* 0x0000000e070f7810 */
/* 0x000fe40007ffe0ff */
/*07e0*/ ISETP.NE.AND P3, PT, R4, R13, PT ; /* 0x0000000d0400720c */
/* 0x000fe40003f65270 */
/*07f0*/ ISETP.LT.OR P2, PT, R9, R4, P2 ; /* 0x000000040900720c */
/* 0x000fe40001741670 */
/*0800*/ ISETP.LT.AND P3, PT, R15, R0, !P3 ; /* 0x000000000f00720c */
/* 0x000fc40005f61270 */
/*0810*/ IADD3 R10, R8, 0x1, RZ ; /* 0x00000001080a7810 */
/* 0x000fe20007ffe0ff */
/*0820*/ @!P1 IMAD.MOV R10, RZ, RZ, R8 ; /* 0x000000ffff0a9224 */
/* 0x000fe200078e0208 */
/*0830*/ ISETP.LT.OR P1, PT, R13, R4, P3 ; /* 0x000000040d00720c */
/* 0x000fe40001f21670 */
/*0840*/ IADD3 R9, R7.reuse, 0xf, RZ ; /* 0x0000000f07097810 */
/* 0x040fe40007ffe0ff */
/*0850*/ IADD3 R8, R10, 0x1, RZ ; /* 0x000000010a087810 */
/* 0x000fe40007ffe0ff */
/*0860*/ ISETP.NE.AND P3, PT, R4, R11, PT ; /* 0x0000000b0400720c */
/* 0x000fe20003f65270 */
/*0870*/ @!P2 IMAD.MOV R8, RZ, RZ, R10 ; /* 0x000000ffff08a224 */
/* 0x000fe200078e020a */
/*0880*/ IADD3 R7, R7, 0x10, RZ ; /* 0x0000001007077810 */
/* 0x000fc40007ffe0ff */
/*0890*/ ISETP.LT.AND P3, PT, R9, R0, !P3 ; /* 0x000000000900720c */
/* 0x000fe40005f61270 */
/*08a0*/ IADD3 R9, R8, 0x1, RZ ; /* 0x0000000108097810 */
/* 0x000fe20007ffe0ff */
/*08b0*/ @!P1 IMAD.MOV R9, RZ, RZ, R8 ; /* 0x000000ffff099224 */
/* 0x000fe200078e0208 */
/*08c0*/ ISETP.GT.AND P1, PT, R16, 0xc, PT ; /* 0x0000000c1000780c */
/* 0x000fe40003f24270 */
/*08d0*/ ISETP.LT.OR P2, PT, R11, R4, P3 ; /* 0x000000040b00720c */
/* 0x000fe40001f41670 */
/*08e0*/ IADD3 R2, P3, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x000fe40007f7e0ff */
/*08f0*/ IADD3 R8, R9, 0x1, RZ ; /* 0x0000000109087810 */
/* 0x000fc60007ffe0ff */
/*0900*/ IMAD.X R3, RZ, RZ, R3, P3 ; /* 0x000000ffff037224 */
/* 0x000fcc00018e0603 */
/*0910*/ @!P2 IMAD.MOV R8, RZ, RZ, R9 ; /* 0x000000ffff08a224 */
/* 0x000fe200078e0209 */
/*0920*/ @P1 BRA 0x1e0 ; /* 0xfffff8b000001947 */
/* 0x000fea000383ffff */
/*0930*/ ISETP.GT.AND P1, PT, R16, 0x4, PT ; /* 0x000000041000780c */
/* 0x000fda0003f24270 */
/*0940*/ @!P1 BRA 0xd10 ; /* 0x000003c000009947 */
/* 0x000fea0003800000 */
/*0950*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea8000c1e1900 */
/*0960*/ LDG.E R13, [R2.64+0x4] ; /* 0x00000404020d7981 */
/* 0x000ee8000c1e1900 */
/*0970*/ LDG.E R15, [R2.64+0x8] ; /* 0x00000804020f7981 */
/* 0x000f28000c1e1900 */
/*0980*/ LDG.E R17, [R2.64+0xc] ; /* 0x00000c0402117981 */
/* 0x000f28000c1e1900 */
/*0990*/ LDG.E R19, [R2.64+0x10] ; /* 0x0000100402137981 */
/* 0x000f28000c1e1900 */
/*09a0*/ LDG.E R21, [R2.64+0x14] ; /* 0x0000140402157981 */
/* 0x000f28000c1e1900 */
/*09b0*/ LDG.E R23, [R2.64+0x18] ; /* 0x0000180402177981 */
/* 0x000f28000c1e1900 */
/*09c0*/ LDG.E R9, [R2.64+0x1c] ; /* 0x00001c0402097981 */
/* 0x000f22000c1e1900 */
/*09d0*/ IADD3 R10, R8, 0x1, RZ ; /* 0x00000001080a7810 */
/* 0x000fc40007ffe0ff */
/*09e0*/ IADD3 R16, R16, -0x8, RZ ; /* 0xfffffff810107810 */
/* 0x000fe40007ffe0ff */
/*09f0*/ ISETP.NE.AND P1, PT, R4, R11, PT ; /* 0x0000000b0400720c */
/* 0x024fc80003f25270 */
/*0a00*/ ISETP.LT.AND P1, PT, R7, R0, !P1 ; /* 0x000000000700720c */
/* 0x000fe40004f21270 */
/*0a10*/ ISETP.NE.AND P0, PT, R4.reuse, R13, PT ; /* 0x0000000d0400720c */
/* 0x048fe40003f05270 */
/*0a20*/ ISETP.LT.OR P1, PT, R11, R4, P1 ; /* 0x000000040b00720c */
/* 0x000fe40000f21670 */
/*0a30*/ IADD3 R11, R7, 0x1, RZ ; /* 0x00000001070b7810 */
/* 0x000fe40007ffe0ff */
/*0a40*/ ISETP.NE.AND P2, PT, R4, R15, PT ; /* 0x0000000f0400720c */
/* 0x010fe40003f45270 */
/*0a50*/ ISETP.LT.AND P0, PT, R11, R0, !P0 ; /* 0x000000000b00720c */
/* 0x000fc40004701270 */
/*0a60*/ IADD3 R11, R7, 0x2, RZ ; /* 0x00000002070b7810 */
/* 0x000fe40007ffe0ff */
/*0a70*/ ISETP.LT.OR P0, PT, R13, R4, P0 ; /* 0x000000040d00720c */
/* 0x000fe40000701670 */
/*0a80*/ ISETP.LT.AND P2, PT, R11, R0, !P2 ; /* 0x000000000b00720c */
/* 0x000fe20005741270 */
/*0a90*/ @!P1 IMAD.MOV R10, RZ, RZ, R8 ; /* 0x000000ffff0a9224 */
/* 0x000fe200078e0208 */
/*0aa0*/ IADD3 R11, R7, 0x3, RZ ; /* 0x00000003070b7810 */
/* 0x000fe40007ffe0ff */
/*0ab0*/ ISETP.LT.OR P1, PT, R15, R4, P2 ; /* 0x000000040f00720c */
/* 0x000fe40001721670 */
/*0ac0*/ ISETP.NE.AND P2, PT, R4, R17, PT ; /* 0x000000110400720c */
/* 0x000fc40003f45270 */
/*0ad0*/ IADD3 R8, R10, 0x1, RZ ; /* 0x000000010a087810 */
/* 0x000fe40007ffe0ff */
/*0ae0*/ ISETP.LT.AND P2, PT, R11, R0, !P2 ; /* 0x000000000b00720c */
/* 0x000fe20005741270 */
/*0af0*/ @!P0 IMAD.MOV R8, RZ, RZ, R10 ; /* 0x000000ffff088224 */
/* 0x000fe200078e020a */
/*0b00*/ IADD3 R11, R7, 0x4, RZ ; /* 0x00000004070b7810 */
/* 0x000fe40007ffe0ff */
/*0b10*/ ISETP.NE.AND P0, PT, R4, R19, PT ; /* 0x000000130400720c */
/* 0x000fe40003f05270 */
/*0b20*/ ISETP.LT.OR P2, PT, R17, R4, P2 ; /* 0x000000041100720c */
/* 0x000fe40001741670 */
/*0b30*/ ISETP.LT.AND P0, PT, R11, R0, !P0 ; /* 0x000000000b00720c */
/* 0x000fc40004701270 */
/*0b40*/ IADD3 R10, R8, 0x1, RZ ; /* 0x00000001080a7810 */
/* 0x000fe20007ffe0ff */
/*0b50*/ @!P1 IMAD.MOV R10, RZ, RZ, R8 ; /* 0x000000ffff0a9224 */
/* 0x000fe200078e0208 */
/*0b60*/ ISETP.LT.OR P0, PT, R19, R4, P0 ; /* 0x000000041300720c */
/* 0x000fe40000701670 */
/*0b70*/ IADD3 R11, R7, 0x5, RZ ; /* 0x00000005070b7810 */
/* 0x000fe40007ffe0ff */
/*0b80*/ ISETP.NE.AND P1, PT, R4, R21, PT ; /* 0x000000150400720c */
/* 0x000fe40003f25270 */
/*0b90*/ IADD3 R8, R10, 0x1, RZ ; /* 0x000000010a087810 */
/* 0x000fe20007ffe0ff */
/*0ba0*/ @!P2 IMAD.MOV R8, RZ, RZ, R10 ; /* 0x000000ffff08a224 */
/* 0x000fe200078e020a */
/*0bb0*/ ISETP.LT.AND P1, PT, R11, R0, !P1 ; /* 0x000000000b00720c */
/* 0x000fc40004f21270 */
/*0bc0*/ IADD3 R11, R7, 0x6, RZ ; /* 0x00000006070b7810 */
/* 0x000fe40007ffe0ff */
/*0bd0*/ ISETP.NE.AND P2, PT, R4, R23, PT ; /* 0x000000170400720c */
/* 0x000fe40003f45270 */
/*0be0*/ ISETP.LT.OR P1, PT, R21, R4, P1 ; /* 0x000000041500720c */
/* 0x000fe40000f21670 */
/*0bf0*/ ISETP.LT.AND P2, PT, R11, R0, !P2 ; /* 0x000000000b00720c */
/* 0x000fe40005741270 */
/*0c00*/ IADD3 R10, R8, 0x1, RZ ; /* 0x00000001080a7810 */
/* 0x000fe20007ffe0ff */
/*0c10*/ @!P0 IMAD.MOV R10, RZ, RZ, R8 ; /* 0x000000ffff0a8224 */
/* 0x000fe200078e0208 */
/*0c20*/ ISETP.LT.OR P0, PT, R23, R4, P2 ; /* 0x000000041700720c */
/* 0x000fc40001701670 */
/*0c30*/ IADD3 R11, R7, 0x7, RZ ; /* 0x00000007070b7810 */
/* 0x000fe40007ffe0ff */
/*0c40*/ ISETP.NE.AND P2, PT, R4, R9, PT ; /* 0x000000090400720c */
/* 0x000fe40003f45270 */
/*0c50*/ IADD3 R8, R10, 0x1, RZ ; /* 0x000000010a087810 */
/* 0x000fe20007ffe0ff */
/*0c60*/ @!P1 IMAD.MOV R8, RZ, RZ, R10 ; /* 0x000000ffff089224 */
/* 0x000fe200078e020a */
/*0c70*/ ISETP.LT.AND P2, PT, R11, R0, !P2 ; /* 0x000000000b00720c */
/* 0x000fe40005741270 */
/*0c80*/ IADD3 R2, P1, R2, 0x20, RZ ; /* 0x0000002002027810 */
/* 0x000fe40007f3e0ff */
/*0c90*/ ISETP.LT.OR P2, PT, R9, R4, P2 ; /* 0x000000040900720c */
/* 0x000fc40001741670 */
/*0ca0*/ IADD3 R9, R8, 0x1, RZ ; /* 0x0000000108097810 */
/* 0x000fe20007ffe0ff */
/*0cb0*/ @!P0 IMAD.MOV R9, RZ, RZ, R8 ; /* 0x000000ffff098224 */
/* 0x000fe200078e0208 */
/*0cc0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0cd0*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fe200008e0603 */
/*0ce0*/ IADD3 R7, R7, 0x8, RZ ; /* 0x0000000807077810 */
/* 0x000fe40007ffe0ff */
/*0cf0*/ IADD3 R8, R9, 0x1, RZ ; /* 0x0000000109087810 */
/* 0x000fca0007ffe0ff */
/*0d00*/ @!P2 IMAD.MOV R8, RZ, RZ, R9 ; /* 0x000000ffff08a224 */
/* 0x000fe400078e0209 */
/*0d10*/ ISETP.NE.OR P0, PT, R16, RZ, P0 ; /* 0x000000ff1000720c */
/* 0x000fda0000705670 */
/*0d20*/ @!P0 BRA 0xf40 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*0d30*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea8000c1e1900 */
/*0d40*/ LDG.E R11, [R2.64+0x4] ; /* 0x00000404020b7981 */
/* 0x000ee8000c1e1900 */
/*0d50*/ LDG.E R13, [R2.64+0x8] ; /* 0x00000804020d7981 */
/* 0x000f28000c1e1900 */
/*0d60*/ LDG.E R15, [R2.64+0xc] ; /* 0x00000c04020f7981 */
/* 0x000f22000c1e1900 */
/*0d70*/ IADD3 R17, R7, 0x2, RZ ; /* 0x0000000207117810 */
/* 0x000fc40007ffe0ff */
/*0d80*/ IADD3 R16, R16, -0x4, RZ ; /* 0xfffffffc10107810 */
/* 0x000fe40007ffe0ff */
/*0d90*/ ISETP.NE.AND P1, PT, R4, R9, PT ; /* 0x000000090400720c */
/* 0x024fc80003f25270 */
/*0da0*/ ISETP.LT.AND P1, PT, R7, R0, !P1 ; /* 0x000000000700720c */
/* 0x000fe40004f21270 */
/*0db0*/ ISETP.NE.AND P0, PT, R4.reuse, R11, PT ; /* 0x0000000b0400720c */
/* 0x048fe40003f05270 */
/*0dc0*/ ISETP.LT.OR P1, PT, R9, R4, P1 ; /* 0x000000040900720c */
/* 0x000fe40000f21670 */
/*0dd0*/ IADD3 R9, R7, 0x1, RZ ; /* 0x0000000107097810 */
/* 0x000fe40007ffe0ff */
/*0de0*/ ISETP.NE.AND P2, PT, R4, R13, PT ; /* 0x0000000d0400720c */
/* 0x010fe40003f45270 */
/*0df0*/ ISETP.LT.AND P0, PT, R9, R0, !P0 ; /* 0x000000000900720c */
/* 0x000fc40004701270 */
/*0e00*/ ISETP.LT.AND P2, PT, R17, R0, !P2 ; /* 0x000000001100720c */
/* 0x000fe40005741270 */
/*0e10*/ ISETP.LT.OR P0, PT, R11, R4.reuse, P0 ; /* 0x000000040b00720c */
/* 0x080fe40000701670 */
/*0e20*/ IADD3 R9, R8, 0x1, RZ ; /* 0x0000000108097810 */
/* 0x000fe20007ffe0ff */
/*0e30*/ @!P1 IMAD.MOV R9, RZ, RZ, R8 ; /* 0x000000ffff099224 */
/* 0x000fe200078e0208 */
/*0e40*/ ISETP.LT.OR P1, PT, R13, R4, P2 ; /* 0x000000040d00720c */
/* 0x000fe40001721670 */
/*0e50*/ IADD3 R11, R7, 0x3, RZ ; /* 0x00000003070b7810 */
/* 0x000fe40007ffe0ff */
/*0e60*/ ISETP.NE.AND P2, PT, R4, R15, PT ; /* 0x0000000f0400720c */
/* 0x000fc40003f45270 */
/*0e70*/ IADD3 R8, R9, 0x1, RZ ; /* 0x0000000109087810 */
/* 0x000fe40007ffe0ff */
/*0e80*/ ISETP.LT.AND P2, PT, R11, R0, !P2 ; /* 0x000000000b00720c */
/* 0x000fe20005741270 */
/*0e90*/ @!P0 IMAD.MOV R8, RZ, RZ, R9 ; /* 0x000000ffff088224 */
/* 0x000fe200078e0209 */
/*0ea0*/ ISETP.NE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe40003f05270 */
/*0eb0*/ ISETP.LT.OR P2, PT, R15, R4, P2 ; /* 0x000000040f00720c */
/* 0x000fe40001741670 */
/*0ec0*/ IADD3 R9, R8, 0x1, RZ ; /* 0x0000000108097810 */
/* 0x000fe20007ffe0ff */
/*0ed0*/ @!P1 IMAD.MOV R9, RZ, RZ, R8 ; /* 0x000000ffff099224 */
/* 0x000fe200078e0208 */
/*0ee0*/ IADD3 R2, P1, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fc40007f3e0ff */
/*0ef0*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fe40007ffe0ff */
/*0f00*/ IADD3 R8, R9, 0x1, RZ ; /* 0x0000000109087810 */
/* 0x000fe20007ffe0ff */
/*0f10*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fc800008e0603 */
/*0f20*/ @!P2 IMAD.MOV R8, RZ, RZ, R9 ; /* 0x000000ffff08a224 */
/* 0x000fe200078e0209 */
/*0f30*/ @P0 BRA 0xd30 ; /* 0xfffffdf000000947 */
/* 0x000fea000383ffff */
/*0f40*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0f50*/ @!P0 BRA 0x1060 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0f60*/ IMAD.WIDE R2, R7, R5, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x000fc800078e0205 */
/*0f70*/ IMAD.MOV.U32 R11, RZ, RZ, R3 ; /* 0x000000ffff0b7224 */
/* 0x000fc800078e0003 */
/*0f80*/ IMAD.MOV.U32 R3, RZ, RZ, R11 ; /* 0x000000ffff037224 */
/* 0x000fcc00078e000b */
/*0f90*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x0000a2000c1e1900 */
/*0fa0*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*0fb0*/ IADD3 R9, R8, 0x1, RZ ; /* 0x0000000108097810 */
/* 0x000fe40007ffe0ff */
/*0fc0*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f25270 */
/*0fd0*/ IADD3 R2, P2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fca0007f5e0ff */
/*0fe0*/ IMAD.X R11, RZ, RZ, R11, P2 ; /* 0x000000ffff0b7224 */
/* 0x000fe200010e060b */
/*0ff0*/ ISETP.NE.AND P0, PT, R4, R3, PT ; /* 0x000000030400720c */
/* 0x024fc80003f05270 */
/*1000*/ ISETP.LT.AND P0, PT, R7.reuse, R0, !P0 ; /* 0x000000000700720c */
/* 0x040fe40004701270 */
/*1010*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe40007ffe0ff */
/*1020*/ ISETP.LT.OR P0, PT, R3, R4, P0 ; /* 0x000000040300720c */
/* 0x000fda0000701670 */
/*1030*/ @!P0 IMAD.MOV R9, RZ, RZ, R8 ; /* 0x000000ffff098224 */
/* 0x000fc800078e0208 */
/*1040*/ IMAD.MOV.U32 R8, RZ, RZ, R9 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0009 */
/*1050*/ @P1 BRA 0xf80 ; /* 0xffffff2000001947 */
/* 0x000fea000383ffff */
/*1060*/ IMAD.WIDE R8, R8, R5, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fca00078e0205 */
/*1070*/ STG.E [R8.64], R4 ; /* 0x0000000408007986 */
/* 0x020fe2000c101904 */
/*1080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1090*/ BRA 0x1090; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void counting_sort(int* array, int *temp, int size) {
int i, j, count;
i = threadIdx.x + (blockIdx.x * blockDim.x);
if (i < size) {
count = 0;
for(j = 0; j < size; j++) {
if(array[j] < array[i]) {
count++;
} else if(array[i] == array[j] && j < i) {
count++;
}
}
temp[count] = array[i];
}
} | .file "tmpxft_000376a7_00000000-6_counting_sort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z13counting_sortPiS_iPiS_i
.type _Z36__device_stub__Z13counting_sortPiS_iPiS_i, @function
_Z36__device_stub__Z13counting_sortPiS_iPiS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13counting_sortPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z13counting_sortPiS_iPiS_i, .-_Z36__device_stub__Z13counting_sortPiS_iPiS_i
.globl _Z13counting_sortPiS_i
.type _Z13counting_sortPiS_i, @function
_Z13counting_sortPiS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13counting_sortPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13counting_sortPiS_i, .-_Z13counting_sortPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13counting_sortPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13counting_sortPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void counting_sort(int* array, int *temp, int size) {
int i, j, count;
i = threadIdx.x + (blockIdx.x * blockDim.x);
if (i < size) {
count = 0;
for(j = 0; j < size; j++) {
if(array[j] < array[i]) {
count++;
} else if(array[i] == array[j] && j < i) {
count++;
}
}
temp[count] = array[i];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void counting_sort(int* array, int *temp, int size) {
int i, j, count;
i = threadIdx.x + (blockIdx.x * blockDim.x);
if (i < size) {
count = 0;
for(j = 0; j < size; j++) {
if(array[j] < array[i]) {
count++;
} else if(array[i] == array[j] && j < i) {
count++;
}
}
temp[count] = array[i];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void counting_sort(int* array, int *temp, int size) {
int i, j, count;
i = threadIdx.x + (blockIdx.x * blockDim.x);
if (i < size) {
count = 0;
for(j = 0; j < size; j++) {
if(array[j] < array[i]) {
count++;
} else if(array[i] == array[j] && j < i) {
count++;
}
}
temp[count] = array[i];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13counting_sortPiS_i
.globl _Z13counting_sortPiS_i
.p2align 8
.type _Z13counting_sortPiS_i,@function
_Z13counting_sortPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_7
s_load_b64 s[4:5], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
s_mov_b64 s[6:7], s[4:5]
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v0, v[3:4], off
v_mov_b32_e32 v3, 0
.LBB0_3:
s_load_b32 s3, s[6:7], 0x0
v_cmp_lt_i32_e32 vcc_lo, s9, v1
s_add_i32 s9, s9, 1
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_eq_u32_e64 s2, s3, v0
v_cmp_lt_i32_e64 s3, s3, v0
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_or_b32 vcc_lo, s3, s2
s_add_u32 s6, s6, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_addc_u32 s7, s7, 0
s_cmp_lg_u32 s8, s9
s_cbranch_scc1 .LBB0_3
v_mov_b32_e32 v4, 0
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
.LBB0_6:
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[0:1], off
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13counting_sortPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13counting_sortPiS_i, .Lfunc_end0-_Z13counting_sortPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13counting_sortPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13counting_sortPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void counting_sort(int* array, int *temp, int size) {
int i, j, count;
i = threadIdx.x + (blockIdx.x * blockDim.x);
if (i < size) {
count = 0;
for(j = 0; j < size; j++) {
if(array[j] < array[i]) {
count++;
} else if(array[i] == array[j] && j < i) {
count++;
}
}
temp[count] = array[i];
}
} | .text
.file "counting_sort.hip"
.globl _Z28__device_stub__counting_sortPiS_i # -- Begin function _Z28__device_stub__counting_sortPiS_i
.p2align 4, 0x90
.type _Z28__device_stub__counting_sortPiS_i,@function
_Z28__device_stub__counting_sortPiS_i: # @_Z28__device_stub__counting_sortPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13counting_sortPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__counting_sortPiS_i, .Lfunc_end0-_Z28__device_stub__counting_sortPiS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13counting_sortPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13counting_sortPiS_i,@object # @_Z13counting_sortPiS_i
.section .rodata,"a",@progbits
.globl _Z13counting_sortPiS_i
.p2align 3, 0x0
_Z13counting_sortPiS_i:
.quad _Z28__device_stub__counting_sortPiS_i
.size _Z13counting_sortPiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13counting_sortPiS_i"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__counting_sortPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13counting_sortPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13counting_sortPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc600078e00ff */
/*0090*/ ISETP.GE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe20003f06270 */
/*00a0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0205 */
/*00b0*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000162000c1e1900 */
/*00c0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fcc00078e00ff */
/*00d0*/ @!P0 BRA 0x1060 ; /* 0x00000f8000008947 */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R2, R6.reuse, -0x1, RZ ; /* 0xffffffff06027810 */
/* 0x041fe20007ffe0ff */
/*00f0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe200078e00ff */
/*0100*/ LOP3.LUT R6, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306067812 */
/* 0x000fe200078ec0ff */
/*0110*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0130*/ @!P0 BRA 0xf40 ; /* 0x00000e0000008947 */
/* 0x000fea0003800000 */
/*0140*/ IADD3 R16, -R6, c[0x0][0x170], RZ ; /* 0x00005c0006107a10 */
/* 0x000fe20007ffe1ff */
/*0150*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe400078e00ff */
/*0160*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0170*/ ISETP.GT.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe20003f04270 */
/*0180*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fd800078e00ff */
/*0190*/ @!P0 BRA 0xd30 ; /* 0x00000b9000008947 */
/* 0x000fea0003800000 */
/*01a0*/ ISETP.GT.AND P1, PT, R16, 0xc, PT ; /* 0x0000000c1000780c */
/* 0x000fe40003f24270 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01c0*/ @!P1 BRA 0x930 ; /* 0x0000076000009947 */
/* 0x000fea0003800000 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01e0*/ LDG.E R14, [R2.64] ; /* 0x00000004020e7981 */
/* 0x000ea8000c1e1900 */
/*01f0*/ LDG.E R18, [R2.64+0x4] ; /* 0x0000040402127981 */
/* 0x000ee8000c1e1900 */
/*0200*/ LDG.E R20, [R2.64+0x8] ; /* 0x0000080402147981 */
/* 0x000f28000c1e1900 */
/*0210*/ LDG.E R12, [R2.64+0xc] ; /* 0x00000c04020c7981 */
/* 0x000f28000c1e1900 */
/*0220*/ LDG.E R10, [R2.64+0x10] ; /* 0x00001004020a7981 */
/* 0x000f28000c1e1900 */
/*0230*/ LDG.E R27, [R2.64+0x14] ; /* 0x00001404021b7981 */
/* 0x000f28000c1e1900 */
/*0240*/ LDG.E R29, [R2.64+0x18] ; /* 0x00001804021d7981 */
/* 0x000f28000c1e1900 */
/*0250*/ LDG.E R23, [R2.64+0x1c] ; /* 0x00001c0402177981 */
/* 0x000f28000c1e1900 */
/*0260*/ LDG.E R25, [R2.64+0x20] ; /* 0x0000200402197981 */
/* 0x000f28000c1e1900 */
/*0270*/ LDG.E R19, [R2.64+0x24] ; /* 0x0000240402137981 */
/* 0x000f28000c1e1900 */
/*0280*/ LDG.E R21, [R2.64+0x28] ; /* 0x0000280402157981 */
/* 0x000f28000c1e1900 */
/*0290*/ LDG.E R15, [R2.64+0x2c] ; /* 0x00002c04020f7981 */
/* 0x000f28000c1e1900 */
/*02a0*/ LDG.E R17, [R2.64+0x30] ; /* 0x0000300402117981 */
/* 0x000f28000c1e1900 */
/*02b0*/ LDG.E R9, [R2.64+0x34] ; /* 0x0000340402097981 */
/* 0x000f28000c1e1900 */
/*02c0*/ LDG.E R13, [R2.64+0x38] ; /* 0x00003804020d7981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R11, [R2.64+0x3c] ; /* 0x00003c04020b7981 */
/* 0x000f22000c1e1900 */
/*02e0*/ IADD3 R22, R7, 0x2, RZ ; /* 0x0000000207167810 */
/* 0x000fc40007ffe0ff */
/*02f0*/ IADD3 R16, R16, -0x10, RZ ; /* 0xfffffff010107810 */
/* 0x000fe40007ffe0ff */
/*0300*/ ISETP.NE.AND P1, PT, R4, R14, PT ; /* 0x0000000e0400720c */
/* 0x024fc80003f25270 */
/*0310*/ ISETP.LT.AND P1, PT, R7.reuse, R0, !P1 ; /* 0x000000000700720c */
/* 0x040fe40004f21270 */
/*0320*/ ISETP.NE.AND P2, PT, R4, R18, PT ; /* 0x000000120400720c */
/* 0x008fe40003f45270 */
/*0330*/ ISETP.LT.OR P1, PT, R14, R4, P1 ; /* 0x000000040e00720c */
/* 0x000fe40000f21670 */
/*0340*/ IADD3 R14, R7, 0x1, RZ ; /* 0x00000001070e7810 */
/* 0x000fe40007ffe0ff */
/*0350*/ ISETP.NE.AND P3, PT, R4, R20, PT ; /* 0x000000140400720c */
/* 0x010fe40003f65270 */
/*0360*/ ISETP.LT.AND P2, PT, R14, R0, !P2 ; /* 0x000000000e00720c */
/* 0x000fc40005741270 */
/*0370*/ ISETP.LT.AND P3, PT, R22, R0, !P3 ; /* 0x000000001600720c */
/* 0x000fe40005f61270 */
/*0380*/ ISETP.LT.OR P2, PT, R18, R4.reuse, P2 ; /* 0x000000041200720c */
/* 0x080fe40001741670 */
/*0390*/ IADD3 R14, R8, 0x1, RZ ; /* 0x00000001080e7810 */
/* 0x000fe20007ffe0ff */
/*03a0*/ @!P1 IMAD.MOV R14, RZ, RZ, R8 ; /* 0x000000ffff0e9224 */
/* 0x000fe200078e0208 */
/*03b0*/ ISETP.LT.OR P1, PT, R20, R4, P3 ; /* 0x000000041400720c */
/* 0x000fe40001f21670 */
/*03c0*/ IADD3 R8, R7, 0x3, RZ ; /* 0x0000000307087810 */
/* 0x000fe40007ffe0ff */
/*03d0*/ ISETP.NE.AND P3, PT, R4, R12, PT ; /* 0x0000000c0400720c */
/* 0x000fc40003f65270 */
/*03e0*/ IADD3 R18, R14, 0x1, RZ ; /* 0x000000010e127810 */
/* 0x000fe40007ffe0ff */
/*03f0*/ ISETP.LT.AND P3, PT, R8, R0, !P3 ; /* 0x000000000800720c */
/* 0x000fe20005f61270 */
/*0400*/ @!P2 IMAD.MOV R18, RZ, RZ, R14 ; /* 0x000000ffff12a224 */
/* 0x000fe200078e020e */
/*0410*/ IADD3 R8, R7, 0x4, RZ ; /* 0x0000000407087810 */
/* 0x000fe40007ffe0ff */
/*0420*/ ISETP.LT.OR P3, PT, R12, R4, P3 ; /* 0x000000040c00720c */
/* 0x000fe40001f61670 */
/*0430*/ ISETP.NE.AND P2, PT, R4, R10, PT ; /* 0x0000000a0400720c */
/* 0x000fe40003f45270 */
/*0440*/ IADD3 R12, R18, 0x1, RZ ; /* 0x00000001120c7810 */
/* 0x000fe20007ffe0ff */
/*0450*/ @!P1 IMAD.MOV R12, RZ, RZ, R18 ; /* 0x000000ffff0c9224 */
/* 0x000fe200078e0212 */
/*0460*/ ISETP.LT.AND P2, PT, R8, R0, !P2 ; /* 0x000000000800720c */
/* 0x000fc40005741270 */
/*0470*/ IADD3 R8, R7.reuse, 0x5, RZ ; /* 0x0000000507087810 */
/* 0x040fe40007ffe0ff */
/*0480*/ ISETP.LT.OR P1, PT, R10, R4, P2 ; /* 0x000000040a00720c */
/* 0x000fe40001721670 */
/*0490*/ ISETP.NE.AND P2, PT, R4, R27, PT ; /* 0x0000001b0400720c */
/* 0x000fe40003f45270 */
/*04a0*/ IADD3 R10, R12, 0x1, RZ ; /* 0x000000010c0a7810 */
/* 0x000fe20007ffe0ff */
/*04b0*/ @!P3 IMAD.MOV R10, RZ, RZ, R12 ; /* 0x000000ffff0ab224 */
/* 0x000fe200078e020c */
/*04c0*/ ISETP.LT.AND P3, PT, R8, R0, !P2 ; /* 0x000000000800720c */
/* 0x000fe40005761270 */
/*04d0*/ IADD3 R8, R7, 0x6, RZ ; /* 0x0000000607087810 */
/* 0x000fc40007ffe0ff */
/*04e0*/ ISETP.NE.AND P2, PT, R4, R29, PT ; /* 0x0000001d0400720c */
/* 0x000fe40003f45270 */
/*04f0*/ ISETP.LT.OR P3, PT, R27, R4, P3 ; /* 0x000000041b00720c */
/* 0x000fe40001f61670 */
/*0500*/ ISETP.LT.AND P2, PT, R8, R0, !P2 ; /* 0x000000000800720c */
/* 0x000fe40005741270 */
/*0510*/ IADD3 R12, R10, 0x1, RZ ; /* 0x000000010a0c7810 */
/* 0x000fe20007ffe0ff */
/*0520*/ @!P1 IMAD.MOV R12, RZ, RZ, R10 ; /* 0x000000ffff0c9224 */
/* 0x000fe200078e020a */
/*0530*/ ISETP.LT.OR P1, PT, R29, R4, P2 ; /* 0x000000041d00720c */
/* 0x000fe40001721670 */
/*0540*/ IADD3 R27, R7, 0x7, RZ ; /* 0x00000007071b7810 */
/* 0x000fc40007ffe0ff */
/*0550*/ ISETP.NE.AND P2, PT, R4, R23, PT ; /* 0x000000170400720c */
/* 0x000fe40003f45270 */
/*0560*/ IADD3 R8, R12, 0x1, RZ ; /* 0x000000010c087810 */
/* 0x000fe20007ffe0ff */
/*0570*/ @!P3 IMAD.MOV R8, RZ, RZ, R12 ; /* 0x000000ffff08b224 */
/* 0x000fe200078e020c */
/*0580*/ ISETP.LT.AND P2, PT, R27, R0, !P2 ; /* 0x000000001b00720c */
/* 0x000fe40005741270 */
/*0590*/ IADD3 R27, R7, 0x8, RZ ; /* 0x00000008071b7810 */
/* 0x000fe40007ffe0ff */
/*05a0*/ ISETP.NE.AND P3, PT, R4, R25, PT ; /* 0x000000190400720c */
/* 0x000fe40003f65270 */
/*05b0*/ ISETP.LT.OR P2, PT, R23, R4, P2 ; /* 0x000000041700720c */
/* 0x000fc40001741670 */
/*05c0*/ ISETP.LT.AND P3, PT, R27, R0, !P3 ; /* 0x000000001b00720c */
/* 0x000fe40005f61270 */
/*05d0*/ IADD3 R10, R8, 0x1, RZ ; /* 0x00000001080a7810 */
/* 0x000fe20007ffe0ff */
/*05e0*/ @!P1 IMAD.MOV R10, RZ, RZ, R8 ; /* 0x000000ffff0a9224 */
/* 0x000fe200078e0208 */
/*05f0*/ ISETP.LT.OR P1, PT, R25, R4, P3 ; /* 0x000000041900720c */
/* 0x000fe40001f21670 */
/*0600*/ IADD3 R23, R7, 0x9, RZ ; /* 0x0000000907177810 */
/* 0x000fe40007ffe0ff */
/*0610*/ ISETP.NE.AND P3, PT, R4, R19, PT ; /* 0x000000130400720c */
/* 0x000fe40003f65270 */
/*0620*/ IADD3 R8, R10, 0x1, RZ ; /* 0x000000010a087810 */
/* 0x000fe20007ffe0ff */
/*0630*/ @!P2 IMAD.MOV R8, RZ, RZ, R10 ; /* 0x000000ffff08a224 */
/* 0x000fe200078e020a */
/*0640*/ ISETP.LT.AND P3, PT, R23, R0, !P3 ; /* 0x000000001700720c */
/* 0x000fc40005f61270 */
/*0650*/ IADD3 R23, R7, 0xa, RZ ; /* 0x0000000a07177810 */
/* 0x000fe40007ffe0ff */
/*0660*/ ISETP.NE.AND P2, PT, R4, R21, PT ; /* 0x000000150400720c */
/* 0x000fe40003f45270 */
/*0670*/ ISETP.LT.OR P3, PT, R19, R4, P3 ; /* 0x000000041300720c */
/* 0x000fe40001f61670 */
/*0680*/ ISETP.LT.AND P2, PT, R23, R0, !P2 ; /* 0x000000001700720c */
/* 0x000fe40005741270 */
/*0690*/ IADD3 R10, R8, 0x1, RZ ; /* 0x00000001080a7810 */
/* 0x000fe20007ffe0ff */
/*06a0*/ @!P1 IMAD.MOV R10, RZ, RZ, R8 ; /* 0x000000ffff0a9224 */
/* 0x000fe200078e0208 */
/*06b0*/ ISETP.LT.OR P1, PT, R21, R4, P2 ; /* 0x000000041500720c */
/* 0x000fc40001721670 */
/*06c0*/ IADD3 R19, R7, 0xb, RZ ; /* 0x0000000b07137810 */
/* 0x000fe40007ffe0ff */
/*06d0*/ ISETP.NE.AND P2, PT, R4, R15, PT ; /* 0x0000000f0400720c */
/* 0x000fe40003f45270 */
/*06e0*/ IADD3 R8, R10, 0x1, RZ ; /* 0x000000010a087810 */
/* 0x000fe20007ffe0ff */
/*06f0*/ @!P3 IMAD.MOV R8, RZ, RZ, R10 ; /* 0x000000ffff08b224 */
/* 0x000fe200078e020a */
/*0700*/ ISETP.LT.AND P2, PT, R19, R0, !P2 ; /* 0x000000001300720c */
/* 0x000fe40005741270 */
/*0710*/ IADD3 R19, R7, 0xc, RZ ; /* 0x0000000c07137810 */
/* 0x000fe40007ffe0ff */
/*0720*/ ISETP.LT.OR P2, PT, R15, R4, P2 ; /* 0x000000040f00720c */
/* 0x000fc40001741670 */
/*0730*/ ISETP.NE.AND P3, PT, R4, R17, PT ; /* 0x000000110400720c */
/* 0x000fe40003f65270 */
/*0740*/ IADD3 R10, R8, 0x1, RZ ; /* 0x00000001080a7810 */
/* 0x000fe20007ffe0ff */
/*0750*/ @!P1 IMAD.MOV R10, RZ, RZ, R8 ; /* 0x000000ffff0a9224 */
/* 0x000fe200078e0208 */
/*0760*/ ISETP.LT.AND P3, PT, R19, R0, !P3 ; /* 0x000000001300720c */
/* 0x000fe40005f61270 */
/*0770*/ IADD3 R15, R7, 0xd, RZ ; /* 0x0000000d070f7810 */
/* 0x000fe40007ffe0ff */
/*0780*/ ISETP.LT.OR P1, PT, R17, R4, P3 ; /* 0x000000041100720c */
/* 0x000fe40001f21670 */
/*0790*/ ISETP.NE.AND P3, PT, R4, R9, PT ; /* 0x000000090400720c */
/* 0x000fc40003f65270 */
/*07a0*/ IADD3 R8, R10, 0x1, RZ ; /* 0x000000010a087810 */
/* 0x000fe20007ffe0ff */
/*07b0*/ @!P2 IMAD.MOV R8, RZ, RZ, R10 ; /* 0x000000ffff08a224 */
/* 0x000fe200078e020a */
/*07c0*/ ISETP.LT.AND P2, PT, R15, R0, !P3 ; /* 0x000000000f00720c */
/* 0x000fe40005f41270 */
/*07d0*/ IADD3 R15, R7, 0xe, RZ ; /* 0x0000000e070f7810 */
/* 0x000fe40007ffe0ff */
/*07e0*/ ISETP.NE.AND P3, PT, R4, R13, PT ; /* 0x0000000d0400720c */
/* 0x000fe40003f65270 */
/*07f0*/ ISETP.LT.OR P2, PT, R9, R4, P2 ; /* 0x000000040900720c */
/* 0x000fe40001741670 */
/*0800*/ ISETP.LT.AND P3, PT, R15, R0, !P3 ; /* 0x000000000f00720c */
/* 0x000fc40005f61270 */
/*0810*/ IADD3 R10, R8, 0x1, RZ ; /* 0x00000001080a7810 */
/* 0x000fe20007ffe0ff */
/*0820*/ @!P1 IMAD.MOV R10, RZ, RZ, R8 ; /* 0x000000ffff0a9224 */
/* 0x000fe200078e0208 */
/*0830*/ ISETP.LT.OR P1, PT, R13, R4, P3 ; /* 0x000000040d00720c */
/* 0x000fe40001f21670 */
/*0840*/ IADD3 R9, R7.reuse, 0xf, RZ ; /* 0x0000000f07097810 */
/* 0x040fe40007ffe0ff */
/*0850*/ IADD3 R8, R10, 0x1, RZ ; /* 0x000000010a087810 */
/* 0x000fe40007ffe0ff */
/*0860*/ ISETP.NE.AND P3, PT, R4, R11, PT ; /* 0x0000000b0400720c */
/* 0x000fe20003f65270 */
/*0870*/ @!P2 IMAD.MOV R8, RZ, RZ, R10 ; /* 0x000000ffff08a224 */
/* 0x000fe200078e020a */
/*0880*/ IADD3 R7, R7, 0x10, RZ ; /* 0x0000001007077810 */
/* 0x000fc40007ffe0ff */
/*0890*/ ISETP.LT.AND P3, PT, R9, R0, !P3 ; /* 0x000000000900720c */
/* 0x000fe40005f61270 */
/*08a0*/ IADD3 R9, R8, 0x1, RZ ; /* 0x0000000108097810 */
/* 0x000fe20007ffe0ff */
/*08b0*/ @!P1 IMAD.MOV R9, RZ, RZ, R8 ; /* 0x000000ffff099224 */
/* 0x000fe200078e0208 */
/*08c0*/ ISETP.GT.AND P1, PT, R16, 0xc, PT ; /* 0x0000000c1000780c */
/* 0x000fe40003f24270 */
/*08d0*/ ISETP.LT.OR P2, PT, R11, R4, P3 ; /* 0x000000040b00720c */
/* 0x000fe40001f41670 */
/*08e0*/ IADD3 R2, P3, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x000fe40007f7e0ff */
/*08f0*/ IADD3 R8, R9, 0x1, RZ ; /* 0x0000000109087810 */
/* 0x000fc60007ffe0ff */
/*0900*/ IMAD.X R3, RZ, RZ, R3, P3 ; /* 0x000000ffff037224 */
/* 0x000fcc00018e0603 */
/*0910*/ @!P2 IMAD.MOV R8, RZ, RZ, R9 ; /* 0x000000ffff08a224 */
/* 0x000fe200078e0209 */
/*0920*/ @P1 BRA 0x1e0 ; /* 0xfffff8b000001947 */
/* 0x000fea000383ffff */
/*0930*/ ISETP.GT.AND P1, PT, R16, 0x4, PT ; /* 0x000000041000780c */
/* 0x000fda0003f24270 */
/*0940*/ @!P1 BRA 0xd10 ; /* 0x000003c000009947 */
/* 0x000fea0003800000 */
/*0950*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea8000c1e1900 */
/*0960*/ LDG.E R13, [R2.64+0x4] ; /* 0x00000404020d7981 */
/* 0x000ee8000c1e1900 */
/*0970*/ LDG.E R15, [R2.64+0x8] ; /* 0x00000804020f7981 */
/* 0x000f28000c1e1900 */
/*0980*/ LDG.E R17, [R2.64+0xc] ; /* 0x00000c0402117981 */
/* 0x000f28000c1e1900 */
/*0990*/ LDG.E R19, [R2.64+0x10] ; /* 0x0000100402137981 */
/* 0x000f28000c1e1900 */
/*09a0*/ LDG.E R21, [R2.64+0x14] ; /* 0x0000140402157981 */
/* 0x000f28000c1e1900 */
/*09b0*/ LDG.E R23, [R2.64+0x18] ; /* 0x0000180402177981 */
/* 0x000f28000c1e1900 */
/*09c0*/ LDG.E R9, [R2.64+0x1c] ; /* 0x00001c0402097981 */
/* 0x000f22000c1e1900 */
/*09d0*/ IADD3 R10, R8, 0x1, RZ ; /* 0x00000001080a7810 */
/* 0x000fc40007ffe0ff */
/*09e0*/ IADD3 R16, R16, -0x8, RZ ; /* 0xfffffff810107810 */
/* 0x000fe40007ffe0ff */
/*09f0*/ ISETP.NE.AND P1, PT, R4, R11, PT ; /* 0x0000000b0400720c */
/* 0x024fc80003f25270 */
/*0a00*/ ISETP.LT.AND P1, PT, R7, R0, !P1 ; /* 0x000000000700720c */
/* 0x000fe40004f21270 */
/*0a10*/ ISETP.NE.AND P0, PT, R4.reuse, R13, PT ; /* 0x0000000d0400720c */
/* 0x048fe40003f05270 */
/*0a20*/ ISETP.LT.OR P1, PT, R11, R4, P1 ; /* 0x000000040b00720c */
/* 0x000fe40000f21670 */
/*0a30*/ IADD3 R11, R7, 0x1, RZ ; /* 0x00000001070b7810 */
/* 0x000fe40007ffe0ff */
/*0a40*/ ISETP.NE.AND P2, PT, R4, R15, PT ; /* 0x0000000f0400720c */
/* 0x010fe40003f45270 */
/*0a50*/ ISETP.LT.AND P0, PT, R11, R0, !P0 ; /* 0x000000000b00720c */
/* 0x000fc40004701270 */
/*0a60*/ IADD3 R11, R7, 0x2, RZ ; /* 0x00000002070b7810 */
/* 0x000fe40007ffe0ff */
/*0a70*/ ISETP.LT.OR P0, PT, R13, R4, P0 ; /* 0x000000040d00720c */
/* 0x000fe40000701670 */
/*0a80*/ ISETP.LT.AND P2, PT, R11, R0, !P2 ; /* 0x000000000b00720c */
/* 0x000fe20005741270 */
/*0a90*/ @!P1 IMAD.MOV R10, RZ, RZ, R8 ; /* 0x000000ffff0a9224 */
/* 0x000fe200078e0208 */
/*0aa0*/ IADD3 R11, R7, 0x3, RZ ; /* 0x00000003070b7810 */
/* 0x000fe40007ffe0ff */
/*0ab0*/ ISETP.LT.OR P1, PT, R15, R4, P2 ; /* 0x000000040f00720c */
/* 0x000fe40001721670 */
/*0ac0*/ ISETP.NE.AND P2, PT, R4, R17, PT ; /* 0x000000110400720c */
/* 0x000fc40003f45270 */
/*0ad0*/ IADD3 R8, R10, 0x1, RZ ; /* 0x000000010a087810 */
/* 0x000fe40007ffe0ff */
/*0ae0*/ ISETP.LT.AND P2, PT, R11, R0, !P2 ; /* 0x000000000b00720c */
/* 0x000fe20005741270 */
/*0af0*/ @!P0 IMAD.MOV R8, RZ, RZ, R10 ; /* 0x000000ffff088224 */
/* 0x000fe200078e020a */
/*0b00*/ IADD3 R11, R7, 0x4, RZ ; /* 0x00000004070b7810 */
/* 0x000fe40007ffe0ff */
/*0b10*/ ISETP.NE.AND P0, PT, R4, R19, PT ; /* 0x000000130400720c */
/* 0x000fe40003f05270 */
/*0b20*/ ISETP.LT.OR P2, PT, R17, R4, P2 ; /* 0x000000041100720c */
/* 0x000fe40001741670 */
/*0b30*/ ISETP.LT.AND P0, PT, R11, R0, !P0 ; /* 0x000000000b00720c */
/* 0x000fc40004701270 */
/*0b40*/ IADD3 R10, R8, 0x1, RZ ; /* 0x00000001080a7810 */
/* 0x000fe20007ffe0ff */
/*0b50*/ @!P1 IMAD.MOV R10, RZ, RZ, R8 ; /* 0x000000ffff0a9224 */
/* 0x000fe200078e0208 */
/*0b60*/ ISETP.LT.OR P0, PT, R19, R4, P0 ; /* 0x000000041300720c */
/* 0x000fe40000701670 */
/*0b70*/ IADD3 R11, R7, 0x5, RZ ; /* 0x00000005070b7810 */
/* 0x000fe40007ffe0ff */
/*0b80*/ ISETP.NE.AND P1, PT, R4, R21, PT ; /* 0x000000150400720c */
/* 0x000fe40003f25270 */
/*0b90*/ IADD3 R8, R10, 0x1, RZ ; /* 0x000000010a087810 */
/* 0x000fe20007ffe0ff */
/*0ba0*/ @!P2 IMAD.MOV R8, RZ, RZ, R10 ; /* 0x000000ffff08a224 */
/* 0x000fe200078e020a */
/*0bb0*/ ISETP.LT.AND P1, PT, R11, R0, !P1 ; /* 0x000000000b00720c */
/* 0x000fc40004f21270 */
/*0bc0*/ IADD3 R11, R7, 0x6, RZ ; /* 0x00000006070b7810 */
/* 0x000fe40007ffe0ff */
/*0bd0*/ ISETP.NE.AND P2, PT, R4, R23, PT ; /* 0x000000170400720c */
/* 0x000fe40003f45270 */
/*0be0*/ ISETP.LT.OR P1, PT, R21, R4, P1 ; /* 0x000000041500720c */
/* 0x000fe40000f21670 */
/*0bf0*/ ISETP.LT.AND P2, PT, R11, R0, !P2 ; /* 0x000000000b00720c */
/* 0x000fe40005741270 */
/*0c00*/ IADD3 R10, R8, 0x1, RZ ; /* 0x00000001080a7810 */
/* 0x000fe20007ffe0ff */
/*0c10*/ @!P0 IMAD.MOV R10, RZ, RZ, R8 ; /* 0x000000ffff0a8224 */
/* 0x000fe200078e0208 */
/*0c20*/ ISETP.LT.OR P0, PT, R23, R4, P2 ; /* 0x000000041700720c */
/* 0x000fc40001701670 */
/*0c30*/ IADD3 R11, R7, 0x7, RZ ; /* 0x00000007070b7810 */
/* 0x000fe40007ffe0ff */
/*0c40*/ ISETP.NE.AND P2, PT, R4, R9, PT ; /* 0x000000090400720c */
/* 0x000fe40003f45270 */
/*0c50*/ IADD3 R8, R10, 0x1, RZ ; /* 0x000000010a087810 */
/* 0x000fe20007ffe0ff */
/*0c60*/ @!P1 IMAD.MOV R8, RZ, RZ, R10 ; /* 0x000000ffff089224 */
/* 0x000fe200078e020a */
/*0c70*/ ISETP.LT.AND P2, PT, R11, R0, !P2 ; /* 0x000000000b00720c */
/* 0x000fe40005741270 */
/*0c80*/ IADD3 R2, P1, R2, 0x20, RZ ; /* 0x0000002002027810 */
/* 0x000fe40007f3e0ff */
/*0c90*/ ISETP.LT.OR P2, PT, R9, R4, P2 ; /* 0x000000040900720c */
/* 0x000fc40001741670 */
/*0ca0*/ IADD3 R9, R8, 0x1, RZ ; /* 0x0000000108097810 */
/* 0x000fe20007ffe0ff */
/*0cb0*/ @!P0 IMAD.MOV R9, RZ, RZ, R8 ; /* 0x000000ffff098224 */
/* 0x000fe200078e0208 */
/*0cc0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0cd0*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fe200008e0603 */
/*0ce0*/ IADD3 R7, R7, 0x8, RZ ; /* 0x0000000807077810 */
/* 0x000fe40007ffe0ff */
/*0cf0*/ IADD3 R8, R9, 0x1, RZ ; /* 0x0000000109087810 */
/* 0x000fca0007ffe0ff */
/*0d00*/ @!P2 IMAD.MOV R8, RZ, RZ, R9 ; /* 0x000000ffff08a224 */
/* 0x000fe400078e0209 */
/*0d10*/ ISETP.NE.OR P0, PT, R16, RZ, P0 ; /* 0x000000ff1000720c */
/* 0x000fda0000705670 */
/*0d20*/ @!P0 BRA 0xf40 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*0d30*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea8000c1e1900 */
/*0d40*/ LDG.E R11, [R2.64+0x4] ; /* 0x00000404020b7981 */
/* 0x000ee8000c1e1900 */
/*0d50*/ LDG.E R13, [R2.64+0x8] ; /* 0x00000804020d7981 */
/* 0x000f28000c1e1900 */
/*0d60*/ LDG.E R15, [R2.64+0xc] ; /* 0x00000c04020f7981 */
/* 0x000f22000c1e1900 */
/*0d70*/ IADD3 R17, R7, 0x2, RZ ; /* 0x0000000207117810 */
/* 0x000fc40007ffe0ff */
/*0d80*/ IADD3 R16, R16, -0x4, RZ ; /* 0xfffffffc10107810 */
/* 0x000fe40007ffe0ff */
/*0d90*/ ISETP.NE.AND P1, PT, R4, R9, PT ; /* 0x000000090400720c */
/* 0x024fc80003f25270 */
/*0da0*/ ISETP.LT.AND P1, PT, R7, R0, !P1 ; /* 0x000000000700720c */
/* 0x000fe40004f21270 */
/*0db0*/ ISETP.NE.AND P0, PT, R4.reuse, R11, PT ; /* 0x0000000b0400720c */
/* 0x048fe40003f05270 */
/*0dc0*/ ISETP.LT.OR P1, PT, R9, R4, P1 ; /* 0x000000040900720c */
/* 0x000fe40000f21670 */
/*0dd0*/ IADD3 R9, R7, 0x1, RZ ; /* 0x0000000107097810 */
/* 0x000fe40007ffe0ff */
/*0de0*/ ISETP.NE.AND P2, PT, R4, R13, PT ; /* 0x0000000d0400720c */
/* 0x010fe40003f45270 */
/*0df0*/ ISETP.LT.AND P0, PT, R9, R0, !P0 ; /* 0x000000000900720c */
/* 0x000fc40004701270 */
/*0e00*/ ISETP.LT.AND P2, PT, R17, R0, !P2 ; /* 0x000000001100720c */
/* 0x000fe40005741270 */
/*0e10*/ ISETP.LT.OR P0, PT, R11, R4.reuse, P0 ; /* 0x000000040b00720c */
/* 0x080fe40000701670 */
/*0e20*/ IADD3 R9, R8, 0x1, RZ ; /* 0x0000000108097810 */
/* 0x000fe20007ffe0ff */
/*0e30*/ @!P1 IMAD.MOV R9, RZ, RZ, R8 ; /* 0x000000ffff099224 */
/* 0x000fe200078e0208 */
/*0e40*/ ISETP.LT.OR P1, PT, R13, R4, P2 ; /* 0x000000040d00720c */
/* 0x000fe40001721670 */
/*0e50*/ IADD3 R11, R7, 0x3, RZ ; /* 0x00000003070b7810 */
/* 0x000fe40007ffe0ff */
/*0e60*/ ISETP.NE.AND P2, PT, R4, R15, PT ; /* 0x0000000f0400720c */
/* 0x000fc40003f45270 */
/*0e70*/ IADD3 R8, R9, 0x1, RZ ; /* 0x0000000109087810 */
/* 0x000fe40007ffe0ff */
/*0e80*/ ISETP.LT.AND P2, PT, R11, R0, !P2 ; /* 0x000000000b00720c */
/* 0x000fe20005741270 */
/*0e90*/ @!P0 IMAD.MOV R8, RZ, RZ, R9 ; /* 0x000000ffff088224 */
/* 0x000fe200078e0209 */
/*0ea0*/ ISETP.NE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe40003f05270 */
/*0eb0*/ ISETP.LT.OR P2, PT, R15, R4, P2 ; /* 0x000000040f00720c */
/* 0x000fe40001741670 */
/*0ec0*/ IADD3 R9, R8, 0x1, RZ ; /* 0x0000000108097810 */
/* 0x000fe20007ffe0ff */
/*0ed0*/ @!P1 IMAD.MOV R9, RZ, RZ, R8 ; /* 0x000000ffff099224 */
/* 0x000fe200078e0208 */
/*0ee0*/ IADD3 R2, P1, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fc40007f3e0ff */
/*0ef0*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fe40007ffe0ff */
/*0f00*/ IADD3 R8, R9, 0x1, RZ ; /* 0x0000000109087810 */
/* 0x000fe20007ffe0ff */
/*0f10*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fc800008e0603 */
/*0f20*/ @!P2 IMAD.MOV R8, RZ, RZ, R9 ; /* 0x000000ffff08a224 */
/* 0x000fe200078e0209 */
/*0f30*/ @P0 BRA 0xd30 ; /* 0xfffffdf000000947 */
/* 0x000fea000383ffff */
/*0f40*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0f50*/ @!P0 BRA 0x1060 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0f60*/ IMAD.WIDE R2, R7, R5, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x000fc800078e0205 */
/*0f70*/ IMAD.MOV.U32 R11, RZ, RZ, R3 ; /* 0x000000ffff0b7224 */
/* 0x000fc800078e0003 */
/*0f80*/ IMAD.MOV.U32 R3, RZ, RZ, R11 ; /* 0x000000ffff037224 */
/* 0x000fcc00078e000b */
/*0f90*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x0000a2000c1e1900 */
/*0fa0*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*0fb0*/ IADD3 R9, R8, 0x1, RZ ; /* 0x0000000108097810 */
/* 0x000fe40007ffe0ff */
/*0fc0*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f25270 */
/*0fd0*/ IADD3 R2, P2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fca0007f5e0ff */
/*0fe0*/ IMAD.X R11, RZ, RZ, R11, P2 ; /* 0x000000ffff0b7224 */
/* 0x000fe200010e060b */
/*0ff0*/ ISETP.NE.AND P0, PT, R4, R3, PT ; /* 0x000000030400720c */
/* 0x024fc80003f05270 */
/*1000*/ ISETP.LT.AND P0, PT, R7.reuse, R0, !P0 ; /* 0x000000000700720c */
/* 0x040fe40004701270 */
/*1010*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe40007ffe0ff */
/*1020*/ ISETP.LT.OR P0, PT, R3, R4, P0 ; /* 0x000000040300720c */
/* 0x000fda0000701670 */
/*1030*/ @!P0 IMAD.MOV R9, RZ, RZ, R8 ; /* 0x000000ffff098224 */
/* 0x000fc800078e0208 */
/*1040*/ IMAD.MOV.U32 R8, RZ, RZ, R9 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0009 */
/*1050*/ @P1 BRA 0xf80 ; /* 0xffffff2000001947 */
/* 0x000fea000383ffff */
/*1060*/ IMAD.WIDE R8, R8, R5, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fca00078e0205 */
/*1070*/ STG.E [R8.64], R4 ; /* 0x0000000408007986 */
/* 0x020fe2000c101904 */
/*1080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1090*/ BRA 0x1090; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13counting_sortPiS_i
.globl _Z13counting_sortPiS_i
.p2align 8
.type _Z13counting_sortPiS_i,@function
_Z13counting_sortPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_7
s_load_b64 s[4:5], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
s_mov_b64 s[6:7], s[4:5]
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v0, v[3:4], off
v_mov_b32_e32 v3, 0
.LBB0_3:
s_load_b32 s3, s[6:7], 0x0
v_cmp_lt_i32_e32 vcc_lo, s9, v1
s_add_i32 s9, s9, 1
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_eq_u32_e64 s2, s3, v0
v_cmp_lt_i32_e64 s3, s3, v0
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_or_b32 vcc_lo, s3, s2
s_add_u32 s6, s6, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_addc_u32 s7, s7, 0
s_cmp_lg_u32 s8, s9
s_cbranch_scc1 .LBB0_3
v_mov_b32_e32 v4, 0
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
.LBB0_6:
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[0:1], off
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13counting_sortPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13counting_sortPiS_i, .Lfunc_end0-_Z13counting_sortPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13counting_sortPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13counting_sortPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000376a7_00000000-6_counting_sort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z13counting_sortPiS_iPiS_i
.type _Z36__device_stub__Z13counting_sortPiS_iPiS_i, @function
_Z36__device_stub__Z13counting_sortPiS_iPiS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13counting_sortPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z13counting_sortPiS_iPiS_i, .-_Z36__device_stub__Z13counting_sortPiS_iPiS_i
.globl _Z13counting_sortPiS_i
.type _Z13counting_sortPiS_i, @function
_Z13counting_sortPiS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13counting_sortPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13counting_sortPiS_i, .-_Z13counting_sortPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13counting_sortPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13counting_sortPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "counting_sort.hip"
.globl _Z28__device_stub__counting_sortPiS_i # -- Begin function _Z28__device_stub__counting_sortPiS_i
.p2align 4, 0x90
.type _Z28__device_stub__counting_sortPiS_i,@function
_Z28__device_stub__counting_sortPiS_i: # @_Z28__device_stub__counting_sortPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13counting_sortPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__counting_sortPiS_i, .Lfunc_end0-_Z28__device_stub__counting_sortPiS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13counting_sortPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13counting_sortPiS_i,@object # @_Z13counting_sortPiS_i
.section .rodata,"a",@progbits
.globl _Z13counting_sortPiS_i
.p2align 3, 0x0
_Z13counting_sortPiS_i:
.quad _Z28__device_stub__counting_sortPiS_i
.size _Z13counting_sortPiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13counting_sortPiS_i"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__counting_sortPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13counting_sortPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // data-racer
#include <stdio.h>
#include <cuda.h>
#include <assert.h>
#define N 2
__global__ void foo(int *p, int *ptr_a) {
ptr_a = p + threadIdx.x;
// assert(*ptr_a == 2);
} | code for sm_80
Function : _Z3fooPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // data-racer
#include <stdio.h>
#include <cuda.h>
#include <assert.h>
#define N 2
__global__ void foo(int *p, int *ptr_a) {
ptr_a = p + threadIdx.x;
// assert(*ptr_a == 2);
} | .file "tmpxft_00194f2e_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3fooPiS_PiS_
.type _Z24__device_stub__Z3fooPiS_PiS_, @function
_Z24__device_stub__Z3fooPiS_PiS_:
.LFB2081:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3fooPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z24__device_stub__Z3fooPiS_PiS_, .-_Z24__device_stub__Z3fooPiS_PiS_
.globl _Z3fooPiS_
.type _Z3fooPiS_, @function
_Z3fooPiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3fooPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z3fooPiS_, .-_Z3fooPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3fooPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3fooPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // data-racer
#include <stdio.h>
#include <cuda.h>
#include <assert.h>
#define N 2
__global__ void foo(int *p, int *ptr_a) {
ptr_a = p + threadIdx.x;
// assert(*ptr_a == 2);
} | // data-racer
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <assert.h>
#define N 2
__global__ void foo(int *p, int *ptr_a) {
ptr_a = p + threadIdx.x;
// assert(*ptr_a == 2);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // data-racer
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <assert.h>
#define N 2
__global__ void foo(int *p, int *ptr_a) {
ptr_a = p + threadIdx.x;
// assert(*ptr_a == 2);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3fooPiS_
.globl _Z3fooPiS_
.p2align 8
.type _Z3fooPiS_,@function
_Z3fooPiS_:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3fooPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3fooPiS_, .Lfunc_end0-_Z3fooPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3fooPiS_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z3fooPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // data-racer
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <assert.h>
#define N 2
__global__ void foo(int *p, int *ptr_a) {
ptr_a = p + threadIdx.x;
// assert(*ptr_a == 2);
} | .text
.file "main.hip"
.globl _Z18__device_stub__fooPiS_ # -- Begin function _Z18__device_stub__fooPiS_
.p2align 4, 0x90
.type _Z18__device_stub__fooPiS_,@function
_Z18__device_stub__fooPiS_: # @_Z18__device_stub__fooPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3fooPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__fooPiS_, .Lfunc_end0-_Z18__device_stub__fooPiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3fooPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3fooPiS_,@object # @_Z3fooPiS_
.section .rodata,"a",@progbits
.globl _Z3fooPiS_
.p2align 3, 0x0
_Z3fooPiS_:
.quad _Z18__device_stub__fooPiS_
.size _Z3fooPiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3fooPiS_"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__fooPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3fooPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3fooPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3fooPiS_
.globl _Z3fooPiS_
.p2align 8
.type _Z3fooPiS_,@function
_Z3fooPiS_:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3fooPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3fooPiS_, .Lfunc_end0-_Z3fooPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3fooPiS_
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z3fooPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00194f2e_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3fooPiS_PiS_
.type _Z24__device_stub__Z3fooPiS_PiS_, @function
_Z24__device_stub__Z3fooPiS_PiS_:
.LFB2081:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3fooPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z24__device_stub__Z3fooPiS_PiS_, .-_Z24__device_stub__Z3fooPiS_PiS_
.globl _Z3fooPiS_
.type _Z3fooPiS_, @function
_Z3fooPiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3fooPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z3fooPiS_, .-_Z3fooPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3fooPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3fooPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z18__device_stub__fooPiS_ # -- Begin function _Z18__device_stub__fooPiS_
.p2align 4, 0x90
.type _Z18__device_stub__fooPiS_,@function
_Z18__device_stub__fooPiS_: # @_Z18__device_stub__fooPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3fooPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__fooPiS_, .Lfunc_end0-_Z18__device_stub__fooPiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3fooPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3fooPiS_,@object # @_Z3fooPiS_
.section .rodata,"a",@progbits
.globl _Z3fooPiS_
.p2align 3, 0x0
_Z3fooPiS_:
.quad _Z18__device_stub__fooPiS_
.size _Z3fooPiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3fooPiS_"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__fooPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3fooPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void transposeSmemDyn(float *out, float *in, int nx, int ny)
{
// dynamic shared memory
extern __shared__ float tile[];
// coordinate in original matrix
unsigned int ix, iy, ti, to;
ix = blockDim.x * blockIdx.x + threadIdx.x;
iy = blockDim.y * blockIdx.y + threadIdx.y;
// linear global memory index for original matrix
ti = iy * nx + ix;
// thread index in transposed block
unsigned int row_idx, col_idx, irow, icol;
row_idx = threadIdx.y * blockDim.x + threadIdx.x;
irow = row_idx / blockDim.y;
icol = row_idx % blockDim.y;
col_idx = icol * blockDim.x + irow;
// coordinate in transposed matrix
ix = blockDim.y * blockIdx.y + icol;
iy = blockDim.x * blockIdx.x + irow;
// linear global memory index for transposed matrix
to = iy * ny + ix;
// transpose with boundary test
if (ix < nx && iy < ny)
{
// load data from global memory to shared memory
tile[row_idx] = in[ti];
// thread synchronization
__syncthreads();
// store data to global memory from shared memory
out[to] = tile[col_idx];
}
} | code for sm_80
Function : _Z16transposeSmemDynPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ I2F.U32.RP R0, c[0x0][0x4] ; /* 0x0000010000007b06 */
/* 0x000e220000209000 */
/*0020*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e620000002100 */
/*0030*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x4], PT ; /* 0x00000100ff007a0c */
/* 0x000fc60003f45070 */
/*0040*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000e660000002200 */
/*0050*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e220000001000 */
/*0060*/ IMAD R6, R9, c[0x0][0x0], R10 ; /* 0x0000000009067a24 */
/* 0x002fe200078e020a */
/*0070*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*0080*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0090*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00a0*/ IADD3 R5, RZ, -R3, RZ ; /* 0x80000003ff057210 */
/* 0x002fca0007ffe0ff */
/*00b0*/ IMAD R5, R5, c[0x0][0x4], RZ ; /* 0x0000010005057a24 */
/* 0x000fc800078e02ff */
/*00c0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fe400078e0002 */
/*00d0*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002600 */
/*00e0*/ IMAD.HI.U32 R4, R3, R6, RZ ; /* 0x0000000603047227 */
/* 0x000fca00078e00ff */
/*00f0*/ IADD3 R3, -R4, RZ, RZ ; /* 0x000000ff04037210 */
/* 0x000fca0007ffe1ff */
/*0100*/ IMAD R0, R3, c[0x0][0x4], R6 ; /* 0x0000010003007a24 */
/* 0x000fe400078e0206 */
/*0110*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e660000002500 */
/*0120*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x4], PT ; /* 0x0000010000007a0c */
/* 0x000fda0003f06070 */
/*0130*/ @P0 IADD3 R0, R0, -c[0x0][0x4], RZ ; /* 0x8000010000000a10 */
/* 0x000fe40007ffe0ff */
/*0140*/ @P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104040810 */
/* 0x000fe40007ffe0ff */
/*0150*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x4], PT ; /* 0x0000010000007a0c */
/* 0x000fe20003f26070 */
/*0160*/ IMAD R0, R3, c[0x0][0x0], R10 ; /* 0x0000000003007a24 */
/* 0x002fd800078e020a */
/*0170*/ @P1 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104041810 */
/* 0x000fe40007ffe0ff */
/*0180*/ @!P2 LOP3.LUT R4, RZ, c[0x0][0x4], RZ, 0x33, !PT ; /* 0x00000100ff04aa12 */
/* 0x000fc800078e33ff */
/*0190*/ IADD3 R5, -R4, RZ, RZ ; /* 0x000000ff04057210 */
/* 0x000fe20007ffe1ff */
/*01a0*/ IMAD R8, R3, c[0x0][0x0], R4 ; /* 0x0000000003087a24 */
/* 0x000fe400078e0204 */
/*01b0*/ IMAD R3, R2, c[0x0][0x4], R9 ; /* 0x0000010002037a24 */
/* 0x001fe400078e0209 */
/*01c0*/ IMAD R5, R5, c[0x0][0x4], R6 ; /* 0x0000010005057a24 */
/* 0x000fc800078e0206 */
/*01d0*/ IMAD R7, R2, c[0x0][0x4], R5 ; /* 0x0000010002077a24 */
/* 0x000fca00078e0205 */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fc80003f06070 */
/*01f0*/ ISETP.GE.U32.OR P0, PT, R8, c[0x0][0x174], P0 ; /* 0x00005d0008007a0c */
/* 0x000fda0000706470 */
/*0200*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0210*/ MOV R10, 0x4 ; /* 0x00000004000a7802 */
/* 0x000fe20000000f00 */
/*0220*/ IMAD R3, R3, c[0x0][0x170], R0 ; /* 0x00005c0003037a24 */
/* 0x000fe200078e0200 */
/*0230*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0240*/ IMAD.WIDE.U32 R2, R3, R10, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fcc00078e000a */
/*0250*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IMAD R0, R5, c[0x0][0x0], R4 ; /* 0x0000000005007a24 */
/* 0x000fe400078e0204 */
/*0270*/ IMAD R4, R8, c[0x0][0x174], R7 ; /* 0x00005d0008047a24 */
/* 0x000fc800078e0207 */
/*0280*/ IMAD.WIDE.U32 R4, R4, R10, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e000a */
/*0290*/ STS [R6.X4], R3 ; /* 0x0000000306007388 */
/* 0x004fe80000004800 */
/*02a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02b0*/ LDS R9, [R0.X4] ; /* 0x0000000000097984 */
/* 0x000e280000004800 */
/*02c0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x001fe2000c101904 */
/*02d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02e0*/ BRA 0x2e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void transposeSmemDyn(float *out, float *in, int nx, int ny)
{
// dynamic shared memory
extern __shared__ float tile[];
// coordinate in original matrix
unsigned int ix, iy, ti, to;
ix = blockDim.x * blockIdx.x + threadIdx.x;
iy = blockDim.y * blockIdx.y + threadIdx.y;
// linear global memory index for original matrix
ti = iy * nx + ix;
// thread index in transposed block
unsigned int row_idx, col_idx, irow, icol;
row_idx = threadIdx.y * blockDim.x + threadIdx.x;
irow = row_idx / blockDim.y;
icol = row_idx % blockDim.y;
col_idx = icol * blockDim.x + irow;
// coordinate in transposed matrix
ix = blockDim.y * blockIdx.y + icol;
iy = blockDim.x * blockIdx.x + irow;
// linear global memory index for transposed matrix
to = iy * ny + ix;
// transpose with boundary test
if (ix < nx && iy < ny)
{
// load data from global memory to shared memory
tile[row_idx] = in[ti];
// thread synchronization
__syncthreads();
// store data to global memory from shared memory
out[to] = tile[col_idx];
}
} | .file "tmpxft_00025d33_00000000-6_transposeSmemDyn.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z16transposeSmemDynPfS_iiPfS_ii
.type _Z40__device_stub__Z16transposeSmemDynPfS_iiPfS_ii, @function
_Z40__device_stub__Z16transposeSmemDynPfS_iiPfS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16transposeSmemDynPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z16transposeSmemDynPfS_iiPfS_ii, .-_Z40__device_stub__Z16transposeSmemDynPfS_iiPfS_ii
.globl _Z16transposeSmemDynPfS_ii
.type _Z16transposeSmemDynPfS_ii, @function
_Z16transposeSmemDynPfS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z16transposeSmemDynPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16transposeSmemDynPfS_ii, .-_Z16transposeSmemDynPfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16transposeSmemDynPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16transposeSmemDynPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void transposeSmemDyn(float *out, float *in, int nx, int ny)
{
// dynamic shared memory
extern __shared__ float tile[];
// coordinate in original matrix
unsigned int ix, iy, ti, to;
ix = blockDim.x * blockIdx.x + threadIdx.x;
iy = blockDim.y * blockIdx.y + threadIdx.y;
// linear global memory index for original matrix
ti = iy * nx + ix;
// thread index in transposed block
unsigned int row_idx, col_idx, irow, icol;
row_idx = threadIdx.y * blockDim.x + threadIdx.x;
irow = row_idx / blockDim.y;
icol = row_idx % blockDim.y;
col_idx = icol * blockDim.x + irow;
// coordinate in transposed matrix
ix = blockDim.y * blockIdx.y + icol;
iy = blockDim.x * blockIdx.x + irow;
// linear global memory index for transposed matrix
to = iy * ny + ix;
// transpose with boundary test
if (ix < nx && iy < ny)
{
// load data from global memory to shared memory
tile[row_idx] = in[ti];
// thread synchronization
__syncthreads();
// store data to global memory from shared memory
out[to] = tile[col_idx];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void transposeSmemDyn(float *out, float *in, int nx, int ny)
{
// dynamic shared memory
extern __shared__ float tile[];
// coordinate in original matrix
unsigned int ix, iy, ti, to;
ix = blockDim.x * blockIdx.x + threadIdx.x;
iy = blockDim.y * blockIdx.y + threadIdx.y;
// linear global memory index for original matrix
ti = iy * nx + ix;
// thread index in transposed block
unsigned int row_idx, col_idx, irow, icol;
row_idx = threadIdx.y * blockDim.x + threadIdx.x;
irow = row_idx / blockDim.y;
icol = row_idx % blockDim.y;
col_idx = icol * blockDim.x + irow;
// coordinate in transposed matrix
ix = blockDim.y * blockIdx.y + icol;
iy = blockDim.x * blockIdx.x + irow;
// linear global memory index for transposed matrix
to = iy * ny + ix;
// transpose with boundary test
if (ix < nx && iy < ny)
{
// load data from global memory to shared memory
tile[row_idx] = in[ti];
// thread synchronization
__syncthreads();
// store data to global memory from shared memory
out[to] = tile[col_idx];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void transposeSmemDyn(float *out, float *in, int nx, int ny)
{
// dynamic shared memory
extern __shared__ float tile[];
// coordinate in original matrix
unsigned int ix, iy, ti, to;
ix = blockDim.x * blockIdx.x + threadIdx.x;
iy = blockDim.y * blockIdx.y + threadIdx.y;
// linear global memory index for original matrix
ti = iy * nx + ix;
// thread index in transposed block
unsigned int row_idx, col_idx, irow, icol;
row_idx = threadIdx.y * blockDim.x + threadIdx.x;
irow = row_idx / blockDim.y;
icol = row_idx % blockDim.y;
col_idx = icol * blockDim.x + irow;
// coordinate in transposed matrix
ix = blockDim.y * blockIdx.y + icol;
iy = blockDim.x * blockIdx.x + irow;
// linear global memory index for transposed matrix
to = iy * ny + ix;
// transpose with boundary test
if (ix < nx && iy < ny)
{
// load data from global memory to shared memory
tile[row_idx] = in[ti];
// thread synchronization
__syncthreads();
// store data to global memory from shared memory
out[to] = tile[col_idx];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16transposeSmemDynPfS_ii
.globl _Z16transposeSmemDynPfS_ii
.p2align 8
.type _Z16transposeSmemDynPfS_ii,@function
_Z16transposeSmemDynPfS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v3, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s6, s2, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s6
s_sub_i32 s3, 0, s6
s_mul_i32 s15, s15, s6
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_mul_lo_u32 v2, s3, v1
s_and_b32 s3, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s14, s14, s3
v_mul_hi_u32 v5, v1, v2
v_mad_u32_u24 v2, v4, s3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v1, v5
v_mul_hi_u32 v0, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v1, v0, s6
v_add_nc_u32_e32 v5, 1, v0
v_sub_nc_u32_e32 v1, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cmp_le_u32_e32 vcc_lo, s6, v1
v_subrev_nc_u32_e32 v6, s6, v1
v_cndmask_b32_e32 v0, v0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v5, 1, v0
v_cndmask_b32_e32 v1, v1, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s6, v1
v_cndmask_b32_e32 v0, v0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v0, s6
v_add_nc_u32_e32 v6, s14, v0
v_cmp_gt_u32_e64 s2, s5, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v2, v1
v_add_nc_u32_e32 v1, s15, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_gt_u32_e32 vcc_lo, s4, v1
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s6, s2
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v4, s15, v4
s_load_b128 s[8:11], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v7, v4, s4
v_mov_b32_e32 v4, 0
v_add3_u32 v3, s14, v3, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s10, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s11, v8, vcc_lo
global_load_b32 v9, v[7:8], off
v_mad_u64_u32 v[7:8], null, v5, s3, v[0:1]
v_lshl_add_u32 v0, v2, 2, 0
v_mad_u64_u32 v[2:3], null, v6, s5, v[1:2]
v_mov_b32_e32 v3, v4
s_delay_alu instid0(VALU_DEP_4)
v_lshl_add_u32 v1, v7, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v0, v9
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v5, v1
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v5, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16transposeSmemDynPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16transposeSmemDynPfS_ii, .Lfunc_end0-_Z16transposeSmemDynPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16transposeSmemDynPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16transposeSmemDynPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void transposeSmemDyn(float *out, float *in, int nx, int ny)
{
// dynamic shared memory
extern __shared__ float tile[];
// coordinate in original matrix
unsigned int ix, iy, ti, to;
ix = blockDim.x * blockIdx.x + threadIdx.x;
iy = blockDim.y * blockIdx.y + threadIdx.y;
// linear global memory index for original matrix
ti = iy * nx + ix;
// thread index in transposed block
unsigned int row_idx, col_idx, irow, icol;
row_idx = threadIdx.y * blockDim.x + threadIdx.x;
irow = row_idx / blockDim.y;
icol = row_idx % blockDim.y;
col_idx = icol * blockDim.x + irow;
// coordinate in transposed matrix
ix = blockDim.y * blockIdx.y + icol;
iy = blockDim.x * blockIdx.x + irow;
// linear global memory index for transposed matrix
to = iy * ny + ix;
// transpose with boundary test
if (ix < nx && iy < ny)
{
// load data from global memory to shared memory
tile[row_idx] = in[ti];
// thread synchronization
__syncthreads();
// store data to global memory from shared memory
out[to] = tile[col_idx];
}
} | .text
.file "transposeSmemDyn.hip"
.globl _Z31__device_stub__transposeSmemDynPfS_ii # -- Begin function _Z31__device_stub__transposeSmemDynPfS_ii
.p2align 4, 0x90
.type _Z31__device_stub__transposeSmemDynPfS_ii,@function
_Z31__device_stub__transposeSmemDynPfS_ii: # @_Z31__device_stub__transposeSmemDynPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16transposeSmemDynPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__transposeSmemDynPfS_ii, .Lfunc_end0-_Z31__device_stub__transposeSmemDynPfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16transposeSmemDynPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16transposeSmemDynPfS_ii,@object # @_Z16transposeSmemDynPfS_ii
.section .rodata,"a",@progbits
.globl _Z16transposeSmemDynPfS_ii
.p2align 3, 0x0
_Z16transposeSmemDynPfS_ii:
.quad _Z31__device_stub__transposeSmemDynPfS_ii
.size _Z16transposeSmemDynPfS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16transposeSmemDynPfS_ii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__transposeSmemDynPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16transposeSmemDynPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16transposeSmemDynPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ I2F.U32.RP R0, c[0x0][0x4] ; /* 0x0000010000007b06 */
/* 0x000e220000209000 */
/*0020*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e620000002100 */
/*0030*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x4], PT ; /* 0x00000100ff007a0c */
/* 0x000fc60003f45070 */
/*0040*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000e660000002200 */
/*0050*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e220000001000 */
/*0060*/ IMAD R6, R9, c[0x0][0x0], R10 ; /* 0x0000000009067a24 */
/* 0x002fe200078e020a */
/*0070*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*0080*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0090*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00a0*/ IADD3 R5, RZ, -R3, RZ ; /* 0x80000003ff057210 */
/* 0x002fca0007ffe0ff */
/*00b0*/ IMAD R5, R5, c[0x0][0x4], RZ ; /* 0x0000010005057a24 */
/* 0x000fc800078e02ff */
/*00c0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fe400078e0002 */
/*00d0*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002600 */
/*00e0*/ IMAD.HI.U32 R4, R3, R6, RZ ; /* 0x0000000603047227 */
/* 0x000fca00078e00ff */
/*00f0*/ IADD3 R3, -R4, RZ, RZ ; /* 0x000000ff04037210 */
/* 0x000fca0007ffe1ff */
/*0100*/ IMAD R0, R3, c[0x0][0x4], R6 ; /* 0x0000010003007a24 */
/* 0x000fe400078e0206 */
/*0110*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e660000002500 */
/*0120*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x4], PT ; /* 0x0000010000007a0c */
/* 0x000fda0003f06070 */
/*0130*/ @P0 IADD3 R0, R0, -c[0x0][0x4], RZ ; /* 0x8000010000000a10 */
/* 0x000fe40007ffe0ff */
/*0140*/ @P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104040810 */
/* 0x000fe40007ffe0ff */
/*0150*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x4], PT ; /* 0x0000010000007a0c */
/* 0x000fe20003f26070 */
/*0160*/ IMAD R0, R3, c[0x0][0x0], R10 ; /* 0x0000000003007a24 */
/* 0x002fd800078e020a */
/*0170*/ @P1 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104041810 */
/* 0x000fe40007ffe0ff */
/*0180*/ @!P2 LOP3.LUT R4, RZ, c[0x0][0x4], RZ, 0x33, !PT ; /* 0x00000100ff04aa12 */
/* 0x000fc800078e33ff */
/*0190*/ IADD3 R5, -R4, RZ, RZ ; /* 0x000000ff04057210 */
/* 0x000fe20007ffe1ff */
/*01a0*/ IMAD R8, R3, c[0x0][0x0], R4 ; /* 0x0000000003087a24 */
/* 0x000fe400078e0204 */
/*01b0*/ IMAD R3, R2, c[0x0][0x4], R9 ; /* 0x0000010002037a24 */
/* 0x001fe400078e0209 */
/*01c0*/ IMAD R5, R5, c[0x0][0x4], R6 ; /* 0x0000010005057a24 */
/* 0x000fc800078e0206 */
/*01d0*/ IMAD R7, R2, c[0x0][0x4], R5 ; /* 0x0000010002077a24 */
/* 0x000fca00078e0205 */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fc80003f06070 */
/*01f0*/ ISETP.GE.U32.OR P0, PT, R8, c[0x0][0x174], P0 ; /* 0x00005d0008007a0c */
/* 0x000fda0000706470 */
/*0200*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0210*/ MOV R10, 0x4 ; /* 0x00000004000a7802 */
/* 0x000fe20000000f00 */
/*0220*/ IMAD R3, R3, c[0x0][0x170], R0 ; /* 0x00005c0003037a24 */
/* 0x000fe200078e0200 */
/*0230*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0240*/ IMAD.WIDE.U32 R2, R3, R10, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fcc00078e000a */
/*0250*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IMAD R0, R5, c[0x0][0x0], R4 ; /* 0x0000000005007a24 */
/* 0x000fe400078e0204 */
/*0270*/ IMAD R4, R8, c[0x0][0x174], R7 ; /* 0x00005d0008047a24 */
/* 0x000fc800078e0207 */
/*0280*/ IMAD.WIDE.U32 R4, R4, R10, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e000a */
/*0290*/ STS [R6.X4], R3 ; /* 0x0000000306007388 */
/* 0x004fe80000004800 */
/*02a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02b0*/ LDS R9, [R0.X4] ; /* 0x0000000000097984 */
/* 0x000e280000004800 */
/*02c0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x001fe2000c101904 */
/*02d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02e0*/ BRA 0x2e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16transposeSmemDynPfS_ii
.globl _Z16transposeSmemDynPfS_ii
.p2align 8
.type _Z16transposeSmemDynPfS_ii,@function
_Z16transposeSmemDynPfS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v3, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s6, s2, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s6
s_sub_i32 s3, 0, s6
s_mul_i32 s15, s15, s6
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_mul_lo_u32 v2, s3, v1
s_and_b32 s3, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s14, s14, s3
v_mul_hi_u32 v5, v1, v2
v_mad_u32_u24 v2, v4, s3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v1, v5
v_mul_hi_u32 v0, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v1, v0, s6
v_add_nc_u32_e32 v5, 1, v0
v_sub_nc_u32_e32 v1, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cmp_le_u32_e32 vcc_lo, s6, v1
v_subrev_nc_u32_e32 v6, s6, v1
v_cndmask_b32_e32 v0, v0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v5, 1, v0
v_cndmask_b32_e32 v1, v1, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s6, v1
v_cndmask_b32_e32 v0, v0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v0, s6
v_add_nc_u32_e32 v6, s14, v0
v_cmp_gt_u32_e64 s2, s5, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, v2, v1
v_add_nc_u32_e32 v1, s15, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_gt_u32_e32 vcc_lo, s4, v1
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s6, s2
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v4, s15, v4
s_load_b128 s[8:11], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v7, v4, s4
v_mov_b32_e32 v4, 0
v_add3_u32 v3, s14, v3, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s10, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s11, v8, vcc_lo
global_load_b32 v9, v[7:8], off
v_mad_u64_u32 v[7:8], null, v5, s3, v[0:1]
v_lshl_add_u32 v0, v2, 2, 0
v_mad_u64_u32 v[2:3], null, v6, s5, v[1:2]
v_mov_b32_e32 v3, v4
s_delay_alu instid0(VALU_DEP_4)
v_lshl_add_u32 v1, v7, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v0, v9
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v5, v1
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v5, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16transposeSmemDynPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16transposeSmemDynPfS_ii, .Lfunc_end0-_Z16transposeSmemDynPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16transposeSmemDynPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16transposeSmemDynPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00025d33_00000000-6_transposeSmemDyn.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z16transposeSmemDynPfS_iiPfS_ii
.type _Z40__device_stub__Z16transposeSmemDynPfS_iiPfS_ii, @function
_Z40__device_stub__Z16transposeSmemDynPfS_iiPfS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16transposeSmemDynPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z16transposeSmemDynPfS_iiPfS_ii, .-_Z40__device_stub__Z16transposeSmemDynPfS_iiPfS_ii
.globl _Z16transposeSmemDynPfS_ii
.type _Z16transposeSmemDynPfS_ii, @function
_Z16transposeSmemDynPfS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z16transposeSmemDynPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16transposeSmemDynPfS_ii, .-_Z16transposeSmemDynPfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16transposeSmemDynPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16transposeSmemDynPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "transposeSmemDyn.hip"
.globl _Z31__device_stub__transposeSmemDynPfS_ii # -- Begin function _Z31__device_stub__transposeSmemDynPfS_ii
.p2align 4, 0x90
.type _Z31__device_stub__transposeSmemDynPfS_ii,@function
_Z31__device_stub__transposeSmemDynPfS_ii: # @_Z31__device_stub__transposeSmemDynPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16transposeSmemDynPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__transposeSmemDynPfS_ii, .Lfunc_end0-_Z31__device_stub__transposeSmemDynPfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16transposeSmemDynPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16transposeSmemDynPfS_ii,@object # @_Z16transposeSmemDynPfS_ii
.section .rodata,"a",@progbits
.globl _Z16transposeSmemDynPfS_ii
.p2align 3, 0x0
_Z16transposeSmemDynPfS_ii:
.quad _Z31__device_stub__transposeSmemDynPfS_ii
.size _Z16transposeSmemDynPfS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16transposeSmemDynPfS_ii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__transposeSmemDynPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16transposeSmemDynPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // CUDA programming
// Exercise n. 06
#include <errno.h>
#include <cuda.h>
#include <stdio.h>
#define BLOCKS 4
#define THREADS 4
// Prototype
__global__ void saxpy(float a, float *x, float *y, float *z, int N);
__host__ void ints(float *m, int N);
__host__ void print_saxpy(float a, float *x, float *y, float *z, int N);
int main(void)
{
float *x, *y, *z, a; // host copies of x, y, a
float *d_x, *d_y, *d_z; // device copies of x, y
int N = BLOCKS * THREADS;
int size = N * sizeof(float);
// Allocate space for host copies of x, y
x = (float *)malloc(size);
y = (float *)malloc(size);
z = (float *)malloc(size);
// Setup input values
ints(x, N);
ints(y, N);
a = 3.0/2.5;
// Allocate space for device copies of x, y
cudaMalloc((void **)&d_x, size);
cudaMalloc((void **)&d_y, size);
cudaMalloc((void **)&d_z, size);
// Copy inputs to device
cudaMemcpy(d_x, x, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, size, cudaMemcpyHostToDevice);
// Call the kernel on GPU
saxpy<<< BLOCKS, THREADS >>>(a, d_x, d_y, d_z, N);
// Copy result back to host
cudaMemcpy(z, d_z, size, cudaMemcpyDeviceToHost);
print_saxpy(a, x, y, z, N);
// Cleanup
free(x);
free(y);
free(z);
cudaFree(d_x);
cudaFree(d_y);
cudaFree(d_z);
return(EXIT_SUCCESS);
}
// Single-precision A*X Plus Y (on device)
__global__ void saxpy(float a, float *x, float *y, float *z, int N)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
// Avoid accessing beyond the end of the arrays
if(index < N)
{
z[index] = a * x[index] + y[index];
}
}
// Initialisation
__host__ void ints(float *m, int N)
{
int i;
for(i = 0; i < N; i++)
m[i] = i/(i + 1.0);
}
// Print the elements of the equation
__host__ void print_saxpy(float a, float *x, float *y, float *z, int N)
{
for(int i = 0; i < N; i++)
{
printf("%5.2f = %5.2f x %5.2f + %5.2f\n", z[i], a, x[i], y[i]);
}
printf("\n");
} | code for sm_80
Function : _Z5saxpyfPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x180], PT ; /* 0x0000600006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FFMA R9, R2, c[0x0][0x160], R5 ; /* 0x0000580002097a23 */
/* 0x004fca0000000005 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // CUDA programming
// Exercise n. 06
#include <errno.h>
#include <cuda.h>
#include <stdio.h>
#define BLOCKS 4
#define THREADS 4
// Prototype
__global__ void saxpy(float a, float *x, float *y, float *z, int N);
__host__ void ints(float *m, int N);
__host__ void print_saxpy(float a, float *x, float *y, float *z, int N);
int main(void)
{
float *x, *y, *z, a; // host copies of x, y, a
float *d_x, *d_y, *d_z; // device copies of x, y
int N = BLOCKS * THREADS;
int size = N * sizeof(float);
// Allocate space for host copies of x, y
x = (float *)malloc(size);
y = (float *)malloc(size);
z = (float *)malloc(size);
// Setup input values
ints(x, N);
ints(y, N);
a = 3.0/2.5;
// Allocate space for device copies of x, y
cudaMalloc((void **)&d_x, size);
cudaMalloc((void **)&d_y, size);
cudaMalloc((void **)&d_z, size);
// Copy inputs to device
cudaMemcpy(d_x, x, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, size, cudaMemcpyHostToDevice);
// Call the kernel on GPU
saxpy<<< BLOCKS, THREADS >>>(a, d_x, d_y, d_z, N);
// Copy result back to host
cudaMemcpy(z, d_z, size, cudaMemcpyDeviceToHost);
print_saxpy(a, x, y, z, N);
// Cleanup
free(x);
free(y);
free(z);
cudaFree(d_x);
cudaFree(d_y);
cudaFree(d_z);
return(EXIT_SUCCESS);
}
// Single-precision A*X Plus Y (on device)
__global__ void saxpy(float a, float *x, float *y, float *z, int N)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
// Avoid accessing beyond the end of the arrays
if(index < N)
{
z[index] = a * x[index] + y[index];
}
}
// Initialisation
__host__ void ints(float *m, int N)
{
int i;
for(i = 0; i < N; i++)
m[i] = i/(i + 1.0);
}
// Print the elements of the equation
__host__ void print_saxpy(float a, float *x, float *y, float *z, int N)
{
for(int i = 0; i < N; i++)
{
printf("%5.2f = %5.2f x %5.2f + %5.2f\n", z[i], a, x[i], y[i]);
}
printf("\n");
} | .file "tmpxft_0014329e_00000000-6_ex06.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4intsPfi
.type _Z4intsPfi, @function
_Z4intsPfi:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L3
movslq %esi, %rsi
movl $0, %eax
movsd .LC0(%rip), %xmm2
.L5:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movapd %xmm0, %xmm1
addsd %xmm2, %xmm1
divsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rdi,%rax,4)
addq $1, %rax
cmpq %rsi, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2058:
.size _Z4intsPfi, .-_Z4intsPfi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "%5.2f = %5.2f x %5.2f + %5.2f\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "\n"
.text
.globl _Z11print_saxpyfPfS_S_i
.type _Z11print_saxpyfPfS_S_i, @function
_Z11print_saxpyfPfS_S_i:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
testl %ecx, %ecx
jle .L8
movq %rdi, %r12
movq %rsi, %r13
movq %rdx, %r14
movslq %ecx, %rcx
leaq 0(,%rcx,4), %rbp
movl $0, %ebx
pxor %xmm4, %xmm4
cvtss2sd %xmm0, %xmm4
movsd %xmm4, 8(%rsp)
leaq .LC1(%rip), %r15
.L9:
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx), %xmm0
pxor %xmm3, %xmm3
cvtss2sd 0(%r13,%rbx), %xmm3
pxor %xmm2, %xmm2
cvtss2sd (%r12,%rbx), %xmm2
movsd 8(%rsp), %xmm1
movq %r15, %rsi
movl $2, %edi
movl $4, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L9
.L8:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z11print_saxpyfPfS_S_i, .-_Z11print_saxpyfPfS_S_i
.globl _Z30__device_stub__Z5saxpyfPfS_S_ifPfS_S_i
.type _Z30__device_stub__Z5saxpyfPfS_S_ifPfS_S_i, @function
_Z30__device_stub__Z5saxpyfPfS_S_ifPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movss %xmm0, 28(%rsp)
movq %rdi, 16(%rsp)
movq %rsi, 8(%rsp)
movq %rdx, (%rsp)
movl %ecx, 24(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5saxpyfPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z30__device_stub__Z5saxpyfPfS_S_ifPfS_S_i, .-_Z30__device_stub__Z5saxpyfPfS_S_ifPfS_S_i
.globl _Z5saxpyfPfS_S_i
.type _Z5saxpyfPfS_S_i, @function
_Z5saxpyfPfS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z5saxpyfPfS_S_ifPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z5saxpyfPfS_S_i, .-_Z5saxpyfPfS_S_i
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $64, %edi
call malloc@PLT
movq %rax, %rbp
movl $64, %edi
call malloc@PLT
movq %rax, %rbx
movl $64, %edi
call malloc@PLT
movq %rax, %r12
movl $16, %esi
movq %rbp, %rdi
call _Z4intsPfi
movl $16, %esi
movq %rbx, %rdi
call _Z4intsPfi
leaq 8(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $64, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $64, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 44(%rsp)
movl $1, 48(%rsp)
movl $4, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L21:
movl $2, %ecx
movl $64, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $16, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
movss .LC3(%rip), %xmm0
call _Z11print_saxpyfPfS_S_i
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl $16, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
movss .LC3(%rip), %xmm0
call _Z30__device_stub__Z5saxpyfPfS_S_ifPfS_S_i
jmp .L21
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z5saxpyfPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z5saxpyfPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1072693248
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1067030938
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // CUDA programming
// Exercise n. 06
#include <errno.h>
#include <cuda.h>
#include <stdio.h>
#define BLOCKS 4
#define THREADS 4
// Prototype
__global__ void saxpy(float a, float *x, float *y, float *z, int N);
__host__ void ints(float *m, int N);
__host__ void print_saxpy(float a, float *x, float *y, float *z, int N);
int main(void)
{
float *x, *y, *z, a; // host copies of x, y, a
float *d_x, *d_y, *d_z; // device copies of x, y
int N = BLOCKS * THREADS;
int size = N * sizeof(float);
// Allocate space for host copies of x, y
x = (float *)malloc(size);
y = (float *)malloc(size);
z = (float *)malloc(size);
// Setup input values
ints(x, N);
ints(y, N);
a = 3.0/2.5;
// Allocate space for device copies of x, y
cudaMalloc((void **)&d_x, size);
cudaMalloc((void **)&d_y, size);
cudaMalloc((void **)&d_z, size);
// Copy inputs to device
cudaMemcpy(d_x, x, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_y, y, size, cudaMemcpyHostToDevice);
// Call the kernel on GPU
saxpy<<< BLOCKS, THREADS >>>(a, d_x, d_y, d_z, N);
// Copy result back to host
cudaMemcpy(z, d_z, size, cudaMemcpyDeviceToHost);
print_saxpy(a, x, y, z, N);
// Cleanup
free(x);
free(y);
free(z);
cudaFree(d_x);
cudaFree(d_y);
cudaFree(d_z);
return(EXIT_SUCCESS);
}
// Single-precision A*X Plus Y (on device)
__global__ void saxpy(float a, float *x, float *y, float *z, int N)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
// Avoid accessing beyond the end of the arrays
if(index < N)
{
z[index] = a * x[index] + y[index];
}
}
// Initialisation
__host__ void ints(float *m, int N)
{
int i;
for(i = 0; i < N; i++)
m[i] = i/(i + 1.0);
}
// Print the elements of the equation
__host__ void print_saxpy(float a, float *x, float *y, float *z, int N)
{
for(int i = 0; i < N; i++)
{
printf("%5.2f = %5.2f x %5.2f + %5.2f\n", z[i], a, x[i], y[i]);
}
printf("\n");
} | // CUDA programming
// Exercise n. 06
#include <errno.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#define BLOCKS 4
#define THREADS 4
// Prototype
__global__ void saxpy(float a, float *x, float *y, float *z, int N);
__host__ void ints(float *m, int N);
__host__ void print_saxpy(float a, float *x, float *y, float *z, int N);
int main(void)
{
float *x, *y, *z, a; // host copies of x, y, a
float *d_x, *d_y, *d_z; // device copies of x, y
int N = BLOCKS * THREADS;
int size = N * sizeof(float);
// Allocate space for host copies of x, y
x = (float *)malloc(size);
y = (float *)malloc(size);
z = (float *)malloc(size);
// Setup input values
ints(x, N);
ints(y, N);
a = 3.0/2.5;
// Allocate space for device copies of x, y
hipMalloc((void **)&d_x, size);
hipMalloc((void **)&d_y, size);
hipMalloc((void **)&d_z, size);
// Copy inputs to device
hipMemcpy(d_x, x, size, hipMemcpyHostToDevice);
hipMemcpy(d_y, y, size, hipMemcpyHostToDevice);
// Call the kernel on GPU
saxpy<<< BLOCKS, THREADS >>>(a, d_x, d_y, d_z, N);
// Copy result back to host
hipMemcpy(z, d_z, size, hipMemcpyDeviceToHost);
print_saxpy(a, x, y, z, N);
// Cleanup
free(x);
free(y);
free(z);
hipFree(d_x);
hipFree(d_y);
hipFree(d_z);
return(EXIT_SUCCESS);
}
// Single-precision A*X Plus Y (on device)
__global__ void saxpy(float a, float *x, float *y, float *z, int N)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
// Avoid accessing beyond the end of the arrays
if(index < N)
{
z[index] = a * x[index] + y[index];
}
}
// Initialisation
__host__ void ints(float *m, int N)
{
int i;
for(i = 0; i < N; i++)
m[i] = i/(i + 1.0);
}
// Print the elements of the equation
__host__ void print_saxpy(float a, float *x, float *y, float *z, int N)
{
for(int i = 0; i < N; i++)
{
printf("%5.2f = %5.2f x %5.2f + %5.2f\n", z[i], a, x[i], y[i]);
}
printf("\n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // CUDA programming
// Exercise n. 06
#include <errno.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#define BLOCKS 4
#define THREADS 4
// Prototype
__global__ void saxpy(float a, float *x, float *y, float *z, int N);
__host__ void ints(float *m, int N);
__host__ void print_saxpy(float a, float *x, float *y, float *z, int N);
int main(void)
{
float *x, *y, *z, a; // host copies of x, y, a
float *d_x, *d_y, *d_z; // device copies of x, y
int N = BLOCKS * THREADS;
int size = N * sizeof(float);
// Allocate space for host copies of x, y
x = (float *)malloc(size);
y = (float *)malloc(size);
z = (float *)malloc(size);
// Setup input values
ints(x, N);
ints(y, N);
a = 3.0/2.5;
// Allocate space for device copies of x, y
hipMalloc((void **)&d_x, size);
hipMalloc((void **)&d_y, size);
hipMalloc((void **)&d_z, size);
// Copy inputs to device
hipMemcpy(d_x, x, size, hipMemcpyHostToDevice);
hipMemcpy(d_y, y, size, hipMemcpyHostToDevice);
// Call the kernel on GPU
saxpy<<< BLOCKS, THREADS >>>(a, d_x, d_y, d_z, N);
// Copy result back to host
hipMemcpy(z, d_z, size, hipMemcpyDeviceToHost);
print_saxpy(a, x, y, z, N);
// Cleanup
free(x);
free(y);
free(z);
hipFree(d_x);
hipFree(d_y);
hipFree(d_z);
return(EXIT_SUCCESS);
}
// Single-precision A*X Plus Y (on device)
__global__ void saxpy(float a, float *x, float *y, float *z, int N)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
// Avoid accessing beyond the end of the arrays
if(index < N)
{
z[index] = a * x[index] + y[index];
}
}
// Initialisation
__host__ void ints(float *m, int N)
{
int i;
for(i = 0; i < N; i++)
m[i] = i/(i + 1.0);
}
// Print the elements of the equation
__host__ void print_saxpy(float a, float *x, float *y, float *z, int N)
{
for(int i = 0; i < N; i++)
{
printf("%5.2f = %5.2f x %5.2f + %5.2f\n", z[i], a, x[i], y[i]);
}
printf("\n");
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5saxpyfPfS_S_i
.globl _Z5saxpyfPfS_S_i
.p2align 8
.type _Z5saxpyfPfS_S_i,@function
_Z5saxpyfPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
s_clause 0x1
s_load_b32 s2, s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, s2, v2
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5saxpyfPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5saxpyfPfS_S_i, .Lfunc_end0-_Z5saxpyfPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5saxpyfPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5saxpyfPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // CUDA programming
// Exercise n. 06
#include <errno.h>
#include <hip/hip_runtime.h>
#include <stdio.h>
#define BLOCKS 4
#define THREADS 4
// Prototype
__global__ void saxpy(float a, float *x, float *y, float *z, int N);
__host__ void ints(float *m, int N);
__host__ void print_saxpy(float a, float *x, float *y, float *z, int N);
int main(void)
{
float *x, *y, *z, a; // host copies of x, y, a
float *d_x, *d_y, *d_z; // device copies of x, y
int N = BLOCKS * THREADS;
int size = N * sizeof(float);
// Allocate space for host copies of x, y
x = (float *)malloc(size);
y = (float *)malloc(size);
z = (float *)malloc(size);
// Setup input values
ints(x, N);
ints(y, N);
a = 3.0/2.5;
// Allocate space for device copies of x, y
hipMalloc((void **)&d_x, size);
hipMalloc((void **)&d_y, size);
hipMalloc((void **)&d_z, size);
// Copy inputs to device
hipMemcpy(d_x, x, size, hipMemcpyHostToDevice);
hipMemcpy(d_y, y, size, hipMemcpyHostToDevice);
// Call the kernel on GPU
saxpy<<< BLOCKS, THREADS >>>(a, d_x, d_y, d_z, N);
// Copy result back to host
hipMemcpy(z, d_z, size, hipMemcpyDeviceToHost);
print_saxpy(a, x, y, z, N);
// Cleanup
free(x);
free(y);
free(z);
hipFree(d_x);
hipFree(d_y);
hipFree(d_z);
return(EXIT_SUCCESS);
}
// Single-precision A*X Plus Y (on device)
__global__ void saxpy(float a, float *x, float *y, float *z, int N)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
// Avoid accessing beyond the end of the arrays
if(index < N)
{
z[index] = a * x[index] + y[index];
}
}
// Initialisation
__host__ void ints(float *m, int N)
{
int i;
for(i = 0; i < N; i++)
m[i] = i/(i + 1.0);
}
// Print the elements of the equation
__host__ void print_saxpy(float a, float *x, float *y, float *z, int N)
{
for(int i = 0; i < N; i++)
{
printf("%5.2f = %5.2f x %5.2f + %5.2f\n", z[i], a, x[i], y[i]);
}
printf("\n");
} | .text
.file "ex06.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x3ff0000000000000 # double 1
.LCPI0_1:
.quad 0x3ff3333340000000 # double 1.2000000476837158
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $64, %edi
callq malloc
movq %rax, %rbx
movl $64, %edi
callq malloc
movq %rax, %r14
movl $64, %edi
callq malloc
movq %rax, %r15
xorl %eax, %eax
movsd .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB0_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
movapd %xmm1, %xmm2
addsd %xmm0, %xmm2
divsd %xmm2, %xmm1
cvtsd2ss %xmm1, %xmm1
movss %xmm1, (%rbx,%rax,4)
incq %rax
cmpq $16, %rax
jne .LBB0_1
# %bb.2: # %.lr.ph.i28.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_3: # %.lr.ph.i28
# =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
movapd %xmm1, %xmm2
addsd %xmm0, %xmm2
divsd %xmm2, %xmm1
cvtsd2ss %xmm1, %xmm1
movss %xmm1, (%r14,%rax,4)
incq %rax
cmpq $16, %rax
jne .LBB0_3
# %bb.4: # %_Z4intsPfi.exit32
leaq 24(%rsp), %rdi
movl $64, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $64, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq 24(%rsp), %rdi
movl $64, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $64, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967300, %rdi # imm = 0x100000004
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl $1067030938, 36(%rsp) # imm = 0x3F99999A
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $16, 32(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 104(%rsp), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z5saxpyfPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_6:
movq 8(%rsp), %rsi
movl $64, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_7: # =>This Inner Loop Header: Depth=1
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss (%rbx,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm2, %xmm2
cvtss2sd %xmm1, %xmm2
movss (%r14,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm3, %xmm3
cvtss2sd %xmm1, %xmm3
movl $.L.str, %edi
movsd .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero
movb $4, %al
callq printf
incq %r12
cmpq $16, %r12
jne .LBB0_7
# %bb.8: # %_Z11print_saxpyfPfS_S_i.exit
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z4intsPfi
.LCPI1_0:
.quad 0x3ff0000000000000 # double 1
.text
.globl _Z4intsPfi
.p2align 4, 0x90
.type _Z4intsPfi,@function
_Z4intsPfi: # @_Z4intsPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2sd %ecx, %xmm1
movapd %xmm1, %xmm2
addsd %xmm0, %xmm2
divsd %xmm2, %xmm1
cvtsd2ss %xmm1, %xmm1
movss %xmm1, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z4intsPfi, .Lfunc_end1-_Z4intsPfi
.cfi_endproc
# -- End function
.globl _Z20__device_stub__saxpyfPfS_S_i # -- Begin function _Z20__device_stub__saxpyfPfS_S_i
.p2align 4, 0x90
.type _Z20__device_stub__saxpyfPfS_S_i,@function
_Z20__device_stub__saxpyfPfS_S_i: # @_Z20__device_stub__saxpyfPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movss %xmm0, 4(%rsp)
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, (%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5saxpyfPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z20__device_stub__saxpyfPfS_S_i, .Lfunc_end2-_Z20__device_stub__saxpyfPfS_S_i
.cfi_endproc
# -- End function
.globl _Z11print_saxpyfPfS_S_i # -- Begin function _Z11print_saxpyfPfS_S_i
.p2align 4, 0x90
.type _Z11print_saxpyfPfS_S_i,@function
_Z11print_saxpyfPfS_S_i: # @_Z11print_saxpyfPfS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB3_4
# %bb.1: # %.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
cvtss2sd %xmm0, %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
movl %ecx, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_2: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss (%r15,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm2, %xmm2
cvtss2sd %xmm1, %xmm2
movss (%r14,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm3, %xmm3
cvtss2sd %xmm1, %xmm3
movl $.L.str, %edi
movsd 8(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
movb $4, %al
callq printf
incq %r13
cmpq %r13, %r12
jne .LBB3_2
# %bb.3:
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.LBB3_4: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end3:
.size _Z11print_saxpyfPfS_S_i, .Lfunc_end3-_Z11print_saxpyfPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5saxpyfPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5saxpyfPfS_S_i,@object # @_Z5saxpyfPfS_S_i
.section .rodata,"a",@progbits
.globl _Z5saxpyfPfS_S_i
.p2align 3, 0x0
_Z5saxpyfPfS_S_i:
.quad _Z20__device_stub__saxpyfPfS_S_i
.size _Z5saxpyfPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%5.2f = %5.2f x %5.2f + %5.2f\n"
.size .L.str, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5saxpyfPfS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__saxpyfPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5saxpyfPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5saxpyfPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x180], PT ; /* 0x0000600006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FFMA R9, R2, c[0x0][0x160], R5 ; /* 0x0000580002097a23 */
/* 0x004fca0000000005 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5saxpyfPfS_S_i
.globl _Z5saxpyfPfS_S_i
.p2align 8
.type _Z5saxpyfPfS_S_i,@function
_Z5saxpyfPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
s_clause 0x1
s_load_b32 s2, s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, s2, v2
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5saxpyfPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5saxpyfPfS_S_i, .Lfunc_end0-_Z5saxpyfPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5saxpyfPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5saxpyfPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014329e_00000000-6_ex06.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4intsPfi
.type _Z4intsPfi, @function
_Z4intsPfi:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L3
movslq %esi, %rsi
movl $0, %eax
movsd .LC0(%rip), %xmm2
.L5:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movapd %xmm0, %xmm1
addsd %xmm2, %xmm1
divsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rdi,%rax,4)
addq $1, %rax
cmpq %rsi, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2058:
.size _Z4intsPfi, .-_Z4intsPfi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "%5.2f = %5.2f x %5.2f + %5.2f\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "\n"
.text
.globl _Z11print_saxpyfPfS_S_i
.type _Z11print_saxpyfPfS_S_i, @function
_Z11print_saxpyfPfS_S_i:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
testl %ecx, %ecx
jle .L8
movq %rdi, %r12
movq %rsi, %r13
movq %rdx, %r14
movslq %ecx, %rcx
leaq 0(,%rcx,4), %rbp
movl $0, %ebx
pxor %xmm4, %xmm4
cvtss2sd %xmm0, %xmm4
movsd %xmm4, 8(%rsp)
leaq .LC1(%rip), %r15
.L9:
pxor %xmm0, %xmm0
cvtss2sd (%r14,%rbx), %xmm0
pxor %xmm3, %xmm3
cvtss2sd 0(%r13,%rbx), %xmm3
pxor %xmm2, %xmm2
cvtss2sd (%r12,%rbx), %xmm2
movsd 8(%rsp), %xmm1
movq %r15, %rsi
movl $2, %edi
movl $4, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L9
.L8:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z11print_saxpyfPfS_S_i, .-_Z11print_saxpyfPfS_S_i
.globl _Z30__device_stub__Z5saxpyfPfS_S_ifPfS_S_i
.type _Z30__device_stub__Z5saxpyfPfS_S_ifPfS_S_i, @function
_Z30__device_stub__Z5saxpyfPfS_S_ifPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movss %xmm0, 28(%rsp)
movq %rdi, 16(%rsp)
movq %rsi, 8(%rsp)
movq %rdx, (%rsp)
movl %ecx, 24(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5saxpyfPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z30__device_stub__Z5saxpyfPfS_S_ifPfS_S_i, .-_Z30__device_stub__Z5saxpyfPfS_S_ifPfS_S_i
.globl _Z5saxpyfPfS_S_i
.type _Z5saxpyfPfS_S_i, @function
_Z5saxpyfPfS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z5saxpyfPfS_S_ifPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z5saxpyfPfS_S_i, .-_Z5saxpyfPfS_S_i
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $64, %edi
call malloc@PLT
movq %rax, %rbp
movl $64, %edi
call malloc@PLT
movq %rax, %rbx
movl $64, %edi
call malloc@PLT
movq %rax, %r12
movl $16, %esi
movq %rbp, %rdi
call _Z4intsPfi
movl $16, %esi
movq %rbx, %rdi
call _Z4intsPfi
leaq 8(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $64, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $64, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 44(%rsp)
movl $1, 48(%rsp)
movl $4, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L21:
movl $2, %ecx
movl $64, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $16, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
movss .LC3(%rip), %xmm0
call _Z11print_saxpyfPfS_S_i
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl $16, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
movss .LC3(%rip), %xmm0
call _Z30__device_stub__Z5saxpyfPfS_S_ifPfS_S_i
jmp .L21
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z5saxpyfPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z5saxpyfPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1072693248
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1067030938
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ex06.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x3ff0000000000000 # double 1
.LCPI0_1:
.quad 0x3ff3333340000000 # double 1.2000000476837158
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $64, %edi
callq malloc
movq %rax, %rbx
movl $64, %edi
callq malloc
movq %rax, %r14
movl $64, %edi
callq malloc
movq %rax, %r15
xorl %eax, %eax
movsd .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB0_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
movapd %xmm1, %xmm2
addsd %xmm0, %xmm2
divsd %xmm2, %xmm1
cvtsd2ss %xmm1, %xmm1
movss %xmm1, (%rbx,%rax,4)
incq %rax
cmpq $16, %rax
jne .LBB0_1
# %bb.2: # %.lr.ph.i28.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_3: # %.lr.ph.i28
# =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2sd %eax, %xmm1
movapd %xmm1, %xmm2
addsd %xmm0, %xmm2
divsd %xmm2, %xmm1
cvtsd2ss %xmm1, %xmm1
movss %xmm1, (%r14,%rax,4)
incq %rax
cmpq $16, %rax
jne .LBB0_3
# %bb.4: # %_Z4intsPfi.exit32
leaq 24(%rsp), %rdi
movl $64, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $64, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq 24(%rsp), %rdi
movl $64, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $64, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967300, %rdi # imm = 0x100000004
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl $1067030938, 36(%rsp) # imm = 0x3F99999A
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $16, 32(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 104(%rsp), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z5saxpyfPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_6:
movq 8(%rsp), %rsi
movl $64, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_7: # =>This Inner Loop Header: Depth=1
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss (%rbx,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm2, %xmm2
cvtss2sd %xmm1, %xmm2
movss (%r14,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm3, %xmm3
cvtss2sd %xmm1, %xmm3
movl $.L.str, %edi
movsd .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero
movb $4, %al
callq printf
incq %r12
cmpq $16, %r12
jne .LBB0_7
# %bb.8: # %_Z11print_saxpyfPfS_S_i.exit
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z4intsPfi
.LCPI1_0:
.quad 0x3ff0000000000000 # double 1
.text
.globl _Z4intsPfi
.p2align 4, 0x90
.type _Z4intsPfi,@function
_Z4intsPfi: # @_Z4intsPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
movsd .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2sd %ecx, %xmm1
movapd %xmm1, %xmm2
addsd %xmm0, %xmm2
divsd %xmm2, %xmm1
cvtsd2ss %xmm1, %xmm1
movss %xmm1, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z4intsPfi, .Lfunc_end1-_Z4intsPfi
.cfi_endproc
# -- End function
.globl _Z20__device_stub__saxpyfPfS_S_i # -- Begin function _Z20__device_stub__saxpyfPfS_S_i
.p2align 4, 0x90
.type _Z20__device_stub__saxpyfPfS_S_i,@function
_Z20__device_stub__saxpyfPfS_S_i: # @_Z20__device_stub__saxpyfPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movss %xmm0, 4(%rsp)
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, (%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5saxpyfPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z20__device_stub__saxpyfPfS_S_i, .Lfunc_end2-_Z20__device_stub__saxpyfPfS_S_i
.cfi_endproc
# -- End function
.globl _Z11print_saxpyfPfS_S_i # -- Begin function _Z11print_saxpyfPfS_S_i
.p2align 4, 0x90
.type _Z11print_saxpyfPfS_S_i,@function
_Z11print_saxpyfPfS_S_i: # @_Z11print_saxpyfPfS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB3_4
# %bb.1: # %.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
cvtss2sd %xmm0, %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
movl %ecx, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_2: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss (%r15,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm2, %xmm2
cvtss2sd %xmm1, %xmm2
movss (%r14,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm3, %xmm3
cvtss2sd %xmm1, %xmm3
movl $.L.str, %edi
movsd 8(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
movb $4, %al
callq printf
incq %r13
cmpq %r13, %r12
jne .LBB3_2
# %bb.3:
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.LBB3_4: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end3:
.size _Z11print_saxpyfPfS_S_i, .Lfunc_end3-_Z11print_saxpyfPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5saxpyfPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5saxpyfPfS_S_i,@object # @_Z5saxpyfPfS_S_i
.section .rodata,"a",@progbits
.globl _Z5saxpyfPfS_S_i
.p2align 3, 0x0
_Z5saxpyfPfS_S_i:
.quad _Z20__device_stub__saxpyfPfS_S_i
.size _Z5saxpyfPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%5.2f = %5.2f x %5.2f + %5.2f\n"
.size .L.str, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5saxpyfPfS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__saxpyfPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5saxpyfPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdlib.h>
#include<stdio.h>
#include<unistd.h>
#include<sys/time.h>
#include<math.h>
#include<iostream>
struct Particle{
float px;
float py;
float pz;
float vx;
float vy;
float vz;
};
typedef struct timeval tval;
double get_elapsed(tval t0, tval t1);
void get_input_data(struct Particle **particles, int N, const int seed);
void kernel(struct Particle *particles, int N, int n_steps, const double delta_t, const int seed);
__global__
void kernel_cuda(struct Particle *particles, int N, int n_steps, const double delta_t, const int seed);
__host__ __device__
float rand_float(const int seed, int particle, int iter, int N);
#define HLINE "-------------------------------------------------------------\n"
int main(int argc, char *argv[])
{
int c;
int N=1000;
int n_threads=256;
int n_steps=100;
const int seed=2020;
const double delta_t=0.05;
tval t[2] = {0};
double elapsed[2] = {0};
while ((c = getopt(argc, argv, "n:p:s:h")) != -1)
switch (c)
{
case 'n':
N = atoi(optarg);
break;
case 'p':
n_threads = atoi(optarg);
break;
case 's':
n_steps = atoi(optarg);
break;
case 'h':
printf(
"Options:\n-n SIZE\t\tNum Particle\n-s ITERS\tNum Iters\n-p NTHREAD\tNumber of threads\n");
exit(1);
case '?':
break;
}
struct Particle* particles;
struct Particle* d_particles;
get_input_data(&particles, N, seed);
cudaMalloc(&d_particles, N*sizeof(struct Particle));
// For storing the final result copied from Device to Host
struct Particle* particles_=(struct Particle*)malloc(N*sizeof(struct Particle));
cudaMemcpy(d_particles, particles, N*sizeof(struct Particle), cudaMemcpyHostToDevice);
int n_blocks = (N + n_threads - 1) / n_threads;
printf(HLINE);
printf(" N\tNum steps\tNum Threads\tNum Blocks\n");
printf("%4d %8d %14d %16d\n", N, n_steps, n_threads, n_blocks);
printf(HLINE);
// Launch the CPU version
printf("Running particle simulation on the CPU...");
gettimeofday(&t[0], NULL);
kernel(particles, N, n_steps, delta_t, seed);
gettimeofday(&t[1], NULL);
elapsed[0] = get_elapsed(t[0], t[1]);
printf("Done!\n");
// Launch the GPU version
printf("Running particle simulation on the GPU...");
gettimeofday(&t[0], NULL);
for (int iter = 1; iter <= n_steps; iter++)
kernel_cuda<<<n_blocks, n_threads>>>(d_particles, N, iter, delta_t, seed);
cudaMemcpy(particles_, d_particles, N*sizeof(struct Particle), cudaMemcpyDeviceToHost);
gettimeofday(&t[1], NULL);
elapsed[1] = get_elapsed(t[0], t[1]);
printf("Done!\n");
printf("Comparing the output for each implementation...");
float error = 0.0f;
for (int i = 0; i < N; i++)
error = fmax(error, fabs(particles[i].px - particles_[i].px));
if (error < 1e-8){
printf("Correct!\n");
}
else{
printf("Not correct!\n");
}
printf("Elapsed CPU (ms): %f / Elapsed GPU (ms): %f\n", elapsed[0], elapsed[1]);
printf(HLINE);
free(particles);
free(particles_);
cudaFree(d_particles);
return 0;
}
__host__ __device__
float rand_float(const int seed, int particle, int iter, int N)
{
float result = (seed * particle + iter) % N;
return result;
}
__global__
void kernel_cuda(struct Particle *particles, int N, int iter, const double delta_t, const int seed)
{
int q = blockIdx.x * blockDim.x + threadIdx.x;
if(q < N){
// particles[q].vx = (rand() / (double)(RAND_MAX)) * 2 - 1;
// particles[q].vy = (rand() / (double)(RAND_MAX)) * 2 - 1;
// particles[q].vz = (rand() / (double)(RAND_MAX)) * 2 - 1;
particles[q].vx = rand_float(seed, q, iter, N) + 0.0f;
particles[q].vy = rand_float(seed, q, iter, N) + 0.1f;
particles[q].vz = rand_float(seed, q, iter, N) + 0.2f;
particles[q].px += delta_t * particles[q].vx;
particles[q].py += delta_t * particles[q].vy;
particles[q].pz += delta_t * particles[q].vz;
}
}
void kernel(struct Particle *particles, int N, int n_steps, const double delta_t, const int seed)
{
for (int iter = 1; iter <= n_steps; iter++)
{
for (int q = 0; q < N; q++)
{
// particles[q].vx = (rand() / (double)(RAND_MAX)) * 2 - 1;
// particles[q].vy = (rand() / (double)(RAND_MAX)) * 2 - 1;
// particles[q].vz = (rand() / (double)(RAND_MAX)) * 2 - 1;
particles[q].vx = rand_float(seed, q, iter, N) + 0.0f;
particles[q].vy = rand_float(seed, q, iter, N) + 0.1f;
particles[q].vz = rand_float(seed, q, iter, N) + 0.2f;
particles[q].px += delta_t * particles[q].vx;
particles[q].py += delta_t * particles[q].vy;
particles[q].pz += delta_t * particles[q].vz;
}
}
}
void get_input_data(struct Particle **particles, int N, const int seed )
{
struct Particle* particle_t = (struct Particle*)malloc(N*sizeof(struct Particle));
srand(seed);
for(int q=0; q < N; q++)
{
particle_t[q].px = (rand() / (double)(RAND_MAX)) * 2 - 1;
particle_t[q].py = (rand() / (double)(RAND_MAX)) * 2 - 1;
particle_t[q].pz = (rand() / (double)(RAND_MAX)) * 2 - 1;
particle_t[q].vx = (rand() / (double)(RAND_MAX)) * 2 - 1;
particle_t[q].vy = (rand() / (double)(RAND_MAX)) * 2 - 1;
particle_t[q].vz = (rand() / (double)(RAND_MAX)) * 2 - 1;
}
*particles = particle_t;
}
double get_elapsed(tval t0, tval t1)
{
return (double)(t1.tv_sec - t0.tv_sec) * 1000.0L + (double)(t1.tv_usec - t0.tv_usec) / 1000.0L;
} | code for sm_80
Function : _Z11kernel_cudaP8Particleiidi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 1.430511474609375e-06 ; /* 0x00000018ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R3, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000404020a7981 */
/* 0x000ea8000c1e1900 */
/*00a0*/ LDG.E R14, [R2.64+0x8] ; /* 0x00000804020e7981 */
/* 0x000ee8000c1e1900 */
/*00b0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000f22000c1e1900 */
/*00c0*/ IABS R11, c[0x0][0x168] ; /* 0x00005a00000b7a13 */
/* 0x000fe20000000000 */
/*00d0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff097624 */
/* 0x000fc600078e00ff */
/*00e0*/ I2F.RP R7, R11 ; /* 0x0000000b00077306 */
/* 0x000e220000209400 */
/*00f0*/ IMAD R6, R4, R9, c[0x0][0x16c] ; /* 0x00005b0004067624 */
/* 0x000fe400078e0209 */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*0110*/ ISETP.GE.AND P2, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f46270 */
/*0120*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e240000001000 */
/*0130*/ IADD3 R5, R7, 0xffffffe, RZ ; /* 0x0ffffffe07057810 */
/* 0x001fe40007ffe0ff */
/*0140*/ IABS R7, R6 ; /* 0x0000000600077213 */
/* 0x000fc80000000000 */
/*0150*/ F2I.FTZ.U32.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e24000021f000 */
/*0160*/ IADD3 R8, RZ, -R5, RZ ; /* 0x80000005ff087210 */
/* 0x001fca0007ffe0ff */
/*0170*/ IMAD R9, R8, R11, RZ ; /* 0x0000000b08097224 */
/* 0x000fc800078e02ff */
/*0180*/ IMAD.HI.U32 R4, R5, R9, R4 ; /* 0x0000000905047227 */
/* 0x000fcc00078e0004 */
/*0190*/ IMAD.HI.U32 R4, R4, R7, RZ ; /* 0x0000000704047227 */
/* 0x000fca00078e00ff */
/*01a0*/ IADD3 R4, -R4, RZ, RZ ; /* 0x000000ff04047210 */
/* 0x000fca0007ffe1ff */
/*01b0*/ IMAD R4, R11, R4, R7 ; /* 0x000000040b047224 */
/* 0x000fca00078e0207 */
/*01c0*/ ISETP.GT.U32.AND P0, PT, R11, R4, PT ; /* 0x000000040b00720c */
/* 0x000fda0003f04070 */
/*01d0*/ @!P0 IMAD.IADD R4, R4, 0x1, -R11 ; /* 0x0000000104048824 */
/* 0x000fe200078e0a0b */
/*01e0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fc80003f05270 */
/*01f0*/ ISETP.GT.U32.AND P1, PT, R11, R4, PT ; /* 0x000000040b00720c */
/* 0x000fda0003f24070 */
/*0200*/ @!P1 IADD3 R4, R4, -R11, RZ ; /* 0x8000000b04049210 */
/* 0x000fca0007ffe0ff */
/*0210*/ @!P2 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff04a224 */
/* 0x000fe200078e0a04 */
/*0220*/ @!P0 LOP3.LUT R4, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff048a12 */
/* 0x000fc800078e33ff */
/*0230*/ I2F R17, R4 ; /* 0x0000000400117306 */
/* 0x000e240000201400 */
/*0240*/ FADD R19, R17, 0.10000000149011611938 ; /* 0x3dcccccd11137421 */
/* 0x001fcc0000000000 */
/*0250*/ F2F.F64.F32 R4, R17 ; /* 0x0000001100047310 */
/* 0x000fe20000201800 */
/*0260*/ FADD R21, R17, 0.20000000298023223877 ; /* 0x3e4ccccd11157421 */
/* 0x000fe20000000000 */
/*0270*/ STG.E [R2.64+0xc], R17 ; /* 0x00000c1102007986 */
/* 0x000fe8000c101904 */
/*0280*/ STG.E [R2.64+0x10], R19 ; /* 0x0000101302007986 */
/* 0x000fe4000c101904 */
/*0290*/ F2F.F64.F32 R8, R19 ; /* 0x0000001300087310 */
/* 0x000fe40000201800 */
/*02a0*/ STG.E [R2.64+0x14], R21 ; /* 0x0000141502007986 */
/* 0x000fec000c101904 */
/*02b0*/ F2F.F64.F32 R12, R21 ; /* 0x00000015000c7310 */
/* 0x000ff00000201800 */
/*02c0*/ F2F.F64.F32 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x004e300000201800 */
/*02d0*/ F2F.F64.F32 R14, R14 ; /* 0x0000000e000e7310 */
/* 0x008e700000201800 */
/*02e0*/ F2F.F64.F32 R6, R0 ; /* 0x0000000000067310 */
/* 0x010ea20000201800 */
/*02f0*/ DFMA R8, R8, c[0x0][0x170], R10 ; /* 0x00005c0008087a2b */
/* 0x001e08000000000a */
/*0300*/ DFMA R12, R12, c[0x0][0x170], R14 ; /* 0x00005c000c0c7a2b */
/* 0x002e4c000000000e */
/*0310*/ F2F.F32.F64 R9, R8 ; /* 0x0000000800097310 */
/* 0x001e220000301000 */
/*0320*/ DFMA R4, R4, c[0x0][0x170], R6 ; /* 0x00005c0004047a2b */
/* 0x004e8e0000000006 */
/*0330*/ F2F.F32.F64 R13, R12 ; /* 0x0000000c000d7310 */
/* 0x002e700000301000 */
/*0340*/ F2F.F32.F64 R5, R4 ; /* 0x0000000400057310 */
/* 0x004ea20000301000 */
/*0350*/ STG.E [R2.64+0x4], R9 ; /* 0x0000040902007986 */
/* 0x001fe8000c101904 */
/*0360*/ STG.E [R2.64+0x8], R13 ; /* 0x0000080d02007986 */
/* 0x002fe8000c101904 */
/*0370*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*0380*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0390*/ BRA 0x390; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdlib.h>
#include<stdio.h>
#include<unistd.h>
#include<sys/time.h>
#include<math.h>
#include<iostream>
struct Particle{
float px;
float py;
float pz;
float vx;
float vy;
float vz;
};
typedef struct timeval tval;
double get_elapsed(tval t0, tval t1);
void get_input_data(struct Particle **particles, int N, const int seed);
void kernel(struct Particle *particles, int N, int n_steps, const double delta_t, const int seed);
__global__
void kernel_cuda(struct Particle *particles, int N, int n_steps, const double delta_t, const int seed);
__host__ __device__
float rand_float(const int seed, int particle, int iter, int N);
#define HLINE "-------------------------------------------------------------\n"
int main(int argc, char *argv[])
{
int c;
int N=1000;
int n_threads=256;
int n_steps=100;
const int seed=2020;
const double delta_t=0.05;
tval t[2] = {0};
double elapsed[2] = {0};
while ((c = getopt(argc, argv, "n:p:s:h")) != -1)
switch (c)
{
case 'n':
N = atoi(optarg);
break;
case 'p':
n_threads = atoi(optarg);
break;
case 's':
n_steps = atoi(optarg);
break;
case 'h':
printf(
"Options:\n-n SIZE\t\tNum Particle\n-s ITERS\tNum Iters\n-p NTHREAD\tNumber of threads\n");
exit(1);
case '?':
break;
}
struct Particle* particles;
struct Particle* d_particles;
get_input_data(&particles, N, seed);
cudaMalloc(&d_particles, N*sizeof(struct Particle));
// For storing the final result copied from Device to Host
struct Particle* particles_=(struct Particle*)malloc(N*sizeof(struct Particle));
cudaMemcpy(d_particles, particles, N*sizeof(struct Particle), cudaMemcpyHostToDevice);
int n_blocks = (N + n_threads - 1) / n_threads;
printf(HLINE);
printf(" N\tNum steps\tNum Threads\tNum Blocks\n");
printf("%4d %8d %14d %16d\n", N, n_steps, n_threads, n_blocks);
printf(HLINE);
// Launch the CPU version
printf("Running particle simulation on the CPU...");
gettimeofday(&t[0], NULL);
kernel(particles, N, n_steps, delta_t, seed);
gettimeofday(&t[1], NULL);
elapsed[0] = get_elapsed(t[0], t[1]);
printf("Done!\n");
// Launch the GPU version
printf("Running particle simulation on the GPU...");
gettimeofday(&t[0], NULL);
for (int iter = 1; iter <= n_steps; iter++)
kernel_cuda<<<n_blocks, n_threads>>>(d_particles, N, iter, delta_t, seed);
cudaMemcpy(particles_, d_particles, N*sizeof(struct Particle), cudaMemcpyDeviceToHost);
gettimeofday(&t[1], NULL);
elapsed[1] = get_elapsed(t[0], t[1]);
printf("Done!\n");
printf("Comparing the output for each implementation...");
float error = 0.0f;
for (int i = 0; i < N; i++)
error = fmax(error, fabs(particles[i].px - particles_[i].px));
if (error < 1e-8){
printf("Correct!\n");
}
else{
printf("Not correct!\n");
}
printf("Elapsed CPU (ms): %f / Elapsed GPU (ms): %f\n", elapsed[0], elapsed[1]);
printf(HLINE);
free(particles);
free(particles_);
cudaFree(d_particles);
return 0;
}
__host__ __device__
float rand_float(const int seed, int particle, int iter, int N)
{
float result = (seed * particle + iter) % N;
return result;
}
__global__
void kernel_cuda(struct Particle *particles, int N, int iter, const double delta_t, const int seed)
{
int q = blockIdx.x * blockDim.x + threadIdx.x;
if(q < N){
// particles[q].vx = (rand() / (double)(RAND_MAX)) * 2 - 1;
// particles[q].vy = (rand() / (double)(RAND_MAX)) * 2 - 1;
// particles[q].vz = (rand() / (double)(RAND_MAX)) * 2 - 1;
particles[q].vx = rand_float(seed, q, iter, N) + 0.0f;
particles[q].vy = rand_float(seed, q, iter, N) + 0.1f;
particles[q].vz = rand_float(seed, q, iter, N) + 0.2f;
particles[q].px += delta_t * particles[q].vx;
particles[q].py += delta_t * particles[q].vy;
particles[q].pz += delta_t * particles[q].vz;
}
}
void kernel(struct Particle *particles, int N, int n_steps, const double delta_t, const int seed)
{
for (int iter = 1; iter <= n_steps; iter++)
{
for (int q = 0; q < N; q++)
{
// particles[q].vx = (rand() / (double)(RAND_MAX)) * 2 - 1;
// particles[q].vy = (rand() / (double)(RAND_MAX)) * 2 - 1;
// particles[q].vz = (rand() / (double)(RAND_MAX)) * 2 - 1;
particles[q].vx = rand_float(seed, q, iter, N) + 0.0f;
particles[q].vy = rand_float(seed, q, iter, N) + 0.1f;
particles[q].vz = rand_float(seed, q, iter, N) + 0.2f;
particles[q].px += delta_t * particles[q].vx;
particles[q].py += delta_t * particles[q].vy;
particles[q].pz += delta_t * particles[q].vz;
}
}
}
void get_input_data(struct Particle **particles, int N, const int seed )
{
struct Particle* particle_t = (struct Particle*)malloc(N*sizeof(struct Particle));
srand(seed);
for(int q=0; q < N; q++)
{
particle_t[q].px = (rand() / (double)(RAND_MAX)) * 2 - 1;
particle_t[q].py = (rand() / (double)(RAND_MAX)) * 2 - 1;
particle_t[q].pz = (rand() / (double)(RAND_MAX)) * 2 - 1;
particle_t[q].vx = (rand() / (double)(RAND_MAX)) * 2 - 1;
particle_t[q].vy = (rand() / (double)(RAND_MAX)) * 2 - 1;
particle_t[q].vz = (rand() / (double)(RAND_MAX)) * 2 - 1;
}
*particles = particle_t;
}
double get_elapsed(tval t0, tval t1)
{
return (double)(t1.tv_sec - t0.tv_sec) * 1000.0L + (double)(t1.tv_usec - t0.tv_usec) / 1000.0L;
} | .file "tmpxft_0009a04a_00000000-6_particle.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3689:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3689:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10rand_floatiiii
.type _Z10rand_floatiiii, @function
_Z10rand_floatiiii:
.LFB3683:
.cfi_startproc
endbr64
imull %esi, %edi
leal (%rdi,%rdx), %eax
cltd
idivl %ecx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
ret
.cfi_endproc
.LFE3683:
.size _Z10rand_floatiiii, .-_Z10rand_floatiiii
.globl _Z6kernelP8Particleiidi
.type _Z6kernelP8Particleiidi, @function
_Z6kernelP8Particleiidi:
.LFB3684:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L13
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %r10
movl %esi, %edi
movapd %xmm0, %xmm3
movl %ecx, %r8d
leal 1(%rdx), %ebx
movslq %esi, %rax
leaq (%rax,%rax,2), %rax
leaq (%r10,%rax,8), %r9
movl $1, %r11d
pxor %xmm6, %xmm6
movss .LC1(%rip), %xmm5
movss .LC2(%rip), %xmm4
jmp .L6
.L7:
movl %esi, %eax
cltd
idivl %edi
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movaps %xmm0, %xmm2
addss %xmm6, %xmm2
movss %xmm2, 12(%rcx)
movaps %xmm0, %xmm1
addss %xmm5, %xmm1
movss %xmm1, 16(%rcx)
addss %xmm4, %xmm0
movss %xmm0, 20(%rcx)
pxor %xmm7, %xmm7
cvtss2sd (%rcx), %xmm7
cvtss2sd %xmm2, %xmm2
mulsd %xmm3, %xmm2
addsd %xmm7, %xmm2
cvtsd2ss %xmm2, %xmm2
movss %xmm2, (%rcx)
pxor %xmm2, %xmm2
cvtss2sd 4(%rcx), %xmm2
cvtss2sd %xmm1, %xmm1
mulsd %xmm3, %xmm1
addsd %xmm2, %xmm1
cvtsd2ss %xmm1, %xmm1
movss %xmm1, 4(%rcx)
pxor %xmm1, %xmm1
cvtss2sd 8(%rcx), %xmm1
cvtss2sd %xmm0, %xmm0
mulsd %xmm3, %xmm0
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 8(%rcx)
addl %r8d, %esi
addq $24, %rcx
cmpq %r9, %rcx
jne .L7
.L9:
addl $1, %r11d
cmpl %ebx, %r11d
je .L4
.L6:
movl %r11d, %esi
movq %r10, %rcx
testl %edi, %edi
jg .L7
jmp .L9
.L4:
popq %rbx
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore 3
ret
.cfi_endproc
.LFE3684:
.size _Z6kernelP8Particleiidi, .-_Z6kernelP8Particleiidi
.globl _Z14get_input_dataPP8Particleii
.type _Z14get_input_dataPP8Particleii, @function
_Z14get_input_dataPP8Particleii:
.LFB3685:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r13
movl %esi, %ebx
movl %edx, %r14d
movslq %esi, %rax
leaq (%rax,%rax,2), %rbp
salq $3, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
movl %r14d, %edi
call srand@PLT
testl %ebx, %ebx
jle .L17
movq %r12, %rbx
addq %r12, %rbp
.L18:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC3(%rip), %xmm0
addsd %xmm0, %xmm0
subsd .LC4(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC3(%rip), %xmm0
addsd %xmm0, %xmm0
subsd .LC4(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 4(%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC3(%rip), %xmm0
addsd %xmm0, %xmm0
subsd .LC4(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 8(%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC3(%rip), %xmm0
addsd %xmm0, %xmm0
subsd .LC4(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 12(%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC3(%rip), %xmm0
addsd %xmm0, %xmm0
subsd .LC4(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 16(%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC3(%rip), %xmm0
addsd %xmm0, %xmm0
subsd .LC4(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 20(%rbx)
addq $24, %rbx
cmpq %rbp, %rbx
jne .L18
.L17:
movq %r12, 0(%r13)
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3685:
.size _Z14get_input_dataPP8Particleii, .-_Z14get_input_dataPP8Particleii
.globl _Z11get_elapsed7timevalS_
.type _Z11get_elapsed7timevalS_, @function
_Z11get_elapsed7timevalS_:
.LFB3686:
.cfi_startproc
endbr64
subq %rdi, %rdx
pxor %xmm1, %xmm1
cvtsi2sdq %rdx, %xmm1
movsd %xmm1, -16(%rsp)
flds .LC5(%rip)
fld %st(0)
fmull -16(%rsp)
fxch %st(1)
subq %rsi, %rcx
pxor %xmm2, %xmm2
cvtsi2sdq %rcx, %xmm2
movsd %xmm2, -16(%rsp)
fdivrl -16(%rsp)
faddp %st, %st(1)
fstpl -16(%rsp)
movsd -16(%rsp), %xmm0
ret
.cfi_endproc
.LFE3686:
.size _Z11get_elapsed7timevalS_, .-_Z11get_elapsed7timevalS_
.globl _Z43__device_stub__Z11kernel_cudaP8ParticleiidiP8Particleiidi
.type _Z43__device_stub__Z11kernel_cudaP8ParticleiidiP8Particleiidi, @function
_Z43__device_stub__Z11kernel_cudaP8ParticleiidiP8Particleiidi:
.LFB3711:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movsd %xmm0, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11kernel_cudaP8Particleiidi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3711:
.size _Z43__device_stub__Z11kernel_cudaP8ParticleiidiP8Particleiidi, .-_Z43__device_stub__Z11kernel_cudaP8ParticleiidiP8Particleiidi
.globl _Z11kernel_cudaP8Particleiidi
.type _Z11kernel_cudaP8Particleiidi, @function
_Z11kernel_cudaP8Particleiidi:
.LFB3712:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z11kernel_cudaP8ParticleiidiP8Particleiidi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3712:
.size _Z11kernel_cudaP8Particleiidi, .-_Z11kernel_cudaP8Particleiidi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "Options:\n-n SIZE\t\tNum Particle\n-s ITERS\tNum Iters\n-p NTHREAD\tNumber of threads\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC8:
.string "n:p:s:h"
.section .rodata.str1.8
.align 8
.LC9:
.string "-------------------------------------------------------------\n"
.align 8
.LC10:
.string " N\tNum steps\tNum Threads\tNum Blocks\n"
.section .rodata.str1.1
.LC11:
.string "%4d %8d %14d %16d\n"
.section .rodata.str1.8
.align 8
.LC12:
.string "Running particle simulation on the CPU..."
.section .rodata.str1.1
.LC14:
.string "Done!\n"
.section .rodata.str1.8
.align 8
.LC15:
.string "Running particle simulation on the GPU..."
.align 8
.LC16:
.string "Comparing the output for each implementation..."
.section .rodata.str1.1
.LC19:
.string "Correct!\n"
.LC20:
.string "Not correct!\n"
.section .rodata.str1.8
.align 8
.LC21:
.string "Elapsed CPU (ms): %f / Elapsed GPU (ms): %f\n"
.text
.globl main
.type main, @function
main:
.LFB3682:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movl %edi, %r14d
movq %rsi, %r13
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
pxor %xmm0, %xmm0
movaps %xmm0, 80(%rsp)
movaps %xmm0, 96(%rsp)
movl $100, %ebp
movl $256, %ebx
movl $1000, %r12d
leaq .LC8(%rip), %r15
jmp .L51
.L33:
cmpl $115, %eax
jne .L51
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %ebp
jmp .L51
.L35:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %r12d
.L51:
movq %r15, %rdx
movq %r13, %rsi
movl %r14d, %edi
call getopt@PLT
cmpl $-1, %eax
je .L54
cmpl $112, %eax
je .L32
jg .L33
cmpl $104, %eax
je .L34
cmpl $110, %eax
je .L35
jmp .L51
.L32:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %ebx
jmp .L51
.L34:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L54:
leaq 40(%rsp), %rdi
movl $2020, %edx
movl %r12d, %esi
call _Z14get_input_dataPP8Particleii
movslq %r12d, %rax
leaq (%rax,%rax,2), %rax
leaq 0(,%rax,8), %r14
movq %r14, 24(%rsp)
leaq 48(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movq %r14, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq 40(%rsp), %r15
movl $1, %ecx
movq %r14, %rdx
movq %r15, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
leal -1(%r12,%rbx), %eax
cltd
idivl %ebx
movl %eax, %r14d
leaq .LC9(%rip), %r13
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r14d, %r9d
movl %ebx, %r8d
movl %ebp, %ecx
movl %r12d, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 80(%rsp), %r13
movl $0, %esi
movq %r13, %rdi
call gettimeofday@PLT
movl $2020, %ecx
movsd .LC13(%rip), %xmm0
movl %ebp, %edx
movl %r12d, %esi
movq %r15, %rdi
call _Z6kernelP8Particleiidi
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 96(%rsp), %rdx
movq 104(%rsp), %rcx
movq 80(%rsp), %rdi
movq 88(%rsp), %rsi
call _Z11get_elapsed7timevalS_
movsd %xmm0, 16(%rsp)
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq %r13, %rdi
call gettimeofday@PLT
testl %ebp, %ebp
jle .L40
movl $1, %r13d
jmp .L42
.L41:
addl $1, %r13d
cmpl %ebp, %r13d
jg .L40
.L42:
movl %ebx, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl %r14d, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L41
movl $2020, %ecx
movsd .LC13(%rip), %xmm0
movl %r13d, %edx
movl %r12d, %esi
movq 48(%rsp), %rdi
call _Z43__device_stub__Z11kernel_cudaP8ParticleiidiP8Particleiidi
jmp .L41
.L40:
movl $2, %ecx
movq 24(%rsp), %r14
movq %r14, %rdx
movq 48(%rsp), %rsi
movq 8(%rsp), %rbp
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 96(%rsp), %rdx
movq 104(%rsp), %rcx
movq 80(%rsp), %rdi
movq 88(%rsp), %rsi
call _Z11get_elapsed7timevalS_
movsd %xmm0, 24(%rsp)
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %r12d, %r12d
jle .L43
movq %r15, %rbx
addq %r15, %r14
movq %r14, %r12
pxor %xmm1, %xmm1
.L44:
movss (%rbx), %xmm2
subss 0(%rbp), %xmm2
andps .LC17(%rip), %xmm2
movaps %xmm2, %xmm0
call fmaxf@PLT
movaps %xmm0, %xmm1
addq $24, %rbx
addq $24, %rbp
cmpq %r12, %rbx
jne .L44
pxor %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movsd .LC18(%rip), %xmm0
comisd %xmm1, %xmm0
ja .L43
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L47
.L43:
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L47:
movsd 24(%rsp), %xmm1
movsd 16(%rsp), %xmm0
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r15, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L55
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3682:
.size main, .-main
.section .rodata.str1.1
.LC23:
.string "_Z11kernel_cudaP8Particleiidi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3714:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC23(%rip), %rdx
movq %rdx, %rcx
leaq _Z11kernel_cudaP8Particleiidi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3714:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1036831949
.align 4
.LC2:
.long 1045220557
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long -4194304
.long 1105199103
.align 8
.LC4:
.long 0
.long 1072693248
.section .rodata.cst4
.align 4
.LC5:
.long 1148846080
.section .rodata.cst8
.align 8
.LC13:
.long -1717986918
.long 1068079513
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC17:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC18:
.long -500134854
.long 1044740494
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdlib.h>
#include<stdio.h>
#include<unistd.h>
#include<sys/time.h>
#include<math.h>
#include<iostream>
struct Particle{
float px;
float py;
float pz;
float vx;
float vy;
float vz;
};
typedef struct timeval tval;
double get_elapsed(tval t0, tval t1);
void get_input_data(struct Particle **particles, int N, const int seed);
void kernel(struct Particle *particles, int N, int n_steps, const double delta_t, const int seed);
__global__
void kernel_cuda(struct Particle *particles, int N, int n_steps, const double delta_t, const int seed);
__host__ __device__
float rand_float(const int seed, int particle, int iter, int N);
#define HLINE "-------------------------------------------------------------\n"
int main(int argc, char *argv[])
{
int c;
int N=1000;
int n_threads=256;
int n_steps=100;
const int seed=2020;
const double delta_t=0.05;
tval t[2] = {0};
double elapsed[2] = {0};
while ((c = getopt(argc, argv, "n:p:s:h")) != -1)
switch (c)
{
case 'n':
N = atoi(optarg);
break;
case 'p':
n_threads = atoi(optarg);
break;
case 's':
n_steps = atoi(optarg);
break;
case 'h':
printf(
"Options:\n-n SIZE\t\tNum Particle\n-s ITERS\tNum Iters\n-p NTHREAD\tNumber of threads\n");
exit(1);
case '?':
break;
}
struct Particle* particles;
struct Particle* d_particles;
get_input_data(&particles, N, seed);
cudaMalloc(&d_particles, N*sizeof(struct Particle));
// For storing the final result copied from Device to Host
struct Particle* particles_=(struct Particle*)malloc(N*sizeof(struct Particle));
cudaMemcpy(d_particles, particles, N*sizeof(struct Particle), cudaMemcpyHostToDevice);
int n_blocks = (N + n_threads - 1) / n_threads;
printf(HLINE);
printf(" N\tNum steps\tNum Threads\tNum Blocks\n");
printf("%4d %8d %14d %16d\n", N, n_steps, n_threads, n_blocks);
printf(HLINE);
// Launch the CPU version
printf("Running particle simulation on the CPU...");
gettimeofday(&t[0], NULL);
kernel(particles, N, n_steps, delta_t, seed);
gettimeofday(&t[1], NULL);
elapsed[0] = get_elapsed(t[0], t[1]);
printf("Done!\n");
// Launch the GPU version
printf("Running particle simulation on the GPU...");
gettimeofday(&t[0], NULL);
for (int iter = 1; iter <= n_steps; iter++)
kernel_cuda<<<n_blocks, n_threads>>>(d_particles, N, iter, delta_t, seed);
cudaMemcpy(particles_, d_particles, N*sizeof(struct Particle), cudaMemcpyDeviceToHost);
gettimeofday(&t[1], NULL);
elapsed[1] = get_elapsed(t[0], t[1]);
printf("Done!\n");
printf("Comparing the output for each implementation...");
float error = 0.0f;
for (int i = 0; i < N; i++)
error = fmax(error, fabs(particles[i].px - particles_[i].px));
if (error < 1e-8){
printf("Correct!\n");
}
else{
printf("Not correct!\n");
}
printf("Elapsed CPU (ms): %f / Elapsed GPU (ms): %f\n", elapsed[0], elapsed[1]);
printf(HLINE);
free(particles);
free(particles_);
cudaFree(d_particles);
return 0;
}
__host__ __device__
float rand_float(const int seed, int particle, int iter, int N)
{
float result = (seed * particle + iter) % N;
return result;
}
__global__
void kernel_cuda(struct Particle *particles, int N, int iter, const double delta_t, const int seed)
{
int q = blockIdx.x * blockDim.x + threadIdx.x;
if(q < N){
// particles[q].vx = (rand() / (double)(RAND_MAX)) * 2 - 1;
// particles[q].vy = (rand() / (double)(RAND_MAX)) * 2 - 1;
// particles[q].vz = (rand() / (double)(RAND_MAX)) * 2 - 1;
particles[q].vx = rand_float(seed, q, iter, N) + 0.0f;
particles[q].vy = rand_float(seed, q, iter, N) + 0.1f;
particles[q].vz = rand_float(seed, q, iter, N) + 0.2f;
particles[q].px += delta_t * particles[q].vx;
particles[q].py += delta_t * particles[q].vy;
particles[q].pz += delta_t * particles[q].vz;
}
}
void kernel(struct Particle *particles, int N, int n_steps, const double delta_t, const int seed)
{
for (int iter = 1; iter <= n_steps; iter++)
{
for (int q = 0; q < N; q++)
{
// particles[q].vx = (rand() / (double)(RAND_MAX)) * 2 - 1;
// particles[q].vy = (rand() / (double)(RAND_MAX)) * 2 - 1;
// particles[q].vz = (rand() / (double)(RAND_MAX)) * 2 - 1;
particles[q].vx = rand_float(seed, q, iter, N) + 0.0f;
particles[q].vy = rand_float(seed, q, iter, N) + 0.1f;
particles[q].vz = rand_float(seed, q, iter, N) + 0.2f;
particles[q].px += delta_t * particles[q].vx;
particles[q].py += delta_t * particles[q].vy;
particles[q].pz += delta_t * particles[q].vz;
}
}
}
void get_input_data(struct Particle **particles, int N, const int seed )
{
struct Particle* particle_t = (struct Particle*)malloc(N*sizeof(struct Particle));
srand(seed);
for(int q=0; q < N; q++)
{
particle_t[q].px = (rand() / (double)(RAND_MAX)) * 2 - 1;
particle_t[q].py = (rand() / (double)(RAND_MAX)) * 2 - 1;
particle_t[q].pz = (rand() / (double)(RAND_MAX)) * 2 - 1;
particle_t[q].vx = (rand() / (double)(RAND_MAX)) * 2 - 1;
particle_t[q].vy = (rand() / (double)(RAND_MAX)) * 2 - 1;
particle_t[q].vz = (rand() / (double)(RAND_MAX)) * 2 - 1;
}
*particles = particle_t;
}
double get_elapsed(tval t0, tval t1)
{
return (double)(t1.tv_sec - t0.tv_sec) * 1000.0L + (double)(t1.tv_usec - t0.tv_usec) / 1000.0L;
} | #include <hip/hip_runtime.h>
#include<stdlib.h>
#include<stdio.h>
#include<unistd.h>
#include<sys/time.h>
#include<math.h>
#include<iostream>
struct Particle{
float px;
float py;
float pz;
float vx;
float vy;
float vz;
};
typedef struct timeval tval;
double get_elapsed(tval t0, tval t1);
void get_input_data(struct Particle **particles, int N, const int seed);
void kernel(struct Particle *particles, int N, int n_steps, const double delta_t, const int seed);
__global__
void kernel_cuda(struct Particle *particles, int N, int n_steps, const double delta_t, const int seed);
__host__ __device__
float rand_float(const int seed, int particle, int iter, int N);
#define HLINE "-------------------------------------------------------------\n"
int main(int argc, char *argv[])
{
int c;
int N=1000;
int n_threads=256;
int n_steps=100;
const int seed=2020;
const double delta_t=0.05;
tval t[2] = {0};
double elapsed[2] = {0};
while ((c = getopt(argc, argv, "n:p:s:h")) != -1)
switch (c)
{
case 'n':
N = atoi(optarg);
break;
case 'p':
n_threads = atoi(optarg);
break;
case 's':
n_steps = atoi(optarg);
break;
case 'h':
printf(
"Options:\n-n SIZE\t\tNum Particle\n-s ITERS\tNum Iters\n-p NTHREAD\tNumber of threads\n");
exit(1);
case '?':
break;
}
struct Particle* particles;
struct Particle* d_particles;
get_input_data(&particles, N, seed);
hipMalloc(&d_particles, N*sizeof(struct Particle));
// For storing the final result copied from Device to Host
struct Particle* particles_=(struct Particle*)malloc(N*sizeof(struct Particle));
hipMemcpy(d_particles, particles, N*sizeof(struct Particle), hipMemcpyHostToDevice);
int n_blocks = (N + n_threads - 1) / n_threads;
printf(HLINE);
printf(" N\tNum steps\tNum Threads\tNum Blocks\n");
printf("%4d %8d %14d %16d\n", N, n_steps, n_threads, n_blocks);
printf(HLINE);
// Launch the CPU version
printf("Running particle simulation on the CPU...");
gettimeofday(&t[0], NULL);
kernel(particles, N, n_steps, delta_t, seed);
gettimeofday(&t[1], NULL);
elapsed[0] = get_elapsed(t[0], t[1]);
printf("Done!\n");
// Launch the GPU version
printf("Running particle simulation on the GPU...");
gettimeofday(&t[0], NULL);
for (int iter = 1; iter <= n_steps; iter++)
kernel_cuda<<<n_blocks, n_threads>>>(d_particles, N, iter, delta_t, seed);
hipMemcpy(particles_, d_particles, N*sizeof(struct Particle), hipMemcpyDeviceToHost);
gettimeofday(&t[1], NULL);
elapsed[1] = get_elapsed(t[0], t[1]);
printf("Done!\n");
printf("Comparing the output for each implementation...");
float error = 0.0f;
for (int i = 0; i < N; i++)
error = fmax(error, fabs(particles[i].px - particles_[i].px));
if (error < 1e-8){
printf("Correct!\n");
}
else{
printf("Not correct!\n");
}
printf("Elapsed CPU (ms): %f / Elapsed GPU (ms): %f\n", elapsed[0], elapsed[1]);
printf(HLINE);
free(particles);
free(particles_);
hipFree(d_particles);
return 0;
}
__host__ __device__
float rand_float(const int seed, int particle, int iter, int N)
{
float result = (seed * particle + iter) % N;
return result;
}
__global__
void kernel_cuda(struct Particle *particles, int N, int iter, const double delta_t, const int seed)
{
int q = blockIdx.x * blockDim.x + threadIdx.x;
if(q < N){
// particles[q].vx = (rand() / (double)(RAND_MAX)) * 2 - 1;
// particles[q].vy = (rand() / (double)(RAND_MAX)) * 2 - 1;
// particles[q].vz = (rand() / (double)(RAND_MAX)) * 2 - 1;
particles[q].vx = rand_float(seed, q, iter, N) + 0.0f;
particles[q].vy = rand_float(seed, q, iter, N) + 0.1f;
particles[q].vz = rand_float(seed, q, iter, N) + 0.2f;
particles[q].px += delta_t * particles[q].vx;
particles[q].py += delta_t * particles[q].vy;
particles[q].pz += delta_t * particles[q].vz;
}
}
void kernel(struct Particle *particles, int N, int n_steps, const double delta_t, const int seed)
{
for (int iter = 1; iter <= n_steps; iter++)
{
for (int q = 0; q < N; q++)
{
// particles[q].vx = (rand() / (double)(RAND_MAX)) * 2 - 1;
// particles[q].vy = (rand() / (double)(RAND_MAX)) * 2 - 1;
// particles[q].vz = (rand() / (double)(RAND_MAX)) * 2 - 1;
particles[q].vx = rand_float(seed, q, iter, N) + 0.0f;
particles[q].vy = rand_float(seed, q, iter, N) + 0.1f;
particles[q].vz = rand_float(seed, q, iter, N) + 0.2f;
particles[q].px += delta_t * particles[q].vx;
particles[q].py += delta_t * particles[q].vy;
particles[q].pz += delta_t * particles[q].vz;
}
}
}
void get_input_data(struct Particle **particles, int N, const int seed )
{
struct Particle* particle_t = (struct Particle*)malloc(N*sizeof(struct Particle));
srand(seed);
for(int q=0; q < N; q++)
{
particle_t[q].px = (rand() / (double)(RAND_MAX)) * 2 - 1;
particle_t[q].py = (rand() / (double)(RAND_MAX)) * 2 - 1;
particle_t[q].pz = (rand() / (double)(RAND_MAX)) * 2 - 1;
particle_t[q].vx = (rand() / (double)(RAND_MAX)) * 2 - 1;
particle_t[q].vy = (rand() / (double)(RAND_MAX)) * 2 - 1;
particle_t[q].vz = (rand() / (double)(RAND_MAX)) * 2 - 1;
}
*particles = particle_t;
}
double get_elapsed(tval t0, tval t1)
{
return (double)(t1.tv_sec - t0.tv_sec) * 1000.0L + (double)(t1.tv_usec - t0.tv_usec) / 1000.0L;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdlib.h>
#include<stdio.h>
#include<unistd.h>
#include<sys/time.h>
#include<math.h>
#include<iostream>
struct Particle{
float px;
float py;
float pz;
float vx;
float vy;
float vz;
};
typedef struct timeval tval;
double get_elapsed(tval t0, tval t1);
void get_input_data(struct Particle **particles, int N, const int seed);
void kernel(struct Particle *particles, int N, int n_steps, const double delta_t, const int seed);
__global__
void kernel_cuda(struct Particle *particles, int N, int n_steps, const double delta_t, const int seed);
__host__ __device__
float rand_float(const int seed, int particle, int iter, int N);
#define HLINE "-------------------------------------------------------------\n"
int main(int argc, char *argv[])
{
int c;
int N=1000;
int n_threads=256;
int n_steps=100;
const int seed=2020;
const double delta_t=0.05;
tval t[2] = {0};
double elapsed[2] = {0};
while ((c = getopt(argc, argv, "n:p:s:h")) != -1)
switch (c)
{
case 'n':
N = atoi(optarg);
break;
case 'p':
n_threads = atoi(optarg);
break;
case 's':
n_steps = atoi(optarg);
break;
case 'h':
printf(
"Options:\n-n SIZE\t\tNum Particle\n-s ITERS\tNum Iters\n-p NTHREAD\tNumber of threads\n");
exit(1);
case '?':
break;
}
struct Particle* particles;
struct Particle* d_particles;
get_input_data(&particles, N, seed);
hipMalloc(&d_particles, N*sizeof(struct Particle));
// For storing the final result copied from Device to Host
struct Particle* particles_=(struct Particle*)malloc(N*sizeof(struct Particle));
hipMemcpy(d_particles, particles, N*sizeof(struct Particle), hipMemcpyHostToDevice);
int n_blocks = (N + n_threads - 1) / n_threads;
printf(HLINE);
printf(" N\tNum steps\tNum Threads\tNum Blocks\n");
printf("%4d %8d %14d %16d\n", N, n_steps, n_threads, n_blocks);
printf(HLINE);
// Launch the CPU version
printf("Running particle simulation on the CPU...");
gettimeofday(&t[0], NULL);
kernel(particles, N, n_steps, delta_t, seed);
gettimeofday(&t[1], NULL);
elapsed[0] = get_elapsed(t[0], t[1]);
printf("Done!\n");
// Launch the GPU version
printf("Running particle simulation on the GPU...");
gettimeofday(&t[0], NULL);
for (int iter = 1; iter <= n_steps; iter++)
kernel_cuda<<<n_blocks, n_threads>>>(d_particles, N, iter, delta_t, seed);
hipMemcpy(particles_, d_particles, N*sizeof(struct Particle), hipMemcpyDeviceToHost);
gettimeofday(&t[1], NULL);
elapsed[1] = get_elapsed(t[0], t[1]);
printf("Done!\n");
printf("Comparing the output for each implementation...");
float error = 0.0f;
for (int i = 0; i < N; i++)
error = fmax(error, fabs(particles[i].px - particles_[i].px));
if (error < 1e-8){
printf("Correct!\n");
}
else{
printf("Not correct!\n");
}
printf("Elapsed CPU (ms): %f / Elapsed GPU (ms): %f\n", elapsed[0], elapsed[1]);
printf(HLINE);
free(particles);
free(particles_);
hipFree(d_particles);
return 0;
}
__host__ __device__
float rand_float(const int seed, int particle, int iter, int N)
{
float result = (seed * particle + iter) % N;
return result;
}
__global__
void kernel_cuda(struct Particle *particles, int N, int iter, const double delta_t, const int seed)
{
int q = blockIdx.x * blockDim.x + threadIdx.x;
if(q < N){
// particles[q].vx = (rand() / (double)(RAND_MAX)) * 2 - 1;
// particles[q].vy = (rand() / (double)(RAND_MAX)) * 2 - 1;
// particles[q].vz = (rand() / (double)(RAND_MAX)) * 2 - 1;
particles[q].vx = rand_float(seed, q, iter, N) + 0.0f;
particles[q].vy = rand_float(seed, q, iter, N) + 0.1f;
particles[q].vz = rand_float(seed, q, iter, N) + 0.2f;
particles[q].px += delta_t * particles[q].vx;
particles[q].py += delta_t * particles[q].vy;
particles[q].pz += delta_t * particles[q].vz;
}
}
void kernel(struct Particle *particles, int N, int n_steps, const double delta_t, const int seed)
{
for (int iter = 1; iter <= n_steps; iter++)
{
for (int q = 0; q < N; q++)
{
// particles[q].vx = (rand() / (double)(RAND_MAX)) * 2 - 1;
// particles[q].vy = (rand() / (double)(RAND_MAX)) * 2 - 1;
// particles[q].vz = (rand() / (double)(RAND_MAX)) * 2 - 1;
particles[q].vx = rand_float(seed, q, iter, N) + 0.0f;
particles[q].vy = rand_float(seed, q, iter, N) + 0.1f;
particles[q].vz = rand_float(seed, q, iter, N) + 0.2f;
particles[q].px += delta_t * particles[q].vx;
particles[q].py += delta_t * particles[q].vy;
particles[q].pz += delta_t * particles[q].vz;
}
}
}
void get_input_data(struct Particle **particles, int N, const int seed )
{
struct Particle* particle_t = (struct Particle*)malloc(N*sizeof(struct Particle));
srand(seed);
for(int q=0; q < N; q++)
{
particle_t[q].px = (rand() / (double)(RAND_MAX)) * 2 - 1;
particle_t[q].py = (rand() / (double)(RAND_MAX)) * 2 - 1;
particle_t[q].pz = (rand() / (double)(RAND_MAX)) * 2 - 1;
particle_t[q].vx = (rand() / (double)(RAND_MAX)) * 2 - 1;
particle_t[q].vy = (rand() / (double)(RAND_MAX)) * 2 - 1;
particle_t[q].vz = (rand() / (double)(RAND_MAX)) * 2 - 1;
}
*particles = particle_t;
}
double get_elapsed(tval t0, tval t1)
{
return (double)(t1.tv_sec - t0.tv_sec) * 1000.0L + (double)(t1.tv_usec - t0.tv_usec) / 1000.0L;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11kernel_cudaP8Particleiidi
.globl _Z11kernel_cudaP8Particleiidi
.p2align 8
.type _Z11kernel_cudaP8Particleiidi,@function
_Z11kernel_cudaP8Particleiidi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_clause 0x3
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0xc
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b32 s0, s[0:1], 0x18
s_ashr_i32 s1, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s1
s_xor_b32 s1, s2, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v0, s1
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[7:8], null, v1, 24, s[4:5]
v_mad_u64_u32 v[2:3], null, v1, s0, s[6:7]
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_sub_i32 s0, 0, s1
global_load_b96 v[4:6], v[7:8], off
v_cvt_u32_f32_e32 v0, v0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v1, s0, v0
v_add_nc_u32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v2, v2, v3
v_mul_hi_u32 v1, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v1
v_mul_hi_u32 v0, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s1
v_sub_nc_u32_e32 v0, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v1, s1, v0
v_cmp_le_u32_e32 vcc_lo, s1, v0
v_cndmask_b32_e32 v0, v0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v1, s1, v0
v_cmp_le_u32_e32 vcc_lo, s1, v0
v_cndmask_b32_e32 v0, v0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v3
v_sub_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v3, v0
v_add_f32_e32 v9, 0x3dcccccd, v3
v_add_f32_e32 v10, 0x3e4ccccd, v3
v_cvt_f64_f32_e32 v[0:1], v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f64_f32_e32 v[11:12], v9
v_cvt_f64_f32_e32 v[13:14], v10
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[15:16], v4
v_cvt_f64_f32_e32 v[4:5], v5
v_cvt_f64_f32_e32 v[17:18], v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[0:1], v[0:1], s[8:9], v[15:16]
v_fma_f64 v[4:5], v[11:12], s[8:9], v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[11:12], v[13:14], s[8:9], v[17:18]
v_cvt_f32_f64_e32 v0, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f32_f64_e32 v1, v[4:5]
v_cvt_f32_f64_e32 v2, v[11:12]
s_clause 0x1
global_store_b64 v[7:8], v[9:10], off offset:16
global_store_b128 v[7:8], v[0:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11kernel_cudaP8Particleiidi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 19
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11kernel_cudaP8Particleiidi, .Lfunc_end0-_Z11kernel_cudaP8Particleiidi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11kernel_cudaP8Particleiidi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11kernel_cudaP8Particleiidi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 19
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdlib.h>
#include<stdio.h>
#include<unistd.h>
#include<sys/time.h>
#include<math.h>
#include<iostream>
struct Particle{
float px;
float py;
float pz;
float vx;
float vy;
float vz;
};
typedef struct timeval tval;
double get_elapsed(tval t0, tval t1);
void get_input_data(struct Particle **particles, int N, const int seed);
void kernel(struct Particle *particles, int N, int n_steps, const double delta_t, const int seed);
__global__
void kernel_cuda(struct Particle *particles, int N, int n_steps, const double delta_t, const int seed);
__host__ __device__
float rand_float(const int seed, int particle, int iter, int N);
#define HLINE "-------------------------------------------------------------\n"
int main(int argc, char *argv[])
{
int c;
int N=1000;
int n_threads=256;
int n_steps=100;
const int seed=2020;
const double delta_t=0.05;
tval t[2] = {0};
double elapsed[2] = {0};
while ((c = getopt(argc, argv, "n:p:s:h")) != -1)
switch (c)
{
case 'n':
N = atoi(optarg);
break;
case 'p':
n_threads = atoi(optarg);
break;
case 's':
n_steps = atoi(optarg);
break;
case 'h':
printf(
"Options:\n-n SIZE\t\tNum Particle\n-s ITERS\tNum Iters\n-p NTHREAD\tNumber of threads\n");
exit(1);
case '?':
break;
}
struct Particle* particles;
struct Particle* d_particles;
get_input_data(&particles, N, seed);
hipMalloc(&d_particles, N*sizeof(struct Particle));
// For storing the final result copied from Device to Host
struct Particle* particles_=(struct Particle*)malloc(N*sizeof(struct Particle));
hipMemcpy(d_particles, particles, N*sizeof(struct Particle), hipMemcpyHostToDevice);
int n_blocks = (N + n_threads - 1) / n_threads;
printf(HLINE);
printf(" N\tNum steps\tNum Threads\tNum Blocks\n");
printf("%4d %8d %14d %16d\n", N, n_steps, n_threads, n_blocks);
printf(HLINE);
// Launch the CPU version
printf("Running particle simulation on the CPU...");
gettimeofday(&t[0], NULL);
kernel(particles, N, n_steps, delta_t, seed);
gettimeofday(&t[1], NULL);
elapsed[0] = get_elapsed(t[0], t[1]);
printf("Done!\n");
// Launch the GPU version
printf("Running particle simulation on the GPU...");
gettimeofday(&t[0], NULL);
for (int iter = 1; iter <= n_steps; iter++)
kernel_cuda<<<n_blocks, n_threads>>>(d_particles, N, iter, delta_t, seed);
hipMemcpy(particles_, d_particles, N*sizeof(struct Particle), hipMemcpyDeviceToHost);
gettimeofday(&t[1], NULL);
elapsed[1] = get_elapsed(t[0], t[1]);
printf("Done!\n");
printf("Comparing the output for each implementation...");
float error = 0.0f;
for (int i = 0; i < N; i++)
error = fmax(error, fabs(particles[i].px - particles_[i].px));
if (error < 1e-8){
printf("Correct!\n");
}
else{
printf("Not correct!\n");
}
printf("Elapsed CPU (ms): %f / Elapsed GPU (ms): %f\n", elapsed[0], elapsed[1]);
printf(HLINE);
free(particles);
free(particles_);
hipFree(d_particles);
return 0;
}
__host__ __device__
float rand_float(const int seed, int particle, int iter, int N)
{
float result = (seed * particle + iter) % N;
return result;
}
__global__
void kernel_cuda(struct Particle *particles, int N, int iter, const double delta_t, const int seed)
{
int q = blockIdx.x * blockDim.x + threadIdx.x;
if(q < N){
// particles[q].vx = (rand() / (double)(RAND_MAX)) * 2 - 1;
// particles[q].vy = (rand() / (double)(RAND_MAX)) * 2 - 1;
// particles[q].vz = (rand() / (double)(RAND_MAX)) * 2 - 1;
particles[q].vx = rand_float(seed, q, iter, N) + 0.0f;
particles[q].vy = rand_float(seed, q, iter, N) + 0.1f;
particles[q].vz = rand_float(seed, q, iter, N) + 0.2f;
particles[q].px += delta_t * particles[q].vx;
particles[q].py += delta_t * particles[q].vy;
particles[q].pz += delta_t * particles[q].vz;
}
}
void kernel(struct Particle *particles, int N, int n_steps, const double delta_t, const int seed)
{
for (int iter = 1; iter <= n_steps; iter++)
{
for (int q = 0; q < N; q++)
{
// particles[q].vx = (rand() / (double)(RAND_MAX)) * 2 - 1;
// particles[q].vy = (rand() / (double)(RAND_MAX)) * 2 - 1;
// particles[q].vz = (rand() / (double)(RAND_MAX)) * 2 - 1;
particles[q].vx = rand_float(seed, q, iter, N) + 0.0f;
particles[q].vy = rand_float(seed, q, iter, N) + 0.1f;
particles[q].vz = rand_float(seed, q, iter, N) + 0.2f;
particles[q].px += delta_t * particles[q].vx;
particles[q].py += delta_t * particles[q].vy;
particles[q].pz += delta_t * particles[q].vz;
}
}
}
void get_input_data(struct Particle **particles, int N, const int seed )
{
struct Particle* particle_t = (struct Particle*)malloc(N*sizeof(struct Particle));
srand(seed);
for(int q=0; q < N; q++)
{
particle_t[q].px = (rand() / (double)(RAND_MAX)) * 2 - 1;
particle_t[q].py = (rand() / (double)(RAND_MAX)) * 2 - 1;
particle_t[q].pz = (rand() / (double)(RAND_MAX)) * 2 - 1;
particle_t[q].vx = (rand() / (double)(RAND_MAX)) * 2 - 1;
particle_t[q].vy = (rand() / (double)(RAND_MAX)) * 2 - 1;
particle_t[q].vz = (rand() / (double)(RAND_MAX)) * 2 - 1;
}
*particles = particle_t;
}
double get_elapsed(tval t0, tval t1)
{
return (double)(t1.tv_sec - t0.tv_sec) * 1000.0L + (double)(t1.tv_usec - t0.tv_usec) / 1000.0L;
} | .text
.file "particle.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x3dcccccd # float 0.100000001
.LCPI0_1:
.long 0x3e4ccccd # float 0.200000003
.LCPI0_5:
.long 0x447a0000 # float 1000
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI0_2:
.quad 0x3fa999999999999a # double 0.050000000000000003
.LCPI0_4:
.quad 0x3e45798ee2308c3a # double 1.0E-8
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI0_3:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 336
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %r14d
xorps %xmm0, %xmm0
movaps %xmm0, 48(%rsp)
movaps %xmm0, 32(%rsp)
movl $1000, %r15d # imm = 0x3E8
movl $256, %ebp # imm = 0x100
movl $100, %r12d
jmp .LBB0_1
.p2align 4, 0x90
.LBB0_2: # in Loop: Header=BB0_1 Depth=1
cmpl $-1, %eax
je .LBB0_3
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl $.L.str, %edx
movl %r14d, %edi
movq %rbx, %rsi
callq getopt
# kill: def $eax killed $eax def $rax
leal -104(%rax), %ecx
cmpl $11, %ecx
ja .LBB0_2
# %bb.20: # in Loop: Header=BB0_1 Depth=1
jmpq *.LJTI0_0(,%rcx,8)
.LBB0_21: # in Loop: Header=BB0_1 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
jmp .LBB0_1
.LBB0_22: # in Loop: Header=BB0_1 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
jmp .LBB0_1
.LBB0_23: # in Loop: Header=BB0_1 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
jmp .LBB0_1
.LBB0_3:
leaq 168(%rsp), %rdi
movl %r15d, %esi
movl $2020, %edx # imm = 0x7E4
callq _Z14get_input_dataPP8Particleii
movslq %r15d, %r13
leaq (,%r13,8), %rax
leaq (%rax,%rax,2), %rbx
movq %rsp, %rdi
movq %rbx, %rsi
callq hipMalloc
movq %rbx, %rdi
callq malloc
movq %rax, 112(%rsp) # 8-byte Spill
movq (%rsp), %rdi
movq 168(%rsp), %r14
movq %r14, %rsi
movq %rbx, 8(%rsp) # 8-byte Spill
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
leal -1(%rbp,%r13), %eax
cltd
idivl %ebp
movl %eax, %ebx
movl $.Lstr.7, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
movl $.L.str.4, %edi
movl %r13d, %esi
movl %r12d, %edx
movl %ebp, %ecx
movl %ebx, %r8d
xorl %eax, %eax
callq printf
movl $.Lstr.7, %edi
callq puts@PLT
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl %r15d, %r10d
testl %r12d, %r12d
jle .LBB0_9
# %bb.4: # %.preheader.lr.ph.i
leal 1(%r12), %esi
leaq (,%r10,8), %rax
leaq (%rax,%rax,2), %rdi
movl $1, %r8d
movss .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movsd .LCPI0_2(%rip), %xmm2 # xmm2 = mem[0],zero
jmp .LBB0_5
.p2align 4, 0x90
.LBB0_8: # %._crit_edge.i
# in Loop: Header=BB0_5 Depth=1
incq %r8
cmpq %rsi, %r8
je .LBB0_9
.LBB0_5: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB0_7 Depth 2
testl %r15d, %r15d
jle .LBB0_8
# %bb.6: # %.lr.ph.i.preheader
# in Loop: Header=BB0_5 Depth=1
movl %r8d, %ecx
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB0_7: # %.lr.ph.i
# Parent Loop BB0_5 Depth=1
# => This Inner Loop Header: Depth=2
movl %ecx, %eax
cltd
idivl %r15d
xorps %xmm3, %xmm3
cvtsi2ss %edx, %xmm3
movss %xmm3, 12(%r14,%r9)
movaps %xmm3, %xmm4
addss %xmm0, %xmm4
movss %xmm4, 16(%r14,%r9)
xorps %xmm5, %xmm5
cvtss2sd %xmm3, %xmm5
addss %xmm1, %xmm3
movss %xmm3, 20(%r14,%r9)
mulsd %xmm2, %xmm5
movss (%r14,%r9), %xmm6 # xmm6 = mem[0],zero,zero,zero
cvtss2sd %xmm6, %xmm6
addsd %xmm5, %xmm6
xorps %xmm5, %xmm5
cvtsd2ss %xmm6, %xmm5
movss 4(%r14,%r9), %xmm6 # xmm6 = mem[0],zero,zero,zero
movss %xmm5, (%r14,%r9)
cvtss2sd %xmm4, %xmm4
mulsd %xmm2, %xmm4
xorps %xmm5, %xmm5
cvtss2sd %xmm6, %xmm5
addsd %xmm4, %xmm5
xorps %xmm4, %xmm4
cvtsd2ss %xmm5, %xmm4
movss %xmm4, 4(%r14,%r9)
cvtss2sd %xmm3, %xmm3
mulsd %xmm2, %xmm3
movss 8(%r14,%r9), %xmm4 # xmm4 = mem[0],zero,zero,zero
cvtss2sd %xmm4, %xmm4
addsd %xmm3, %xmm4
xorps %xmm3, %xmm3
cvtsd2ss %xmm4, %xmm3
movss %xmm3, 8(%r14,%r9)
addq $24, %r9
addl $2020, %ecx # imm = 0x7E4
cmpq %r9, %rdi
jne .LBB0_7
jmp .LBB0_8
.LBB0_9: # %_Z6kernelP8Particleiidi.exit
movq %r10, 72(%rsp) # 8-byte Spill
leaq 48(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 32(%rsp), %rax
movq %rax, 88(%rsp) # 8-byte Spill
movq 40(%rsp), %rax
movq %rax, 104(%rsp) # 8-byte Spill
movq 48(%rsp), %rax
movq %rax, 80(%rsp) # 8-byte Spill
movq 56(%rsp), %rax
movq %rax, 96(%rsp) # 8-byte Spill
movl $.Lstr.4, %edi
callq puts@PLT
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
testl %r12d, %r12d
jle .LBB0_14
# %bb.10: # %.lr.ph
movl %ebx, %r13d
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r13
movl %ebp, %ebp
orq %rax, %rbp
negl %r12d
movl $1, %ebx
jmp .LBB0_11
.p2align 4, 0x90
.LBB0_13: # in Loop: Header=BB0_11 Depth=1
leal (%r12,%rbx), %eax
incl %eax
movl %ebx, %ecx
incl %ecx
movl %ecx, %ebx
cmpl $1, %eax
je .LBB0_14
.LBB0_11: # =>This Inner Loop Header: Depth=1
movq %r13, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_13
# %bb.12: # in Loop: Header=BB0_11 Depth=1
movq (%rsp), %rax
movq %rax, 232(%rsp)
movl %r15d, 28(%rsp)
movl %ebx, 24(%rsp)
movabsq $4587366580439587226, %rax # imm = 0x3FA999999999999A
movq %rax, 224(%rsp)
movl $2020, 20(%rsp) # imm = 0x7E4
leaq 232(%rsp), %rax
movq %rax, 240(%rsp)
leaq 28(%rsp), %rax
movq %rax, 248(%rsp)
leaq 24(%rsp), %rax
movq %rax, 256(%rsp)
leaq 224(%rsp), %rax
movq %rax, 264(%rsp)
leaq 20(%rsp), %rax
movq %rax, 272(%rsp)
leaq 208(%rsp), %rdi
leaq 192(%rsp), %rsi
leaq 184(%rsp), %rdx
leaq 176(%rsp), %rcx
callq __hipPopCallConfiguration
movq 208(%rsp), %rsi
movl 216(%rsp), %edx
movq 192(%rsp), %rcx
movl 200(%rsp), %r8d
movl $_Z11kernel_cudaP8Particleiidi, %edi
leaq 240(%rsp), %r9
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB0_13
.LBB0_14: # %._crit_edge
movq (%rsp), %rsi
movq 112(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movq 8(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
leaq 48(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 32(%rsp), %rbp
movq 40(%rsp), %rax
movq %rax, 8(%rsp) # 8-byte Spill
movq 48(%rsp), %r12
movq 56(%rsp), %r13
movl $.Lstr.4, %edi
callq puts@PLT
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl $.Lstr.6, %edi
testl %r15d, %r15d
jle .LBB0_19
# %bb.15: # %.lr.ph73.preheader
movq 72(%rsp), %rax # 8-byte Reload
shlq $3, %rax
leaq (%rax,%rax,2), %rax
xorpd %xmm2, %xmm2
xorl %ecx, %ecx
movaps .LCPI0_3(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movapd %xmm2, %xmm0
.p2align 4, 0x90
.LBB0_16: # %.lr.ph73
# =>This Inner Loop Header: Depth=1
movss (%r14,%rcx), %xmm3 # xmm3 = mem[0],zero,zero,zero
subss (%rbx,%rcx), %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm0, %xmm0
movaps %xmm0, %xmm4
andps %xmm3, %xmm4
maxss %xmm2, %xmm3
andnps %xmm3, %xmm0
orps %xmm4, %xmm0
addq $24, %rcx
movaps %xmm0, %xmm2
cmpq %rcx, %rax
jne .LBB0_16
# %bb.17: # %._crit_edge74.loopexit
cvtss2sd %xmm0, %xmm0
movsd .LCPI0_4(%rip), %xmm1 # xmm1 = mem[0],zero
ucomisd %xmm0, %xmm1
ja .LBB0_19
# %bb.18:
movl $.Lstr.5, %edi
.LBB0_19: # %.critedge
callq puts@PLT
subq %rbp, %r12
xorps %xmm0, %xmm0
cvtsi2sd %r12, %xmm0
movsd %xmm0, 160(%rsp)
flds .LCPI0_5(%rip)
fld %st(0)
fmull 160(%rsp)
subq 8(%rsp), %r13 # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %r13, %xmm0
movsd %xmm0, 152(%rsp)
fld %st(1)
fdivrl 152(%rsp)
faddp %st, %st(1)
fstpl 128(%rsp)
movq 80(%rsp), %rax # 8-byte Reload
subq 88(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movsd 128(%rsp), %xmm1 # xmm1 = mem[0],zero
movsd %xmm0, 144(%rsp)
fld %st(0)
fmull 144(%rsp)
movq 96(%rsp), %rax # 8-byte Reload
subq 104(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movsd %xmm0, 136(%rsp)
fxch %st(1)
fdivrl 136(%rsp)
faddp %st, %st(1)
fstpl 120(%rsp)
movsd 120(%rsp), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.11, %edi
movb $2, %al
callq printf
movl $.Lstr.7, %edi
callq puts@PLT
movq %r14, %rdi
callq free
movq %rbx, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_24:
.cfi_def_cfa_offset 336
movl $.Lstr.8, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
.section .rodata,"a",@progbits
.p2align 3, 0x0
.LJTI0_0:
.quad .LBB0_24
.quad .LBB0_1
.quad .LBB0_1
.quad .LBB0_1
.quad .LBB0_1
.quad .LBB0_1
.quad .LBB0_21
.quad .LBB0_1
.quad .LBB0_22
.quad .LBB0_1
.quad .LBB0_1
.quad .LBB0_23
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z14get_input_dataPP8Particleii
.LCPI1_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI1_1:
.quad 0xbff0000000000000 # double -1
.text
.globl _Z14get_input_dataPP8Particleii
.p2align 4, 0x90
.type _Z14get_input_dataPP8Particleii,@function
_Z14get_input_dataPP8Particleii: # @_Z14get_input_dataPP8Particleii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r15d
movl %esi, %ebp
movq %rdi, %rbx
movslq %esi, %r12
leaq (,%r12,8), %rax
leaq (%rax,%rax,2), %rdi
callq malloc
movq %rax, %r14
movl %r15d, %edi
callq srand
testl %r12d, %r12d
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %eax
shlq $3, %rax
leaq (%rax,%rax,2), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
addsd %xmm0, %xmm0
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r14,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
addsd %xmm0, %xmm0
addsd .LCPI1_1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 4(%r14,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
addsd %xmm0, %xmm0
addsd .LCPI1_1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 8(%r14,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
addsd %xmm0, %xmm0
addsd .LCPI1_1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 12(%r14,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
addsd %xmm0, %xmm0
addsd .LCPI1_1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 16(%r14,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
addsd %xmm0, %xmm0
addsd .LCPI1_1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 20(%r14,%r12)
addq $24, %r12
cmpq %r12, %r15
jne .LBB1_2
.LBB1_3: # %._crit_edge
movq %r14, (%rbx)
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z14get_input_dataPP8Particleii, .Lfunc_end1-_Z14get_input_dataPP8Particleii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z6kernelP8Particleiidi
.LCPI2_0:
.long 0x3dcccccd # float 0.100000001
.LCPI2_1:
.long 0x3e4ccccd # float 0.200000003
.text
.globl _Z6kernelP8Particleiidi
.p2align 4, 0x90
.type _Z6kernelP8Particleiidi,@function
_Z6kernelP8Particleiidi: # @_Z6kernelP8Particleiidi
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB2_7
# %bb.1: # %.preheader.lr.ph
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %edx, %r8d
incl %r8d
movl %esi, %eax
shlq $3, %rax
leaq (%rax,%rax,2), %r10
movl $1, %r11d
movss .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss .LCPI2_1(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %r11
cmpq %r8, %r11
je .LBB2_6
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
testl %esi, %esi
jle .LBB2_5
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB2_2 Depth=1
movl %r11d, %r9d
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_4: # %.lr.ph
# Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %r9d, %eax
cltd
idivl %esi
xorps %xmm3, %xmm3
cvtsi2ss %edx, %xmm3
movss %xmm3, 12(%rdi,%rbx)
movaps %xmm3, %xmm4
addss %xmm1, %xmm4
movss %xmm4, 16(%rdi,%rbx)
xorps %xmm5, %xmm5
cvtss2sd %xmm3, %xmm5
addss %xmm2, %xmm3
movss %xmm3, 20(%rdi,%rbx)
mulsd %xmm0, %xmm5
movss (%rdi,%rbx), %xmm6 # xmm6 = mem[0],zero,zero,zero
cvtss2sd %xmm6, %xmm6
addsd %xmm5, %xmm6
xorps %xmm5, %xmm5
cvtsd2ss %xmm6, %xmm5
movss 4(%rdi,%rbx), %xmm6 # xmm6 = mem[0],zero,zero,zero
movss %xmm5, (%rdi,%rbx)
cvtss2sd %xmm4, %xmm4
mulsd %xmm0, %xmm4
xorps %xmm5, %xmm5
cvtss2sd %xmm6, %xmm5
addsd %xmm4, %xmm5
xorps %xmm4, %xmm4
cvtsd2ss %xmm5, %xmm4
movss %xmm4, 4(%rdi,%rbx)
cvtss2sd %xmm3, %xmm3
mulsd %xmm0, %xmm3
movss 8(%rdi,%rbx), %xmm4 # xmm4 = mem[0],zero,zero,zero
cvtss2sd %xmm4, %xmm4
addsd %xmm3, %xmm4
xorps %xmm3, %xmm3
cvtsd2ss %xmm4, %xmm3
movss %xmm3, 8(%rdi,%rbx)
addq $24, %rbx
addl %ecx, %r9d
cmpq %rbx, %r10
jne .LBB2_4
jmp .LBB2_5
.LBB2_6:
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.LBB2_7: # %._crit_edge43
retq
.Lfunc_end2:
.size _Z6kernelP8Particleiidi, .Lfunc_end2-_Z6kernelP8Particleiidi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11get_elapsed7timevalS_
.LCPI3_0:
.long 0x447a0000 # float 1000
.text
.globl _Z11get_elapsed7timevalS_
.p2align 4, 0x90
.type _Z11get_elapsed7timevalS_,@function
_Z11get_elapsed7timevalS_: # @_Z11get_elapsed7timevalS_
.cfi_startproc
# %bb.0:
subq %rdi, %rdx
cvtsi2sd %rdx, %xmm0
movsd %xmm0, -8(%rsp)
flds .LCPI3_0(%rip)
fld %st(0)
fmull -8(%rsp)
subq %rsi, %rcx
xorps %xmm0, %xmm0
cvtsi2sd %rcx, %xmm0
movsd %xmm0, -16(%rsp)
fxch %st(1)
fdivrl -16(%rsp)
faddp %st, %st(1)
fstpl -24(%rsp)
movsd -24(%rsp), %xmm0 # xmm0 = mem[0],zero
retq
.Lfunc_end3:
.size _Z11get_elapsed7timevalS_, .Lfunc_end3-_Z11get_elapsed7timevalS_
.cfi_endproc
# -- End function
.globl _Z26__device_stub__kernel_cudaP8Particleiidi # -- Begin function _Z26__device_stub__kernel_cudaP8Particleiidi
.p2align 4, 0x90
.type _Z26__device_stub__kernel_cudaP8Particleiidi,@function
_Z26__device_stub__kernel_cudaP8Particleiidi: # @_Z26__device_stub__kernel_cudaP8Particleiidi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movsd %xmm0, 64(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11kernel_cudaP8Particleiidi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z26__device_stub__kernel_cudaP8Particleiidi, .Lfunc_end4-_Z26__device_stub__kernel_cudaP8Particleiidi
.cfi_endproc
# -- End function
.globl _Z10rand_floatiiii # -- Begin function _Z10rand_floatiiii
.p2align 4, 0x90
.type _Z10rand_floatiiii,@function
_Z10rand_floatiiii: # @_Z10rand_floatiiii
.cfi_startproc
# %bb.0:
# kill: def $edx killed $edx def $rdx
# kill: def $edi killed $edi def $rdi
imull %esi, %edi
leal (%rdi,%rdx), %eax
cltd
idivl %ecx
cvtsi2ss %edx, %xmm0
retq
.Lfunc_end5:
.size _Z10rand_floatiiii, .Lfunc_end5-_Z10rand_floatiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11kernel_cudaP8Particleiidi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "n:p:s:h"
.size .L.str, 8
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%4d %8d %14d %16d\n"
.size .L.str.4, 19
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Running particle simulation on the CPU..."
.size .L.str.5, 42
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Running particle simulation on the GPU..."
.size .L.str.7, 42
.type _Z11kernel_cudaP8Particleiidi,@object # @_Z11kernel_cudaP8Particleiidi
.section .rodata,"a",@progbits
.globl _Z11kernel_cudaP8Particleiidi
.p2align 3, 0x0
_Z11kernel_cudaP8Particleiidi:
.quad _Z26__device_stub__kernel_cudaP8Particleiidi
.size _Z11kernel_cudaP8Particleiidi, 8
.type .L.str.8,@object # @.str.8
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.8:
.asciz "Comparing the output for each implementation..."
.size .L.str.8, 48
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Elapsed CPU (ms): %f / Elapsed GPU (ms): %f\n"
.size .L.str.11, 45
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11kernel_cudaP8Particleiidi"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz " N\tNum steps\tNum Threads\tNum Blocks"
.size .Lstr.1, 37
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Done!"
.size .Lstr.4, 6
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "Not correct!"
.size .Lstr.5, 13
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "Correct!"
.size .Lstr.6, 9
.type .Lstr.7,@object # @str.7
.Lstr.7:
.asciz "-------------------------------------------------------------"
.size .Lstr.7, 62
.type .Lstr.8,@object # @str.8
.Lstr.8:
.asciz "Options:\n-n SIZE\t\tNum Particle\n-s ITERS\tNum Iters\n-p NTHREAD\tNumber of threads"
.size .Lstr.8, 79
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__kernel_cudaP8Particleiidi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11kernel_cudaP8Particleiidi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11kernel_cudaP8Particleiidi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 1.430511474609375e-06 ; /* 0x00000018ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R3, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000404020a7981 */
/* 0x000ea8000c1e1900 */
/*00a0*/ LDG.E R14, [R2.64+0x8] ; /* 0x00000804020e7981 */
/* 0x000ee8000c1e1900 */
/*00b0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000f22000c1e1900 */
/*00c0*/ IABS R11, c[0x0][0x168] ; /* 0x00005a00000b7a13 */
/* 0x000fe20000000000 */
/*00d0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff097624 */
/* 0x000fc600078e00ff */
/*00e0*/ I2F.RP R7, R11 ; /* 0x0000000b00077306 */
/* 0x000e220000209400 */
/*00f0*/ IMAD R6, R4, R9, c[0x0][0x16c] ; /* 0x00005b0004067624 */
/* 0x000fe400078e0209 */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*0110*/ ISETP.GE.AND P2, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f46270 */
/*0120*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e240000001000 */
/*0130*/ IADD3 R5, R7, 0xffffffe, RZ ; /* 0x0ffffffe07057810 */
/* 0x001fe40007ffe0ff */
/*0140*/ IABS R7, R6 ; /* 0x0000000600077213 */
/* 0x000fc80000000000 */
/*0150*/ F2I.FTZ.U32.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e24000021f000 */
/*0160*/ IADD3 R8, RZ, -R5, RZ ; /* 0x80000005ff087210 */
/* 0x001fca0007ffe0ff */
/*0170*/ IMAD R9, R8, R11, RZ ; /* 0x0000000b08097224 */
/* 0x000fc800078e02ff */
/*0180*/ IMAD.HI.U32 R4, R5, R9, R4 ; /* 0x0000000905047227 */
/* 0x000fcc00078e0004 */
/*0190*/ IMAD.HI.U32 R4, R4, R7, RZ ; /* 0x0000000704047227 */
/* 0x000fca00078e00ff */
/*01a0*/ IADD3 R4, -R4, RZ, RZ ; /* 0x000000ff04047210 */
/* 0x000fca0007ffe1ff */
/*01b0*/ IMAD R4, R11, R4, R7 ; /* 0x000000040b047224 */
/* 0x000fca00078e0207 */
/*01c0*/ ISETP.GT.U32.AND P0, PT, R11, R4, PT ; /* 0x000000040b00720c */
/* 0x000fda0003f04070 */
/*01d0*/ @!P0 IMAD.IADD R4, R4, 0x1, -R11 ; /* 0x0000000104048824 */
/* 0x000fe200078e0a0b */
/*01e0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fc80003f05270 */
/*01f0*/ ISETP.GT.U32.AND P1, PT, R11, R4, PT ; /* 0x000000040b00720c */
/* 0x000fda0003f24070 */
/*0200*/ @!P1 IADD3 R4, R4, -R11, RZ ; /* 0x8000000b04049210 */
/* 0x000fca0007ffe0ff */
/*0210*/ @!P2 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff04a224 */
/* 0x000fe200078e0a04 */
/*0220*/ @!P0 LOP3.LUT R4, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff048a12 */
/* 0x000fc800078e33ff */
/*0230*/ I2F R17, R4 ; /* 0x0000000400117306 */
/* 0x000e240000201400 */
/*0240*/ FADD R19, R17, 0.10000000149011611938 ; /* 0x3dcccccd11137421 */
/* 0x001fcc0000000000 */
/*0250*/ F2F.F64.F32 R4, R17 ; /* 0x0000001100047310 */
/* 0x000fe20000201800 */
/*0260*/ FADD R21, R17, 0.20000000298023223877 ; /* 0x3e4ccccd11157421 */
/* 0x000fe20000000000 */
/*0270*/ STG.E [R2.64+0xc], R17 ; /* 0x00000c1102007986 */
/* 0x000fe8000c101904 */
/*0280*/ STG.E [R2.64+0x10], R19 ; /* 0x0000101302007986 */
/* 0x000fe4000c101904 */
/*0290*/ F2F.F64.F32 R8, R19 ; /* 0x0000001300087310 */
/* 0x000fe40000201800 */
/*02a0*/ STG.E [R2.64+0x14], R21 ; /* 0x0000141502007986 */
/* 0x000fec000c101904 */
/*02b0*/ F2F.F64.F32 R12, R21 ; /* 0x00000015000c7310 */
/* 0x000ff00000201800 */
/*02c0*/ F2F.F64.F32 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x004e300000201800 */
/*02d0*/ F2F.F64.F32 R14, R14 ; /* 0x0000000e000e7310 */
/* 0x008e700000201800 */
/*02e0*/ F2F.F64.F32 R6, R0 ; /* 0x0000000000067310 */
/* 0x010ea20000201800 */
/*02f0*/ DFMA R8, R8, c[0x0][0x170], R10 ; /* 0x00005c0008087a2b */
/* 0x001e08000000000a */
/*0300*/ DFMA R12, R12, c[0x0][0x170], R14 ; /* 0x00005c000c0c7a2b */
/* 0x002e4c000000000e */
/*0310*/ F2F.F32.F64 R9, R8 ; /* 0x0000000800097310 */
/* 0x001e220000301000 */
/*0320*/ DFMA R4, R4, c[0x0][0x170], R6 ; /* 0x00005c0004047a2b */
/* 0x004e8e0000000006 */
/*0330*/ F2F.F32.F64 R13, R12 ; /* 0x0000000c000d7310 */
/* 0x002e700000301000 */
/*0340*/ F2F.F32.F64 R5, R4 ; /* 0x0000000400057310 */
/* 0x004ea20000301000 */
/*0350*/ STG.E [R2.64+0x4], R9 ; /* 0x0000040902007986 */
/* 0x001fe8000c101904 */
/*0360*/ STG.E [R2.64+0x8], R13 ; /* 0x0000080d02007986 */
/* 0x002fe8000c101904 */
/*0370*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*0380*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0390*/ BRA 0x390; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11kernel_cudaP8Particleiidi
.globl _Z11kernel_cudaP8Particleiidi
.p2align 8
.type _Z11kernel_cudaP8Particleiidi,@function
_Z11kernel_cudaP8Particleiidi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_clause 0x3
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0xc
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b32 s0, s[0:1], 0x18
s_ashr_i32 s1, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s1
s_xor_b32 s1, s2, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v0, s1
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[7:8], null, v1, 24, s[4:5]
v_mad_u64_u32 v[2:3], null, v1, s0, s[6:7]
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_sub_i32 s0, 0, s1
global_load_b96 v[4:6], v[7:8], off
v_cvt_u32_f32_e32 v0, v0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v1, s0, v0
v_add_nc_u32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v2, v2, v3
v_mul_hi_u32 v1, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v1
v_mul_hi_u32 v0, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s1
v_sub_nc_u32_e32 v0, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v1, s1, v0
v_cmp_le_u32_e32 vcc_lo, s1, v0
v_cndmask_b32_e32 v0, v0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v1, s1, v0
v_cmp_le_u32_e32 vcc_lo, s1, v0
v_cndmask_b32_e32 v0, v0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v3
v_sub_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v3, v0
v_add_f32_e32 v9, 0x3dcccccd, v3
v_add_f32_e32 v10, 0x3e4ccccd, v3
v_cvt_f64_f32_e32 v[0:1], v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f64_f32_e32 v[11:12], v9
v_cvt_f64_f32_e32 v[13:14], v10
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[15:16], v4
v_cvt_f64_f32_e32 v[4:5], v5
v_cvt_f64_f32_e32 v[17:18], v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[0:1], v[0:1], s[8:9], v[15:16]
v_fma_f64 v[4:5], v[11:12], s[8:9], v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[11:12], v[13:14], s[8:9], v[17:18]
v_cvt_f32_f64_e32 v0, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f32_f64_e32 v1, v[4:5]
v_cvt_f32_f64_e32 v2, v[11:12]
s_clause 0x1
global_store_b64 v[7:8], v[9:10], off offset:16
global_store_b128 v[7:8], v[0:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11kernel_cudaP8Particleiidi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 19
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11kernel_cudaP8Particleiidi, .Lfunc_end0-_Z11kernel_cudaP8Particleiidi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11kernel_cudaP8Particleiidi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11kernel_cudaP8Particleiidi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 19
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009a04a_00000000-6_particle.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3689:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3689:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10rand_floatiiii
.type _Z10rand_floatiiii, @function
_Z10rand_floatiiii:
.LFB3683:
.cfi_startproc
endbr64
imull %esi, %edi
leal (%rdi,%rdx), %eax
cltd
idivl %ecx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
ret
.cfi_endproc
.LFE3683:
.size _Z10rand_floatiiii, .-_Z10rand_floatiiii
.globl _Z6kernelP8Particleiidi
.type _Z6kernelP8Particleiidi, @function
_Z6kernelP8Particleiidi:
.LFB3684:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L13
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %r10
movl %esi, %edi
movapd %xmm0, %xmm3
movl %ecx, %r8d
leal 1(%rdx), %ebx
movslq %esi, %rax
leaq (%rax,%rax,2), %rax
leaq (%r10,%rax,8), %r9
movl $1, %r11d
pxor %xmm6, %xmm6
movss .LC1(%rip), %xmm5
movss .LC2(%rip), %xmm4
jmp .L6
.L7:
movl %esi, %eax
cltd
idivl %edi
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movaps %xmm0, %xmm2
addss %xmm6, %xmm2
movss %xmm2, 12(%rcx)
movaps %xmm0, %xmm1
addss %xmm5, %xmm1
movss %xmm1, 16(%rcx)
addss %xmm4, %xmm0
movss %xmm0, 20(%rcx)
pxor %xmm7, %xmm7
cvtss2sd (%rcx), %xmm7
cvtss2sd %xmm2, %xmm2
mulsd %xmm3, %xmm2
addsd %xmm7, %xmm2
cvtsd2ss %xmm2, %xmm2
movss %xmm2, (%rcx)
pxor %xmm2, %xmm2
cvtss2sd 4(%rcx), %xmm2
cvtss2sd %xmm1, %xmm1
mulsd %xmm3, %xmm1
addsd %xmm2, %xmm1
cvtsd2ss %xmm1, %xmm1
movss %xmm1, 4(%rcx)
pxor %xmm1, %xmm1
cvtss2sd 8(%rcx), %xmm1
cvtss2sd %xmm0, %xmm0
mulsd %xmm3, %xmm0
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 8(%rcx)
addl %r8d, %esi
addq $24, %rcx
cmpq %r9, %rcx
jne .L7
.L9:
addl $1, %r11d
cmpl %ebx, %r11d
je .L4
.L6:
movl %r11d, %esi
movq %r10, %rcx
testl %edi, %edi
jg .L7
jmp .L9
.L4:
popq %rbx
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore 3
ret
.cfi_endproc
.LFE3684:
.size _Z6kernelP8Particleiidi, .-_Z6kernelP8Particleiidi
.globl _Z14get_input_dataPP8Particleii
.type _Z14get_input_dataPP8Particleii, @function
_Z14get_input_dataPP8Particleii:
.LFB3685:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r13
movl %esi, %ebx
movl %edx, %r14d
movslq %esi, %rax
leaq (%rax,%rax,2), %rbp
salq $3, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
movl %r14d, %edi
call srand@PLT
testl %ebx, %ebx
jle .L17
movq %r12, %rbx
addq %r12, %rbp
.L18:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC3(%rip), %xmm0
addsd %xmm0, %xmm0
subsd .LC4(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC3(%rip), %xmm0
addsd %xmm0, %xmm0
subsd .LC4(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 4(%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC3(%rip), %xmm0
addsd %xmm0, %xmm0
subsd .LC4(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 8(%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC3(%rip), %xmm0
addsd %xmm0, %xmm0
subsd .LC4(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 12(%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC3(%rip), %xmm0
addsd %xmm0, %xmm0
subsd .LC4(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 16(%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
divsd .LC3(%rip), %xmm0
addsd %xmm0, %xmm0
subsd .LC4(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 20(%rbx)
addq $24, %rbx
cmpq %rbp, %rbx
jne .L18
.L17:
movq %r12, 0(%r13)
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3685:
.size _Z14get_input_dataPP8Particleii, .-_Z14get_input_dataPP8Particleii
.globl _Z11get_elapsed7timevalS_
.type _Z11get_elapsed7timevalS_, @function
_Z11get_elapsed7timevalS_:
.LFB3686:
.cfi_startproc
endbr64
subq %rdi, %rdx
pxor %xmm1, %xmm1
cvtsi2sdq %rdx, %xmm1
movsd %xmm1, -16(%rsp)
flds .LC5(%rip)
fld %st(0)
fmull -16(%rsp)
fxch %st(1)
subq %rsi, %rcx
pxor %xmm2, %xmm2
cvtsi2sdq %rcx, %xmm2
movsd %xmm2, -16(%rsp)
fdivrl -16(%rsp)
faddp %st, %st(1)
fstpl -16(%rsp)
movsd -16(%rsp), %xmm0
ret
.cfi_endproc
.LFE3686:
.size _Z11get_elapsed7timevalS_, .-_Z11get_elapsed7timevalS_
.globl _Z43__device_stub__Z11kernel_cudaP8ParticleiidiP8Particleiidi
.type _Z43__device_stub__Z11kernel_cudaP8ParticleiidiP8Particleiidi, @function
_Z43__device_stub__Z11kernel_cudaP8ParticleiidiP8Particleiidi:
.LFB3711:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movsd %xmm0, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11kernel_cudaP8Particleiidi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3711:
.size _Z43__device_stub__Z11kernel_cudaP8ParticleiidiP8Particleiidi, .-_Z43__device_stub__Z11kernel_cudaP8ParticleiidiP8Particleiidi
.globl _Z11kernel_cudaP8Particleiidi
.type _Z11kernel_cudaP8Particleiidi, @function
_Z11kernel_cudaP8Particleiidi:
.LFB3712:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z11kernel_cudaP8ParticleiidiP8Particleiidi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3712:
.size _Z11kernel_cudaP8Particleiidi, .-_Z11kernel_cudaP8Particleiidi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "Options:\n-n SIZE\t\tNum Particle\n-s ITERS\tNum Iters\n-p NTHREAD\tNumber of threads\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC8:
.string "n:p:s:h"
.section .rodata.str1.8
.align 8
.LC9:
.string "-------------------------------------------------------------\n"
.align 8
.LC10:
.string " N\tNum steps\tNum Threads\tNum Blocks\n"
.section .rodata.str1.1
.LC11:
.string "%4d %8d %14d %16d\n"
.section .rodata.str1.8
.align 8
.LC12:
.string "Running particle simulation on the CPU..."
.section .rodata.str1.1
.LC14:
.string "Done!\n"
.section .rodata.str1.8
.align 8
.LC15:
.string "Running particle simulation on the GPU..."
.align 8
.LC16:
.string "Comparing the output for each implementation..."
.section .rodata.str1.1
.LC19:
.string "Correct!\n"
.LC20:
.string "Not correct!\n"
.section .rodata.str1.8
.align 8
.LC21:
.string "Elapsed CPU (ms): %f / Elapsed GPU (ms): %f\n"
.text
.globl main
.type main, @function
main:
.LFB3682:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movl %edi, %r14d
movq %rsi, %r13
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
pxor %xmm0, %xmm0
movaps %xmm0, 80(%rsp)
movaps %xmm0, 96(%rsp)
movl $100, %ebp
movl $256, %ebx
movl $1000, %r12d
leaq .LC8(%rip), %r15
jmp .L51
.L33:
cmpl $115, %eax
jne .L51
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %ebp
jmp .L51
.L35:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %r12d
.L51:
movq %r15, %rdx
movq %r13, %rsi
movl %r14d, %edi
call getopt@PLT
cmpl $-1, %eax
je .L54
cmpl $112, %eax
je .L32
jg .L33
cmpl $104, %eax
je .L34
cmpl $110, %eax
je .L35
jmp .L51
.L32:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %ebx
jmp .L51
.L34:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L54:
leaq 40(%rsp), %rdi
movl $2020, %edx
movl %r12d, %esi
call _Z14get_input_dataPP8Particleii
movslq %r12d, %rax
leaq (%rax,%rax,2), %rax
leaq 0(,%rax,8), %r14
movq %r14, 24(%rsp)
leaq 48(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movq %r14, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq 40(%rsp), %r15
movl $1, %ecx
movq %r14, %rdx
movq %r15, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
leal -1(%r12,%rbx), %eax
cltd
idivl %ebx
movl %eax, %r14d
leaq .LC9(%rip), %r13
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r14d, %r9d
movl %ebx, %r8d
movl %ebp, %ecx
movl %r12d, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 80(%rsp), %r13
movl $0, %esi
movq %r13, %rdi
call gettimeofday@PLT
movl $2020, %ecx
movsd .LC13(%rip), %xmm0
movl %ebp, %edx
movl %r12d, %esi
movq %r15, %rdi
call _Z6kernelP8Particleiidi
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 96(%rsp), %rdx
movq 104(%rsp), %rcx
movq 80(%rsp), %rdi
movq 88(%rsp), %rsi
call _Z11get_elapsed7timevalS_
movsd %xmm0, 16(%rsp)
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq %r13, %rdi
call gettimeofday@PLT
testl %ebp, %ebp
jle .L40
movl $1, %r13d
jmp .L42
.L41:
addl $1, %r13d
cmpl %ebp, %r13d
jg .L40
.L42:
movl %ebx, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl %r14d, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L41
movl $2020, %ecx
movsd .LC13(%rip), %xmm0
movl %r13d, %edx
movl %r12d, %esi
movq 48(%rsp), %rdi
call _Z43__device_stub__Z11kernel_cudaP8ParticleiidiP8Particleiidi
jmp .L41
.L40:
movl $2, %ecx
movq 24(%rsp), %r14
movq %r14, %rdx
movq 48(%rsp), %rsi
movq 8(%rsp), %rbp
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 96(%rsp), %rdx
movq 104(%rsp), %rcx
movq 80(%rsp), %rdi
movq 88(%rsp), %rsi
call _Z11get_elapsed7timevalS_
movsd %xmm0, 24(%rsp)
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %r12d, %r12d
jle .L43
movq %r15, %rbx
addq %r15, %r14
movq %r14, %r12
pxor %xmm1, %xmm1
.L44:
movss (%rbx), %xmm2
subss 0(%rbp), %xmm2
andps .LC17(%rip), %xmm2
movaps %xmm2, %xmm0
call fmaxf@PLT
movaps %xmm0, %xmm1
addq $24, %rbx
addq $24, %rbp
cmpq %r12, %rbx
jne .L44
pxor %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movsd .LC18(%rip), %xmm0
comisd %xmm1, %xmm0
ja .L43
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L47
.L43:
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L47:
movsd 24(%rsp), %xmm1
movsd 16(%rsp), %xmm0
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r15, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L55
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3682:
.size main, .-main
.section .rodata.str1.1
.LC23:
.string "_Z11kernel_cudaP8Particleiidi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3714:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC23(%rip), %rdx
movq %rdx, %rcx
leaq _Z11kernel_cudaP8Particleiidi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3714:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1036831949
.align 4
.LC2:
.long 1045220557
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long -4194304
.long 1105199103
.align 8
.LC4:
.long 0
.long 1072693248
.section .rodata.cst4
.align 4
.LC5:
.long 1148846080
.section .rodata.cst8
.align 8
.LC13:
.long -1717986918
.long 1068079513
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC17:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC18:
.long -500134854
.long 1044740494
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "particle.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x3dcccccd # float 0.100000001
.LCPI0_1:
.long 0x3e4ccccd # float 0.200000003
.LCPI0_5:
.long 0x447a0000 # float 1000
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI0_2:
.quad 0x3fa999999999999a # double 0.050000000000000003
.LCPI0_4:
.quad 0x3e45798ee2308c3a # double 1.0E-8
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI0_3:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 336
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %r14d
xorps %xmm0, %xmm0
movaps %xmm0, 48(%rsp)
movaps %xmm0, 32(%rsp)
movl $1000, %r15d # imm = 0x3E8
movl $256, %ebp # imm = 0x100
movl $100, %r12d
jmp .LBB0_1
.p2align 4, 0x90
.LBB0_2: # in Loop: Header=BB0_1 Depth=1
cmpl $-1, %eax
je .LBB0_3
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl $.L.str, %edx
movl %r14d, %edi
movq %rbx, %rsi
callq getopt
# kill: def $eax killed $eax def $rax
leal -104(%rax), %ecx
cmpl $11, %ecx
ja .LBB0_2
# %bb.20: # in Loop: Header=BB0_1 Depth=1
jmpq *.LJTI0_0(,%rcx,8)
.LBB0_21: # in Loop: Header=BB0_1 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
jmp .LBB0_1
.LBB0_22: # in Loop: Header=BB0_1 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
jmp .LBB0_1
.LBB0_23: # in Loop: Header=BB0_1 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
jmp .LBB0_1
.LBB0_3:
leaq 168(%rsp), %rdi
movl %r15d, %esi
movl $2020, %edx # imm = 0x7E4
callq _Z14get_input_dataPP8Particleii
movslq %r15d, %r13
leaq (,%r13,8), %rax
leaq (%rax,%rax,2), %rbx
movq %rsp, %rdi
movq %rbx, %rsi
callq hipMalloc
movq %rbx, %rdi
callq malloc
movq %rax, 112(%rsp) # 8-byte Spill
movq (%rsp), %rdi
movq 168(%rsp), %r14
movq %r14, %rsi
movq %rbx, 8(%rsp) # 8-byte Spill
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
leal -1(%rbp,%r13), %eax
cltd
idivl %ebp
movl %eax, %ebx
movl $.Lstr.7, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
movl $.L.str.4, %edi
movl %r13d, %esi
movl %r12d, %edx
movl %ebp, %ecx
movl %ebx, %r8d
xorl %eax, %eax
callq printf
movl $.Lstr.7, %edi
callq puts@PLT
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl %r15d, %r10d
testl %r12d, %r12d
jle .LBB0_9
# %bb.4: # %.preheader.lr.ph.i
leal 1(%r12), %esi
leaq (,%r10,8), %rax
leaq (%rax,%rax,2), %rdi
movl $1, %r8d
movss .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI0_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movsd .LCPI0_2(%rip), %xmm2 # xmm2 = mem[0],zero
jmp .LBB0_5
.p2align 4, 0x90
.LBB0_8: # %._crit_edge.i
# in Loop: Header=BB0_5 Depth=1
incq %r8
cmpq %rsi, %r8
je .LBB0_9
.LBB0_5: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB0_7 Depth 2
testl %r15d, %r15d
jle .LBB0_8
# %bb.6: # %.lr.ph.i.preheader
# in Loop: Header=BB0_5 Depth=1
movl %r8d, %ecx
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB0_7: # %.lr.ph.i
# Parent Loop BB0_5 Depth=1
# => This Inner Loop Header: Depth=2
movl %ecx, %eax
cltd
idivl %r15d
xorps %xmm3, %xmm3
cvtsi2ss %edx, %xmm3
movss %xmm3, 12(%r14,%r9)
movaps %xmm3, %xmm4
addss %xmm0, %xmm4
movss %xmm4, 16(%r14,%r9)
xorps %xmm5, %xmm5
cvtss2sd %xmm3, %xmm5
addss %xmm1, %xmm3
movss %xmm3, 20(%r14,%r9)
mulsd %xmm2, %xmm5
movss (%r14,%r9), %xmm6 # xmm6 = mem[0],zero,zero,zero
cvtss2sd %xmm6, %xmm6
addsd %xmm5, %xmm6
xorps %xmm5, %xmm5
cvtsd2ss %xmm6, %xmm5
movss 4(%r14,%r9), %xmm6 # xmm6 = mem[0],zero,zero,zero
movss %xmm5, (%r14,%r9)
cvtss2sd %xmm4, %xmm4
mulsd %xmm2, %xmm4
xorps %xmm5, %xmm5
cvtss2sd %xmm6, %xmm5
addsd %xmm4, %xmm5
xorps %xmm4, %xmm4
cvtsd2ss %xmm5, %xmm4
movss %xmm4, 4(%r14,%r9)
cvtss2sd %xmm3, %xmm3
mulsd %xmm2, %xmm3
movss 8(%r14,%r9), %xmm4 # xmm4 = mem[0],zero,zero,zero
cvtss2sd %xmm4, %xmm4
addsd %xmm3, %xmm4
xorps %xmm3, %xmm3
cvtsd2ss %xmm4, %xmm3
movss %xmm3, 8(%r14,%r9)
addq $24, %r9
addl $2020, %ecx # imm = 0x7E4
cmpq %r9, %rdi
jne .LBB0_7
jmp .LBB0_8
.LBB0_9: # %_Z6kernelP8Particleiidi.exit
movq %r10, 72(%rsp) # 8-byte Spill
leaq 48(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 32(%rsp), %rax
movq %rax, 88(%rsp) # 8-byte Spill
movq 40(%rsp), %rax
movq %rax, 104(%rsp) # 8-byte Spill
movq 48(%rsp), %rax
movq %rax, 80(%rsp) # 8-byte Spill
movq 56(%rsp), %rax
movq %rax, 96(%rsp) # 8-byte Spill
movl $.Lstr.4, %edi
callq puts@PLT
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
testl %r12d, %r12d
jle .LBB0_14
# %bb.10: # %.lr.ph
movl %ebx, %r13d
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r13
movl %ebp, %ebp
orq %rax, %rbp
negl %r12d
movl $1, %ebx
jmp .LBB0_11
.p2align 4, 0x90
.LBB0_13: # in Loop: Header=BB0_11 Depth=1
leal (%r12,%rbx), %eax
incl %eax
movl %ebx, %ecx
incl %ecx
movl %ecx, %ebx
cmpl $1, %eax
je .LBB0_14
.LBB0_11: # =>This Inner Loop Header: Depth=1
movq %r13, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_13
# %bb.12: # in Loop: Header=BB0_11 Depth=1
movq (%rsp), %rax
movq %rax, 232(%rsp)
movl %r15d, 28(%rsp)
movl %ebx, 24(%rsp)
movabsq $4587366580439587226, %rax # imm = 0x3FA999999999999A
movq %rax, 224(%rsp)
movl $2020, 20(%rsp) # imm = 0x7E4
leaq 232(%rsp), %rax
movq %rax, 240(%rsp)
leaq 28(%rsp), %rax
movq %rax, 248(%rsp)
leaq 24(%rsp), %rax
movq %rax, 256(%rsp)
leaq 224(%rsp), %rax
movq %rax, 264(%rsp)
leaq 20(%rsp), %rax
movq %rax, 272(%rsp)
leaq 208(%rsp), %rdi
leaq 192(%rsp), %rsi
leaq 184(%rsp), %rdx
leaq 176(%rsp), %rcx
callq __hipPopCallConfiguration
movq 208(%rsp), %rsi
movl 216(%rsp), %edx
movq 192(%rsp), %rcx
movl 200(%rsp), %r8d
movl $_Z11kernel_cudaP8Particleiidi, %edi
leaq 240(%rsp), %r9
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB0_13
.LBB0_14: # %._crit_edge
movq (%rsp), %rsi
movq 112(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movq 8(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
leaq 48(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 32(%rsp), %rbp
movq 40(%rsp), %rax
movq %rax, 8(%rsp) # 8-byte Spill
movq 48(%rsp), %r12
movq 56(%rsp), %r13
movl $.Lstr.4, %edi
callq puts@PLT
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl $.Lstr.6, %edi
testl %r15d, %r15d
jle .LBB0_19
# %bb.15: # %.lr.ph73.preheader
movq 72(%rsp), %rax # 8-byte Reload
shlq $3, %rax
leaq (%rax,%rax,2), %rax
xorpd %xmm2, %xmm2
xorl %ecx, %ecx
movaps .LCPI0_3(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movapd %xmm2, %xmm0
.p2align 4, 0x90
.LBB0_16: # %.lr.ph73
# =>This Inner Loop Header: Depth=1
movss (%r14,%rcx), %xmm3 # xmm3 = mem[0],zero,zero,zero
subss (%rbx,%rcx), %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm0, %xmm0
movaps %xmm0, %xmm4
andps %xmm3, %xmm4
maxss %xmm2, %xmm3
andnps %xmm3, %xmm0
orps %xmm4, %xmm0
addq $24, %rcx
movaps %xmm0, %xmm2
cmpq %rcx, %rax
jne .LBB0_16
# %bb.17: # %._crit_edge74.loopexit
cvtss2sd %xmm0, %xmm0
movsd .LCPI0_4(%rip), %xmm1 # xmm1 = mem[0],zero
ucomisd %xmm0, %xmm1
ja .LBB0_19
# %bb.18:
movl $.Lstr.5, %edi
.LBB0_19: # %.critedge
callq puts@PLT
subq %rbp, %r12
xorps %xmm0, %xmm0
cvtsi2sd %r12, %xmm0
movsd %xmm0, 160(%rsp)
flds .LCPI0_5(%rip)
fld %st(0)
fmull 160(%rsp)
subq 8(%rsp), %r13 # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %r13, %xmm0
movsd %xmm0, 152(%rsp)
fld %st(1)
fdivrl 152(%rsp)
faddp %st, %st(1)
fstpl 128(%rsp)
movq 80(%rsp), %rax # 8-byte Reload
subq 88(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movsd 128(%rsp), %xmm1 # xmm1 = mem[0],zero
movsd %xmm0, 144(%rsp)
fld %st(0)
fmull 144(%rsp)
movq 96(%rsp), %rax # 8-byte Reload
subq 104(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movsd %xmm0, 136(%rsp)
fxch %st(1)
fdivrl 136(%rsp)
faddp %st, %st(1)
fstpl 120(%rsp)
movsd 120(%rsp), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.11, %edi
movb $2, %al
callq printf
movl $.Lstr.7, %edi
callq puts@PLT
movq %r14, %rdi
callq free
movq %rbx, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $280, %rsp # imm = 0x118
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_24:
.cfi_def_cfa_offset 336
movl $.Lstr.8, %edi
callq puts@PLT
movl $1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
.section .rodata,"a",@progbits
.p2align 3, 0x0
.LJTI0_0:
.quad .LBB0_24
.quad .LBB0_1
.quad .LBB0_1
.quad .LBB0_1
.quad .LBB0_1
.quad .LBB0_1
.quad .LBB0_21
.quad .LBB0_1
.quad .LBB0_22
.quad .LBB0_1
.quad .LBB0_1
.quad .LBB0_23
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z14get_input_dataPP8Particleii
.LCPI1_0:
.quad 0x41dfffffffc00000 # double 2147483647
.LCPI1_1:
.quad 0xbff0000000000000 # double -1
.text
.globl _Z14get_input_dataPP8Particleii
.p2align 4, 0x90
.type _Z14get_input_dataPP8Particleii,@function
_Z14get_input_dataPP8Particleii: # @_Z14get_input_dataPP8Particleii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r15d
movl %esi, %ebp
movq %rdi, %rbx
movslq %esi, %r12
leaq (,%r12,8), %rax
leaq (%rax,%rax,2), %rdi
callq malloc
movq %rax, %r14
movl %r15d, %edi
callq srand
testl %r12d, %r12d
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %eax
shlq $3, %rax
leaq (%rax,%rax,2), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
addsd %xmm0, %xmm0
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r14,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
addsd %xmm0, %xmm0
addsd .LCPI1_1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 4(%r14,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
addsd %xmm0, %xmm0
addsd .LCPI1_1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 8(%r14,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
addsd %xmm0, %xmm0
addsd .LCPI1_1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 12(%r14,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
addsd %xmm0, %xmm0
addsd .LCPI1_1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 16(%r14,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
addsd %xmm0, %xmm0
addsd .LCPI1_1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 20(%r14,%r12)
addq $24, %r12
cmpq %r12, %r15
jne .LBB1_2
.LBB1_3: # %._crit_edge
movq %r14, (%rbx)
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z14get_input_dataPP8Particleii, .Lfunc_end1-_Z14get_input_dataPP8Particleii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z6kernelP8Particleiidi
.LCPI2_0:
.long 0x3dcccccd # float 0.100000001
.LCPI2_1:
.long 0x3e4ccccd # float 0.200000003
.text
.globl _Z6kernelP8Particleiidi
.p2align 4, 0x90
.type _Z6kernelP8Particleiidi,@function
_Z6kernelP8Particleiidi: # @_Z6kernelP8Particleiidi
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB2_7
# %bb.1: # %.preheader.lr.ph
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %edx, %r8d
incl %r8d
movl %esi, %eax
shlq $3, %rax
leaq (%rax,%rax,2), %r10
movl $1, %r11d
movss .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss .LCPI2_1(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %r11
cmpq %r8, %r11
je .LBB2_6
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
testl %esi, %esi
jle .LBB2_5
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB2_2 Depth=1
movl %r11d, %r9d
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_4: # %.lr.ph
# Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movl %r9d, %eax
cltd
idivl %esi
xorps %xmm3, %xmm3
cvtsi2ss %edx, %xmm3
movss %xmm3, 12(%rdi,%rbx)
movaps %xmm3, %xmm4
addss %xmm1, %xmm4
movss %xmm4, 16(%rdi,%rbx)
xorps %xmm5, %xmm5
cvtss2sd %xmm3, %xmm5
addss %xmm2, %xmm3
movss %xmm3, 20(%rdi,%rbx)
mulsd %xmm0, %xmm5
movss (%rdi,%rbx), %xmm6 # xmm6 = mem[0],zero,zero,zero
cvtss2sd %xmm6, %xmm6
addsd %xmm5, %xmm6
xorps %xmm5, %xmm5
cvtsd2ss %xmm6, %xmm5
movss 4(%rdi,%rbx), %xmm6 # xmm6 = mem[0],zero,zero,zero
movss %xmm5, (%rdi,%rbx)
cvtss2sd %xmm4, %xmm4
mulsd %xmm0, %xmm4
xorps %xmm5, %xmm5
cvtss2sd %xmm6, %xmm5
addsd %xmm4, %xmm5
xorps %xmm4, %xmm4
cvtsd2ss %xmm5, %xmm4
movss %xmm4, 4(%rdi,%rbx)
cvtss2sd %xmm3, %xmm3
mulsd %xmm0, %xmm3
movss 8(%rdi,%rbx), %xmm4 # xmm4 = mem[0],zero,zero,zero
cvtss2sd %xmm4, %xmm4
addsd %xmm3, %xmm4
xorps %xmm3, %xmm3
cvtsd2ss %xmm4, %xmm3
movss %xmm3, 8(%rdi,%rbx)
addq $24, %rbx
addl %ecx, %r9d
cmpq %rbx, %r10
jne .LBB2_4
jmp .LBB2_5
.LBB2_6:
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.LBB2_7: # %._crit_edge43
retq
.Lfunc_end2:
.size _Z6kernelP8Particleiidi, .Lfunc_end2-_Z6kernelP8Particleiidi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11get_elapsed7timevalS_
.LCPI3_0:
.long 0x447a0000 # float 1000
.text
.globl _Z11get_elapsed7timevalS_
.p2align 4, 0x90
.type _Z11get_elapsed7timevalS_,@function
_Z11get_elapsed7timevalS_: # @_Z11get_elapsed7timevalS_
.cfi_startproc
# %bb.0:
subq %rdi, %rdx
cvtsi2sd %rdx, %xmm0
movsd %xmm0, -8(%rsp)
flds .LCPI3_0(%rip)
fld %st(0)
fmull -8(%rsp)
subq %rsi, %rcx
xorps %xmm0, %xmm0
cvtsi2sd %rcx, %xmm0
movsd %xmm0, -16(%rsp)
fxch %st(1)
fdivrl -16(%rsp)
faddp %st, %st(1)
fstpl -24(%rsp)
movsd -24(%rsp), %xmm0 # xmm0 = mem[0],zero
retq
.Lfunc_end3:
.size _Z11get_elapsed7timevalS_, .Lfunc_end3-_Z11get_elapsed7timevalS_
.cfi_endproc
# -- End function
.globl _Z26__device_stub__kernel_cudaP8Particleiidi # -- Begin function _Z26__device_stub__kernel_cudaP8Particleiidi
.p2align 4, 0x90
.type _Z26__device_stub__kernel_cudaP8Particleiidi,@function
_Z26__device_stub__kernel_cudaP8Particleiidi: # @_Z26__device_stub__kernel_cudaP8Particleiidi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movsd %xmm0, 64(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11kernel_cudaP8Particleiidi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z26__device_stub__kernel_cudaP8Particleiidi, .Lfunc_end4-_Z26__device_stub__kernel_cudaP8Particleiidi
.cfi_endproc
# -- End function
.globl _Z10rand_floatiiii # -- Begin function _Z10rand_floatiiii
.p2align 4, 0x90
.type _Z10rand_floatiiii,@function
_Z10rand_floatiiii: # @_Z10rand_floatiiii
.cfi_startproc
# %bb.0:
# kill: def $edx killed $edx def $rdx
# kill: def $edi killed $edi def $rdi
imull %esi, %edi
leal (%rdi,%rdx), %eax
cltd
idivl %ecx
cvtsi2ss %edx, %xmm0
retq
.Lfunc_end5:
.size _Z10rand_floatiiii, .Lfunc_end5-_Z10rand_floatiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11kernel_cudaP8Particleiidi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "n:p:s:h"
.size .L.str, 8
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%4d %8d %14d %16d\n"
.size .L.str.4, 19
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Running particle simulation on the CPU..."
.size .L.str.5, 42
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Running particle simulation on the GPU..."
.size .L.str.7, 42
.type _Z11kernel_cudaP8Particleiidi,@object # @_Z11kernel_cudaP8Particleiidi
.section .rodata,"a",@progbits
.globl _Z11kernel_cudaP8Particleiidi
.p2align 3, 0x0
_Z11kernel_cudaP8Particleiidi:
.quad _Z26__device_stub__kernel_cudaP8Particleiidi
.size _Z11kernel_cudaP8Particleiidi, 8
.type .L.str.8,@object # @.str.8
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.8:
.asciz "Comparing the output for each implementation..."
.size .L.str.8, 48
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Elapsed CPU (ms): %f / Elapsed GPU (ms): %f\n"
.size .L.str.11, 45
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11kernel_cudaP8Particleiidi"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz " N\tNum steps\tNum Threads\tNum Blocks"
.size .Lstr.1, 37
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Done!"
.size .Lstr.4, 6
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "Not correct!"
.size .Lstr.5, 13
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "Correct!"
.size .Lstr.6, 9
.type .Lstr.7,@object # @str.7
.Lstr.7:
.asciz "-------------------------------------------------------------"
.size .Lstr.7, 62
.type .Lstr.8,@object # @str.8
.Lstr.8:
.asciz "Options:\n-n SIZE\t\tNum Particle\n-s ITERS\tNum Iters\n-p NTHREAD\tNumber of threads"
.size .Lstr.8, 79
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__kernel_cudaP8Particleiidi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11kernel_cudaP8Particleiidi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C"
__global__ void multiply(long n, float *a, float *b, float *output) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<n) {
output[i] = a[i] + b[i];
}
} | code for sm_80
Function : multiply
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.AND.EX P0, PT, R3, c[0x0][0x164], PT, P0 ; /* 0x0000590003007a0c */
/* 0x000fda0003f06300 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.SHL.U32 R6, R0.reuse, 0x4, RZ ; /* 0x0000000400067824 */
/* 0x040fe200078e00ff */
/*0090*/ SHF.L.U64.HI R0, R0, 0x2, R3 ; /* 0x0000000200007819 */
/* 0x000fe20000010203 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00b0*/ IADD3 R4, P0, R6.reuse, c[0x0][0x168], RZ ; /* 0x00005a0006047a10 */
/* 0x040fe40007f1e0ff */
/*00c0*/ IADD3 R2, P1, R6, c[0x0][0x170], RZ ; /* 0x00005c0006027a10 */
/* 0x000fe40007f3e0ff */
/*00d0*/ IADD3.X R5, R0.reuse, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0000057a10 */
/* 0x040fe400007fe4ff */
/*00e0*/ IADD3.X R3, R0, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0000037a10 */
/* 0x000fc80000ffe4ff */
/*00f0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IADD3 R6, P0, R6, c[0x0][0x178], RZ ; /* 0x00005e0006067a10 */
/* 0x000fc80007f1e0ff */
/*0120*/ IADD3.X R7, R0, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f0000077a10 */
/* 0x000fe200007fe4ff */
/*0130*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*0140*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
__global__ void multiply(long n, float *a, float *b, float *output) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<n) {
output[i] = a[i] + b[i];
}
} | .file "tmpxft_0013bc68_00000000-6_product.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z8multiplylPfS_S_lPfS_S_
.type _Z32__device_stub__Z8multiplylPfS_S_lPfS_S_, @function
_Z32__device_stub__Z8multiplylPfS_S_lPfS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq multiply(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z8multiplylPfS_S_lPfS_S_, .-_Z32__device_stub__Z8multiplylPfS_S_lPfS_S_
.globl multiply
.type multiply, @function
multiply:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8multiplylPfS_S_lPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size multiply, .-multiply
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "multiply"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq multiply(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
__global__ void multiply(long n, float *a, float *b, float *output) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<n) {
output[i] = a[i] + b[i];
}
} | #include <hip/hip_runtime.h>
extern "C"
__global__ void multiply(long n, float *a, float *b, float *output) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<n) {
output[i] = a[i] + b[i];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__ void multiply(long n, float *a, float *b, float *output) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<n) {
output[i] = a[i] + b[i];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected multiply
.globl multiply
.p2align 8
.type multiply,@function
multiply:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel multiply
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size multiply, .Lfunc_end0-multiply
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: multiply
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: multiply.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__ void multiply(long n, float *a, float *b, float *output) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i<n) {
output[i] = a[i] + b[i];
}
} | .text
.file "product.hip"
.globl __device_stub__multiply # -- Begin function __device_stub__multiply
.p2align 4, 0x90
.type __device_stub__multiply,@function
__device_stub__multiply: # @__device_stub__multiply
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $multiply, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__multiply, .Lfunc_end0-__device_stub__multiply
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $multiply, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type multiply,@object # @multiply
.section .rodata,"a",@progbits
.globl multiply
.p2align 3, 0x0
multiply:
.quad __device_stub__multiply
.size multiply, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "multiply"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__multiply
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym multiply
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : multiply
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.AND.EX P0, PT, R3, c[0x0][0x164], PT, P0 ; /* 0x0000590003007a0c */
/* 0x000fda0003f06300 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.SHL.U32 R6, R0.reuse, 0x4, RZ ; /* 0x0000000400067824 */
/* 0x040fe200078e00ff */
/*0090*/ SHF.L.U64.HI R0, R0, 0x2, R3 ; /* 0x0000000200007819 */
/* 0x000fe20000010203 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00b0*/ IADD3 R4, P0, R6.reuse, c[0x0][0x168], RZ ; /* 0x00005a0006047a10 */
/* 0x040fe40007f1e0ff */
/*00c0*/ IADD3 R2, P1, R6, c[0x0][0x170], RZ ; /* 0x00005c0006027a10 */
/* 0x000fe40007f3e0ff */
/*00d0*/ IADD3.X R5, R0.reuse, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0000057a10 */
/* 0x040fe400007fe4ff */
/*00e0*/ IADD3.X R3, R0, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0000037a10 */
/* 0x000fc80000ffe4ff */
/*00f0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IADD3 R6, P0, R6, c[0x0][0x178], RZ ; /* 0x00005e0006067a10 */
/* 0x000fc80007f1e0ff */
/*0120*/ IADD3.X R7, R0, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f0000077a10 */
/* 0x000fe200007fe4ff */
/*0130*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*0140*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected multiply
.globl multiply
.p2align 8
.type multiply,@function
multiply:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel multiply
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size multiply, .Lfunc_end0-multiply
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: multiply
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: multiply.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013bc68_00000000-6_product.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z8multiplylPfS_S_lPfS_S_
.type _Z32__device_stub__Z8multiplylPfS_S_lPfS_S_, @function
_Z32__device_stub__Z8multiplylPfS_S_lPfS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq multiply(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z8multiplylPfS_S_lPfS_S_, .-_Z32__device_stub__Z8multiplylPfS_S_lPfS_S_
.globl multiply
.type multiply, @function
multiply:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8multiplylPfS_S_lPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size multiply, .-multiply
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "multiply"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq multiply(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "product.hip"
.globl __device_stub__multiply # -- Begin function __device_stub__multiply
.p2align 4, 0x90
.type __device_stub__multiply,@function
__device_stub__multiply: # @__device_stub__multiply
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $multiply, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__multiply, .Lfunc_end0-__device_stub__multiply
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $multiply, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type multiply,@object # @multiply
.section .rodata,"a",@progbits
.globl multiply
.p2align 3, 0x0
multiply:
.quad __device_stub__multiply
.size multiply, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "multiply"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__multiply
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym multiply
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
// CUDA kernel. Each thread takes care of one element of c
__global__ void hello_cuda() {
printf("hello from the GPU\n");
}
int main( int argc, char* argv[] )
{
// Execute the kernel
hello_cuda<<<1, 1>>>();
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z10hello_cudav
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
// CUDA kernel. Each thread takes care of one element of c
__global__ void hello_cuda() {
printf("hello from the GPU\n");
}
int main( int argc, char* argv[] )
{
// Execute the kernel
hello_cuda<<<1, 1>>>();
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_0009432f_00000000-6_HelloCuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10hello_cudavv
.type _Z29__device_stub__Z10hello_cudavv, @function
_Z29__device_stub__Z10hello_cudavv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10hello_cudav(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10hello_cudavv, .-_Z29__device_stub__Z10hello_cudavv
.globl _Z10hello_cudav
.type _Z10hello_cudav, @function
_Z10hello_cudav:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10hello_cudavv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10hello_cudav, .-_Z10hello_cudav
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z29__device_stub__Z10hello_cudavv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10hello_cudav"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10hello_cudav(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
// CUDA kernel. Each thread takes care of one element of c
__global__ void hello_cuda() {
printf("hello from the GPU\n");
}
int main( int argc, char* argv[] )
{
// Execute the kernel
hello_cuda<<<1, 1>>>();
cudaDeviceSynchronize();
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
// CUDA kernel. Each thread takes care of one element of c
__global__ void hello_cuda() {
printf("hello from the GPU\n");
}
int main( int argc, char* argv[] )
{
// Execute the kernel
hello_cuda<<<1, 1>>>();
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
// CUDA kernel. Each thread takes care of one element of c
__global__ void hello_cuda() {
printf("hello from the GPU\n");
}
int main( int argc, char* argv[] )
{
// Execute the kernel
hello_cuda<<<1, 1>>>();
hipDeviceSynchronize();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10hello_cudav
.globl _Z10hello_cudav
.p2align 8
.type _Z10hello_cudav,@function
_Z10hello_cudav:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 20
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10hello_cudav
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10hello_cudav, .Lfunc_end0-_Z10hello_cudav
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "hello from the GPU\n"
.size .str, 20
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10hello_cudav
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z10hello_cudav.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
// CUDA kernel. Each thread takes care of one element of c
__global__ void hello_cuda() {
printf("hello from the GPU\n");
}
int main( int argc, char* argv[] )
{
// Execute the kernel
hello_cuda<<<1, 1>>>();
hipDeviceSynchronize();
return 0;
} | .text
.file "HelloCuda.hip"
.globl _Z25__device_stub__hello_cudav # -- Begin function _Z25__device_stub__hello_cudav
.p2align 4, 0x90
.type _Z25__device_stub__hello_cudav,@function
_Z25__device_stub__hello_cudav: # @_Z25__device_stub__hello_cudav
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10hello_cudav, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__hello_cudav, .Lfunc_end0-_Z25__device_stub__hello_cudav
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10hello_cudav, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10hello_cudav, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10hello_cudav,@object # @_Z10hello_cudav
.section .rodata,"a",@progbits
.globl _Z10hello_cudav
.p2align 3, 0x0
_Z10hello_cudav:
.quad _Z25__device_stub__hello_cudav
.size _Z10hello_cudav, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10hello_cudav"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__hello_cudav
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10hello_cudav
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10hello_cudav
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10hello_cudav
.globl _Z10hello_cudav
.p2align 8
.type _Z10hello_cudav,@function
_Z10hello_cudav:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 20
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10hello_cudav
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10hello_cudav, .Lfunc_end0-_Z10hello_cudav
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "hello from the GPU\n"
.size .str, 20
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10hello_cudav
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z10hello_cudav.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009432f_00000000-6_HelloCuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10hello_cudavv
.type _Z29__device_stub__Z10hello_cudavv, @function
_Z29__device_stub__Z10hello_cudavv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10hello_cudav(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10hello_cudavv, .-_Z29__device_stub__Z10hello_cudavv
.globl _Z10hello_cudav
.type _Z10hello_cudav, @function
_Z10hello_cudav:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10hello_cudavv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10hello_cudav, .-_Z10hello_cudav
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z29__device_stub__Z10hello_cudavv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10hello_cudav"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10hello_cudav(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "HelloCuda.hip"
.globl _Z25__device_stub__hello_cudav # -- Begin function _Z25__device_stub__hello_cudav
.p2align 4, 0x90
.type _Z25__device_stub__hello_cudav,@function
_Z25__device_stub__hello_cudav: # @_Z25__device_stub__hello_cudav
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10hello_cudav, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__hello_cudav, .Lfunc_end0-_Z25__device_stub__hello_cudav
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10hello_cudav, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10hello_cudav, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10hello_cudav,@object # @_Z10hello_cudav
.section .rodata,"a",@progbits
.globl _Z10hello_cudav
.p2align 3, 0x0
_Z10hello_cudav:
.quad _Z25__device_stub__hello_cudav
.size _Z10hello_cudav, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10hello_cudav"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__hello_cudav
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10hello_cudav
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <math.h>
#include <float.h>
#define IDX2C(i,j,rows) (((j)*(rows))+(i))
__global__ void matrixPlusVector(float* input, float* bias, float * output, int rows, int columns)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
output[ij] = input[ij] + bias[i];
}
}
__global__ void matrixTanh(float* input, float* output, int rows, int columns)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
output[ij] = tanh(input[ij]);
}
}
__global__ void matrixIncorporateTanhDeriv(float* base, float* activation, float* output, int rows, int columns)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
output[ij] = base[ij] * (1 + activation[ij])*(1 - activation[ij]);
}
}
__global__ void matrixReLu(float* input, float* output, int rows, int columns)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
output[ij] = fmaxf(input[ij], 0);
}
}
__global__ void matrixIncorporateReLuDeriv(float* base, float* activation, float* output, int rows, int columns)
{
int j = blockDim.x * blockIdx.x + threadIdx.x;
int i = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
output[ij] = activation[ij] <= 0 ? 0 : base[ij];
}
}
__global__ void matrixSigmoid(float* input, float* output, int rows, int columns)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
// how to refactor the sigmoid calculation???
output[ij] = (tanhf((input[ij]) / 2) + 1) / 2.0f;
}
}
__global__ void matrixIncorporateSigmoidDeriv(float* base, float* activation, float* output, int rows, int columns)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
output[ij] = base[ij] * activation[ij] * (1 - activation[ij]);
}
}
__global__ void matrixCrossEntropyError(float* sigmoidScores, float* trueLabels, float* output, int rows, int columns)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
output[ij] = trueLabels[ij] > 0 ? logf(sigmoidScores[ij] + FLT_EPSILON) : logf(1 - sigmoidScores[ij] + FLT_EPSILON);
output[ij] *= -1;
}
}
__global__ void matrixBellmanErrorAndDeriv(float* predictedQValues, float* maxQHatValues, float* chosenActionIndices, float* currentRewards, float* error, float* errorDerivative,
float discount, float* isLastEpisode, int rows, int columns)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
float y = isLastEpisode[j] > 0 ? currentRewards[j] : currentRewards[j] + (discount*maxQHatValues[j]);
errorDerivative[ij] = 0;
// Calculating error and errorDerivative
if (i == chosenActionIndices[j])
{
float tmp = predictedQValues[i] - y;
errorDerivative[ij] = tmp;
error[j] = 0.5*tmp*tmp;
}
}
}
__global__ void DqnStanfordEvaluation(float* predictedactionIndices, float* chosenActionIndices, float* currentRewards, float* matchPredictRewards, float* nonMatchPredictRewards, int rows)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < rows)
{
if (predictedactionIndices[i] == chosenActionIndices[i])
{
matchPredictRewards[i] = currentRewards[i];
}
else
{
nonMatchPredictRewards[i] = currentRewards[i];
}
}
}
__global__ void matrixHadamard(float* input1, float* input2, float alpha, float* output, float beta, int rows, int columns)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
output[ij] = alpha*input1[ij] * input2[ij] + beta*output[ij];
}
}
__global__ void columnwiseMax(float* input, float* output, int rows, int columns)
{
int j = blockDim.x * blockIdx.x + threadIdx.x;
if (j < columns)
{
float maxInColumn = input[IDX2C(0, j, rows)];
for (int i = 0; i < rows; i++)
{
int ij = IDX2C(i, j, rows);
if (input[ij] > maxInColumn)
{
maxInColumn = input[ij];
}
}
output[j] = maxInColumn;
}
}
__global__ void columnwiseMaxIndex(float* input, float* output, int rows, int columns)
{
int j = blockDim.x * blockIdx.x + threadIdx.x;
if (j < columns)
{
int maxInColumnIndex = 0;
float maxInColumn = input[IDX2C(maxInColumnIndex, j, rows)];
for (int i = 0; i < rows; i++)
{
int ij = IDX2C(i, j, rows);
if (input[ij] > maxInColumn)
{
maxInColumn = input[ij];
maxInColumnIndex = i;
}
}
output[j] = (float)maxInColumnIndex;
}
}
int main()
{
return 0;
} | .file "tmpxft_000ca958_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
movl $0, %eax
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z42__device_stub__Z16matrixPlusVectorPfS_S_iiPfS_S_ii
.type _Z42__device_stub__Z16matrixPlusVectorPfS_S_iiPfS_S_ii, @function
_Z42__device_stub__Z16matrixPlusVectorPfS_S_iiPfS_S_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L8
.L4:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16matrixPlusVectorPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L4
.L9:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z42__device_stub__Z16matrixPlusVectorPfS_S_iiPfS_S_ii, .-_Z42__device_stub__Z16matrixPlusVectorPfS_S_iiPfS_S_ii
.globl _Z16matrixPlusVectorPfS_S_ii
.type _Z16matrixPlusVectorPfS_S_ii, @function
_Z16matrixPlusVectorPfS_S_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z16matrixPlusVectorPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z16matrixPlusVectorPfS_S_ii, .-_Z16matrixPlusVectorPfS_S_ii
.globl _Z34__device_stub__Z10matrixTanhPfS_iiPfS_ii
.type _Z34__device_stub__Z10matrixTanhPfS_iiPfS_ii, @function
_Z34__device_stub__Z10matrixTanhPfS_iiPfS_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10matrixTanhPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z34__device_stub__Z10matrixTanhPfS_iiPfS_ii, .-_Z34__device_stub__Z10matrixTanhPfS_iiPfS_ii
.globl _Z10matrixTanhPfS_ii
.type _Z10matrixTanhPfS_ii, @function
_Z10matrixTanhPfS_ii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10matrixTanhPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10matrixTanhPfS_ii, .-_Z10matrixTanhPfS_ii
.globl _Z52__device_stub__Z26matrixIncorporateTanhDerivPfS_S_iiPfS_S_ii
.type _Z52__device_stub__Z26matrixIncorporateTanhDerivPfS_S_iiPfS_S_ii, @function
_Z52__device_stub__Z26matrixIncorporateTanhDerivPfS_S_iiPfS_S_ii:
.LFB2086:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26matrixIncorporateTanhDerivPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z52__device_stub__Z26matrixIncorporateTanhDerivPfS_S_iiPfS_S_ii, .-_Z52__device_stub__Z26matrixIncorporateTanhDerivPfS_S_iiPfS_S_ii
.globl _Z26matrixIncorporateTanhDerivPfS_S_ii
.type _Z26matrixIncorporateTanhDerivPfS_S_ii, @function
_Z26matrixIncorporateTanhDerivPfS_S_ii:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z26matrixIncorporateTanhDerivPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z26matrixIncorporateTanhDerivPfS_S_ii, .-_Z26matrixIncorporateTanhDerivPfS_S_ii
.globl _Z34__device_stub__Z10matrixReLuPfS_iiPfS_ii
.type _Z34__device_stub__Z10matrixReLuPfS_iiPfS_ii, @function
_Z34__device_stub__Z10matrixReLuPfS_iiPfS_ii:
.LFB2088:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L32
.L28:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10matrixReLuPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L28
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z34__device_stub__Z10matrixReLuPfS_iiPfS_ii, .-_Z34__device_stub__Z10matrixReLuPfS_iiPfS_ii
.globl _Z10matrixReLuPfS_ii
.type _Z10matrixReLuPfS_ii, @function
_Z10matrixReLuPfS_ii:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10matrixReLuPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z10matrixReLuPfS_ii, .-_Z10matrixReLuPfS_ii
.globl _Z52__device_stub__Z26matrixIncorporateReLuDerivPfS_S_iiPfS_S_ii
.type _Z52__device_stub__Z26matrixIncorporateReLuDerivPfS_S_iiPfS_S_ii, @function
_Z52__device_stub__Z26matrixIncorporateReLuDerivPfS_S_iiPfS_S_ii:
.LFB2090:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L40
.L36:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L41
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26matrixIncorporateReLuDerivPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L36
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z52__device_stub__Z26matrixIncorporateReLuDerivPfS_S_iiPfS_S_ii, .-_Z52__device_stub__Z26matrixIncorporateReLuDerivPfS_S_iiPfS_S_ii
.globl _Z26matrixIncorporateReLuDerivPfS_S_ii
.type _Z26matrixIncorporateReLuDerivPfS_S_ii, @function
_Z26matrixIncorporateReLuDerivPfS_S_ii:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z26matrixIncorporateReLuDerivPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z26matrixIncorporateReLuDerivPfS_S_ii, .-_Z26matrixIncorporateReLuDerivPfS_S_ii
.globl _Z37__device_stub__Z13matrixSigmoidPfS_iiPfS_ii
.type _Z37__device_stub__Z13matrixSigmoidPfS_iiPfS_ii, @function
_Z37__device_stub__Z13matrixSigmoidPfS_iiPfS_ii:
.LFB2092:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L48
.L44:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L49
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13matrixSigmoidPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L44
.L49:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2092:
.size _Z37__device_stub__Z13matrixSigmoidPfS_iiPfS_ii, .-_Z37__device_stub__Z13matrixSigmoidPfS_iiPfS_ii
.globl _Z13matrixSigmoidPfS_ii
.type _Z13matrixSigmoidPfS_ii, @function
_Z13matrixSigmoidPfS_ii:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13matrixSigmoidPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _Z13matrixSigmoidPfS_ii, .-_Z13matrixSigmoidPfS_ii
.globl _Z55__device_stub__Z29matrixIncorporateSigmoidDerivPfS_S_iiPfS_S_ii
.type _Z55__device_stub__Z29matrixIncorporateSigmoidDerivPfS_S_iiPfS_S_ii, @function
_Z55__device_stub__Z29matrixIncorporateSigmoidDerivPfS_S_iiPfS_S_ii:
.LFB2094:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L56
.L52:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L57
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L56:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z29matrixIncorporateSigmoidDerivPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L52
.L57:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2094:
.size _Z55__device_stub__Z29matrixIncorporateSigmoidDerivPfS_S_iiPfS_S_ii, .-_Z55__device_stub__Z29matrixIncorporateSigmoidDerivPfS_S_iiPfS_S_ii
.globl _Z29matrixIncorporateSigmoidDerivPfS_S_ii
.type _Z29matrixIncorporateSigmoidDerivPfS_S_ii, @function
_Z29matrixIncorporateSigmoidDerivPfS_S_ii:
.LFB2095:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z29matrixIncorporateSigmoidDerivPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _Z29matrixIncorporateSigmoidDerivPfS_S_ii, .-_Z29matrixIncorporateSigmoidDerivPfS_S_ii
.globl _Z49__device_stub__Z23matrixCrossEntropyErrorPfS_S_iiPfS_S_ii
.type _Z49__device_stub__Z23matrixCrossEntropyErrorPfS_S_iiPfS_S_ii, @function
_Z49__device_stub__Z23matrixCrossEntropyErrorPfS_S_iiPfS_S_ii:
.LFB2096:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L64
.L60:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L65
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L64:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23matrixCrossEntropyErrorPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L60
.L65:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2096:
.size _Z49__device_stub__Z23matrixCrossEntropyErrorPfS_S_iiPfS_S_ii, .-_Z49__device_stub__Z23matrixCrossEntropyErrorPfS_S_iiPfS_S_ii
.globl _Z23matrixCrossEntropyErrorPfS_S_ii
.type _Z23matrixCrossEntropyErrorPfS_S_ii, @function
_Z23matrixCrossEntropyErrorPfS_S_ii:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z23matrixCrossEntropyErrorPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _Z23matrixCrossEntropyErrorPfS_S_ii, .-_Z23matrixCrossEntropyErrorPfS_S_ii
.globl _Z61__device_stub__Z26matrixBellmanErrorAndDerivPfS_S_S_S_S_fS_iiPfS_S_S_S_S_fS_ii
.type _Z61__device_stub__Z26matrixBellmanErrorAndDerivPfS_S_S_S_S_fS_iiPfS_S_S_S_S_fS_ii, @function
_Z61__device_stub__Z26matrixBellmanErrorAndDerivPfS_S_S_S_S_fS_iiPfS_S_S_S_S_fS_ii:
.LFB2098:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movss %xmm0, 12(%rsp)
movq 240(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
movq %rsp, %rax
movq %rax, 184(%rsp)
leaq 248(%rsp), %rax
movq %rax, 192(%rsp)
leaq 256(%rsp), %rax
movq %rax, 200(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L72
.L68:
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L73
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L72:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 248
pushq 72(%rsp)
.cfi_def_cfa_offset 256
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z26matrixBellmanErrorAndDerivPfS_S_S_S_S_fS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 240
jmp .L68
.L73:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2098:
.size _Z61__device_stub__Z26matrixBellmanErrorAndDerivPfS_S_S_S_S_fS_iiPfS_S_S_S_S_fS_ii, .-_Z61__device_stub__Z26matrixBellmanErrorAndDerivPfS_S_S_S_S_fS_iiPfS_S_S_S_S_fS_ii
.globl _Z26matrixBellmanErrorAndDerivPfS_S_S_S_S_fS_ii
.type _Z26matrixBellmanErrorAndDerivPfS_S_S_S_S_fS_ii, @function
_Z26matrixBellmanErrorAndDerivPfS_S_S_S_S_fS_ii:
.LFB2099:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z61__device_stub__Z26matrixBellmanErrorAndDerivPfS_S_S_S_S_fS_iiPfS_S_S_S_S_fS_ii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _Z26matrixBellmanErrorAndDerivPfS_S_S_S_S_fS_ii, .-_Z26matrixBellmanErrorAndDerivPfS_S_S_S_S_fS_ii
.globl _Z50__device_stub__Z21DqnStanfordEvaluationPfS_S_S_S_iPfS_S_S_S_i
.type _Z50__device_stub__Z21DqnStanfordEvaluationPfS_S_S_S_iPfS_S_S_S_i, @function
_Z50__device_stub__Z21DqnStanfordEvaluationPfS_S_S_S_iPfS_S_S_S_i:
.LFB2100:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L80
.L76:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L81
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L80:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z21DqnStanfordEvaluationPfS_S_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L76
.L81:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2100:
.size _Z50__device_stub__Z21DqnStanfordEvaluationPfS_S_S_S_iPfS_S_S_S_i, .-_Z50__device_stub__Z21DqnStanfordEvaluationPfS_S_S_S_iPfS_S_S_S_i
.globl _Z21DqnStanfordEvaluationPfS_S_S_S_i
.type _Z21DqnStanfordEvaluationPfS_S_S_S_i, @function
_Z21DqnStanfordEvaluationPfS_S_S_S_i:
.LFB2101:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z21DqnStanfordEvaluationPfS_S_S_S_iPfS_S_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2101:
.size _Z21DqnStanfordEvaluationPfS_S_S_S_i, .-_Z21DqnStanfordEvaluationPfS_S_S_S_i
.globl _Z42__device_stub__Z14matrixHadamardPfS_fS_fiiPfS_fS_fii
.type _Z42__device_stub__Z14matrixHadamardPfS_fS_fiiPfS_fS_fii, @function
_Z42__device_stub__Z14matrixHadamardPfS_fS_fiiPfS_fS_fii:
.LFB2102:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movss %xmm0, 28(%rsp)
movq %rdx, 16(%rsp)
movss %xmm1, 24(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L88
.L84:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L89
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L88:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14matrixHadamardPfS_fS_fii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L84
.L89:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2102:
.size _Z42__device_stub__Z14matrixHadamardPfS_fS_fiiPfS_fS_fii, .-_Z42__device_stub__Z14matrixHadamardPfS_fS_fiiPfS_fS_fii
.globl _Z14matrixHadamardPfS_fS_fii
.type _Z14matrixHadamardPfS_fS_fii, @function
_Z14matrixHadamardPfS_fS_fii:
.LFB2103:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z14matrixHadamardPfS_fS_fiiPfS_fS_fii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2103:
.size _Z14matrixHadamardPfS_fS_fii, .-_Z14matrixHadamardPfS_fS_fii
.globl _Z37__device_stub__Z13columnwiseMaxPfS_iiPfS_ii
.type _Z37__device_stub__Z13columnwiseMaxPfS_iiPfS_ii, @function
_Z37__device_stub__Z13columnwiseMaxPfS_iiPfS_ii:
.LFB2104:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L96
.L92:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L97
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L96:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13columnwiseMaxPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L92
.L97:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2104:
.size _Z37__device_stub__Z13columnwiseMaxPfS_iiPfS_ii, .-_Z37__device_stub__Z13columnwiseMaxPfS_iiPfS_ii
.globl _Z13columnwiseMaxPfS_ii
.type _Z13columnwiseMaxPfS_ii, @function
_Z13columnwiseMaxPfS_ii:
.LFB2105:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13columnwiseMaxPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2105:
.size _Z13columnwiseMaxPfS_ii, .-_Z13columnwiseMaxPfS_ii
.globl _Z42__device_stub__Z18columnwiseMaxIndexPfS_iiPfS_ii
.type _Z42__device_stub__Z18columnwiseMaxIndexPfS_iiPfS_ii, @function
_Z42__device_stub__Z18columnwiseMaxIndexPfS_iiPfS_ii:
.LFB2106:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L104
.L100:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L105
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L104:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18columnwiseMaxIndexPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L100
.L105:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2106:
.size _Z42__device_stub__Z18columnwiseMaxIndexPfS_iiPfS_ii, .-_Z42__device_stub__Z18columnwiseMaxIndexPfS_iiPfS_ii
.globl _Z18columnwiseMaxIndexPfS_ii
.type _Z18columnwiseMaxIndexPfS_ii, @function
_Z18columnwiseMaxIndexPfS_ii:
.LFB2107:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18columnwiseMaxIndexPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2107:
.size _Z18columnwiseMaxIndexPfS_ii, .-_Z18columnwiseMaxIndexPfS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18columnwiseMaxIndexPfS_ii"
.LC1:
.string "_Z13columnwiseMaxPfS_ii"
.LC2:
.string "_Z14matrixHadamardPfS_fS_fii"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "_Z21DqnStanfordEvaluationPfS_S_S_S_i"
.align 8
.LC4:
.string "_Z26matrixBellmanErrorAndDerivPfS_S_S_S_S_fS_ii"
.align 8
.LC5:
.string "_Z23matrixCrossEntropyErrorPfS_S_ii"
.align 8
.LC6:
.string "_Z29matrixIncorporateSigmoidDerivPfS_S_ii"
.section .rodata.str1.1
.LC7:
.string "_Z13matrixSigmoidPfS_ii"
.section .rodata.str1.8
.align 8
.LC8:
.string "_Z26matrixIncorporateReLuDerivPfS_S_ii"
.section .rodata.str1.1
.LC9:
.string "_Z10matrixReLuPfS_ii"
.section .rodata.str1.8
.align 8
.LC10:
.string "_Z26matrixIncorporateTanhDerivPfS_S_ii"
.section .rodata.str1.1
.LC11:
.string "_Z10matrixTanhPfS_ii"
.LC12:
.string "_Z16matrixPlusVectorPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2109:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18columnwiseMaxIndexPfS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13columnwiseMaxPfS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z14matrixHadamardPfS_fS_fii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z21DqnStanfordEvaluationPfS_S_S_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z26matrixBellmanErrorAndDerivPfS_S_S_S_S_fS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z23matrixCrossEntropyErrorPfS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z29matrixIncorporateSigmoidDerivPfS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z13matrixSigmoidPfS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z26matrixIncorporateReLuDerivPfS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matrixReLuPfS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z26matrixIncorporateTanhDerivPfS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matrixTanhPfS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z16matrixPlusVectorPfS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2109:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <math.h>
#include <float.h>
#define IDX2C(i,j,rows) (((j)*(rows))+(i))
__global__ void matrixPlusVector(float* input, float* bias, float * output, int rows, int columns)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
output[ij] = input[ij] + bias[i];
}
}
__global__ void matrixTanh(float* input, float* output, int rows, int columns)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
output[ij] = tanh(input[ij]);
}
}
__global__ void matrixIncorporateTanhDeriv(float* base, float* activation, float* output, int rows, int columns)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
output[ij] = base[ij] * (1 + activation[ij])*(1 - activation[ij]);
}
}
__global__ void matrixReLu(float* input, float* output, int rows, int columns)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
output[ij] = fmaxf(input[ij], 0);
}
}
__global__ void matrixIncorporateReLuDeriv(float* base, float* activation, float* output, int rows, int columns)
{
int j = blockDim.x * blockIdx.x + threadIdx.x;
int i = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
output[ij] = activation[ij] <= 0 ? 0 : base[ij];
}
}
__global__ void matrixSigmoid(float* input, float* output, int rows, int columns)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
// how to refactor the sigmoid calculation???
output[ij] = (tanhf((input[ij]) / 2) + 1) / 2.0f;
}
}
__global__ void matrixIncorporateSigmoidDeriv(float* base, float* activation, float* output, int rows, int columns)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
output[ij] = base[ij] * activation[ij] * (1 - activation[ij]);
}
}
__global__ void matrixCrossEntropyError(float* sigmoidScores, float* trueLabels, float* output, int rows, int columns)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
output[ij] = trueLabels[ij] > 0 ? logf(sigmoidScores[ij] + FLT_EPSILON) : logf(1 - sigmoidScores[ij] + FLT_EPSILON);
output[ij] *= -1;
}
}
__global__ void matrixBellmanErrorAndDeriv(float* predictedQValues, float* maxQHatValues, float* chosenActionIndices, float* currentRewards, float* error, float* errorDerivative,
float discount, float* isLastEpisode, int rows, int columns)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
float y = isLastEpisode[j] > 0 ? currentRewards[j] : currentRewards[j] + (discount*maxQHatValues[j]);
errorDerivative[ij] = 0;
// Calculating error and errorDerivative
if (i == chosenActionIndices[j])
{
float tmp = predictedQValues[i] - y;
errorDerivative[ij] = tmp;
error[j] = 0.5*tmp*tmp;
}
}
}
__global__ void DqnStanfordEvaluation(float* predictedactionIndices, float* chosenActionIndices, float* currentRewards, float* matchPredictRewards, float* nonMatchPredictRewards, int rows)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < rows)
{
if (predictedactionIndices[i] == chosenActionIndices[i])
{
matchPredictRewards[i] = currentRewards[i];
}
else
{
nonMatchPredictRewards[i] = currentRewards[i];
}
}
}
__global__ void matrixHadamard(float* input1, float* input2, float alpha, float* output, float beta, int rows, int columns)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
output[ij] = alpha*input1[ij] * input2[ij] + beta*output[ij];
}
}
__global__ void columnwiseMax(float* input, float* output, int rows, int columns)
{
int j = blockDim.x * blockIdx.x + threadIdx.x;
if (j < columns)
{
float maxInColumn = input[IDX2C(0, j, rows)];
for (int i = 0; i < rows; i++)
{
int ij = IDX2C(i, j, rows);
if (input[ij] > maxInColumn)
{
maxInColumn = input[ij];
}
}
output[j] = maxInColumn;
}
}
__global__ void columnwiseMaxIndex(float* input, float* output, int rows, int columns)
{
int j = blockDim.x * blockIdx.x + threadIdx.x;
if (j < columns)
{
int maxInColumnIndex = 0;
float maxInColumn = input[IDX2C(maxInColumnIndex, j, rows)];
for (int i = 0; i < rows; i++)
{
int ij = IDX2C(i, j, rows);
if (input[ij] > maxInColumn)
{
maxInColumn = input[ij];
maxInColumnIndex = i;
}
}
output[j] = (float)maxInColumnIndex;
}
}
int main()
{
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <math.h>
#include <float.h>
#define IDX2C(i,j,rows) (((j)*(rows))+(i))
__global__ void matrixPlusVector(float* input, float* bias, float * output, int rows, int columns)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
output[ij] = input[ij] + bias[i];
}
}
__global__ void matrixTanh(float* input, float* output, int rows, int columns)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
output[ij] = tanh(input[ij]);
}
}
__global__ void matrixIncorporateTanhDeriv(float* base, float* activation, float* output, int rows, int columns)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
output[ij] = base[ij] * (1 + activation[ij])*(1 - activation[ij]);
}
}
__global__ void matrixReLu(float* input, float* output, int rows, int columns)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
output[ij] = fmaxf(input[ij], 0);
}
}
__global__ void matrixIncorporateReLuDeriv(float* base, float* activation, float* output, int rows, int columns)
{
int j = blockDim.x * blockIdx.x + threadIdx.x;
int i = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
output[ij] = activation[ij] <= 0 ? 0 : base[ij];
}
}
__global__ void matrixSigmoid(float* input, float* output, int rows, int columns)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
// how to refactor the sigmoid calculation???
output[ij] = (tanhf((input[ij]) / 2) + 1) / 2.0f;
}
}
__global__ void matrixIncorporateSigmoidDeriv(float* base, float* activation, float* output, int rows, int columns)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
output[ij] = base[ij] * activation[ij] * (1 - activation[ij]);
}
}
__global__ void matrixCrossEntropyError(float* sigmoidScores, float* trueLabels, float* output, int rows, int columns)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
output[ij] = trueLabels[ij] > 0 ? logf(sigmoidScores[ij] + FLT_EPSILON) : logf(1 - sigmoidScores[ij] + FLT_EPSILON);
output[ij] *= -1;
}
}
__global__ void matrixBellmanErrorAndDeriv(float* predictedQValues, float* maxQHatValues, float* chosenActionIndices, float* currentRewards, float* error, float* errorDerivative,
float discount, float* isLastEpisode, int rows, int columns)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
float y = isLastEpisode[j] > 0 ? currentRewards[j] : currentRewards[j] + (discount*maxQHatValues[j]);
errorDerivative[ij] = 0;
// Calculating error and errorDerivative
if (i == chosenActionIndices[j])
{
float tmp = predictedQValues[i] - y;
errorDerivative[ij] = tmp;
error[j] = 0.5*tmp*tmp;
}
}
}
__global__ void DqnStanfordEvaluation(float* predictedactionIndices, float* chosenActionIndices, float* currentRewards, float* matchPredictRewards, float* nonMatchPredictRewards, int rows)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < rows)
{
if (predictedactionIndices[i] == chosenActionIndices[i])
{
matchPredictRewards[i] = currentRewards[i];
}
else
{
nonMatchPredictRewards[i] = currentRewards[i];
}
}
}
__global__ void matrixHadamard(float* input1, float* input2, float alpha, float* output, float beta, int rows, int columns)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
output[ij] = alpha*input1[ij] * input2[ij] + beta*output[ij];
}
}
__global__ void columnwiseMax(float* input, float* output, int rows, int columns)
{
int j = blockDim.x * blockIdx.x + threadIdx.x;
if (j < columns)
{
float maxInColumn = input[IDX2C(0, j, rows)];
for (int i = 0; i < rows; i++)
{
int ij = IDX2C(i, j, rows);
if (input[ij] > maxInColumn)
{
maxInColumn = input[ij];
}
}
output[j] = maxInColumn;
}
}
__global__ void columnwiseMaxIndex(float* input, float* output, int rows, int columns)
{
int j = blockDim.x * blockIdx.x + threadIdx.x;
if (j < columns)
{
int maxInColumnIndex = 0;
float maxInColumn = input[IDX2C(maxInColumnIndex, j, rows)];
for (int i = 0; i < rows; i++)
{
int ij = IDX2C(i, j, rows);
if (input[ij] > maxInColumn)
{
maxInColumn = input[ij];
maxInColumnIndex = i;
}
}
output[j] = (float)maxInColumnIndex;
}
}
int main()
{
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <math.h>
#include <float.h>
#define IDX2C(i,j,rows) (((j)*(rows))+(i))
__global__ void matrixPlusVector(float* input, float* bias, float * output, int rows, int columns)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
output[ij] = input[ij] + bias[i];
}
}
__global__ void matrixTanh(float* input, float* output, int rows, int columns)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
output[ij] = tanh(input[ij]);
}
}
__global__ void matrixIncorporateTanhDeriv(float* base, float* activation, float* output, int rows, int columns)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
output[ij] = base[ij] * (1 + activation[ij])*(1 - activation[ij]);
}
}
__global__ void matrixReLu(float* input, float* output, int rows, int columns)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
output[ij] = fmaxf(input[ij], 0);
}
}
__global__ void matrixIncorporateReLuDeriv(float* base, float* activation, float* output, int rows, int columns)
{
int j = blockDim.x * blockIdx.x + threadIdx.x;
int i = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
output[ij] = activation[ij] <= 0 ? 0 : base[ij];
}
}
__global__ void matrixSigmoid(float* input, float* output, int rows, int columns)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
// how to refactor the sigmoid calculation???
output[ij] = (tanhf((input[ij]) / 2) + 1) / 2.0f;
}
}
__global__ void matrixIncorporateSigmoidDeriv(float* base, float* activation, float* output, int rows, int columns)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
output[ij] = base[ij] * activation[ij] * (1 - activation[ij]);
}
}
__global__ void matrixCrossEntropyError(float* sigmoidScores, float* trueLabels, float* output, int rows, int columns)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
output[ij] = trueLabels[ij] > 0 ? logf(sigmoidScores[ij] + FLT_EPSILON) : logf(1 - sigmoidScores[ij] + FLT_EPSILON);
output[ij] *= -1;
}
}
__global__ void matrixBellmanErrorAndDeriv(float* predictedQValues, float* maxQHatValues, float* chosenActionIndices, float* currentRewards, float* error, float* errorDerivative,
float discount, float* isLastEpisode, int rows, int columns)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
float y = isLastEpisode[j] > 0 ? currentRewards[j] : currentRewards[j] + (discount*maxQHatValues[j]);
errorDerivative[ij] = 0;
// Calculating error and errorDerivative
if (i == chosenActionIndices[j])
{
float tmp = predictedQValues[i] - y;
errorDerivative[ij] = tmp;
error[j] = 0.5*tmp*tmp;
}
}
}
__global__ void DqnStanfordEvaluation(float* predictedactionIndices, float* chosenActionIndices, float* currentRewards, float* matchPredictRewards, float* nonMatchPredictRewards, int rows)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < rows)
{
if (predictedactionIndices[i] == chosenActionIndices[i])
{
matchPredictRewards[i] = currentRewards[i];
}
else
{
nonMatchPredictRewards[i] = currentRewards[i];
}
}
}
__global__ void matrixHadamard(float* input1, float* input2, float alpha, float* output, float beta, int rows, int columns)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
int j = blockDim.y * blockIdx.y + threadIdx.y;
if (i < rows && j < columns)
{
int ij = IDX2C(i, j, rows);
output[ij] = alpha*input1[ij] * input2[ij] + beta*output[ij];
}
}
__global__ void columnwiseMax(float* input, float* output, int rows, int columns)
{
int j = blockDim.x * blockIdx.x + threadIdx.x;
if (j < columns)
{
float maxInColumn = input[IDX2C(0, j, rows)];
for (int i = 0; i < rows; i++)
{
int ij = IDX2C(i, j, rows);
if (input[ij] > maxInColumn)
{
maxInColumn = input[ij];
}
}
output[j] = maxInColumn;
}
}
__global__ void columnwiseMaxIndex(float* input, float* output, int rows, int columns)
{
int j = blockDim.x * blockIdx.x + threadIdx.x;
if (j < columns)
{
int maxInColumnIndex = 0;
float maxInColumn = input[IDX2C(maxInColumnIndex, j, rows)];
for (int i = 0; i < rows; i++)
{
int ij = IDX2C(i, j, rows);
if (input[ij] > maxInColumn)
{
maxInColumn = input[ij];
maxInColumnIndex = i;
}
}
output[j] = (float)maxInColumnIndex;
}
}
int main()
{
return 0;
} | .text
.file "kernel.hip"
.globl _Z31__device_stub__matrixPlusVectorPfS_S_ii # -- Begin function _Z31__device_stub__matrixPlusVectorPfS_S_ii
.p2align 4, 0x90
.type _Z31__device_stub__matrixPlusVectorPfS_S_ii,@function
_Z31__device_stub__matrixPlusVectorPfS_S_ii: # @_Z31__device_stub__matrixPlusVectorPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16matrixPlusVectorPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__matrixPlusVectorPfS_S_ii, .Lfunc_end0-_Z31__device_stub__matrixPlusVectorPfS_S_ii
.cfi_endproc
# -- End function
.globl _Z25__device_stub__matrixTanhPfS_ii # -- Begin function _Z25__device_stub__matrixTanhPfS_ii
.p2align 4, 0x90
.type _Z25__device_stub__matrixTanhPfS_ii,@function
_Z25__device_stub__matrixTanhPfS_ii: # @_Z25__device_stub__matrixTanhPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10matrixTanhPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z25__device_stub__matrixTanhPfS_ii, .Lfunc_end1-_Z25__device_stub__matrixTanhPfS_ii
.cfi_endproc
# -- End function
.globl _Z41__device_stub__matrixIncorporateTanhDerivPfS_S_ii # -- Begin function _Z41__device_stub__matrixIncorporateTanhDerivPfS_S_ii
.p2align 4, 0x90
.type _Z41__device_stub__matrixIncorporateTanhDerivPfS_S_ii,@function
_Z41__device_stub__matrixIncorporateTanhDerivPfS_S_ii: # @_Z41__device_stub__matrixIncorporateTanhDerivPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26matrixIncorporateTanhDerivPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z41__device_stub__matrixIncorporateTanhDerivPfS_S_ii, .Lfunc_end2-_Z41__device_stub__matrixIncorporateTanhDerivPfS_S_ii
.cfi_endproc
# -- End function
.globl _Z25__device_stub__matrixReLuPfS_ii # -- Begin function _Z25__device_stub__matrixReLuPfS_ii
.p2align 4, 0x90
.type _Z25__device_stub__matrixReLuPfS_ii,@function
_Z25__device_stub__matrixReLuPfS_ii: # @_Z25__device_stub__matrixReLuPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10matrixReLuPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z25__device_stub__matrixReLuPfS_ii, .Lfunc_end3-_Z25__device_stub__matrixReLuPfS_ii
.cfi_endproc
# -- End function
.globl _Z41__device_stub__matrixIncorporateReLuDerivPfS_S_ii # -- Begin function _Z41__device_stub__matrixIncorporateReLuDerivPfS_S_ii
.p2align 4, 0x90
.type _Z41__device_stub__matrixIncorporateReLuDerivPfS_S_ii,@function
_Z41__device_stub__matrixIncorporateReLuDerivPfS_S_ii: # @_Z41__device_stub__matrixIncorporateReLuDerivPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26matrixIncorporateReLuDerivPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z41__device_stub__matrixIncorporateReLuDerivPfS_S_ii, .Lfunc_end4-_Z41__device_stub__matrixIncorporateReLuDerivPfS_S_ii
.cfi_endproc
# -- End function
.globl _Z28__device_stub__matrixSigmoidPfS_ii # -- Begin function _Z28__device_stub__matrixSigmoidPfS_ii
.p2align 4, 0x90
.type _Z28__device_stub__matrixSigmoidPfS_ii,@function
_Z28__device_stub__matrixSigmoidPfS_ii: # @_Z28__device_stub__matrixSigmoidPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13matrixSigmoidPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end5:
.size _Z28__device_stub__matrixSigmoidPfS_ii, .Lfunc_end5-_Z28__device_stub__matrixSigmoidPfS_ii
.cfi_endproc
# -- End function
.globl _Z44__device_stub__matrixIncorporateSigmoidDerivPfS_S_ii # -- Begin function _Z44__device_stub__matrixIncorporateSigmoidDerivPfS_S_ii
.p2align 4, 0x90
.type _Z44__device_stub__matrixIncorporateSigmoidDerivPfS_S_ii,@function
_Z44__device_stub__matrixIncorporateSigmoidDerivPfS_S_ii: # @_Z44__device_stub__matrixIncorporateSigmoidDerivPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z29matrixIncorporateSigmoidDerivPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end6:
.size _Z44__device_stub__matrixIncorporateSigmoidDerivPfS_S_ii, .Lfunc_end6-_Z44__device_stub__matrixIncorporateSigmoidDerivPfS_S_ii
.cfi_endproc
# -- End function
.globl _Z38__device_stub__matrixCrossEntropyErrorPfS_S_ii # -- Begin function _Z38__device_stub__matrixCrossEntropyErrorPfS_S_ii
.p2align 4, 0x90
.type _Z38__device_stub__matrixCrossEntropyErrorPfS_S_ii,@function
_Z38__device_stub__matrixCrossEntropyErrorPfS_S_ii: # @_Z38__device_stub__matrixCrossEntropyErrorPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23matrixCrossEntropyErrorPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end7:
.size _Z38__device_stub__matrixCrossEntropyErrorPfS_S_ii, .Lfunc_end7-_Z38__device_stub__matrixCrossEntropyErrorPfS_S_ii
.cfi_endproc
# -- End function
.globl _Z41__device_stub__matrixBellmanErrorAndDerivPfS_S_S_S_S_fS_ii # -- Begin function _Z41__device_stub__matrixBellmanErrorAndDerivPfS_S_S_S_S_fS_ii
.p2align 4, 0x90
.type _Z41__device_stub__matrixBellmanErrorAndDerivPfS_S_S_S_S_fS_ii,@function
_Z41__device_stub__matrixBellmanErrorAndDerivPfS_S_S_S_S_fS_ii: # @_Z41__device_stub__matrixBellmanErrorAndDerivPfS_S_S_S_S_fS_ii
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movss %xmm0, 12(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 208(%rsp), %rax
movq %rax, 168(%rsp)
leaq 216(%rsp), %rax
movq %rax, 176(%rsp)
leaq 224(%rsp), %rax
movq %rax, 184(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z26matrixBellmanErrorAndDerivPfS_S_S_S_S_fS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end8:
.size _Z41__device_stub__matrixBellmanErrorAndDerivPfS_S_S_S_S_fS_ii, .Lfunc_end8-_Z41__device_stub__matrixBellmanErrorAndDerivPfS_S_S_S_S_fS_ii
.cfi_endproc
# -- End function
.globl _Z36__device_stub__DqnStanfordEvaluationPfS_S_S_S_i # -- Begin function _Z36__device_stub__DqnStanfordEvaluationPfS_S_S_S_i
.p2align 4, 0x90
.type _Z36__device_stub__DqnStanfordEvaluationPfS_S_S_S_i,@function
_Z36__device_stub__DqnStanfordEvaluationPfS_S_S_S_i: # @_Z36__device_stub__DqnStanfordEvaluationPfS_S_S_S_i
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z21DqnStanfordEvaluationPfS_S_S_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end9:
.size _Z36__device_stub__DqnStanfordEvaluationPfS_S_S_S_i, .Lfunc_end9-_Z36__device_stub__DqnStanfordEvaluationPfS_S_S_S_i
.cfi_endproc
# -- End function
.globl _Z29__device_stub__matrixHadamardPfS_fS_fii # -- Begin function _Z29__device_stub__matrixHadamardPfS_fS_fii
.p2align 4, 0x90
.type _Z29__device_stub__matrixHadamardPfS_fS_fii,@function
_Z29__device_stub__matrixHadamardPfS_fS_fii: # @_Z29__device_stub__matrixHadamardPfS_fS_fii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movss %xmm0, 20(%rsp)
movq %rdx, 72(%rsp)
movss %xmm1, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14matrixHadamardPfS_fS_fii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end10:
.size _Z29__device_stub__matrixHadamardPfS_fS_fii, .Lfunc_end10-_Z29__device_stub__matrixHadamardPfS_fS_fii
.cfi_endproc
# -- End function
.globl _Z28__device_stub__columnwiseMaxPfS_ii # -- Begin function _Z28__device_stub__columnwiseMaxPfS_ii
.p2align 4, 0x90
.type _Z28__device_stub__columnwiseMaxPfS_ii,@function
_Z28__device_stub__columnwiseMaxPfS_ii: # @_Z28__device_stub__columnwiseMaxPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13columnwiseMaxPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end11:
.size _Z28__device_stub__columnwiseMaxPfS_ii, .Lfunc_end11-_Z28__device_stub__columnwiseMaxPfS_ii
.cfi_endproc
# -- End function
.globl _Z33__device_stub__columnwiseMaxIndexPfS_ii # -- Begin function _Z33__device_stub__columnwiseMaxIndexPfS_ii
.p2align 4, 0x90
.type _Z33__device_stub__columnwiseMaxIndexPfS_ii,@function
_Z33__device_stub__columnwiseMaxIndexPfS_ii: # @_Z33__device_stub__columnwiseMaxIndexPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18columnwiseMaxIndexPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end12:
.size _Z33__device_stub__columnwiseMaxIndexPfS_ii, .Lfunc_end12-_Z33__device_stub__columnwiseMaxIndexPfS_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
xorl %eax, %eax
retq
.Lfunc_end13:
.size main, .Lfunc_end13-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB14_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB14_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16matrixPlusVectorPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matrixTanhPfS_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26matrixIncorporateTanhDerivPfS_S_ii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matrixReLuPfS_ii, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26matrixIncorporateReLuDerivPfS_S_ii, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13matrixSigmoidPfS_ii, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z29matrixIncorporateSigmoidDerivPfS_S_ii, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23matrixCrossEntropyErrorPfS_S_ii, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26matrixBellmanErrorAndDerivPfS_S_S_S_S_fS_ii, %esi
movl $.L__unnamed_9, %edx
movl $.L__unnamed_9, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21DqnStanfordEvaluationPfS_S_S_S_i, %esi
movl $.L__unnamed_10, %edx
movl $.L__unnamed_10, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14matrixHadamardPfS_fS_fii, %esi
movl $.L__unnamed_11, %edx
movl $.L__unnamed_11, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13columnwiseMaxPfS_ii, %esi
movl $.L__unnamed_12, %edx
movl $.L__unnamed_12, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18columnwiseMaxIndexPfS_ii, %esi
movl $.L__unnamed_13, %edx
movl $.L__unnamed_13, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end14:
.size __hip_module_ctor, .Lfunc_end14-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB15_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB15_2:
retq
.Lfunc_end15:
.size __hip_module_dtor, .Lfunc_end15-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16matrixPlusVectorPfS_S_ii,@object # @_Z16matrixPlusVectorPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z16matrixPlusVectorPfS_S_ii
.p2align 3, 0x0
_Z16matrixPlusVectorPfS_S_ii:
.quad _Z31__device_stub__matrixPlusVectorPfS_S_ii
.size _Z16matrixPlusVectorPfS_S_ii, 8
.type _Z10matrixTanhPfS_ii,@object # @_Z10matrixTanhPfS_ii
.globl _Z10matrixTanhPfS_ii
.p2align 3, 0x0
_Z10matrixTanhPfS_ii:
.quad _Z25__device_stub__matrixTanhPfS_ii
.size _Z10matrixTanhPfS_ii, 8
.type _Z26matrixIncorporateTanhDerivPfS_S_ii,@object # @_Z26matrixIncorporateTanhDerivPfS_S_ii
.globl _Z26matrixIncorporateTanhDerivPfS_S_ii
.p2align 3, 0x0
_Z26matrixIncorporateTanhDerivPfS_S_ii:
.quad _Z41__device_stub__matrixIncorporateTanhDerivPfS_S_ii
.size _Z26matrixIncorporateTanhDerivPfS_S_ii, 8
.type _Z10matrixReLuPfS_ii,@object # @_Z10matrixReLuPfS_ii
.globl _Z10matrixReLuPfS_ii
.p2align 3, 0x0
_Z10matrixReLuPfS_ii:
.quad _Z25__device_stub__matrixReLuPfS_ii
.size _Z10matrixReLuPfS_ii, 8
.type _Z26matrixIncorporateReLuDerivPfS_S_ii,@object # @_Z26matrixIncorporateReLuDerivPfS_S_ii
.globl _Z26matrixIncorporateReLuDerivPfS_S_ii
.p2align 3, 0x0
_Z26matrixIncorporateReLuDerivPfS_S_ii:
.quad _Z41__device_stub__matrixIncorporateReLuDerivPfS_S_ii
.size _Z26matrixIncorporateReLuDerivPfS_S_ii, 8
.type _Z13matrixSigmoidPfS_ii,@object # @_Z13matrixSigmoidPfS_ii
.globl _Z13matrixSigmoidPfS_ii
.p2align 3, 0x0
_Z13matrixSigmoidPfS_ii:
.quad _Z28__device_stub__matrixSigmoidPfS_ii
.size _Z13matrixSigmoidPfS_ii, 8
.type _Z29matrixIncorporateSigmoidDerivPfS_S_ii,@object # @_Z29matrixIncorporateSigmoidDerivPfS_S_ii
.globl _Z29matrixIncorporateSigmoidDerivPfS_S_ii
.p2align 3, 0x0
_Z29matrixIncorporateSigmoidDerivPfS_S_ii:
.quad _Z44__device_stub__matrixIncorporateSigmoidDerivPfS_S_ii
.size _Z29matrixIncorporateSigmoidDerivPfS_S_ii, 8
.type _Z23matrixCrossEntropyErrorPfS_S_ii,@object # @_Z23matrixCrossEntropyErrorPfS_S_ii
.globl _Z23matrixCrossEntropyErrorPfS_S_ii
.p2align 3, 0x0
_Z23matrixCrossEntropyErrorPfS_S_ii:
.quad _Z38__device_stub__matrixCrossEntropyErrorPfS_S_ii
.size _Z23matrixCrossEntropyErrorPfS_S_ii, 8
.type _Z26matrixBellmanErrorAndDerivPfS_S_S_S_S_fS_ii,@object # @_Z26matrixBellmanErrorAndDerivPfS_S_S_S_S_fS_ii
.globl _Z26matrixBellmanErrorAndDerivPfS_S_S_S_S_fS_ii
.p2align 3, 0x0
_Z26matrixBellmanErrorAndDerivPfS_S_S_S_S_fS_ii:
.quad _Z41__device_stub__matrixBellmanErrorAndDerivPfS_S_S_S_S_fS_ii
.size _Z26matrixBellmanErrorAndDerivPfS_S_S_S_S_fS_ii, 8
.type _Z21DqnStanfordEvaluationPfS_S_S_S_i,@object # @_Z21DqnStanfordEvaluationPfS_S_S_S_i
.globl _Z21DqnStanfordEvaluationPfS_S_S_S_i
.p2align 3, 0x0
_Z21DqnStanfordEvaluationPfS_S_S_S_i:
.quad _Z36__device_stub__DqnStanfordEvaluationPfS_S_S_S_i
.size _Z21DqnStanfordEvaluationPfS_S_S_S_i, 8
.type _Z14matrixHadamardPfS_fS_fii,@object # @_Z14matrixHadamardPfS_fS_fii
.globl _Z14matrixHadamardPfS_fS_fii
.p2align 3, 0x0
_Z14matrixHadamardPfS_fS_fii:
.quad _Z29__device_stub__matrixHadamardPfS_fS_fii
.size _Z14matrixHadamardPfS_fS_fii, 8
.type _Z13columnwiseMaxPfS_ii,@object # @_Z13columnwiseMaxPfS_ii
.globl _Z13columnwiseMaxPfS_ii
.p2align 3, 0x0
_Z13columnwiseMaxPfS_ii:
.quad _Z28__device_stub__columnwiseMaxPfS_ii
.size _Z13columnwiseMaxPfS_ii, 8
.type _Z18columnwiseMaxIndexPfS_ii,@object # @_Z18columnwiseMaxIndexPfS_ii
.globl _Z18columnwiseMaxIndexPfS_ii
.p2align 3, 0x0
_Z18columnwiseMaxIndexPfS_ii:
.quad _Z33__device_stub__columnwiseMaxIndexPfS_ii
.size _Z18columnwiseMaxIndexPfS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16matrixPlusVectorPfS_S_ii"
.size .L__unnamed_1, 29
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10matrixTanhPfS_ii"
.size .L__unnamed_2, 21
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z26matrixIncorporateTanhDerivPfS_S_ii"
.size .L__unnamed_3, 39
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z10matrixReLuPfS_ii"
.size .L__unnamed_4, 21
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z26matrixIncorporateReLuDerivPfS_S_ii"
.size .L__unnamed_5, 39
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z13matrixSigmoidPfS_ii"
.size .L__unnamed_6, 24
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "_Z29matrixIncorporateSigmoidDerivPfS_S_ii"
.size .L__unnamed_7, 42
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "_Z23matrixCrossEntropyErrorPfS_S_ii"
.size .L__unnamed_8, 36
.type .L__unnamed_9,@object # @8
.L__unnamed_9:
.asciz "_Z26matrixBellmanErrorAndDerivPfS_S_S_S_S_fS_ii"
.size .L__unnamed_9, 48
.type .L__unnamed_10,@object # @9
.L__unnamed_10:
.asciz "_Z21DqnStanfordEvaluationPfS_S_S_S_i"
.size .L__unnamed_10, 37
.type .L__unnamed_11,@object # @10
.L__unnamed_11:
.asciz "_Z14matrixHadamardPfS_fS_fii"
.size .L__unnamed_11, 29
.type .L__unnamed_12,@object # @11
.L__unnamed_12:
.asciz "_Z13columnwiseMaxPfS_ii"
.size .L__unnamed_12, 24
.type .L__unnamed_13,@object # @12
.L__unnamed_13:
.asciz "_Z18columnwiseMaxIndexPfS_ii"
.size .L__unnamed_13, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__matrixPlusVectorPfS_S_ii
.addrsig_sym _Z25__device_stub__matrixTanhPfS_ii
.addrsig_sym _Z41__device_stub__matrixIncorporateTanhDerivPfS_S_ii
.addrsig_sym _Z25__device_stub__matrixReLuPfS_ii
.addrsig_sym _Z41__device_stub__matrixIncorporateReLuDerivPfS_S_ii
.addrsig_sym _Z28__device_stub__matrixSigmoidPfS_ii
.addrsig_sym _Z44__device_stub__matrixIncorporateSigmoidDerivPfS_S_ii
.addrsig_sym _Z38__device_stub__matrixCrossEntropyErrorPfS_S_ii
.addrsig_sym _Z41__device_stub__matrixBellmanErrorAndDerivPfS_S_S_S_S_fS_ii
.addrsig_sym _Z36__device_stub__DqnStanfordEvaluationPfS_S_S_S_i
.addrsig_sym _Z29__device_stub__matrixHadamardPfS_fS_fii
.addrsig_sym _Z28__device_stub__columnwiseMaxPfS_ii
.addrsig_sym _Z33__device_stub__columnwiseMaxIndexPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16matrixPlusVectorPfS_S_ii
.addrsig_sym _Z10matrixTanhPfS_ii
.addrsig_sym _Z26matrixIncorporateTanhDerivPfS_S_ii
.addrsig_sym _Z10matrixReLuPfS_ii
.addrsig_sym _Z26matrixIncorporateReLuDerivPfS_S_ii
.addrsig_sym _Z13matrixSigmoidPfS_ii
.addrsig_sym _Z29matrixIncorporateSigmoidDerivPfS_S_ii
.addrsig_sym _Z23matrixCrossEntropyErrorPfS_S_ii
.addrsig_sym _Z26matrixBellmanErrorAndDerivPfS_S_S_S_S_fS_ii
.addrsig_sym _Z21DqnStanfordEvaluationPfS_S_S_S_i
.addrsig_sym _Z14matrixHadamardPfS_fS_fii
.addrsig_sym _Z13columnwiseMaxPfS_ii
.addrsig_sym _Z18columnwiseMaxIndexPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define REPEAT 1
__global__ void arrayFunc(float* d_idata, float* d_jdata, float* d_odata, int size)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid < size) {
for(int i=0; i < REPEAT; i++)
d_odata[tid] = d_idata[tid] * __expf(d_jdata[tid]);
}
}
void initArrayData(float * array, float alpha, int size);
void arrayFuncCPU(const float* h_idata, const float* h_jdata, float* h_odata, int size);
#define NSIZE 1048576
int
main (void) {
float *h_a, *h_b, *h_c;
float *d_a, *d_b, *d_c;
int nsize = NSIZE;
int nThreads = 256;
int nBlocks;
cudaEvent_t start, end;
float eventEtime;
// calculate block number
nBlocks = (nsize-1) / nThreads + 1;
printf("Number of elements: %d\n", nsize);
printf("GPU execution with %d blocks each one of %d threads\n", nBlocks, nThreads);
// allocation and initialization of host buffers
h_a = (float*) malloc (nsize * sizeof(float));
h_b = (float*) malloc (nsize * sizeof(float));
h_c = (float*) malloc (nsize * sizeof(float));
initArrayData(h_a, 1.0f, nsize);
initArrayData(h_b, 10.0f, nsize);
//-- insert CUDE code ----------------
// allocation of device buffers
//------------------------------------
// creation of cuda events: start, end
cudaEventCreate(&start);
cudaEventCreate(&end);
printf ("\nGPU computation ... ");
cudaEventRecord(start,0);
//-- insert CUDA code ----------------
// host to device buffer copies
//------------------------------------
//-- insert CUDA code ----------------
// arrayFunc kernel launch
//------------------------------------
//-- insert CUDA code ----------------
// copy back of results from device
//------------------------------------
cudaEventRecord(end,0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&eventEtime, start, end);
printf ("ok\n");
printf("Elapsed time on GPU: %.2f ms\n", eventEtime);
// host computation
printf("\nCPU computation ... ");
float *cpuResult;
float eventTimeCPU;
cudaMallocHost((void**)&cpuResult, nsize * sizeof(float));
cudaEventRecord(start,0);
arrayFuncCPU(h_a, h_b, cpuResult, nsize);
cudaEventRecord(end,0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&eventTimeCPU, start, end);
printf ("ok\n");
printf("Elapsed time on CPU: %.2f ms\n", eventTimeCPU);
printf("\nSpeed UP CPU/GPU %.1fx\n", eventTimeCPU/eventEtime);
printf("\nCheck results:\n");
printf ("h_c[0] = %f\n", h_c[0]);
printf ("cpuResult[0] = %f\n", cpuResult[0]);
// free resources on device
cudaEventDestroy(start);
cudaEventDestroy(end);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
// free resources on host
free(h_a);
free(h_b);
free(h_c);
return 0;
}
void
initArrayData(float * array, float alpha, int size)
{
int i;
for (i=0; i< size; i++)
array[i] = alpha * (float) rand() / (float) RAND_MAX;
}
void arrayFuncCPU(const float* h_idata, const float* h_jdata, float* h_odata, int size)
{
int i, j;
for (i=0; i<size; i++)
for (j=0; j<REPEAT; j++)
h_odata[i] = h_idata[i] * expf(h_jdata[i]);
} | code for sm_80
Function : _Z9arrayFuncPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fcc00078e0207 */
/*0090*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fcc00078e0207 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ee2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FMUL R0, R4, 1.4426950216293334961 ; /* 0x3fb8aa3b04007820 */
/* 0x004fca0000400000 */
/*00e0*/ FSETP.GEU.AND P0, PT, R0, -126, PT ; /* 0xc2fc00000000780b */
/* 0x000fda0003f0e000 */
/*00f0*/ @!P0 FMUL R0, R0, 0.5 ; /* 0x3f00000000008820 */
/* 0x000fc80000400000 */
/*0100*/ MUFU.EX2 R8, R0 ; /* 0x0000000000087308 */
/* 0x000e240000000800 */
/*0110*/ @!P0 FMUL R8, R8, R8 ; /* 0x0000000808088220 */
/* 0x001fc80000400000 */
/*0120*/ FMUL R9, R8, R3 ; /* 0x0000000308097220 */
/* 0x008fca0000400000 */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define REPEAT 1
__global__ void arrayFunc(float* d_idata, float* d_jdata, float* d_odata, int size)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid < size) {
for(int i=0; i < REPEAT; i++)
d_odata[tid] = d_idata[tid] * __expf(d_jdata[tid]);
}
}
void initArrayData(float * array, float alpha, int size);
void arrayFuncCPU(const float* h_idata, const float* h_jdata, float* h_odata, int size);
#define NSIZE 1048576
int
main (void) {
float *h_a, *h_b, *h_c;
float *d_a, *d_b, *d_c;
int nsize = NSIZE;
int nThreads = 256;
int nBlocks;
cudaEvent_t start, end;
float eventEtime;
// calculate block number
nBlocks = (nsize-1) / nThreads + 1;
printf("Number of elements: %d\n", nsize);
printf("GPU execution with %d blocks each one of %d threads\n", nBlocks, nThreads);
// allocation and initialization of host buffers
h_a = (float*) malloc (nsize * sizeof(float));
h_b = (float*) malloc (nsize * sizeof(float));
h_c = (float*) malloc (nsize * sizeof(float));
initArrayData(h_a, 1.0f, nsize);
initArrayData(h_b, 10.0f, nsize);
//-- insert CUDE code ----------------
// allocation of device buffers
//------------------------------------
// creation of cuda events: start, end
cudaEventCreate(&start);
cudaEventCreate(&end);
printf ("\nGPU computation ... ");
cudaEventRecord(start,0);
//-- insert CUDA code ----------------
// host to device buffer copies
//------------------------------------
//-- insert CUDA code ----------------
// arrayFunc kernel launch
//------------------------------------
//-- insert CUDA code ----------------
// copy back of results from device
//------------------------------------
cudaEventRecord(end,0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&eventEtime, start, end);
printf ("ok\n");
printf("Elapsed time on GPU: %.2f ms\n", eventEtime);
// host computation
printf("\nCPU computation ... ");
float *cpuResult;
float eventTimeCPU;
cudaMallocHost((void**)&cpuResult, nsize * sizeof(float));
cudaEventRecord(start,0);
arrayFuncCPU(h_a, h_b, cpuResult, nsize);
cudaEventRecord(end,0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&eventTimeCPU, start, end);
printf ("ok\n");
printf("Elapsed time on CPU: %.2f ms\n", eventTimeCPU);
printf("\nSpeed UP CPU/GPU %.1fx\n", eventTimeCPU/eventEtime);
printf("\nCheck results:\n");
printf ("h_c[0] = %f\n", h_c[0]);
printf ("cpuResult[0] = %f\n", cpuResult[0]);
// free resources on device
cudaEventDestroy(start);
cudaEventDestroy(end);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
// free resources on host
free(h_a);
free(h_b);
free(h_c);
return 0;
}
void
initArrayData(float * array, float alpha, int size)
{
int i;
for (i=0; i< size; i++)
array[i] = alpha * (float) rand() / (float) RAND_MAX;
}
void arrayFuncCPU(const float* h_idata, const float* h_jdata, float* h_odata, int size)
{
int i, j;
for (i=0; i<size; i++)
for (j=0; j<REPEAT; j++)
h_odata[i] = h_idata[i] * expf(h_jdata[i]);
} | .file "tmpxft_000f13d6_00000000-6_Exercise_1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13initArrayDataPffi
.type _Z13initArrayDataPffi, @function
_Z13initArrayDataPffi:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movss %xmm0, 12(%rsp)
testl %esi, %esi
jle .L3
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss 12(%rsp), %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
.L3:
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z13initArrayDataPffi, .-_Z13initArrayDataPffi
.globl _Z12arrayFuncCPUPKfS0_Pfi
.type _Z12arrayFuncCPUPKfS0_Pfi, @function
_Z12arrayFuncCPUPKfS0_Pfi:
.LFB2059:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L13
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r13
movq %rsi, %r14
movq %rdx, %r15
movslq %ecx, %rcx
leaq 0(,%rcx,4), %r12
movl $0, %ebx
.L10:
movl 0(%r13,%rbx), %ebp
movss (%r14,%rbx), %xmm0
call expf@PLT
movd %ebp, %xmm1
mulss %xmm0, %xmm1
movss %xmm1, (%r15,%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L10
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2059:
.size _Z12arrayFuncCPUPKfS0_Pfi, .-_Z12arrayFuncCPUPKfS0_Pfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Number of elements: %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "GPU execution with %d blocks each one of %d threads\n"
.section .rodata.str1.1
.LC5:
.string "\nGPU computation ... "
.LC6:
.string "ok\n"
.LC7:
.string "Elapsed time on GPU: %.2f ms\n"
.LC8:
.string "\nCPU computation ... "
.LC9:
.string "Elapsed time on CPU: %.2f ms\n"
.LC10:
.string "\nSpeed UP CPU/GPU %.1fx\n"
.LC11:
.string "\nCheck results:\n"
.LC12:
.string "h_c[0] = %f\n"
.LC13:
.string "cpuResult[0] = %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $1048576, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $256, %ecx
movl $4096, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
movl $1048576, %esi
movss .LC3(%rip), %xmm0
movq %rbp, %rdi
call _Z13initArrayDataPffi
movl $1048576, %esi
movss .LC4(%rip), %xmm0
movq %rbx, %rdi
call _Z13initArrayDataPffi
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 8(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC6(%rip), %r13
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rdi
movl $4194304, %esi
call cudaMallocHost@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $1048576, %ecx
movq 32(%rsp), %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z12arrayFuncCPUPKfS0_Pfi
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 12(%rsp), %xmm0
divss 8(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax), %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movl $0, %edi
call cudaFree@PLT
movl $0, %edi
call cudaFree@PLT
movl $0, %edi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L19
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z33__device_stub__Z9arrayFuncPfS_S_iPfS_S_i
.type _Z33__device_stub__Z9arrayFuncPfS_S_iPfS_S_i, @function
_Z33__device_stub__Z9arrayFuncPfS_S_iPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9arrayFuncPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z33__device_stub__Z9arrayFuncPfS_S_iPfS_S_i, .-_Z33__device_stub__Z9arrayFuncPfS_S_iPfS_S_i
.globl _Z9arrayFuncPfS_S_i
.type _Z9arrayFuncPfS_S_i, @function
_Z9arrayFuncPfS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9arrayFuncPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9arrayFuncPfS_S_i, .-_Z9arrayFuncPfS_S_i
.section .rodata.str1.1
.LC14:
.string "_Z9arrayFuncPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z9arrayFuncPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.align 4
.LC3:
.long 1065353216
.align 4
.LC4:
.long 1092616192
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define REPEAT 1
__global__ void arrayFunc(float* d_idata, float* d_jdata, float* d_odata, int size)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid < size) {
for(int i=0; i < REPEAT; i++)
d_odata[tid] = d_idata[tid] * __expf(d_jdata[tid]);
}
}
void initArrayData(float * array, float alpha, int size);
void arrayFuncCPU(const float* h_idata, const float* h_jdata, float* h_odata, int size);
#define NSIZE 1048576
int
main (void) {
float *h_a, *h_b, *h_c;
float *d_a, *d_b, *d_c;
int nsize = NSIZE;
int nThreads = 256;
int nBlocks;
cudaEvent_t start, end;
float eventEtime;
// calculate block number
nBlocks = (nsize-1) / nThreads + 1;
printf("Number of elements: %d\n", nsize);
printf("GPU execution with %d blocks each one of %d threads\n", nBlocks, nThreads);
// allocation and initialization of host buffers
h_a = (float*) malloc (nsize * sizeof(float));
h_b = (float*) malloc (nsize * sizeof(float));
h_c = (float*) malloc (nsize * sizeof(float));
initArrayData(h_a, 1.0f, nsize);
initArrayData(h_b, 10.0f, nsize);
//-- insert CUDE code ----------------
// allocation of device buffers
//------------------------------------
// creation of cuda events: start, end
cudaEventCreate(&start);
cudaEventCreate(&end);
printf ("\nGPU computation ... ");
cudaEventRecord(start,0);
//-- insert CUDA code ----------------
// host to device buffer copies
//------------------------------------
//-- insert CUDA code ----------------
// arrayFunc kernel launch
//------------------------------------
//-- insert CUDA code ----------------
// copy back of results from device
//------------------------------------
cudaEventRecord(end,0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&eventEtime, start, end);
printf ("ok\n");
printf("Elapsed time on GPU: %.2f ms\n", eventEtime);
// host computation
printf("\nCPU computation ... ");
float *cpuResult;
float eventTimeCPU;
cudaMallocHost((void**)&cpuResult, nsize * sizeof(float));
cudaEventRecord(start,0);
arrayFuncCPU(h_a, h_b, cpuResult, nsize);
cudaEventRecord(end,0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&eventTimeCPU, start, end);
printf ("ok\n");
printf("Elapsed time on CPU: %.2f ms\n", eventTimeCPU);
printf("\nSpeed UP CPU/GPU %.1fx\n", eventTimeCPU/eventEtime);
printf("\nCheck results:\n");
printf ("h_c[0] = %f\n", h_c[0]);
printf ("cpuResult[0] = %f\n", cpuResult[0]);
// free resources on device
cudaEventDestroy(start);
cudaEventDestroy(end);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
// free resources on host
free(h_a);
free(h_b);
free(h_c);
return 0;
}
void
initArrayData(float * array, float alpha, int size)
{
int i;
for (i=0; i< size; i++)
array[i] = alpha * (float) rand() / (float) RAND_MAX;
}
void arrayFuncCPU(const float* h_idata, const float* h_jdata, float* h_odata, int size)
{
int i, j;
for (i=0; i<size; i++)
for (j=0; j<REPEAT; j++)
h_odata[i] = h_idata[i] * expf(h_jdata[i]);
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define REPEAT 1
__global__ void arrayFunc(float* d_idata, float* d_jdata, float* d_odata, int size)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid < size) {
for(int i=0; i < REPEAT; i++)
d_odata[tid] = d_idata[tid] * __expf(d_jdata[tid]);
}
}
void initArrayData(float * array, float alpha, int size);
void arrayFuncCPU(const float* h_idata, const float* h_jdata, float* h_odata, int size);
#define NSIZE 1048576
int
main (void) {
float *h_a, *h_b, *h_c;
float *d_a, *d_b, *d_c;
int nsize = NSIZE;
int nThreads = 256;
int nBlocks;
hipEvent_t start, end;
float eventEtime;
// calculate block number
nBlocks = (nsize-1) / nThreads + 1;
printf("Number of elements: %d\n", nsize);
printf("GPU execution with %d blocks each one of %d threads\n", nBlocks, nThreads);
// allocation and initialization of host buffers
h_a = (float*) malloc (nsize * sizeof(float));
h_b = (float*) malloc (nsize * sizeof(float));
h_c = (float*) malloc (nsize * sizeof(float));
initArrayData(h_a, 1.0f, nsize);
initArrayData(h_b, 10.0f, nsize);
//-- insert CUDE code ----------------
// allocation of device buffers
//------------------------------------
// creation of cuda events: start, end
hipEventCreate(&start);
hipEventCreate(&end);
printf ("\nGPU computation ... ");
hipEventRecord(start,0);
//-- insert CUDA code ----------------
// host to device buffer copies
//------------------------------------
//-- insert CUDA code ----------------
// arrayFunc kernel launch
//------------------------------------
//-- insert CUDA code ----------------
// copy back of results from device
//------------------------------------
hipEventRecord(end,0);
hipEventSynchronize(end);
hipEventElapsedTime(&eventEtime, start, end);
printf ("ok\n");
printf("Elapsed time on GPU: %.2f ms\n", eventEtime);
// host computation
printf("\nCPU computation ... ");
float *cpuResult;
float eventTimeCPU;
hipHostMalloc((void**)&cpuResult, nsize * sizeof(float), hipHostMallocDefault);
hipEventRecord(start,0);
arrayFuncCPU(h_a, h_b, cpuResult, nsize);
hipEventRecord(end,0);
hipEventSynchronize(end);
hipEventElapsedTime(&eventTimeCPU, start, end);
printf ("ok\n");
printf("Elapsed time on CPU: %.2f ms\n", eventTimeCPU);
printf("\nSpeed UP CPU/GPU %.1fx\n", eventTimeCPU/eventEtime);
printf("\nCheck results:\n");
printf ("h_c[0] = %f\n", h_c[0]);
printf ("cpuResult[0] = %f\n", cpuResult[0]);
// free resources on device
hipEventDestroy(start);
hipEventDestroy(end);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
// free resources on host
free(h_a);
free(h_b);
free(h_c);
return 0;
}
void
initArrayData(float * array, float alpha, int size)
{
int i;
for (i=0; i< size; i++)
array[i] = alpha * (float) rand() / (float) RAND_MAX;
}
void arrayFuncCPU(const float* h_idata, const float* h_jdata, float* h_odata, int size)
{
int i, j;
for (i=0; i<size; i++)
for (j=0; j<REPEAT; j++)
h_odata[i] = h_idata[i] * expf(h_jdata[i]);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define REPEAT 1
__global__ void arrayFunc(float* d_idata, float* d_jdata, float* d_odata, int size)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid < size) {
for(int i=0; i < REPEAT; i++)
d_odata[tid] = d_idata[tid] * __expf(d_jdata[tid]);
}
}
void initArrayData(float * array, float alpha, int size);
void arrayFuncCPU(const float* h_idata, const float* h_jdata, float* h_odata, int size);
#define NSIZE 1048576
int
main (void) {
float *h_a, *h_b, *h_c;
float *d_a, *d_b, *d_c;
int nsize = NSIZE;
int nThreads = 256;
int nBlocks;
hipEvent_t start, end;
float eventEtime;
// calculate block number
nBlocks = (nsize-1) / nThreads + 1;
printf("Number of elements: %d\n", nsize);
printf("GPU execution with %d blocks each one of %d threads\n", nBlocks, nThreads);
// allocation and initialization of host buffers
h_a = (float*) malloc (nsize * sizeof(float));
h_b = (float*) malloc (nsize * sizeof(float));
h_c = (float*) malloc (nsize * sizeof(float));
initArrayData(h_a, 1.0f, nsize);
initArrayData(h_b, 10.0f, nsize);
//-- insert CUDE code ----------------
// allocation of device buffers
//------------------------------------
// creation of cuda events: start, end
hipEventCreate(&start);
hipEventCreate(&end);
printf ("\nGPU computation ... ");
hipEventRecord(start,0);
//-- insert CUDA code ----------------
// host to device buffer copies
//------------------------------------
//-- insert CUDA code ----------------
// arrayFunc kernel launch
//------------------------------------
//-- insert CUDA code ----------------
// copy back of results from device
//------------------------------------
hipEventRecord(end,0);
hipEventSynchronize(end);
hipEventElapsedTime(&eventEtime, start, end);
printf ("ok\n");
printf("Elapsed time on GPU: %.2f ms\n", eventEtime);
// host computation
printf("\nCPU computation ... ");
float *cpuResult;
float eventTimeCPU;
hipHostMalloc((void**)&cpuResult, nsize * sizeof(float), hipHostMallocDefault);
hipEventRecord(start,0);
arrayFuncCPU(h_a, h_b, cpuResult, nsize);
hipEventRecord(end,0);
hipEventSynchronize(end);
hipEventElapsedTime(&eventTimeCPU, start, end);
printf ("ok\n");
printf("Elapsed time on CPU: %.2f ms\n", eventTimeCPU);
printf("\nSpeed UP CPU/GPU %.1fx\n", eventTimeCPU/eventEtime);
printf("\nCheck results:\n");
printf ("h_c[0] = %f\n", h_c[0]);
printf ("cpuResult[0] = %f\n", cpuResult[0]);
// free resources on device
hipEventDestroy(start);
hipEventDestroy(end);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
// free resources on host
free(h_a);
free(h_b);
free(h_c);
return 0;
}
void
initArrayData(float * array, float alpha, int size)
{
int i;
for (i=0; i< size; i++)
array[i] = alpha * (float) rand() / (float) RAND_MAX;
}
void arrayFuncCPU(const float* h_idata, const float* h_jdata, float* h_odata, int size)
{
int i, j;
for (i=0; i<size; i++)
for (j=0; j<REPEAT; j++)
h_odata[i] = h_idata[i] * expf(h_jdata[i]);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9arrayFuncPfS_S_i
.globl _Z9arrayFuncPfS_S_i
.p2align 8
.type _Z9arrayFuncPfS_S_i,@function
_Z9arrayFuncPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
global_load_b32 v4, v[2:3], off
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v3, 0x3fb8aa3b, v4
s_delay_alu instid0(VALU_DEP_1)
v_exp_f32_e32 v3, v3
s_waitcnt vmcnt(0)
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9arrayFuncPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9arrayFuncPfS_S_i, .Lfunc_end0-_Z9arrayFuncPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9arrayFuncPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9arrayFuncPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define REPEAT 1
__global__ void arrayFunc(float* d_idata, float* d_jdata, float* d_odata, int size)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid < size) {
for(int i=0; i < REPEAT; i++)
d_odata[tid] = d_idata[tid] * __expf(d_jdata[tid]);
}
}
void initArrayData(float * array, float alpha, int size);
void arrayFuncCPU(const float* h_idata, const float* h_jdata, float* h_odata, int size);
#define NSIZE 1048576
int
main (void) {
float *h_a, *h_b, *h_c;
float *d_a, *d_b, *d_c;
int nsize = NSIZE;
int nThreads = 256;
int nBlocks;
hipEvent_t start, end;
float eventEtime;
// calculate block number
nBlocks = (nsize-1) / nThreads + 1;
printf("Number of elements: %d\n", nsize);
printf("GPU execution with %d blocks each one of %d threads\n", nBlocks, nThreads);
// allocation and initialization of host buffers
h_a = (float*) malloc (nsize * sizeof(float));
h_b = (float*) malloc (nsize * sizeof(float));
h_c = (float*) malloc (nsize * sizeof(float));
initArrayData(h_a, 1.0f, nsize);
initArrayData(h_b, 10.0f, nsize);
//-- insert CUDE code ----------------
// allocation of device buffers
//------------------------------------
// creation of cuda events: start, end
hipEventCreate(&start);
hipEventCreate(&end);
printf ("\nGPU computation ... ");
hipEventRecord(start,0);
//-- insert CUDA code ----------------
// host to device buffer copies
//------------------------------------
//-- insert CUDA code ----------------
// arrayFunc kernel launch
//------------------------------------
//-- insert CUDA code ----------------
// copy back of results from device
//------------------------------------
hipEventRecord(end,0);
hipEventSynchronize(end);
hipEventElapsedTime(&eventEtime, start, end);
printf ("ok\n");
printf("Elapsed time on GPU: %.2f ms\n", eventEtime);
// host computation
printf("\nCPU computation ... ");
float *cpuResult;
float eventTimeCPU;
hipHostMalloc((void**)&cpuResult, nsize * sizeof(float), hipHostMallocDefault);
hipEventRecord(start,0);
arrayFuncCPU(h_a, h_b, cpuResult, nsize);
hipEventRecord(end,0);
hipEventSynchronize(end);
hipEventElapsedTime(&eventTimeCPU, start, end);
printf ("ok\n");
printf("Elapsed time on CPU: %.2f ms\n", eventTimeCPU);
printf("\nSpeed UP CPU/GPU %.1fx\n", eventTimeCPU/eventEtime);
printf("\nCheck results:\n");
printf ("h_c[0] = %f\n", h_c[0]);
printf ("cpuResult[0] = %f\n", cpuResult[0]);
// free resources on device
hipEventDestroy(start);
hipEventDestroy(end);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
// free resources on host
free(h_a);
free(h_b);
free(h_c);
return 0;
}
void
initArrayData(float * array, float alpha, int size)
{
int i;
for (i=0; i< size; i++)
array[i] = alpha * (float) rand() / (float) RAND_MAX;
}
void arrayFuncCPU(const float* h_idata, const float* h_jdata, float* h_odata, int size)
{
int i, j;
for (i=0; i<size; i++)
for (j=0; j<REPEAT; j++)
h_odata[i] = h_idata[i] * expf(h_jdata[i]);
} | .text
.file "Exercise_1.hip"
.globl _Z24__device_stub__arrayFuncPfS_S_i # -- Begin function _Z24__device_stub__arrayFuncPfS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__arrayFuncPfS_S_i,@function
_Z24__device_stub__arrayFuncPfS_S_i: # @_Z24__device_stub__arrayFuncPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9arrayFuncPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__arrayFuncPfS_S_i, .Lfunc_end0-_Z24__device_stub__arrayFuncPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI1_1:
.long 0x41200000 # float 10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $48, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %r12d, %r12d
movl $.L.str, %edi
movl $1048576, %esi # imm = 0x100000
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $4096, %esi # imm = 0x1000
movl $256, %edx # imm = 0x100
xorl %eax, %eax
callq printf
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r15
.p2align 4, 0x90
.LBB1_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, (%rbx,%r12,4)
incq %r12
cmpq $1048576, %r12 # imm = 0x100000
jne .LBB1_1
# %bb.2: # %.lr.ph.i24.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_3: # %.lr.ph.i24
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_1(%rip), %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq $1048576, %r12 # imm = 0x100000
jne .LBB1_3
# %bb.4: # %_Z13initArrayDataPffi.exit28
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
xorl %r12d, %r12d
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movl $.Lstr.1, %edi
callq puts@PLT
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
leaq 40(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
xorl %edx, %edx
callq hipHostMalloc
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %r13
.p2align 4, 0x90
.LBB1_5: # %.critedge.i
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, 36(%rsp) # 4-byte Spill
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
callq expf
mulss 36(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, (%r13,%r12,4)
incq %r12
cmpq $1048576, %r12 # imm = 0x100000
jne .LBB1_5
# %bb.6: # %_Z12arrayFuncCPUPKfS0_Pfi.exit
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 28(%rsp), %rdi
callq hipEventElapsedTime
movl $.Lstr.1, %edi
callq puts@PLT
movss 28(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movss 28(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss 32(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movl $.Lstr.2, %edi
callq puts@PLT
movss (%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.9, %edi
movb $1, %al
callq printf
movq 40(%rsp), %rax
movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
callq hipFree
callq hipFree
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $48, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z13initArrayDataPffi
.LCPI2_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z13initArrayDataPffi
.p2align 4, 0x90
.type _Z13initArrayDataPffi,@function
_Z13initArrayDataPffi: # @_Z13initArrayDataPffi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
movss %xmm0, 12(%rsp) # 4-byte Spill
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
mulss %xmm0, %xmm1
mulss .LCPI2_0(%rip), %xmm1
movss %xmm1, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB2_2
# %bb.3:
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
retq
.Lfunc_end2:
.size _Z13initArrayDataPffi, .Lfunc_end2-_Z13initArrayDataPffi
.cfi_endproc
# -- End function
.globl _Z12arrayFuncCPUPKfS0_Pfi # -- Begin function _Z12arrayFuncCPUPKfS0_Pfi
.p2align 4, 0x90
.type _Z12arrayFuncCPUPKfS0_Pfi,@function
_Z12arrayFuncCPUPKfS0_Pfi: # @_Z12arrayFuncCPUPKfS0_Pfi
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB3_4
# %bb.1: # %.critedge.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movl %ecx, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_2: # %.critedge
# =>This Inner Loop Header: Depth=1
movss (%r15,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, 12(%rsp) # 4-byte Spill
movss (%r14,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
callq expf
mulss 12(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, (%rbx,%r13,4)
incq %r13
cmpq %r13, %r12
jne .LBB3_2
# %bb.3:
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.LBB3_4: # %._crit_edge
retq
.Lfunc_end3:
.size _Z12arrayFuncCPUPKfS0_Pfi, .Lfunc_end3-_Z12arrayFuncCPUPKfS0_Pfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9arrayFuncPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9arrayFuncPfS_S_i,@object # @_Z9arrayFuncPfS_S_i
.section .rodata,"a",@progbits
.globl _Z9arrayFuncPfS_S_i
.p2align 3, 0x0
_Z9arrayFuncPfS_S_i:
.quad _Z24__device_stub__arrayFuncPfS_S_i
.size _Z9arrayFuncPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Number of elements: %d\n"
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU execution with %d blocks each one of %d threads\n"
.size .L.str.1, 53
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nGPU computation ... "
.size .L.str.2, 22
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Elapsed time on GPU: %.2f ms\n"
.size .L.str.4, 30
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\nCPU computation ... "
.size .L.str.5, 22
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Elapsed time on CPU: %.2f ms\n"
.size .L.str.6, 30
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\nSpeed UP CPU/GPU %.1fx\n"
.size .L.str.7, 25
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "h_c[0] = %f\n"
.size .L.str.9, 19
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "cpuResult[0] = %f\n"
.size .L.str.10, 19
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9arrayFuncPfS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "ok"
.size .Lstr.1, 3
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\nCheck results:"
.size .Lstr.2, 16
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__arrayFuncPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9arrayFuncPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9arrayFuncPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fcc00078e0207 */
/*0090*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fcc00078e0207 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ee2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FMUL R0, R4, 1.4426950216293334961 ; /* 0x3fb8aa3b04007820 */
/* 0x004fca0000400000 */
/*00e0*/ FSETP.GEU.AND P0, PT, R0, -126, PT ; /* 0xc2fc00000000780b */
/* 0x000fda0003f0e000 */
/*00f0*/ @!P0 FMUL R0, R0, 0.5 ; /* 0x3f00000000008820 */
/* 0x000fc80000400000 */
/*0100*/ MUFU.EX2 R8, R0 ; /* 0x0000000000087308 */
/* 0x000e240000000800 */
/*0110*/ @!P0 FMUL R8, R8, R8 ; /* 0x0000000808088220 */
/* 0x001fc80000400000 */
/*0120*/ FMUL R9, R8, R3 ; /* 0x0000000308097220 */
/* 0x008fca0000400000 */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9arrayFuncPfS_S_i
.globl _Z9arrayFuncPfS_S_i
.p2align 8
.type _Z9arrayFuncPfS_S_i,@function
_Z9arrayFuncPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
global_load_b32 v4, v[2:3], off
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v3, 0x3fb8aa3b, v4
s_delay_alu instid0(VALU_DEP_1)
v_exp_f32_e32 v3, v3
s_waitcnt vmcnt(0)
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9arrayFuncPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9arrayFuncPfS_S_i, .Lfunc_end0-_Z9arrayFuncPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9arrayFuncPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9arrayFuncPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f13d6_00000000-6_Exercise_1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13initArrayDataPffi
.type _Z13initArrayDataPffi, @function
_Z13initArrayDataPffi:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movss %xmm0, 12(%rsp)
testl %esi, %esi
jle .L3
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss 12(%rsp), %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
.L3:
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z13initArrayDataPffi, .-_Z13initArrayDataPffi
.globl _Z12arrayFuncCPUPKfS0_Pfi
.type _Z12arrayFuncCPUPKfS0_Pfi, @function
_Z12arrayFuncCPUPKfS0_Pfi:
.LFB2059:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L13
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r13
movq %rsi, %r14
movq %rdx, %r15
movslq %ecx, %rcx
leaq 0(,%rcx,4), %r12
movl $0, %ebx
.L10:
movl 0(%r13,%rbx), %ebp
movss (%r14,%rbx), %xmm0
call expf@PLT
movd %ebp, %xmm1
mulss %xmm0, %xmm1
movss %xmm1, (%r15,%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L10
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2059:
.size _Z12arrayFuncCPUPKfS0_Pfi, .-_Z12arrayFuncCPUPKfS0_Pfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Number of elements: %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "GPU execution with %d blocks each one of %d threads\n"
.section .rodata.str1.1
.LC5:
.string "\nGPU computation ... "
.LC6:
.string "ok\n"
.LC7:
.string "Elapsed time on GPU: %.2f ms\n"
.LC8:
.string "\nCPU computation ... "
.LC9:
.string "Elapsed time on CPU: %.2f ms\n"
.LC10:
.string "\nSpeed UP CPU/GPU %.1fx\n"
.LC11:
.string "\nCheck results:\n"
.LC12:
.string "h_c[0] = %f\n"
.LC13:
.string "cpuResult[0] = %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $1048576, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $256, %ecx
movl $4096, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
movl $1048576, %esi
movss .LC3(%rip), %xmm0
movq %rbp, %rdi
call _Z13initArrayDataPffi
movl $1048576, %esi
movss .LC4(%rip), %xmm0
movq %rbx, %rdi
call _Z13initArrayDataPffi
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 8(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC6(%rip), %r13
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rdi
movl $4194304, %esi
call cudaMallocHost@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $1048576, %ecx
movq 32(%rsp), %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z12arrayFuncCPUPKfS0_Pfi
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 12(%rsp), %xmm0
divss 8(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 32(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax), %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movl $0, %edi
call cudaFree@PLT
movl $0, %edi
call cudaFree@PLT
movl $0, %edi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L19
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z33__device_stub__Z9arrayFuncPfS_S_iPfS_S_i
.type _Z33__device_stub__Z9arrayFuncPfS_S_iPfS_S_i, @function
_Z33__device_stub__Z9arrayFuncPfS_S_iPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9arrayFuncPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z33__device_stub__Z9arrayFuncPfS_S_iPfS_S_i, .-_Z33__device_stub__Z9arrayFuncPfS_S_iPfS_S_i
.globl _Z9arrayFuncPfS_S_i
.type _Z9arrayFuncPfS_S_i, @function
_Z9arrayFuncPfS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9arrayFuncPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9arrayFuncPfS_S_i, .-_Z9arrayFuncPfS_S_i
.section .rodata.str1.1
.LC14:
.string "_Z9arrayFuncPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z9arrayFuncPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.align 4
.LC3:
.long 1065353216
.align 4
.LC4:
.long 1092616192
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Exercise_1.hip"
.globl _Z24__device_stub__arrayFuncPfS_S_i # -- Begin function _Z24__device_stub__arrayFuncPfS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__arrayFuncPfS_S_i,@function
_Z24__device_stub__arrayFuncPfS_S_i: # @_Z24__device_stub__arrayFuncPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9arrayFuncPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__arrayFuncPfS_S_i, .Lfunc_end0-_Z24__device_stub__arrayFuncPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI1_1:
.long 0x41200000 # float 10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $48, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %r12d, %r12d
movl $.L.str, %edi
movl $1048576, %esi # imm = 0x100000
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $4096, %esi # imm = 0x1000
movl $256, %edx # imm = 0x100
xorl %eax, %eax
callq printf
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r15
.p2align 4, 0x90
.LBB1_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, (%rbx,%r12,4)
incq %r12
cmpq $1048576, %r12 # imm = 0x100000
jne .LBB1_1
# %bb.2: # %.lr.ph.i24.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_3: # %.lr.ph.i24
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_1(%rip), %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, (%r14,%r12,4)
incq %r12
cmpq $1048576, %r12 # imm = 0x100000
jne .LBB1_3
# %bb.4: # %_Z13initArrayDataPffi.exit28
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
xorl %r12d, %r12d
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movl $.Lstr.1, %edi
callq puts@PLT
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
leaq 40(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
xorl %edx, %edx
callq hipHostMalloc
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %r13
.p2align 4, 0x90
.LBB1_5: # %.critedge.i
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, 36(%rsp) # 4-byte Spill
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
callq expf
mulss 36(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, (%r13,%r12,4)
incq %r12
cmpq $1048576, %r12 # imm = 0x100000
jne .LBB1_5
# %bb.6: # %_Z12arrayFuncCPUPKfS0_Pfi.exit
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 28(%rsp), %rdi
callq hipEventElapsedTime
movl $.Lstr.1, %edi
callq puts@PLT
movss 28(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movss 28(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss 32(%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movl $.Lstr.2, %edi
callq puts@PLT
movss (%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.9, %edi
movb $1, %al
callq printf
movq 40(%rsp), %rax
movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
callq hipFree
callq hipFree
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $48, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z13initArrayDataPffi
.LCPI2_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z13initArrayDataPffi
.p2align 4, 0x90
.type _Z13initArrayDataPffi,@function
_Z13initArrayDataPffi: # @_Z13initArrayDataPffi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
movss %xmm0, 12(%rsp) # 4-byte Spill
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
mulss %xmm0, %xmm1
mulss .LCPI2_0(%rip), %xmm1
movss %xmm1, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB2_2
# %bb.3:
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
retq
.Lfunc_end2:
.size _Z13initArrayDataPffi, .Lfunc_end2-_Z13initArrayDataPffi
.cfi_endproc
# -- End function
.globl _Z12arrayFuncCPUPKfS0_Pfi # -- Begin function _Z12arrayFuncCPUPKfS0_Pfi
.p2align 4, 0x90
.type _Z12arrayFuncCPUPKfS0_Pfi,@function
_Z12arrayFuncCPUPKfS0_Pfi: # @_Z12arrayFuncCPUPKfS0_Pfi
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB3_4
# %bb.1: # %.critedge.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movl %ecx, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_2: # %.critedge
# =>This Inner Loop Header: Depth=1
movss (%r15,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, 12(%rsp) # 4-byte Spill
movss (%r14,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
callq expf
mulss 12(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, (%rbx,%r13,4)
incq %r13
cmpq %r13, %r12
jne .LBB3_2
# %bb.3:
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.LBB3_4: # %._crit_edge
retq
.Lfunc_end3:
.size _Z12arrayFuncCPUPKfS0_Pfi, .Lfunc_end3-_Z12arrayFuncCPUPKfS0_Pfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9arrayFuncPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9arrayFuncPfS_S_i,@object # @_Z9arrayFuncPfS_S_i
.section .rodata,"a",@progbits
.globl _Z9arrayFuncPfS_S_i
.p2align 3, 0x0
_Z9arrayFuncPfS_S_i:
.quad _Z24__device_stub__arrayFuncPfS_S_i
.size _Z9arrayFuncPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Number of elements: %d\n"
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU execution with %d blocks each one of %d threads\n"
.size .L.str.1, 53
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nGPU computation ... "
.size .L.str.2, 22
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Elapsed time on GPU: %.2f ms\n"
.size .L.str.4, 30
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\nCPU computation ... "
.size .L.str.5, 22
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Elapsed time on CPU: %.2f ms\n"
.size .L.str.6, 30
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\nSpeed UP CPU/GPU %.1fx\n"
.size .L.str.7, 25
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "h_c[0] = %f\n"
.size .L.str.9, 19
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "cpuResult[0] = %f\n"
.size .L.str.10, 19
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9arrayFuncPfS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "ok"
.size .Lstr.1, 3
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\nCheck results:"
.size .Lstr.2, 16
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__arrayFuncPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9arrayFuncPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cub/cub.cuh>
using namespace cub;
template<int BLOCK_SIZE, int CPG>
__global__ void cal_group_coo_format_nnz_kernel_cm(float *A, int nRows, int nCols, int *pNnzPerGroup)
{
int startIdx = blockIdx.x * CPG;
int nnz = 0;
int nColPerThread = (nCols + BLOCK_SIZE - 1) / BLOCK_SIZE;
int colOffset = threadIdx.x * nColPerThread;
for (int i = threadIdx.x; i < nCols; i+=BLOCK_SIZE) {
for (int j = 0; j < CPG; j++) {
int row = j + startIdx;
if (row >= nRows)
break;
float v = A[row * nCols + i];
if (v != 0.0) {
nnz++;
}
}
}
typedef BlockReduce<int, BLOCK_SIZE> BlockReduceT;
__shared__ typename BlockReduceT::TempStorage temp_storage;
int aggregate = BlockReduceT(temp_storage).Sum(nnz);
if (threadIdx.x == 0) {
pNnzPerGroup[blockIdx.x] = aggregate;
}
}
template<int BLOCK_SIZE, int CPG>
__global__ void convert_to_group_coo_format_kernel_cm(float *A, int nRows, int nCols,
float *pVals, int *pRows, int *pCols, int *pGroupIndex, int *pNnzPerGroup)
{
int startIdx = blockIdx.x * CPG;
int currGroupOffset = pGroupIndex[blockIdx.x];
int cooIndex = currGroupOffset;
float *currVals = pVals + cooIndex;
int *currCols = pCols + cooIndex;
int *currRows = pRows + cooIndex;
__shared__ float sA[BLOCK_SIZE * CPG];
typedef BlockScan<int, BLOCK_SIZE> BlockScanT;
__shared__ typename BlockScanT::TempStorage temp_storage;
__shared__ int sNNz;
sNNz = 0;
__syncthreads();
int end = (nCols + BLOCK_SIZE - 1)/ BLOCK_SIZE * BLOCK_SIZE;
for (int i = threadIdx.x; i < end; i+=BLOCK_SIZE) {
int nnz = 0;
int nnz_i = 0;
for (int j = 0; j < CPG; j++) {
int row = j + startIdx;
if (row < nRows && i < nCols) {
float v = A[row * nCols + i];
sA[j * BLOCK_SIZE + threadIdx.x] = v;
if (v != 0.0)
nnz++;
}
}
BlockScanT(temp_storage).InclusiveSum(nnz, nnz_i);
__syncthreads();
BlockScanT(temp_storage).ExclusiveSum(nnz, nnz);
float *vals = currVals + nnz;
int *cols = currCols + nnz;
int *rows = currRows + nnz;
for (int j = 0; j < CPG; j++) {
int row = j + startIdx;
if (row >= nRows || i >= nCols)
break;
float v = sA[j * BLOCK_SIZE + threadIdx.x];
if (v != 0.0) {
*(vals++) = v;
*(rows++) = row;
*(cols++) = i;
}
}
if (threadIdx.x == BLOCK_SIZE - 1) {
sNNz = nnz_i;
}
__syncthreads();
currVals += sNNz;
currCols += sNNz;
currRows += sNNz;
}
}
template<int BLOCK_SIZE, int CPG>
__global__ void sparse_dense_groupcoo_mat_mul_kernel(float *vals_A, int *cols_A, int *rows_A, int *groupIndex_A, int *nnzPerGroup_A, int wA, int hA, float *B, int wB, int hB, float *C)
{
int Cj = blockIdx.y * BLOCK_SIZE + threadIdx.x;
int Ci0 = blockIdx.x * CPG;
float c0 =0.0; float c1 =0.0; float c2 =0.0; float c3 =0.0;
int groupIdxOfCurrentBlock = groupIndex_A[blockIdx.x];
int nnz = nnzPerGroup_A[blockIdx.x];
float *currValsA = vals_A + groupIdxOfCurrentBlock;
int *currColsA = cols_A + groupIdxOfCurrentBlock;
int *currRowsA = rows_A + groupIdxOfCurrentBlock;
__shared__ float sValsA[BLOCK_SIZE];
__shared__ int sRowsA[BLOCK_SIZE];
__shared__ int sColsA[BLOCK_SIZE];
__shared__ int sNNz[1];
int nIter = (BLOCK_SIZE + nnz - 1) / BLOCK_SIZE;
int extra = nnz & (BLOCK_SIZE - 1);
for (int i = 0; i < nIter; i++) {
sColsA[threadIdx.x] = -1;
sValsA[threadIdx.x] = 0.0;
sNNz[0] = BLOCK_SIZE;
__syncthreads();
int valIdxStart = i * BLOCK_SIZE;
int valIdx = valIdxStart + threadIdx.x;
if (valIdx < nnz) {
sValsA[threadIdx.x] = currValsA[valIdx];
sRowsA[threadIdx.x] = currRowsA[valIdx];
sColsA[threadIdx.x] = currColsA[valIdx];
} else {
sNNz[0] = extra;
}
__syncthreads();
if (Cj < wB) {
int k = 1;
int rNNz = sNNz[0];
int precol = -1;
float b;
for (int j = 0; j < rNNz;) {
int col = sColsA[j];
if (col != precol) {
b = B[col * wB + Cj];
precol = col;
}
float a = sValsA[j];
int currRow = sRowsA[j];
int index = currRow & (CPG-1);
if (index == 0) c0 = fmaf(a,b,c0); else if (index == 1) c1=fmaf(a,b,c1); else if (index == 2) c2=fmaf(a,b,c2); else if (index == 3) c3=fmaf(a,b,c3);
j++;
}
}
__syncthreads();
}
if (Cj < wB) {
if (Ci0 < hA)
C[Cj + Ci0 * wB] = c0;
if (Ci0+1 < hA)
C[Cj + (Ci0 + 1)*wB] = c1;
if (Ci0+2 < hA)
C[Cj + (Ci0 + 2)*wB] = c2;
if (Ci0+3 < hA)
C[Cj + (Ci0 + 3)*wB] = c3;
}
}
__global__ void prefix_sum_kernel2(int *src, int *dst, int n)
{
if (threadIdx.x == 0 && blockIdx.x == 0) {
dst[0] = 0;
for (int i = 1; i < n; i++) {
dst[i] = dst[i-1] + src[i-1];
}
}
} | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z18prefix_sum_kernel2PiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ LOP3.LUT P0, RZ, R0, UR4, RZ, 0xfc, !PT ; /* 0x0000000400ff7c12 */
/* 0x001fda000f80fcff */
/*0040*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0050*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff007624 */
/* 0x000fe200078e00ff */
/*0060*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe20000000f00 */
/*0070*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe40000000a00 */
/*0090*/ ISETP.GE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe40003f06270 */
/*00a0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001f6000c10190a */
/*00b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R0.reuse, -0x2, RZ ; /* 0xfffffffe00027810 */
/* 0x041fe20007ffe0ff */
/*00d0*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe20000000000 */
/*00e0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc40007ffe0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0100*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fd600078ec0ff */
/*0110*/ @!P0 BRA 0x9c0 ; /* 0x000008a000008947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R6, -R0, c[0x0][0x170], RZ ; /* 0x00005c0000067a10 */
/* 0x000fe20007ffe1ff */
/*0130*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe20000000000 */
/*0140*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0150*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0160*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0170*/ ISETP.GT.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe20003f04270 */
/*0180*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe400078e00ff */
/*0190*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fd400078e00ff */
/*01a0*/ @!P0 BRA 0x840 ; /* 0x0000069000008947 */
/* 0x000fea0003800000 */
/*01b0*/ IADD3 R8, R6, -0x1, RZ ; /* 0xffffffff06087810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*01d0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fda0003f24270 */
/*01e0*/ @!P1 BRA 0x5c0 ; /* 0x000003d000009947 */
/* 0x000fea0003800000 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0200*/ LDG.E R8, [R2.64] ; /* 0x0000000a02087981 */
/* 0x000ea4000c1e1900 */
/*0210*/ IMAD.IADD R7, R8, 0x1, R7 ; /* 0x0000000108077824 */
/* 0x004fca00078e0207 */
/*0220*/ STG.E [R4.64+0x4], R7 ; /* 0x0000040704007986 */
/* 0x0001e8000c10190a */
/*0230*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040a02087981 */
/* 0x000ea4000c1e1900 */
/*0240*/ IMAD.IADD R9, R7, 0x1, R8 ; /* 0x0000000107097824 */
/* 0x004fca00078e0208 */
/*0250*/ STG.E [R4.64+0x8], R9 ; /* 0x0000080904007986 */
/* 0x0003e8000c10190a */
/*0260*/ LDG.E R8, [R2.64+0x8] ; /* 0x0000080a02087981 */
/* 0x000ea4000c1e1900 */
/*0270*/ IADD3 R11, R9, R8, RZ ; /* 0x00000008090b7210 */
/* 0x004fca0007ffe0ff */
/*0280*/ STG.E [R4.64+0xc], R11 ; /* 0x00000c0b04007986 */
/* 0x0005e8000c10190a */
/*0290*/ LDG.E R8, [R2.64+0xc] ; /* 0x00000c0a02087981 */
/* 0x000ee4000c1e1900 */
/*02a0*/ IMAD.IADD R13, R11, 0x1, R8 ; /* 0x000000010b0d7824 */
/* 0x008fca00078e0208 */
/*02b0*/ STG.E [R4.64+0x10], R13 ; /* 0x0000100d04007986 */
/* 0x0007e8000c10190a */
/*02c0*/ LDG.E R8, [R2.64+0x10] ; /* 0x0000100a02087981 */
/* 0x000e24000c1e1900 */
/*02d0*/ IMAD.IADD R7, R13, 0x1, R8 ; /* 0x000000010d077824 */
/* 0x001fca00078e0208 */
/*02e0*/ STG.E [R4.64+0x14], R7 ; /* 0x0000140704007986 */
/* 0x0001e8000c10190a */
/*02f0*/ LDG.E R8, [R2.64+0x14] ; /* 0x0000140a02087981 */
/* 0x000e64000c1e1900 */
/*0300*/ IMAD.IADD R9, R7, 0x1, R8 ; /* 0x0000000107097824 */
/* 0x002fca00078e0208 */
/*0310*/ STG.E [R4.64+0x18], R9 ; /* 0x0000180904007986 */
/* 0x0003e8000c10190a */
/*0320*/ LDG.E R8, [R2.64+0x18] ; /* 0x0000180a02087981 */
/* 0x000ea4000c1e1900 */
/*0330*/ IADD3 R11, R9, R8, RZ ; /* 0x00000008090b7210 */
/* 0x004fca0007ffe0ff */
/*0340*/ STG.E [R4.64+0x1c], R11 ; /* 0x00001c0b04007986 */
/* 0x0005e8000c10190a */
/*0350*/ LDG.E R8, [R2.64+0x1c] ; /* 0x00001c0a02087981 */
/* 0x000ee4000c1e1900 */
/*0360*/ IMAD.IADD R13, R11, 0x1, R8 ; /* 0x000000010b0d7824 */
/* 0x008fca00078e0208 */
/*0370*/ STG.E [R4.64+0x20], R13 ; /* 0x0000200d04007986 */
/* 0x0007e8000c10190a */
/*0380*/ LDG.E R8, [R2.64+0x20] ; /* 0x0000200a02087981 */
/* 0x000e24000c1e1900 */
/*0390*/ IMAD.IADD R7, R13, 0x1, R8 ; /* 0x000000010d077824 */
/* 0x001fca00078e0208 */
/*03a0*/ STG.E [R4.64+0x24], R7 ; /* 0x0000240704007986 */
/* 0x000fe8000c10190a */
/*03b0*/ LDG.E R8, [R2.64+0x24] ; /* 0x0000240a02087981 */
/* 0x000e64000c1e1900 */
/*03c0*/ IMAD.IADD R9, R7, 0x1, R8 ; /* 0x0000000107097824 */
/* 0x002fca00078e0208 */
/*03d0*/ STG.E [R4.64+0x28], R9 ; /* 0x0000280904007986 */
/* 0x0001e8000c10190a */
/*03e0*/ LDG.E R8, [R2.64+0x28] ; /* 0x0000280a02087981 */
/* 0x000ea4000c1e1900 */
/*03f0*/ IADD3 R11, R9, R8, RZ ; /* 0x00000008090b7210 */
/* 0x004fca0007ffe0ff */
/*0400*/ STG.E [R4.64+0x2c], R11 ; /* 0x00002c0b04007986 */
/* 0x0003e8000c10190a */
/*0410*/ LDG.E R8, [R2.64+0x2c] ; /* 0x00002c0a02087981 */
/* 0x000ee4000c1e1900 */
/*0420*/ IMAD.IADD R13, R11, 0x1, R8 ; /* 0x000000010b0d7824 */
/* 0x008fca00078e0208 */
/*0430*/ STG.E [R4.64+0x30], R13 ; /* 0x0000300d04007986 */
/* 0x0005e8000c10190a */
/*0440*/ LDG.E R8, [R2.64+0x30] ; /* 0x0000300a02087981 */
/* 0x000ee4000c1e1900 */
/*0450*/ IMAD.IADD R15, R13, 0x1, R8 ; /* 0x000000010d0f7824 */
/* 0x008fca00078e0208 */
/*0460*/ STG.E [R4.64+0x34], R15 ; /* 0x0000340f04007986 */
/* 0x000fe8000c10190a */
/*0470*/ LDG.E R8, [R2.64+0x34] ; /* 0x0000340a02087981 */
/* 0x000e24000c1e1900 */
/*0480*/ IMAD.IADD R9, R15, 0x1, R8 ; /* 0x000000010f097824 */
/* 0x001fca00078e0208 */
/*0490*/ STG.E [R4.64+0x38], R9 ; /* 0x0000380904007986 */
/* 0x0001e8000c10190a */
/*04a0*/ LDG.E R8, [R2.64+0x38] ; /* 0x0000380a02087981 */
/* 0x000e62000c1e1900 */
/*04b0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fe40007ffe0ff */
/*04c0*/ IADD3 R11, R9, R8, RZ ; /* 0x00000008090b7210 */
/* 0x002fca0007ffe0ff */
/*04d0*/ STG.E [R4.64+0x3c], R11 ; /* 0x00003c0b04007986 */
/* 0x000fe8000c10190a */
/*04e0*/ LDG.E R8, [R2.64+0x3c] ; /* 0x00003c0a02087981 */
/* 0x000ee2000c1e1900 */
/*04f0*/ ISETP.GT.AND P1, PT, R6, 0xd, PT ; /* 0x0000000d0600780c */
/* 0x000fe20003f24270 */
/*0500*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*0510*/ IADD3 R10, P2, R4, 0x40, RZ ; /* 0x00000040040a7810 */
/* 0x000fca0007f5e0ff */
/*0520*/ IMAD.X R13, RZ, RZ, R5, P2 ; /* 0x000000ffff0d7224 */
/* 0x004fe400010e0605 */
/*0530*/ IMAD.IADD R7, R11, 0x1, R8 ; /* 0x000000010b077824 */
/* 0x008fe200078e0208 */
/*0540*/ IADD3 R8, P3, R2, 0x40, RZ ; /* 0x0000004002087810 */
/* 0x000fc80007f7e0ff */
/*0550*/ STG.E [R4.64+0x40], R7 ; /* 0x0000400704007986 */
/* 0x0003e2000c10190a */
/*0560*/ IMAD.X R9, RZ, RZ, R3, P3 ; /* 0x000000ffff097224 */
/* 0x001fe200018e0603 */
/*0570*/ MOV R2, R8 ; /* 0x0000000800027202 */
/* 0x000fc60000000f00 */
/*0580*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0009 */
/*0590*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x002fe400078e000a */
/*05a0*/ IMAD.MOV.U32 R5, RZ, RZ, R13 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000d */
/*05b0*/ @P1 BRA 0x200 ; /* 0xfffffc4000001947 */
/* 0x000fea000383ffff */
/*05c0*/ IADD3 R8, R6, -0x1, RZ ; /* 0xffffffff06087810 */
/* 0x000fc80007ffe0ff */
/*05d0*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*05e0*/ @!P1 BRA 0x820 ; /* 0x0000023000009947 */
/* 0x000fea0003800000 */
/*05f0*/ LDG.E R8, [R2.64] ; /* 0x0000000a02087981 */
/* 0x000ea4000c1e1900 */
/*0600*/ IADD3 R7, R7, R8, RZ ; /* 0x0000000807077210 */
/* 0x004fca0007ffe0ff */
/*0610*/ STG.E [R4.64+0x4], R7 ; /* 0x0000040704007986 */
/* 0x000fe8000c10190a */
/*0620*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040a02087981 */
/* 0x000ea4000c1e1900 */
/*0630*/ IMAD.IADD R9, R7, 0x1, R8 ; /* 0x0000000107097824 */
/* 0x004fca00078e0208 */
/*0640*/ STG.E [R4.64+0x8], R9 ; /* 0x0000080904007986 */
/* 0x0001e8000c10190a */
/*0650*/ LDG.E R8, [R2.64+0x8] ; /* 0x0000080a02087981 */
/* 0x000ea4000c1e1900 */
/*0660*/ IMAD.IADD R11, R9, 0x1, R8 ; /* 0x00000001090b7824 */
/* 0x004fca00078e0208 */
/*0670*/ STG.E [R4.64+0xc], R11 ; /* 0x00000c0b04007986 */
/* 0x0003e8000c10190a */
/*0680*/ LDG.E R8, [R2.64+0xc] ; /* 0x00000c0a02087981 */
/* 0x000ea4000c1e1900 */
/*0690*/ IMAD.IADD R13, R11, 0x1, R8 ; /* 0x000000010b0d7824 */
/* 0x004fca00078e0208 */
/*06a0*/ STG.E [R4.64+0x10], R13 ; /* 0x0000100d04007986 */
/* 0x0005e8000c10190a */
/*06b0*/ LDG.E R8, [R2.64+0x10] ; /* 0x0000100a02087981 */
/* 0x000ee4000c1e1900 */
/*06c0*/ IADD3 R15, R13, R8, RZ ; /* 0x000000080d0f7210 */
/* 0x008fca0007ffe0ff */
/*06d0*/ STG.E [R4.64+0x14], R15 ; /* 0x0000140f04007986 */
/* 0x000fe8000c10190a */
/*06e0*/ LDG.E R8, [R2.64+0x14] ; /* 0x0000140a02087981 */
/* 0x000e24000c1e1900 */
/*06f0*/ IMAD.IADD R9, R15, 0x1, R8 ; /* 0x000000010f097824 */
/* 0x001fca00078e0208 */
/*0700*/ STG.E [R4.64+0x18], R9 ; /* 0x0000180904007986 */
/* 0x0001e8000c10190a */
/*0710*/ LDG.E R8, [R2.64+0x18] ; /* 0x0000180a02087981 */
/* 0x000e64000c1e1900 */
/*0720*/ IMAD.IADD R11, R9, 0x1, R8 ; /* 0x00000001090b7824 */
/* 0x002fca00078e0208 */
/*0730*/ STG.E [R4.64+0x1c], R11 ; /* 0x00001c0b04007986 */
/* 0x000fe8000c10190a */
/*0740*/ LDG.E R8, [R2.64+0x1c] ; /* 0x00001c0a02087981 */
/* 0x000ee2000c1e1900 */
/*0750*/ IADD3 R10, P1, R4, 0x20, RZ ; /* 0x00000020040a7810 */
/* 0x000fe20007f3e0ff */
/*0760*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0770*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0780*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0790*/ IMAD.X R13, RZ, RZ, R5, P1 ; /* 0x000000ffff0d7224 */
/* 0x004fe200008e0605 */
/*07a0*/ IADD3 R7, R11, R8, RZ ; /* 0x000000080b077210 */
/* 0x008fc40007ffe0ff */
/*07b0*/ IADD3 R8, P2, R2, 0x20, RZ ; /* 0x0000002002087810 */
/* 0x000fc60007f5e0ff */
/*07c0*/ STG.E [R4.64+0x20], R7 ; /* 0x0000200704007986 */
/* 0x0003e2000c10190a */
/*07d0*/ MOV R2, R8 ; /* 0x0000000800027202 */
/* 0x000fe20000000f00 */
/*07e0*/ IMAD.X R9, RZ, RZ, R3, P2 ; /* 0x000000ffff097224 */
/* 0x001fc800010e0603 */
/*07f0*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0009 */
/*0800*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x002fe200078e000a */
/*0810*/ MOV R5, R13 ; /* 0x0000000d00057202 */
/* 0x000fe40000000f00 */
/*0820*/ ISETP.NE.OR P0, PT, R6, 0x1, P0 ; /* 0x000000010600780c */
/* 0x000fda0000705670 */
/*0830*/ @!P0 BRA 0x9c0 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0840*/ LDG.E R8, [R2.64] ; /* 0x0000000a02087981 */
/* 0x000ea4000c1e1900 */
/*0850*/ IMAD.IADD R9, R8, 0x1, R7 ; /* 0x0000000108097824 */
/* 0x004fca00078e0207 */
/*0860*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x000fe8000c10190a */
/*0870*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040a02087981 */
/* 0x000ea4000c1e1900 */
/*0880*/ IMAD.IADD R11, R9, 0x1, R8 ; /* 0x00000001090b7824 */
/* 0x004fca00078e0208 */
/*0890*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x0001e8000c10190a */
/*08a0*/ LDG.E R8, [R2.64+0x8] ; /* 0x0000080a02087981 */
/* 0x000ea2000c1e1900 */
/*08b0*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fe40007ffe0ff */
/*08c0*/ IADD3 R13, R11, R8, RZ ; /* 0x000000080b0d7210 */
/* 0x004fca0007ffe0ff */
/*08d0*/ STG.E [R4.64+0xc], R13 ; /* 0x00000c0d04007986 */
/* 0x000fe8000c10190a */
/*08e0*/ LDG.E R8, [R2.64+0xc] ; /* 0x00000c0a02087981 */
/* 0x000ea2000c1e1900 */
/*08f0*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe20003f05270 */
/*0900*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0910*/ IADD3 R10, P1, R4, 0x10, RZ ; /* 0x00000010040a7810 */
/* 0x000fc80007f3e0ff */
/*0920*/ IADD3.X R11, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff0b7210 */
/* 0x001fe20000ffe4ff */
/*0930*/ IMAD.IADD R7, R13, 0x1, R8 ; /* 0x000000010d077824 */
/* 0x004fe200078e0208 */
/*0940*/ IADD3 R8, P2, R2, 0x10, RZ ; /* 0x0000001002087810 */
/* 0x000fc80007f5e0ff */
/*0950*/ STG.E [R4.64+0x10], R7 ; /* 0x0000100704007986 */
/* 0x0001e2000c10190a */
/*0960*/ IMAD.X R9, RZ, RZ, R3, P2 ; /* 0x000000ffff097224 */
/* 0x000fe400010e0603 */
/*0970*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0008 */
/*0980*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0009 */
/*0990*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x001fe20000000f00 */
/*09a0*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000b */
/*09b0*/ @P0 BRA 0x840 ; /* 0xfffffe8000000947 */
/* 0x000fea000383ffff */
/*09c0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*09d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*09e0*/ UIADD3 UR8, UR4, -0x1, URZ ; /* 0xffffffff04087890 */
/* 0x000fe4000fffe03f */
/*09f0*/ UMOV UR9, 0x4 ; /* 0x0000000400097882 */
/* 0x000fe40000000000 */
/*0a00*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe40000000a00 */
/*0a10*/ UIMAD.WIDE UR6, UR8, UR9, UR6 ; /* 0x00000009080672a5 */
/* 0x000fe4000f8e0206 */
/*0a20*/ ULDC.64 UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe40000000a00 */
/*0a30*/ UIMAD.WIDE UR4, UR8, UR9, UR4 ; /* 0x00000009080472a5 */
/* 0x000fc4000f8e0204 */
/*0a40*/ IMAD.U32 R2, RZ, RZ, UR6 ; /* 0x00000006ff027e24 */
/* 0x000fe2000f8e00ff */
/*0a50*/ MOV R3, UR7 ; /* 0x0000000700037c02 */
/* 0x000fe20008000f00 */
/*0a60*/ IMAD.U32 R5, RZ, RZ, UR7 ; /* 0x00000007ff057e24 */
/* 0x000fe4000f8e00ff */
/*0a70*/ IMAD.U32 R4, RZ, RZ, UR6 ; /* 0x00000006ff047e24 */
/* 0x000fe2000f8e00ff */
/*0a80*/ MOV R6, R2 ; /* 0x0000000200067202 */
/* 0x000fe20000000f00 */
/*0a90*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0005 */
/*0aa0*/ IMAD.U32 R4, RZ, RZ, UR4 ; /* 0x00000004ff047e24 */
/* 0x000fe2000f8e00ff */
/*0ab0*/ MOV R5, UR5 ; /* 0x0000000500057c02 */
/* 0x000fe20008000f00 */
/*0ac0*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0006 */
/*0ad0*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fc400078e0009 */
/*0ae0*/ LDG.E R4, [R4.64] ; /* 0x0000000a04047981 */
/* 0x000ea8000c1e1900 */
/*0af0*/ LDG.E R7, [R2.64] ; /* 0x0000000a02077981 */
/* 0x000ea2000c1e1900 */
/*0b00*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc80007ffe0ff */
/*0b10*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0b20*/ UIADD3 UR4, UP0, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000ff1e03f */
/*0b30*/ IADD3 R6, P1, R2, 0x4, RZ ; /* 0x0000000402067810 */
/* 0x000fc60007f3e0ff */
/*0b40*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe400087fe43f */
/*0b50*/ IMAD.X R9, RZ, RZ, R3, P1 ; /* 0x000000ffff097224 */
/* 0x000fe200008e0603 */
/*0b60*/ IADD3 R7, R4, R7, RZ ; /* 0x0000000704077210 */
/* 0x004fca0007ffe0ff */
/*0b70*/ STG.E [R2.64+0x4], R7 ; /* 0x0000040702007986 */
/* 0x0001e2000c10190a */
/*0b80*/ @P0 BRA 0xaa0 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*0b90*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ba0*/ BRA 0xba0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cub/cub.cuh>
using namespace cub;
template<int BLOCK_SIZE, int CPG>
__global__ void cal_group_coo_format_nnz_kernel_cm(float *A, int nRows, int nCols, int *pNnzPerGroup)
{
int startIdx = blockIdx.x * CPG;
int nnz = 0;
int nColPerThread = (nCols + BLOCK_SIZE - 1) / BLOCK_SIZE;
int colOffset = threadIdx.x * nColPerThread;
for (int i = threadIdx.x; i < nCols; i+=BLOCK_SIZE) {
for (int j = 0; j < CPG; j++) {
int row = j + startIdx;
if (row >= nRows)
break;
float v = A[row * nCols + i];
if (v != 0.0) {
nnz++;
}
}
}
typedef BlockReduce<int, BLOCK_SIZE> BlockReduceT;
__shared__ typename BlockReduceT::TempStorage temp_storage;
int aggregate = BlockReduceT(temp_storage).Sum(nnz);
if (threadIdx.x == 0) {
pNnzPerGroup[blockIdx.x] = aggregate;
}
}
template<int BLOCK_SIZE, int CPG>
__global__ void convert_to_group_coo_format_kernel_cm(float *A, int nRows, int nCols,
float *pVals, int *pRows, int *pCols, int *pGroupIndex, int *pNnzPerGroup)
{
int startIdx = blockIdx.x * CPG;
int currGroupOffset = pGroupIndex[blockIdx.x];
int cooIndex = currGroupOffset;
float *currVals = pVals + cooIndex;
int *currCols = pCols + cooIndex;
int *currRows = pRows + cooIndex;
__shared__ float sA[BLOCK_SIZE * CPG];
typedef BlockScan<int, BLOCK_SIZE> BlockScanT;
__shared__ typename BlockScanT::TempStorage temp_storage;
__shared__ int sNNz;
sNNz = 0;
__syncthreads();
int end = (nCols + BLOCK_SIZE - 1)/ BLOCK_SIZE * BLOCK_SIZE;
for (int i = threadIdx.x; i < end; i+=BLOCK_SIZE) {
int nnz = 0;
int nnz_i = 0;
for (int j = 0; j < CPG; j++) {
int row = j + startIdx;
if (row < nRows && i < nCols) {
float v = A[row * nCols + i];
sA[j * BLOCK_SIZE + threadIdx.x] = v;
if (v != 0.0)
nnz++;
}
}
BlockScanT(temp_storage).InclusiveSum(nnz, nnz_i);
__syncthreads();
BlockScanT(temp_storage).ExclusiveSum(nnz, nnz);
float *vals = currVals + nnz;
int *cols = currCols + nnz;
int *rows = currRows + nnz;
for (int j = 0; j < CPG; j++) {
int row = j + startIdx;
if (row >= nRows || i >= nCols)
break;
float v = sA[j * BLOCK_SIZE + threadIdx.x];
if (v != 0.0) {
*(vals++) = v;
*(rows++) = row;
*(cols++) = i;
}
}
if (threadIdx.x == BLOCK_SIZE - 1) {
sNNz = nnz_i;
}
__syncthreads();
currVals += sNNz;
currCols += sNNz;
currRows += sNNz;
}
}
template<int BLOCK_SIZE, int CPG>
__global__ void sparse_dense_groupcoo_mat_mul_kernel(float *vals_A, int *cols_A, int *rows_A, int *groupIndex_A, int *nnzPerGroup_A, int wA, int hA, float *B, int wB, int hB, float *C)
{
int Cj = blockIdx.y * BLOCK_SIZE + threadIdx.x;
int Ci0 = blockIdx.x * CPG;
float c0 =0.0; float c1 =0.0; float c2 =0.0; float c3 =0.0;
int groupIdxOfCurrentBlock = groupIndex_A[blockIdx.x];
int nnz = nnzPerGroup_A[blockIdx.x];
float *currValsA = vals_A + groupIdxOfCurrentBlock;
int *currColsA = cols_A + groupIdxOfCurrentBlock;
int *currRowsA = rows_A + groupIdxOfCurrentBlock;
__shared__ float sValsA[BLOCK_SIZE];
__shared__ int sRowsA[BLOCK_SIZE];
__shared__ int sColsA[BLOCK_SIZE];
__shared__ int sNNz[1];
int nIter = (BLOCK_SIZE + nnz - 1) / BLOCK_SIZE;
int extra = nnz & (BLOCK_SIZE - 1);
for (int i = 0; i < nIter; i++) {
sColsA[threadIdx.x] = -1;
sValsA[threadIdx.x] = 0.0;
sNNz[0] = BLOCK_SIZE;
__syncthreads();
int valIdxStart = i * BLOCK_SIZE;
int valIdx = valIdxStart + threadIdx.x;
if (valIdx < nnz) {
sValsA[threadIdx.x] = currValsA[valIdx];
sRowsA[threadIdx.x] = currRowsA[valIdx];
sColsA[threadIdx.x] = currColsA[valIdx];
} else {
sNNz[0] = extra;
}
__syncthreads();
if (Cj < wB) {
int k = 1;
int rNNz = sNNz[0];
int precol = -1;
float b;
for (int j = 0; j < rNNz;) {
int col = sColsA[j];
if (col != precol) {
b = B[col * wB + Cj];
precol = col;
}
float a = sValsA[j];
int currRow = sRowsA[j];
int index = currRow & (CPG-1);
if (index == 0) c0 = fmaf(a,b,c0); else if (index == 1) c1=fmaf(a,b,c1); else if (index == 2) c2=fmaf(a,b,c2); else if (index == 3) c3=fmaf(a,b,c3);
j++;
}
}
__syncthreads();
}
if (Cj < wB) {
if (Ci0 < hA)
C[Cj + Ci0 * wB] = c0;
if (Ci0+1 < hA)
C[Cj + (Ci0 + 1)*wB] = c1;
if (Ci0+2 < hA)
C[Cj + (Ci0 + 2)*wB] = c2;
if (Ci0+3 < hA)
C[Cj + (Ci0 + 3)*wB] = c3;
}
}
__global__ void prefix_sum_kernel2(int *src, int *dst, int n)
{
if (threadIdx.x == 0 && blockIdx.x == 0) {
dst[0] = 0;
for (int i = 1; i < n; i++) {
dst[i] = dst[i-1] + src[i-1];
}
}
} | #include <hip/hip_runtime.h>
#include <hipcub/hipcub.hpp>
using namespace hipcub;
template<int BLOCK_SIZE, int CPG>
__global__ void cal_group_coo_format_nnz_kernel_cm(float *A, int nRows, int nCols, int *pNnzPerGroup)
{
int startIdx = blockIdx.x * CPG;
int nnz = 0;
int nColPerThread = (nCols + BLOCK_SIZE - 1) / BLOCK_SIZE;
int colOffset = threadIdx.x * nColPerThread;
for (int i = threadIdx.x; i < nCols; i+=BLOCK_SIZE) {
for (int j = 0; j < CPG; j++) {
int row = j + startIdx;
if (row >= nRows)
break;
float v = A[row * nCols + i];
if (v != 0.0) {
nnz++;
}
}
}
typedef BlockReduce<int, BLOCK_SIZE> BlockReduceT;
__shared__ typename BlockReduceT::TempStorage temp_storage;
int aggregate = BlockReduceT(temp_storage).Sum(nnz);
if (threadIdx.x == 0) {
pNnzPerGroup[blockIdx.x] = aggregate;
}
}
template<int BLOCK_SIZE, int CPG>
__global__ void convert_to_group_coo_format_kernel_cm(float *A, int nRows, int nCols,
float *pVals, int *pRows, int *pCols, int *pGroupIndex, int *pNnzPerGroup)
{
int startIdx = blockIdx.x * CPG;
int currGroupOffset = pGroupIndex[blockIdx.x];
int cooIndex = currGroupOffset;
float *currVals = pVals + cooIndex;
int *currCols = pCols + cooIndex;
int *currRows = pRows + cooIndex;
__shared__ float sA[BLOCK_SIZE * CPG];
typedef BlockScan<int, BLOCK_SIZE> BlockScanT;
__shared__ typename BlockScanT::TempStorage temp_storage;
__shared__ int sNNz;
sNNz = 0;
__syncthreads();
int end = (nCols + BLOCK_SIZE - 1)/ BLOCK_SIZE * BLOCK_SIZE;
for (int i = threadIdx.x; i < end; i+=BLOCK_SIZE) {
int nnz = 0;
int nnz_i = 0;
for (int j = 0; j < CPG; j++) {
int row = j + startIdx;
if (row < nRows && i < nCols) {
float v = A[row * nCols + i];
sA[j * BLOCK_SIZE + threadIdx.x] = v;
if (v != 0.0)
nnz++;
}
}
BlockScanT(temp_storage).InclusiveSum(nnz, nnz_i);
__syncthreads();
BlockScanT(temp_storage).ExclusiveSum(nnz, nnz);
float *vals = currVals + nnz;
int *cols = currCols + nnz;
int *rows = currRows + nnz;
for (int j = 0; j < CPG; j++) {
int row = j + startIdx;
if (row >= nRows || i >= nCols)
break;
float v = sA[j * BLOCK_SIZE + threadIdx.x];
if (v != 0.0) {
*(vals++) = v;
*(rows++) = row;
*(cols++) = i;
}
}
if (threadIdx.x == BLOCK_SIZE - 1) {
sNNz = nnz_i;
}
__syncthreads();
currVals += sNNz;
currCols += sNNz;
currRows += sNNz;
}
}
template<int BLOCK_SIZE, int CPG>
__global__ void sparse_dense_groupcoo_mat_mul_kernel(float *vals_A, int *cols_A, int *rows_A, int *groupIndex_A, int *nnzPerGroup_A, int wA, int hA, float *B, int wB, int hB, float *C)
{
int Cj = blockIdx.y * BLOCK_SIZE + threadIdx.x;
int Ci0 = blockIdx.x * CPG;
float c0 =0.0; float c1 =0.0; float c2 =0.0; float c3 =0.0;
int groupIdxOfCurrentBlock = groupIndex_A[blockIdx.x];
int nnz = nnzPerGroup_A[blockIdx.x];
float *currValsA = vals_A + groupIdxOfCurrentBlock;
int *currColsA = cols_A + groupIdxOfCurrentBlock;
int *currRowsA = rows_A + groupIdxOfCurrentBlock;
__shared__ float sValsA[BLOCK_SIZE];
__shared__ int sRowsA[BLOCK_SIZE];
__shared__ int sColsA[BLOCK_SIZE];
__shared__ int sNNz[1];
int nIter = (BLOCK_SIZE + nnz - 1) / BLOCK_SIZE;
int extra = nnz & (BLOCK_SIZE - 1);
for (int i = 0; i < nIter; i++) {
sColsA[threadIdx.x] = -1;
sValsA[threadIdx.x] = 0.0;
sNNz[0] = BLOCK_SIZE;
__syncthreads();
int valIdxStart = i * BLOCK_SIZE;
int valIdx = valIdxStart + threadIdx.x;
if (valIdx < nnz) {
sValsA[threadIdx.x] = currValsA[valIdx];
sRowsA[threadIdx.x] = currRowsA[valIdx];
sColsA[threadIdx.x] = currColsA[valIdx];
} else {
sNNz[0] = extra;
}
__syncthreads();
if (Cj < wB) {
int k = 1;
int rNNz = sNNz[0];
int precol = -1;
float b;
for (int j = 0; j < rNNz;) {
int col = sColsA[j];
if (col != precol) {
b = B[col * wB + Cj];
precol = col;
}
float a = sValsA[j];
int currRow = sRowsA[j];
int index = currRow & (CPG-1);
if (index == 0) c0 = fmaf(a,b,c0); else if (index == 1) c1=fmaf(a,b,c1); else if (index == 2) c2=fmaf(a,b,c2); else if (index == 3) c3=fmaf(a,b,c3);
j++;
}
}
__syncthreads();
}
if (Cj < wB) {
if (Ci0 < hA)
C[Cj + Ci0 * wB] = c0;
if (Ci0+1 < hA)
C[Cj + (Ci0 + 1)*wB] = c1;
if (Ci0+2 < hA)
C[Cj + (Ci0 + 2)*wB] = c2;
if (Ci0+3 < hA)
C[Cj + (Ci0 + 3)*wB] = c3;
}
}
__global__ void prefix_sum_kernel2(int *src, int *dst, int n)
{
if (threadIdx.x == 0 && blockIdx.x == 0) {
dst[0] = 0;
for (int i = 1; i < n; i++) {
dst[i] = dst[i-1] + src[i-1];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <hipcub/hipcub.hpp>
using namespace hipcub;
template<int BLOCK_SIZE, int CPG>
__global__ void cal_group_coo_format_nnz_kernel_cm(float *A, int nRows, int nCols, int *pNnzPerGroup)
{
int startIdx = blockIdx.x * CPG;
int nnz = 0;
int nColPerThread = (nCols + BLOCK_SIZE - 1) / BLOCK_SIZE;
int colOffset = threadIdx.x * nColPerThread;
for (int i = threadIdx.x; i < nCols; i+=BLOCK_SIZE) {
for (int j = 0; j < CPG; j++) {
int row = j + startIdx;
if (row >= nRows)
break;
float v = A[row * nCols + i];
if (v != 0.0) {
nnz++;
}
}
}
typedef BlockReduce<int, BLOCK_SIZE> BlockReduceT;
__shared__ typename BlockReduceT::TempStorage temp_storage;
int aggregate = BlockReduceT(temp_storage).Sum(nnz);
if (threadIdx.x == 0) {
pNnzPerGroup[blockIdx.x] = aggregate;
}
}
template<int BLOCK_SIZE, int CPG>
__global__ void convert_to_group_coo_format_kernel_cm(float *A, int nRows, int nCols,
float *pVals, int *pRows, int *pCols, int *pGroupIndex, int *pNnzPerGroup)
{
int startIdx = blockIdx.x * CPG;
int currGroupOffset = pGroupIndex[blockIdx.x];
int cooIndex = currGroupOffset;
float *currVals = pVals + cooIndex;
int *currCols = pCols + cooIndex;
int *currRows = pRows + cooIndex;
__shared__ float sA[BLOCK_SIZE * CPG];
typedef BlockScan<int, BLOCK_SIZE> BlockScanT;
__shared__ typename BlockScanT::TempStorage temp_storage;
__shared__ int sNNz;
sNNz = 0;
__syncthreads();
int end = (nCols + BLOCK_SIZE - 1)/ BLOCK_SIZE * BLOCK_SIZE;
for (int i = threadIdx.x; i < end; i+=BLOCK_SIZE) {
int nnz = 0;
int nnz_i = 0;
for (int j = 0; j < CPG; j++) {
int row = j + startIdx;
if (row < nRows && i < nCols) {
float v = A[row * nCols + i];
sA[j * BLOCK_SIZE + threadIdx.x] = v;
if (v != 0.0)
nnz++;
}
}
BlockScanT(temp_storage).InclusiveSum(nnz, nnz_i);
__syncthreads();
BlockScanT(temp_storage).ExclusiveSum(nnz, nnz);
float *vals = currVals + nnz;
int *cols = currCols + nnz;
int *rows = currRows + nnz;
for (int j = 0; j < CPG; j++) {
int row = j + startIdx;
if (row >= nRows || i >= nCols)
break;
float v = sA[j * BLOCK_SIZE + threadIdx.x];
if (v != 0.0) {
*(vals++) = v;
*(rows++) = row;
*(cols++) = i;
}
}
if (threadIdx.x == BLOCK_SIZE - 1) {
sNNz = nnz_i;
}
__syncthreads();
currVals += sNNz;
currCols += sNNz;
currRows += sNNz;
}
}
template<int BLOCK_SIZE, int CPG>
__global__ void sparse_dense_groupcoo_mat_mul_kernel(float *vals_A, int *cols_A, int *rows_A, int *groupIndex_A, int *nnzPerGroup_A, int wA, int hA, float *B, int wB, int hB, float *C)
{
int Cj = blockIdx.y * BLOCK_SIZE + threadIdx.x;
int Ci0 = blockIdx.x * CPG;
float c0 =0.0; float c1 =0.0; float c2 =0.0; float c3 =0.0;
int groupIdxOfCurrentBlock = groupIndex_A[blockIdx.x];
int nnz = nnzPerGroup_A[blockIdx.x];
float *currValsA = vals_A + groupIdxOfCurrentBlock;
int *currColsA = cols_A + groupIdxOfCurrentBlock;
int *currRowsA = rows_A + groupIdxOfCurrentBlock;
__shared__ float sValsA[BLOCK_SIZE];
__shared__ int sRowsA[BLOCK_SIZE];
__shared__ int sColsA[BLOCK_SIZE];
__shared__ int sNNz[1];
int nIter = (BLOCK_SIZE + nnz - 1) / BLOCK_SIZE;
int extra = nnz & (BLOCK_SIZE - 1);
for (int i = 0; i < nIter; i++) {
sColsA[threadIdx.x] = -1;
sValsA[threadIdx.x] = 0.0;
sNNz[0] = BLOCK_SIZE;
__syncthreads();
int valIdxStart = i * BLOCK_SIZE;
int valIdx = valIdxStart + threadIdx.x;
if (valIdx < nnz) {
sValsA[threadIdx.x] = currValsA[valIdx];
sRowsA[threadIdx.x] = currRowsA[valIdx];
sColsA[threadIdx.x] = currColsA[valIdx];
} else {
sNNz[0] = extra;
}
__syncthreads();
if (Cj < wB) {
int k = 1;
int rNNz = sNNz[0];
int precol = -1;
float b;
for (int j = 0; j < rNNz;) {
int col = sColsA[j];
if (col != precol) {
b = B[col * wB + Cj];
precol = col;
}
float a = sValsA[j];
int currRow = sRowsA[j];
int index = currRow & (CPG-1);
if (index == 0) c0 = fmaf(a,b,c0); else if (index == 1) c1=fmaf(a,b,c1); else if (index == 2) c2=fmaf(a,b,c2); else if (index == 3) c3=fmaf(a,b,c3);
j++;
}
}
__syncthreads();
}
if (Cj < wB) {
if (Ci0 < hA)
C[Cj + Ci0 * wB] = c0;
if (Ci0+1 < hA)
C[Cj + (Ci0 + 1)*wB] = c1;
if (Ci0+2 < hA)
C[Cj + (Ci0 + 2)*wB] = c2;
if (Ci0+3 < hA)
C[Cj + (Ci0 + 3)*wB] = c3;
}
}
__global__ void prefix_sum_kernel2(int *src, int *dst, int n)
{
if (threadIdx.x == 0 && blockIdx.x == 0) {
dst[0] = 0;
for (int i = 1; i < n; i++) {
dst[i] = dst[i-1] + src[i-1];
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18prefix_sum_kernel2PiS_i
.globl _Z18prefix_sum_kernel2PiS_i
.p2align 8
.type _Z18prefix_sum_kernel2PiS_i,@function
_Z18prefix_sum_kernel2PiS_i:
v_or_b32_e32 v0, s15, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_4
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x8
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 2
global_store_b32 v0, v0, s[2:3]
s_cbranch_scc1 .LBB0_4
global_load_b32 v1, v0, s[2:3]
s_load_b64 s[0:1], s[0:1], 0x0
s_add_i32 s4, s4, -1
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
.LBB0_3:
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v0, s[0:1]
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_add_i32 s4, s4, -1
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[2:3]
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s4, 0
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18prefix_sum_kernel2PiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18prefix_sum_kernel2PiS_i, .Lfunc_end0-_Z18prefix_sum_kernel2PiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18prefix_sum_kernel2PiS_i
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z18prefix_sum_kernel2PiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hipcub/hipcub.hpp>
using namespace hipcub;
template<int BLOCK_SIZE, int CPG>
__global__ void cal_group_coo_format_nnz_kernel_cm(float *A, int nRows, int nCols, int *pNnzPerGroup)
{
int startIdx = blockIdx.x * CPG;
int nnz = 0;
int nColPerThread = (nCols + BLOCK_SIZE - 1) / BLOCK_SIZE;
int colOffset = threadIdx.x * nColPerThread;
for (int i = threadIdx.x; i < nCols; i+=BLOCK_SIZE) {
for (int j = 0; j < CPG; j++) {
int row = j + startIdx;
if (row >= nRows)
break;
float v = A[row * nCols + i];
if (v != 0.0) {
nnz++;
}
}
}
typedef BlockReduce<int, BLOCK_SIZE> BlockReduceT;
__shared__ typename BlockReduceT::TempStorage temp_storage;
int aggregate = BlockReduceT(temp_storage).Sum(nnz);
if (threadIdx.x == 0) {
pNnzPerGroup[blockIdx.x] = aggregate;
}
}
template<int BLOCK_SIZE, int CPG>
__global__ void convert_to_group_coo_format_kernel_cm(float *A, int nRows, int nCols,
float *pVals, int *pRows, int *pCols, int *pGroupIndex, int *pNnzPerGroup)
{
int startIdx = blockIdx.x * CPG;
int currGroupOffset = pGroupIndex[blockIdx.x];
int cooIndex = currGroupOffset;
float *currVals = pVals + cooIndex;
int *currCols = pCols + cooIndex;
int *currRows = pRows + cooIndex;
__shared__ float sA[BLOCK_SIZE * CPG];
typedef BlockScan<int, BLOCK_SIZE> BlockScanT;
__shared__ typename BlockScanT::TempStorage temp_storage;
__shared__ int sNNz;
sNNz = 0;
__syncthreads();
int end = (nCols + BLOCK_SIZE - 1)/ BLOCK_SIZE * BLOCK_SIZE;
for (int i = threadIdx.x; i < end; i+=BLOCK_SIZE) {
int nnz = 0;
int nnz_i = 0;
for (int j = 0; j < CPG; j++) {
int row = j + startIdx;
if (row < nRows && i < nCols) {
float v = A[row * nCols + i];
sA[j * BLOCK_SIZE + threadIdx.x] = v;
if (v != 0.0)
nnz++;
}
}
BlockScanT(temp_storage).InclusiveSum(nnz, nnz_i);
__syncthreads();
BlockScanT(temp_storage).ExclusiveSum(nnz, nnz);
float *vals = currVals + nnz;
int *cols = currCols + nnz;
int *rows = currRows + nnz;
for (int j = 0; j < CPG; j++) {
int row = j + startIdx;
if (row >= nRows || i >= nCols)
break;
float v = sA[j * BLOCK_SIZE + threadIdx.x];
if (v != 0.0) {
*(vals++) = v;
*(rows++) = row;
*(cols++) = i;
}
}
if (threadIdx.x == BLOCK_SIZE - 1) {
sNNz = nnz_i;
}
__syncthreads();
currVals += sNNz;
currCols += sNNz;
currRows += sNNz;
}
}
template<int BLOCK_SIZE, int CPG>
__global__ void sparse_dense_groupcoo_mat_mul_kernel(float *vals_A, int *cols_A, int *rows_A, int *groupIndex_A, int *nnzPerGroup_A, int wA, int hA, float *B, int wB, int hB, float *C)
{
int Cj = blockIdx.y * BLOCK_SIZE + threadIdx.x;
int Ci0 = blockIdx.x * CPG;
float c0 =0.0; float c1 =0.0; float c2 =0.0; float c3 =0.0;
int groupIdxOfCurrentBlock = groupIndex_A[blockIdx.x];
int nnz = nnzPerGroup_A[blockIdx.x];
float *currValsA = vals_A + groupIdxOfCurrentBlock;
int *currColsA = cols_A + groupIdxOfCurrentBlock;
int *currRowsA = rows_A + groupIdxOfCurrentBlock;
__shared__ float sValsA[BLOCK_SIZE];
__shared__ int sRowsA[BLOCK_SIZE];
__shared__ int sColsA[BLOCK_SIZE];
__shared__ int sNNz[1];
int nIter = (BLOCK_SIZE + nnz - 1) / BLOCK_SIZE;
int extra = nnz & (BLOCK_SIZE - 1);
for (int i = 0; i < nIter; i++) {
sColsA[threadIdx.x] = -1;
sValsA[threadIdx.x] = 0.0;
sNNz[0] = BLOCK_SIZE;
__syncthreads();
int valIdxStart = i * BLOCK_SIZE;
int valIdx = valIdxStart + threadIdx.x;
if (valIdx < nnz) {
sValsA[threadIdx.x] = currValsA[valIdx];
sRowsA[threadIdx.x] = currRowsA[valIdx];
sColsA[threadIdx.x] = currColsA[valIdx];
} else {
sNNz[0] = extra;
}
__syncthreads();
if (Cj < wB) {
int k = 1;
int rNNz = sNNz[0];
int precol = -1;
float b;
for (int j = 0; j < rNNz;) {
int col = sColsA[j];
if (col != precol) {
b = B[col * wB + Cj];
precol = col;
}
float a = sValsA[j];
int currRow = sRowsA[j];
int index = currRow & (CPG-1);
if (index == 0) c0 = fmaf(a,b,c0); else if (index == 1) c1=fmaf(a,b,c1); else if (index == 2) c2=fmaf(a,b,c2); else if (index == 3) c3=fmaf(a,b,c3);
j++;
}
}
__syncthreads();
}
if (Cj < wB) {
if (Ci0 < hA)
C[Cj + Ci0 * wB] = c0;
if (Ci0+1 < hA)
C[Cj + (Ci0 + 1)*wB] = c1;
if (Ci0+2 < hA)
C[Cj + (Ci0 + 2)*wB] = c2;
if (Ci0+3 < hA)
C[Cj + (Ci0 + 3)*wB] = c3;
}
}
__global__ void prefix_sum_kernel2(int *src, int *dst, int n)
{
if (threadIdx.x == 0 && blockIdx.x == 0) {
dst[0] = 0;
for (int i = 1; i < n; i++) {
dst[i] = dst[i-1] + src[i-1];
}
}
} | .text
.file "gcoo_spdm_kernels.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z33__device_stub__prefix_sum_kernel2PiS_i # -- Begin function _Z33__device_stub__prefix_sum_kernel2PiS_i
.p2align 4, 0x90
.type _Z33__device_stub__prefix_sum_kernel2PiS_i,@function
_Z33__device_stub__prefix_sum_kernel2PiS_i: # @_Z33__device_stub__prefix_sum_kernel2PiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18prefix_sum_kernel2PiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z33__device_stub__prefix_sum_kernel2PiS_i, .Lfunc_end0-_Z33__device_stub__prefix_sum_kernel2PiS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18prefix_sum_kernel2PiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18prefix_sum_kernel2PiS_i,@object # @_Z18prefix_sum_kernel2PiS_i
.section .rodata,"a",@progbits
.globl _Z18prefix_sum_kernel2PiS_i
.p2align 3, 0x0
_Z18prefix_sum_kernel2PiS_i:
.quad _Z33__device_stub__prefix_sum_kernel2PiS_i
.size _Z18prefix_sum_kernel2PiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18prefix_sum_kernel2PiS_i"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__prefix_sum_kernel2PiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18prefix_sum_kernel2PiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z18prefix_sum_kernel2PiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ LOP3.LUT P0, RZ, R0, UR4, RZ, 0xfc, !PT ; /* 0x0000000400ff7c12 */
/* 0x001fda000f80fcff */
/*0040*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0050*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff007624 */
/* 0x000fe200078e00ff */
/*0060*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe20000000f00 */
/*0070*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe40000000a00 */
/*0090*/ ISETP.GE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe40003f06270 */
/*00a0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001f6000c10190a */
/*00b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R0.reuse, -0x2, RZ ; /* 0xfffffffe00027810 */
/* 0x041fe20007ffe0ff */
/*00d0*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe20000000000 */
/*00e0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc40007ffe0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0100*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fd600078ec0ff */
/*0110*/ @!P0 BRA 0x9c0 ; /* 0x000008a000008947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R6, -R0, c[0x0][0x170], RZ ; /* 0x00005c0000067a10 */
/* 0x000fe20007ffe1ff */
/*0130*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe20000000000 */
/*0140*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0150*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0160*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0170*/ ISETP.GT.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe20003f04270 */
/*0180*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe400078e00ff */
/*0190*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fd400078e00ff */
/*01a0*/ @!P0 BRA 0x840 ; /* 0x0000069000008947 */
/* 0x000fea0003800000 */
/*01b0*/ IADD3 R8, R6, -0x1, RZ ; /* 0xffffffff06087810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*01d0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fda0003f24270 */
/*01e0*/ @!P1 BRA 0x5c0 ; /* 0x000003d000009947 */
/* 0x000fea0003800000 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0200*/ LDG.E R8, [R2.64] ; /* 0x0000000a02087981 */
/* 0x000ea4000c1e1900 */
/*0210*/ IMAD.IADD R7, R8, 0x1, R7 ; /* 0x0000000108077824 */
/* 0x004fca00078e0207 */
/*0220*/ STG.E [R4.64+0x4], R7 ; /* 0x0000040704007986 */
/* 0x0001e8000c10190a */
/*0230*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040a02087981 */
/* 0x000ea4000c1e1900 */
/*0240*/ IMAD.IADD R9, R7, 0x1, R8 ; /* 0x0000000107097824 */
/* 0x004fca00078e0208 */
/*0250*/ STG.E [R4.64+0x8], R9 ; /* 0x0000080904007986 */
/* 0x0003e8000c10190a */
/*0260*/ LDG.E R8, [R2.64+0x8] ; /* 0x0000080a02087981 */
/* 0x000ea4000c1e1900 */
/*0270*/ IADD3 R11, R9, R8, RZ ; /* 0x00000008090b7210 */
/* 0x004fca0007ffe0ff */
/*0280*/ STG.E [R4.64+0xc], R11 ; /* 0x00000c0b04007986 */
/* 0x0005e8000c10190a */
/*0290*/ LDG.E R8, [R2.64+0xc] ; /* 0x00000c0a02087981 */
/* 0x000ee4000c1e1900 */
/*02a0*/ IMAD.IADD R13, R11, 0x1, R8 ; /* 0x000000010b0d7824 */
/* 0x008fca00078e0208 */
/*02b0*/ STG.E [R4.64+0x10], R13 ; /* 0x0000100d04007986 */
/* 0x0007e8000c10190a */
/*02c0*/ LDG.E R8, [R2.64+0x10] ; /* 0x0000100a02087981 */
/* 0x000e24000c1e1900 */
/*02d0*/ IMAD.IADD R7, R13, 0x1, R8 ; /* 0x000000010d077824 */
/* 0x001fca00078e0208 */
/*02e0*/ STG.E [R4.64+0x14], R7 ; /* 0x0000140704007986 */
/* 0x0001e8000c10190a */
/*02f0*/ LDG.E R8, [R2.64+0x14] ; /* 0x0000140a02087981 */
/* 0x000e64000c1e1900 */
/*0300*/ IMAD.IADD R9, R7, 0x1, R8 ; /* 0x0000000107097824 */
/* 0x002fca00078e0208 */
/*0310*/ STG.E [R4.64+0x18], R9 ; /* 0x0000180904007986 */
/* 0x0003e8000c10190a */
/*0320*/ LDG.E R8, [R2.64+0x18] ; /* 0x0000180a02087981 */
/* 0x000ea4000c1e1900 */
/*0330*/ IADD3 R11, R9, R8, RZ ; /* 0x00000008090b7210 */
/* 0x004fca0007ffe0ff */
/*0340*/ STG.E [R4.64+0x1c], R11 ; /* 0x00001c0b04007986 */
/* 0x0005e8000c10190a */
/*0350*/ LDG.E R8, [R2.64+0x1c] ; /* 0x00001c0a02087981 */
/* 0x000ee4000c1e1900 */
/*0360*/ IMAD.IADD R13, R11, 0x1, R8 ; /* 0x000000010b0d7824 */
/* 0x008fca00078e0208 */
/*0370*/ STG.E [R4.64+0x20], R13 ; /* 0x0000200d04007986 */
/* 0x0007e8000c10190a */
/*0380*/ LDG.E R8, [R2.64+0x20] ; /* 0x0000200a02087981 */
/* 0x000e24000c1e1900 */
/*0390*/ IMAD.IADD R7, R13, 0x1, R8 ; /* 0x000000010d077824 */
/* 0x001fca00078e0208 */
/*03a0*/ STG.E [R4.64+0x24], R7 ; /* 0x0000240704007986 */
/* 0x000fe8000c10190a */
/*03b0*/ LDG.E R8, [R2.64+0x24] ; /* 0x0000240a02087981 */
/* 0x000e64000c1e1900 */
/*03c0*/ IMAD.IADD R9, R7, 0x1, R8 ; /* 0x0000000107097824 */
/* 0x002fca00078e0208 */
/*03d0*/ STG.E [R4.64+0x28], R9 ; /* 0x0000280904007986 */
/* 0x0001e8000c10190a */
/*03e0*/ LDG.E R8, [R2.64+0x28] ; /* 0x0000280a02087981 */
/* 0x000ea4000c1e1900 */
/*03f0*/ IADD3 R11, R9, R8, RZ ; /* 0x00000008090b7210 */
/* 0x004fca0007ffe0ff */
/*0400*/ STG.E [R4.64+0x2c], R11 ; /* 0x00002c0b04007986 */
/* 0x0003e8000c10190a */
/*0410*/ LDG.E R8, [R2.64+0x2c] ; /* 0x00002c0a02087981 */
/* 0x000ee4000c1e1900 */
/*0420*/ IMAD.IADD R13, R11, 0x1, R8 ; /* 0x000000010b0d7824 */
/* 0x008fca00078e0208 */
/*0430*/ STG.E [R4.64+0x30], R13 ; /* 0x0000300d04007986 */
/* 0x0005e8000c10190a */
/*0440*/ LDG.E R8, [R2.64+0x30] ; /* 0x0000300a02087981 */
/* 0x000ee4000c1e1900 */
/*0450*/ IMAD.IADD R15, R13, 0x1, R8 ; /* 0x000000010d0f7824 */
/* 0x008fca00078e0208 */
/*0460*/ STG.E [R4.64+0x34], R15 ; /* 0x0000340f04007986 */
/* 0x000fe8000c10190a */
/*0470*/ LDG.E R8, [R2.64+0x34] ; /* 0x0000340a02087981 */
/* 0x000e24000c1e1900 */
/*0480*/ IMAD.IADD R9, R15, 0x1, R8 ; /* 0x000000010f097824 */
/* 0x001fca00078e0208 */
/*0490*/ STG.E [R4.64+0x38], R9 ; /* 0x0000380904007986 */
/* 0x0001e8000c10190a */
/*04a0*/ LDG.E R8, [R2.64+0x38] ; /* 0x0000380a02087981 */
/* 0x000e62000c1e1900 */
/*04b0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fe40007ffe0ff */
/*04c0*/ IADD3 R11, R9, R8, RZ ; /* 0x00000008090b7210 */
/* 0x002fca0007ffe0ff */
/*04d0*/ STG.E [R4.64+0x3c], R11 ; /* 0x00003c0b04007986 */
/* 0x000fe8000c10190a */
/*04e0*/ LDG.E R8, [R2.64+0x3c] ; /* 0x00003c0a02087981 */
/* 0x000ee2000c1e1900 */
/*04f0*/ ISETP.GT.AND P1, PT, R6, 0xd, PT ; /* 0x0000000d0600780c */
/* 0x000fe20003f24270 */
/*0500*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*0510*/ IADD3 R10, P2, R4, 0x40, RZ ; /* 0x00000040040a7810 */
/* 0x000fca0007f5e0ff */
/*0520*/ IMAD.X R13, RZ, RZ, R5, P2 ; /* 0x000000ffff0d7224 */
/* 0x004fe400010e0605 */
/*0530*/ IMAD.IADD R7, R11, 0x1, R8 ; /* 0x000000010b077824 */
/* 0x008fe200078e0208 */
/*0540*/ IADD3 R8, P3, R2, 0x40, RZ ; /* 0x0000004002087810 */
/* 0x000fc80007f7e0ff */
/*0550*/ STG.E [R4.64+0x40], R7 ; /* 0x0000400704007986 */
/* 0x0003e2000c10190a */
/*0560*/ IMAD.X R9, RZ, RZ, R3, P3 ; /* 0x000000ffff097224 */
/* 0x001fe200018e0603 */
/*0570*/ MOV R2, R8 ; /* 0x0000000800027202 */
/* 0x000fc60000000f00 */
/*0580*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0009 */
/*0590*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x002fe400078e000a */
/*05a0*/ IMAD.MOV.U32 R5, RZ, RZ, R13 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000d */
/*05b0*/ @P1 BRA 0x200 ; /* 0xfffffc4000001947 */
/* 0x000fea000383ffff */
/*05c0*/ IADD3 R8, R6, -0x1, RZ ; /* 0xffffffff06087810 */
/* 0x000fc80007ffe0ff */
/*05d0*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*05e0*/ @!P1 BRA 0x820 ; /* 0x0000023000009947 */
/* 0x000fea0003800000 */
/*05f0*/ LDG.E R8, [R2.64] ; /* 0x0000000a02087981 */
/* 0x000ea4000c1e1900 */
/*0600*/ IADD3 R7, R7, R8, RZ ; /* 0x0000000807077210 */
/* 0x004fca0007ffe0ff */
/*0610*/ STG.E [R4.64+0x4], R7 ; /* 0x0000040704007986 */
/* 0x000fe8000c10190a */
/*0620*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040a02087981 */
/* 0x000ea4000c1e1900 */
/*0630*/ IMAD.IADD R9, R7, 0x1, R8 ; /* 0x0000000107097824 */
/* 0x004fca00078e0208 */
/*0640*/ STG.E [R4.64+0x8], R9 ; /* 0x0000080904007986 */
/* 0x0001e8000c10190a */
/*0650*/ LDG.E R8, [R2.64+0x8] ; /* 0x0000080a02087981 */
/* 0x000ea4000c1e1900 */
/*0660*/ IMAD.IADD R11, R9, 0x1, R8 ; /* 0x00000001090b7824 */
/* 0x004fca00078e0208 */
/*0670*/ STG.E [R4.64+0xc], R11 ; /* 0x00000c0b04007986 */
/* 0x0003e8000c10190a */
/*0680*/ LDG.E R8, [R2.64+0xc] ; /* 0x00000c0a02087981 */
/* 0x000ea4000c1e1900 */
/*0690*/ IMAD.IADD R13, R11, 0x1, R8 ; /* 0x000000010b0d7824 */
/* 0x004fca00078e0208 */
/*06a0*/ STG.E [R4.64+0x10], R13 ; /* 0x0000100d04007986 */
/* 0x0005e8000c10190a */
/*06b0*/ LDG.E R8, [R2.64+0x10] ; /* 0x0000100a02087981 */
/* 0x000ee4000c1e1900 */
/*06c0*/ IADD3 R15, R13, R8, RZ ; /* 0x000000080d0f7210 */
/* 0x008fca0007ffe0ff */
/*06d0*/ STG.E [R4.64+0x14], R15 ; /* 0x0000140f04007986 */
/* 0x000fe8000c10190a */
/*06e0*/ LDG.E R8, [R2.64+0x14] ; /* 0x0000140a02087981 */
/* 0x000e24000c1e1900 */
/*06f0*/ IMAD.IADD R9, R15, 0x1, R8 ; /* 0x000000010f097824 */
/* 0x001fca00078e0208 */
/*0700*/ STG.E [R4.64+0x18], R9 ; /* 0x0000180904007986 */
/* 0x0001e8000c10190a */
/*0710*/ LDG.E R8, [R2.64+0x18] ; /* 0x0000180a02087981 */
/* 0x000e64000c1e1900 */
/*0720*/ IMAD.IADD R11, R9, 0x1, R8 ; /* 0x00000001090b7824 */
/* 0x002fca00078e0208 */
/*0730*/ STG.E [R4.64+0x1c], R11 ; /* 0x00001c0b04007986 */
/* 0x000fe8000c10190a */
/*0740*/ LDG.E R8, [R2.64+0x1c] ; /* 0x00001c0a02087981 */
/* 0x000ee2000c1e1900 */
/*0750*/ IADD3 R10, P1, R4, 0x20, RZ ; /* 0x00000020040a7810 */
/* 0x000fe20007f3e0ff */
/*0760*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0770*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0780*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0790*/ IMAD.X R13, RZ, RZ, R5, P1 ; /* 0x000000ffff0d7224 */
/* 0x004fe200008e0605 */
/*07a0*/ IADD3 R7, R11, R8, RZ ; /* 0x000000080b077210 */
/* 0x008fc40007ffe0ff */
/*07b0*/ IADD3 R8, P2, R2, 0x20, RZ ; /* 0x0000002002087810 */
/* 0x000fc60007f5e0ff */
/*07c0*/ STG.E [R4.64+0x20], R7 ; /* 0x0000200704007986 */
/* 0x0003e2000c10190a */
/*07d0*/ MOV R2, R8 ; /* 0x0000000800027202 */
/* 0x000fe20000000f00 */
/*07e0*/ IMAD.X R9, RZ, RZ, R3, P2 ; /* 0x000000ffff097224 */
/* 0x001fc800010e0603 */
/*07f0*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0009 */
/*0800*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x002fe200078e000a */
/*0810*/ MOV R5, R13 ; /* 0x0000000d00057202 */
/* 0x000fe40000000f00 */
/*0820*/ ISETP.NE.OR P0, PT, R6, 0x1, P0 ; /* 0x000000010600780c */
/* 0x000fda0000705670 */
/*0830*/ @!P0 BRA 0x9c0 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0840*/ LDG.E R8, [R2.64] ; /* 0x0000000a02087981 */
/* 0x000ea4000c1e1900 */
/*0850*/ IMAD.IADD R9, R8, 0x1, R7 ; /* 0x0000000108097824 */
/* 0x004fca00078e0207 */
/*0860*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x000fe8000c10190a */
/*0870*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040a02087981 */
/* 0x000ea4000c1e1900 */
/*0880*/ IMAD.IADD R11, R9, 0x1, R8 ; /* 0x00000001090b7824 */
/* 0x004fca00078e0208 */
/*0890*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x0001e8000c10190a */
/*08a0*/ LDG.E R8, [R2.64+0x8] ; /* 0x0000080a02087981 */
/* 0x000ea2000c1e1900 */
/*08b0*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fe40007ffe0ff */
/*08c0*/ IADD3 R13, R11, R8, RZ ; /* 0x000000080b0d7210 */
/* 0x004fca0007ffe0ff */
/*08d0*/ STG.E [R4.64+0xc], R13 ; /* 0x00000c0d04007986 */
/* 0x000fe8000c10190a */
/*08e0*/ LDG.E R8, [R2.64+0xc] ; /* 0x00000c0a02087981 */
/* 0x000ea2000c1e1900 */
/*08f0*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe20003f05270 */
/*0900*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0910*/ IADD3 R10, P1, R4, 0x10, RZ ; /* 0x00000010040a7810 */
/* 0x000fc80007f3e0ff */
/*0920*/ IADD3.X R11, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff0b7210 */
/* 0x001fe20000ffe4ff */
/*0930*/ IMAD.IADD R7, R13, 0x1, R8 ; /* 0x000000010d077824 */
/* 0x004fe200078e0208 */
/*0940*/ IADD3 R8, P2, R2, 0x10, RZ ; /* 0x0000001002087810 */
/* 0x000fc80007f5e0ff */
/*0950*/ STG.E [R4.64+0x10], R7 ; /* 0x0000100704007986 */
/* 0x0001e2000c10190a */
/*0960*/ IMAD.X R9, RZ, RZ, R3, P2 ; /* 0x000000ffff097224 */
/* 0x000fe400010e0603 */
/*0970*/ IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0008 */
/*0980*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0009 */
/*0990*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x001fe20000000f00 */
/*09a0*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000b */
/*09b0*/ @P0 BRA 0x840 ; /* 0xfffffe8000000947 */
/* 0x000fea000383ffff */
/*09c0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*09d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*09e0*/ UIADD3 UR8, UR4, -0x1, URZ ; /* 0xffffffff04087890 */
/* 0x000fe4000fffe03f */
/*09f0*/ UMOV UR9, 0x4 ; /* 0x0000000400097882 */
/* 0x000fe40000000000 */
/*0a00*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe40000000a00 */
/*0a10*/ UIMAD.WIDE UR6, UR8, UR9, UR6 ; /* 0x00000009080672a5 */
/* 0x000fe4000f8e0206 */
/*0a20*/ ULDC.64 UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe40000000a00 */
/*0a30*/ UIMAD.WIDE UR4, UR8, UR9, UR4 ; /* 0x00000009080472a5 */
/* 0x000fc4000f8e0204 */
/*0a40*/ IMAD.U32 R2, RZ, RZ, UR6 ; /* 0x00000006ff027e24 */
/* 0x000fe2000f8e00ff */
/*0a50*/ MOV R3, UR7 ; /* 0x0000000700037c02 */
/* 0x000fe20008000f00 */
/*0a60*/ IMAD.U32 R5, RZ, RZ, UR7 ; /* 0x00000007ff057e24 */
/* 0x000fe4000f8e00ff */
/*0a70*/ IMAD.U32 R4, RZ, RZ, UR6 ; /* 0x00000006ff047e24 */
/* 0x000fe2000f8e00ff */
/*0a80*/ MOV R6, R2 ; /* 0x0000000200067202 */
/* 0x000fe20000000f00 */
/*0a90*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0005 */
/*0aa0*/ IMAD.U32 R4, RZ, RZ, UR4 ; /* 0x00000004ff047e24 */
/* 0x000fe2000f8e00ff */
/*0ab0*/ MOV R5, UR5 ; /* 0x0000000500057c02 */
/* 0x000fe20008000f00 */
/*0ac0*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0006 */
/*0ad0*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fc400078e0009 */
/*0ae0*/ LDG.E R4, [R4.64] ; /* 0x0000000a04047981 */
/* 0x000ea8000c1e1900 */
/*0af0*/ LDG.E R7, [R2.64] ; /* 0x0000000a02077981 */
/* 0x000ea2000c1e1900 */
/*0b00*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc80007ffe0ff */
/*0b10*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0b20*/ UIADD3 UR4, UP0, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000ff1e03f */
/*0b30*/ IADD3 R6, P1, R2, 0x4, RZ ; /* 0x0000000402067810 */
/* 0x000fc60007f3e0ff */
/*0b40*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe400087fe43f */
/*0b50*/ IMAD.X R9, RZ, RZ, R3, P1 ; /* 0x000000ffff097224 */
/* 0x000fe200008e0603 */
/*0b60*/ IADD3 R7, R4, R7, RZ ; /* 0x0000000704077210 */
/* 0x004fca0007ffe0ff */
/*0b70*/ STG.E [R2.64+0x4], R7 ; /* 0x0000040702007986 */
/* 0x0001e2000c10190a */
/*0b80*/ @P0 BRA 0xaa0 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*0b90*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ba0*/ BRA 0xba0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18prefix_sum_kernel2PiS_i
.globl _Z18prefix_sum_kernel2PiS_i
.p2align 8
.type _Z18prefix_sum_kernel2PiS_i,@function
_Z18prefix_sum_kernel2PiS_i:
v_or_b32_e32 v0, s15, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_4
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x8
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 2
global_store_b32 v0, v0, s[2:3]
s_cbranch_scc1 .LBB0_4
global_load_b32 v1, v0, s[2:3]
s_load_b64 s[0:1], s[0:1], 0x0
s_add_i32 s4, s4, -1
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
.LBB0_3:
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v0, s[0:1]
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_add_i32 s4, s4, -1
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[2:3]
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s4, 0
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18prefix_sum_kernel2PiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18prefix_sum_kernel2PiS_i, .Lfunc_end0-_Z18prefix_sum_kernel2PiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18prefix_sum_kernel2PiS_i
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z18prefix_sum_kernel2PiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <iostream>
#include <fstream>
#include <math.h>
#include <stdlib.h>
#include <time.h>
using namespace std;
float randomNumber(int max)
{
return (rand() % (max + 1 ));
}
struct vect
{
float x;
float y;
float z;
};
struct vectProd
{
vect v1;
vect v2;
float dot;
};
__global__ void dot(vectProd* pointer)
{
int threadId = threadIdx.x + blockIdx.x * blockDim.x;
pointer[threadId].dot =
pointer[threadId].v1.x*pointer[threadId].v2.x
+pointer[threadId].v1.y*pointer[threadId].v2.y
+pointer[threadId].v1.z*pointer[threadId].v2.z;
}
void openDotKernelAndTime(int blocksize, int gridsize, vectProd* devicePointer, std::ofstream &f )
{
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
dim3 dimBlock1(blocksize);
dim3 dimGrid1(gridsize);
cudaEventRecord(start, 0);
dot<<<dimGrid1, dimBlock1>>>(devicePointer);
f << "ErrorCode " <<cudaThreadSynchronize()<<std::endl;
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
f << "Blöcke: "<< gridsize << ", Threads: "<< blocksize << std::endl;
f << ", Timing:" << fixed<< elapsedTime <<std::endl;
}
int main(int argc, char** argv)
{
srand((unsigned) time(NULL));
vectProd* hostPointer;
std::ofstream f("timing.txt");
f << "Timing for different Grid / Block size:" << std::endl << std::endl;
size_t Elements = 1024*1024;
size_t sizeInBytes = Elements * sizeof(*hostPointer);
hostPointer = (vectProd*) malloc(sizeInBytes);
cudaHostAlloc(&hostPointer, sizeInBytes, cudaHostAllocDefault);
memset(hostPointer, 0, Elements);
for ( int l=0; l<Elements; l++ )
{
hostPointer[l].v1.x=randomNumber(10);
hostPointer[l].v1.y=randomNumber(10);
hostPointer[l].v1.z=randomNumber(10);
hostPointer[l].v2.x=randomNumber(10);
hostPointer[l].v2.y=randomNumber(10);
hostPointer[l].v2.z=randomNumber(10);
}
vectProd* devicePointer;
f << "ErrorCode " <<cudaMalloc(&devicePointer, sizeInBytes)<< std::endl;
f << "ErrorCode " <<cudaMemcpy(devicePointer, hostPointer, sizeInBytes, cudaMemcpyHostToDevice) <<std::endl;
f << "ErrorCode "<< cudaThreadSynchronize() << std::endl;
int blocksize;
int gridsize;
//Maximum sizes of each dimension of a block: 1024 x 1024 x 64
//Maximum sizes of each dimension of a grid: 65535 x 65535 x 1
blocksize=32;
gridsize=32768;
openDotKernelAndTime(blocksize,gridsize, devicePointer, f);
blocksize=64;
gridsize=16384;
openDotKernelAndTime(blocksize,gridsize, devicePointer, f);
blocksize=128;
gridsize=8192;
openDotKernelAndTime(blocksize,gridsize, devicePointer, f);
blocksize=256;
gridsize=4096;
openDotKernelAndTime(blocksize,gridsize, devicePointer, f);
blocksize=512;
gridsize=2048;
openDotKernelAndTime(blocksize,gridsize, devicePointer, f);
blocksize=1024;
gridsize=1024;
openDotKernelAndTime(blocksize,gridsize, devicePointer, f);
f << "ErrorCode " <<cudaMemcpy(hostPointer, devicePointer, sizeInBytes, cudaMemcpyDeviceToHost)<<std::endl;
f << "ErrorCode " <<cudaFree(devicePointer)<<std::endl;
f << "ErrorCode " <<cudaFreeHost(hostPointer)<<std::endl;
return 0;
} | code for sm_80
Function : _Z3dotP8vectProd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 1.6689300537109375e-06 ; /* 0x0000001cff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0060*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R4, [R2.64+0x4] ; /* 0x0000040402047981 */
/* 0x000ea8000c1e1900 */
/*0080*/ LDG.E R7, [R2.64+0x10] ; /* 0x0000100402077981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ee8000c1e1900 */
/*00a0*/ LDG.E R5, [R2.64+0xc] ; /* 0x00000c0402057981 */
/* 0x000ee8000c1e1900 */
/*00b0*/ LDG.E R9, [R2.64+0x8] ; /* 0x0000080402097981 */
/* 0x000f28000c1e1900 */
/*00c0*/ LDG.E R6, [R2.64+0x14] ; /* 0x0000140402067981 */
/* 0x000f22000c1e1900 */
/*00d0*/ FMUL R4, R4, R7 ; /* 0x0000000704047220 */
/* 0x004fc80000400000 */
/*00e0*/ FFMA R0, R0, R5, R4 ; /* 0x0000000500007223 */
/* 0x008fc80000000004 */
/*00f0*/ FFMA R9, R9, R6, R0 ; /* 0x0000000609097223 */
/* 0x010fca0000000000 */
/*0100*/ STG.E [R2.64+0x18], R9 ; /* 0x0000180902007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <iostream>
#include <fstream>
#include <math.h>
#include <stdlib.h>
#include <time.h>
using namespace std;
float randomNumber(int max)
{
return (rand() % (max + 1 ));
}
struct vect
{
float x;
float y;
float z;
};
struct vectProd
{
vect v1;
vect v2;
float dot;
};
__global__ void dot(vectProd* pointer)
{
int threadId = threadIdx.x + blockIdx.x * blockDim.x;
pointer[threadId].dot =
pointer[threadId].v1.x*pointer[threadId].v2.x
+pointer[threadId].v1.y*pointer[threadId].v2.y
+pointer[threadId].v1.z*pointer[threadId].v2.z;
}
void openDotKernelAndTime(int blocksize, int gridsize, vectProd* devicePointer, std::ofstream &f )
{
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
dim3 dimBlock1(blocksize);
dim3 dimGrid1(gridsize);
cudaEventRecord(start, 0);
dot<<<dimGrid1, dimBlock1>>>(devicePointer);
f << "ErrorCode " <<cudaThreadSynchronize()<<std::endl;
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
f << "Blöcke: "<< gridsize << ", Threads: "<< blocksize << std::endl;
f << ", Timing:" << fixed<< elapsedTime <<std::endl;
}
int main(int argc, char** argv)
{
srand((unsigned) time(NULL));
vectProd* hostPointer;
std::ofstream f("timing.txt");
f << "Timing for different Grid / Block size:" << std::endl << std::endl;
size_t Elements = 1024*1024;
size_t sizeInBytes = Elements * sizeof(*hostPointer);
hostPointer = (vectProd*) malloc(sizeInBytes);
cudaHostAlloc(&hostPointer, sizeInBytes, cudaHostAllocDefault);
memset(hostPointer, 0, Elements);
for ( int l=0; l<Elements; l++ )
{
hostPointer[l].v1.x=randomNumber(10);
hostPointer[l].v1.y=randomNumber(10);
hostPointer[l].v1.z=randomNumber(10);
hostPointer[l].v2.x=randomNumber(10);
hostPointer[l].v2.y=randomNumber(10);
hostPointer[l].v2.z=randomNumber(10);
}
vectProd* devicePointer;
f << "ErrorCode " <<cudaMalloc(&devicePointer, sizeInBytes)<< std::endl;
f << "ErrorCode " <<cudaMemcpy(devicePointer, hostPointer, sizeInBytes, cudaMemcpyHostToDevice) <<std::endl;
f << "ErrorCode "<< cudaThreadSynchronize() << std::endl;
int blocksize;
int gridsize;
//Maximum sizes of each dimension of a block: 1024 x 1024 x 64
//Maximum sizes of each dimension of a grid: 65535 x 65535 x 1
blocksize=32;
gridsize=32768;
openDotKernelAndTime(blocksize,gridsize, devicePointer, f);
blocksize=64;
gridsize=16384;
openDotKernelAndTime(blocksize,gridsize, devicePointer, f);
blocksize=128;
gridsize=8192;
openDotKernelAndTime(blocksize,gridsize, devicePointer, f);
blocksize=256;
gridsize=4096;
openDotKernelAndTime(blocksize,gridsize, devicePointer, f);
blocksize=512;
gridsize=2048;
openDotKernelAndTime(blocksize,gridsize, devicePointer, f);
blocksize=1024;
gridsize=1024;
openDotKernelAndTime(blocksize,gridsize, devicePointer, f);
f << "ErrorCode " <<cudaMemcpy(hostPointer, devicePointer, sizeInBytes, cudaMemcpyDeviceToHost)<<std::endl;
f << "ErrorCode " <<cudaFree(devicePointer)<<std::endl;
f << "ErrorCode " <<cudaFreeHost(hostPointer)<<std::endl;
return 0;
} | .file "tmpxft_0004d387_00000000-6_dotRandVect.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3805:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3805:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12randomNumberi
.type _Z12randomNumberi, @function
_Z12randomNumberi:
.LFB3800:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %ebx
call rand@PLT
leal 1(%rbx), %edi
cltd
idivl %edi
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3800:
.size _Z12randomNumberi, .-_Z12randomNumberi
.globl _Z30__device_stub__Z3dotP8vectProdP8vectProd
.type _Z30__device_stub__Z3dotP8vectProdP8vectProd, @function
_Z30__device_stub__Z3dotP8vectProdP8vectProd:
.LFB3827:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3dotP8vectProd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3827:
.size _Z30__device_stub__Z3dotP8vectProdP8vectProd, .-_Z30__device_stub__Z3dotP8vectProdP8vectProd
.globl _Z3dotP8vectProd
.type _Z3dotP8vectProd, @function
_Z3dotP8vectProd:
.LFB3828:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z3dotP8vectProdP8vectProd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3828:
.size _Z3dotP8vectProd, .-_Z3dotP8vectProd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "ErrorCode "
.LC1:
.string "Bl\303\266cke: "
.LC2:
.string ", Threads: "
.LC3:
.string ", Timing:"
.text
.globl _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE
.type _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE, @function
_Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE:
.LFB3801:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movl %edi, %r12d
movl %esi, %r13d
movq %rdx, %rbp
movq %rcx, %rbx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl %r12d, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl %r13d, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L14:
movl $10, %edx
leaq .LC0(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
call cudaThreadSynchronize@PLT
movl %eax, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r14
testq %r14, %r14
je .L30
cmpb $0, 56(%r14)
je .L17
movzbl 67(%r14), %esi
.L18:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movl $9, %edx
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r13d, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $11, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r12d, %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L31
cmpb $0, 56(%r12)
je .L21
movzbl 67(%r12), %esi
.L22:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $9, %edx
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq %rbx, %rdx
addq -24(%rax), %rdx
movl 24(%rdx), %eax
andl $-261, %eax
orl $4, %eax
movl %eax, 24(%rdx)
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L32
cmpb $0, 56(%rbp)
je .L25
movzbl 67(%rbp), %esi
.L26:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movq %rbp, %rdi
call _Z30__device_stub__Z3dotP8vectProdP8vectProd
jmp .L14
.L30:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L34
call _ZSt16__throw_bad_castv@PLT
.L34:
call __stack_chk_fail@PLT
.L17:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L18
.L31:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L35
call _ZSt16__throw_bad_castv@PLT
.L35:
call __stack_chk_fail@PLT
.L21:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L22
.L32:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L36
call _ZSt16__throw_bad_castv@PLT
.L36:
call __stack_chk_fail@PLT
.L25:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L26
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3801:
.size _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE, .-_Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE
.section .rodata.str1.1
.LC4:
.string "_Z3dotP8vectProd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3830:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z3dotP8vectProd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3830:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1
.LC5:
.string "timing.txt"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "Timing for different Grid / Block size:"
.text
.globl main
.type main, @function
main:
.LFB3802:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3802
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $552, %rsp
.cfi_def_cfa_offset 576
movq %fs:40, %rax
movq %rax, 536(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
leaq 16(%rsp), %rbx
movl $16, %edx
leaq .LC5(%rip), %rsi
movq %rbx, %rdi
.LEHB0:
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE0:
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
.LEHB1:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $29360128, %edi
call malloc@PLT
movq %rax, (%rsp)
movq %rsp, %rdi
movl $0, %edx
movl $29360128, %esi
call cudaHostAlloc@PLT
movl $1048576, %edx
movl $0, %esi
movq (%rsp), %rdi
call memset@PLT
movl $0, %ebx
.L40:
movq %rbx, %rbp
addq (%rsp), %rbp
movl $10, %edi
call _Z12randomNumberi
movss %xmm0, 0(%rbp)
movq %rbx, %rbp
addq (%rsp), %rbp
movl $10, %edi
call _Z12randomNumberi
movss %xmm0, 4(%rbp)
movq %rbx, %rbp
addq (%rsp), %rbp
movl $10, %edi
call _Z12randomNumberi
movss %xmm0, 8(%rbp)
movq %rbx, %rbp
addq (%rsp), %rbp
movl $10, %edi
call _Z12randomNumberi
movss %xmm0, 12(%rbp)
movq %rbx, %rbp
addq (%rsp), %rbp
movl $10, %edi
call _Z12randomNumberi
movss %xmm0, 16(%rbp)
movq %rbx, %rbp
addq (%rsp), %rbp
movl $10, %edi
call _Z12randomNumberi
movss %xmm0, 20(%rbp)
addq $28, %rbx
cmpq $29360128, %rbx
jne .L40
leaq 16(%rsp), %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $29360128, %esi
call cudaMalloc@PLT
movl %eax, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 16(%rsp), %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movl $1, %ecx
movl $29360128, %edx
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 16(%rsp), %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
call cudaThreadSynchronize@PLT
movl %eax, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl $32768, %esi
movl $32, %edi
call _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE
leaq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl $16384, %esi
movl $64, %edi
call _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE
leaq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl $8192, %esi
movl $128, %edi
call _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE
leaq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl $4096, %esi
movl $256, %edi
call _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE
leaq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl $2048, %esi
movl $512, %edi
call _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE
leaq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl $1024, %esi
movl $1024, %edi
call _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE
leaq 16(%rsp), %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movl $2, %ecx
movl $29360128, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 16(%rsp), %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 16(%rsp), %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movq (%rsp), %rdi
call cudaFreeHost@PLT
movl %eax, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE1:
leaq 16(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 536(%rsp), %rax
subq %fs:40, %rax
jne .L48
movl $0, %eax
addq $552, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 16(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 536(%rsp), %rax
subq %fs:40, %rax
je .L42
call __stack_chk_fail@PLT
.L42:
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3802:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3802:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3802-.LLSDACSB3802
.LLSDACSB3802:
.uleb128 .LEHB0-.LFB3802
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3802
.uleb128 .LEHE1-.LEHB1
.uleb128 .L44-.LFB3802
.uleb128 0
.uleb128 .LEHB2-.LFB3802
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE3802:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <iostream>
#include <fstream>
#include <math.h>
#include <stdlib.h>
#include <time.h>
using namespace std;
float randomNumber(int max)
{
return (rand() % (max + 1 ));
}
struct vect
{
float x;
float y;
float z;
};
struct vectProd
{
vect v1;
vect v2;
float dot;
};
__global__ void dot(vectProd* pointer)
{
int threadId = threadIdx.x + blockIdx.x * blockDim.x;
pointer[threadId].dot =
pointer[threadId].v1.x*pointer[threadId].v2.x
+pointer[threadId].v1.y*pointer[threadId].v2.y
+pointer[threadId].v1.z*pointer[threadId].v2.z;
}
void openDotKernelAndTime(int blocksize, int gridsize, vectProd* devicePointer, std::ofstream &f )
{
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
dim3 dimBlock1(blocksize);
dim3 dimGrid1(gridsize);
cudaEventRecord(start, 0);
dot<<<dimGrid1, dimBlock1>>>(devicePointer);
f << "ErrorCode " <<cudaThreadSynchronize()<<std::endl;
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
f << "Blöcke: "<< gridsize << ", Threads: "<< blocksize << std::endl;
f << ", Timing:" << fixed<< elapsedTime <<std::endl;
}
int main(int argc, char** argv)
{
srand((unsigned) time(NULL));
vectProd* hostPointer;
std::ofstream f("timing.txt");
f << "Timing for different Grid / Block size:" << std::endl << std::endl;
size_t Elements = 1024*1024;
size_t sizeInBytes = Elements * sizeof(*hostPointer);
hostPointer = (vectProd*) malloc(sizeInBytes);
cudaHostAlloc(&hostPointer, sizeInBytes, cudaHostAllocDefault);
memset(hostPointer, 0, Elements);
for ( int l=0; l<Elements; l++ )
{
hostPointer[l].v1.x=randomNumber(10);
hostPointer[l].v1.y=randomNumber(10);
hostPointer[l].v1.z=randomNumber(10);
hostPointer[l].v2.x=randomNumber(10);
hostPointer[l].v2.y=randomNumber(10);
hostPointer[l].v2.z=randomNumber(10);
}
vectProd* devicePointer;
f << "ErrorCode " <<cudaMalloc(&devicePointer, sizeInBytes)<< std::endl;
f << "ErrorCode " <<cudaMemcpy(devicePointer, hostPointer, sizeInBytes, cudaMemcpyHostToDevice) <<std::endl;
f << "ErrorCode "<< cudaThreadSynchronize() << std::endl;
int blocksize;
int gridsize;
//Maximum sizes of each dimension of a block: 1024 x 1024 x 64
//Maximum sizes of each dimension of a grid: 65535 x 65535 x 1
blocksize=32;
gridsize=32768;
openDotKernelAndTime(blocksize,gridsize, devicePointer, f);
blocksize=64;
gridsize=16384;
openDotKernelAndTime(blocksize,gridsize, devicePointer, f);
blocksize=128;
gridsize=8192;
openDotKernelAndTime(blocksize,gridsize, devicePointer, f);
blocksize=256;
gridsize=4096;
openDotKernelAndTime(blocksize,gridsize, devicePointer, f);
blocksize=512;
gridsize=2048;
openDotKernelAndTime(blocksize,gridsize, devicePointer, f);
blocksize=1024;
gridsize=1024;
openDotKernelAndTime(blocksize,gridsize, devicePointer, f);
f << "ErrorCode " <<cudaMemcpy(hostPointer, devicePointer, sizeInBytes, cudaMemcpyDeviceToHost)<<std::endl;
f << "ErrorCode " <<cudaFree(devicePointer)<<std::endl;
f << "ErrorCode " <<cudaFreeHost(hostPointer)<<std::endl;
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <fstream>
#include <math.h>
#include <stdlib.h>
#include <time.h>
using namespace std;
float randomNumber(int max)
{
return (rand() % (max + 1 ));
}
struct vect
{
float x;
float y;
float z;
};
struct vectProd
{
vect v1;
vect v2;
float dot;
};
__global__ void dot(vectProd* pointer)
{
int threadId = threadIdx.x + blockIdx.x * blockDim.x;
pointer[threadId].dot =
pointer[threadId].v1.x*pointer[threadId].v2.x
+pointer[threadId].v1.y*pointer[threadId].v2.y
+pointer[threadId].v1.z*pointer[threadId].v2.z;
}
void openDotKernelAndTime(int blocksize, int gridsize, vectProd* devicePointer, std::ofstream &f )
{
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
dim3 dimBlock1(blocksize);
dim3 dimGrid1(gridsize);
hipEventRecord(start, 0);
dot<<<dimGrid1, dimBlock1>>>(devicePointer);
f << "ErrorCode " <<hipDeviceSynchronize()<<std::endl;
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
f << "Blöcke: "<< gridsize << ", Threads: "<< blocksize << std::endl;
f << ", Timing:" << fixed<< elapsedTime <<std::endl;
}
int main(int argc, char** argv)
{
srand((unsigned) time(NULL));
vectProd* hostPointer;
std::ofstream f("timing.txt");
f << "Timing for different Grid / Block size:" << std::endl << std::endl;
size_t Elements = 1024*1024;
size_t sizeInBytes = Elements * sizeof(*hostPointer);
hostPointer = (vectProd*) malloc(sizeInBytes);
hipHostAlloc(&hostPointer, sizeInBytes, hipHostMallocDefault);
memset(hostPointer, 0, Elements);
for ( int l=0; l<Elements; l++ )
{
hostPointer[l].v1.x=randomNumber(10);
hostPointer[l].v1.y=randomNumber(10);
hostPointer[l].v1.z=randomNumber(10);
hostPointer[l].v2.x=randomNumber(10);
hostPointer[l].v2.y=randomNumber(10);
hostPointer[l].v2.z=randomNumber(10);
}
vectProd* devicePointer;
f << "ErrorCode " <<hipMalloc(&devicePointer, sizeInBytes)<< std::endl;
f << "ErrorCode " <<hipMemcpy(devicePointer, hostPointer, sizeInBytes, hipMemcpyHostToDevice) <<std::endl;
f << "ErrorCode "<< hipDeviceSynchronize() << std::endl;
int blocksize;
int gridsize;
//Maximum sizes of each dimension of a block: 1024 x 1024 x 64
//Maximum sizes of each dimension of a grid: 65535 x 65535 x 1
blocksize=32;
gridsize=32768;
openDotKernelAndTime(blocksize,gridsize, devicePointer, f);
blocksize=64;
gridsize=16384;
openDotKernelAndTime(blocksize,gridsize, devicePointer, f);
blocksize=128;
gridsize=8192;
openDotKernelAndTime(blocksize,gridsize, devicePointer, f);
blocksize=256;
gridsize=4096;
openDotKernelAndTime(blocksize,gridsize, devicePointer, f);
blocksize=512;
gridsize=2048;
openDotKernelAndTime(blocksize,gridsize, devicePointer, f);
blocksize=1024;
gridsize=1024;
openDotKernelAndTime(blocksize,gridsize, devicePointer, f);
f << "ErrorCode " <<hipMemcpy(hostPointer, devicePointer, sizeInBytes, hipMemcpyDeviceToHost)<<std::endl;
f << "ErrorCode " <<hipFree(devicePointer)<<std::endl;
f << "ErrorCode " <<hipHostFree(hostPointer)<<std::endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <fstream>
#include <math.h>
#include <stdlib.h>
#include <time.h>
using namespace std;
float randomNumber(int max)
{
return (rand() % (max + 1 ));
}
struct vect
{
float x;
float y;
float z;
};
struct vectProd
{
vect v1;
vect v2;
float dot;
};
__global__ void dot(vectProd* pointer)
{
int threadId = threadIdx.x + blockIdx.x * blockDim.x;
pointer[threadId].dot =
pointer[threadId].v1.x*pointer[threadId].v2.x
+pointer[threadId].v1.y*pointer[threadId].v2.y
+pointer[threadId].v1.z*pointer[threadId].v2.z;
}
void openDotKernelAndTime(int blocksize, int gridsize, vectProd* devicePointer, std::ofstream &f )
{
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
dim3 dimBlock1(blocksize);
dim3 dimGrid1(gridsize);
hipEventRecord(start, 0);
dot<<<dimGrid1, dimBlock1>>>(devicePointer);
f << "ErrorCode " <<hipDeviceSynchronize()<<std::endl;
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
f << "Blöcke: "<< gridsize << ", Threads: "<< blocksize << std::endl;
f << ", Timing:" << fixed<< elapsedTime <<std::endl;
}
int main(int argc, char** argv)
{
srand((unsigned) time(NULL));
vectProd* hostPointer;
std::ofstream f("timing.txt");
f << "Timing for different Grid / Block size:" << std::endl << std::endl;
size_t Elements = 1024*1024;
size_t sizeInBytes = Elements * sizeof(*hostPointer);
hostPointer = (vectProd*) malloc(sizeInBytes);
hipHostAlloc(&hostPointer, sizeInBytes, hipHostMallocDefault);
memset(hostPointer, 0, Elements);
for ( int l=0; l<Elements; l++ )
{
hostPointer[l].v1.x=randomNumber(10);
hostPointer[l].v1.y=randomNumber(10);
hostPointer[l].v1.z=randomNumber(10);
hostPointer[l].v2.x=randomNumber(10);
hostPointer[l].v2.y=randomNumber(10);
hostPointer[l].v2.z=randomNumber(10);
}
vectProd* devicePointer;
f << "ErrorCode " <<hipMalloc(&devicePointer, sizeInBytes)<< std::endl;
f << "ErrorCode " <<hipMemcpy(devicePointer, hostPointer, sizeInBytes, hipMemcpyHostToDevice) <<std::endl;
f << "ErrorCode "<< hipDeviceSynchronize() << std::endl;
int blocksize;
int gridsize;
//Maximum sizes of each dimension of a block: 1024 x 1024 x 64
//Maximum sizes of each dimension of a grid: 65535 x 65535 x 1
blocksize=32;
gridsize=32768;
openDotKernelAndTime(blocksize,gridsize, devicePointer, f);
blocksize=64;
gridsize=16384;
openDotKernelAndTime(blocksize,gridsize, devicePointer, f);
blocksize=128;
gridsize=8192;
openDotKernelAndTime(blocksize,gridsize, devicePointer, f);
blocksize=256;
gridsize=4096;
openDotKernelAndTime(blocksize,gridsize, devicePointer, f);
blocksize=512;
gridsize=2048;
openDotKernelAndTime(blocksize,gridsize, devicePointer, f);
blocksize=1024;
gridsize=1024;
openDotKernelAndTime(blocksize,gridsize, devicePointer, f);
f << "ErrorCode " <<hipMemcpy(hostPointer, devicePointer, sizeInBytes, hipMemcpyDeviceToHost)<<std::endl;
f << "ErrorCode " <<hipFree(devicePointer)<<std::endl;
f << "ErrorCode " <<hipHostFree(hostPointer)<<std::endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3dotP8vectProd
.globl _Z3dotP8vectProd
.p2align 8
.type _Z3dotP8vectProd,@function
_Z3dotP8vectProd:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mad_i64_i32 v[4:5], null, v1, 28, s[0:1]
s_clause 0x1
global_load_b128 v[0:3], v[4:5], off
global_load_b64 v[6:7], v[4:5], off offset:16
s_waitcnt vmcnt(0)
v_mul_f32_e32 v1, v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v1, v0, v3
v_fmac_f32_e32 v1, v2, v7
global_store_b32 v[4:5], v1, off offset:24
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3dotP8vectProd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3dotP8vectProd, .Lfunc_end0-_Z3dotP8vectProd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3dotP8vectProd
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3dotP8vectProd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <fstream>
#include <math.h>
#include <stdlib.h>
#include <time.h>
using namespace std;
float randomNumber(int max)
{
return (rand() % (max + 1 ));
}
struct vect
{
float x;
float y;
float z;
};
struct vectProd
{
vect v1;
vect v2;
float dot;
};
__global__ void dot(vectProd* pointer)
{
int threadId = threadIdx.x + blockIdx.x * blockDim.x;
pointer[threadId].dot =
pointer[threadId].v1.x*pointer[threadId].v2.x
+pointer[threadId].v1.y*pointer[threadId].v2.y
+pointer[threadId].v1.z*pointer[threadId].v2.z;
}
void openDotKernelAndTime(int blocksize, int gridsize, vectProd* devicePointer, std::ofstream &f )
{
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
dim3 dimBlock1(blocksize);
dim3 dimGrid1(gridsize);
hipEventRecord(start, 0);
dot<<<dimGrid1, dimBlock1>>>(devicePointer);
f << "ErrorCode " <<hipDeviceSynchronize()<<std::endl;
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float elapsedTime;
hipEventElapsedTime(&elapsedTime, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
f << "Blöcke: "<< gridsize << ", Threads: "<< blocksize << std::endl;
f << ", Timing:" << fixed<< elapsedTime <<std::endl;
}
int main(int argc, char** argv)
{
srand((unsigned) time(NULL));
vectProd* hostPointer;
std::ofstream f("timing.txt");
f << "Timing for different Grid / Block size:" << std::endl << std::endl;
size_t Elements = 1024*1024;
size_t sizeInBytes = Elements * sizeof(*hostPointer);
hostPointer = (vectProd*) malloc(sizeInBytes);
hipHostAlloc(&hostPointer, sizeInBytes, hipHostMallocDefault);
memset(hostPointer, 0, Elements);
for ( int l=0; l<Elements; l++ )
{
hostPointer[l].v1.x=randomNumber(10);
hostPointer[l].v1.y=randomNumber(10);
hostPointer[l].v1.z=randomNumber(10);
hostPointer[l].v2.x=randomNumber(10);
hostPointer[l].v2.y=randomNumber(10);
hostPointer[l].v2.z=randomNumber(10);
}
vectProd* devicePointer;
f << "ErrorCode " <<hipMalloc(&devicePointer, sizeInBytes)<< std::endl;
f << "ErrorCode " <<hipMemcpy(devicePointer, hostPointer, sizeInBytes, hipMemcpyHostToDevice) <<std::endl;
f << "ErrorCode "<< hipDeviceSynchronize() << std::endl;
int blocksize;
int gridsize;
//Maximum sizes of each dimension of a block: 1024 x 1024 x 64
//Maximum sizes of each dimension of a grid: 65535 x 65535 x 1
blocksize=32;
gridsize=32768;
openDotKernelAndTime(blocksize,gridsize, devicePointer, f);
blocksize=64;
gridsize=16384;
openDotKernelAndTime(blocksize,gridsize, devicePointer, f);
blocksize=128;
gridsize=8192;
openDotKernelAndTime(blocksize,gridsize, devicePointer, f);
blocksize=256;
gridsize=4096;
openDotKernelAndTime(blocksize,gridsize, devicePointer, f);
blocksize=512;
gridsize=2048;
openDotKernelAndTime(blocksize,gridsize, devicePointer, f);
blocksize=1024;
gridsize=1024;
openDotKernelAndTime(blocksize,gridsize, devicePointer, f);
f << "ErrorCode " <<hipMemcpy(hostPointer, devicePointer, sizeInBytes, hipMemcpyDeviceToHost)<<std::endl;
f << "ErrorCode " <<hipFree(devicePointer)<<std::endl;
f << "ErrorCode " <<hipHostFree(hostPointer)<<std::endl;
return 0;
} | .text
.file "dotRandVect.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z12randomNumberi # -- Begin function _Z12randomNumberi
.p2align 4, 0x90
.type _Z12randomNumberi,@function
_Z12randomNumberi: # @_Z12randomNumberi
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %edi, %ebx
callq rand
incl %ebx
cltd
idivl %ebx
cvtsi2ss %edx, %xmm0
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z12randomNumberi, .Lfunc_end0-_Z12randomNumberi
.cfi_endproc
# -- End function
.globl _Z18__device_stub__dotP8vectProd # -- Begin function _Z18__device_stub__dotP8vectProd
.p2align 4, 0x90
.type _Z18__device_stub__dotP8vectProd,@function
_Z18__device_stub__dotP8vectProd: # @_Z18__device_stub__dotP8vectProd
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3dotP8vectProd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z18__device_stub__dotP8vectProd, .Lfunc_end1-_Z18__device_stub__dotP8vectProd
.cfi_endproc
# -- End function
.globl _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE # -- Begin function _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE
.p2align 4, 0x90
.type _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE,@function
_Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE: # @_Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $88, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rcx, %rbx
movq %rdx, %r15
movl %esi, %r14d
movl %edi, %ebp
leaq 8(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movl %ebp, %r12d
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r12
movl %r14d, %r13d
orq %rax, %r13
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq %r15, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 32(%rsp)
leaq 16(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z3dotP8vectProd, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movl $.L.str, %esi
movl $10, %edx
movq %rbx, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
callq hipDeviceSynchronize
movq %rbx, %rdi
movl %eax, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB2_15
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB2_5
# %bb.4:
movzbl 67(%r15), %ecx
jmp .LBB2_6
.LBB2_5:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB2_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rsi
movq (%rsp), %rdx
leaq 16(%rsp), %rdi
callq hipEventElapsedTime
movq 8(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
callq hipEventDestroy
movl $.L.str.1, %esi
movl $9, %edx
movq %rbx, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.2, %esi
movl $11, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rdi
movl %ebp, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_15
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i14
cmpb $0, 56(%r14)
je .LBB2_9
# %bb.8:
movzbl 67(%r14), %ecx
jmp .LBB2_10
.LBB2_9:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB2_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit17
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $.L.str.3, %esi
movl $9, %edx
movq %rbx, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movl $-261, %ecx # imm = 0xFEFB
andl 24(%rbx,%rax), %ecx
orl $4, %ecx
movl %ecx, 24(%rbx,%rax)
movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_15
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i19
cmpb $0, 56(%rbx)
je .LBB2_13
# %bb.12:
movzbl 67(%rbx), %ecx
jmp .LBB2_14
.LBB2_13:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit22
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
addq $88, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_15:
.cfi_def_cfa_offset 144
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE, .Lfunc_end2-_Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $536, %rsp # imm = 0x218
.cfi_def_cfa_offset 560
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
leaq 24(%rsp), %rbx
movl $.L.str.4, %esi
movq %rbx, %rdi
movl $16, %edx
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
.Ltmp0:
movl $.L.str.5, %esi
movl $39, %edx
movq %rbx, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp1:
# %bb.1: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq 24(%rsp), %rax
movq -24(%rax), %rax
movq 264(%rsp,%rax), %rbx
testq %rbx, %rbx
je .LBB3_9
# %bb.2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB3_4
# %bb.3:
movzbl 67(%rbx), %eax
jmp .LBB3_6
.LBB3_4:
.Ltmp2:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp3:
# %bb.5: # %.noexc51
movq (%rbx), %rax
.Ltmp4:
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp5:
.LBB3_6: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp6:
movsbl %al, %esi
leaq 24(%rsp), %rdi
callq _ZNSo3putEc
.Ltmp7:
# %bb.7: # %.noexc53
.Ltmp8:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp9:
# %bb.8: # %_ZNSolsEPFRSoS_E.exit
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB3_9
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i56
cmpb $0, 56(%r14)
je .LBB3_13
# %bb.12:
movzbl 67(%r14), %eax
jmp .LBB3_15
.LBB3_13:
.Ltmp10:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp11:
# %bb.14: # %.noexc61
movq (%r14), %rax
.Ltmp12:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp13:
.LBB3_15: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i58
.Ltmp14:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp15:
# %bb.16: # %.noexc63
.Ltmp16:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp17:
# %bb.17: # %_ZNSolsEPFRSoS_E.exit38
movl $29360128, %edi # imm = 0x1C00000
callq malloc
movq %rax, 8(%rsp)
.Ltmp18:
leaq 8(%rsp), %rdi
movl $29360128, %esi # imm = 0x1C00000
xorl %edx, %edx
callq hipHostAlloc
.Ltmp19:
# %bb.18: # %_ZL12hipHostAllocI8vectProdE10hipError_tPPT_mj.exit
movq 8(%rsp), %rdi
xorl %ebx, %ebx
movl $1048576, %edx # imm = 0x100000
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB3_19: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $780903145, %rax, %rcx # imm = 0x2E8BA2E9
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %edx
leal (%rcx,%rdx,2), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movq 8(%rsp), %rax
movss %xmm0, (%rax,%rbx)
callq rand
cltq
imulq $780903145, %rax, %rcx # imm = 0x2E8BA2E9
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %edx
leal (%rcx,%rdx,2), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movq 8(%rsp), %rax
movss %xmm0, 4(%rax,%rbx)
callq rand
cltq
imulq $780903145, %rax, %rcx # imm = 0x2E8BA2E9
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %edx
leal (%rcx,%rdx,2), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movq 8(%rsp), %rax
movss %xmm0, 8(%rax,%rbx)
callq rand
cltq
imulq $780903145, %rax, %rcx # imm = 0x2E8BA2E9
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %edx
leal (%rcx,%rdx,2), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movq 8(%rsp), %rax
movss %xmm0, 12(%rax,%rbx)
callq rand
cltq
imulq $780903145, %rax, %rcx # imm = 0x2E8BA2E9
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %edx
leal (%rcx,%rdx,2), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movq 8(%rsp), %rax
movss %xmm0, 16(%rax,%rbx)
callq rand
cltq
imulq $780903145, %rax, %rcx # imm = 0x2E8BA2E9
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %edx
leal (%rcx,%rdx,2), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movq 8(%rsp), %rax
movss %xmm0, 20(%rax,%rbx)
addq $28, %rbx
cmpq $29360128, %rbx # imm = 0x1C00000
jne .LBB3_19
# %bb.20:
.Ltmp21:
leaq 24(%rsp), %rdi
movl $.L.str, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp22:
# %bb.21: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit39
.Ltmp23:
leaq 16(%rsp), %rdi
movl $29360128, %esi # imm = 0x1C00000
callq hipMalloc
.Ltmp24:
# %bb.22: # %_ZL9hipMallocI8vectProdE10hipError_tPPT_m.exit
.Ltmp25:
leaq 24(%rsp), %rdi
movl %eax, %esi
callq _ZNSolsEi
.Ltmp26:
# %bb.23:
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB3_46
# %bb.24: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i67
cmpb $0, 56(%r14)
je .LBB3_28
# %bb.25:
movzbl 67(%r14), %eax
jmp .LBB3_30
.LBB3_28:
.Ltmp27:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp28:
# %bb.29: # %.noexc72
movq (%r14), %rax
.Ltmp29:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp30:
.LBB3_30: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i69
.Ltmp31:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp32:
# %bb.31: # %.noexc74
.Ltmp33:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp34:
# %bb.32: # %_ZNSolsEPFRSoS_E.exit40
.Ltmp35:
leaq 24(%rsp), %rdi
movl $.L.str, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp36:
# %bb.33: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit41
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
.Ltmp37:
movl $29360128, %edx # imm = 0x1C00000
movl $1, %ecx
callq hipMemcpy
.Ltmp38:
# %bb.34:
.Ltmp39:
leaq 24(%rsp), %rdi
movl %eax, %esi
callq _ZNSolsEi
.Ltmp40:
# %bb.35:
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB3_46
# %bb.36: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i78
cmpb $0, 56(%r14)
je .LBB3_38
# %bb.37:
movzbl 67(%r14), %eax
jmp .LBB3_40
.LBB3_38:
.Ltmp41:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp42:
# %bb.39: # %.noexc83
movq (%r14), %rax
.Ltmp43:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp44:
.LBB3_40: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i80
.Ltmp45:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp46:
# %bb.41: # %.noexc85
.Ltmp47:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp48:
# %bb.42: # %_ZNSolsEPFRSoS_E.exit42
.Ltmp49:
leaq 24(%rsp), %rdi
movl $.L.str, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp50:
# %bb.43: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit43
.Ltmp51:
callq hipDeviceSynchronize
.Ltmp52:
# %bb.44:
.Ltmp53:
leaq 24(%rsp), %rdi
movl %eax, %esi
callq _ZNSolsEi
.Ltmp54:
# %bb.45:
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB3_46
# %bb.48: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i89
cmpb $0, 56(%r14)
je .LBB3_50
# %bb.49:
movzbl 67(%r14), %eax
jmp .LBB3_52
.LBB3_50:
.Ltmp55:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp56:
# %bb.51: # %.noexc94
movq (%r14), %rax
.Ltmp57:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp58:
.LBB3_52: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i91
.Ltmp59:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp60:
# %bb.53: # %.noexc96
.Ltmp61:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp62:
# %bb.54: # %_ZNSolsEPFRSoS_E.exit44
movq 16(%rsp), %rdx
.Ltmp63:
leaq 24(%rsp), %rcx
movl $32, %edi
movl $32768, %esi # imm = 0x8000
callq _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE
.Ltmp64:
# %bb.55:
movq 16(%rsp), %rdx
.Ltmp65:
leaq 24(%rsp), %rcx
movl $64, %edi
movl $16384, %esi # imm = 0x4000
callq _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE
.Ltmp66:
# %bb.56:
movq 16(%rsp), %rdx
.Ltmp67:
leaq 24(%rsp), %rcx
movl $128, %edi
movl $8192, %esi # imm = 0x2000
callq _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE
.Ltmp68:
# %bb.57:
movq 16(%rsp), %rdx
.Ltmp69:
leaq 24(%rsp), %rcx
movl $256, %edi # imm = 0x100
movl $4096, %esi # imm = 0x1000
callq _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE
.Ltmp70:
# %bb.58:
movq 16(%rsp), %rdx
.Ltmp71:
leaq 24(%rsp), %rcx
movl $512, %edi # imm = 0x200
movl $2048, %esi # imm = 0x800
callq _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE
.Ltmp72:
# %bb.59:
movq 16(%rsp), %rdx
.Ltmp73:
leaq 24(%rsp), %rcx
movl $1024, %edi # imm = 0x400
movl $1024, %esi # imm = 0x400
callq _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE
.Ltmp74:
# %bb.60:
.Ltmp75:
leaq 24(%rsp), %rdi
movl $.L.str, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp76:
# %bb.61: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit45
movq 8(%rsp), %rdi
movq 16(%rsp), %rsi
.Ltmp77:
movl $29360128, %edx # imm = 0x1C00000
movl $2, %ecx
callq hipMemcpy
.Ltmp78:
# %bb.62:
.Ltmp79:
leaq 24(%rsp), %rdi
movl %eax, %esi
callq _ZNSolsEi
.Ltmp80:
# %bb.63:
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB3_84
# %bb.64: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i100
cmpb $0, 56(%r14)
je .LBB3_66
# %bb.65:
movzbl 67(%r14), %eax
jmp .LBB3_68
.LBB3_66:
.Ltmp81:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp82:
# %bb.67: # %.noexc105
movq (%r14), %rax
.Ltmp83:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp84:
.LBB3_68: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i102
.Ltmp85:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp86:
# %bb.69: # %.noexc107
.Ltmp87:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp88:
# %bb.70: # %_ZNSolsEPFRSoS_E.exit46
.Ltmp89:
leaq 24(%rsp), %rdi
movl $.L.str, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp90:
# %bb.71: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit47
movq 16(%rsp), %rdi
.Ltmp91:
callq hipFree
.Ltmp92:
# %bb.72:
.Ltmp93:
leaq 24(%rsp), %rdi
movl %eax, %esi
callq _ZNSolsEi
.Ltmp94:
# %bb.73:
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB3_84
# %bb.74: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i111
cmpb $0, 56(%r14)
je .LBB3_76
# %bb.75:
movzbl 67(%r14), %eax
jmp .LBB3_78
.LBB3_76:
.Ltmp95:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp96:
# %bb.77: # %.noexc116
movq (%r14), %rax
.Ltmp97:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp98:
.LBB3_78: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i113
.Ltmp99:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp100:
# %bb.79: # %.noexc118
.Ltmp101:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp102:
# %bb.80: # %_ZNSolsEPFRSoS_E.exit48
.Ltmp103:
leaq 24(%rsp), %rdi
movl $.L.str, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp104:
# %bb.81: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit49
movq 8(%rsp), %rdi
.Ltmp105:
callq hipHostFree
.Ltmp106:
# %bb.82:
.Ltmp107:
leaq 24(%rsp), %rdi
movl %eax, %esi
callq _ZNSolsEi
.Ltmp108:
# %bb.83:
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB3_84
# %bb.86: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i122
cmpb $0, 56(%r14)
je .LBB3_88
# %bb.87:
movzbl 67(%r14), %eax
jmp .LBB3_90
.LBB3_88:
.Ltmp109:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp110:
# %bb.89: # %.noexc127
movq (%r14), %rax
.Ltmp111:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp112:
.LBB3_90: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i124
.Ltmp113:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp114:
# %bb.91: # %.noexc129
.Ltmp115:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp116:
# %bb.92: # %_ZNSolsEPFRSoS_E.exit50
leaq 24(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
xorl %eax, %eax
addq $536, %rsp # imm = 0x218
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB3_46: # %.invoke134
.cfi_def_cfa_offset 560
.Ltmp120:
callq _ZSt16__throw_bad_castv
.Ltmp121:
# %bb.47: # %.cont135
.LBB3_84: # %.invoke136
.Ltmp117:
callq _ZSt16__throw_bad_castv
.Ltmp118:
# %bb.85: # %.cont137
.LBB3_9: # %.invoke
.Ltmp123:
callq _ZSt16__throw_bad_castv
.Ltmp124:
# %bb.10: # %.cont
.LBB3_27:
.Ltmp20:
jmp .LBB3_95
.LBB3_26:
.Ltmp125:
jmp .LBB3_95
.LBB3_93:
.Ltmp122:
jmp .LBB3_95
.LBB3_94:
.Ltmp119:
.LBB3_95:
movq %rax, %rbx
leaq 24(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table3:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp17-.Ltmp0 # Call between .Ltmp0 and .Ltmp17
.uleb128 .Ltmp125-.Lfunc_begin0 # jumps to .Ltmp125
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp19-.Ltmp18 # Call between .Ltmp18 and .Ltmp19
.uleb128 .Ltmp20-.Lfunc_begin0 # jumps to .Ltmp20
.byte 0 # On action: cleanup
.uleb128 .Ltmp19-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp21-.Ltmp19 # Call between .Ltmp19 and .Ltmp21
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp21-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp62-.Ltmp21 # Call between .Ltmp21 and .Ltmp62
.uleb128 .Ltmp122-.Lfunc_begin0 # jumps to .Ltmp122
.byte 0 # On action: cleanup
.uleb128 .Ltmp63-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp116-.Ltmp63 # Call between .Ltmp63 and .Ltmp116
.uleb128 .Ltmp119-.Lfunc_begin0 # jumps to .Ltmp119
.byte 0 # On action: cleanup
.uleb128 .Ltmp120-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp121-.Ltmp120 # Call between .Ltmp120 and .Ltmp121
.uleb128 .Ltmp122-.Lfunc_begin0 # jumps to .Ltmp122
.byte 0 # On action: cleanup
.uleb128 .Ltmp117-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp118-.Ltmp117 # Call between .Ltmp117 and .Ltmp118
.uleb128 .Ltmp119-.Lfunc_begin0 # jumps to .Ltmp119
.byte 0 # On action: cleanup
.uleb128 .Ltmp123-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp124-.Ltmp123 # Call between .Ltmp123 and .Ltmp124
.uleb128 .Ltmp125-.Lfunc_begin0 # jumps to .Ltmp125
.byte 0 # On action: cleanup
.uleb128 .Ltmp124-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Lfunc_end3-.Ltmp124 # Call between .Ltmp124 and .Lfunc_end3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3dotP8vectProd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3dotP8vectProd,@object # @_Z3dotP8vectProd
.section .rodata,"a",@progbits
.globl _Z3dotP8vectProd
.p2align 3, 0x0
_Z3dotP8vectProd:
.quad _Z18__device_stub__dotP8vectProd
.size _Z3dotP8vectProd, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "ErrorCode "
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Bl\303\266cke: "
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz ", Threads: "
.size .L.str.2, 12
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz ", Timing:"
.size .L.str.3, 10
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "timing.txt"
.size .L.str.4, 11
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Timing for different Grid / Block size:"
.size .L.str.5, 40
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3dotP8vectProd"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__dotP8vectProd
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z3dotP8vectProd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3dotP8vectProd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 1.6689300537109375e-06 ; /* 0x0000001cff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0060*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R4, [R2.64+0x4] ; /* 0x0000040402047981 */
/* 0x000ea8000c1e1900 */
/*0080*/ LDG.E R7, [R2.64+0x10] ; /* 0x0000100402077981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ee8000c1e1900 */
/*00a0*/ LDG.E R5, [R2.64+0xc] ; /* 0x00000c0402057981 */
/* 0x000ee8000c1e1900 */
/*00b0*/ LDG.E R9, [R2.64+0x8] ; /* 0x0000080402097981 */
/* 0x000f28000c1e1900 */
/*00c0*/ LDG.E R6, [R2.64+0x14] ; /* 0x0000140402067981 */
/* 0x000f22000c1e1900 */
/*00d0*/ FMUL R4, R4, R7 ; /* 0x0000000704047220 */
/* 0x004fc80000400000 */
/*00e0*/ FFMA R0, R0, R5, R4 ; /* 0x0000000500007223 */
/* 0x008fc80000000004 */
/*00f0*/ FFMA R9, R9, R6, R0 ; /* 0x0000000609097223 */
/* 0x010fca0000000000 */
/*0100*/ STG.E [R2.64+0x18], R9 ; /* 0x0000180902007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3dotP8vectProd
.globl _Z3dotP8vectProd
.p2align 8
.type _Z3dotP8vectProd,@function
_Z3dotP8vectProd:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mad_i64_i32 v[4:5], null, v1, 28, s[0:1]
s_clause 0x1
global_load_b128 v[0:3], v[4:5], off
global_load_b64 v[6:7], v[4:5], off offset:16
s_waitcnt vmcnt(0)
v_mul_f32_e32 v1, v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v1, v0, v3
v_fmac_f32_e32 v1, v2, v7
global_store_b32 v[4:5], v1, off offset:24
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3dotP8vectProd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3dotP8vectProd, .Lfunc_end0-_Z3dotP8vectProd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3dotP8vectProd
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3dotP8vectProd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004d387_00000000-6_dotRandVect.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3805:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3805:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12randomNumberi
.type _Z12randomNumberi, @function
_Z12randomNumberi:
.LFB3800:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %ebx
call rand@PLT
leal 1(%rbx), %edi
cltd
idivl %edi
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3800:
.size _Z12randomNumberi, .-_Z12randomNumberi
.globl _Z30__device_stub__Z3dotP8vectProdP8vectProd
.type _Z30__device_stub__Z3dotP8vectProdP8vectProd, @function
_Z30__device_stub__Z3dotP8vectProdP8vectProd:
.LFB3827:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3dotP8vectProd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3827:
.size _Z30__device_stub__Z3dotP8vectProdP8vectProd, .-_Z30__device_stub__Z3dotP8vectProdP8vectProd
.globl _Z3dotP8vectProd
.type _Z3dotP8vectProd, @function
_Z3dotP8vectProd:
.LFB3828:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z3dotP8vectProdP8vectProd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3828:
.size _Z3dotP8vectProd, .-_Z3dotP8vectProd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "ErrorCode "
.LC1:
.string "Bl\303\266cke: "
.LC2:
.string ", Threads: "
.LC3:
.string ", Timing:"
.text
.globl _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE
.type _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE, @function
_Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE:
.LFB3801:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movl %edi, %r12d
movl %esi, %r13d
movq %rdx, %rbp
movq %rcx, %rbx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl %r12d, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl %r13d, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L14:
movl $10, %edx
leaq .LC0(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
call cudaThreadSynchronize@PLT
movl %eax, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r14
testq %r14, %r14
je .L30
cmpb $0, 56(%r14)
je .L17
movzbl 67(%r14), %esi
.L18:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movl $9, %edx
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r13d, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movl $11, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r12d, %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L31
cmpb $0, 56(%r12)
je .L21
movzbl 67(%r12), %esi
.L22:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $9, %edx
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq %rbx, %rdx
addq -24(%rax), %rdx
movl 24(%rdx), %eax
andl $-261, %eax
orl $4, %eax
movl %eax, 24(%rdx)
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L32
cmpb $0, 56(%rbp)
je .L25
movzbl 67(%rbp), %esi
.L26:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movq %rbp, %rdi
call _Z30__device_stub__Z3dotP8vectProdP8vectProd
jmp .L14
.L30:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L34
call _ZSt16__throw_bad_castv@PLT
.L34:
call __stack_chk_fail@PLT
.L17:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L18
.L31:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L35
call _ZSt16__throw_bad_castv@PLT
.L35:
call __stack_chk_fail@PLT
.L21:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L22
.L32:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L36
call _ZSt16__throw_bad_castv@PLT
.L36:
call __stack_chk_fail@PLT
.L25:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L26
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3801:
.size _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE, .-_Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE
.section .rodata.str1.1
.LC4:
.string "_Z3dotP8vectProd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3830:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z3dotP8vectProd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3830:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1
.LC5:
.string "timing.txt"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "Timing for different Grid / Block size:"
.text
.globl main
.type main, @function
main:
.LFB3802:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3802
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $552, %rsp
.cfi_def_cfa_offset 576
movq %fs:40, %rax
movq %rax, 536(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
leaq 16(%rsp), %rbx
movl $16, %edx
leaq .LC5(%rip), %rsi
movq %rbx, %rdi
.LEHB0:
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE0:
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
.LEHB1:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $29360128, %edi
call malloc@PLT
movq %rax, (%rsp)
movq %rsp, %rdi
movl $0, %edx
movl $29360128, %esi
call cudaHostAlloc@PLT
movl $1048576, %edx
movl $0, %esi
movq (%rsp), %rdi
call memset@PLT
movl $0, %ebx
.L40:
movq %rbx, %rbp
addq (%rsp), %rbp
movl $10, %edi
call _Z12randomNumberi
movss %xmm0, 0(%rbp)
movq %rbx, %rbp
addq (%rsp), %rbp
movl $10, %edi
call _Z12randomNumberi
movss %xmm0, 4(%rbp)
movq %rbx, %rbp
addq (%rsp), %rbp
movl $10, %edi
call _Z12randomNumberi
movss %xmm0, 8(%rbp)
movq %rbx, %rbp
addq (%rsp), %rbp
movl $10, %edi
call _Z12randomNumberi
movss %xmm0, 12(%rbp)
movq %rbx, %rbp
addq (%rsp), %rbp
movl $10, %edi
call _Z12randomNumberi
movss %xmm0, 16(%rbp)
movq %rbx, %rbp
addq (%rsp), %rbp
movl $10, %edi
call _Z12randomNumberi
movss %xmm0, 20(%rbp)
addq $28, %rbx
cmpq $29360128, %rbx
jne .L40
leaq 16(%rsp), %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $29360128, %esi
call cudaMalloc@PLT
movl %eax, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 16(%rsp), %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movl $1, %ecx
movl $29360128, %edx
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 16(%rsp), %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
call cudaThreadSynchronize@PLT
movl %eax, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl $32768, %esi
movl $32, %edi
call _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE
leaq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl $16384, %esi
movl $64, %edi
call _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE
leaq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl $8192, %esi
movl $128, %edi
call _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE
leaq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl $4096, %esi
movl $256, %edi
call _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE
leaq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl $2048, %esi
movl $512, %edi
call _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE
leaq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl $1024, %esi
movl $1024, %edi
call _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE
leaq 16(%rsp), %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movl $2, %ecx
movl $29360128, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 16(%rsp), %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 16(%rsp), %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movq (%rsp), %rdi
call cudaFreeHost@PLT
movl %eax, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE1:
leaq 16(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 536(%rsp), %rax
subq %fs:40, %rax
jne .L48
movl $0, %eax
addq $552, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 16(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 536(%rsp), %rax
subq %fs:40, %rax
je .L42
call __stack_chk_fail@PLT
.L42:
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3802:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3802:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3802-.LLSDACSB3802
.LLSDACSB3802:
.uleb128 .LEHB0-.LFB3802
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3802
.uleb128 .LEHE1-.LEHB1
.uleb128 .L44-.LFB3802
.uleb128 0
.uleb128 .LEHB2-.LFB3802
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE3802:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "dotRandVect.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z12randomNumberi # -- Begin function _Z12randomNumberi
.p2align 4, 0x90
.type _Z12randomNumberi,@function
_Z12randomNumberi: # @_Z12randomNumberi
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %edi, %ebx
callq rand
incl %ebx
cltd
idivl %ebx
cvtsi2ss %edx, %xmm0
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z12randomNumberi, .Lfunc_end0-_Z12randomNumberi
.cfi_endproc
# -- End function
.globl _Z18__device_stub__dotP8vectProd # -- Begin function _Z18__device_stub__dotP8vectProd
.p2align 4, 0x90
.type _Z18__device_stub__dotP8vectProd,@function
_Z18__device_stub__dotP8vectProd: # @_Z18__device_stub__dotP8vectProd
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3dotP8vectProd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z18__device_stub__dotP8vectProd, .Lfunc_end1-_Z18__device_stub__dotP8vectProd
.cfi_endproc
# -- End function
.globl _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE # -- Begin function _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE
.p2align 4, 0x90
.type _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE,@function
_Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE: # @_Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $88, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rcx, %rbx
movq %rdx, %r15
movl %esi, %r14d
movl %edi, %ebp
leaq 8(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movl %ebp, %r12d
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r12
movl %r14d, %r13d
orq %rax, %r13
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq %r15, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 32(%rsp)
leaq 16(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z3dotP8vectProd, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movl $.L.str, %esi
movl $10, %edx
movq %rbx, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
callq hipDeviceSynchronize
movq %rbx, %rdi
movl %eax, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB2_15
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB2_5
# %bb.4:
movzbl 67(%r15), %ecx
jmp .LBB2_6
.LBB2_5:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB2_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rsi
movq (%rsp), %rdx
leaq 16(%rsp), %rdi
callq hipEventElapsedTime
movq 8(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
callq hipEventDestroy
movl $.L.str.1, %esi
movl $9, %edx
movq %rbx, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %r14
movl $.L.str.2, %esi
movl $11, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r14, %rdi
movl %ebp, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_15
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i14
cmpb $0, 56(%r14)
je .LBB2_9
# %bb.8:
movzbl 67(%r14), %ecx
jmp .LBB2_10
.LBB2_9:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB2_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit17
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $.L.str.3, %esi
movl $9, %edx
movq %rbx, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movl $-261, %ecx # imm = 0xFEFB
andl 24(%rbx,%rax), %ecx
orl $4, %ecx
movl %ecx, 24(%rbx,%rax)
movss 16(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_15
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i19
cmpb $0, 56(%rbx)
je .LBB2_13
# %bb.12:
movzbl 67(%rbx), %ecx
jmp .LBB2_14
.LBB2_13:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit22
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
addq $88, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_15:
.cfi_def_cfa_offset 144
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE, .Lfunc_end2-_Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $536, %rsp # imm = 0x218
.cfi_def_cfa_offset 560
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
leaq 24(%rsp), %rbx
movl $.L.str.4, %esi
movq %rbx, %rdi
movl $16, %edx
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
.Ltmp0:
movl $.L.str.5, %esi
movl $39, %edx
movq %rbx, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp1:
# %bb.1: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq 24(%rsp), %rax
movq -24(%rax), %rax
movq 264(%rsp,%rax), %rbx
testq %rbx, %rbx
je .LBB3_9
# %bb.2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB3_4
# %bb.3:
movzbl 67(%rbx), %eax
jmp .LBB3_6
.LBB3_4:
.Ltmp2:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp3:
# %bb.5: # %.noexc51
movq (%rbx), %rax
.Ltmp4:
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp5:
.LBB3_6: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp6:
movsbl %al, %esi
leaq 24(%rsp), %rdi
callq _ZNSo3putEc
.Ltmp7:
# %bb.7: # %.noexc53
.Ltmp8:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp9:
# %bb.8: # %_ZNSolsEPFRSoS_E.exit
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB3_9
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i56
cmpb $0, 56(%r14)
je .LBB3_13
# %bb.12:
movzbl 67(%r14), %eax
jmp .LBB3_15
.LBB3_13:
.Ltmp10:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp11:
# %bb.14: # %.noexc61
movq (%r14), %rax
.Ltmp12:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp13:
.LBB3_15: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i58
.Ltmp14:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp15:
# %bb.16: # %.noexc63
.Ltmp16:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp17:
# %bb.17: # %_ZNSolsEPFRSoS_E.exit38
movl $29360128, %edi # imm = 0x1C00000
callq malloc
movq %rax, 8(%rsp)
.Ltmp18:
leaq 8(%rsp), %rdi
movl $29360128, %esi # imm = 0x1C00000
xorl %edx, %edx
callq hipHostAlloc
.Ltmp19:
# %bb.18: # %_ZL12hipHostAllocI8vectProdE10hipError_tPPT_mj.exit
movq 8(%rsp), %rdi
xorl %ebx, %ebx
movl $1048576, %edx # imm = 0x100000
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB3_19: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $780903145, %rax, %rcx # imm = 0x2E8BA2E9
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %edx
leal (%rcx,%rdx,2), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movq 8(%rsp), %rax
movss %xmm0, (%rax,%rbx)
callq rand
cltq
imulq $780903145, %rax, %rcx # imm = 0x2E8BA2E9
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %edx
leal (%rcx,%rdx,2), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movq 8(%rsp), %rax
movss %xmm0, 4(%rax,%rbx)
callq rand
cltq
imulq $780903145, %rax, %rcx # imm = 0x2E8BA2E9
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %edx
leal (%rcx,%rdx,2), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movq 8(%rsp), %rax
movss %xmm0, 8(%rax,%rbx)
callq rand
cltq
imulq $780903145, %rax, %rcx # imm = 0x2E8BA2E9
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %edx
leal (%rcx,%rdx,2), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movq 8(%rsp), %rax
movss %xmm0, 12(%rax,%rbx)
callq rand
cltq
imulq $780903145, %rax, %rcx # imm = 0x2E8BA2E9
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %edx
leal (%rcx,%rdx,2), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movq 8(%rsp), %rax
movss %xmm0, 16(%rax,%rbx)
callq rand
cltq
imulq $780903145, %rax, %rcx # imm = 0x2E8BA2E9
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %edx
leal (%rcx,%rdx,2), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movq 8(%rsp), %rax
movss %xmm0, 20(%rax,%rbx)
addq $28, %rbx
cmpq $29360128, %rbx # imm = 0x1C00000
jne .LBB3_19
# %bb.20:
.Ltmp21:
leaq 24(%rsp), %rdi
movl $.L.str, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp22:
# %bb.21: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit39
.Ltmp23:
leaq 16(%rsp), %rdi
movl $29360128, %esi # imm = 0x1C00000
callq hipMalloc
.Ltmp24:
# %bb.22: # %_ZL9hipMallocI8vectProdE10hipError_tPPT_m.exit
.Ltmp25:
leaq 24(%rsp), %rdi
movl %eax, %esi
callq _ZNSolsEi
.Ltmp26:
# %bb.23:
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB3_46
# %bb.24: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i67
cmpb $0, 56(%r14)
je .LBB3_28
# %bb.25:
movzbl 67(%r14), %eax
jmp .LBB3_30
.LBB3_28:
.Ltmp27:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp28:
# %bb.29: # %.noexc72
movq (%r14), %rax
.Ltmp29:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp30:
.LBB3_30: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i69
.Ltmp31:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp32:
# %bb.31: # %.noexc74
.Ltmp33:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp34:
# %bb.32: # %_ZNSolsEPFRSoS_E.exit40
.Ltmp35:
leaq 24(%rsp), %rdi
movl $.L.str, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp36:
# %bb.33: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit41
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
.Ltmp37:
movl $29360128, %edx # imm = 0x1C00000
movl $1, %ecx
callq hipMemcpy
.Ltmp38:
# %bb.34:
.Ltmp39:
leaq 24(%rsp), %rdi
movl %eax, %esi
callq _ZNSolsEi
.Ltmp40:
# %bb.35:
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB3_46
# %bb.36: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i78
cmpb $0, 56(%r14)
je .LBB3_38
# %bb.37:
movzbl 67(%r14), %eax
jmp .LBB3_40
.LBB3_38:
.Ltmp41:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp42:
# %bb.39: # %.noexc83
movq (%r14), %rax
.Ltmp43:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp44:
.LBB3_40: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i80
.Ltmp45:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp46:
# %bb.41: # %.noexc85
.Ltmp47:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp48:
# %bb.42: # %_ZNSolsEPFRSoS_E.exit42
.Ltmp49:
leaq 24(%rsp), %rdi
movl $.L.str, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp50:
# %bb.43: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit43
.Ltmp51:
callq hipDeviceSynchronize
.Ltmp52:
# %bb.44:
.Ltmp53:
leaq 24(%rsp), %rdi
movl %eax, %esi
callq _ZNSolsEi
.Ltmp54:
# %bb.45:
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB3_46
# %bb.48: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i89
cmpb $0, 56(%r14)
je .LBB3_50
# %bb.49:
movzbl 67(%r14), %eax
jmp .LBB3_52
.LBB3_50:
.Ltmp55:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp56:
# %bb.51: # %.noexc94
movq (%r14), %rax
.Ltmp57:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp58:
.LBB3_52: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i91
.Ltmp59:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp60:
# %bb.53: # %.noexc96
.Ltmp61:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp62:
# %bb.54: # %_ZNSolsEPFRSoS_E.exit44
movq 16(%rsp), %rdx
.Ltmp63:
leaq 24(%rsp), %rcx
movl $32, %edi
movl $32768, %esi # imm = 0x8000
callq _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE
.Ltmp64:
# %bb.55:
movq 16(%rsp), %rdx
.Ltmp65:
leaq 24(%rsp), %rcx
movl $64, %edi
movl $16384, %esi # imm = 0x4000
callq _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE
.Ltmp66:
# %bb.56:
movq 16(%rsp), %rdx
.Ltmp67:
leaq 24(%rsp), %rcx
movl $128, %edi
movl $8192, %esi # imm = 0x2000
callq _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE
.Ltmp68:
# %bb.57:
movq 16(%rsp), %rdx
.Ltmp69:
leaq 24(%rsp), %rcx
movl $256, %edi # imm = 0x100
movl $4096, %esi # imm = 0x1000
callq _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE
.Ltmp70:
# %bb.58:
movq 16(%rsp), %rdx
.Ltmp71:
leaq 24(%rsp), %rcx
movl $512, %edi # imm = 0x200
movl $2048, %esi # imm = 0x800
callq _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE
.Ltmp72:
# %bb.59:
movq 16(%rsp), %rdx
.Ltmp73:
leaq 24(%rsp), %rcx
movl $1024, %edi # imm = 0x400
movl $1024, %esi # imm = 0x400
callq _Z20openDotKernelAndTimeiiP8vectProdRSt14basic_ofstreamIcSt11char_traitsIcEE
.Ltmp74:
# %bb.60:
.Ltmp75:
leaq 24(%rsp), %rdi
movl $.L.str, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp76:
# %bb.61: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit45
movq 8(%rsp), %rdi
movq 16(%rsp), %rsi
.Ltmp77:
movl $29360128, %edx # imm = 0x1C00000
movl $2, %ecx
callq hipMemcpy
.Ltmp78:
# %bb.62:
.Ltmp79:
leaq 24(%rsp), %rdi
movl %eax, %esi
callq _ZNSolsEi
.Ltmp80:
# %bb.63:
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB3_84
# %bb.64: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i100
cmpb $0, 56(%r14)
je .LBB3_66
# %bb.65:
movzbl 67(%r14), %eax
jmp .LBB3_68
.LBB3_66:
.Ltmp81:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp82:
# %bb.67: # %.noexc105
movq (%r14), %rax
.Ltmp83:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp84:
.LBB3_68: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i102
.Ltmp85:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp86:
# %bb.69: # %.noexc107
.Ltmp87:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp88:
# %bb.70: # %_ZNSolsEPFRSoS_E.exit46
.Ltmp89:
leaq 24(%rsp), %rdi
movl $.L.str, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp90:
# %bb.71: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit47
movq 16(%rsp), %rdi
.Ltmp91:
callq hipFree
.Ltmp92:
# %bb.72:
.Ltmp93:
leaq 24(%rsp), %rdi
movl %eax, %esi
callq _ZNSolsEi
.Ltmp94:
# %bb.73:
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB3_84
# %bb.74: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i111
cmpb $0, 56(%r14)
je .LBB3_76
# %bb.75:
movzbl 67(%r14), %eax
jmp .LBB3_78
.LBB3_76:
.Ltmp95:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp96:
# %bb.77: # %.noexc116
movq (%r14), %rax
.Ltmp97:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp98:
.LBB3_78: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i113
.Ltmp99:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp100:
# %bb.79: # %.noexc118
.Ltmp101:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp102:
# %bb.80: # %_ZNSolsEPFRSoS_E.exit48
.Ltmp103:
leaq 24(%rsp), %rdi
movl $.L.str, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp104:
# %bb.81: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit49
movq 8(%rsp), %rdi
.Ltmp105:
callq hipHostFree
.Ltmp106:
# %bb.82:
.Ltmp107:
leaq 24(%rsp), %rdi
movl %eax, %esi
callq _ZNSolsEi
.Ltmp108:
# %bb.83:
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB3_84
# %bb.86: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i122
cmpb $0, 56(%r14)
je .LBB3_88
# %bb.87:
movzbl 67(%r14), %eax
jmp .LBB3_90
.LBB3_88:
.Ltmp109:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp110:
# %bb.89: # %.noexc127
movq (%r14), %rax
.Ltmp111:
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp112:
.LBB3_90: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i124
.Ltmp113:
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp114:
# %bb.91: # %.noexc129
.Ltmp115:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp116:
# %bb.92: # %_ZNSolsEPFRSoS_E.exit50
leaq 24(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
xorl %eax, %eax
addq $536, %rsp # imm = 0x218
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB3_46: # %.invoke134
.cfi_def_cfa_offset 560
.Ltmp120:
callq _ZSt16__throw_bad_castv
.Ltmp121:
# %bb.47: # %.cont135
.LBB3_84: # %.invoke136
.Ltmp117:
callq _ZSt16__throw_bad_castv
.Ltmp118:
# %bb.85: # %.cont137
.LBB3_9: # %.invoke
.Ltmp123:
callq _ZSt16__throw_bad_castv
.Ltmp124:
# %bb.10: # %.cont
.LBB3_27:
.Ltmp20:
jmp .LBB3_95
.LBB3_26:
.Ltmp125:
jmp .LBB3_95
.LBB3_93:
.Ltmp122:
jmp .LBB3_95
.LBB3_94:
.Ltmp119:
.LBB3_95:
movq %rax, %rbx
leaq 24(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table3:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp17-.Ltmp0 # Call between .Ltmp0 and .Ltmp17
.uleb128 .Ltmp125-.Lfunc_begin0 # jumps to .Ltmp125
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp19-.Ltmp18 # Call between .Ltmp18 and .Ltmp19
.uleb128 .Ltmp20-.Lfunc_begin0 # jumps to .Ltmp20
.byte 0 # On action: cleanup
.uleb128 .Ltmp19-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp21-.Ltmp19 # Call between .Ltmp19 and .Ltmp21
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp21-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp62-.Ltmp21 # Call between .Ltmp21 and .Ltmp62
.uleb128 .Ltmp122-.Lfunc_begin0 # jumps to .Ltmp122
.byte 0 # On action: cleanup
.uleb128 .Ltmp63-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp116-.Ltmp63 # Call between .Ltmp63 and .Ltmp116
.uleb128 .Ltmp119-.Lfunc_begin0 # jumps to .Ltmp119
.byte 0 # On action: cleanup
.uleb128 .Ltmp120-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp121-.Ltmp120 # Call between .Ltmp120 and .Ltmp121
.uleb128 .Ltmp122-.Lfunc_begin0 # jumps to .Ltmp122
.byte 0 # On action: cleanup
.uleb128 .Ltmp117-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp118-.Ltmp117 # Call between .Ltmp117 and .Ltmp118
.uleb128 .Ltmp119-.Lfunc_begin0 # jumps to .Ltmp119
.byte 0 # On action: cleanup
.uleb128 .Ltmp123-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp124-.Ltmp123 # Call between .Ltmp123 and .Ltmp124
.uleb128 .Ltmp125-.Lfunc_begin0 # jumps to .Ltmp125
.byte 0 # On action: cleanup
.uleb128 .Ltmp124-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Lfunc_end3-.Ltmp124 # Call between .Ltmp124 and .Lfunc_end3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3dotP8vectProd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3dotP8vectProd,@object # @_Z3dotP8vectProd
.section .rodata,"a",@progbits
.globl _Z3dotP8vectProd
.p2align 3, 0x0
_Z3dotP8vectProd:
.quad _Z18__device_stub__dotP8vectProd
.size _Z3dotP8vectProd, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "ErrorCode "
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Bl\303\266cke: "
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz ", Threads: "
.size .L.str.2, 12
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz ", Timing:"
.size .L.str.3, 10
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "timing.txt"
.size .L.str.4, 11
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Timing for different Grid / Block size:"
.size .L.str.5, 40
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3dotP8vectProd"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__dotP8vectProd
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z3dotP8vectProd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include<iostream>
using namespace std;
#include <device_launch_parameters.h>
//programs ran on GPU, called device
//func itself is a kernel
//global identifier indicates func ran on device, not host
//main code -> compiled via host, kernel code -> compiled via device
__global__ void add(int a, int b, int *c) {
*c = a + b;
}
//programs run on CPU, called host
int main(void) {
//invoke code from host
//angled brackets indicate args to runtime, influence how code executes on GPU
//local host int c
int c;
//create device ptr which creates mem via cudaMalloc
int *dev_c;
//allocate device memory via cudaMalloc, first arg = ptr to ptr that holds new mem addr, second arg = size mem
//cast as addr of pointer to int c as void double ptr
//handle error micro to return error code if exists
//cudaMalloc returns ptr to mem, cannot use this ptr to read from or write to memory from code that executes on host
//CAN pass mem ptr to func exec on device, or to read/write to device, and to func that execute on host
//important error, C compiler won't notify
//cannot deref dev_c
cudaMalloc ( (void**)&dev_c, sizeof(int) );
//run kernel call, pass ptr for device to use
add<<<1,1>>>(2, 7, dev_c);
//copy block of memory at address of ptr c inside device, to local int c inside host
//number of bytes copied indicated by sizeof(int), and define type of copy is to host
cudaMemcpy(&c, dev_c, sizeof(int), cudaMemcpyDeviceToHost);
printf("2 + 7 = %d\n", c);
cudaFree(dev_c);
return 0;
} | code for sm_80
Function : _Z3addiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe40000000f00 */
/*0050*/ IADD3 R5, R5, c[0x0][0x160], RZ ; /* 0x0000580005057a10 */
/* 0x000fca0007ffe0ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include<iostream>
using namespace std;
#include <device_launch_parameters.h>
//programs ran on GPU, called device
//func itself is a kernel
//global identifier indicates func ran on device, not host
//main code -> compiled via host, kernel code -> compiled via device
__global__ void add(int a, int b, int *c) {
*c = a + b;
}
//programs run on CPU, called host
int main(void) {
//invoke code from host
//angled brackets indicate args to runtime, influence how code executes on GPU
//local host int c
int c;
//create device ptr which creates mem via cudaMalloc
int *dev_c;
//allocate device memory via cudaMalloc, first arg = ptr to ptr that holds new mem addr, second arg = size mem
//cast as addr of pointer to int c as void double ptr
//handle error micro to return error code if exists
//cudaMalloc returns ptr to mem, cannot use this ptr to read from or write to memory from code that executes on host
//CAN pass mem ptr to func exec on device, or to read/write to device, and to func that execute on host
//important error, C compiler won't notify
//cannot deref dev_c
cudaMalloc ( (void**)&dev_c, sizeof(int) );
//run kernel call, pass ptr for device to use
add<<<1,1>>>(2, 7, dev_c);
//copy block of memory at address of ptr c inside device, to local int c inside host
//number of bytes copied indicated by sizeof(int), and define type of copy is to host
cudaMemcpy(&c, dev_c, sizeof(int), cudaMemcpyDeviceToHost);
printf("2 + 7 = %d\n", c);
cudaFree(dev_c);
return 0;
} | .file "tmpxft_0008a683_00000000-6_intro.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3addiiPiiiPi
.type _Z24__device_stub__Z3addiiPiiiPi, @function
_Z24__device_stub__Z3addiiPiiiPi:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z24__device_stub__Z3addiiPiiiPi, .-_Z24__device_stub__Z3addiiPiiiPi
.globl _Z3addiiPi
.type _Z3addiiPi, @function
_Z3addiiPi:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3addiiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3addiiPi, .-_Z3addiiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "2 + 7 = %d\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
movl 28(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdx
movl $7, %esi
movl $2, %edi
call _Z24__device_stub__Z3addiiPiiiPi
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include<iostream>
using namespace std;
#include <device_launch_parameters.h>
//programs ran on GPU, called device
//func itself is a kernel
//global identifier indicates func ran on device, not host
//main code -> compiled via host, kernel code -> compiled via device
__global__ void add(int a, int b, int *c) {
*c = a + b;
}
//programs run on CPU, called host
int main(void) {
//invoke code from host
//angled brackets indicate args to runtime, influence how code executes on GPU
//local host int c
int c;
//create device ptr which creates mem via cudaMalloc
int *dev_c;
//allocate device memory via cudaMalloc, first arg = ptr to ptr that holds new mem addr, second arg = size mem
//cast as addr of pointer to int c as void double ptr
//handle error micro to return error code if exists
//cudaMalloc returns ptr to mem, cannot use this ptr to read from or write to memory from code that executes on host
//CAN pass mem ptr to func exec on device, or to read/write to device, and to func that execute on host
//important error, C compiler won't notify
//cannot deref dev_c
cudaMalloc ( (void**)&dev_c, sizeof(int) );
//run kernel call, pass ptr for device to use
add<<<1,1>>>(2, 7, dev_c);
//copy block of memory at address of ptr c inside device, to local int c inside host
//number of bytes copied indicated by sizeof(int), and define type of copy is to host
cudaMemcpy(&c, dev_c, sizeof(int), cudaMemcpyDeviceToHost);
printf("2 + 7 = %d\n", c);
cudaFree(dev_c);
return 0;
} | #include <hip/hip_runtime.h>
#include<iostream>
using namespace std;
//programs ran on GPU, called device
//func itself is a kernel
//global identifier indicates func ran on device, not host
//main code -> compiled via host, kernel code -> compiled via device
__global__ void add(int a, int b, int *c) {
*c = a + b;
}
//programs run on CPU, called host
int main(void) {
//invoke code from host
//angled brackets indicate args to runtime, influence how code executes on GPU
//local host int c
int c;
//create device ptr which creates mem via cudaMalloc
int *dev_c;
//allocate device memory via cudaMalloc, first arg = ptr to ptr that holds new mem addr, second arg = size mem
//cast as addr of pointer to int c as void double ptr
//handle error micro to return error code if exists
//cudaMalloc returns ptr to mem, cannot use this ptr to read from or write to memory from code that executes on host
//CAN pass mem ptr to func exec on device, or to read/write to device, and to func that execute on host
//important error, C compiler won't notify
//cannot deref dev_c
hipMalloc ( (void**)&dev_c, sizeof(int) );
//run kernel call, pass ptr for device to use
add<<<1,1>>>(2, 7, dev_c);
//copy block of memory at address of ptr c inside device, to local int c inside host
//number of bytes copied indicated by sizeof(int), and define type of copy is to host
hipMemcpy(&c, dev_c, sizeof(int), hipMemcpyDeviceToHost);
printf("2 + 7 = %d\n", c);
hipFree(dev_c);
return 0;
} |
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