system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include<stdio.h>
__global__ void cuda_gray_kernel(unsigned char *b, unsigned char *g, unsigned char *r, unsigned char *gray, size_t size)
{
size_t idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx >= size) {
return;
}
gray[idx] = (unsigned char)(0.114f*b[idx] + 0.587f*g[idx] + 0.299f*r[idx] + 0.5);
}
extern "C" {
void cuda_gray(unsigned char *a, unsigned char *b, unsigned char *c, unsigned char *d, size_t size)
{
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
unsigned char *d_a, *d_b, *d_c, *d_d;
hipMalloc((void **)&d_a, size * sizeof(char));
hipMalloc((void **)&d_b, size * sizeof(char));
hipMalloc((void **)&d_c, size * sizeof(char));
hipMalloc((void **)&d_d, size * sizeof(char));
hipMemcpy(d_a, a, size * sizeof(char), hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size * sizeof(char), hipMemcpyHostToDevice);
hipMemcpy(d_c, c, size * sizeof(char), hipMemcpyHostToDevice);
hipMemcpy(d_d, d, size * sizeof(char), hipMemcpyHostToDevice);
hipEventRecord(start);
cuda_gray_kernel <<< ceil(size / 1024.0), 1024 >>> (d_a, d_b, d_c, d_d, size);
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("Time on GPU : %f msec\n", milliseconds);
hipMemcpy(d, d_d, size * sizeof(char), hipMemcpyDeviceToHost);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
hipFree(d_d);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16cuda_gray_kernelPhS_S_S_m
.globl _Z16cuda_gray_kernelPhS_S_S_m
.p2align 8
.type _Z16cuda_gray_kernelPhS_S_S_m,@function
_Z16cuda_gray_kernelPhS_S_S_m:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v2, vcc_lo
global_load_u8 v0, v[3:4], off
global_load_u8 v5, v[5:6], off
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
global_load_u8 v3, v[3:4], off
s_waitcnt vmcnt(2)
v_cvt_f32_ubyte0_e32 v0, v0
s_waitcnt vmcnt(1)
v_cvt_f32_ubyte0_e32 v4, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_f32_e32 v0, 0x3f1645a2, v0
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v3, v3
v_fmamk_f32 v0, v4, 0x3de978d5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v0, v3, 0x3e991687, v0
v_cvt_f64_f32_e32 v[3:4], v0
v_add_co_u32 v0, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[3:4], v[3:4], 0.5
v_cvt_i32_f64_e32 v3, v[3:4]
global_store_b8 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16cuda_gray_kernelPhS_S_S_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16cuda_gray_kernelPhS_S_S_m, .Lfunc_end0-_Z16cuda_gray_kernelPhS_S_S_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16cuda_gray_kernelPhS_S_S_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16cuda_gray_kernelPhS_S_S_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include<stdio.h>
__global__ void cuda_gray_kernel(unsigned char *b, unsigned char *g, unsigned char *r, unsigned char *gray, size_t size)
{
size_t idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx >= size) {
return;
}
gray[idx] = (unsigned char)(0.114f*b[idx] + 0.587f*g[idx] + 0.299f*r[idx] + 0.5);
}
extern "C" {
void cuda_gray(unsigned char *a, unsigned char *b, unsigned char *c, unsigned char *d, size_t size)
{
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
unsigned char *d_a, *d_b, *d_c, *d_d;
hipMalloc((void **)&d_a, size * sizeof(char));
hipMalloc((void **)&d_b, size * sizeof(char));
hipMalloc((void **)&d_c, size * sizeof(char));
hipMalloc((void **)&d_d, size * sizeof(char));
hipMemcpy(d_a, a, size * sizeof(char), hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size * sizeof(char), hipMemcpyHostToDevice);
hipMemcpy(d_c, c, size * sizeof(char), hipMemcpyHostToDevice);
hipMemcpy(d_d, d, size * sizeof(char), hipMemcpyHostToDevice);
hipEventRecord(start);
cuda_gray_kernel <<< ceil(size / 1024.0), 1024 >>> (d_a, d_b, d_c, d_d, size);
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("Time on GPU : %f msec\n", milliseconds);
hipMemcpy(d, d_d, size * sizeof(char), hipMemcpyDeviceToHost);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
hipFree(d_d);
}
} | .text
.file "cuda_lib.hip"
.globl _Z31__device_stub__cuda_gray_kernelPhS_S_S_m # -- Begin function _Z31__device_stub__cuda_gray_kernelPhS_S_S_m
.p2align 4, 0x90
.type _Z31__device_stub__cuda_gray_kernelPhS_S_S_m,@function
_Z31__device_stub__cuda_gray_kernelPhS_S_S_m: # @_Z31__device_stub__cuda_gray_kernelPhS_S_S_m
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16cuda_gray_kernelPhS_S_S_m, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z31__device_stub__cuda_gray_kernelPhS_S_S_m, .Lfunc_end0-_Z31__device_stub__cuda_gray_kernelPhS_S_S_m
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function cuda_gray
.LCPI1_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI1_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_2:
.quad 0x3f50000000000000 # double 9.765625E-4
.text
.globl cuda_gray
.p2align 4, 0x90
.type cuda_gray,@function
cuda_gray: # @cuda_gray
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $192, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %r8, %rbx
movq %rcx, %r14
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %r13
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq %r13, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r12, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %rbx, %xmm1
punpckldq .LCPI1_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI1_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
mulsd .LCPI1_2(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movq %rsi, 112(%rsp)
movq %rbx, 104(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z16cuda_gray_kernelPhS_S_S_m, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rdi
callq hipEventSynchronize
movl $0, 144(%rsp)
movq 48(%rsp), %rsi
movq 40(%rsp), %rdx
leaq 144(%rsp), %rdi
callq hipEventElapsedTime
movss 144(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $192, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size cuda_gray, .Lfunc_end1-cuda_gray
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16cuda_gray_kernelPhS_S_S_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16cuda_gray_kernelPhS_S_S_m,@object # @_Z16cuda_gray_kernelPhS_S_S_m
.section .rodata,"a",@progbits
.globl _Z16cuda_gray_kernelPhS_S_S_m
.p2align 3, 0x0
_Z16cuda_gray_kernelPhS_S_S_m:
.quad _Z31__device_stub__cuda_gray_kernelPhS_S_S_m
.size _Z16cuda_gray_kernelPhS_S_S_m, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time on GPU : %f msec\n"
.size .L.str, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16cuda_gray_kernelPhS_S_S_m"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__cuda_gray_kernelPhS_S_S_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16cuda_gray_kernelPhS_S_S_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16cuda_gray_kernelPhS_S_S_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x184], PT, P0 ; /* 0x00006100ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IADD3 R6, P1, R0.reuse, c[0x0][0x168], RZ ; /* 0x00005a0000067a10 */
/* 0x040fe20007f3e0ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IADD3 R4, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000047a10 */
/* 0x000fc60007f1e0ff */
/*00a0*/ IMAD.X R7, RZ, RZ, c[0x0][0x16c], P1 ; /* 0x00005b00ff077624 */
/* 0x000fe200008e06ff */
/*00b0*/ IADD3.X R5, RZ, c[0x0][0x164], RZ, P0, !PT ; /* 0x00005900ff057a10 */
/* 0x000fe400007fe4ff */
/*00c0*/ IADD3 R8, P0, R0.reuse, c[0x0][0x170], RZ ; /* 0x00005c0000087a10 */
/* 0x040fe40007f1e0ff */
/*00d0*/ LDG.E.U8 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1100 */
/*00e0*/ IADD3.X R9, RZ, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d00ff097a10 */
/* 0x000fe400007fe4ff */
/*00f0*/ LDG.E.U8 R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x0000e8000c1e1100 */
/*0100*/ LDG.E.U8 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f22000c1e1100 */
/*0110*/ IADD3 R4, P0, R0, c[0x0][0x178], RZ ; /* 0x00005e0000047a10 */
/* 0x001fca0007f1e0ff */
/*0120*/ IMAD.X R5, RZ, RZ, c[0x0][0x17c], P0 ; /* 0x00005f00ff057624 */
/* 0x000fe200000e06ff */
/*0130*/ I2F.U16 R2, R6 ; /* 0x0000000600027306 */
/* 0x004e300000101000 */
/*0140*/ I2F.U16 R10, R10 ; /* 0x0000000a000a7306 */
/* 0x008e700000101000 */
/*0150*/ I2F.U16 R12, R8 ; /* 0x00000008000c7306 */
/* 0x010ea20000101000 */
/*0160*/ FMUL R3, R2, 0.58700001239776611328 ; /* 0x3f1645a202037820 */
/* 0x001fc80000400000 */
/*0170*/ FFMA R3, R10, 0.11400000005960464478, R3 ; /* 0x3de978d50a037823 */
/* 0x002fc80000000003 */
/*0180*/ FFMA R12, R12, 0.29899999499320983887, R3 ; /* 0x3e9916870c0c7823 */
/* 0x004fc80000000003 */
/*0190*/ F2F.F64.F32 R2, R12 ; /* 0x0000000c00027310 */
/* 0x000e240000201800 */
/*01a0*/ DADD R2, R2, 0.5 ; /* 0x3fe0000002027429 */
/* 0x001e140000000000 */
/*01b0*/ F2I.U32.F64.TRUNC R3, R2 ; /* 0x0000000200037311 */
/* 0x001e24000030d000 */
/*01c0*/ STG.E.U8 [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x001fe2000c101104 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16cuda_gray_kernelPhS_S_S_m
.globl _Z16cuda_gray_kernelPhS_S_S_m
.p2align 8
.type _Z16cuda_gray_kernelPhS_S_S_m,@function
_Z16cuda_gray_kernelPhS_S_S_m:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v2, vcc_lo
global_load_u8 v0, v[3:4], off
global_load_u8 v5, v[5:6], off
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
global_load_u8 v3, v[3:4], off
s_waitcnt vmcnt(2)
v_cvt_f32_ubyte0_e32 v0, v0
s_waitcnt vmcnt(1)
v_cvt_f32_ubyte0_e32 v4, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_f32_e32 v0, 0x3f1645a2, v0
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v3, v3
v_fmamk_f32 v0, v4, 0x3de978d5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v0, v3, 0x3e991687, v0
v_cvt_f64_f32_e32 v[3:4], v0
v_add_co_u32 v0, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[3:4], v[3:4], 0.5
v_cvt_i32_f64_e32 v3, v[3:4]
global_store_b8 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16cuda_gray_kernelPhS_S_S_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16cuda_gray_kernelPhS_S_S_m, .Lfunc_end0-_Z16cuda_gray_kernelPhS_S_S_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16cuda_gray_kernelPhS_S_S_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16cuda_gray_kernelPhS_S_S_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010459c_00000000-6_cuda_lib.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z16cuda_gray_kernelPhS_S_S_mPhS_S_S_m
.type _Z43__device_stub__Z16cuda_gray_kernelPhS_S_S_mPhS_S_S_m, @function
_Z43__device_stub__Z16cuda_gray_kernelPhS_S_S_mPhS_S_S_m:
.LFB2082:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16cuda_gray_kernelPhS_S_S_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z43__device_stub__Z16cuda_gray_kernelPhS_S_S_mPhS_S_S_m, .-_Z43__device_stub__Z16cuda_gray_kernelPhS_S_S_mPhS_S_S_m
.globl _Z16cuda_gray_kernelPhS_S_S_m
.type _Z16cuda_gray_kernelPhS_S_S_m, @function
_Z16cuda_gray_kernelPhS_S_S_m:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z16cuda_gray_kernelPhS_S_S_mPhS_S_S_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z16cuda_gray_kernelPhS_S_S_m, .-_Z16cuda_gray_kernelPhS_S_S_m
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "Time on GPU : %f msec\n"
.text
.globl cuda_gray
.type cuda_gray, @function
cuda_gray:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movq %rcx, %rbp
movq %r8, %rbx
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
call cudaEventCreate@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq (%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
testq %rbx, %rbx
js .L12
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
.L13:
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC6(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC1(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L14
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L14:
cvttsd2siq %xmm3, %rax
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L15:
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movq 8(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 60(%rsp)
leaq 60(%rsp), %rdi
movq 8(%rsp), %rdx
movq (%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 60(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movq %rbx, %rax
shrq %rax
movq %rbx, %rdx
andl $1, %edx
orq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
jmp .L13
.L18:
movq %rbx, %r8
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z43__device_stub__Z16cuda_gray_kernelPhS_S_S_mPhS_S_S_m
jmp .L15
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size cuda_gray, .-cuda_gray
.section .rodata.str1.1
.LC7:
.string "_Z16cuda_gray_kernelPhS_S_S_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z16cuda_gray_kernelPhS_S_S_m(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1062207488
.align 8
.LC1:
.long 0
.long 1127219200
.align 8
.LC3:
.long 0
.long 1072693248
.align 8
.LC6:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_lib.hip"
.globl _Z31__device_stub__cuda_gray_kernelPhS_S_S_m # -- Begin function _Z31__device_stub__cuda_gray_kernelPhS_S_S_m
.p2align 4, 0x90
.type _Z31__device_stub__cuda_gray_kernelPhS_S_S_m,@function
_Z31__device_stub__cuda_gray_kernelPhS_S_S_m: # @_Z31__device_stub__cuda_gray_kernelPhS_S_S_m
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16cuda_gray_kernelPhS_S_S_m, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z31__device_stub__cuda_gray_kernelPhS_S_S_m, .Lfunc_end0-_Z31__device_stub__cuda_gray_kernelPhS_S_S_m
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function cuda_gray
.LCPI1_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI1_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_2:
.quad 0x3f50000000000000 # double 9.765625E-4
.text
.globl cuda_gray
.p2align 4, 0x90
.type cuda_gray,@function
cuda_gray: # @cuda_gray
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $192, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %r8, %rbx
movq %rcx, %r14
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %r13
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq %r13, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq %r12, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %rbx, %xmm1
punpckldq .LCPI1_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI1_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
mulsd .LCPI1_2(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movq %rsi, 112(%rsp)
movq %rbx, 104(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z16cuda_gray_kernelPhS_S_S_m, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rdi
callq hipEventSynchronize
movl $0, 144(%rsp)
movq 48(%rsp), %rsi
movq 40(%rsp), %rdx
leaq 144(%rsp), %rdi
callq hipEventElapsedTime
movss 144(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $192, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size cuda_gray, .Lfunc_end1-cuda_gray
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16cuda_gray_kernelPhS_S_S_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16cuda_gray_kernelPhS_S_S_m,@object # @_Z16cuda_gray_kernelPhS_S_S_m
.section .rodata,"a",@progbits
.globl _Z16cuda_gray_kernelPhS_S_S_m
.p2align 3, 0x0
_Z16cuda_gray_kernelPhS_S_S_m:
.quad _Z31__device_stub__cuda_gray_kernelPhS_S_S_m
.size _Z16cuda_gray_kernelPhS_S_S_m, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time on GPU : %f msec\n"
.size .L.str, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16cuda_gray_kernelPhS_S_S_m"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__cuda_gray_kernelPhS_S_S_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16cuda_gray_kernelPhS_S_S_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <cuda.h>
/**
* Encrypt Program Cuda
*
* This program encrypts a file using a degree 2 formula using Cuda
* Parallelization and then decrypts the file using another degree 2
* formula.
*
* @Author: Clayton Chase Glenn
*/
#define MAX 20
#define DEBUG 0
/** Kernel Function
* First finds the Thread ID within the block of GPU Threads
* and if the Thread is Correct, it Encrypts the corresponding
* Character in the String.
**/
__global__
void encrypt(char *p, char *c, int a, int b, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < n) c[tid] = (a*p[tid] + b) % 256;
}
/** Kernel Function
* First finds the Thread ID within the block of GPU Threads
* and if the Thread is Correct, it Encrypts the corresponding
* Character in the String.
**/
__global__
void decrypt(char *p, char *c, int a, int b, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < n) c[tid] = (a*p[tid] + b) % 256;
}
/** Kernel Function
* First finds the Thread ID within the block of GPU Threads
* and if the Thread is Correct, it checks if the corresponding
* character in array a matches b.
**/
__global__
void isMatch(char *p, char *c, int *a, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < n) {
if (c[tid] != p[tid]) {
*a = 1;
}
}
}
/**
* Helper Function
* Prints an string to standard error showing help
* for valid arguments in the executable
**/
void printerror(){
fprintf(stderr, "Invalid Arguments\n");
fprintf(stderr, "Correct Form: ./encrypt [File to Encrypt]\n");
fprintf(stderr, " or\n");
fprintf(stderr, " ./encrypt -n [2^(1:20)]\n");
exit(0);
}
/**
* Main Program
* This Program is for Homework 6 to encrypt some text or show
* the encryption method of text that is 2 to the power of N
* characters long all initialized to zero.
**/
int main(int argc, char **argv) {
// Declare a buffer of max size to start
int N = MAX;
char *buf;
// Check for immediate errors in args
if (argc < 2) printerror();
if (argc == 3 && strcmp(argv[1], "-n")) printerror();
// If args match for testing, Initiallize the program
if(!strcmp(argv[1], "-n") && argc == 3){
// Get total characters from args
N = strtol(argv[2], NULL, 10);
// Show error if N isn't within constraints
if(N < 1 || N > 20) printerror();
// N <- calc to 2^N as size and allocate space
N = (int)pow(2, N);
buf = (char*)malloc(N*sizeof(char));
//Initiallize the buffer to Zero
int i = 0;
while (i < N) buf[i++] = 48;
}
// If 2 args, this means file
if(argc == 2) {
// Declare a file pointer, character array, and single character for reading
FILE *fp;
char c;
char chars[1048576];
int i = 0;
// Open the file for reading
fp = fopen(argv[1], "r");
// If file is null, file does not exist or error
if (fp == NULL) {
fprintf(stderr, "Not a Valid File\n");
return (-1);
}
// Read each character and keep within 2^20, add to array
while((c = fgetc(fp)) != EOF) {
if (i >= 1048576) {
fprintf(stderr, "File Too Large\n");
return (-1);
}
chars[i++] = c;
}
// Increment i for space and allocate space for buffer
N = i + 1;
buf = (char*)malloc(N*sizeof(char));
// Copy read elements into buffer
i = 0;
while(i < N) buf[i] = chars[i++];
// Close File, not needed anymore
fclose(fp);
}
// Initiallize Character Arrays for Encrypting and manual memset
char h_p[N];
char h_c[N];
char h_r[N];
int i = 0;
while (i < N) {
h_p[i] = buf[i];
h_c[i] = 32;
h_r[i++] = 32;
}
// Init all other variables
char *dev_p, *dev_c, *dev_r;
int *match;
int h_match = 0;
int h_a = 171, h_b = 55;
int r_a = 3, r_b = 91;
cudaEvent_t start1, start2, start3, startf, stop1, stop2, stop3, stopf;
cudaEventCreate(&start1);
cudaEventCreate(&stop1);
cudaEventCreate(&start2);
cudaEventCreate(&stop2);
cudaEventCreate(&start3);
cudaEventCreate(&stop3);
cudaEventCreate(&startf);
cudaEventCreate(&stopf);
float final_time1 = 0.0, final_time2 = 0.0, final_time3 = 0.0, final_timef = 0.0;
// Allocate Memory for match flag
match = (int*)malloc(sizeof(int));
*match = 0;
// Allocate memory in the GPU for the character arrays
cudaMalloc(&dev_p, N*sizeof(char));
cudaMalloc(&dev_c, N*sizeof(char));
cudaMalloc(&dev_r, N*sizeof(char));
cudaMalloc(&match, sizeof(int));
// Print N for distinguish
printf("N: %d\n", N);
// If debug on, show plain text
if(DEBUG) {
printf("Plain Text: ");
i = 0;
while(i < N) printf("%c", h_p[i++]);
printf("\n");
}
// Copy the Memory from the arrays to the array pointers
cudaMemcpy(dev_p, h_p, N*sizeof(char), cudaMemcpyHostToDevice);
cudaMemcpy(dev_c, h_c, N*sizeof(char), cudaMemcpyHostToDevice);
cudaMemcpy(dev_r, h_r, N*sizeof(char), cudaMemcpyHostToDevice);
// Start Total Time Record
cudaEventRecord(startf);
// Encrypt the Plain Text and Record Start and Finish
cudaEventRecord(start1);
encrypt<<<128, 128>>>(dev_p, dev_c, h_a, h_b, N);
cudaEventRecord(stop1);
// Copy the results from GPU to the CPU
cudaMemcpy(h_c, dev_c, N*sizeof(char), cudaMemcpyDeviceToHost);
// If debug on, show encrypted text
if(DEBUG) {
printf("Encrypted Text: ");
i = 0;
while(i < N) printf("%c", h_c[i++]);
printf("\n");
}
// Syncronize all blocks and threads in GPU and get time
cudaEventSynchronize(stop1);
cudaEventElapsedTime(&final_time1, start1, stop1);
// Decrypt the Encrypted Text
cudaEventRecord(stop2);
decrypt<<<128, 128>>>(dev_c, dev_r, r_a, r_b, N);
cudaEventRecord(stop2);
// Copy the results from GPU to CPU
cudaMemcpy(h_r, dev_r, N*sizeof(char), cudaMemcpyDeviceToHost);
// If debug on, show decrypted text
if(DEBUG) {
printf("Decrypted Text: ", h_r);
i = 0;
while(i < N) printf("%c", h_r[i++]);
printf("\n");
}
// Syncronize all blocks and threads in GPU and get time
cudaEventSynchronize(stop2);
cudaEventElapsedTime(&final_time2, start2, stop2);
// Check if Plain Text and Encrypt<-->Decrypt Text is matching by GPU
cudaEventRecord(start3);
isMatch<<<128, 128>>>(dev_r, dev_p, match, N);
cudaEventRecord(stop3);
// Copy the Match Result from GPU to CPU
cudaMemcpy(&h_match, match, sizeof(int), cudaMemcpyDeviceToHost);
// If match is zero, success, else, no success
if (h_match) fprintf(stdout, "Does not Match\n");
else fprintf(stdout, "Does Match\n");
// Syncronize all blocks and threads in GPU and get time
cudaEventSynchronize(stop3);
cudaEventElapsedTime(&final_time3, start3, stop3);
// Syncronize all blocks and threads in GPU and get time
cudaEventRecord(stopf);
cudaEventSynchronize(stopf);
cudaEventElapsedTime(&final_timef, startf, stopf);
// Print Times
printf("Encrypt Time: %4.10f seconds\n", final_time1/1000);
printf("Decrypt Time: %4.10f seconds\n", final_time2/1000);
printf("Match Time: %4.10f seconds\n", final_time3/1000);
printf("Total Time: %4.10f seconds\n\n", final_timef/1000);
// Free the GPU memory
cudaFree(dev_p);
cudaFree(dev_c);
cudaFree(dev_r);
} | code for sm_80
Function : _Z7isMatchPcS_Pii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ SHF.R.S32.HI R0, RZ, 0x1f, R4 ; /* 0x0000001fff007819 */
/* 0x000fe20000011404 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IADD3 R2, P1, R4.reuse, c[0x0][0x160], RZ ; /* 0x0000580004027a10 */
/* 0x040fe40007f3e0ff */
/*0090*/ IADD3 R4, P0, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fe40007f1e0ff */
/*00a0*/ IADD3.X R3, R0.reuse, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590000037a10 */
/* 0x040fe40000ffe4ff */
/*00b0*/ IADD3.X R5, R0, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0000057a10 */
/* 0x000fc600007fe4ff */
/*00c0*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1100 */
/*00d0*/ LDG.E.U8 R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1100 */
/*00e0*/ ISETP.NE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x004fda0003f05270 */
/*00f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0100*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fe400078e00ff */
/*0110*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe400078e00ff */
/*0120*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fca00078e00ff */
/*0130*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7decryptPcS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ SHF.R.S32.HI R0, RZ, 0x1f, R4 ; /* 0x0000001fff007819 */
/* 0x000fe20000011404 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IADD3 R2, P0, R4, c[0x0][0x160], RZ ; /* 0x0000580004027a10 */
/* 0x000fc80007f1e0ff */
/*0090*/ IADD3.X R3, R0, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000037a10 */
/* 0x000fca00007fe4ff */
/*00a0*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1100 */
/*00b0*/ IADD3 R4, P0, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fe20007f1e0ff */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff077624 */
/* 0x000fc600078e00ff */
/*00d0*/ IADD3.X R5, R0, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0000057a10 */
/* 0x000fe200007fe4ff */
/*00e0*/ IMAD R7, R2, R7, c[0x0][0x174] ; /* 0x00005d0002077624 */
/* 0x004fca00078e0207 */
/*00f0*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101104 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7encryptPcS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ SHF.R.S32.HI R0, RZ, 0x1f, R4 ; /* 0x0000001fff007819 */
/* 0x000fe20000011404 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IADD3 R2, P0, R4, c[0x0][0x160], RZ ; /* 0x0000580004027a10 */
/* 0x000fc80007f1e0ff */
/*0090*/ IADD3.X R3, R0, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000037a10 */
/* 0x000fca00007fe4ff */
/*00a0*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1100 */
/*00b0*/ IADD3 R4, P0, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fe20007f1e0ff */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff077624 */
/* 0x000fc600078e00ff */
/*00d0*/ IADD3.X R5, R0, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0000057a10 */
/* 0x000fe200007fe4ff */
/*00e0*/ IMAD R7, R2, R7, c[0x0][0x174] ; /* 0x00005d0002077624 */
/* 0x004fca00078e0207 */
/*00f0*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101104 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <cuda.h>
/**
* Encrypt Program Cuda
*
* This program encrypts a file using a degree 2 formula using Cuda
* Parallelization and then decrypts the file using another degree 2
* formula.
*
* @Author: Clayton Chase Glenn
*/
#define MAX 20
#define DEBUG 0
/** Kernel Function
* First finds the Thread ID within the block of GPU Threads
* and if the Thread is Correct, it Encrypts the corresponding
* Character in the String.
**/
__global__
void encrypt(char *p, char *c, int a, int b, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < n) c[tid] = (a*p[tid] + b) % 256;
}
/** Kernel Function
* First finds the Thread ID within the block of GPU Threads
* and if the Thread is Correct, it Encrypts the corresponding
* Character in the String.
**/
__global__
void decrypt(char *p, char *c, int a, int b, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < n) c[tid] = (a*p[tid] + b) % 256;
}
/** Kernel Function
* First finds the Thread ID within the block of GPU Threads
* and if the Thread is Correct, it checks if the corresponding
* character in array a matches b.
**/
__global__
void isMatch(char *p, char *c, int *a, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < n) {
if (c[tid] != p[tid]) {
*a = 1;
}
}
}
/**
* Helper Function
* Prints an string to standard error showing help
* for valid arguments in the executable
**/
void printerror(){
fprintf(stderr, "Invalid Arguments\n");
fprintf(stderr, "Correct Form: ./encrypt [File to Encrypt]\n");
fprintf(stderr, " or\n");
fprintf(stderr, " ./encrypt -n [2^(1:20)]\n");
exit(0);
}
/**
* Main Program
* This Program is for Homework 6 to encrypt some text or show
* the encryption method of text that is 2 to the power of N
* characters long all initialized to zero.
**/
int main(int argc, char **argv) {
// Declare a buffer of max size to start
int N = MAX;
char *buf;
// Check for immediate errors in args
if (argc < 2) printerror();
if (argc == 3 && strcmp(argv[1], "-n")) printerror();
// If args match for testing, Initiallize the program
if(!strcmp(argv[1], "-n") && argc == 3){
// Get total characters from args
N = strtol(argv[2], NULL, 10);
// Show error if N isn't within constraints
if(N < 1 || N > 20) printerror();
// N <- calc to 2^N as size and allocate space
N = (int)pow(2, N);
buf = (char*)malloc(N*sizeof(char));
//Initiallize the buffer to Zero
int i = 0;
while (i < N) buf[i++] = 48;
}
// If 2 args, this means file
if(argc == 2) {
// Declare a file pointer, character array, and single character for reading
FILE *fp;
char c;
char chars[1048576];
int i = 0;
// Open the file for reading
fp = fopen(argv[1], "r");
// If file is null, file does not exist or error
if (fp == NULL) {
fprintf(stderr, "Not a Valid File\n");
return (-1);
}
// Read each character and keep within 2^20, add to array
while((c = fgetc(fp)) != EOF) {
if (i >= 1048576) {
fprintf(stderr, "File Too Large\n");
return (-1);
}
chars[i++] = c;
}
// Increment i for space and allocate space for buffer
N = i + 1;
buf = (char*)malloc(N*sizeof(char));
// Copy read elements into buffer
i = 0;
while(i < N) buf[i] = chars[i++];
// Close File, not needed anymore
fclose(fp);
}
// Initiallize Character Arrays for Encrypting and manual memset
char h_p[N];
char h_c[N];
char h_r[N];
int i = 0;
while (i < N) {
h_p[i] = buf[i];
h_c[i] = 32;
h_r[i++] = 32;
}
// Init all other variables
char *dev_p, *dev_c, *dev_r;
int *match;
int h_match = 0;
int h_a = 171, h_b = 55;
int r_a = 3, r_b = 91;
cudaEvent_t start1, start2, start3, startf, stop1, stop2, stop3, stopf;
cudaEventCreate(&start1);
cudaEventCreate(&stop1);
cudaEventCreate(&start2);
cudaEventCreate(&stop2);
cudaEventCreate(&start3);
cudaEventCreate(&stop3);
cudaEventCreate(&startf);
cudaEventCreate(&stopf);
float final_time1 = 0.0, final_time2 = 0.0, final_time3 = 0.0, final_timef = 0.0;
// Allocate Memory for match flag
match = (int*)malloc(sizeof(int));
*match = 0;
// Allocate memory in the GPU for the character arrays
cudaMalloc(&dev_p, N*sizeof(char));
cudaMalloc(&dev_c, N*sizeof(char));
cudaMalloc(&dev_r, N*sizeof(char));
cudaMalloc(&match, sizeof(int));
// Print N for distinguish
printf("N: %d\n", N);
// If debug on, show plain text
if(DEBUG) {
printf("Plain Text: ");
i = 0;
while(i < N) printf("%c", h_p[i++]);
printf("\n");
}
// Copy the Memory from the arrays to the array pointers
cudaMemcpy(dev_p, h_p, N*sizeof(char), cudaMemcpyHostToDevice);
cudaMemcpy(dev_c, h_c, N*sizeof(char), cudaMemcpyHostToDevice);
cudaMemcpy(dev_r, h_r, N*sizeof(char), cudaMemcpyHostToDevice);
// Start Total Time Record
cudaEventRecord(startf);
// Encrypt the Plain Text and Record Start and Finish
cudaEventRecord(start1);
encrypt<<<128, 128>>>(dev_p, dev_c, h_a, h_b, N);
cudaEventRecord(stop1);
// Copy the results from GPU to the CPU
cudaMemcpy(h_c, dev_c, N*sizeof(char), cudaMemcpyDeviceToHost);
// If debug on, show encrypted text
if(DEBUG) {
printf("Encrypted Text: ");
i = 0;
while(i < N) printf("%c", h_c[i++]);
printf("\n");
}
// Syncronize all blocks and threads in GPU and get time
cudaEventSynchronize(stop1);
cudaEventElapsedTime(&final_time1, start1, stop1);
// Decrypt the Encrypted Text
cudaEventRecord(stop2);
decrypt<<<128, 128>>>(dev_c, dev_r, r_a, r_b, N);
cudaEventRecord(stop2);
// Copy the results from GPU to CPU
cudaMemcpy(h_r, dev_r, N*sizeof(char), cudaMemcpyDeviceToHost);
// If debug on, show decrypted text
if(DEBUG) {
printf("Decrypted Text: ", h_r);
i = 0;
while(i < N) printf("%c", h_r[i++]);
printf("\n");
}
// Syncronize all blocks and threads in GPU and get time
cudaEventSynchronize(stop2);
cudaEventElapsedTime(&final_time2, start2, stop2);
// Check if Plain Text and Encrypt<-->Decrypt Text is matching by GPU
cudaEventRecord(start3);
isMatch<<<128, 128>>>(dev_r, dev_p, match, N);
cudaEventRecord(stop3);
// Copy the Match Result from GPU to CPU
cudaMemcpy(&h_match, match, sizeof(int), cudaMemcpyDeviceToHost);
// If match is zero, success, else, no success
if (h_match) fprintf(stdout, "Does not Match\n");
else fprintf(stdout, "Does Match\n");
// Syncronize all blocks and threads in GPU and get time
cudaEventSynchronize(stop3);
cudaEventElapsedTime(&final_time3, start3, stop3);
// Syncronize all blocks and threads in GPU and get time
cudaEventRecord(stopf);
cudaEventSynchronize(stopf);
cudaEventElapsedTime(&final_timef, startf, stopf);
// Print Times
printf("Encrypt Time: %4.10f seconds\n", final_time1/1000);
printf("Decrypt Time: %4.10f seconds\n", final_time2/1000);
printf("Match Time: %4.10f seconds\n", final_time3/1000);
printf("Total Time: %4.10f seconds\n\n", final_timef/1000);
// Free the GPU memory
cudaFree(dev_p);
cudaFree(dev_c);
cudaFree(dev_r);
} | .file "tmpxft_00099575_00000000-6_Encrypt_CUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Invalid Arguments\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Correct Form: ./encrypt [File to Encrypt]\n"
.section .rodata.str1.1
.LC2:
.string " or\n"
.section .rodata.str1.8
.align 8
.LC3:
.string " ./encrypt -n [2^(1:20)]\n"
.text
.globl _Z10printerrorv
.type _Z10printerrorv, @function
_Z10printerrorv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z10printerrorv, .-_Z10printerrorv
.globl _Z31__device_stub__Z7encryptPcS_iiiPcS_iii
.type _Z31__device_stub__Z7encryptPcS_iiiPcS_iii, @function
_Z31__device_stub__Z7encryptPcS_iiiPcS_iii:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7encryptPcS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z31__device_stub__Z7encryptPcS_iiiPcS_iii, .-_Z31__device_stub__Z7encryptPcS_iiiPcS_iii
.globl _Z7encryptPcS_iii
.type _Z7encryptPcS_iii, @function
_Z7encryptPcS_iii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z7encryptPcS_iiiPcS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7encryptPcS_iii, .-_Z7encryptPcS_iii
.globl _Z31__device_stub__Z7decryptPcS_iiiPcS_iii
.type _Z31__device_stub__Z7decryptPcS_iiiPcS_iii, @function
_Z31__device_stub__Z7decryptPcS_iiiPcS_iii:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7decryptPcS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z31__device_stub__Z7decryptPcS_iiiPcS_iii, .-_Z31__device_stub__Z7decryptPcS_iiiPcS_iii
.globl _Z7decryptPcS_iii
.type _Z7decryptPcS_iii, @function
_Z7decryptPcS_iii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z7decryptPcS_iiiPcS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z7decryptPcS_iii, .-_Z7decryptPcS_iii
.globl _Z31__device_stub__Z7isMatchPcS_PiiPcS_Pii
.type _Z31__device_stub__Z7isMatchPcS_PiiPcS_Pii, @function
_Z31__device_stub__Z7isMatchPcS_PiiPcS_Pii:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7isMatchPcS_Pii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z31__device_stub__Z7isMatchPcS_PiiPcS_Pii, .-_Z31__device_stub__Z7isMatchPcS_PiiPcS_Pii
.globl _Z7isMatchPcS_Pii
.type _Z7isMatchPcS_Pii, @function
_Z7isMatchPcS_Pii:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z7isMatchPcS_PiiPcS_Pii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z7isMatchPcS_Pii, .-_Z7isMatchPcS_Pii
.section .rodata.str1.1
.LC4:
.string "-n"
.LC6:
.string "r"
.LC7:
.string "Not a Valid File\n"
.LC8:
.string "File Too Large\n"
.LC10:
.string "N: %d\n"
.LC11:
.string "Does not Match\n"
.LC12:
.string "Does Match\n"
.section .rodata.str1.8
.align 8
.LC14:
.string "Encrypt Time: %4.10f seconds\n"
.align 8
.LC15:
.string "Decrypt Time: %4.10f seconds\n"
.align 8
.LC16:
.string "Match Time: %4.10f seconds\n"
.align 8
.LC17:
.string "Total Time: %4.10f seconds\n\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
leaq -1048576(%rsp), %r11
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
subq $184, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
cmpl $1, %edi
jle .L92
movq %rsi, %rbx
cmpl $3, %edi
je .L93
movl $20, -1048788(%rbp)
cmpl $2, %edi
je .L94
.L38:
movslq -1048788(%rbp), %rbx
leaq 15(%rbx), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L65:
cmpq %rdx, %rsp
je .L66
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L65
.L92:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L95
call _Z10printerrorv
.L95:
call __stack_chk_fail@PLT
.L93:
movq 8(%rsi), %rdi
leaq .LC4(%rip), %rsi
call strcmp@PLT
testl %eax, %eax
jne .L96
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
leal -1(%rax), %edx
cmpl $19, %edx
ja .L97
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
movsd .LC5(%rip), %xmm0
call pow@PLT
cvttsd2sil %xmm0, %r14d
movl %r14d, -1048788(%rbp)
movslq %r14d, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
testl %r14d, %r14d
jle .L36
leaq (%rbx,%rax), %rdx
.L37:
movb $48, (%rax)
addq $1, %rax
cmpq %rdx, %rax
jne .L37
jmp .L38
.L96:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L98
call _Z10printerrorv
.L98:
call __stack_chk_fail@PLT
.L97:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L99
call _Z10printerrorv
.L99:
call __stack_chk_fail@PLT
.L94:
movq 8(%rsi), %rdi
leaq .LC6(%rip), %rsi
call fopen@PLT
movq %rax, %r13
movl $0, %ebx
testq %rax, %rax
jne .L39
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L40
.L41:
movb %al, -1048640(%rbp,%rbx)
addq $1, %rbx
.L39:
movq %r13, %rdi
call fgetc@PLT
cmpb $-1, %al
je .L100
cmpq $1048576, %rbx
jne .L41
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L40:
movl $-1, %eax
jmp .L29
.L100:
leal 1(%rbx), %r15d
movl %r15d, -1048788(%rbp)
movslq %r15d, %rdi
call malloc@PLT
movq %rax, %r12
testl %r15d, %r15d
jle .L43
movl %ebx, %ebx
movl $0, %eax
.L44:
movzbl -1048640(%rbp,%rax), %edx
movb %dl, 1(%r12,%rax)
movq %rax, %rdx
addq $1, %rax
cmpq %rdx, %rbx
jne .L44
.L43:
movq %r13, %rdi
call fclose@PLT
movslq -1048788(%rbp), %rbx
leaq 15(%rbx), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L45:
cmpq %rdx, %rsp
je .L46
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L45
.L46:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L47
orq $0, -8(%rsp,%rax)
.L47:
movq %rsp, %r15
leaq 15(%rbx), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L48:
cmpq %rdx, %rsp
je .L49
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L48
.L49:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L50
orq $0, -8(%rsp,%rax)
.L50:
movq %rsp, %r13
leaq 15(%rbx), %rdx
movq %rdx, %rax
andq $-16, %rax
andq $-4096, %rdx
movq %rsp, %rcx
subq %rdx, %rcx
.L51:
cmpq %rcx, %rsp
je .L52
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L51
.L52:
movq %rax, %rdx
andl $4095, %edx
subq %rdx, %rsp
testq %rdx, %rdx
je .L53
orq $0, -8(%rsp,%rdx)
.L53:
movq %rsp, %r14
cmpl $0, -1048788(%rbp)
jle .L55
jmp .L54
.L101:
movl -1048788(%rbp), %r8d
movl $55, %ecx
movl $171, %edx
movq -1048752(%rbp), %rsi
movq -1048760(%rbp), %rdi
call _Z31__device_stub__Z7encryptPcS_iiiPcS_iii
jmp .L58
.L102:
movl -1048788(%rbp), %r8d
movl $91, %ecx
movl $3, %edx
movq -1048744(%rbp), %rsi
movq -1048752(%rbp), %rdi
call _Z31__device_stub__Z7decryptPcS_iiiPcS_iii
jmp .L59
.L103:
movl -1048788(%rbp), %ecx
movq -1048736(%rbp), %rdx
movq -1048760(%rbp), %rsi
movq -1048744(%rbp), %rdi
call _Z31__device_stub__Z7isMatchPcS_PiiPcS_Pii
jmp .L60
.L61:
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L62
.L66:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L67
orq $0, -8(%rsp,%rax)
.L67:
movq %rsp, %r15
leaq 15(%rbx), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L68:
cmpq %rdx, %rsp
je .L69
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L68
.L69:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L70
orq $0, -8(%rsp,%rax)
.L70:
movq %rsp, %r13
leaq 15(%rbx), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L71:
cmpq %rdx, %rsp
je .L72
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L71
.L72:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L73
orq $0, -8(%rsp,%rax)
.L73:
movq %rsp, %r14
.L54:
movl $0, %eax
.L57:
movzbl (%r12,%rax), %edx
movb %dl, (%r15,%rax)
movb $32, 0(%r13,%rax)
movb $32, (%r14,%rax)
addq $1, %rax
cmpq %rbx, %rax
jne .L57
.L55:
movl $0, -1048780(%rbp)
leaq -1048728(%rbp), %rdi
call cudaEventCreate@PLT
leaq -1048696(%rbp), %rdi
call cudaEventCreate@PLT
leaq -1048720(%rbp), %rdi
call cudaEventCreate@PLT
leaq -1048688(%rbp), %rdi
call cudaEventCreate@PLT
leaq -1048712(%rbp), %rdi
call cudaEventCreate@PLT
leaq -1048680(%rbp), %rdi
call cudaEventCreate@PLT
leaq -1048704(%rbp), %rdi
call cudaEventCreate@PLT
leaq -1048672(%rbp), %rdi
call cudaEventCreate@PLT
movl $0x00000000, -1048776(%rbp)
movl $0x00000000, -1048772(%rbp)
movl $0x00000000, -1048768(%rbp)
movl $0x00000000, -1048764(%rbp)
movl $4, %edi
call malloc@PLT
movq %rax, -1048736(%rbp)
movl $0, (%rax)
leaq -1048760(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -1048752(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -1048744(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -1048736(%rbp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl -1048788(%rbp), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq -1048760(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq -1048752(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq -1048744(%rbp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq -1048704(%rbp), %rdi
call cudaEventRecord@PLT
movl $0, %esi
movq -1048728(%rbp), %rdi
call cudaEventRecord@PLT
movl $128, -1048652(%rbp)
movl $1, -1048648(%rbp)
movl $1, -1048644(%rbp)
movl $128, -1048664(%rbp)
movl $1, -1048660(%rbp)
movl $1, -1048656(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -1048652(%rbp), %rdx
movl $1, %ecx
movq -1048664(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L101
.L58:
movl $0, %esi
movq -1048696(%rbp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %rbx, %rdx
movq -1048752(%rbp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq -1048696(%rbp), %rdi
call cudaEventSynchronize@PLT
leaq -1048776(%rbp), %rdi
movq -1048696(%rbp), %rdx
movq -1048728(%rbp), %rsi
call cudaEventElapsedTime@PLT
movl $0, %esi
movq -1048688(%rbp), %rdi
call cudaEventRecord@PLT
movl $128, -1048652(%rbp)
movl $1, -1048648(%rbp)
movl $1, -1048644(%rbp)
movl $128, -1048664(%rbp)
movl $1, -1048660(%rbp)
movl $1, -1048656(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -1048652(%rbp), %rdx
movl $1, %ecx
movq -1048664(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L102
.L59:
movl $0, %esi
movq -1048688(%rbp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %rbx, %rdx
movq -1048744(%rbp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq -1048688(%rbp), %rdi
call cudaEventSynchronize@PLT
leaq -1048772(%rbp), %rdi
movq -1048688(%rbp), %rdx
movq -1048720(%rbp), %rsi
call cudaEventElapsedTime@PLT
movl $0, %esi
movq -1048712(%rbp), %rdi
call cudaEventRecord@PLT
movl $128, -1048652(%rbp)
movl $1, -1048648(%rbp)
movl $1, -1048644(%rbp)
movl $128, -1048664(%rbp)
movl $1, -1048660(%rbp)
movl $1, -1048656(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -1048652(%rbp), %rdx
movl $1, %ecx
movq -1048664(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L103
.L60:
movl $0, %esi
movq -1048680(%rbp), %rdi
call cudaEventRecord@PLT
leaq -1048780(%rbp), %rdi
movl $2, %ecx
movl $4, %edx
movq -1048736(%rbp), %rsi
call cudaMemcpy@PLT
cmpl $0, -1048780(%rbp)
je .L61
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L62:
movq -1048680(%rbp), %rdi
call cudaEventSynchronize@PLT
leaq -1048768(%rbp), %rdi
movq -1048680(%rbp), %rdx
movq -1048712(%rbp), %rsi
call cudaEventElapsedTime@PLT
movl $0, %esi
movq -1048672(%rbp), %rdi
call cudaEventRecord@PLT
movq -1048672(%rbp), %rdi
call cudaEventSynchronize@PLT
leaq -1048764(%rbp), %rdi
movq -1048672(%rbp), %rdx
movq -1048704(%rbp), %rsi
call cudaEventElapsedTime@PLT
movss -1048776(%rbp), %xmm0
divss .LC13(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss -1048772(%rbp), %xmm0
divss .LC13(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss -1048768(%rbp), %xmm0
divss .LC13(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss -1048764(%rbp), %xmm0
divss .LC13(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq -1048760(%rbp), %rdi
call cudaFree@PLT
movq -1048752(%rbp), %rdi
call cudaFree@PLT
movq -1048744(%rbp), %rdi
call cudaFree@PLT
movl $0, %eax
.L29:
movq -56(%rbp), %rdx
subq %fs:40, %rdx
jne .L104
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L36:
.cfi_restore_state
movslq -1048788(%rbp), %rbx
leaq 15(%rbx), %rdx
movq %rdx, %rax
andq $-16, %rax
andq $-4096, %rdx
movq %rsp, %rcx
subq %rdx, %rcx
.L74:
cmpq %rcx, %rsp
je .L75
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L74
.L75:
movq %rax, %rdx
andl $4095, %edx
subq %rdx, %rsp
testq %rdx, %rdx
je .L76
orq $0, -8(%rsp,%rdx)
.L76:
movq %rsp, %r15
leaq 15(%rbx), %rdx
movq %rdx, %rax
andq $-16, %rax
andq $-4096, %rdx
movq %rsp, %rcx
subq %rdx, %rcx
.L77:
cmpq %rcx, %rsp
je .L78
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L77
.L78:
movq %rax, %rdx
andl $4095, %edx
subq %rdx, %rsp
testq %rdx, %rdx
je .L79
orq $0, -8(%rsp,%rdx)
.L79:
movq %rsp, %r13
leaq 15(%rbx), %rdx
movq %rdx, %rax
andq $-16, %rax
andq $-4096, %rdx
movq %rsp, %rcx
subq %rdx, %rcx
.L80:
cmpq %rcx, %rsp
je .L81
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L80
.L81:
movq %rax, %rdx
andl $4095, %edx
subq %rdx, %rsp
testq %rdx, %rdx
je .L82
orq $0, -8(%rsp,%rdx)
.L82:
movq %rsp, %r14
jmp .L55
.L104:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC18:
.string "_Z7isMatchPcS_Pii"
.LC19:
.string "_Z7decryptPcS_iii"
.LC20:
.string "_Z7encryptPcS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z7isMatchPcS_Pii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z7decryptPcS_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z7encryptPcS_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1073741824
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC13:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <cuda.h>
/**
* Encrypt Program Cuda
*
* This program encrypts a file using a degree 2 formula using Cuda
* Parallelization and then decrypts the file using another degree 2
* formula.
*
* @Author: Clayton Chase Glenn
*/
#define MAX 20
#define DEBUG 0
/** Kernel Function
* First finds the Thread ID within the block of GPU Threads
* and if the Thread is Correct, it Encrypts the corresponding
* Character in the String.
**/
__global__
void encrypt(char *p, char *c, int a, int b, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < n) c[tid] = (a*p[tid] + b) % 256;
}
/** Kernel Function
* First finds the Thread ID within the block of GPU Threads
* and if the Thread is Correct, it Encrypts the corresponding
* Character in the String.
**/
__global__
void decrypt(char *p, char *c, int a, int b, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < n) c[tid] = (a*p[tid] + b) % 256;
}
/** Kernel Function
* First finds the Thread ID within the block of GPU Threads
* and if the Thread is Correct, it checks if the corresponding
* character in array a matches b.
**/
__global__
void isMatch(char *p, char *c, int *a, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < n) {
if (c[tid] != p[tid]) {
*a = 1;
}
}
}
/**
* Helper Function
* Prints an string to standard error showing help
* for valid arguments in the executable
**/
void printerror(){
fprintf(stderr, "Invalid Arguments\n");
fprintf(stderr, "Correct Form: ./encrypt [File to Encrypt]\n");
fprintf(stderr, " or\n");
fprintf(stderr, " ./encrypt -n [2^(1:20)]\n");
exit(0);
}
/**
* Main Program
* This Program is for Homework 6 to encrypt some text or show
* the encryption method of text that is 2 to the power of N
* characters long all initialized to zero.
**/
int main(int argc, char **argv) {
// Declare a buffer of max size to start
int N = MAX;
char *buf;
// Check for immediate errors in args
if (argc < 2) printerror();
if (argc == 3 && strcmp(argv[1], "-n")) printerror();
// If args match for testing, Initiallize the program
if(!strcmp(argv[1], "-n") && argc == 3){
// Get total characters from args
N = strtol(argv[2], NULL, 10);
// Show error if N isn't within constraints
if(N < 1 || N > 20) printerror();
// N <- calc to 2^N as size and allocate space
N = (int)pow(2, N);
buf = (char*)malloc(N*sizeof(char));
//Initiallize the buffer to Zero
int i = 0;
while (i < N) buf[i++] = 48;
}
// If 2 args, this means file
if(argc == 2) {
// Declare a file pointer, character array, and single character for reading
FILE *fp;
char c;
char chars[1048576];
int i = 0;
// Open the file for reading
fp = fopen(argv[1], "r");
// If file is null, file does not exist or error
if (fp == NULL) {
fprintf(stderr, "Not a Valid File\n");
return (-1);
}
// Read each character and keep within 2^20, add to array
while((c = fgetc(fp)) != EOF) {
if (i >= 1048576) {
fprintf(stderr, "File Too Large\n");
return (-1);
}
chars[i++] = c;
}
// Increment i for space and allocate space for buffer
N = i + 1;
buf = (char*)malloc(N*sizeof(char));
// Copy read elements into buffer
i = 0;
while(i < N) buf[i] = chars[i++];
// Close File, not needed anymore
fclose(fp);
}
// Initiallize Character Arrays for Encrypting and manual memset
char h_p[N];
char h_c[N];
char h_r[N];
int i = 0;
while (i < N) {
h_p[i] = buf[i];
h_c[i] = 32;
h_r[i++] = 32;
}
// Init all other variables
char *dev_p, *dev_c, *dev_r;
int *match;
int h_match = 0;
int h_a = 171, h_b = 55;
int r_a = 3, r_b = 91;
cudaEvent_t start1, start2, start3, startf, stop1, stop2, stop3, stopf;
cudaEventCreate(&start1);
cudaEventCreate(&stop1);
cudaEventCreate(&start2);
cudaEventCreate(&stop2);
cudaEventCreate(&start3);
cudaEventCreate(&stop3);
cudaEventCreate(&startf);
cudaEventCreate(&stopf);
float final_time1 = 0.0, final_time2 = 0.0, final_time3 = 0.0, final_timef = 0.0;
// Allocate Memory for match flag
match = (int*)malloc(sizeof(int));
*match = 0;
// Allocate memory in the GPU for the character arrays
cudaMalloc(&dev_p, N*sizeof(char));
cudaMalloc(&dev_c, N*sizeof(char));
cudaMalloc(&dev_r, N*sizeof(char));
cudaMalloc(&match, sizeof(int));
// Print N for distinguish
printf("N: %d\n", N);
// If debug on, show plain text
if(DEBUG) {
printf("Plain Text: ");
i = 0;
while(i < N) printf("%c", h_p[i++]);
printf("\n");
}
// Copy the Memory from the arrays to the array pointers
cudaMemcpy(dev_p, h_p, N*sizeof(char), cudaMemcpyHostToDevice);
cudaMemcpy(dev_c, h_c, N*sizeof(char), cudaMemcpyHostToDevice);
cudaMemcpy(dev_r, h_r, N*sizeof(char), cudaMemcpyHostToDevice);
// Start Total Time Record
cudaEventRecord(startf);
// Encrypt the Plain Text and Record Start and Finish
cudaEventRecord(start1);
encrypt<<<128, 128>>>(dev_p, dev_c, h_a, h_b, N);
cudaEventRecord(stop1);
// Copy the results from GPU to the CPU
cudaMemcpy(h_c, dev_c, N*sizeof(char), cudaMemcpyDeviceToHost);
// If debug on, show encrypted text
if(DEBUG) {
printf("Encrypted Text: ");
i = 0;
while(i < N) printf("%c", h_c[i++]);
printf("\n");
}
// Syncronize all blocks and threads in GPU and get time
cudaEventSynchronize(stop1);
cudaEventElapsedTime(&final_time1, start1, stop1);
// Decrypt the Encrypted Text
cudaEventRecord(stop2);
decrypt<<<128, 128>>>(dev_c, dev_r, r_a, r_b, N);
cudaEventRecord(stop2);
// Copy the results from GPU to CPU
cudaMemcpy(h_r, dev_r, N*sizeof(char), cudaMemcpyDeviceToHost);
// If debug on, show decrypted text
if(DEBUG) {
printf("Decrypted Text: ", h_r);
i = 0;
while(i < N) printf("%c", h_r[i++]);
printf("\n");
}
// Syncronize all blocks and threads in GPU and get time
cudaEventSynchronize(stop2);
cudaEventElapsedTime(&final_time2, start2, stop2);
// Check if Plain Text and Encrypt<-->Decrypt Text is matching by GPU
cudaEventRecord(start3);
isMatch<<<128, 128>>>(dev_r, dev_p, match, N);
cudaEventRecord(stop3);
// Copy the Match Result from GPU to CPU
cudaMemcpy(&h_match, match, sizeof(int), cudaMemcpyDeviceToHost);
// If match is zero, success, else, no success
if (h_match) fprintf(stdout, "Does not Match\n");
else fprintf(stdout, "Does Match\n");
// Syncronize all blocks and threads in GPU and get time
cudaEventSynchronize(stop3);
cudaEventElapsedTime(&final_time3, start3, stop3);
// Syncronize all blocks and threads in GPU and get time
cudaEventRecord(stopf);
cudaEventSynchronize(stopf);
cudaEventElapsedTime(&final_timef, startf, stopf);
// Print Times
printf("Encrypt Time: %4.10f seconds\n", final_time1/1000);
printf("Decrypt Time: %4.10f seconds\n", final_time2/1000);
printf("Match Time: %4.10f seconds\n", final_time3/1000);
printf("Total Time: %4.10f seconds\n\n", final_timef/1000);
// Free the GPU memory
cudaFree(dev_p);
cudaFree(dev_c);
cudaFree(dev_r);
} | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <hip/hip_runtime.h>
/**
* Encrypt Program Cuda
*
* This program encrypts a file using a degree 2 formula using Cuda
* Parallelization and then decrypts the file using another degree 2
* formula.
*
* @Author: Clayton Chase Glenn
*/
#define MAX 20
#define DEBUG 0
/** Kernel Function
* First finds the Thread ID within the block of GPU Threads
* and if the Thread is Correct, it Encrypts the corresponding
* Character in the String.
**/
__global__
void encrypt(char *p, char *c, int a, int b, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < n) c[tid] = (a*p[tid] + b) % 256;
}
/** Kernel Function
* First finds the Thread ID within the block of GPU Threads
* and if the Thread is Correct, it Encrypts the corresponding
* Character in the String.
**/
__global__
void decrypt(char *p, char *c, int a, int b, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < n) c[tid] = (a*p[tid] + b) % 256;
}
/** Kernel Function
* First finds the Thread ID within the block of GPU Threads
* and if the Thread is Correct, it checks if the corresponding
* character in array a matches b.
**/
__global__
void isMatch(char *p, char *c, int *a, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < n) {
if (c[tid] != p[tid]) {
*a = 1;
}
}
}
/**
* Helper Function
* Prints an string to standard error showing help
* for valid arguments in the executable
**/
void printerror(){
fprintf(stderr, "Invalid Arguments\n");
fprintf(stderr, "Correct Form: ./encrypt [File to Encrypt]\n");
fprintf(stderr, " or\n");
fprintf(stderr, " ./encrypt -n [2^(1:20)]\n");
exit(0);
}
/**
* Main Program
* This Program is for Homework 6 to encrypt some text or show
* the encryption method of text that is 2 to the power of N
* characters long all initialized to zero.
**/
int main(int argc, char **argv) {
// Declare a buffer of max size to start
int N = MAX;
char *buf;
// Check for immediate errors in args
if (argc < 2) printerror();
if (argc == 3 && strcmp(argv[1], "-n")) printerror();
// If args match for testing, Initiallize the program
if(!strcmp(argv[1], "-n") && argc == 3){
// Get total characters from args
N = strtol(argv[2], NULL, 10);
// Show error if N isn't within constraints
if(N < 1 || N > 20) printerror();
// N <- calc to 2^N as size and allocate space
N = (int)pow(2, N);
buf = (char*)malloc(N*sizeof(char));
//Initiallize the buffer to Zero
int i = 0;
while (i < N) buf[i++] = 48;
}
// If 2 args, this means file
if(argc == 2) {
// Declare a file pointer, character array, and single character for reading
FILE *fp;
char c;
char chars[1048576];
int i = 0;
// Open the file for reading
fp = fopen(argv[1], "r");
// If file is null, file does not exist or error
if (fp == NULL) {
fprintf(stderr, "Not a Valid File\n");
return (-1);
}
// Read each character and keep within 2^20, add to array
while((c = fgetc(fp)) != EOF) {
if (i >= 1048576) {
fprintf(stderr, "File Too Large\n");
return (-1);
}
chars[i++] = c;
}
// Increment i for space and allocate space for buffer
N = i + 1;
buf = (char*)malloc(N*sizeof(char));
// Copy read elements into buffer
i = 0;
while(i < N) buf[i] = chars[i++];
// Close File, not needed anymore
fclose(fp);
}
// Initiallize Character Arrays for Encrypting and manual memset
char h_p[N];
char h_c[N];
char h_r[N];
int i = 0;
while (i < N) {
h_p[i] = buf[i];
h_c[i] = 32;
h_r[i++] = 32;
}
// Init all other variables
char *dev_p, *dev_c, *dev_r;
int *match;
int h_match = 0;
int h_a = 171, h_b = 55;
int r_a = 3, r_b = 91;
hipEvent_t start1, start2, start3, startf, stop1, stop2, stop3, stopf;
hipEventCreate(&start1);
hipEventCreate(&stop1);
hipEventCreate(&start2);
hipEventCreate(&stop2);
hipEventCreate(&start3);
hipEventCreate(&stop3);
hipEventCreate(&startf);
hipEventCreate(&stopf);
float final_time1 = 0.0, final_time2 = 0.0, final_time3 = 0.0, final_timef = 0.0;
// Allocate Memory for match flag
match = (int*)malloc(sizeof(int));
*match = 0;
// Allocate memory in the GPU for the character arrays
hipMalloc(&dev_p, N*sizeof(char));
hipMalloc(&dev_c, N*sizeof(char));
hipMalloc(&dev_r, N*sizeof(char));
hipMalloc(&match, sizeof(int));
// Print N for distinguish
printf("N: %d\n", N);
// If debug on, show plain text
if(DEBUG) {
printf("Plain Text: ");
i = 0;
while(i < N) printf("%c", h_p[i++]);
printf("\n");
}
// Copy the Memory from the arrays to the array pointers
hipMemcpy(dev_p, h_p, N*sizeof(char), hipMemcpyHostToDevice);
hipMemcpy(dev_c, h_c, N*sizeof(char), hipMemcpyHostToDevice);
hipMemcpy(dev_r, h_r, N*sizeof(char), hipMemcpyHostToDevice);
// Start Total Time Record
hipEventRecord(startf);
// Encrypt the Plain Text and Record Start and Finish
hipEventRecord(start1);
encrypt<<<128, 128>>>(dev_p, dev_c, h_a, h_b, N);
hipEventRecord(stop1);
// Copy the results from GPU to the CPU
hipMemcpy(h_c, dev_c, N*sizeof(char), hipMemcpyDeviceToHost);
// If debug on, show encrypted text
if(DEBUG) {
printf("Encrypted Text: ");
i = 0;
while(i < N) printf("%c", h_c[i++]);
printf("\n");
}
// Syncronize all blocks and threads in GPU and get time
hipEventSynchronize(stop1);
hipEventElapsedTime(&final_time1, start1, stop1);
// Decrypt the Encrypted Text
hipEventRecord(stop2);
decrypt<<<128, 128>>>(dev_c, dev_r, r_a, r_b, N);
hipEventRecord(stop2);
// Copy the results from GPU to CPU
hipMemcpy(h_r, dev_r, N*sizeof(char), hipMemcpyDeviceToHost);
// If debug on, show decrypted text
if(DEBUG) {
printf("Decrypted Text: ", h_r);
i = 0;
while(i < N) printf("%c", h_r[i++]);
printf("\n");
}
// Syncronize all blocks and threads in GPU and get time
hipEventSynchronize(stop2);
hipEventElapsedTime(&final_time2, start2, stop2);
// Check if Plain Text and Encrypt<-->Decrypt Text is matching by GPU
hipEventRecord(start3);
isMatch<<<128, 128>>>(dev_r, dev_p, match, N);
hipEventRecord(stop3);
// Copy the Match Result from GPU to CPU
hipMemcpy(&h_match, match, sizeof(int), hipMemcpyDeviceToHost);
// If match is zero, success, else, no success
if (h_match) fprintf(stdout, "Does not Match\n");
else fprintf(stdout, "Does Match\n");
// Syncronize all blocks and threads in GPU and get time
hipEventSynchronize(stop3);
hipEventElapsedTime(&final_time3, start3, stop3);
// Syncronize all blocks and threads in GPU and get time
hipEventRecord(stopf);
hipEventSynchronize(stopf);
hipEventElapsedTime(&final_timef, startf, stopf);
// Print Times
printf("Encrypt Time: %4.10f seconds\n", final_time1/1000);
printf("Decrypt Time: %4.10f seconds\n", final_time2/1000);
printf("Match Time: %4.10f seconds\n", final_time3/1000);
printf("Total Time: %4.10f seconds\n\n", final_timef/1000);
// Free the GPU memory
hipFree(dev_p);
hipFree(dev_c);
hipFree(dev_r);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <hip/hip_runtime.h>
/**
* Encrypt Program Cuda
*
* This program encrypts a file using a degree 2 formula using Cuda
* Parallelization and then decrypts the file using another degree 2
* formula.
*
* @Author: Clayton Chase Glenn
*/
#define MAX 20
#define DEBUG 0
/** Kernel Function
* First finds the Thread ID within the block of GPU Threads
* and if the Thread is Correct, it Encrypts the corresponding
* Character in the String.
**/
__global__
void encrypt(char *p, char *c, int a, int b, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < n) c[tid] = (a*p[tid] + b) % 256;
}
/** Kernel Function
* First finds the Thread ID within the block of GPU Threads
* and if the Thread is Correct, it Encrypts the corresponding
* Character in the String.
**/
__global__
void decrypt(char *p, char *c, int a, int b, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < n) c[tid] = (a*p[tid] + b) % 256;
}
/** Kernel Function
* First finds the Thread ID within the block of GPU Threads
* and if the Thread is Correct, it checks if the corresponding
* character in array a matches b.
**/
__global__
void isMatch(char *p, char *c, int *a, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < n) {
if (c[tid] != p[tid]) {
*a = 1;
}
}
}
/**
* Helper Function
* Prints an string to standard error showing help
* for valid arguments in the executable
**/
void printerror(){
fprintf(stderr, "Invalid Arguments\n");
fprintf(stderr, "Correct Form: ./encrypt [File to Encrypt]\n");
fprintf(stderr, " or\n");
fprintf(stderr, " ./encrypt -n [2^(1:20)]\n");
exit(0);
}
/**
* Main Program
* This Program is for Homework 6 to encrypt some text or show
* the encryption method of text that is 2 to the power of N
* characters long all initialized to zero.
**/
int main(int argc, char **argv) {
// Declare a buffer of max size to start
int N = MAX;
char *buf;
// Check for immediate errors in args
if (argc < 2) printerror();
if (argc == 3 && strcmp(argv[1], "-n")) printerror();
// If args match for testing, Initiallize the program
if(!strcmp(argv[1], "-n") && argc == 3){
// Get total characters from args
N = strtol(argv[2], NULL, 10);
// Show error if N isn't within constraints
if(N < 1 || N > 20) printerror();
// N <- calc to 2^N as size and allocate space
N = (int)pow(2, N);
buf = (char*)malloc(N*sizeof(char));
//Initiallize the buffer to Zero
int i = 0;
while (i < N) buf[i++] = 48;
}
// If 2 args, this means file
if(argc == 2) {
// Declare a file pointer, character array, and single character for reading
FILE *fp;
char c;
char chars[1048576];
int i = 0;
// Open the file for reading
fp = fopen(argv[1], "r");
// If file is null, file does not exist or error
if (fp == NULL) {
fprintf(stderr, "Not a Valid File\n");
return (-1);
}
// Read each character and keep within 2^20, add to array
while((c = fgetc(fp)) != EOF) {
if (i >= 1048576) {
fprintf(stderr, "File Too Large\n");
return (-1);
}
chars[i++] = c;
}
// Increment i for space and allocate space for buffer
N = i + 1;
buf = (char*)malloc(N*sizeof(char));
// Copy read elements into buffer
i = 0;
while(i < N) buf[i] = chars[i++];
// Close File, not needed anymore
fclose(fp);
}
// Initiallize Character Arrays for Encrypting and manual memset
char h_p[N];
char h_c[N];
char h_r[N];
int i = 0;
while (i < N) {
h_p[i] = buf[i];
h_c[i] = 32;
h_r[i++] = 32;
}
// Init all other variables
char *dev_p, *dev_c, *dev_r;
int *match;
int h_match = 0;
int h_a = 171, h_b = 55;
int r_a = 3, r_b = 91;
hipEvent_t start1, start2, start3, startf, stop1, stop2, stop3, stopf;
hipEventCreate(&start1);
hipEventCreate(&stop1);
hipEventCreate(&start2);
hipEventCreate(&stop2);
hipEventCreate(&start3);
hipEventCreate(&stop3);
hipEventCreate(&startf);
hipEventCreate(&stopf);
float final_time1 = 0.0, final_time2 = 0.0, final_time3 = 0.0, final_timef = 0.0;
// Allocate Memory for match flag
match = (int*)malloc(sizeof(int));
*match = 0;
// Allocate memory in the GPU for the character arrays
hipMalloc(&dev_p, N*sizeof(char));
hipMalloc(&dev_c, N*sizeof(char));
hipMalloc(&dev_r, N*sizeof(char));
hipMalloc(&match, sizeof(int));
// Print N for distinguish
printf("N: %d\n", N);
// If debug on, show plain text
if(DEBUG) {
printf("Plain Text: ");
i = 0;
while(i < N) printf("%c", h_p[i++]);
printf("\n");
}
// Copy the Memory from the arrays to the array pointers
hipMemcpy(dev_p, h_p, N*sizeof(char), hipMemcpyHostToDevice);
hipMemcpy(dev_c, h_c, N*sizeof(char), hipMemcpyHostToDevice);
hipMemcpy(dev_r, h_r, N*sizeof(char), hipMemcpyHostToDevice);
// Start Total Time Record
hipEventRecord(startf);
// Encrypt the Plain Text and Record Start and Finish
hipEventRecord(start1);
encrypt<<<128, 128>>>(dev_p, dev_c, h_a, h_b, N);
hipEventRecord(stop1);
// Copy the results from GPU to the CPU
hipMemcpy(h_c, dev_c, N*sizeof(char), hipMemcpyDeviceToHost);
// If debug on, show encrypted text
if(DEBUG) {
printf("Encrypted Text: ");
i = 0;
while(i < N) printf("%c", h_c[i++]);
printf("\n");
}
// Syncronize all blocks and threads in GPU and get time
hipEventSynchronize(stop1);
hipEventElapsedTime(&final_time1, start1, stop1);
// Decrypt the Encrypted Text
hipEventRecord(stop2);
decrypt<<<128, 128>>>(dev_c, dev_r, r_a, r_b, N);
hipEventRecord(stop2);
// Copy the results from GPU to CPU
hipMemcpy(h_r, dev_r, N*sizeof(char), hipMemcpyDeviceToHost);
// If debug on, show decrypted text
if(DEBUG) {
printf("Decrypted Text: ", h_r);
i = 0;
while(i < N) printf("%c", h_r[i++]);
printf("\n");
}
// Syncronize all blocks and threads in GPU and get time
hipEventSynchronize(stop2);
hipEventElapsedTime(&final_time2, start2, stop2);
// Check if Plain Text and Encrypt<-->Decrypt Text is matching by GPU
hipEventRecord(start3);
isMatch<<<128, 128>>>(dev_r, dev_p, match, N);
hipEventRecord(stop3);
// Copy the Match Result from GPU to CPU
hipMemcpy(&h_match, match, sizeof(int), hipMemcpyDeviceToHost);
// If match is zero, success, else, no success
if (h_match) fprintf(stdout, "Does not Match\n");
else fprintf(stdout, "Does Match\n");
// Syncronize all blocks and threads in GPU and get time
hipEventSynchronize(stop3);
hipEventElapsedTime(&final_time3, start3, stop3);
// Syncronize all blocks and threads in GPU and get time
hipEventRecord(stopf);
hipEventSynchronize(stopf);
hipEventElapsedTime(&final_timef, startf, stopf);
// Print Times
printf("Encrypt Time: %4.10f seconds\n", final_time1/1000);
printf("Decrypt Time: %4.10f seconds\n", final_time2/1000);
printf("Match Time: %4.10f seconds\n", final_time3/1000);
printf("Total Time: %4.10f seconds\n\n", final_timef/1000);
// Free the GPU memory
hipFree(dev_p);
hipFree(dev_c);
hipFree(dev_r);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7encryptPcS_iii
.globl _Z7encryptPcS_iii
.p2align 8
.type _Z7encryptPcS_iii,@function
_Z7encryptPcS_iii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v4, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v4, vcc_lo
s_mov_b32 s2, s1
global_load_u8 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[2:3], null, v0, s0, s[2:3]
v_add_co_u32 v0, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v4, vcc_lo
global_store_b8 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7encryptPcS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7encryptPcS_iii, .Lfunc_end0-_Z7encryptPcS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7decryptPcS_iii
.globl _Z7decryptPcS_iii
.p2align 8
.type _Z7decryptPcS_iii,@function
_Z7decryptPcS_iii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v4, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v4, vcc_lo
s_mov_b32 s2, s1
global_load_u8 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[2:3], null, v0, s0, s[2:3]
v_add_co_u32 v0, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v4, vcc_lo
global_store_b8 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7decryptPcS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7decryptPcS_iii, .Lfunc_end1-_Z7decryptPcS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7isMatchPcS_Pii
.globl _Z7isMatchPcS_Pii
.p2align 8
.type _Z7isMatchPcS_Pii,@function
_Z7isMatchPcS_Pii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB2_3
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v4, 31, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v4, vcc_lo
global_load_u8 v2, v[2:3], off
global_load_u8 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_ne_u16_e32 vcc_lo, v2, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_3
s_load_b64 s[0:1], s[0:1], 0x10
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB2_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7isMatchPcS_Pii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z7isMatchPcS_Pii, .Lfunc_end2-_Z7isMatchPcS_Pii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7encryptPcS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7encryptPcS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7decryptPcS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7decryptPcS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7isMatchPcS_Pii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7isMatchPcS_Pii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
#include <hip/hip_runtime.h>
/**
* Encrypt Program Cuda
*
* This program encrypts a file using a degree 2 formula using Cuda
* Parallelization and then decrypts the file using another degree 2
* formula.
*
* @Author: Clayton Chase Glenn
*/
#define MAX 20
#define DEBUG 0
/** Kernel Function
* First finds the Thread ID within the block of GPU Threads
* and if the Thread is Correct, it Encrypts the corresponding
* Character in the String.
**/
__global__
void encrypt(char *p, char *c, int a, int b, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < n) c[tid] = (a*p[tid] + b) % 256;
}
/** Kernel Function
* First finds the Thread ID within the block of GPU Threads
* and if the Thread is Correct, it Encrypts the corresponding
* Character in the String.
**/
__global__
void decrypt(char *p, char *c, int a, int b, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < n) c[tid] = (a*p[tid] + b) % 256;
}
/** Kernel Function
* First finds the Thread ID within the block of GPU Threads
* and if the Thread is Correct, it checks if the corresponding
* character in array a matches b.
**/
__global__
void isMatch(char *p, char *c, int *a, int n) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < n) {
if (c[tid] != p[tid]) {
*a = 1;
}
}
}
/**
* Helper Function
* Prints an string to standard error showing help
* for valid arguments in the executable
**/
void printerror(){
fprintf(stderr, "Invalid Arguments\n");
fprintf(stderr, "Correct Form: ./encrypt [File to Encrypt]\n");
fprintf(stderr, " or\n");
fprintf(stderr, " ./encrypt -n [2^(1:20)]\n");
exit(0);
}
/**
* Main Program
* This Program is for Homework 6 to encrypt some text or show
* the encryption method of text that is 2 to the power of N
* characters long all initialized to zero.
**/
int main(int argc, char **argv) {
// Declare a buffer of max size to start
int N = MAX;
char *buf;
// Check for immediate errors in args
if (argc < 2) printerror();
if (argc == 3 && strcmp(argv[1], "-n")) printerror();
// If args match for testing, Initiallize the program
if(!strcmp(argv[1], "-n") && argc == 3){
// Get total characters from args
N = strtol(argv[2], NULL, 10);
// Show error if N isn't within constraints
if(N < 1 || N > 20) printerror();
// N <- calc to 2^N as size and allocate space
N = (int)pow(2, N);
buf = (char*)malloc(N*sizeof(char));
//Initiallize the buffer to Zero
int i = 0;
while (i < N) buf[i++] = 48;
}
// If 2 args, this means file
if(argc == 2) {
// Declare a file pointer, character array, and single character for reading
FILE *fp;
char c;
char chars[1048576];
int i = 0;
// Open the file for reading
fp = fopen(argv[1], "r");
// If file is null, file does not exist or error
if (fp == NULL) {
fprintf(stderr, "Not a Valid File\n");
return (-1);
}
// Read each character and keep within 2^20, add to array
while((c = fgetc(fp)) != EOF) {
if (i >= 1048576) {
fprintf(stderr, "File Too Large\n");
return (-1);
}
chars[i++] = c;
}
// Increment i for space and allocate space for buffer
N = i + 1;
buf = (char*)malloc(N*sizeof(char));
// Copy read elements into buffer
i = 0;
while(i < N) buf[i] = chars[i++];
// Close File, not needed anymore
fclose(fp);
}
// Initiallize Character Arrays for Encrypting and manual memset
char h_p[N];
char h_c[N];
char h_r[N];
int i = 0;
while (i < N) {
h_p[i] = buf[i];
h_c[i] = 32;
h_r[i++] = 32;
}
// Init all other variables
char *dev_p, *dev_c, *dev_r;
int *match;
int h_match = 0;
int h_a = 171, h_b = 55;
int r_a = 3, r_b = 91;
hipEvent_t start1, start2, start3, startf, stop1, stop2, stop3, stopf;
hipEventCreate(&start1);
hipEventCreate(&stop1);
hipEventCreate(&start2);
hipEventCreate(&stop2);
hipEventCreate(&start3);
hipEventCreate(&stop3);
hipEventCreate(&startf);
hipEventCreate(&stopf);
float final_time1 = 0.0, final_time2 = 0.0, final_time3 = 0.0, final_timef = 0.0;
// Allocate Memory for match flag
match = (int*)malloc(sizeof(int));
*match = 0;
// Allocate memory in the GPU for the character arrays
hipMalloc(&dev_p, N*sizeof(char));
hipMalloc(&dev_c, N*sizeof(char));
hipMalloc(&dev_r, N*sizeof(char));
hipMalloc(&match, sizeof(int));
// Print N for distinguish
printf("N: %d\n", N);
// If debug on, show plain text
if(DEBUG) {
printf("Plain Text: ");
i = 0;
while(i < N) printf("%c", h_p[i++]);
printf("\n");
}
// Copy the Memory from the arrays to the array pointers
hipMemcpy(dev_p, h_p, N*sizeof(char), hipMemcpyHostToDevice);
hipMemcpy(dev_c, h_c, N*sizeof(char), hipMemcpyHostToDevice);
hipMemcpy(dev_r, h_r, N*sizeof(char), hipMemcpyHostToDevice);
// Start Total Time Record
hipEventRecord(startf);
// Encrypt the Plain Text and Record Start and Finish
hipEventRecord(start1);
encrypt<<<128, 128>>>(dev_p, dev_c, h_a, h_b, N);
hipEventRecord(stop1);
// Copy the results from GPU to the CPU
hipMemcpy(h_c, dev_c, N*sizeof(char), hipMemcpyDeviceToHost);
// If debug on, show encrypted text
if(DEBUG) {
printf("Encrypted Text: ");
i = 0;
while(i < N) printf("%c", h_c[i++]);
printf("\n");
}
// Syncronize all blocks and threads in GPU and get time
hipEventSynchronize(stop1);
hipEventElapsedTime(&final_time1, start1, stop1);
// Decrypt the Encrypted Text
hipEventRecord(stop2);
decrypt<<<128, 128>>>(dev_c, dev_r, r_a, r_b, N);
hipEventRecord(stop2);
// Copy the results from GPU to CPU
hipMemcpy(h_r, dev_r, N*sizeof(char), hipMemcpyDeviceToHost);
// If debug on, show decrypted text
if(DEBUG) {
printf("Decrypted Text: ", h_r);
i = 0;
while(i < N) printf("%c", h_r[i++]);
printf("\n");
}
// Syncronize all blocks and threads in GPU and get time
hipEventSynchronize(stop2);
hipEventElapsedTime(&final_time2, start2, stop2);
// Check if Plain Text and Encrypt<-->Decrypt Text is matching by GPU
hipEventRecord(start3);
isMatch<<<128, 128>>>(dev_r, dev_p, match, N);
hipEventRecord(stop3);
// Copy the Match Result from GPU to CPU
hipMemcpy(&h_match, match, sizeof(int), hipMemcpyDeviceToHost);
// If match is zero, success, else, no success
if (h_match) fprintf(stdout, "Does not Match\n");
else fprintf(stdout, "Does Match\n");
// Syncronize all blocks and threads in GPU and get time
hipEventSynchronize(stop3);
hipEventElapsedTime(&final_time3, start3, stop3);
// Syncronize all blocks and threads in GPU and get time
hipEventRecord(stopf);
hipEventSynchronize(stopf);
hipEventElapsedTime(&final_timef, startf, stopf);
// Print Times
printf("Encrypt Time: %4.10f seconds\n", final_time1/1000);
printf("Decrypt Time: %4.10f seconds\n", final_time2/1000);
printf("Match Time: %4.10f seconds\n", final_time3/1000);
printf("Total Time: %4.10f seconds\n\n", final_timef/1000);
// Free the GPU memory
hipFree(dev_p);
hipFree(dev_c);
hipFree(dev_r);
} | .text
.file "Encrypt_CUDA.hip"
.globl _Z22__device_stub__encryptPcS_iii # -- Begin function _Z22__device_stub__encryptPcS_iii
.p2align 4, 0x90
.type _Z22__device_stub__encryptPcS_iii,@function
_Z22__device_stub__encryptPcS_iii: # @_Z22__device_stub__encryptPcS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7encryptPcS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__encryptPcS_iii, .Lfunc_end0-_Z22__device_stub__encryptPcS_iii
.cfi_endproc
# -- End function
.globl _Z22__device_stub__decryptPcS_iii # -- Begin function _Z22__device_stub__decryptPcS_iii
.p2align 4, 0x90
.type _Z22__device_stub__decryptPcS_iii,@function
_Z22__device_stub__decryptPcS_iii: # @_Z22__device_stub__decryptPcS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7decryptPcS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z22__device_stub__decryptPcS_iii, .Lfunc_end1-_Z22__device_stub__decryptPcS_iii
.cfi_endproc
# -- End function
.globl _Z22__device_stub__isMatchPcS_Pii # -- Begin function _Z22__device_stub__isMatchPcS_Pii
.p2align 4, 0x90
.type _Z22__device_stub__isMatchPcS_Pii,@function
_Z22__device_stub__isMatchPcS_Pii: # @_Z22__device_stub__isMatchPcS_Pii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7isMatchPcS_Pii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z22__device_stub__isMatchPcS_Pii, .Lfunc_end2-_Z22__device_stub__isMatchPcS_Pii
.cfi_endproc
# -- End function
.globl _Z10printerrorv # -- Begin function _Z10printerrorv
.p2align 4, 0x90
.type _Z10printerrorv,@function
_Z10printerrorv: # @_Z10printerrorv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $18, %esi
movl $1, %edx
callq fwrite@PLT
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $42, %esi
movl $1, %edx
callq fwrite@PLT
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $17, %esi
movl $1, %edx
callq fwrite@PLT
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $38, %esi
movl $1, %edx
callq fwrite@PLT
xorl %edi, %edi
callq exit
.Lfunc_end3:
.size _Z10printerrorv, .Lfunc_end3-_Z10printerrorv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x3ff0000000000000 # double 1
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI4_1:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $1048808, %rsp # imm = 0x1000E8
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
cmpl $1, %edi
jle .LBB4_33
# %bb.1:
movq %rsi, %rbx
movl %edi, %r14d
cmpl $3, %edi
jne .LBB4_3
# %bb.2:
movq 8(%rbx), %rdi
movl $.L.str.4, %esi
callq strcmp
testl %eax, %eax
jne .LBB4_33
.LBB4_3:
movq 8(%rbx), %rdi
movl $.L.str.4, %esi
callq strcmp
movl $20, %r13d
# implicit-def: $r15
cmpl $3, %r14d
jne .LBB4_8
# %bb.4:
testl %eax, %eax
jne .LBB4_8
# %bb.5:
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
leal -21(%rax), %ecx
cmpl $-21, %ecx
jbe .LBB4_33
# %bb.6:
movsd .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero
movl %eax, %edi
callq ldexp@PLT
cvttsd2si %xmm0, %r13d
movslq %r13d, %r12
movq %r12, %rdi
callq malloc
movq %rax, %r15
testl %r12d, %r12d
jle .LBB4_8
# %bb.7: # %.lr.ph.preheader
movl %r13d, %edx
movq %r15, %rdi
movl $48, %esi
callq memset@PLT
.LBB4_8: # %.loopexit
xorl %r12d, %r12d
cmpl $2, %r14d
jne .LBB4_19
# %bb.9:
movq 8(%rbx), %rdi
movl $.L.str.5, %esi
callq fopen
testq %rax, %rax
je .LBB4_14
# %bb.10: # %.preheader
movq %rax, %rbx
movq %rax, %rdi
callq fgetc
xorl %r12d, %r12d
movl $0, %r14d
cmpb $-1, %al
je .LBB4_17
# %bb.11: # %.lr.ph123.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_12: # %.lr.ph123
# =>This Inner Loop Header: Depth=1
cmpq $1048576, %r14 # imm = 0x100000
je .LBB4_13
# %bb.16: # in Loop: Header=BB4_12 Depth=1
movb %al, -1048848(%rbp,%r14)
incq %r14
movq %rbx, %rdi
callq fgetc
cmpb $-1, %al
jne .LBB4_12
.LBB4_17: # %._crit_edge
leal 1(%r14), %r13d
movq %r13, %rdi
callq malloc
movq %rax, %r15
leaq 1(%rax), %rdi
movl %r14d, %edx
incq %rdx
leaq -1048848(%rbp), %rsi
callq memcpy@PLT
movq %rbx, %rdi
callq fclose
movb $1, %al
testb %al, %al
je .LBB4_32
.LBB4_19:
movl %r12d, -220(%rbp) # 4-byte Spill
movq %rsp, -256(%rbp) # 8-byte Spill
movl %r13d, %eax
movq %rsp, %r14
leaq 15(%rax), %rcx
andq $-16, %rcx
subq %rcx, %r14
movq %r14, %rsp
movq %rsp, %rbx
subq %rcx, %rbx
movq %rbx, %rsp
movq %rsp, %r12
subq %rcx, %r12
movq %r12, %rsp
testl %r13d, %r13d
jle .LBB4_22
# %bb.20: # %.lr.ph127.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_21: # %.lr.ph127
# =>This Inner Loop Header: Depth=1
movzbl (%r15,%rcx), %edx
movb %dl, (%r14,%rcx)
movb $32, (%rbx,%rcx)
movb $32, (%r12,%rcx)
incq %rcx
cmpq %rcx, %rax
jne .LBB4_21
.LBB4_22: # %._crit_edge128
movl $0, -156(%rbp)
leaq -248(%rbp), %rdi
callq hipEventCreate
leaq -208(%rbp), %rdi
callq hipEventCreate
leaq -264(%rbp), %rdi
callq hipEventCreate
leaq -168(%rbp), %rdi
callq hipEventCreate
leaq -240(%rbp), %rdi
callq hipEventCreate
leaq -200(%rbp), %rdi
callq hipEventCreate
leaq -232(%rbp), %rdi
callq hipEventCreate
leaq -192(%rbp), %rdi
callq hipEventCreate
movl $0, -152(%rbp)
movl $0, -148(%rbp)
movl $0, -144(%rbp)
movl $0, -140(%rbp)
movl $4, %edi
callq malloc
movq %rax, -216(%rbp)
movl $0, (%rax)
movslq %r13d, %r15
leaq -176(%rbp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq -64(%rbp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq -56(%rbp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq -216(%rbp), %rdi
movl $4, %esi
callq hipMalloc
movl $.L.str.8, %edi
movq %r13, -184(%rbp) # 8-byte Spill
movl %r13d, %esi
xorl %eax, %eax
callq printf
movq -176(%rbp), %rdi
movq %r14, %rsi
movabsq $4294967424, %r14 # imm = 0x100000080
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq -64(%rbp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq -56(%rbp), %rdi
movq %r12, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq -232(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -248(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r14, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_24
# %bb.23:
movq -176(%rbp), %rax
movq -64(%rbp), %rcx
movq %rax, -136(%rbp)
movq %rcx, -128(%rbp)
movl $171, -72(%rbp)
movl $55, -44(%rbp)
movq -184(%rbp), %rax # 8-byte Reload
movl %eax, -48(%rbp)
leaq -136(%rbp), %rax
movq %rax, -1048848(%rbp)
leaq -128(%rbp), %rax
movq %rax, -1048840(%rbp)
leaq -72(%rbp), %rax
movq %rax, -1048832(%rbp)
leaq -44(%rbp), %rax
movq %rax, -1048824(%rbp)
leaq -48(%rbp), %rax
movq %rax, -1048816(%rbp)
leaq -112(%rbp), %rdi
leaq -96(%rbp), %rsi
leaq -120(%rbp), %rdx
leaq -80(%rbp), %rcx
callq __hipPopCallConfiguration
movq -112(%rbp), %rsi
movl -104(%rbp), %edx
movq -96(%rbp), %rcx
movl -88(%rbp), %r8d
leaq -1048848(%rbp), %r9
movl $_Z7encryptPcS_iii, %edi
pushq -80(%rbp)
pushq -120(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB4_24:
movq -208(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -64(%rbp), %rsi
movq %rbx, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq -208(%rbp), %rdi
callq hipEventSynchronize
movq -248(%rbp), %rsi
movq -208(%rbp), %rdx
leaq -152(%rbp), %rdi
callq hipEventElapsedTime
movq -168(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r14, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_26
# %bb.25:
movq -64(%rbp), %rax
movq -56(%rbp), %rcx
movq %rax, -136(%rbp)
movq %rcx, -128(%rbp)
movl $3, -72(%rbp)
movl $91, -44(%rbp)
movq -184(%rbp), %rax # 8-byte Reload
movl %eax, -48(%rbp)
leaq -136(%rbp), %rax
movq %rax, -1048848(%rbp)
leaq -128(%rbp), %rax
movq %rax, -1048840(%rbp)
leaq -72(%rbp), %rax
movq %rax, -1048832(%rbp)
leaq -44(%rbp), %rax
movq %rax, -1048824(%rbp)
leaq -48(%rbp), %rax
movq %rax, -1048816(%rbp)
leaq -112(%rbp), %rdi
leaq -96(%rbp), %rsi
leaq -120(%rbp), %rdx
leaq -80(%rbp), %rcx
callq __hipPopCallConfiguration
movq -112(%rbp), %rsi
movl -104(%rbp), %edx
movq -96(%rbp), %rcx
movl -88(%rbp), %r8d
leaq -1048848(%rbp), %r9
movl $_Z7decryptPcS_iii, %edi
pushq -80(%rbp)
pushq -120(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB4_26:
movq -168(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -56(%rbp), %rsi
movq %r12, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq -168(%rbp), %rdi
callq hipEventSynchronize
movq -264(%rbp), %rsi
movq -168(%rbp), %rdx
leaq -148(%rbp), %rdi
callq hipEventElapsedTime
movq -240(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r14, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_28
# %bb.27:
movq -56(%rbp), %rax
movq -176(%rbp), %rcx
movq -216(%rbp), %rdx
movq %rax, -136(%rbp)
movq %rcx, -128(%rbp)
movq %rdx, -120(%rbp)
movq -184(%rbp), %rax # 8-byte Reload
movl %eax, -44(%rbp)
leaq -136(%rbp), %rax
movq %rax, -1048848(%rbp)
leaq -128(%rbp), %rax
movq %rax, -1048840(%rbp)
leaq -120(%rbp), %rax
movq %rax, -1048832(%rbp)
leaq -44(%rbp), %rax
movq %rax, -1048824(%rbp)
leaq -112(%rbp), %rdi
leaq -96(%rbp), %rsi
leaq -80(%rbp), %rdx
leaq -72(%rbp), %rcx
callq __hipPopCallConfiguration
movq -112(%rbp), %rsi
movl -104(%rbp), %edx
movq -96(%rbp), %rcx
movl -88(%rbp), %r8d
leaq -1048848(%rbp), %r9
movl $_Z7isMatchPcS_Pii, %edi
pushq -72(%rbp)
pushq -80(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB4_28:
movq -200(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -216(%rbp), %rsi
leaq -156(%rbp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
cmpl $0, -156(%rbp)
movq stdout(%rip), %rcx
movl -220(%rbp), %r12d # 4-byte Reload
je .LBB4_30
# %bb.29:
movl $.L.str.9, %edi
movl $15, %esi
jmp .LBB4_31
.LBB4_30:
movl $.L.str.10, %edi
movl $11, %esi
.LBB4_31:
movl $1, %edx
callq fwrite@PLT
movq -200(%rbp), %rdi
callq hipEventSynchronize
movq -240(%rbp), %rsi
movq -200(%rbp), %rdx
leaq -144(%rbp), %rdi
callq hipEventElapsedTime
movq -192(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -192(%rbp), %rdi
callq hipEventSynchronize
movq -232(%rbp), %rsi
movq -192(%rbp), %rdx
leaq -140(%rbp), %rdi
callq hipEventElapsedTime
movss -152(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI4_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.11, %edi
movb $1, %al
callq printf
movss -148(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI4_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.12, %edi
movb $1, %al
callq printf
movss -144(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI4_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.13, %edi
movb $1, %al
callq printf
movss -140(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI4_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.14, %edi
movb $1, %al
callq printf
movq -176(%rbp), %rdi
callq hipFree
movq -64(%rbp), %rdi
callq hipFree
movq -56(%rbp), %rdi
callq hipFree
movq -256(%rbp), %rsp # 8-byte Reload
.LBB4_32:
movl %r12d, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB4_14:
.cfi_def_cfa %rbp, 16
movq stderr(%rip), %rcx
movl $.L.str.6, %edi
movl $17, %esi
jmp .LBB4_15
.LBB4_13:
movq stderr(%rip), %rcx
movl $.L.str.7, %edi
movl $15, %esi
.LBB4_15:
movl $1, %edx
callq fwrite@PLT
movl $-1, %r12d
xorl %eax, %eax
testb %al, %al
jne .LBB4_19
jmp .LBB4_32
.LBB4_33:
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $18, %esi
movl $1, %edx
callq fwrite@PLT
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $42, %esi
movl $1, %edx
callq fwrite@PLT
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $17, %esi
movl $1, %edx
callq fwrite@PLT
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $38, %esi
movl $1, %edx
callq fwrite@PLT
xorl %edi, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7encryptPcS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7decryptPcS_iii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7isMatchPcS_Pii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7encryptPcS_iii,@object # @_Z7encryptPcS_iii
.section .rodata,"a",@progbits
.globl _Z7encryptPcS_iii
.p2align 3, 0x0
_Z7encryptPcS_iii:
.quad _Z22__device_stub__encryptPcS_iii
.size _Z7encryptPcS_iii, 8
.type _Z7decryptPcS_iii,@object # @_Z7decryptPcS_iii
.globl _Z7decryptPcS_iii
.p2align 3, 0x0
_Z7decryptPcS_iii:
.quad _Z22__device_stub__decryptPcS_iii
.size _Z7decryptPcS_iii, 8
.type _Z7isMatchPcS_Pii,@object # @_Z7isMatchPcS_Pii
.globl _Z7isMatchPcS_Pii
.p2align 3, 0x0
_Z7isMatchPcS_Pii:
.quad _Z22__device_stub__isMatchPcS_Pii
.size _Z7isMatchPcS_Pii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Invalid Arguments\n"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Correct Form: ./encrypt [File to Encrypt]\n"
.size .L.str.1, 43
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " or\n"
.size .L.str.2, 18
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " ./encrypt -n [2^(1:20)]\n"
.size .L.str.3, 39
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "-n"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "r"
.size .L.str.5, 2
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Not a Valid File\n"
.size .L.str.6, 18
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "File Too Large\n"
.size .L.str.7, 16
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "N: %d\n"
.size .L.str.8, 7
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Does not Match\n"
.size .L.str.9, 16
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Does Match\n"
.size .L.str.10, 12
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Encrypt Time: %4.10f seconds\n"
.size .L.str.11, 32
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Decrypt Time: %4.10f seconds\n"
.size .L.str.12, 32
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Match Time: %4.10f seconds\n"
.size .L.str.13, 32
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Total Time: %4.10f seconds\n\n"
.size .L.str.14, 33
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7encryptPcS_iii"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7decryptPcS_iii"
.size .L__unnamed_2, 18
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z7isMatchPcS_Pii"
.size .L__unnamed_3, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__encryptPcS_iii
.addrsig_sym _Z22__device_stub__decryptPcS_iii
.addrsig_sym _Z22__device_stub__isMatchPcS_Pii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7encryptPcS_iii
.addrsig_sym _Z7decryptPcS_iii
.addrsig_sym _Z7isMatchPcS_Pii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7isMatchPcS_Pii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ SHF.R.S32.HI R0, RZ, 0x1f, R4 ; /* 0x0000001fff007819 */
/* 0x000fe20000011404 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IADD3 R2, P1, R4.reuse, c[0x0][0x160], RZ ; /* 0x0000580004027a10 */
/* 0x040fe40007f3e0ff */
/*0090*/ IADD3 R4, P0, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fe40007f1e0ff */
/*00a0*/ IADD3.X R3, R0.reuse, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590000037a10 */
/* 0x040fe40000ffe4ff */
/*00b0*/ IADD3.X R5, R0, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0000057a10 */
/* 0x000fc600007fe4ff */
/*00c0*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1100 */
/*00d0*/ LDG.E.U8 R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1100 */
/*00e0*/ ISETP.NE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x004fda0003f05270 */
/*00f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0100*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fe400078e00ff */
/*0110*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe400078e00ff */
/*0120*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fca00078e00ff */
/*0130*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7decryptPcS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ SHF.R.S32.HI R0, RZ, 0x1f, R4 ; /* 0x0000001fff007819 */
/* 0x000fe20000011404 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IADD3 R2, P0, R4, c[0x0][0x160], RZ ; /* 0x0000580004027a10 */
/* 0x000fc80007f1e0ff */
/*0090*/ IADD3.X R3, R0, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000037a10 */
/* 0x000fca00007fe4ff */
/*00a0*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1100 */
/*00b0*/ IADD3 R4, P0, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fe20007f1e0ff */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff077624 */
/* 0x000fc600078e00ff */
/*00d0*/ IADD3.X R5, R0, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0000057a10 */
/* 0x000fe200007fe4ff */
/*00e0*/ IMAD R7, R2, R7, c[0x0][0x174] ; /* 0x00005d0002077624 */
/* 0x004fca00078e0207 */
/*00f0*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101104 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7encryptPcS_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ SHF.R.S32.HI R0, RZ, 0x1f, R4 ; /* 0x0000001fff007819 */
/* 0x000fe20000011404 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IADD3 R2, P0, R4, c[0x0][0x160], RZ ; /* 0x0000580004027a10 */
/* 0x000fc80007f1e0ff */
/*0090*/ IADD3.X R3, R0, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000037a10 */
/* 0x000fca00007fe4ff */
/*00a0*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1100 */
/*00b0*/ IADD3 R4, P0, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fe20007f1e0ff */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff077624 */
/* 0x000fc600078e00ff */
/*00d0*/ IADD3.X R5, R0, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0000057a10 */
/* 0x000fe200007fe4ff */
/*00e0*/ IMAD R7, R2, R7, c[0x0][0x174] ; /* 0x00005d0002077624 */
/* 0x004fca00078e0207 */
/*00f0*/ STG.E.U8 [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101104 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7encryptPcS_iii
.globl _Z7encryptPcS_iii
.p2align 8
.type _Z7encryptPcS_iii,@function
_Z7encryptPcS_iii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v4, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v4, vcc_lo
s_mov_b32 s2, s1
global_load_u8 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[2:3], null, v0, s0, s[2:3]
v_add_co_u32 v0, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v4, vcc_lo
global_store_b8 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7encryptPcS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7encryptPcS_iii, .Lfunc_end0-_Z7encryptPcS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7decryptPcS_iii
.globl _Z7decryptPcS_iii
.p2align 8
.type _Z7decryptPcS_iii,@function
_Z7decryptPcS_iii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v4, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v4, vcc_lo
s_mov_b32 s2, s1
global_load_u8 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[2:3], null, v0, s0, s[2:3]
v_add_co_u32 v0, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v4, vcc_lo
global_store_b8 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7decryptPcS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7decryptPcS_iii, .Lfunc_end1-_Z7decryptPcS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7isMatchPcS_Pii
.globl _Z7isMatchPcS_Pii
.p2align 8
.type _Z7isMatchPcS_Pii,@function
_Z7isMatchPcS_Pii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB2_3
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v4, 31, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v4, vcc_lo
global_load_u8 v2, v[2:3], off
global_load_u8 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_ne_u16_e32 vcc_lo, v2, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_3
s_load_b64 s[0:1], s[0:1], 0x10
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB2_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7isMatchPcS_Pii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z7isMatchPcS_Pii, .Lfunc_end2-_Z7isMatchPcS_Pii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7encryptPcS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7encryptPcS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7decryptPcS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7decryptPcS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7isMatchPcS_Pii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7isMatchPcS_Pii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00099575_00000000-6_Encrypt_CUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Invalid Arguments\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Correct Form: ./encrypt [File to Encrypt]\n"
.section .rodata.str1.1
.LC2:
.string " or\n"
.section .rodata.str1.8
.align 8
.LC3:
.string " ./encrypt -n [2^(1:20)]\n"
.text
.globl _Z10printerrorv
.type _Z10printerrorv, @function
_Z10printerrorv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $0, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z10printerrorv, .-_Z10printerrorv
.globl _Z31__device_stub__Z7encryptPcS_iiiPcS_iii
.type _Z31__device_stub__Z7encryptPcS_iiiPcS_iii, @function
_Z31__device_stub__Z7encryptPcS_iiiPcS_iii:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7encryptPcS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z31__device_stub__Z7encryptPcS_iiiPcS_iii, .-_Z31__device_stub__Z7encryptPcS_iiiPcS_iii
.globl _Z7encryptPcS_iii
.type _Z7encryptPcS_iii, @function
_Z7encryptPcS_iii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z7encryptPcS_iiiPcS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7encryptPcS_iii, .-_Z7encryptPcS_iii
.globl _Z31__device_stub__Z7decryptPcS_iiiPcS_iii
.type _Z31__device_stub__Z7decryptPcS_iiiPcS_iii, @function
_Z31__device_stub__Z7decryptPcS_iiiPcS_iii:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7decryptPcS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z31__device_stub__Z7decryptPcS_iiiPcS_iii, .-_Z31__device_stub__Z7decryptPcS_iiiPcS_iii
.globl _Z7decryptPcS_iii
.type _Z7decryptPcS_iii, @function
_Z7decryptPcS_iii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z7decryptPcS_iiiPcS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z7decryptPcS_iii, .-_Z7decryptPcS_iii
.globl _Z31__device_stub__Z7isMatchPcS_PiiPcS_Pii
.type _Z31__device_stub__Z7isMatchPcS_PiiPcS_Pii, @function
_Z31__device_stub__Z7isMatchPcS_PiiPcS_Pii:
.LFB2087:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7isMatchPcS_Pii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z31__device_stub__Z7isMatchPcS_PiiPcS_Pii, .-_Z31__device_stub__Z7isMatchPcS_PiiPcS_Pii
.globl _Z7isMatchPcS_Pii
.type _Z7isMatchPcS_Pii, @function
_Z7isMatchPcS_Pii:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z7isMatchPcS_PiiPcS_Pii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z7isMatchPcS_Pii, .-_Z7isMatchPcS_Pii
.section .rodata.str1.1
.LC4:
.string "-n"
.LC6:
.string "r"
.LC7:
.string "Not a Valid File\n"
.LC8:
.string "File Too Large\n"
.LC10:
.string "N: %d\n"
.LC11:
.string "Does not Match\n"
.LC12:
.string "Does Match\n"
.section .rodata.str1.8
.align 8
.LC14:
.string "Encrypt Time: %4.10f seconds\n"
.align 8
.LC15:
.string "Decrypt Time: %4.10f seconds\n"
.align 8
.LC16:
.string "Match Time: %4.10f seconds\n"
.align 8
.LC17:
.string "Total Time: %4.10f seconds\n\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
leaq -1048576(%rsp), %r11
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
subq $184, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
cmpl $1, %edi
jle .L92
movq %rsi, %rbx
cmpl $3, %edi
je .L93
movl $20, -1048788(%rbp)
cmpl $2, %edi
je .L94
.L38:
movslq -1048788(%rbp), %rbx
leaq 15(%rbx), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L65:
cmpq %rdx, %rsp
je .L66
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L65
.L92:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L95
call _Z10printerrorv
.L95:
call __stack_chk_fail@PLT
.L93:
movq 8(%rsi), %rdi
leaq .LC4(%rip), %rsi
call strcmp@PLT
testl %eax, %eax
jne .L96
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
leal -1(%rax), %edx
cmpl $19, %edx
ja .L97
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
movsd .LC5(%rip), %xmm0
call pow@PLT
cvttsd2sil %xmm0, %r14d
movl %r14d, -1048788(%rbp)
movslq %r14d, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
testl %r14d, %r14d
jle .L36
leaq (%rbx,%rax), %rdx
.L37:
movb $48, (%rax)
addq $1, %rax
cmpq %rdx, %rax
jne .L37
jmp .L38
.L96:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L98
call _Z10printerrorv
.L98:
call __stack_chk_fail@PLT
.L97:
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L99
call _Z10printerrorv
.L99:
call __stack_chk_fail@PLT
.L94:
movq 8(%rsi), %rdi
leaq .LC6(%rip), %rsi
call fopen@PLT
movq %rax, %r13
movl $0, %ebx
testq %rax, %rax
jne .L39
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L40
.L41:
movb %al, -1048640(%rbp,%rbx)
addq $1, %rbx
.L39:
movq %r13, %rdi
call fgetc@PLT
cmpb $-1, %al
je .L100
cmpq $1048576, %rbx
jne .L41
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L40:
movl $-1, %eax
jmp .L29
.L100:
leal 1(%rbx), %r15d
movl %r15d, -1048788(%rbp)
movslq %r15d, %rdi
call malloc@PLT
movq %rax, %r12
testl %r15d, %r15d
jle .L43
movl %ebx, %ebx
movl $0, %eax
.L44:
movzbl -1048640(%rbp,%rax), %edx
movb %dl, 1(%r12,%rax)
movq %rax, %rdx
addq $1, %rax
cmpq %rdx, %rbx
jne .L44
.L43:
movq %r13, %rdi
call fclose@PLT
movslq -1048788(%rbp), %rbx
leaq 15(%rbx), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L45:
cmpq %rdx, %rsp
je .L46
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L45
.L46:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L47
orq $0, -8(%rsp,%rax)
.L47:
movq %rsp, %r15
leaq 15(%rbx), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L48:
cmpq %rdx, %rsp
je .L49
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L48
.L49:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L50
orq $0, -8(%rsp,%rax)
.L50:
movq %rsp, %r13
leaq 15(%rbx), %rdx
movq %rdx, %rax
andq $-16, %rax
andq $-4096, %rdx
movq %rsp, %rcx
subq %rdx, %rcx
.L51:
cmpq %rcx, %rsp
je .L52
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L51
.L52:
movq %rax, %rdx
andl $4095, %edx
subq %rdx, %rsp
testq %rdx, %rdx
je .L53
orq $0, -8(%rsp,%rdx)
.L53:
movq %rsp, %r14
cmpl $0, -1048788(%rbp)
jle .L55
jmp .L54
.L101:
movl -1048788(%rbp), %r8d
movl $55, %ecx
movl $171, %edx
movq -1048752(%rbp), %rsi
movq -1048760(%rbp), %rdi
call _Z31__device_stub__Z7encryptPcS_iiiPcS_iii
jmp .L58
.L102:
movl -1048788(%rbp), %r8d
movl $91, %ecx
movl $3, %edx
movq -1048744(%rbp), %rsi
movq -1048752(%rbp), %rdi
call _Z31__device_stub__Z7decryptPcS_iiiPcS_iii
jmp .L59
.L103:
movl -1048788(%rbp), %ecx
movq -1048736(%rbp), %rdx
movq -1048760(%rbp), %rsi
movq -1048744(%rbp), %rdi
call _Z31__device_stub__Z7isMatchPcS_PiiPcS_Pii
jmp .L60
.L61:
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L62
.L66:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L67
orq $0, -8(%rsp,%rax)
.L67:
movq %rsp, %r15
leaq 15(%rbx), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L68:
cmpq %rdx, %rsp
je .L69
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L68
.L69:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L70
orq $0, -8(%rsp,%rax)
.L70:
movq %rsp, %r13
leaq 15(%rbx), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L71:
cmpq %rdx, %rsp
je .L72
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L71
.L72:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L73
orq $0, -8(%rsp,%rax)
.L73:
movq %rsp, %r14
.L54:
movl $0, %eax
.L57:
movzbl (%r12,%rax), %edx
movb %dl, (%r15,%rax)
movb $32, 0(%r13,%rax)
movb $32, (%r14,%rax)
addq $1, %rax
cmpq %rbx, %rax
jne .L57
.L55:
movl $0, -1048780(%rbp)
leaq -1048728(%rbp), %rdi
call cudaEventCreate@PLT
leaq -1048696(%rbp), %rdi
call cudaEventCreate@PLT
leaq -1048720(%rbp), %rdi
call cudaEventCreate@PLT
leaq -1048688(%rbp), %rdi
call cudaEventCreate@PLT
leaq -1048712(%rbp), %rdi
call cudaEventCreate@PLT
leaq -1048680(%rbp), %rdi
call cudaEventCreate@PLT
leaq -1048704(%rbp), %rdi
call cudaEventCreate@PLT
leaq -1048672(%rbp), %rdi
call cudaEventCreate@PLT
movl $0x00000000, -1048776(%rbp)
movl $0x00000000, -1048772(%rbp)
movl $0x00000000, -1048768(%rbp)
movl $0x00000000, -1048764(%rbp)
movl $4, %edi
call malloc@PLT
movq %rax, -1048736(%rbp)
movl $0, (%rax)
leaq -1048760(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -1048752(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -1048744(%rbp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq -1048736(%rbp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl -1048788(%rbp), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq -1048760(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq -1048752(%rbp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq -1048744(%rbp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq -1048704(%rbp), %rdi
call cudaEventRecord@PLT
movl $0, %esi
movq -1048728(%rbp), %rdi
call cudaEventRecord@PLT
movl $128, -1048652(%rbp)
movl $1, -1048648(%rbp)
movl $1, -1048644(%rbp)
movl $128, -1048664(%rbp)
movl $1, -1048660(%rbp)
movl $1, -1048656(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -1048652(%rbp), %rdx
movl $1, %ecx
movq -1048664(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L101
.L58:
movl $0, %esi
movq -1048696(%rbp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %rbx, %rdx
movq -1048752(%rbp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq -1048696(%rbp), %rdi
call cudaEventSynchronize@PLT
leaq -1048776(%rbp), %rdi
movq -1048696(%rbp), %rdx
movq -1048728(%rbp), %rsi
call cudaEventElapsedTime@PLT
movl $0, %esi
movq -1048688(%rbp), %rdi
call cudaEventRecord@PLT
movl $128, -1048652(%rbp)
movl $1, -1048648(%rbp)
movl $1, -1048644(%rbp)
movl $128, -1048664(%rbp)
movl $1, -1048660(%rbp)
movl $1, -1048656(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -1048652(%rbp), %rdx
movl $1, %ecx
movq -1048664(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L102
.L59:
movl $0, %esi
movq -1048688(%rbp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %rbx, %rdx
movq -1048744(%rbp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movq -1048688(%rbp), %rdi
call cudaEventSynchronize@PLT
leaq -1048772(%rbp), %rdi
movq -1048688(%rbp), %rdx
movq -1048720(%rbp), %rsi
call cudaEventElapsedTime@PLT
movl $0, %esi
movq -1048712(%rbp), %rdi
call cudaEventRecord@PLT
movl $128, -1048652(%rbp)
movl $1, -1048648(%rbp)
movl $1, -1048644(%rbp)
movl $128, -1048664(%rbp)
movl $1, -1048660(%rbp)
movl $1, -1048656(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -1048652(%rbp), %rdx
movl $1, %ecx
movq -1048664(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L103
.L60:
movl $0, %esi
movq -1048680(%rbp), %rdi
call cudaEventRecord@PLT
leaq -1048780(%rbp), %rdi
movl $2, %ecx
movl $4, %edx
movq -1048736(%rbp), %rsi
call cudaMemcpy@PLT
cmpl $0, -1048780(%rbp)
je .L61
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L62:
movq -1048680(%rbp), %rdi
call cudaEventSynchronize@PLT
leaq -1048768(%rbp), %rdi
movq -1048680(%rbp), %rdx
movq -1048712(%rbp), %rsi
call cudaEventElapsedTime@PLT
movl $0, %esi
movq -1048672(%rbp), %rdi
call cudaEventRecord@PLT
movq -1048672(%rbp), %rdi
call cudaEventSynchronize@PLT
leaq -1048764(%rbp), %rdi
movq -1048672(%rbp), %rdx
movq -1048704(%rbp), %rsi
call cudaEventElapsedTime@PLT
movss -1048776(%rbp), %xmm0
divss .LC13(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss -1048772(%rbp), %xmm0
divss .LC13(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss -1048768(%rbp), %xmm0
divss .LC13(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss -1048764(%rbp), %xmm0
divss .LC13(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq -1048760(%rbp), %rdi
call cudaFree@PLT
movq -1048752(%rbp), %rdi
call cudaFree@PLT
movq -1048744(%rbp), %rdi
call cudaFree@PLT
movl $0, %eax
.L29:
movq -56(%rbp), %rdx
subq %fs:40, %rdx
jne .L104
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L36:
.cfi_restore_state
movslq -1048788(%rbp), %rbx
leaq 15(%rbx), %rdx
movq %rdx, %rax
andq $-16, %rax
andq $-4096, %rdx
movq %rsp, %rcx
subq %rdx, %rcx
.L74:
cmpq %rcx, %rsp
je .L75
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L74
.L75:
movq %rax, %rdx
andl $4095, %edx
subq %rdx, %rsp
testq %rdx, %rdx
je .L76
orq $0, -8(%rsp,%rdx)
.L76:
movq %rsp, %r15
leaq 15(%rbx), %rdx
movq %rdx, %rax
andq $-16, %rax
andq $-4096, %rdx
movq %rsp, %rcx
subq %rdx, %rcx
.L77:
cmpq %rcx, %rsp
je .L78
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L77
.L78:
movq %rax, %rdx
andl $4095, %edx
subq %rdx, %rsp
testq %rdx, %rdx
je .L79
orq $0, -8(%rsp,%rdx)
.L79:
movq %rsp, %r13
leaq 15(%rbx), %rdx
movq %rdx, %rax
andq $-16, %rax
andq $-4096, %rdx
movq %rsp, %rcx
subq %rdx, %rcx
.L80:
cmpq %rcx, %rsp
je .L81
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L80
.L81:
movq %rax, %rdx
andl $4095, %edx
subq %rdx, %rsp
testq %rdx, %rdx
je .L82
orq $0, -8(%rsp,%rdx)
.L82:
movq %rsp, %r14
jmp .L55
.L104:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC18:
.string "_Z7isMatchPcS_Pii"
.LC19:
.string "_Z7decryptPcS_iii"
.LC20:
.string "_Z7encryptPcS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z7isMatchPcS_Pii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z7decryptPcS_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z7encryptPcS_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1073741824
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC13:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Encrypt_CUDA.hip"
.globl _Z22__device_stub__encryptPcS_iii # -- Begin function _Z22__device_stub__encryptPcS_iii
.p2align 4, 0x90
.type _Z22__device_stub__encryptPcS_iii,@function
_Z22__device_stub__encryptPcS_iii: # @_Z22__device_stub__encryptPcS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7encryptPcS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__encryptPcS_iii, .Lfunc_end0-_Z22__device_stub__encryptPcS_iii
.cfi_endproc
# -- End function
.globl _Z22__device_stub__decryptPcS_iii # -- Begin function _Z22__device_stub__decryptPcS_iii
.p2align 4, 0x90
.type _Z22__device_stub__decryptPcS_iii,@function
_Z22__device_stub__decryptPcS_iii: # @_Z22__device_stub__decryptPcS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7decryptPcS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z22__device_stub__decryptPcS_iii, .Lfunc_end1-_Z22__device_stub__decryptPcS_iii
.cfi_endproc
# -- End function
.globl _Z22__device_stub__isMatchPcS_Pii # -- Begin function _Z22__device_stub__isMatchPcS_Pii
.p2align 4, 0x90
.type _Z22__device_stub__isMatchPcS_Pii,@function
_Z22__device_stub__isMatchPcS_Pii: # @_Z22__device_stub__isMatchPcS_Pii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7isMatchPcS_Pii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z22__device_stub__isMatchPcS_Pii, .Lfunc_end2-_Z22__device_stub__isMatchPcS_Pii
.cfi_endproc
# -- End function
.globl _Z10printerrorv # -- Begin function _Z10printerrorv
.p2align 4, 0x90
.type _Z10printerrorv,@function
_Z10printerrorv: # @_Z10printerrorv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $18, %esi
movl $1, %edx
callq fwrite@PLT
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $42, %esi
movl $1, %edx
callq fwrite@PLT
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $17, %esi
movl $1, %edx
callq fwrite@PLT
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $38, %esi
movl $1, %edx
callq fwrite@PLT
xorl %edi, %edi
callq exit
.Lfunc_end3:
.size _Z10printerrorv, .Lfunc_end3-_Z10printerrorv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x3ff0000000000000 # double 1
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI4_1:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $1048808, %rsp # imm = 0x1000E8
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
cmpl $1, %edi
jle .LBB4_33
# %bb.1:
movq %rsi, %rbx
movl %edi, %r14d
cmpl $3, %edi
jne .LBB4_3
# %bb.2:
movq 8(%rbx), %rdi
movl $.L.str.4, %esi
callq strcmp
testl %eax, %eax
jne .LBB4_33
.LBB4_3:
movq 8(%rbx), %rdi
movl $.L.str.4, %esi
callq strcmp
movl $20, %r13d
# implicit-def: $r15
cmpl $3, %r14d
jne .LBB4_8
# %bb.4:
testl %eax, %eax
jne .LBB4_8
# %bb.5:
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
leal -21(%rax), %ecx
cmpl $-21, %ecx
jbe .LBB4_33
# %bb.6:
movsd .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero
movl %eax, %edi
callq ldexp@PLT
cvttsd2si %xmm0, %r13d
movslq %r13d, %r12
movq %r12, %rdi
callq malloc
movq %rax, %r15
testl %r12d, %r12d
jle .LBB4_8
# %bb.7: # %.lr.ph.preheader
movl %r13d, %edx
movq %r15, %rdi
movl $48, %esi
callq memset@PLT
.LBB4_8: # %.loopexit
xorl %r12d, %r12d
cmpl $2, %r14d
jne .LBB4_19
# %bb.9:
movq 8(%rbx), %rdi
movl $.L.str.5, %esi
callq fopen
testq %rax, %rax
je .LBB4_14
# %bb.10: # %.preheader
movq %rax, %rbx
movq %rax, %rdi
callq fgetc
xorl %r12d, %r12d
movl $0, %r14d
cmpb $-1, %al
je .LBB4_17
# %bb.11: # %.lr.ph123.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_12: # %.lr.ph123
# =>This Inner Loop Header: Depth=1
cmpq $1048576, %r14 # imm = 0x100000
je .LBB4_13
# %bb.16: # in Loop: Header=BB4_12 Depth=1
movb %al, -1048848(%rbp,%r14)
incq %r14
movq %rbx, %rdi
callq fgetc
cmpb $-1, %al
jne .LBB4_12
.LBB4_17: # %._crit_edge
leal 1(%r14), %r13d
movq %r13, %rdi
callq malloc
movq %rax, %r15
leaq 1(%rax), %rdi
movl %r14d, %edx
incq %rdx
leaq -1048848(%rbp), %rsi
callq memcpy@PLT
movq %rbx, %rdi
callq fclose
movb $1, %al
testb %al, %al
je .LBB4_32
.LBB4_19:
movl %r12d, -220(%rbp) # 4-byte Spill
movq %rsp, -256(%rbp) # 8-byte Spill
movl %r13d, %eax
movq %rsp, %r14
leaq 15(%rax), %rcx
andq $-16, %rcx
subq %rcx, %r14
movq %r14, %rsp
movq %rsp, %rbx
subq %rcx, %rbx
movq %rbx, %rsp
movq %rsp, %r12
subq %rcx, %r12
movq %r12, %rsp
testl %r13d, %r13d
jle .LBB4_22
# %bb.20: # %.lr.ph127.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB4_21: # %.lr.ph127
# =>This Inner Loop Header: Depth=1
movzbl (%r15,%rcx), %edx
movb %dl, (%r14,%rcx)
movb $32, (%rbx,%rcx)
movb $32, (%r12,%rcx)
incq %rcx
cmpq %rcx, %rax
jne .LBB4_21
.LBB4_22: # %._crit_edge128
movl $0, -156(%rbp)
leaq -248(%rbp), %rdi
callq hipEventCreate
leaq -208(%rbp), %rdi
callq hipEventCreate
leaq -264(%rbp), %rdi
callq hipEventCreate
leaq -168(%rbp), %rdi
callq hipEventCreate
leaq -240(%rbp), %rdi
callq hipEventCreate
leaq -200(%rbp), %rdi
callq hipEventCreate
leaq -232(%rbp), %rdi
callq hipEventCreate
leaq -192(%rbp), %rdi
callq hipEventCreate
movl $0, -152(%rbp)
movl $0, -148(%rbp)
movl $0, -144(%rbp)
movl $0, -140(%rbp)
movl $4, %edi
callq malloc
movq %rax, -216(%rbp)
movl $0, (%rax)
movslq %r13d, %r15
leaq -176(%rbp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq -64(%rbp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq -56(%rbp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq -216(%rbp), %rdi
movl $4, %esi
callq hipMalloc
movl $.L.str.8, %edi
movq %r13, -184(%rbp) # 8-byte Spill
movl %r13d, %esi
xorl %eax, %eax
callq printf
movq -176(%rbp), %rdi
movq %r14, %rsi
movabsq $4294967424, %r14 # imm = 0x100000080
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq -64(%rbp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq -56(%rbp), %rdi
movq %r12, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq -232(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -248(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r14, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_24
# %bb.23:
movq -176(%rbp), %rax
movq -64(%rbp), %rcx
movq %rax, -136(%rbp)
movq %rcx, -128(%rbp)
movl $171, -72(%rbp)
movl $55, -44(%rbp)
movq -184(%rbp), %rax # 8-byte Reload
movl %eax, -48(%rbp)
leaq -136(%rbp), %rax
movq %rax, -1048848(%rbp)
leaq -128(%rbp), %rax
movq %rax, -1048840(%rbp)
leaq -72(%rbp), %rax
movq %rax, -1048832(%rbp)
leaq -44(%rbp), %rax
movq %rax, -1048824(%rbp)
leaq -48(%rbp), %rax
movq %rax, -1048816(%rbp)
leaq -112(%rbp), %rdi
leaq -96(%rbp), %rsi
leaq -120(%rbp), %rdx
leaq -80(%rbp), %rcx
callq __hipPopCallConfiguration
movq -112(%rbp), %rsi
movl -104(%rbp), %edx
movq -96(%rbp), %rcx
movl -88(%rbp), %r8d
leaq -1048848(%rbp), %r9
movl $_Z7encryptPcS_iii, %edi
pushq -80(%rbp)
pushq -120(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB4_24:
movq -208(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -64(%rbp), %rsi
movq %rbx, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq -208(%rbp), %rdi
callq hipEventSynchronize
movq -248(%rbp), %rsi
movq -208(%rbp), %rdx
leaq -152(%rbp), %rdi
callq hipEventElapsedTime
movq -168(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r14, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_26
# %bb.25:
movq -64(%rbp), %rax
movq -56(%rbp), %rcx
movq %rax, -136(%rbp)
movq %rcx, -128(%rbp)
movl $3, -72(%rbp)
movl $91, -44(%rbp)
movq -184(%rbp), %rax # 8-byte Reload
movl %eax, -48(%rbp)
leaq -136(%rbp), %rax
movq %rax, -1048848(%rbp)
leaq -128(%rbp), %rax
movq %rax, -1048840(%rbp)
leaq -72(%rbp), %rax
movq %rax, -1048832(%rbp)
leaq -44(%rbp), %rax
movq %rax, -1048824(%rbp)
leaq -48(%rbp), %rax
movq %rax, -1048816(%rbp)
leaq -112(%rbp), %rdi
leaq -96(%rbp), %rsi
leaq -120(%rbp), %rdx
leaq -80(%rbp), %rcx
callq __hipPopCallConfiguration
movq -112(%rbp), %rsi
movl -104(%rbp), %edx
movq -96(%rbp), %rcx
movl -88(%rbp), %r8d
leaq -1048848(%rbp), %r9
movl $_Z7decryptPcS_iii, %edi
pushq -80(%rbp)
pushq -120(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB4_26:
movq -168(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -56(%rbp), %rsi
movq %r12, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
movq -168(%rbp), %rdi
callq hipEventSynchronize
movq -264(%rbp), %rsi
movq -168(%rbp), %rdx
leaq -148(%rbp), %rdi
callq hipEventElapsedTime
movq -240(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r14, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_28
# %bb.27:
movq -56(%rbp), %rax
movq -176(%rbp), %rcx
movq -216(%rbp), %rdx
movq %rax, -136(%rbp)
movq %rcx, -128(%rbp)
movq %rdx, -120(%rbp)
movq -184(%rbp), %rax # 8-byte Reload
movl %eax, -44(%rbp)
leaq -136(%rbp), %rax
movq %rax, -1048848(%rbp)
leaq -128(%rbp), %rax
movq %rax, -1048840(%rbp)
leaq -120(%rbp), %rax
movq %rax, -1048832(%rbp)
leaq -44(%rbp), %rax
movq %rax, -1048824(%rbp)
leaq -112(%rbp), %rdi
leaq -96(%rbp), %rsi
leaq -80(%rbp), %rdx
leaq -72(%rbp), %rcx
callq __hipPopCallConfiguration
movq -112(%rbp), %rsi
movl -104(%rbp), %edx
movq -96(%rbp), %rcx
movl -88(%rbp), %r8d
leaq -1048848(%rbp), %r9
movl $_Z7isMatchPcS_Pii, %edi
pushq -72(%rbp)
pushq -80(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB4_28:
movq -200(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -216(%rbp), %rsi
leaq -156(%rbp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
cmpl $0, -156(%rbp)
movq stdout(%rip), %rcx
movl -220(%rbp), %r12d # 4-byte Reload
je .LBB4_30
# %bb.29:
movl $.L.str.9, %edi
movl $15, %esi
jmp .LBB4_31
.LBB4_30:
movl $.L.str.10, %edi
movl $11, %esi
.LBB4_31:
movl $1, %edx
callq fwrite@PLT
movq -200(%rbp), %rdi
callq hipEventSynchronize
movq -240(%rbp), %rsi
movq -200(%rbp), %rdx
leaq -144(%rbp), %rdi
callq hipEventElapsedTime
movq -192(%rbp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq -192(%rbp), %rdi
callq hipEventSynchronize
movq -232(%rbp), %rsi
movq -192(%rbp), %rdx
leaq -140(%rbp), %rdi
callq hipEventElapsedTime
movss -152(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI4_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.11, %edi
movb $1, %al
callq printf
movss -148(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI4_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.12, %edi
movb $1, %al
callq printf
movss -144(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI4_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.13, %edi
movb $1, %al
callq printf
movss -140(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI4_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.14, %edi
movb $1, %al
callq printf
movq -176(%rbp), %rdi
callq hipFree
movq -64(%rbp), %rdi
callq hipFree
movq -56(%rbp), %rdi
callq hipFree
movq -256(%rbp), %rsp # 8-byte Reload
.LBB4_32:
movl %r12d, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB4_14:
.cfi_def_cfa %rbp, 16
movq stderr(%rip), %rcx
movl $.L.str.6, %edi
movl $17, %esi
jmp .LBB4_15
.LBB4_13:
movq stderr(%rip), %rcx
movl $.L.str.7, %edi
movl $15, %esi
.LBB4_15:
movl $1, %edx
callq fwrite@PLT
movl $-1, %r12d
xorl %eax, %eax
testb %al, %al
jne .LBB4_19
jmp .LBB4_32
.LBB4_33:
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $18, %esi
movl $1, %edx
callq fwrite@PLT
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $42, %esi
movl $1, %edx
callq fwrite@PLT
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $17, %esi
movl $1, %edx
callq fwrite@PLT
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $38, %esi
movl $1, %edx
callq fwrite@PLT
xorl %edi, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7encryptPcS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7decryptPcS_iii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7isMatchPcS_Pii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7encryptPcS_iii,@object # @_Z7encryptPcS_iii
.section .rodata,"a",@progbits
.globl _Z7encryptPcS_iii
.p2align 3, 0x0
_Z7encryptPcS_iii:
.quad _Z22__device_stub__encryptPcS_iii
.size _Z7encryptPcS_iii, 8
.type _Z7decryptPcS_iii,@object # @_Z7decryptPcS_iii
.globl _Z7decryptPcS_iii
.p2align 3, 0x0
_Z7decryptPcS_iii:
.quad _Z22__device_stub__decryptPcS_iii
.size _Z7decryptPcS_iii, 8
.type _Z7isMatchPcS_Pii,@object # @_Z7isMatchPcS_Pii
.globl _Z7isMatchPcS_Pii
.p2align 3, 0x0
_Z7isMatchPcS_Pii:
.quad _Z22__device_stub__isMatchPcS_Pii
.size _Z7isMatchPcS_Pii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Invalid Arguments\n"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Correct Form: ./encrypt [File to Encrypt]\n"
.size .L.str.1, 43
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " or\n"
.size .L.str.2, 18
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " ./encrypt -n [2^(1:20)]\n"
.size .L.str.3, 39
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "-n"
.size .L.str.4, 3
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "r"
.size .L.str.5, 2
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Not a Valid File\n"
.size .L.str.6, 18
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "File Too Large\n"
.size .L.str.7, 16
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "N: %d\n"
.size .L.str.8, 7
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Does not Match\n"
.size .L.str.9, 16
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Does Match\n"
.size .L.str.10, 12
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Encrypt Time: %4.10f seconds\n"
.size .L.str.11, 32
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Decrypt Time: %4.10f seconds\n"
.size .L.str.12, 32
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Match Time: %4.10f seconds\n"
.size .L.str.13, 32
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Total Time: %4.10f seconds\n\n"
.size .L.str.14, 33
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7encryptPcS_iii"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7decryptPcS_iii"
.size .L__unnamed_2, 18
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z7isMatchPcS_Pii"
.size .L__unnamed_3, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__encryptPcS_iii
.addrsig_sym _Z22__device_stub__decryptPcS_iii
.addrsig_sym _Z22__device_stub__isMatchPcS_Pii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7encryptPcS_iii
.addrsig_sym _Z7decryptPcS_iii
.addrsig_sym _Z7isMatchPcS_Pii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void elementwise_add(const int * array1,
const int * array2, int * result, int size) {
unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int stride = gridDim.x * blockDim.x;
while (idx < size) {
result[idx] = array1[idx] + array2[idx];
idx += stride;
}
} | code for sm_80
Function : _Z15elementwise_addPKiS0_Pii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE.U32 R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0007 */
/*0090*/ IMAD.WIDE.U32 R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0007 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE.U32 R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0007 */
/*00d0*/ MOV R11, c[0x0][0xc] ; /* 0x00000300000b7a02 */
/* 0x000fca0000000f00 */
/*00e0*/ IMAD R0, R11, c[0x0][0x0], R0 ; /* 0x000000000b007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f06070 */
/*0100*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*0110*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001ec000c101904 */
/*0120*/ @!P0 BRA 0x70 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void elementwise_add(const int * array1,
const int * array2, int * result, int size) {
unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int stride = gridDim.x * blockDim.x;
while (idx < size) {
result[idx] = array1[idx] + array2[idx];
idx += stride;
}
} | .file "tmpxft_0004a4f1_00000000-6_Add_two_arrays.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z15elementwise_addPKiS0_PiiPKiS0_Pii
.type _Z42__device_stub__Z15elementwise_addPKiS0_PiiPKiS0_Pii, @function
_Z42__device_stub__Z15elementwise_addPKiS0_PiiPKiS0_Pii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15elementwise_addPKiS0_Pii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z15elementwise_addPKiS0_PiiPKiS0_Pii, .-_Z42__device_stub__Z15elementwise_addPKiS0_PiiPKiS0_Pii
.globl _Z15elementwise_addPKiS0_Pii
.type _Z15elementwise_addPKiS0_Pii, @function
_Z15elementwise_addPKiS0_Pii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z15elementwise_addPKiS0_PiiPKiS0_Pii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15elementwise_addPKiS0_Pii, .-_Z15elementwise_addPKiS0_Pii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15elementwise_addPKiS0_Pii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15elementwise_addPKiS0_Pii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void elementwise_add(const int * array1,
const int * array2, int * result, int size) {
unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int stride = gridDim.x * blockDim.x;
while (idx < size) {
result[idx] = array1[idx] + array2[idx];
idx += stride;
}
} | #include <hip/hip_runtime.h>
__global__ void elementwise_add(const int * array1,
const int * array2, int * result, int size) {
unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int stride = gridDim.x * blockDim.x;
while (idx < size) {
result[idx] = array1[idx] + array2[idx];
idx += stride;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void elementwise_add(const int * array1,
const int * array2, int * result, int size) {
unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int stride = gridDim.x * blockDim.x;
while (idx < size) {
result[idx] = array1[idx] + array2[idx];
idx += stride;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15elementwise_addPKiS0_Pii
.globl _Z15elementwise_addPKiS0_Pii
.p2align 8
.type _Z15elementwise_addPKiS0_Pii,@function
_Z15elementwise_addPKiS0_Pii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s8, v1
s_cbranch_execz .LBB0_3
s_load_b32 s10, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s10, s9
s_mov_b32 s9, 0
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v5, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s8, v1
global_load_b32 v0, v[5:6], off
global_load_b32 v5, v[7:8], off
v_add_co_u32 v3, s0, s2, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, s3, v4, s0
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v5, v0
global_store_b32 v[3:4], v0, off
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15elementwise_addPKiS0_Pii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15elementwise_addPKiS0_Pii, .Lfunc_end0-_Z15elementwise_addPKiS0_Pii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15elementwise_addPKiS0_Pii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15elementwise_addPKiS0_Pii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void elementwise_add(const int * array1,
const int * array2, int * result, int size) {
unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int stride = gridDim.x * blockDim.x;
while (idx < size) {
result[idx] = array1[idx] + array2[idx];
idx += stride;
}
} | .text
.file "Add_two_arrays.hip"
.globl _Z30__device_stub__elementwise_addPKiS0_Pii # -- Begin function _Z30__device_stub__elementwise_addPKiS0_Pii
.p2align 4, 0x90
.type _Z30__device_stub__elementwise_addPKiS0_Pii,@function
_Z30__device_stub__elementwise_addPKiS0_Pii: # @_Z30__device_stub__elementwise_addPKiS0_Pii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15elementwise_addPKiS0_Pii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__elementwise_addPKiS0_Pii, .Lfunc_end0-_Z30__device_stub__elementwise_addPKiS0_Pii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15elementwise_addPKiS0_Pii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15elementwise_addPKiS0_Pii,@object # @_Z15elementwise_addPKiS0_Pii
.section .rodata,"a",@progbits
.globl _Z15elementwise_addPKiS0_Pii
.p2align 3, 0x0
_Z15elementwise_addPKiS0_Pii:
.quad _Z30__device_stub__elementwise_addPKiS0_Pii
.size _Z15elementwise_addPKiS0_Pii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15elementwise_addPKiS0_Pii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__elementwise_addPKiS0_Pii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15elementwise_addPKiS0_Pii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15elementwise_addPKiS0_Pii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE.U32 R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0007 */
/*0090*/ IMAD.WIDE.U32 R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0007 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE.U32 R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0007 */
/*00d0*/ MOV R11, c[0x0][0xc] ; /* 0x00000300000b7a02 */
/* 0x000fca0000000f00 */
/*00e0*/ IMAD R0, R11, c[0x0][0x0], R0 ; /* 0x000000000b007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f06070 */
/*0100*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*0110*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001ec000c101904 */
/*0120*/ @!P0 BRA 0x70 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15elementwise_addPKiS0_Pii
.globl _Z15elementwise_addPKiS0_Pii
.p2align 8
.type _Z15elementwise_addPKiS0_Pii,@function
_Z15elementwise_addPKiS0_Pii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s8, v1
s_cbranch_execz .LBB0_3
s_load_b32 s10, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s10, s9
s_mov_b32 s9, 0
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v5, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s8, v1
global_load_b32 v0, v[5:6], off
global_load_b32 v5, v[7:8], off
v_add_co_u32 v3, s0, s2, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, s3, v4, s0
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v5, v0
global_store_b32 v[3:4], v0, off
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15elementwise_addPKiS0_Pii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15elementwise_addPKiS0_Pii, .Lfunc_end0-_Z15elementwise_addPKiS0_Pii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15elementwise_addPKiS0_Pii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15elementwise_addPKiS0_Pii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004a4f1_00000000-6_Add_two_arrays.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z15elementwise_addPKiS0_PiiPKiS0_Pii
.type _Z42__device_stub__Z15elementwise_addPKiS0_PiiPKiS0_Pii, @function
_Z42__device_stub__Z15elementwise_addPKiS0_PiiPKiS0_Pii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15elementwise_addPKiS0_Pii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z15elementwise_addPKiS0_PiiPKiS0_Pii, .-_Z42__device_stub__Z15elementwise_addPKiS0_PiiPKiS0_Pii
.globl _Z15elementwise_addPKiS0_Pii
.type _Z15elementwise_addPKiS0_Pii, @function
_Z15elementwise_addPKiS0_Pii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z15elementwise_addPKiS0_PiiPKiS0_Pii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15elementwise_addPKiS0_Pii, .-_Z15elementwise_addPKiS0_Pii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15elementwise_addPKiS0_Pii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15elementwise_addPKiS0_Pii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Add_two_arrays.hip"
.globl _Z30__device_stub__elementwise_addPKiS0_Pii # -- Begin function _Z30__device_stub__elementwise_addPKiS0_Pii
.p2align 4, 0x90
.type _Z30__device_stub__elementwise_addPKiS0_Pii,@function
_Z30__device_stub__elementwise_addPKiS0_Pii: # @_Z30__device_stub__elementwise_addPKiS0_Pii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15elementwise_addPKiS0_Pii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__elementwise_addPKiS0_Pii, .Lfunc_end0-_Z30__device_stub__elementwise_addPKiS0_Pii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15elementwise_addPKiS0_Pii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15elementwise_addPKiS0_Pii,@object # @_Z15elementwise_addPKiS0_Pii
.section .rodata,"a",@progbits
.globl _Z15elementwise_addPKiS0_Pii
.p2align 3, 0x0
_Z15elementwise_addPKiS0_Pii:
.quad _Z30__device_stub__elementwise_addPKiS0_Pii
.size _Z15elementwise_addPKiS0_Pii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15elementwise_addPKiS0_Pii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__elementwise_addPKiS0_Pii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15elementwise_addPKiS0_Pii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void Compute(int *a, int k, int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int id = i / k * 2 * k + k + i % k;
if(id < n) {
a[id] += a[id - id % k - 1];
}
} | code for sm_80
Function : _Z7ComputePiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R0, c[0x0][0x168] ; /* 0x00005a0000007a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0030*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000800 */
/*0040*/ I2F.RP R5, R0 ; /* 0x0000000000057306 */
/* 0x000e620000209400 */
/*0050*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0060*/ USHF.L.U32 UR4, UR4, 0x1, URZ ; /* 0x0000000104047899 */
/* 0x000fcc000800063f */
/*0070*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x002e620000001000 */
/*0080*/ IMAD R4, R4, c[0x0][0x0], R7 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0207 */
/*0090*/ IABS R6, R4 ; /* 0x0000000400067213 */
/* 0x000fe40000000000 */
/*00a0*/ IADD3 R2, R5, 0xffffffe, RZ ; /* 0x0ffffffe05027810 */
/* 0x002fc80007ffe0ff */
/*00b0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00d0*/ IMAD.MOV R9, RZ, RZ, -R3 ; /* 0x000000ffff097224 */
/* 0x002fc800078e0a03 */
/*00e0*/ IMAD R7, R9, R0, RZ ; /* 0x0000000009077224 */
/* 0x000fc800078e02ff */
/*00f0*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe200078e0002 */
/*0100*/ MOV R7, R6 ; /* 0x0000000600077202 */
/* 0x000fe40000000f00 */
/*0110*/ LOP3.LUT R2, R4, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a0004027a12 */
/* 0x000fc600078e3cff */
/*0120*/ IMAD.HI.U32 R5, R3, R7, RZ ; /* 0x0000000703057227 */
/* 0x000fe200078e00ff */
/*0130*/ ISETP.GE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f06270 */
/*0140*/ LOP3.LUT R2, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff027a12 */
/* 0x000fe200078e33ff */
/*0150*/ IMAD.MOV R6, RZ, RZ, -R5 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0a05 */
/*0160*/ IMAD R7, R0, R6, R7 ; /* 0x0000000600077224 */
/* 0x000fca00078e0207 */
/*0170*/ ISETP.GT.U32.AND P2, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fda0003f44070 */
/*0180*/ @!P2 IMAD.IADD R7, R7, 0x1, -R0 ; /* 0x000000010707a824 */
/* 0x000fe200078e0a00 */
/*0190*/ @!P2 IADD3 R5, R5, 0x1, RZ ; /* 0x000000010505a810 */
/* 0x000fc80007ffe0ff */
/*01a0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01b0*/ @P1 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105051810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fc60003f25270 */
/*01d0*/ @!P0 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff058224 */
/* 0x000fca00078e0a05 */
/*01e0*/ SEL R5, R2, R5, !P1 ; /* 0x0000000502057207 */
/* 0x000fc80004800000 */
/*01f0*/ IADD3 R7, -R5, RZ, RZ ; /* 0x000000ff05077210 */
/* 0x000fca0007ffe1ff */
/*0200*/ IMAD R4, R7, c[0x0][0x168], R4 ; /* 0x00005a0007047a24 */
/* 0x000fca00078e0204 */
/*0210*/ IADD3 R4, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fca0007ffe0ff */
/*0220*/ IMAD R5, R5, UR4, R4 ; /* 0x0000000405057c24 */
/* 0x000fca000f8e0204 */
/*0230*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x16c], PT ; /* 0x00005b0005007a0c */
/* 0x000fda0003f06270 */
/*0240*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0250*/ IABS R4, R5 ; /* 0x0000000500047213 */
/* 0x000fe20000000000 */
/*0260*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0270*/ ISETP.GE.AND P2, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc60003f46270 */
/*0280*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fc800078e00ff */
/*0290*/ IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a03 */
/*02a0*/ IMAD R3, R0, R3, R4 ; /* 0x0000000300037224 */
/* 0x000fca00078e0204 */
/*02b0*/ ISETP.GT.U32.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x000fda0003f04070 */
/*02c0*/ @!P0 IMAD.IADD R3, R3, 0x1, -R0 ; /* 0x0000000103038824 */
/* 0x000fca00078e0a00 */
/*02d0*/ ISETP.GT.U32.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x000fda0003f04070 */
/*02e0*/ @!P0 IADD3 R3, R3, -R0, RZ ; /* 0x8000000003038210 */
/* 0x000fca0007ffe0ff */
/*02f0*/ @!P2 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff03a224 */
/* 0x000fca00078e0a03 */
/*0300*/ SEL R2, R2, R3, !P1 ; /* 0x0000000302027207 */
/* 0x000fe20004800000 */
/*0310*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0320*/ LOP3.LUT R2, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff027212 */
/* 0x000fc800078e33ff */
/*0330*/ IADD3 R2, R5.reuse, R2, RZ ; /* 0x0000000205027210 */
/* 0x040fe20007ffe0ff */
/*0340*/ IMAD.WIDE R4, R5, R3, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fc800078e0203 */
/*0350*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e0203 */
/*0360*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000eaa000c1e1900 */
/*0370*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea4000c1e1900 */
/*0380*/ IMAD.IADD R7, R0, 0x1, R3 ; /* 0x0000000100077824 */
/* 0x004fca00078e0203 */
/*0390*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*03a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03b0*/ BRA 0x3b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void Compute(int *a, int k, int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int id = i / k * 2 * k + k + i % k;
if(id < n) {
a[id] += a[id - id % k - 1];
}
} | .file "tmpxft_000fafa2_00000000-6_Compute.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z7ComputePiiiPiii
.type _Z28__device_stub__Z7ComputePiiiPiii, @function
_Z28__device_stub__Z7ComputePiiiPiii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7ComputePiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z7ComputePiiiPiii, .-_Z28__device_stub__Z7ComputePiiiPiii
.globl _Z7ComputePiii
.type _Z7ComputePiii, @function
_Z7ComputePiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7ComputePiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7ComputePiii, .-_Z7ComputePiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7ComputePiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7ComputePiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void Compute(int *a, int k, int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int id = i / k * 2 * k + k + i % k;
if(id < n) {
a[id] += a[id - id % k - 1];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Compute(int *a, int k, int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int id = i / k * 2 * k + k + i % k;
if(id < n) {
a[id] += a[id - id % k - 1];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Compute(int *a, int k, int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int id = i / k * 2 * k + k + i % k;
if(id < n) {
a[id] += a[id - id % k - 1];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7ComputePiii
.globl _Z7ComputePiii
.p2align 8
.type _Z7ComputePiii,@function
_Z7ComputePiii:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x8
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_ashr_i32 s6, s4, 31
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s4, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s2, s2, s6
v_cvt_f32_u32_e32 v1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_sub_i32 s3, 0, s2
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s3, v3
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v1, v4
v_xor_b32_e32 v5, v2, v4
v_xor_b32_e32 v4, s6, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v3, v0
v_mul_hi_u32 v0, v5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, s2
v_sub_nc_u32_e32 v3, v5, v3
v_add_nc_u32_e32 v5, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s2, v3
v_cmp_le_u32_e32 vcc_lo, s2, v3
v_dual_cndmask_b32 v3, v3, v6 :: v_dual_cndmask_b32 v0, v0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s2, v3
v_add_nc_u32_e32 v5, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v5, vcc_lo
v_xor_b32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v4
v_mul_lo_u32 v3, v0, s4
v_lshl_or_b32 v4, v0, 1, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v1, v3
v_mad_u64_u32 v[0:1], null, v4, s4, v[3:4]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s5, v0
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v1, 31, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v0, v1
v_xor_b32_e32 v3, v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v3, v2
v_mul_lo_u32 v2, v2, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v3, v2
v_subrev_nc_u32_e32 v3, s2, v2
v_cmp_le_u32_e32 vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_subrev_nc_u32_e32 v3, s2, v2
v_cmp_le_u32_e32 vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_xor_b32_e32 v2, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v1, v2, v1
v_xad_u32 v2, v1, -1, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_clause 0x1
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7ComputePiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7ComputePiii, .Lfunc_end0-_Z7ComputePiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7ComputePiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7ComputePiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Compute(int *a, int k, int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int id = i / k * 2 * k + k + i % k;
if(id < n) {
a[id] += a[id - id % k - 1];
}
} | .text
.file "Compute.hip"
.globl _Z22__device_stub__ComputePiii # -- Begin function _Z22__device_stub__ComputePiii
.p2align 4, 0x90
.type _Z22__device_stub__ComputePiii,@function
_Z22__device_stub__ComputePiii: # @_Z22__device_stub__ComputePiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7ComputePiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__ComputePiii, .Lfunc_end0-_Z22__device_stub__ComputePiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7ComputePiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7ComputePiii,@object # @_Z7ComputePiii
.section .rodata,"a",@progbits
.globl _Z7ComputePiii
.p2align 3, 0x0
_Z7ComputePiii:
.quad _Z22__device_stub__ComputePiii
.size _Z7ComputePiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7ComputePiii"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__ComputePiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7ComputePiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7ComputePiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R0, c[0x0][0x168] ; /* 0x00005a0000007a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0030*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000800 */
/*0040*/ I2F.RP R5, R0 ; /* 0x0000000000057306 */
/* 0x000e620000209400 */
/*0050*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0060*/ USHF.L.U32 UR4, UR4, 0x1, URZ ; /* 0x0000000104047899 */
/* 0x000fcc000800063f */
/*0070*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x002e620000001000 */
/*0080*/ IMAD R4, R4, c[0x0][0x0], R7 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0207 */
/*0090*/ IABS R6, R4 ; /* 0x0000000400067213 */
/* 0x000fe40000000000 */
/*00a0*/ IADD3 R2, R5, 0xffffffe, RZ ; /* 0x0ffffffe05027810 */
/* 0x002fc80007ffe0ff */
/*00b0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00d0*/ IMAD.MOV R9, RZ, RZ, -R3 ; /* 0x000000ffff097224 */
/* 0x002fc800078e0a03 */
/*00e0*/ IMAD R7, R9, R0, RZ ; /* 0x0000000009077224 */
/* 0x000fc800078e02ff */
/*00f0*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe200078e0002 */
/*0100*/ MOV R7, R6 ; /* 0x0000000600077202 */
/* 0x000fe40000000f00 */
/*0110*/ LOP3.LUT R2, R4, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a0004027a12 */
/* 0x000fc600078e3cff */
/*0120*/ IMAD.HI.U32 R5, R3, R7, RZ ; /* 0x0000000703057227 */
/* 0x000fe200078e00ff */
/*0130*/ ISETP.GE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f06270 */
/*0140*/ LOP3.LUT R2, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff027a12 */
/* 0x000fe200078e33ff */
/*0150*/ IMAD.MOV R6, RZ, RZ, -R5 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0a05 */
/*0160*/ IMAD R7, R0, R6, R7 ; /* 0x0000000600077224 */
/* 0x000fca00078e0207 */
/*0170*/ ISETP.GT.U32.AND P2, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fda0003f44070 */
/*0180*/ @!P2 IMAD.IADD R7, R7, 0x1, -R0 ; /* 0x000000010707a824 */
/* 0x000fe200078e0a00 */
/*0190*/ @!P2 IADD3 R5, R5, 0x1, RZ ; /* 0x000000010505a810 */
/* 0x000fc80007ffe0ff */
/*01a0*/ ISETP.GE.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f26070 */
/*01b0*/ @P1 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105051810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fc60003f25270 */
/*01d0*/ @!P0 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff058224 */
/* 0x000fca00078e0a05 */
/*01e0*/ SEL R5, R2, R5, !P1 ; /* 0x0000000502057207 */
/* 0x000fc80004800000 */
/*01f0*/ IADD3 R7, -R5, RZ, RZ ; /* 0x000000ff05077210 */
/* 0x000fca0007ffe1ff */
/*0200*/ IMAD R4, R7, c[0x0][0x168], R4 ; /* 0x00005a0007047a24 */
/* 0x000fca00078e0204 */
/*0210*/ IADD3 R4, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fca0007ffe0ff */
/*0220*/ IMAD R5, R5, UR4, R4 ; /* 0x0000000405057c24 */
/* 0x000fca000f8e0204 */
/*0230*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x16c], PT ; /* 0x00005b0005007a0c */
/* 0x000fda0003f06270 */
/*0240*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0250*/ IABS R4, R5 ; /* 0x0000000500047213 */
/* 0x000fe20000000000 */
/*0260*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0270*/ ISETP.GE.AND P2, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc60003f46270 */
/*0280*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fc800078e00ff */
/*0290*/ IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a03 */
/*02a0*/ IMAD R3, R0, R3, R4 ; /* 0x0000000300037224 */
/* 0x000fca00078e0204 */
/*02b0*/ ISETP.GT.U32.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x000fda0003f04070 */
/*02c0*/ @!P0 IMAD.IADD R3, R3, 0x1, -R0 ; /* 0x0000000103038824 */
/* 0x000fca00078e0a00 */
/*02d0*/ ISETP.GT.U32.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x000fda0003f04070 */
/*02e0*/ @!P0 IADD3 R3, R3, -R0, RZ ; /* 0x8000000003038210 */
/* 0x000fca0007ffe0ff */
/*02f0*/ @!P2 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff03a224 */
/* 0x000fca00078e0a03 */
/*0300*/ SEL R2, R2, R3, !P1 ; /* 0x0000000302027207 */
/* 0x000fe20004800000 */
/*0310*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0320*/ LOP3.LUT R2, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff027212 */
/* 0x000fc800078e33ff */
/*0330*/ IADD3 R2, R5.reuse, R2, RZ ; /* 0x0000000205027210 */
/* 0x040fe20007ffe0ff */
/*0340*/ IMAD.WIDE R4, R5, R3, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fc800078e0203 */
/*0350*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e0203 */
/*0360*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000eaa000c1e1900 */
/*0370*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea4000c1e1900 */
/*0380*/ IMAD.IADD R7, R0, 0x1, R3 ; /* 0x0000000100077824 */
/* 0x004fca00078e0203 */
/*0390*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*03a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03b0*/ BRA 0x3b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7ComputePiii
.globl _Z7ComputePiii
.p2align 8
.type _Z7ComputePiii,@function
_Z7ComputePiii:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x8
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_ashr_i32 s6, s4, 31
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s4, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s2, s2, s6
v_cvt_f32_u32_e32 v1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_sub_i32 s3, 0, s2
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s3, v3
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v1, v4
v_xor_b32_e32 v5, v2, v4
v_xor_b32_e32 v4, s6, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v3, v0
v_mul_hi_u32 v0, v5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, s2
v_sub_nc_u32_e32 v3, v5, v3
v_add_nc_u32_e32 v5, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s2, v3
v_cmp_le_u32_e32 vcc_lo, s2, v3
v_dual_cndmask_b32 v3, v3, v6 :: v_dual_cndmask_b32 v0, v0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s2, v3
v_add_nc_u32_e32 v5, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v5, vcc_lo
v_xor_b32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v4
v_mul_lo_u32 v3, v0, s4
v_lshl_or_b32 v4, v0, 1, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v1, v3
v_mad_u64_u32 v[0:1], null, v4, s4, v[3:4]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s5, v0
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v1, 31, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, v0, v1
v_xor_b32_e32 v3, v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v3, v2
v_mul_lo_u32 v2, v2, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v3, v2
v_subrev_nc_u32_e32 v3, s2, v2
v_cmp_le_u32_e32 vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_subrev_nc_u32_e32 v3, s2, v2
v_cmp_le_u32_e32 vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_xor_b32_e32 v2, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v1, v2, v1
v_xad_u32 v2, v1, -1, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_clause 0x1
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7ComputePiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7ComputePiii, .Lfunc_end0-_Z7ComputePiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7ComputePiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7ComputePiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000fafa2_00000000-6_Compute.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z7ComputePiiiPiii
.type _Z28__device_stub__Z7ComputePiiiPiii, @function
_Z28__device_stub__Z7ComputePiiiPiii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7ComputePiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z7ComputePiiiPiii, .-_Z28__device_stub__Z7ComputePiiiPiii
.globl _Z7ComputePiii
.type _Z7ComputePiii, @function
_Z7ComputePiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7ComputePiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7ComputePiii, .-_Z7ComputePiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7ComputePiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7ComputePiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Compute.hip"
.globl _Z22__device_stub__ComputePiii # -- Begin function _Z22__device_stub__ComputePiii
.p2align 4, 0x90
.type _Z22__device_stub__ComputePiii,@function
_Z22__device_stub__ComputePiii: # @_Z22__device_stub__ComputePiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7ComputePiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__ComputePiii, .Lfunc_end0-_Z22__device_stub__ComputePiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7ComputePiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7ComputePiii,@object # @_Z7ComputePiii
.section .rodata,"a",@progbits
.globl _Z7ComputePiii
.p2align 3, 0x0
_Z7ComputePiii:
.quad _Z22__device_stub__ComputePiii
.size _Z7ComputePiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7ComputePiii"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__ComputePiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7ComputePiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //
// main.cpp
//
//
// Created by Elijah Afanasiev on 25.09.2018.
//
//
// System includes
#include <assert.h>
#include <stdio.h>
#include <chrono>
#include <cstdlib>
#include <iostream>
// CUDA runtime
#include <cuda.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#ifndef MAX
#define MAX(a, b) (a > b ? a : b)
#endif
__global__ void vectorAddGPU(float* a, float* b, float* c, int N, int offset) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < N) {
c[offset + idx] = a[offset + idx] + b[offset + idx];
}
}
void sample_vec_add(int size = 1048576) {
int n = size;
int nBytes = n * sizeof(int);
float *a, *b, *c;
a = (float*)malloc(nBytes);
b = (float*)malloc(nBytes);
c = (float*)malloc(nBytes);
float *d_A, *d_B, *d_C;
dim3 block(256);
dim3 grid((unsigned int)ceil(n / (float)block.x));
for (int i = 0; i < n; i++) {
a[i] = rand() / (float)RAND_MAX;
b[i] = rand() / (float)RAND_MAX;
c[i] = 0;
}
cudaMalloc((void**)&d_A, n * sizeof(float));
cudaMalloc((void**)&d_B, n * sizeof(float));
cudaMalloc((void**)&d_C, n * sizeof(float));
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
cudaMemcpy(d_A, a, n * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_B, b, n * sizeof(float), cudaMemcpyHostToDevice);
vectorAddGPU<<<grid, block>>>(d_A, d_B, d_C, n, 0);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("Streams Used: 0\nGPU Elapsed time: %f ms\n", milliseconds);
cudaDeviceSynchronize();
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
}
void streams_vec_add(int size = 1048576) {
int n = size;
int nBytes = n * sizeof(float);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float *a, *b, *c;
cudaHostAlloc((void**)&a, nBytes, cudaHostAllocDefault);
cudaHostAlloc((void**)&b, nBytes, cudaHostAllocDefault);
cudaHostAlloc((void**)&c, nBytes, cudaHostAllocDefault);
float *d_A, *d_B, *d_C;
for (int i = 0; i < n; i++) {
a[i] = rand() / (float)RAND_MAX;
b[i] = rand() / (float)RAND_MAX;
c[i] = 0;
}
cudaMalloc((void**)&d_A, nBytes);
cudaMalloc((void**)&d_B, nBytes);
cudaMalloc((void**)&d_C, nBytes);
cudaEventRecord(start);
const int stream_count = 4;
const int stream_size = n / stream_count;
cudaStream_t Stream[stream_count];
for (int i = 0; i < stream_count; i++)
cudaStreamCreate(&Stream[i]);
dim3 block(1024);
dim3 grid((stream_size - 1) / 1024 + 1);
for (int i = 0; i < stream_count; i++) {
int offset = i * stream_size;
cudaMemcpyAsync(&d_A[offset], &a[offset], stream_size * sizeof(float),
cudaMemcpyHostToDevice, Stream[i]);
cudaMemcpyAsync(&d_B[offset], &b[offset], stream_size * sizeof(float),
cudaMemcpyHostToDevice, Stream[i]);
cudaMemcpyAsync(&d_C[offset], &c[offset], stream_size * sizeof(float),
cudaMemcpyHostToDevice, Stream[i]);
vectorAddGPU<<<grid, block>>>(d_A, d_B, d_C, stream_size, offset);
cudaMemcpyAsync(&a[offset], &d_A[offset], stream_size * sizeof(float),
cudaMemcpyDeviceToHost, Stream[i]);
cudaMemcpyAsync(&b[offset], &d_B[offset], stream_size * sizeof(float),
cudaMemcpyDeviceToHost, Stream[i]);
cudaMemcpyAsync(&c[offset], &d_C[offset], stream_size * sizeof(float),
cudaMemcpyDeviceToHost, Stream[i]);
}
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float msecs = 0;
cudaEventElapsedTime(&msecs, start, stop);
std::cout << "Streams Used: " << stream_count
<< "\nGPU Elapsed Time : " << msecs << " ms.\n";
cudaDeviceSynchronize();
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
cudaFreeHost(a);
cudaFreeHost(b);
cudaFreeHost(c);
}
int main(int argc, char** argv) {
sample_vec_add(atoi(argv[1]));
std::cout << "---------------------\n---------------------\n";
streams_vec_add(atoi(argv[1]));
return 0;
} | code for sm_80
Function : _Z12vectorAddGPUPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ IADD3 R0, R0, c[0x0][0x17c], RZ ; /* 0x00005f0000007a10 */
/* 0x000fe20007ffe0ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00a0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*00e0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00f0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //
// main.cpp
//
//
// Created by Elijah Afanasiev on 25.09.2018.
//
//
// System includes
#include <assert.h>
#include <stdio.h>
#include <chrono>
#include <cstdlib>
#include <iostream>
// CUDA runtime
#include <cuda.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#ifndef MAX
#define MAX(a, b) (a > b ? a : b)
#endif
__global__ void vectorAddGPU(float* a, float* b, float* c, int N, int offset) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < N) {
c[offset + idx] = a[offset + idx] + b[offset + idx];
}
}
void sample_vec_add(int size = 1048576) {
int n = size;
int nBytes = n * sizeof(int);
float *a, *b, *c;
a = (float*)malloc(nBytes);
b = (float*)malloc(nBytes);
c = (float*)malloc(nBytes);
float *d_A, *d_B, *d_C;
dim3 block(256);
dim3 grid((unsigned int)ceil(n / (float)block.x));
for (int i = 0; i < n; i++) {
a[i] = rand() / (float)RAND_MAX;
b[i] = rand() / (float)RAND_MAX;
c[i] = 0;
}
cudaMalloc((void**)&d_A, n * sizeof(float));
cudaMalloc((void**)&d_B, n * sizeof(float));
cudaMalloc((void**)&d_C, n * sizeof(float));
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
cudaMemcpy(d_A, a, n * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_B, b, n * sizeof(float), cudaMemcpyHostToDevice);
vectorAddGPU<<<grid, block>>>(d_A, d_B, d_C, n, 0);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("Streams Used: 0\nGPU Elapsed time: %f ms\n", milliseconds);
cudaDeviceSynchronize();
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
}
void streams_vec_add(int size = 1048576) {
int n = size;
int nBytes = n * sizeof(float);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float *a, *b, *c;
cudaHostAlloc((void**)&a, nBytes, cudaHostAllocDefault);
cudaHostAlloc((void**)&b, nBytes, cudaHostAllocDefault);
cudaHostAlloc((void**)&c, nBytes, cudaHostAllocDefault);
float *d_A, *d_B, *d_C;
for (int i = 0; i < n; i++) {
a[i] = rand() / (float)RAND_MAX;
b[i] = rand() / (float)RAND_MAX;
c[i] = 0;
}
cudaMalloc((void**)&d_A, nBytes);
cudaMalloc((void**)&d_B, nBytes);
cudaMalloc((void**)&d_C, nBytes);
cudaEventRecord(start);
const int stream_count = 4;
const int stream_size = n / stream_count;
cudaStream_t Stream[stream_count];
for (int i = 0; i < stream_count; i++)
cudaStreamCreate(&Stream[i]);
dim3 block(1024);
dim3 grid((stream_size - 1) / 1024 + 1);
for (int i = 0; i < stream_count; i++) {
int offset = i * stream_size;
cudaMemcpyAsync(&d_A[offset], &a[offset], stream_size * sizeof(float),
cudaMemcpyHostToDevice, Stream[i]);
cudaMemcpyAsync(&d_B[offset], &b[offset], stream_size * sizeof(float),
cudaMemcpyHostToDevice, Stream[i]);
cudaMemcpyAsync(&d_C[offset], &c[offset], stream_size * sizeof(float),
cudaMemcpyHostToDevice, Stream[i]);
vectorAddGPU<<<grid, block>>>(d_A, d_B, d_C, stream_size, offset);
cudaMemcpyAsync(&a[offset], &d_A[offset], stream_size * sizeof(float),
cudaMemcpyDeviceToHost, Stream[i]);
cudaMemcpyAsync(&b[offset], &d_B[offset], stream_size * sizeof(float),
cudaMemcpyDeviceToHost, Stream[i]);
cudaMemcpyAsync(&c[offset], &d_C[offset], stream_size * sizeof(float),
cudaMemcpyDeviceToHost, Stream[i]);
}
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float msecs = 0;
cudaEventElapsedTime(&msecs, start, stop);
std::cout << "Streams Used: " << stream_count
<< "\nGPU Elapsed Time : " << msecs << " ms.\n";
cudaDeviceSynchronize();
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
cudaFreeHost(a);
cudaFreeHost(b);
cudaFreeHost(c);
}
int main(int argc, char** argv) {
sample_vec_add(atoi(argv[1]));
std::cout << "---------------------\n---------------------\n";
streams_vec_add(atoi(argv[1]));
return 0;
} | .file "tmpxft_0017be8d_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3773:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3773:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z12vectorAddGPUPfS_S_iiPfS_S_ii
.type _Z38__device_stub__Z12vectorAddGPUPfS_S_iiPfS_S_ii, @function
_Z38__device_stub__Z12vectorAddGPUPfS_S_iiPfS_S_ii:
.LFB3795:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12vectorAddGPUPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3795:
.size _Z38__device_stub__Z12vectorAddGPUPfS_S_iiPfS_S_ii, .-_Z38__device_stub__Z12vectorAddGPUPfS_S_iiPfS_S_ii
.globl _Z12vectorAddGPUPfS_S_ii
.type _Z12vectorAddGPUPfS_S_ii, @function
_Z12vectorAddGPUPfS_S_ii:
.LFB3796:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z12vectorAddGPUPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3796:
.size _Z12vectorAddGPUPfS_S_ii, .-_Z12vectorAddGPUPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Streams Used: "
.LC3:
.string "\nGPU Elapsed Time : "
.LC4:
.string " ms.\n"
.text
.globl _Z15streams_vec_addi
.type _Z15streams_vec_addi, @function
_Z15streams_vec_addi:
.LFB3769:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $168, %rsp
.cfi_def_cfa_offset 224
movl %edi, %r12d
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movslq %edi, %rbp
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leal 0(,%r12,4), %r13d
movslq %r13d, %r13
leaq 40(%rsp), %rdi
movl $0, %edx
movq %r13, %rsi
call cudaHostAlloc@PLT
leaq 48(%rsp), %rdi
movl $0, %edx
movq %r13, %rsi
call cudaHostAlloc@PLT
leaq 56(%rsp), %rdi
movl $0, %edx
movq %r13, %rsi
call cudaHostAlloc@PLT
testl %r12d, %r12d
jle .L12
salq $2, %rbp
movl $0, %ebx
.L13:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movq 40(%rsp), %rax
movss %xmm0, (%rax,%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movq 48(%rsp), %rax
movss %xmm0, (%rax,%rbx)
movq 56(%rsp), %rax
movl $0x00000000, (%rax,%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L13
.L12:
leaq 64(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
leal 3(%r12), %r14d
testl %r12d, %r12d
cmovns %r12d, %r14d
sarl $2, %r14d
leaq 112(%rsp), %rbp
movq %rbp, %rdi
call cudaStreamCreate@PLT
leaq 120(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 128(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 136(%rsp), %rdi
call cudaStreamCreate@PLT
movl $1024, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
leal 1022(%r14), %eax
movl %r14d, %edx
subl $1, %edx
cmovns %edx, %eax
sarl $10, %eax
addl $1, %eax
movl %eax, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movslq %r14d, %r12
salq $2, %r12
leaq 144(%rsp), %rax
movq %rax, 8(%rsp)
movl $0, %r15d
movl $0, %ebx
jmp .L15
.L14:
movq %rbx, %rsi
addq 64(%rsp), %rsi
movq %rbx, %rdi
addq 40(%rsp), %rdi
movq 0(%r13), %r8
movl $2, %ecx
movq %r12, %rdx
call cudaMemcpyAsync@PLT
movq %rbx, %rsi
addq 72(%rsp), %rsi
movq %rbx, %rdi
addq 48(%rsp), %rdi
movq 0(%r13), %r8
movl $2, %ecx
movq %r12, %rdx
call cudaMemcpyAsync@PLT
movq %rbx, %rsi
addq 80(%rsp), %rsi
movq %rbx, %rdi
addq 56(%rsp), %rdi
movq 0(%r13), %r8
movl $2, %ecx
movq %r12, %rdx
call cudaMemcpyAsync@PLT
addq $8, %rbp
addq %r12, %rbx
addl %r14d, %r15d
movq 8(%rsp), %rax
cmpq %rax, %rbp
je .L20
.L15:
movq %rbp, %r13
movq %rbx, %rsi
addq 40(%rsp), %rsi
movq %rbx, %rdi
addq 64(%rsp), %rdi
movq 0(%rbp), %r8
movl $1, %ecx
movq %r12, %rdx
call cudaMemcpyAsync@PLT
movq %rbx, %rsi
addq 48(%rsp), %rsi
movq %rbx, %rdi
addq 72(%rsp), %rdi
movq 0(%rbp), %r8
movl $1, %ecx
movq %r12, %rdx
call cudaMemcpyAsync@PLT
movq %rbx, %rsi
addq 56(%rsp), %rsi
movq %rbx, %rdi
addq 80(%rsp), %rdi
movq 0(%rbp), %r8
movl $1, %ecx
movq %r12, %rdx
call cudaMemcpyAsync@PLT
movl 96(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 88(%rsp), %rdx
movq 100(%rsp), %rdi
movl 108(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L14
movl %r15d, %r8d
movl %r14d, %ecx
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z38__device_stub__Z12vectorAddGPUPfS_S_iiPfS_S_ii
jmp .L14
.L20:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 20(%rsp)
leaq 20(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $14, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $4, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $20, %edx
leaq .LC3(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $5, %edx
leaq .LC4(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
call cudaDeviceSynchronize@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFreeHost@PLT
movq 48(%rsp), %rdi
call cudaFreeHost@PLT
movq 56(%rsp), %rdi
call cudaFreeHost@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3769:
.size _Z15streams_vec_addi, .-_Z15streams_vec_addi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC9:
.string "Streams Used: 0\nGPU Elapsed time: %f ms\n"
.text
.globl _Z14sample_vec_addi
.type _Z14sample_vec_addi, @function
_Z14sample_vec_addi:
.LFB3768:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movl %edi, %r15d
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movslq %edi, %rax
movq %rax, 8(%rsp)
leal 0(,%rdi,4), %ebx
movslq %ebx, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movl $1, 68(%rsp)
movl $1, 72(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %r15d, %xmm0
mulss .LC5(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC10(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC6(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L23
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC8(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L23:
cvttss2siq %xmm3, %rax
movl %eax, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
testl %r15d, %r15d
jle .L24
movq 8(%rsp), %rax
leaq 0(,%rax,4), %r14
movl $0, %ebx
.L25:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, (%r12,%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 0(%rbp,%rbx)
movl $0x00000000, 0(%r13,%rbx)
addq $4, %rbx
cmpq %r14, %rbx
jne .L25
.L24:
movq 8(%rsp), %rbx
salq $2, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 64(%rsp)
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 20(%rsp)
leaq 20(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movl $0, %r8d
movl %r15d, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z38__device_stub__Z12vectorAddGPUPfS_S_iiPfS_S_ii
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3768:
.size _Z14sample_vec_addi, .-_Z14sample_vec_addi
.section .rodata.str1.8
.align 8
.LC11:
.string "---------------------\n---------------------\n"
.text
.globl main
.type main, @function
main:
.LFB3770:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %edi
call _Z14sample_vec_addi
leaq .LC11(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %edi
call _Z15streams_vec_addi
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3770:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z12vectorAddGPUPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3798:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z12vectorAddGPUPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3798:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.align 4
.LC5:
.long 998244352
.align 4
.LC6:
.long 1258291200
.align 4
.LC8:
.long 1065353216
.align 4
.LC10:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //
// main.cpp
//
//
// Created by Elijah Afanasiev on 25.09.2018.
//
//
// System includes
#include <assert.h>
#include <stdio.h>
#include <chrono>
#include <cstdlib>
#include <iostream>
// CUDA runtime
#include <cuda.h>
#include <cuda_runtime.h>
#include <device_launch_parameters.h>
#ifndef MAX
#define MAX(a, b) (a > b ? a : b)
#endif
__global__ void vectorAddGPU(float* a, float* b, float* c, int N, int offset) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < N) {
c[offset + idx] = a[offset + idx] + b[offset + idx];
}
}
void sample_vec_add(int size = 1048576) {
int n = size;
int nBytes = n * sizeof(int);
float *a, *b, *c;
a = (float*)malloc(nBytes);
b = (float*)malloc(nBytes);
c = (float*)malloc(nBytes);
float *d_A, *d_B, *d_C;
dim3 block(256);
dim3 grid((unsigned int)ceil(n / (float)block.x));
for (int i = 0; i < n; i++) {
a[i] = rand() / (float)RAND_MAX;
b[i] = rand() / (float)RAND_MAX;
c[i] = 0;
}
cudaMalloc((void**)&d_A, n * sizeof(float));
cudaMalloc((void**)&d_B, n * sizeof(float));
cudaMalloc((void**)&d_C, n * sizeof(float));
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
cudaMemcpy(d_A, a, n * sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_B, b, n * sizeof(float), cudaMemcpyHostToDevice);
vectorAddGPU<<<grid, block>>>(d_A, d_B, d_C, n, 0);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("Streams Used: 0\nGPU Elapsed time: %f ms\n", milliseconds);
cudaDeviceSynchronize();
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
}
void streams_vec_add(int size = 1048576) {
int n = size;
int nBytes = n * sizeof(float);
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
float *a, *b, *c;
cudaHostAlloc((void**)&a, nBytes, cudaHostAllocDefault);
cudaHostAlloc((void**)&b, nBytes, cudaHostAllocDefault);
cudaHostAlloc((void**)&c, nBytes, cudaHostAllocDefault);
float *d_A, *d_B, *d_C;
for (int i = 0; i < n; i++) {
a[i] = rand() / (float)RAND_MAX;
b[i] = rand() / (float)RAND_MAX;
c[i] = 0;
}
cudaMalloc((void**)&d_A, nBytes);
cudaMalloc((void**)&d_B, nBytes);
cudaMalloc((void**)&d_C, nBytes);
cudaEventRecord(start);
const int stream_count = 4;
const int stream_size = n / stream_count;
cudaStream_t Stream[stream_count];
for (int i = 0; i < stream_count; i++)
cudaStreamCreate(&Stream[i]);
dim3 block(1024);
dim3 grid((stream_size - 1) / 1024 + 1);
for (int i = 0; i < stream_count; i++) {
int offset = i * stream_size;
cudaMemcpyAsync(&d_A[offset], &a[offset], stream_size * sizeof(float),
cudaMemcpyHostToDevice, Stream[i]);
cudaMemcpyAsync(&d_B[offset], &b[offset], stream_size * sizeof(float),
cudaMemcpyHostToDevice, Stream[i]);
cudaMemcpyAsync(&d_C[offset], &c[offset], stream_size * sizeof(float),
cudaMemcpyHostToDevice, Stream[i]);
vectorAddGPU<<<grid, block>>>(d_A, d_B, d_C, stream_size, offset);
cudaMemcpyAsync(&a[offset], &d_A[offset], stream_size * sizeof(float),
cudaMemcpyDeviceToHost, Stream[i]);
cudaMemcpyAsync(&b[offset], &d_B[offset], stream_size * sizeof(float),
cudaMemcpyDeviceToHost, Stream[i]);
cudaMemcpyAsync(&c[offset], &d_C[offset], stream_size * sizeof(float),
cudaMemcpyDeviceToHost, Stream[i]);
}
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float msecs = 0;
cudaEventElapsedTime(&msecs, start, stop);
std::cout << "Streams Used: " << stream_count
<< "\nGPU Elapsed Time : " << msecs << " ms.\n";
cudaDeviceSynchronize();
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
cudaFreeHost(a);
cudaFreeHost(b);
cudaFreeHost(c);
}
int main(int argc, char** argv) {
sample_vec_add(atoi(argv[1]));
std::cout << "---------------------\n---------------------\n";
streams_vec_add(atoi(argv[1]));
return 0;
} | //
// main.cpp
//
//
// Created by Elijah Afanasiev on 25.09.2018.
//
//
// System includes
#include <assert.h>
#include <stdio.h>
#include <chrono>
#include <cstdlib>
#include <iostream>
// CUDA runtime
#include <hip/hip_runtime.h>
#ifndef MAX
#define MAX(a, b) (a > b ? a : b)
#endif
__global__ void vectorAddGPU(float* a, float* b, float* c, int N, int offset) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < N) {
c[offset + idx] = a[offset + idx] + b[offset + idx];
}
}
void sample_vec_add(int size = 1048576) {
int n = size;
int nBytes = n * sizeof(int);
float *a, *b, *c;
a = (float*)malloc(nBytes);
b = (float*)malloc(nBytes);
c = (float*)malloc(nBytes);
float *d_A, *d_B, *d_C;
dim3 block(256);
dim3 grid((unsigned int)ceil(n / (float)block.x));
for (int i = 0; i < n; i++) {
a[i] = rand() / (float)RAND_MAX;
b[i] = rand() / (float)RAND_MAX;
c[i] = 0;
}
hipMalloc((void**)&d_A, n * sizeof(float));
hipMalloc((void**)&d_B, n * sizeof(float));
hipMalloc((void**)&d_C, n * sizeof(float));
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
hipMemcpy(d_A, a, n * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_B, b, n * sizeof(float), hipMemcpyHostToDevice);
vectorAddGPU<<<grid, block>>>(d_A, d_B, d_C, n, 0);
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("Streams Used: 0\nGPU Elapsed time: %f ms\n", milliseconds);
hipDeviceSynchronize();
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
}
void streams_vec_add(int size = 1048576) {
int n = size;
int nBytes = n * sizeof(float);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float *a, *b, *c;
hipHostAlloc((void**)&a, nBytes, hipHostMallocDefault);
hipHostAlloc((void**)&b, nBytes, hipHostMallocDefault);
hipHostAlloc((void**)&c, nBytes, hipHostMallocDefault);
float *d_A, *d_B, *d_C;
for (int i = 0; i < n; i++) {
a[i] = rand() / (float)RAND_MAX;
b[i] = rand() / (float)RAND_MAX;
c[i] = 0;
}
hipMalloc((void**)&d_A, nBytes);
hipMalloc((void**)&d_B, nBytes);
hipMalloc((void**)&d_C, nBytes);
hipEventRecord(start);
const int stream_count = 4;
const int stream_size = n / stream_count;
hipStream_t Stream[stream_count];
for (int i = 0; i < stream_count; i++)
hipStreamCreate(&Stream[i]);
dim3 block(1024);
dim3 grid((stream_size - 1) / 1024 + 1);
for (int i = 0; i < stream_count; i++) {
int offset = i * stream_size;
hipMemcpyAsync(&d_A[offset], &a[offset], stream_size * sizeof(float),
hipMemcpyHostToDevice, Stream[i]);
hipMemcpyAsync(&d_B[offset], &b[offset], stream_size * sizeof(float),
hipMemcpyHostToDevice, Stream[i]);
hipMemcpyAsync(&d_C[offset], &c[offset], stream_size * sizeof(float),
hipMemcpyHostToDevice, Stream[i]);
vectorAddGPU<<<grid, block>>>(d_A, d_B, d_C, stream_size, offset);
hipMemcpyAsync(&a[offset], &d_A[offset], stream_size * sizeof(float),
hipMemcpyDeviceToHost, Stream[i]);
hipMemcpyAsync(&b[offset], &d_B[offset], stream_size * sizeof(float),
hipMemcpyDeviceToHost, Stream[i]);
hipMemcpyAsync(&c[offset], &d_C[offset], stream_size * sizeof(float),
hipMemcpyDeviceToHost, Stream[i]);
}
hipEventRecord(stop);
hipEventSynchronize(stop);
float msecs = 0;
hipEventElapsedTime(&msecs, start, stop);
std::cout << "Streams Used: " << stream_count
<< "\nGPU Elapsed Time : " << msecs << " ms.\n";
hipDeviceSynchronize();
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
hipHostFree(a);
hipHostFree(b);
hipHostFree(c);
}
int main(int argc, char** argv) {
sample_vec_add(atoi(argv[1]));
std::cout << "---------------------\n---------------------\n";
streams_vec_add(atoi(argv[1]));
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //
// main.cpp
//
//
// Created by Elijah Afanasiev on 25.09.2018.
//
//
// System includes
#include <assert.h>
#include <stdio.h>
#include <chrono>
#include <cstdlib>
#include <iostream>
// CUDA runtime
#include <hip/hip_runtime.h>
#ifndef MAX
#define MAX(a, b) (a > b ? a : b)
#endif
__global__ void vectorAddGPU(float* a, float* b, float* c, int N, int offset) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < N) {
c[offset + idx] = a[offset + idx] + b[offset + idx];
}
}
void sample_vec_add(int size = 1048576) {
int n = size;
int nBytes = n * sizeof(int);
float *a, *b, *c;
a = (float*)malloc(nBytes);
b = (float*)malloc(nBytes);
c = (float*)malloc(nBytes);
float *d_A, *d_B, *d_C;
dim3 block(256);
dim3 grid((unsigned int)ceil(n / (float)block.x));
for (int i = 0; i < n; i++) {
a[i] = rand() / (float)RAND_MAX;
b[i] = rand() / (float)RAND_MAX;
c[i] = 0;
}
hipMalloc((void**)&d_A, n * sizeof(float));
hipMalloc((void**)&d_B, n * sizeof(float));
hipMalloc((void**)&d_C, n * sizeof(float));
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
hipMemcpy(d_A, a, n * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_B, b, n * sizeof(float), hipMemcpyHostToDevice);
vectorAddGPU<<<grid, block>>>(d_A, d_B, d_C, n, 0);
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("Streams Used: 0\nGPU Elapsed time: %f ms\n", milliseconds);
hipDeviceSynchronize();
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
}
void streams_vec_add(int size = 1048576) {
int n = size;
int nBytes = n * sizeof(float);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float *a, *b, *c;
hipHostAlloc((void**)&a, nBytes, hipHostMallocDefault);
hipHostAlloc((void**)&b, nBytes, hipHostMallocDefault);
hipHostAlloc((void**)&c, nBytes, hipHostMallocDefault);
float *d_A, *d_B, *d_C;
for (int i = 0; i < n; i++) {
a[i] = rand() / (float)RAND_MAX;
b[i] = rand() / (float)RAND_MAX;
c[i] = 0;
}
hipMalloc((void**)&d_A, nBytes);
hipMalloc((void**)&d_B, nBytes);
hipMalloc((void**)&d_C, nBytes);
hipEventRecord(start);
const int stream_count = 4;
const int stream_size = n / stream_count;
hipStream_t Stream[stream_count];
for (int i = 0; i < stream_count; i++)
hipStreamCreate(&Stream[i]);
dim3 block(1024);
dim3 grid((stream_size - 1) / 1024 + 1);
for (int i = 0; i < stream_count; i++) {
int offset = i * stream_size;
hipMemcpyAsync(&d_A[offset], &a[offset], stream_size * sizeof(float),
hipMemcpyHostToDevice, Stream[i]);
hipMemcpyAsync(&d_B[offset], &b[offset], stream_size * sizeof(float),
hipMemcpyHostToDevice, Stream[i]);
hipMemcpyAsync(&d_C[offset], &c[offset], stream_size * sizeof(float),
hipMemcpyHostToDevice, Stream[i]);
vectorAddGPU<<<grid, block>>>(d_A, d_B, d_C, stream_size, offset);
hipMemcpyAsync(&a[offset], &d_A[offset], stream_size * sizeof(float),
hipMemcpyDeviceToHost, Stream[i]);
hipMemcpyAsync(&b[offset], &d_B[offset], stream_size * sizeof(float),
hipMemcpyDeviceToHost, Stream[i]);
hipMemcpyAsync(&c[offset], &d_C[offset], stream_size * sizeof(float),
hipMemcpyDeviceToHost, Stream[i]);
}
hipEventRecord(stop);
hipEventSynchronize(stop);
float msecs = 0;
hipEventElapsedTime(&msecs, start, stop);
std::cout << "Streams Used: " << stream_count
<< "\nGPU Elapsed Time : " << msecs << " ms.\n";
hipDeviceSynchronize();
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
hipHostFree(a);
hipHostFree(b);
hipHostFree(c);
}
int main(int argc, char** argv) {
sample_vec_add(atoi(argv[1]));
std::cout << "---------------------\n---------------------\n";
streams_vec_add(atoi(argv[1]));
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12vectorAddGPUPfS_S_ii
.globl _Z12vectorAddGPUPfS_S_ii
.p2align 8
.type _Z12vectorAddGPUPfS_S_ii,@function
_Z12vectorAddGPUPfS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x2
s_load_b32 s2, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12vectorAddGPUPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12vectorAddGPUPfS_S_ii, .Lfunc_end0-_Z12vectorAddGPUPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12vectorAddGPUPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12vectorAddGPUPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //
// main.cpp
//
//
// Created by Elijah Afanasiev on 25.09.2018.
//
//
// System includes
#include <assert.h>
#include <stdio.h>
#include <chrono>
#include <cstdlib>
#include <iostream>
// CUDA runtime
#include <hip/hip_runtime.h>
#ifndef MAX
#define MAX(a, b) (a > b ? a : b)
#endif
__global__ void vectorAddGPU(float* a, float* b, float* c, int N, int offset) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < N) {
c[offset + idx] = a[offset + idx] + b[offset + idx];
}
}
void sample_vec_add(int size = 1048576) {
int n = size;
int nBytes = n * sizeof(int);
float *a, *b, *c;
a = (float*)malloc(nBytes);
b = (float*)malloc(nBytes);
c = (float*)malloc(nBytes);
float *d_A, *d_B, *d_C;
dim3 block(256);
dim3 grid((unsigned int)ceil(n / (float)block.x));
for (int i = 0; i < n; i++) {
a[i] = rand() / (float)RAND_MAX;
b[i] = rand() / (float)RAND_MAX;
c[i] = 0;
}
hipMalloc((void**)&d_A, n * sizeof(float));
hipMalloc((void**)&d_B, n * sizeof(float));
hipMalloc((void**)&d_C, n * sizeof(float));
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
hipMemcpy(d_A, a, n * sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_B, b, n * sizeof(float), hipMemcpyHostToDevice);
vectorAddGPU<<<grid, block>>>(d_A, d_B, d_C, n, 0);
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("Streams Used: 0\nGPU Elapsed time: %f ms\n", milliseconds);
hipDeviceSynchronize();
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
}
void streams_vec_add(int size = 1048576) {
int n = size;
int nBytes = n * sizeof(float);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
float *a, *b, *c;
hipHostAlloc((void**)&a, nBytes, hipHostMallocDefault);
hipHostAlloc((void**)&b, nBytes, hipHostMallocDefault);
hipHostAlloc((void**)&c, nBytes, hipHostMallocDefault);
float *d_A, *d_B, *d_C;
for (int i = 0; i < n; i++) {
a[i] = rand() / (float)RAND_MAX;
b[i] = rand() / (float)RAND_MAX;
c[i] = 0;
}
hipMalloc((void**)&d_A, nBytes);
hipMalloc((void**)&d_B, nBytes);
hipMalloc((void**)&d_C, nBytes);
hipEventRecord(start);
const int stream_count = 4;
const int stream_size = n / stream_count;
hipStream_t Stream[stream_count];
for (int i = 0; i < stream_count; i++)
hipStreamCreate(&Stream[i]);
dim3 block(1024);
dim3 grid((stream_size - 1) / 1024 + 1);
for (int i = 0; i < stream_count; i++) {
int offset = i * stream_size;
hipMemcpyAsync(&d_A[offset], &a[offset], stream_size * sizeof(float),
hipMemcpyHostToDevice, Stream[i]);
hipMemcpyAsync(&d_B[offset], &b[offset], stream_size * sizeof(float),
hipMemcpyHostToDevice, Stream[i]);
hipMemcpyAsync(&d_C[offset], &c[offset], stream_size * sizeof(float),
hipMemcpyHostToDevice, Stream[i]);
vectorAddGPU<<<grid, block>>>(d_A, d_B, d_C, stream_size, offset);
hipMemcpyAsync(&a[offset], &d_A[offset], stream_size * sizeof(float),
hipMemcpyDeviceToHost, Stream[i]);
hipMemcpyAsync(&b[offset], &d_B[offset], stream_size * sizeof(float),
hipMemcpyDeviceToHost, Stream[i]);
hipMemcpyAsync(&c[offset], &d_C[offset], stream_size * sizeof(float),
hipMemcpyDeviceToHost, Stream[i]);
}
hipEventRecord(stop);
hipEventSynchronize(stop);
float msecs = 0;
hipEventElapsedTime(&msecs, start, stop);
std::cout << "Streams Used: " << stream_count
<< "\nGPU Elapsed Time : " << msecs << " ms.\n";
hipDeviceSynchronize();
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
hipHostFree(a);
hipHostFree(b);
hipHostFree(c);
}
int main(int argc, char** argv) {
sample_vec_add(atoi(argv[1]));
std::cout << "---------------------\n---------------------\n";
streams_vec_add(atoi(argv[1]));
return 0;
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__vectorAddGPUPfS_S_ii # -- Begin function _Z27__device_stub__vectorAddGPUPfS_S_ii
.p2align 4, 0x90
.type _Z27__device_stub__vectorAddGPUPfS_S_ii,@function
_Z27__device_stub__vectorAddGPUPfS_S_ii: # @_Z27__device_stub__vectorAddGPUPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12vectorAddGPUPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__vectorAddGPUPfS_S_ii, .Lfunc_end0-_Z27__device_stub__vectorAddGPUPfS_S_ii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z14sample_vec_addi
.LCPI1_0:
.long 0x3b800000 # float 0.00390625
.LCPI1_1:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z14sample_vec_addi
.p2align 4, 0x90
.type _Z14sample_vec_addi,@function
_Z14sample_vec_addi: # @_Z14sample_vec_addi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967296, %r14 # imm = 0x100000000
movl %edi, 4(%rsp) # 4-byte Spill
movslq %edi, %rbx
leaq (,%rbx,4), %r15
movq %rbx, %r13
shlq $34, %r13
sarq $32, %r13
movq %r13, %rdi
callq malloc
movq %rax, %r12
movq %r13, %rdi
callq malloc
cvtsi2ss %ebx, %xmm0
movq %rax, %r13
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rax
movl %eax, %ebp
orq %r14, %rbp
testl %ebx, %ebx
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl 4(%rsp), %ebx # 4-byte Reload
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, (%r12,%r14,4)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_1(%rip), %xmm0
movss %xmm0, (%r13,%r14,4)
incq %r14
cmpq %r14, %rbx
jne .LBB1_2
.LBB1_3: # %._crit_edge
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
movq %r12, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967296, %rdx # imm = 0x100000000
addq $256, %rdx # imm = 0x100
movq %rbp, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 48(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl 4(%rsp), %eax # 4-byte Reload
movl %eax, 36(%rsp)
movl $0, 32(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z12vectorAddGPUPfS_S_ii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $0, 128(%rsp)
movq 40(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
callq hipDeviceSynchronize
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z14sample_vec_addi, .Lfunc_end1-_Z14sample_vec_addi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z15streams_vec_addi
.LCPI2_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z15streams_vec_addi
.p2align 4, 0x90
.type _Z15streams_vec_addi,@function
_Z15streams_vec_addi: # @_Z15streams_vec_addi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %ebx
leal (,%rbx,4), %ebp
leaq 72(%rsp), %rdi
callq hipEventCreate
leaq 56(%rsp), %rdi
callq hipEventCreate
movslq %ebp, %r14
leaq 48(%rsp), %rdi
movq %r14, %rsi
xorl %edx, %edx
callq hipHostAlloc
leaq 40(%rsp), %rdi
movq %r14, %rsi
xorl %edx, %edx
callq hipHostAlloc
leaq 32(%rsp), %rdi
movq %r14, %rsi
xorl %edx, %edx
callq hipHostAlloc
testl %ebx, %ebx
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl %ebx, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movq 48(%rsp), %rax
movss %xmm0, (%rax,%r12,4)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI2_0(%rip), %xmm0
movq 40(%rsp), %rax
movss %xmm0, (%rax,%r12,4)
movq 32(%rsp), %rax
movl $0, (%rax,%r12,4)
incq %r12
cmpq %r12, %r15
jne .LBB2_2
.LBB2_3: # %._crit_edge
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 72(%rsp), %rdi
xorl %r14d, %r14d
xorl %esi, %esi
callq hipEventRecord
.p2align 4, 0x90
.LBB2_4: # =>This Inner Loop Header: Depth=1
leaq (%rsp,%r14), %rdi
addq $208, %rdi
callq hipStreamCreate
addq $8, %r14
cmpq $32, %r14
jne .LBB2_4
# %bb.5:
leal 3(%rbx), %ebp
testl %ebx, %ebx
cmovnsl %ebx, %ebp
sarl $2, %ebp
leal -1(%rbp), %eax
leal 1022(%rbp), %ebx
testl %eax, %eax
cmovnsl %eax, %ebx
movabsq $4294967296, %rax # imm = 0x100000000
sarl $10, %ebx
incl %ebx
orq %rax, %rbx
movslq %ebp, %r15
shlq $2, %r15
xorl %r12d, %r12d
addq $1024, %rax # imm = 0x400
movq %rax, 80(%rsp) # 8-byte Spill
xorl %r13d, %r13d
xorl %r14d, %r14d
jmp .LBB2_6
.p2align 4, 0x90
.LBB2_8: # in Loop: Header=BB2_6 Depth=1
movq 48(%rsp), %rdi
addq %r12, %rdi
movq 24(%rsp), %rsi
addq %r12, %rsi
movq 208(%rsp,%r14,8), %r8
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpyAsync
movq 40(%rsp), %rdi
addq %r12, %rdi
movq 16(%rsp), %rsi
addq %r12, %rsi
movq 208(%rsp,%r14,8), %r8
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpyAsync
movq 32(%rsp), %rdi
addq %r12, %rdi
movq 8(%rsp), %rsi
addq %r12, %rsi
movq 208(%rsp,%r14,8), %r8
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpyAsync
incq %r14
addl %ebp, %r13d
addq %r15, %r12
cmpq $4, %r14
je .LBB2_9
.LBB2_6: # =>This Inner Loop Header: Depth=1
movq 24(%rsp), %rdi
addq %r12, %rdi
movq 48(%rsp), %rsi
addq %r12, %rsi
movq 208(%rsp,%r14,8), %r8
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpyAsync
movq 16(%rsp), %rdi
addq %r12, %rdi
movq 40(%rsp), %rsi
addq %r12, %rsi
movq 208(%rsp,%r14,8), %r8
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpyAsync
movq 8(%rsp), %rdi
addq %r12, %rdi
movq 32(%rsp), %rsi
addq %r12, %rsi
movq 208(%rsp,%r14,8), %r8
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpyAsync
movq %rbx, %rdi
movl $1, %esi
movq 80(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7: # in Loop: Header=BB2_6 Depth=1
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movl %ebp, 68(%rsp)
movl %r13d, 64(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 68(%rsp), %rax
movq %rax, 184(%rsp)
leaq 64(%rsp), %rax
movq %rax, 192(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
movl $_Z12vectorAddGPUPfS_S_ii, %edi
leaq 160(%rsp), %r9
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_8
.LBB2_9:
movq 56(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 56(%rsp), %rdi
callq hipEventSynchronize
movl $0, 160(%rsp)
movq 72(%rsp), %rsi
movq 56(%rsp), %rdx
leaq 160(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $4, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.2, %esi
movl $20, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 160(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.3, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
callq hipDeviceSynchronize
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipHostFree
movq 40(%rsp), %rdi
callq hipHostFree
movq 32(%rsp), %rdi
callq hipHostFree
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z15streams_vec_addi, .Lfunc_end2-_Z15streams_vec_addi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, %edi
callq _Z14sample_vec_addi
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $44, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, %edi
callq _Z15streams_vec_addi
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12vectorAddGPUPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12vectorAddGPUPfS_S_ii,@object # @_Z12vectorAddGPUPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z12vectorAddGPUPfS_S_ii
.p2align 3, 0x0
_Z12vectorAddGPUPfS_S_ii:
.quad _Z27__device_stub__vectorAddGPUPfS_S_ii
.size _Z12vectorAddGPUPfS_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Streams Used: 0\nGPU Elapsed time: %f ms\n"
.size .L.str, 41
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Streams Used: "
.size .L.str.1, 15
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nGPU Elapsed Time : "
.size .L.str.2, 21
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " ms.\n"
.size .L.str.3, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "---------------------\n---------------------\n"
.size .L.str.4, 45
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12vectorAddGPUPfS_S_ii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__vectorAddGPUPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12vectorAddGPUPfS_S_ii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12vectorAddGPUPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ IADD3 R0, R0, c[0x0][0x17c], RZ ; /* 0x00005f0000007a10 */
/* 0x000fe20007ffe0ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00a0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*00e0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00f0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12vectorAddGPUPfS_S_ii
.globl _Z12vectorAddGPUPfS_S_ii
.p2align 8
.type _Z12vectorAddGPUPfS_S_ii,@function
_Z12vectorAddGPUPfS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x2
s_load_b32 s2, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12vectorAddGPUPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12vectorAddGPUPfS_S_ii, .Lfunc_end0-_Z12vectorAddGPUPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12vectorAddGPUPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12vectorAddGPUPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017be8d_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3773:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3773:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z12vectorAddGPUPfS_S_iiPfS_S_ii
.type _Z38__device_stub__Z12vectorAddGPUPfS_S_iiPfS_S_ii, @function
_Z38__device_stub__Z12vectorAddGPUPfS_S_iiPfS_S_ii:
.LFB3795:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12vectorAddGPUPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3795:
.size _Z38__device_stub__Z12vectorAddGPUPfS_S_iiPfS_S_ii, .-_Z38__device_stub__Z12vectorAddGPUPfS_S_iiPfS_S_ii
.globl _Z12vectorAddGPUPfS_S_ii
.type _Z12vectorAddGPUPfS_S_ii, @function
_Z12vectorAddGPUPfS_S_ii:
.LFB3796:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z12vectorAddGPUPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3796:
.size _Z12vectorAddGPUPfS_S_ii, .-_Z12vectorAddGPUPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Streams Used: "
.LC3:
.string "\nGPU Elapsed Time : "
.LC4:
.string " ms.\n"
.text
.globl _Z15streams_vec_addi
.type _Z15streams_vec_addi, @function
_Z15streams_vec_addi:
.LFB3769:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $168, %rsp
.cfi_def_cfa_offset 224
movl %edi, %r12d
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movslq %edi, %rbp
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leal 0(,%r12,4), %r13d
movslq %r13d, %r13
leaq 40(%rsp), %rdi
movl $0, %edx
movq %r13, %rsi
call cudaHostAlloc@PLT
leaq 48(%rsp), %rdi
movl $0, %edx
movq %r13, %rsi
call cudaHostAlloc@PLT
leaq 56(%rsp), %rdi
movl $0, %edx
movq %r13, %rsi
call cudaHostAlloc@PLT
testl %r12d, %r12d
jle .L12
salq $2, %rbp
movl $0, %ebx
.L13:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movq 40(%rsp), %rax
movss %xmm0, (%rax,%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movq 48(%rsp), %rax
movss %xmm0, (%rax,%rbx)
movq 56(%rsp), %rax
movl $0x00000000, (%rax,%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L13
.L12:
leaq 64(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
leal 3(%r12), %r14d
testl %r12d, %r12d
cmovns %r12d, %r14d
sarl $2, %r14d
leaq 112(%rsp), %rbp
movq %rbp, %rdi
call cudaStreamCreate@PLT
leaq 120(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 128(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 136(%rsp), %rdi
call cudaStreamCreate@PLT
movl $1024, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
leal 1022(%r14), %eax
movl %r14d, %edx
subl $1, %edx
cmovns %edx, %eax
sarl $10, %eax
addl $1, %eax
movl %eax, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movslq %r14d, %r12
salq $2, %r12
leaq 144(%rsp), %rax
movq %rax, 8(%rsp)
movl $0, %r15d
movl $0, %ebx
jmp .L15
.L14:
movq %rbx, %rsi
addq 64(%rsp), %rsi
movq %rbx, %rdi
addq 40(%rsp), %rdi
movq 0(%r13), %r8
movl $2, %ecx
movq %r12, %rdx
call cudaMemcpyAsync@PLT
movq %rbx, %rsi
addq 72(%rsp), %rsi
movq %rbx, %rdi
addq 48(%rsp), %rdi
movq 0(%r13), %r8
movl $2, %ecx
movq %r12, %rdx
call cudaMemcpyAsync@PLT
movq %rbx, %rsi
addq 80(%rsp), %rsi
movq %rbx, %rdi
addq 56(%rsp), %rdi
movq 0(%r13), %r8
movl $2, %ecx
movq %r12, %rdx
call cudaMemcpyAsync@PLT
addq $8, %rbp
addq %r12, %rbx
addl %r14d, %r15d
movq 8(%rsp), %rax
cmpq %rax, %rbp
je .L20
.L15:
movq %rbp, %r13
movq %rbx, %rsi
addq 40(%rsp), %rsi
movq %rbx, %rdi
addq 64(%rsp), %rdi
movq 0(%rbp), %r8
movl $1, %ecx
movq %r12, %rdx
call cudaMemcpyAsync@PLT
movq %rbx, %rsi
addq 48(%rsp), %rsi
movq %rbx, %rdi
addq 72(%rsp), %rdi
movq 0(%rbp), %r8
movl $1, %ecx
movq %r12, %rdx
call cudaMemcpyAsync@PLT
movq %rbx, %rsi
addq 56(%rsp), %rsi
movq %rbx, %rdi
addq 80(%rsp), %rdi
movq 0(%rbp), %r8
movl $1, %ecx
movq %r12, %rdx
call cudaMemcpyAsync@PLT
movl 96(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 88(%rsp), %rdx
movq 100(%rsp), %rdi
movl 108(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L14
movl %r15d, %r8d
movl %r14d, %ecx
movq 80(%rsp), %rdx
movq 72(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z38__device_stub__Z12vectorAddGPUPfS_S_iiPfS_S_ii
jmp .L14
.L20:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 20(%rsp)
leaq 20(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $14, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $4, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $20, %edx
leaq .LC3(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $5, %edx
leaq .LC4(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
call cudaDeviceSynchronize@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFreeHost@PLT
movq 48(%rsp), %rdi
call cudaFreeHost@PLT
movq 56(%rsp), %rdi
call cudaFreeHost@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3769:
.size _Z15streams_vec_addi, .-_Z15streams_vec_addi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC9:
.string "Streams Used: 0\nGPU Elapsed time: %f ms\n"
.text
.globl _Z14sample_vec_addi
.type _Z14sample_vec_addi, @function
_Z14sample_vec_addi:
.LFB3768:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movl %edi, %r15d
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movslq %edi, %rax
movq %rax, 8(%rsp)
leal 0(,%rdi,4), %ebx
movslq %ebx, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movl $1, 68(%rsp)
movl $1, 72(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %r15d, %xmm0
mulss .LC5(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC10(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC6(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L23
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC8(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L23:
cvttss2siq %xmm3, %rax
movl %eax, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
testl %r15d, %r15d
jle .L24
movq 8(%rsp), %rax
leaq 0(,%rax,4), %r14
movl $0, %ebx
.L25:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, (%r12,%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 0(%rbp,%rbx)
movl $0x00000000, 0(%r13,%rbx)
addq $4, %rbx
cmpq %r14, %rbx
jne .L25
.L24:
movq 8(%rsp), %rbx
salq $2, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 64(%rsp)
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 20(%rsp)
leaq 20(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 20(%rsp), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movl $0, %r8d
movl %r15d, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z38__device_stub__Z12vectorAddGPUPfS_S_iiPfS_S_ii
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3768:
.size _Z14sample_vec_addi, .-_Z14sample_vec_addi
.section .rodata.str1.8
.align 8
.LC11:
.string "---------------------\n---------------------\n"
.text
.globl main
.type main, @function
main:
.LFB3770:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %edi
call _Z14sample_vec_addi
leaq .LC11(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %edi
call _Z15streams_vec_addi
movl $0, %eax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3770:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z12vectorAddGPUPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3798:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z12vectorAddGPUPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3798:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.align 4
.LC5:
.long 998244352
.align 4
.LC6:
.long 1258291200
.align 4
.LC8:
.long 1065353216
.align 4
.LC10:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__vectorAddGPUPfS_S_ii # -- Begin function _Z27__device_stub__vectorAddGPUPfS_S_ii
.p2align 4, 0x90
.type _Z27__device_stub__vectorAddGPUPfS_S_ii,@function
_Z27__device_stub__vectorAddGPUPfS_S_ii: # @_Z27__device_stub__vectorAddGPUPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12vectorAddGPUPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__vectorAddGPUPfS_S_ii, .Lfunc_end0-_Z27__device_stub__vectorAddGPUPfS_S_ii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z14sample_vec_addi
.LCPI1_0:
.long 0x3b800000 # float 0.00390625
.LCPI1_1:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z14sample_vec_addi
.p2align 4, 0x90
.type _Z14sample_vec_addi,@function
_Z14sample_vec_addi: # @_Z14sample_vec_addi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967296, %r14 # imm = 0x100000000
movl %edi, 4(%rsp) # 4-byte Spill
movslq %edi, %rbx
leaq (,%rbx,4), %r15
movq %rbx, %r13
shlq $34, %r13
sarq $32, %r13
movq %r13, %rdi
callq malloc
movq %rax, %r12
movq %r13, %rdi
callq malloc
cvtsi2ss %ebx, %xmm0
movq %rax, %r13
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rax
movl %eax, %ebp
orq %r14, %rbp
testl %ebx, %ebx
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl 4(%rsp), %ebx # 4-byte Reload
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, (%r12,%r14,4)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_1(%rip), %xmm0
movss %xmm0, (%r13,%r14,4)
incq %r14
cmpq %r14, %rbx
jne .LBB1_2
.LBB1_3: # %._crit_edge
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 48(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
movq %r12, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967296, %rdx # imm = 0x100000000
addq $256, %rdx # imm = 0x100
movq %rbp, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 48(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl 4(%rsp), %eax # 4-byte Reload
movl %eax, 36(%rsp)
movl $0, 32(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z12vectorAddGPUPfS_S_ii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $0, 128(%rsp)
movq 40(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
callq hipDeviceSynchronize
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z14sample_vec_addi, .Lfunc_end1-_Z14sample_vec_addi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z15streams_vec_addi
.LCPI2_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z15streams_vec_addi
.p2align 4, 0x90
.type _Z15streams_vec_addi,@function
_Z15streams_vec_addi: # @_Z15streams_vec_addi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %ebx
leal (,%rbx,4), %ebp
leaq 72(%rsp), %rdi
callq hipEventCreate
leaq 56(%rsp), %rdi
callq hipEventCreate
movslq %ebp, %r14
leaq 48(%rsp), %rdi
movq %r14, %rsi
xorl %edx, %edx
callq hipHostAlloc
leaq 40(%rsp), %rdi
movq %r14, %rsi
xorl %edx, %edx
callq hipHostAlloc
leaq 32(%rsp), %rdi
movq %r14, %rsi
xorl %edx, %edx
callq hipHostAlloc
testl %ebx, %ebx
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl %ebx, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movq 48(%rsp), %rax
movss %xmm0, (%rax,%r12,4)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI2_0(%rip), %xmm0
movq 40(%rsp), %rax
movss %xmm0, (%rax,%r12,4)
movq 32(%rsp), %rax
movl $0, (%rax,%r12,4)
incq %r12
cmpq %r12, %r15
jne .LBB2_2
.LBB2_3: # %._crit_edge
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 72(%rsp), %rdi
xorl %r14d, %r14d
xorl %esi, %esi
callq hipEventRecord
.p2align 4, 0x90
.LBB2_4: # =>This Inner Loop Header: Depth=1
leaq (%rsp,%r14), %rdi
addq $208, %rdi
callq hipStreamCreate
addq $8, %r14
cmpq $32, %r14
jne .LBB2_4
# %bb.5:
leal 3(%rbx), %ebp
testl %ebx, %ebx
cmovnsl %ebx, %ebp
sarl $2, %ebp
leal -1(%rbp), %eax
leal 1022(%rbp), %ebx
testl %eax, %eax
cmovnsl %eax, %ebx
movabsq $4294967296, %rax # imm = 0x100000000
sarl $10, %ebx
incl %ebx
orq %rax, %rbx
movslq %ebp, %r15
shlq $2, %r15
xorl %r12d, %r12d
addq $1024, %rax # imm = 0x400
movq %rax, 80(%rsp) # 8-byte Spill
xorl %r13d, %r13d
xorl %r14d, %r14d
jmp .LBB2_6
.p2align 4, 0x90
.LBB2_8: # in Loop: Header=BB2_6 Depth=1
movq 48(%rsp), %rdi
addq %r12, %rdi
movq 24(%rsp), %rsi
addq %r12, %rsi
movq 208(%rsp,%r14,8), %r8
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpyAsync
movq 40(%rsp), %rdi
addq %r12, %rdi
movq 16(%rsp), %rsi
addq %r12, %rsi
movq 208(%rsp,%r14,8), %r8
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpyAsync
movq 32(%rsp), %rdi
addq %r12, %rdi
movq 8(%rsp), %rsi
addq %r12, %rsi
movq 208(%rsp,%r14,8), %r8
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpyAsync
incq %r14
addl %ebp, %r13d
addq %r15, %r12
cmpq $4, %r14
je .LBB2_9
.LBB2_6: # =>This Inner Loop Header: Depth=1
movq 24(%rsp), %rdi
addq %r12, %rdi
movq 48(%rsp), %rsi
addq %r12, %rsi
movq 208(%rsp,%r14,8), %r8
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpyAsync
movq 16(%rsp), %rdi
addq %r12, %rdi
movq 40(%rsp), %rsi
addq %r12, %rsi
movq 208(%rsp,%r14,8), %r8
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpyAsync
movq 8(%rsp), %rdi
addq %r12, %rdi
movq 32(%rsp), %rsi
addq %r12, %rsi
movq 208(%rsp,%r14,8), %r8
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpyAsync
movq %rbx, %rdi
movl $1, %esi
movq 80(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7: # in Loop: Header=BB2_6 Depth=1
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movl %ebp, 68(%rsp)
movl %r13d, 64(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 68(%rsp), %rax
movq %rax, 184(%rsp)
leaq 64(%rsp), %rax
movq %rax, 192(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
movl $_Z12vectorAddGPUPfS_S_ii, %edi
leaq 160(%rsp), %r9
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_8
.LBB2_9:
movq 56(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 56(%rsp), %rdi
callq hipEventSynchronize
movl $0, 160(%rsp)
movq 72(%rsp), %rsi
movq 56(%rsp), %rdx
leaq 160(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $4, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.2, %esi
movl $20, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 160(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.3, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
callq hipDeviceSynchronize
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipHostFree
movq 40(%rsp), %rdi
callq hipHostFree
movq 32(%rsp), %rdi
callq hipHostFree
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z15streams_vec_addi, .Lfunc_end2-_Z15streams_vec_addi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, %edi
callq _Z14sample_vec_addi
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $44, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, %edi
callq _Z15streams_vec_addi
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12vectorAddGPUPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12vectorAddGPUPfS_S_ii,@object # @_Z12vectorAddGPUPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z12vectorAddGPUPfS_S_ii
.p2align 3, 0x0
_Z12vectorAddGPUPfS_S_ii:
.quad _Z27__device_stub__vectorAddGPUPfS_S_ii
.size _Z12vectorAddGPUPfS_S_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Streams Used: 0\nGPU Elapsed time: %f ms\n"
.size .L.str, 41
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Streams Used: "
.size .L.str.1, 15
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\nGPU Elapsed Time : "
.size .L.str.2, 21
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " ms.\n"
.size .L.str.3, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "---------------------\n---------------------\n"
.size .L.str.4, 45
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12vectorAddGPUPfS_S_ii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__vectorAddGPUPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12vectorAddGPUPfS_S_ii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /******************************************************************
File : lcsBigBlockInitializationForPositions.cu
Author : Mingcheng Chen
Last Update : January 31st, 2013
*******************************************************************/
#include <stdio.h>
#define BLOCK_SIZE 512
__global__ void BigBlockInitializationForPositionsKernel(double *globalVertexPositions,
int *blockedGlobalPointIDs,
int *startOffsetInPoint,
double *vertexPositionsForBig
) {
// Get number of threads in a work group
int numOfThreads = blockDim.x;
// Get local thread ID
int localID = threadIdx.x;
// Get interesting block ID of the current big block
int interestingBlockID = blockIdx.x;
// Declare some work arrays
double *gVertexPositions;
int startPoint = startOffsetInPoint[interestingBlockID];
int numOfPoints = startOffsetInPoint[interestingBlockID + 1] - startPoint;
// Initialize vertexPositions
gVertexPositions = vertexPositionsForBig + startPoint * 3;
for (int i = localID; i < numOfPoints * 3; i += numOfThreads) {
int localPointID = i / 3;
int dimensionID = i % 3;
int globalPointID = blockedGlobalPointIDs[startPoint + localPointID];
gVertexPositions[i] = globalVertexPositions[globalPointID * 3 + dimensionID];
}
}
extern "C"
void BigBlockInitializationForPositions(double *globalVertexPositions,
int *blockedGlobalPointIDs,
int *startOffsetInPoint,
double *vertexPositionsForBig,
int numOfInterestingBlocks
) {
dim3 dimBlock(BLOCK_SIZE, 1, 1);
dim3 dimGrid(numOfInterestingBlocks, 1, 1);
BigBlockInitializationForPositionsKernel<<<dimGrid, dimBlock>>>(globalVertexPositions, blockedGlobalPointIDs,
startOffsetInPoint, vertexPositionsForBig);
cudaError_t err = cudaDeviceSynchronize();
if (err) {
cudaGetErrorString(err);
exit(0);
}
} | code for sm_80
Function : _Z40BigBlockInitializationForPositionsKernelPdPiS0_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R4, R5, R0, c[0x0][0x170] ; /* 0x00005c0005047625 */
/* 0x001fca00078e0200 */
/*0050*/ LDG.E R3, [R4.64+0x4] ; /* 0x0000040404037981 */
/* 0x000ea8000c1e1900 */
/*0060*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0080*/ IMAD.IADD R3, R3, 0x1, -R2 ; /* 0x0000000103037824 */
/* 0x004fc800078e0a02 */
/*0090*/ IMAD R3, R3, 0x3, RZ ; /* 0x0000000303037824 */
/* 0x000fca00078e02ff */
/*00a0*/ ISETP.GE.AND P0, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x001fda0003f06270 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ I2F.U32.RP R7, c[0x0][0x0] ; /* 0x0000000000077b06 */
/* 0x000e220000209000 */
/*00d0*/ LOP3.LUT R6, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff067212 */
/* 0x000fe200078e33ff */
/*00e0*/ BSSY B0, 0x3f0 ; /* 0x0000030000007945 */
/* 0x000fe20003800000 */
/*00f0*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fe40003f45070 */
/*0100*/ IADD3 R6, R3, R6, RZ ; /* 0x0000000603067210 */
/* 0x000fc60007ffe0ff */
/*0110*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e240000001000 */
/*0120*/ IADD3 R4, R7, 0xffffffe, RZ ; /* 0x0ffffffe07047810 */
/* 0x001fcc0007ffe0ff */
/*0130*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0140*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe200078e00ff */
/*0150*/ IADD3 R9, RZ, -R5, RZ ; /* 0x80000005ff097210 */
/* 0x002fca0007ffe0ff */
/*0160*/ IMAD R9, R9, c[0x0][0x0], RZ ; /* 0x0000000009097a24 */
/* 0x000fc800078e02ff */
/*0170*/ IMAD.HI.U32 R5, R5, R9, R4 ; /* 0x0000000905057227 */
/* 0x000fcc00078e0004 */
/*0180*/ IMAD.HI.U32 R5, R5, R6, RZ ; /* 0x0000000605057227 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD.MOV R7, RZ, RZ, -R5 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0a05 */
/*01a0*/ IMAD R6, R7, c[0x0][0x0], R6 ; /* 0x0000000007067a24 */
/* 0x000fca00078e0206 */
/*01b0*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x0], PT ; /* 0x0000000006007a0c */
/* 0x000fda0003f06070 */
/*01c0*/ @P0 IADD3 R6, R6, -c[0x0][0x0], RZ ; /* 0x8000000006060a10 */
/* 0x000fe40007ffe0ff */
/*01d0*/ @P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105050810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.GE.U32.AND P1, PT, R6, c[0x0][0x0], PT ; /* 0x0000000006007a0c */
/* 0x000fda0003f26070 */
/*01f0*/ @P1 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105051810 */
/* 0x000fe40007ffe0ff */
/*0200*/ @!P2 LOP3.LUT R5, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff05aa12 */
/* 0x000fc800078e33ff */
/*0210*/ IADD3 R4, R5.reuse, 0x1, RZ ; /* 0x0000000105047810 */
/* 0x040fe40007ffe0ff */
/*0220*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe20003f06070 */
/*0230*/ IMAD R5, R2, 0x3, RZ ; /* 0x0000000302057824 */
/* 0x000fe200078e02ff */
/*0240*/ LOP3.LUT P1, R6, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304067812 */
/* 0x000fc8000782c0ff */
/*0250*/ SHF.R.S32.HI R4, RZ, 0x1f, R5 ; /* 0x0000001fff047819 */
/* 0x000fd20000011405 */
/*0260*/ @!P1 BRA 0x3e0 ; /* 0x0000017000009947 */
/* 0x000fea0003800000 */
/*0270*/ IADD3 R13, P1, R8.reuse, R5, RZ ; /* 0x00000005080d7210 */
/* 0x040fe40007f3e0ff */
/*0280*/ MOV R9, R6 ; /* 0x0000000600097202 */
/* 0x000fe40000000f00 */
/*0290*/ LEA R12, P2, R13, c[0x0][0x178], 0x3 ; /* 0x00005e000d0c7a11 */
/* 0x000fe400078418ff */
/*02a0*/ LEA.HI.X.SX32 R10, R8, R4, 0x1, P1 ; /* 0x00000004080a7211 */
/* 0x000fc800008f0eff */
/*02b0*/ LEA.HI.X R13, R13, c[0x0][0x17c], R10, 0x3, P2 ; /* 0x00005f000d0d7a11 */
/* 0x000fe400010f1c0a */
/*02c0*/ IMAD.HI R6, R8, 0x55555556, RZ ; /* 0x5555555608067827 */
/* 0x001fca00078e02ff */
/*02d0*/ LEA.HI R11, R6, R6, RZ, 0x1 ; /* 0x00000006060b7211 */
/* 0x000fca00078f08ff */
/*02e0*/ IMAD.IADD R7, R2, 0x1, R11 ; /* 0x0000000102077824 */
/* 0x000fc800078e020b */
/*02f0*/ IMAD.WIDE R6, R7, R0, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fcc00078e0200 */
/*0300*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*0310*/ HFMA2.MMA R14, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0e7435 */
/* 0x000fe200000001ff */
/*0320*/ IMAD R11, R11, -0x3, R8 ; /* 0xfffffffd0b0b7824 */
/* 0x000fc800078e0208 */
/*0330*/ IMAD R11, R6, 0x3, R11 ; /* 0x00000003060b7824 */
/* 0x004fca00078e020b */
/*0340*/ IMAD.WIDE R10, R11, R14, c[0x0][0x160] ; /* 0x000058000b0a7625 */
/* 0x000fcc00078e020e */
/*0350*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea2000c1e1b00 */
/*0360*/ IMAD.MOV.U32 R6, RZ, RZ, R12 ; /* 0x000000ffff067224 */
/* 0x000fe200078e000c */
/*0370*/ MOV R7, R13 ; /* 0x0000000d00077202 */
/* 0x000fe40000000f00 */
/*0380*/ IADD3 R9, R9, -0x1, RZ ; /* 0xffffffff09097810 */
/* 0x000fe40007ffe0ff */
/*0390*/ IADD3 R8, R8, c[0x0][0x0], RZ ; /* 0x0000000008087a10 */
/* 0x000fe20007ffe0ff */
/*03a0*/ IMAD.WIDE R12, R14, c[0x0][0x0], R6 ; /* 0x000000000e0c7a25 */
/* 0x000fe200078e0206 */
/*03b0*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f25270 */
/*03c0*/ STG.E.64 [R6.64], R10 ; /* 0x0000000a06007986 */
/* 0x0041d8000c101b04 */
/*03d0*/ @P1 BRA 0x2c0 ; /* 0xfffffee000001947 */
/* 0x000fea000383ffff */
/*03e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0400*/ IMAD.HI R6, R8, 0x55555556, RZ ; /* 0x5555555608067827 */
/* 0x001fca00078e02ff */
/*0410*/ LEA.HI R7, R6, R6, RZ, 0x1 ; /* 0x0000000606077211 */
/* 0x000fca00078f08ff */
/*0420*/ IMAD.IADD R11, R2, 0x1, R7 ; /* 0x00000001020b7824 */
/* 0x000fc800078e0207 */
/*0430*/ IMAD.WIDE R10, R11, R0, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x000fcc00078e0200 */
/*0440*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea2000c1e1900 */
/*0450*/ HFMA2.MMA R6, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff067435 */
/* 0x000fe200000001ff */
/*0460*/ IMAD R13, R7, -0x3, R8 ; /* 0xfffffffd070d7824 */
/* 0x000fe200078e0208 */
/*0470*/ IADD3 R18, R8, c[0x0][0x0], RZ ; /* 0x0000000008127a10 */
/* 0x000fca0007ffe0ff */
/*0480*/ IMAD.HI R7, R18, 0x55555556, RZ ; /* 0x5555555612077827 */
/* 0x000fc800078e02ff */
/*0490*/ IMAD R13, R10, 0x3, R13 ; /* 0x000000030a0d7824 */
/* 0x004fc800078e020d */
/*04a0*/ IMAD.WIDE R12, R13, R6, c[0x0][0x160] ; /* 0x000058000d0c7625 */
/* 0x000fcc00078e0206 */
/*04b0*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e1b00 */
/*04c0*/ IADD3 R9, P0, R8.reuse, R5, RZ ; /* 0x0000000508097210 */
/* 0x040fe40007f1e0ff */
/*04d0*/ LEA.HI R7, R7, R7, RZ, 0x1 ; /* 0x0000000707077211 */
/* 0x000fe400078f08ff */
/*04e0*/ LEA.HI.X.SX32 R14, R8, R4, 0x1, P0 ; /* 0x00000004080e7211 */
/* 0x000fe400000f0eff */
/*04f0*/ LEA R8, P0, R9, c[0x0][0x178], 0x3 ; /* 0x00005e0009087a11 */
/* 0x000fe200078018ff */
/*0500*/ IMAD.IADD R15, R2, 0x1, R7 ; /* 0x00000001020f7824 */
/* 0x000fc600078e0207 */
/*0510*/ LEA.HI.X R9, R9, c[0x0][0x17c], R14, 0x3, P0 ; /* 0x00005f0009097a11 */
/* 0x000fe200000f1c0e */
/*0520*/ IMAD.WIDE R14, R15, R0, c[0x0][0x168] ; /* 0x00005a000f0e7625 */
/* 0x000fc800078e0200 */
/*0530*/ STG.E.64 [R8.64], R12 ; /* 0x0000000c08007986 */
/* 0x0041e8000c101b04 */
/*0540*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea2000c1e1900 */
/*0550*/ IMAD R7, R7, -0x3, R18 ; /* 0xfffffffd07077824 */
/* 0x000fc800078e0212 */
/*0560*/ IMAD R7, R14, 0x3, R7 ; /* 0x000000030e077824 */
/* 0x004fc800078e0207 */
/*0570*/ IMAD.WIDE R16, R7, R6, c[0x0][0x160] ; /* 0x0000580007107625 */
/* 0x000fcc00078e0206 */
/*0580*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea2000c1e1b00 */
/*0590*/ IADD3 R7, R18, c[0x0][0x0], RZ ; /* 0x0000000012077a10 */
/* 0x000fca0007ffe0ff */
/*05a0*/ IMAD.HI R10, R7, 0x55555556, RZ ; /* 0x55555556070a7827 */
/* 0x000fca00078e02ff */
/*05b0*/ LEA.HI R18, R10, R10, RZ, 0x1 ; /* 0x0000000a0a127211 */
/* 0x000fe200078f08ff */
/*05c0*/ IMAD.WIDE R10, R6, c[0x0][0x0], R8 ; /* 0x00000000060a7a25 */
/* 0x000fc600078e0208 */
/*05d0*/ IADD3 R19, R2, R18, RZ ; /* 0x0000001202137210 */
/* 0x000fca0007ffe0ff */
/*05e0*/ IMAD.WIDE R8, R19, R0, c[0x0][0x168] ; /* 0x00005a0013087625 */
/* 0x001fe200078e0200 */
/*05f0*/ STG.E.64 [R10.64], R16 ; /* 0x000000100a007986 */
/* 0x0041ea000c101b04 */
/*0600*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0610*/ IMAD R18, R18, -0x3, R7 ; /* 0xfffffffd12127824 */
/* 0x000fc800078e0207 */
/*0620*/ IMAD R13, R9, 0x3, R18 ; /* 0x00000003090d7824 */
/* 0x004fc800078e0212 */
/*0630*/ IMAD.WIDE R12, R13, R6, c[0x0][0x160] ; /* 0x000058000d0c7625 */
/* 0x000fcc00078e0206 */
/*0640*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e1b00 */
/*0650*/ IADD3 R18, R7, c[0x0][0x0], RZ ; /* 0x0000000007127a10 */
/* 0x000fe20007ffe0ff */
/*0660*/ IMAD.WIDE R14, R6, c[0x0][0x0], R10 ; /* 0x00000000060e7a25 */
/* 0x000fc800078e020a */
/*0670*/ IMAD.HI R7, R18, 0x55555556, RZ ; /* 0x5555555612077827 */
/* 0x000fca00078e02ff */
/*0680*/ LEA.HI R7, R7, R7, RZ, 0x1 ; /* 0x0000000707077211 */
/* 0x000fca00078f08ff */
/*0690*/ IMAD.IADD R19, R2, 0x1, R7 ; /* 0x0000000102137824 */
/* 0x000fc800078e0207 */
/*06a0*/ IMAD.WIDE R10, R19, R0, c[0x0][0x168] ; /* 0x00005a00130a7625 */
/* 0x001fe200078e0200 */
/*06b0*/ STG.E.64 [R14.64], R12 ; /* 0x0000000c0e007986 */
/* 0x0041ea000c101b04 */
/*06c0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea2000c1e1900 */
/*06d0*/ IMAD R7, R7, -0x3, R18 ; /* 0xfffffffd07077824 */
/* 0x000fc800078e0212 */
/*06e0*/ IMAD R7, R10, 0x3, R7 ; /* 0x000000030a077824 */
/* 0x004fc800078e0207 */
/*06f0*/ IMAD.WIDE R16, R7, R6, c[0x0][0x160] ; /* 0x0000580007107625 */
/* 0x000fcc00078e0206 */
/*0700*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea2000c1e1b00 */
/*0710*/ IMAD.WIDE R6, R6, c[0x0][0x0], R14 ; /* 0x0000000006067a25 */
/* 0x000fe200078e020e */
/*0720*/ IADD3 R8, R18, c[0x0][0x0], RZ ; /* 0x0000000012087a10 */
/* 0x000fc80007ffe0ff */
/*0730*/ ISETP.GE.AND P0, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fe20003f06270 */
/*0740*/ STG.E.64 [R6.64], R16 ; /* 0x0000001006007986 */
/* 0x0041d8000c101b04 */
/*0750*/ @!P0 BRA 0x400 ; /* 0xfffffca000008947 */
/* 0x000fea000383ffff */
/*0760*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0770*/ BRA 0x770; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /******************************************************************
File : lcsBigBlockInitializationForPositions.cu
Author : Mingcheng Chen
Last Update : January 31st, 2013
*******************************************************************/
#include <stdio.h>
#define BLOCK_SIZE 512
__global__ void BigBlockInitializationForPositionsKernel(double *globalVertexPositions,
int *blockedGlobalPointIDs,
int *startOffsetInPoint,
double *vertexPositionsForBig
) {
// Get number of threads in a work group
int numOfThreads = blockDim.x;
// Get local thread ID
int localID = threadIdx.x;
// Get interesting block ID of the current big block
int interestingBlockID = blockIdx.x;
// Declare some work arrays
double *gVertexPositions;
int startPoint = startOffsetInPoint[interestingBlockID];
int numOfPoints = startOffsetInPoint[interestingBlockID + 1] - startPoint;
// Initialize vertexPositions
gVertexPositions = vertexPositionsForBig + startPoint * 3;
for (int i = localID; i < numOfPoints * 3; i += numOfThreads) {
int localPointID = i / 3;
int dimensionID = i % 3;
int globalPointID = blockedGlobalPointIDs[startPoint + localPointID];
gVertexPositions[i] = globalVertexPositions[globalPointID * 3 + dimensionID];
}
}
extern "C"
void BigBlockInitializationForPositions(double *globalVertexPositions,
int *blockedGlobalPointIDs,
int *startOffsetInPoint,
double *vertexPositionsForBig,
int numOfInterestingBlocks
) {
dim3 dimBlock(BLOCK_SIZE, 1, 1);
dim3 dimGrid(numOfInterestingBlocks, 1, 1);
BigBlockInitializationForPositionsKernel<<<dimGrid, dimBlock>>>(globalVertexPositions, blockedGlobalPointIDs,
startOffsetInPoint, vertexPositionsForBig);
cudaError_t err = cudaDeviceSynchronize();
if (err) {
cudaGetErrorString(err);
exit(0);
}
} | .file "tmpxft_0006fc61_00000000-6_lcsBigBlockInitializationForPositions.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z67__device_stub__Z40BigBlockInitializationForPositionsKernelPdPiS0_S_PdPiS0_S_
.type _Z67__device_stub__Z40BigBlockInitializationForPositionsKernelPdPiS0_S_PdPiS0_S_, @function
_Z67__device_stub__Z40BigBlockInitializationForPositionsKernelPdPiS0_S_PdPiS0_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z40BigBlockInitializationForPositionsKernelPdPiS0_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z67__device_stub__Z40BigBlockInitializationForPositionsKernelPdPiS0_S_PdPiS0_S_, .-_Z67__device_stub__Z40BigBlockInitializationForPositionsKernelPdPiS0_S_PdPiS0_S_
.globl _Z40BigBlockInitializationForPositionsKernelPdPiS0_S_
.type _Z40BigBlockInitializationForPositionsKernelPdPiS0_S_, @function
_Z40BigBlockInitializationForPositionsKernelPdPiS0_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z67__device_stub__Z40BigBlockInitializationForPositionsKernelPdPiS0_S_PdPiS0_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z40BigBlockInitializationForPositionsKernelPdPiS0_S_, .-_Z40BigBlockInitializationForPositionsKernelPdPiS0_S_
.globl BigBlockInitializationForPositions
.type BigBlockInitializationForPositions, @function
BigBlockInitializationForPositions:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r12
movq %rcx, %r13
movl $512, 8(%rsp)
movl $1, 12(%rsp)
movl %r8d, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L16
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z67__device_stub__Z40BigBlockInitializationForPositionsKernelPdPiS0_S_PdPiS0_S_
jmp .L12
.L16:
movl %eax, %edi
call cudaGetErrorString@PLT
movl $0, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size BigBlockInitializationForPositions, .-BigBlockInitializationForPositions
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z40BigBlockInitializationForPositionsKernelPdPiS0_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z40BigBlockInitializationForPositionsKernelPdPiS0_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /******************************************************************
File : lcsBigBlockInitializationForPositions.cu
Author : Mingcheng Chen
Last Update : January 31st, 2013
*******************************************************************/
#include <stdio.h>
#define BLOCK_SIZE 512
__global__ void BigBlockInitializationForPositionsKernel(double *globalVertexPositions,
int *blockedGlobalPointIDs,
int *startOffsetInPoint,
double *vertexPositionsForBig
) {
// Get number of threads in a work group
int numOfThreads = blockDim.x;
// Get local thread ID
int localID = threadIdx.x;
// Get interesting block ID of the current big block
int interestingBlockID = blockIdx.x;
// Declare some work arrays
double *gVertexPositions;
int startPoint = startOffsetInPoint[interestingBlockID];
int numOfPoints = startOffsetInPoint[interestingBlockID + 1] - startPoint;
// Initialize vertexPositions
gVertexPositions = vertexPositionsForBig + startPoint * 3;
for (int i = localID; i < numOfPoints * 3; i += numOfThreads) {
int localPointID = i / 3;
int dimensionID = i % 3;
int globalPointID = blockedGlobalPointIDs[startPoint + localPointID];
gVertexPositions[i] = globalVertexPositions[globalPointID * 3 + dimensionID];
}
}
extern "C"
void BigBlockInitializationForPositions(double *globalVertexPositions,
int *blockedGlobalPointIDs,
int *startOffsetInPoint,
double *vertexPositionsForBig,
int numOfInterestingBlocks
) {
dim3 dimBlock(BLOCK_SIZE, 1, 1);
dim3 dimGrid(numOfInterestingBlocks, 1, 1);
BigBlockInitializationForPositionsKernel<<<dimGrid, dimBlock>>>(globalVertexPositions, blockedGlobalPointIDs,
startOffsetInPoint, vertexPositionsForBig);
cudaError_t err = cudaDeviceSynchronize();
if (err) {
cudaGetErrorString(err);
exit(0);
}
} | /******************************************************************
File : lcsBigBlockInitializationForPositions.cu
Author : Mingcheng Chen
Last Update : January 31st, 2013
*******************************************************************/
#include <hip/hip_runtime.h>
#include <stdio.h>
#define BLOCK_SIZE 512
__global__ void BigBlockInitializationForPositionsKernel(double *globalVertexPositions,
int *blockedGlobalPointIDs,
int *startOffsetInPoint,
double *vertexPositionsForBig
) {
// Get number of threads in a work group
int numOfThreads = blockDim.x;
// Get local thread ID
int localID = threadIdx.x;
// Get interesting block ID of the current big block
int interestingBlockID = blockIdx.x;
// Declare some work arrays
double *gVertexPositions;
int startPoint = startOffsetInPoint[interestingBlockID];
int numOfPoints = startOffsetInPoint[interestingBlockID + 1] - startPoint;
// Initialize vertexPositions
gVertexPositions = vertexPositionsForBig + startPoint * 3;
for (int i = localID; i < numOfPoints * 3; i += numOfThreads) {
int localPointID = i / 3;
int dimensionID = i % 3;
int globalPointID = blockedGlobalPointIDs[startPoint + localPointID];
gVertexPositions[i] = globalVertexPositions[globalPointID * 3 + dimensionID];
}
}
extern "C"
void BigBlockInitializationForPositions(double *globalVertexPositions,
int *blockedGlobalPointIDs,
int *startOffsetInPoint,
double *vertexPositionsForBig,
int numOfInterestingBlocks
) {
dim3 dimBlock(BLOCK_SIZE, 1, 1);
dim3 dimGrid(numOfInterestingBlocks, 1, 1);
BigBlockInitializationForPositionsKernel<<<dimGrid, dimBlock>>>(globalVertexPositions, blockedGlobalPointIDs,
startOffsetInPoint, vertexPositionsForBig);
hipError_t err = hipDeviceSynchronize();
if (err) {
hipGetErrorString(err);
exit(0);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /******************************************************************
File : lcsBigBlockInitializationForPositions.cu
Author : Mingcheng Chen
Last Update : January 31st, 2013
*******************************************************************/
#include <hip/hip_runtime.h>
#include <stdio.h>
#define BLOCK_SIZE 512
__global__ void BigBlockInitializationForPositionsKernel(double *globalVertexPositions,
int *blockedGlobalPointIDs,
int *startOffsetInPoint,
double *vertexPositionsForBig
) {
// Get number of threads in a work group
int numOfThreads = blockDim.x;
// Get local thread ID
int localID = threadIdx.x;
// Get interesting block ID of the current big block
int interestingBlockID = blockIdx.x;
// Declare some work arrays
double *gVertexPositions;
int startPoint = startOffsetInPoint[interestingBlockID];
int numOfPoints = startOffsetInPoint[interestingBlockID + 1] - startPoint;
// Initialize vertexPositions
gVertexPositions = vertexPositionsForBig + startPoint * 3;
for (int i = localID; i < numOfPoints * 3; i += numOfThreads) {
int localPointID = i / 3;
int dimensionID = i % 3;
int globalPointID = blockedGlobalPointIDs[startPoint + localPointID];
gVertexPositions[i] = globalVertexPositions[globalPointID * 3 + dimensionID];
}
}
extern "C"
void BigBlockInitializationForPositions(double *globalVertexPositions,
int *blockedGlobalPointIDs,
int *startOffsetInPoint,
double *vertexPositionsForBig,
int numOfInterestingBlocks
) {
dim3 dimBlock(BLOCK_SIZE, 1, 1);
dim3 dimGrid(numOfInterestingBlocks, 1, 1);
BigBlockInitializationForPositionsKernel<<<dimGrid, dimBlock>>>(globalVertexPositions, blockedGlobalPointIDs,
startOffsetInPoint, vertexPositionsForBig);
hipError_t err = hipDeviceSynchronize();
if (err) {
hipGetErrorString(err);
exit(0);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z40BigBlockInitializationForPositionsKernelPdPiS0_S_
.globl _Z40BigBlockInitializationForPositionsKernelPdPiS0_S_
.p2align 8
.type _Z40BigBlockInitializationForPositionsKernelPdPiS0_S_,@function
_Z40BigBlockInitializationForPositionsKernelPdPiS0_S_:
s_load_b64 s[4:5], s[0:1], 0x10
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s4, s2
s_addc_u32 s3, s5, s3
s_mov_b32 s4, exec_lo
s_load_b64 s[2:3], s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_sub_i32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s3, s3, 3
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_3
s_clause 0x2
s_load_b32 s12, s[0:1], 0x2c
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_mul_i32 s0, s2, 3
v_mov_b32_e32 v1, 0
s_ashr_i32 s1, s0, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[0:1], 3
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s12, 0xffff
s_add_u32 s8, s8, s10
s_addc_u32 s9, s9, s11
s_mov_b32 s10, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_mul_hi_u32 v2, v0, 0xaaaaaaab
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v4, 1, v2
v_add_nc_u32_e32 v2, s2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v2, v[2:3], off
v_mul_lo_u32 v3, v4, -3
v_lshlrev_b64 v[4:5], 3, v[0:1]
s_waitcnt vmcnt(0)
v_lshl_add_u32 v2, v2, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add3_u32 v2, v0, v2, v3
v_add_nc_u32_e32 v0, s1, v0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_i32_e64 s0, s3, v0
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
s_or_b32 s10, s0, s10
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
global_store_b64 v[4:5], v[2:3], off
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z40BigBlockInitializationForPositionsKernelPdPiS0_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z40BigBlockInitializationForPositionsKernelPdPiS0_S_, .Lfunc_end0-_Z40BigBlockInitializationForPositionsKernelPdPiS0_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z40BigBlockInitializationForPositionsKernelPdPiS0_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z40BigBlockInitializationForPositionsKernelPdPiS0_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /******************************************************************
File : lcsBigBlockInitializationForPositions.cu
Author : Mingcheng Chen
Last Update : January 31st, 2013
*******************************************************************/
#include <hip/hip_runtime.h>
#include <stdio.h>
#define BLOCK_SIZE 512
__global__ void BigBlockInitializationForPositionsKernel(double *globalVertexPositions,
int *blockedGlobalPointIDs,
int *startOffsetInPoint,
double *vertexPositionsForBig
) {
// Get number of threads in a work group
int numOfThreads = blockDim.x;
// Get local thread ID
int localID = threadIdx.x;
// Get interesting block ID of the current big block
int interestingBlockID = blockIdx.x;
// Declare some work arrays
double *gVertexPositions;
int startPoint = startOffsetInPoint[interestingBlockID];
int numOfPoints = startOffsetInPoint[interestingBlockID + 1] - startPoint;
// Initialize vertexPositions
gVertexPositions = vertexPositionsForBig + startPoint * 3;
for (int i = localID; i < numOfPoints * 3; i += numOfThreads) {
int localPointID = i / 3;
int dimensionID = i % 3;
int globalPointID = blockedGlobalPointIDs[startPoint + localPointID];
gVertexPositions[i] = globalVertexPositions[globalPointID * 3 + dimensionID];
}
}
extern "C"
void BigBlockInitializationForPositions(double *globalVertexPositions,
int *blockedGlobalPointIDs,
int *startOffsetInPoint,
double *vertexPositionsForBig,
int numOfInterestingBlocks
) {
dim3 dimBlock(BLOCK_SIZE, 1, 1);
dim3 dimGrid(numOfInterestingBlocks, 1, 1);
BigBlockInitializationForPositionsKernel<<<dimGrid, dimBlock>>>(globalVertexPositions, blockedGlobalPointIDs,
startOffsetInPoint, vertexPositionsForBig);
hipError_t err = hipDeviceSynchronize();
if (err) {
hipGetErrorString(err);
exit(0);
}
} | .text
.file "lcsBigBlockInitializationForPositions.hip"
.globl _Z55__device_stub__BigBlockInitializationForPositionsKernelPdPiS0_S_ # -- Begin function _Z55__device_stub__BigBlockInitializationForPositionsKernelPdPiS0_S_
.p2align 4, 0x90
.type _Z55__device_stub__BigBlockInitializationForPositionsKernelPdPiS0_S_,@function
_Z55__device_stub__BigBlockInitializationForPositionsKernelPdPiS0_S_: # @_Z55__device_stub__BigBlockInitializationForPositionsKernelPdPiS0_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z40BigBlockInitializationForPositionsKernelPdPiS0_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z55__device_stub__BigBlockInitializationForPositionsKernelPdPiS0_S_, .Lfunc_end0-_Z55__device_stub__BigBlockInitializationForPositionsKernelPdPiS0_S_
.cfi_endproc
# -- End function
.globl BigBlockInitializationForPositions # -- Begin function BigBlockInitializationForPositions
.p2align 4, 0x90
.type BigBlockInitializationForPositions,@function
BigBlockInitializationForPositions: # @BigBlockInitializationForPositions
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
movl %r8d, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r12, 72(%rsp)
movq %r15, 64(%rsp)
movq %r14, 56(%rsp)
movq %rbx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z40BigBlockInitializationForPositionsKernelPdPiS0_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_4
# %bb.3:
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_4:
.cfi_def_cfa_offset 160
movl %eax, %edi
callq hipGetErrorString
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size BigBlockInitializationForPositions, .Lfunc_end1-BigBlockInitializationForPositions
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z40BigBlockInitializationForPositionsKernelPdPiS0_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z40BigBlockInitializationForPositionsKernelPdPiS0_S_,@object # @_Z40BigBlockInitializationForPositionsKernelPdPiS0_S_
.section .rodata,"a",@progbits
.globl _Z40BigBlockInitializationForPositionsKernelPdPiS0_S_
.p2align 3, 0x0
_Z40BigBlockInitializationForPositionsKernelPdPiS0_S_:
.quad _Z55__device_stub__BigBlockInitializationForPositionsKernelPdPiS0_S_
.size _Z40BigBlockInitializationForPositionsKernelPdPiS0_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z40BigBlockInitializationForPositionsKernelPdPiS0_S_"
.size .L__unnamed_1, 54
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z55__device_stub__BigBlockInitializationForPositionsKernelPdPiS0_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z40BigBlockInitializationForPositionsKernelPdPiS0_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z40BigBlockInitializationForPositionsKernelPdPiS0_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R4, R5, R0, c[0x0][0x170] ; /* 0x00005c0005047625 */
/* 0x001fca00078e0200 */
/*0050*/ LDG.E R3, [R4.64+0x4] ; /* 0x0000040404037981 */
/* 0x000ea8000c1e1900 */
/*0060*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0080*/ IMAD.IADD R3, R3, 0x1, -R2 ; /* 0x0000000103037824 */
/* 0x004fc800078e0a02 */
/*0090*/ IMAD R3, R3, 0x3, RZ ; /* 0x0000000303037824 */
/* 0x000fca00078e02ff */
/*00a0*/ ISETP.GE.AND P0, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x001fda0003f06270 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ I2F.U32.RP R7, c[0x0][0x0] ; /* 0x0000000000077b06 */
/* 0x000e220000209000 */
/*00d0*/ LOP3.LUT R6, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff067212 */
/* 0x000fe200078e33ff */
/*00e0*/ BSSY B0, 0x3f0 ; /* 0x0000030000007945 */
/* 0x000fe20003800000 */
/*00f0*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fe40003f45070 */
/*0100*/ IADD3 R6, R3, R6, RZ ; /* 0x0000000603067210 */
/* 0x000fc60007ffe0ff */
/*0110*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e240000001000 */
/*0120*/ IADD3 R4, R7, 0xffffffe, RZ ; /* 0x0ffffffe07047810 */
/* 0x001fcc0007ffe0ff */
/*0130*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0140*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe200078e00ff */
/*0150*/ IADD3 R9, RZ, -R5, RZ ; /* 0x80000005ff097210 */
/* 0x002fca0007ffe0ff */
/*0160*/ IMAD R9, R9, c[0x0][0x0], RZ ; /* 0x0000000009097a24 */
/* 0x000fc800078e02ff */
/*0170*/ IMAD.HI.U32 R5, R5, R9, R4 ; /* 0x0000000905057227 */
/* 0x000fcc00078e0004 */
/*0180*/ IMAD.HI.U32 R5, R5, R6, RZ ; /* 0x0000000605057227 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD.MOV R7, RZ, RZ, -R5 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0a05 */
/*01a0*/ IMAD R6, R7, c[0x0][0x0], R6 ; /* 0x0000000007067a24 */
/* 0x000fca00078e0206 */
/*01b0*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x0], PT ; /* 0x0000000006007a0c */
/* 0x000fda0003f06070 */
/*01c0*/ @P0 IADD3 R6, R6, -c[0x0][0x0], RZ ; /* 0x8000000006060a10 */
/* 0x000fe40007ffe0ff */
/*01d0*/ @P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105050810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.GE.U32.AND P1, PT, R6, c[0x0][0x0], PT ; /* 0x0000000006007a0c */
/* 0x000fda0003f26070 */
/*01f0*/ @P1 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105051810 */
/* 0x000fe40007ffe0ff */
/*0200*/ @!P2 LOP3.LUT R5, RZ, c[0x0][0x0], RZ, 0x33, !PT ; /* 0x00000000ff05aa12 */
/* 0x000fc800078e33ff */
/*0210*/ IADD3 R4, R5.reuse, 0x1, RZ ; /* 0x0000000105047810 */
/* 0x040fe40007ffe0ff */
/*0220*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe20003f06070 */
/*0230*/ IMAD R5, R2, 0x3, RZ ; /* 0x0000000302057824 */
/* 0x000fe200078e02ff */
/*0240*/ LOP3.LUT P1, R6, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304067812 */
/* 0x000fc8000782c0ff */
/*0250*/ SHF.R.S32.HI R4, RZ, 0x1f, R5 ; /* 0x0000001fff047819 */
/* 0x000fd20000011405 */
/*0260*/ @!P1 BRA 0x3e0 ; /* 0x0000017000009947 */
/* 0x000fea0003800000 */
/*0270*/ IADD3 R13, P1, R8.reuse, R5, RZ ; /* 0x00000005080d7210 */
/* 0x040fe40007f3e0ff */
/*0280*/ MOV R9, R6 ; /* 0x0000000600097202 */
/* 0x000fe40000000f00 */
/*0290*/ LEA R12, P2, R13, c[0x0][0x178], 0x3 ; /* 0x00005e000d0c7a11 */
/* 0x000fe400078418ff */
/*02a0*/ LEA.HI.X.SX32 R10, R8, R4, 0x1, P1 ; /* 0x00000004080a7211 */
/* 0x000fc800008f0eff */
/*02b0*/ LEA.HI.X R13, R13, c[0x0][0x17c], R10, 0x3, P2 ; /* 0x00005f000d0d7a11 */
/* 0x000fe400010f1c0a */
/*02c0*/ IMAD.HI R6, R8, 0x55555556, RZ ; /* 0x5555555608067827 */
/* 0x001fca00078e02ff */
/*02d0*/ LEA.HI R11, R6, R6, RZ, 0x1 ; /* 0x00000006060b7211 */
/* 0x000fca00078f08ff */
/*02e0*/ IMAD.IADD R7, R2, 0x1, R11 ; /* 0x0000000102077824 */
/* 0x000fc800078e020b */
/*02f0*/ IMAD.WIDE R6, R7, R0, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fcc00078e0200 */
/*0300*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*0310*/ HFMA2.MMA R14, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0e7435 */
/* 0x000fe200000001ff */
/*0320*/ IMAD R11, R11, -0x3, R8 ; /* 0xfffffffd0b0b7824 */
/* 0x000fc800078e0208 */
/*0330*/ IMAD R11, R6, 0x3, R11 ; /* 0x00000003060b7824 */
/* 0x004fca00078e020b */
/*0340*/ IMAD.WIDE R10, R11, R14, c[0x0][0x160] ; /* 0x000058000b0a7625 */
/* 0x000fcc00078e020e */
/*0350*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea2000c1e1b00 */
/*0360*/ IMAD.MOV.U32 R6, RZ, RZ, R12 ; /* 0x000000ffff067224 */
/* 0x000fe200078e000c */
/*0370*/ MOV R7, R13 ; /* 0x0000000d00077202 */
/* 0x000fe40000000f00 */
/*0380*/ IADD3 R9, R9, -0x1, RZ ; /* 0xffffffff09097810 */
/* 0x000fe40007ffe0ff */
/*0390*/ IADD3 R8, R8, c[0x0][0x0], RZ ; /* 0x0000000008087a10 */
/* 0x000fe20007ffe0ff */
/*03a0*/ IMAD.WIDE R12, R14, c[0x0][0x0], R6 ; /* 0x000000000e0c7a25 */
/* 0x000fe200078e0206 */
/*03b0*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f25270 */
/*03c0*/ STG.E.64 [R6.64], R10 ; /* 0x0000000a06007986 */
/* 0x0041d8000c101b04 */
/*03d0*/ @P1 BRA 0x2c0 ; /* 0xfffffee000001947 */
/* 0x000fea000383ffff */
/*03e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0400*/ IMAD.HI R6, R8, 0x55555556, RZ ; /* 0x5555555608067827 */
/* 0x001fca00078e02ff */
/*0410*/ LEA.HI R7, R6, R6, RZ, 0x1 ; /* 0x0000000606077211 */
/* 0x000fca00078f08ff */
/*0420*/ IMAD.IADD R11, R2, 0x1, R7 ; /* 0x00000001020b7824 */
/* 0x000fc800078e0207 */
/*0430*/ IMAD.WIDE R10, R11, R0, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x000fcc00078e0200 */
/*0440*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea2000c1e1900 */
/*0450*/ HFMA2.MMA R6, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff067435 */
/* 0x000fe200000001ff */
/*0460*/ IMAD R13, R7, -0x3, R8 ; /* 0xfffffffd070d7824 */
/* 0x000fe200078e0208 */
/*0470*/ IADD3 R18, R8, c[0x0][0x0], RZ ; /* 0x0000000008127a10 */
/* 0x000fca0007ffe0ff */
/*0480*/ IMAD.HI R7, R18, 0x55555556, RZ ; /* 0x5555555612077827 */
/* 0x000fc800078e02ff */
/*0490*/ IMAD R13, R10, 0x3, R13 ; /* 0x000000030a0d7824 */
/* 0x004fc800078e020d */
/*04a0*/ IMAD.WIDE R12, R13, R6, c[0x0][0x160] ; /* 0x000058000d0c7625 */
/* 0x000fcc00078e0206 */
/*04b0*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e1b00 */
/*04c0*/ IADD3 R9, P0, R8.reuse, R5, RZ ; /* 0x0000000508097210 */
/* 0x040fe40007f1e0ff */
/*04d0*/ LEA.HI R7, R7, R7, RZ, 0x1 ; /* 0x0000000707077211 */
/* 0x000fe400078f08ff */
/*04e0*/ LEA.HI.X.SX32 R14, R8, R4, 0x1, P0 ; /* 0x00000004080e7211 */
/* 0x000fe400000f0eff */
/*04f0*/ LEA R8, P0, R9, c[0x0][0x178], 0x3 ; /* 0x00005e0009087a11 */
/* 0x000fe200078018ff */
/*0500*/ IMAD.IADD R15, R2, 0x1, R7 ; /* 0x00000001020f7824 */
/* 0x000fc600078e0207 */
/*0510*/ LEA.HI.X R9, R9, c[0x0][0x17c], R14, 0x3, P0 ; /* 0x00005f0009097a11 */
/* 0x000fe200000f1c0e */
/*0520*/ IMAD.WIDE R14, R15, R0, c[0x0][0x168] ; /* 0x00005a000f0e7625 */
/* 0x000fc800078e0200 */
/*0530*/ STG.E.64 [R8.64], R12 ; /* 0x0000000c08007986 */
/* 0x0041e8000c101b04 */
/*0540*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea2000c1e1900 */
/*0550*/ IMAD R7, R7, -0x3, R18 ; /* 0xfffffffd07077824 */
/* 0x000fc800078e0212 */
/*0560*/ IMAD R7, R14, 0x3, R7 ; /* 0x000000030e077824 */
/* 0x004fc800078e0207 */
/*0570*/ IMAD.WIDE R16, R7, R6, c[0x0][0x160] ; /* 0x0000580007107625 */
/* 0x000fcc00078e0206 */
/*0580*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea2000c1e1b00 */
/*0590*/ IADD3 R7, R18, c[0x0][0x0], RZ ; /* 0x0000000012077a10 */
/* 0x000fca0007ffe0ff */
/*05a0*/ IMAD.HI R10, R7, 0x55555556, RZ ; /* 0x55555556070a7827 */
/* 0x000fca00078e02ff */
/*05b0*/ LEA.HI R18, R10, R10, RZ, 0x1 ; /* 0x0000000a0a127211 */
/* 0x000fe200078f08ff */
/*05c0*/ IMAD.WIDE R10, R6, c[0x0][0x0], R8 ; /* 0x00000000060a7a25 */
/* 0x000fc600078e0208 */
/*05d0*/ IADD3 R19, R2, R18, RZ ; /* 0x0000001202137210 */
/* 0x000fca0007ffe0ff */
/*05e0*/ IMAD.WIDE R8, R19, R0, c[0x0][0x168] ; /* 0x00005a0013087625 */
/* 0x001fe200078e0200 */
/*05f0*/ STG.E.64 [R10.64], R16 ; /* 0x000000100a007986 */
/* 0x0041ea000c101b04 */
/*0600*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0610*/ IMAD R18, R18, -0x3, R7 ; /* 0xfffffffd12127824 */
/* 0x000fc800078e0207 */
/*0620*/ IMAD R13, R9, 0x3, R18 ; /* 0x00000003090d7824 */
/* 0x004fc800078e0212 */
/*0630*/ IMAD.WIDE R12, R13, R6, c[0x0][0x160] ; /* 0x000058000d0c7625 */
/* 0x000fcc00078e0206 */
/*0640*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e1b00 */
/*0650*/ IADD3 R18, R7, c[0x0][0x0], RZ ; /* 0x0000000007127a10 */
/* 0x000fe20007ffe0ff */
/*0660*/ IMAD.WIDE R14, R6, c[0x0][0x0], R10 ; /* 0x00000000060e7a25 */
/* 0x000fc800078e020a */
/*0670*/ IMAD.HI R7, R18, 0x55555556, RZ ; /* 0x5555555612077827 */
/* 0x000fca00078e02ff */
/*0680*/ LEA.HI R7, R7, R7, RZ, 0x1 ; /* 0x0000000707077211 */
/* 0x000fca00078f08ff */
/*0690*/ IMAD.IADD R19, R2, 0x1, R7 ; /* 0x0000000102137824 */
/* 0x000fc800078e0207 */
/*06a0*/ IMAD.WIDE R10, R19, R0, c[0x0][0x168] ; /* 0x00005a00130a7625 */
/* 0x001fe200078e0200 */
/*06b0*/ STG.E.64 [R14.64], R12 ; /* 0x0000000c0e007986 */
/* 0x0041ea000c101b04 */
/*06c0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea2000c1e1900 */
/*06d0*/ IMAD R7, R7, -0x3, R18 ; /* 0xfffffffd07077824 */
/* 0x000fc800078e0212 */
/*06e0*/ IMAD R7, R10, 0x3, R7 ; /* 0x000000030a077824 */
/* 0x004fc800078e0207 */
/*06f0*/ IMAD.WIDE R16, R7, R6, c[0x0][0x160] ; /* 0x0000580007107625 */
/* 0x000fcc00078e0206 */
/*0700*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea2000c1e1b00 */
/*0710*/ IMAD.WIDE R6, R6, c[0x0][0x0], R14 ; /* 0x0000000006067a25 */
/* 0x000fe200078e020e */
/*0720*/ IADD3 R8, R18, c[0x0][0x0], RZ ; /* 0x0000000012087a10 */
/* 0x000fc80007ffe0ff */
/*0730*/ ISETP.GE.AND P0, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fe20003f06270 */
/*0740*/ STG.E.64 [R6.64], R16 ; /* 0x0000001006007986 */
/* 0x0041d8000c101b04 */
/*0750*/ @!P0 BRA 0x400 ; /* 0xfffffca000008947 */
/* 0x000fea000383ffff */
/*0760*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0770*/ BRA 0x770; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z40BigBlockInitializationForPositionsKernelPdPiS0_S_
.globl _Z40BigBlockInitializationForPositionsKernelPdPiS0_S_
.p2align 8
.type _Z40BigBlockInitializationForPositionsKernelPdPiS0_S_,@function
_Z40BigBlockInitializationForPositionsKernelPdPiS0_S_:
s_load_b64 s[4:5], s[0:1], 0x10
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s4, s2
s_addc_u32 s3, s5, s3
s_mov_b32 s4, exec_lo
s_load_b64 s[2:3], s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_sub_i32 s3, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s3, s3, 3
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_3
s_clause 0x2
s_load_b32 s12, s[0:1], 0x2c
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
s_mul_i32 s0, s2, 3
v_mov_b32_e32 v1, 0
s_ashr_i32 s1, s0, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[0:1], 3
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s12, 0xffff
s_add_u32 s8, s8, s10
s_addc_u32 s9, s9, s11
s_mov_b32 s10, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_mul_hi_u32 v2, v0, 0xaaaaaaab
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v4, 1, v2
v_add_nc_u32_e32 v2, s2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v2, v[2:3], off
v_mul_lo_u32 v3, v4, -3
v_lshlrev_b64 v[4:5], 3, v[0:1]
s_waitcnt vmcnt(0)
v_lshl_add_u32 v2, v2, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add3_u32 v2, v0, v2, v3
v_add_nc_u32_e32 v0, s1, v0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_i32_e64 s0, s3, v0
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
s_or_b32 s10, s0, s10
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
global_store_b64 v[4:5], v[2:3], off
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z40BigBlockInitializationForPositionsKernelPdPiS0_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z40BigBlockInitializationForPositionsKernelPdPiS0_S_, .Lfunc_end0-_Z40BigBlockInitializationForPositionsKernelPdPiS0_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z40BigBlockInitializationForPositionsKernelPdPiS0_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z40BigBlockInitializationForPositionsKernelPdPiS0_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006fc61_00000000-6_lcsBigBlockInitializationForPositions.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z67__device_stub__Z40BigBlockInitializationForPositionsKernelPdPiS0_S_PdPiS0_S_
.type _Z67__device_stub__Z40BigBlockInitializationForPositionsKernelPdPiS0_S_PdPiS0_S_, @function
_Z67__device_stub__Z40BigBlockInitializationForPositionsKernelPdPiS0_S_PdPiS0_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z40BigBlockInitializationForPositionsKernelPdPiS0_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z67__device_stub__Z40BigBlockInitializationForPositionsKernelPdPiS0_S_PdPiS0_S_, .-_Z67__device_stub__Z40BigBlockInitializationForPositionsKernelPdPiS0_S_PdPiS0_S_
.globl _Z40BigBlockInitializationForPositionsKernelPdPiS0_S_
.type _Z40BigBlockInitializationForPositionsKernelPdPiS0_S_, @function
_Z40BigBlockInitializationForPositionsKernelPdPiS0_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z67__device_stub__Z40BigBlockInitializationForPositionsKernelPdPiS0_S_PdPiS0_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z40BigBlockInitializationForPositionsKernelPdPiS0_S_, .-_Z40BigBlockInitializationForPositionsKernelPdPiS0_S_
.globl BigBlockInitializationForPositions
.type BigBlockInitializationForPositions, @function
BigBlockInitializationForPositions:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r12
movq %rcx, %r13
movl $512, 8(%rsp)
movl $1, 12(%rsp)
movl %r8d, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L16
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z67__device_stub__Z40BigBlockInitializationForPositionsKernelPdPiS0_S_PdPiS0_S_
jmp .L12
.L16:
movl %eax, %edi
call cudaGetErrorString@PLT
movl $0, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size BigBlockInitializationForPositions, .-BigBlockInitializationForPositions
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z40BigBlockInitializationForPositionsKernelPdPiS0_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z40BigBlockInitializationForPositionsKernelPdPiS0_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "lcsBigBlockInitializationForPositions.hip"
.globl _Z55__device_stub__BigBlockInitializationForPositionsKernelPdPiS0_S_ # -- Begin function _Z55__device_stub__BigBlockInitializationForPositionsKernelPdPiS0_S_
.p2align 4, 0x90
.type _Z55__device_stub__BigBlockInitializationForPositionsKernelPdPiS0_S_,@function
_Z55__device_stub__BigBlockInitializationForPositionsKernelPdPiS0_S_: # @_Z55__device_stub__BigBlockInitializationForPositionsKernelPdPiS0_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z40BigBlockInitializationForPositionsKernelPdPiS0_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z55__device_stub__BigBlockInitializationForPositionsKernelPdPiS0_S_, .Lfunc_end0-_Z55__device_stub__BigBlockInitializationForPositionsKernelPdPiS0_S_
.cfi_endproc
# -- End function
.globl BigBlockInitializationForPositions # -- Begin function BigBlockInitializationForPositions
.p2align 4, 0x90
.type BigBlockInitializationForPositions,@function
BigBlockInitializationForPositions: # @BigBlockInitializationForPositions
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
movl %r8d, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r12, 72(%rsp)
movq %r15, 64(%rsp)
movq %r14, 56(%rsp)
movq %rbx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z40BigBlockInitializationForPositionsKernelPdPiS0_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_4
# %bb.3:
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_4:
.cfi_def_cfa_offset 160
movl %eax, %edi
callq hipGetErrorString
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size BigBlockInitializationForPositions, .Lfunc_end1-BigBlockInitializationForPositions
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z40BigBlockInitializationForPositionsKernelPdPiS0_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z40BigBlockInitializationForPositionsKernelPdPiS0_S_,@object # @_Z40BigBlockInitializationForPositionsKernelPdPiS0_S_
.section .rodata,"a",@progbits
.globl _Z40BigBlockInitializationForPositionsKernelPdPiS0_S_
.p2align 3, 0x0
_Z40BigBlockInitializationForPositionsKernelPdPiS0_S_:
.quad _Z55__device_stub__BigBlockInitializationForPositionsKernelPdPiS0_S_
.size _Z40BigBlockInitializationForPositionsKernelPdPiS0_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z40BigBlockInitializationForPositionsKernelPdPiS0_S_"
.size .L__unnamed_1, 54
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z55__device_stub__BigBlockInitializationForPositionsKernelPdPiS0_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z40BigBlockInitializationForPositionsKernelPdPiS0_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void arrayTest(int n, long *factor, long *arr, long *result, int *const_arr1, long *const_arr2)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i == 0) {
/*
printf("In ArrayTest n=%d factor=%p arr=%p result=%p \n",n,factor,arr,result);
printf("In const %d %d %d\n",const_arr1[0],const_arr1[1],const_arr1[2]);
printf("In const %ld %ld %ld\n",const_arr2[0],const_arr2[1],const_arr2[2]);
*/
}
if (i<n)
{
int idx = i * 3;
result[idx]=arr[idx] * factor[i];
result[idx + 1]=arr[idx + 1] * factor[i];
result[idx + 2]=arr[idx + 2] * factor[i];
/*
printf("ArrayTest [%ld] * [%ld %ld %ld] = [%ld %ld %ld] \n", factor[i],
arr[idx],arr[idx+1],arr[idx+2],
result[idx],result[idx+1],result[idx+2]);
*/
}
} | code for sm_80
Function : _Z9arrayTestiPlS_S_PiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R15, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0f7435 */
/* 0x000fe200000001ff */
/*0070*/ LEA R0, R4, R4, 0x1 ; /* 0x0000000404007211 */
/* 0x000fe200078e08ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R4, R4, R15, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e020f */
/*00a0*/ IMAD.WIDE R2, R0, R15, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fe200078e020f */
/*00b0*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1b00 */
/*00c0*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea4000c1e1b00 */
/*00d0*/ IMAD R7, R7, R8.reuse, RZ ; /* 0x0000000807077224 */
/* 0x084fe400078e02ff */
/*00e0*/ IMAD.WIDE.U32 R10, R6, R8, RZ ; /* 0x00000008060a7225 */
/* 0x000fc800078e00ff */
/*00f0*/ IMAD R7, R6, R9, R7 ; /* 0x0000000906077224 */
/* 0x000fe200078e0207 */
/*0100*/ MOV R12, R10 ; /* 0x0000000a000c7202 */
/* 0x000fc80000000f00 */
/*0110*/ IADD3 R13, R11, R7, RZ ; /* 0x000000070b0d7210 */
/* 0x000fe20007ffe0ff */
/*0120*/ IMAD.WIDE R6, R0, R15, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x000fca00078e020f */
/*0130*/ STG.E.64 [R6.64], R12 ; /* 0x0000000c06007986 */
/* 0x0001e8000c101b04 */
/*0140*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea8000c1e1b00 */
/*0150*/ LDG.E.64 R10, [R2.64+0x8] ; /* 0x00000804020a7981 */
/* 0x000ea4000c1e1b00 */
/*0160*/ IMAD R9, R9, R10, RZ ; /* 0x0000000a09097224 */
/* 0x004fc400078e02ff */
/*0170*/ IMAD.WIDE.U32 R14, R8, R10, RZ ; /* 0x0000000a080e7225 */
/* 0x000fc800078e00ff */
/*0180*/ IMAD R9, R8, R11, R9 ; /* 0x0000000b08097224 */
/* 0x000fca00078e0209 */
/*0190*/ IADD3 R15, R15, R9, RZ ; /* 0x000000090f0f7210 */
/* 0x000fca0007ffe0ff */
/*01a0*/ STG.E.64 [R6.64+0x8], R14 ; /* 0x0000080e06007986 */
/* 0x000fe8000c101b04 */
/*01b0*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea8000c1e1b00 */
/*01c0*/ LDG.E.64 R10, [R2.64+0x10] ; /* 0x00001004020a7981 */
/* 0x000ea4000c1e1b00 */
/*01d0*/ IMAD R9, R9, R10, RZ ; /* 0x0000000a09097224 */
/* 0x004fc400078e02ff */
/*01e0*/ IMAD.WIDE.U32 R12, R8, R10, RZ ; /* 0x0000000a080c7225 */
/* 0x001fc800078e00ff */
/*01f0*/ IMAD R9, R8, R11, R9 ; /* 0x0000000b08097224 */
/* 0x000fca00078e0209 */
/*0200*/ IADD3 R13, R13, R9, RZ ; /* 0x000000090d0d7210 */
/* 0x000fca0007ffe0ff */
/*0210*/ STG.E.64 [R6.64+0x10], R12 ; /* 0x0000100c06007986 */
/* 0x000fe2000c101b04 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void arrayTest(int n, long *factor, long *arr, long *result, int *const_arr1, long *const_arr2)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i == 0) {
/*
printf("In ArrayTest n=%d factor=%p arr=%p result=%p \n",n,factor,arr,result);
printf("In const %d %d %d\n",const_arr1[0],const_arr1[1],const_arr1[2]);
printf("In const %ld %ld %ld\n",const_arr2[0],const_arr2[1],const_arr2[2]);
*/
}
if (i<n)
{
int idx = i * 3;
result[idx]=arr[idx] * factor[i];
result[idx + 1]=arr[idx + 1] * factor[i];
result[idx + 2]=arr[idx + 2] * factor[i];
/*
printf("ArrayTest [%ld] * [%ld %ld %ld] = [%ld %ld %ld] \n", factor[i],
arr[idx],arr[idx+1],arr[idx+2],
result[idx],result[idx+1],result[idx+2]);
*/
}
} | .file "tmpxft_001228bd_00000000-6_arrayTest.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z9arrayTestiPlS_S_PiS_iPlS_S_PiS_
.type _Z37__device_stub__Z9arrayTestiPlS_S_PiS_iPlS_S_PiS_, @function
_Z37__device_stub__Z9arrayTestiPlS_S_PiS_iPlS_S_PiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9arrayTestiPlS_S_PiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z9arrayTestiPlS_S_PiS_iPlS_S_PiS_, .-_Z37__device_stub__Z9arrayTestiPlS_S_PiS_iPlS_S_PiS_
.globl _Z9arrayTestiPlS_S_PiS_
.type _Z9arrayTestiPlS_S_PiS_, @function
_Z9arrayTestiPlS_S_PiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z9arrayTestiPlS_S_PiS_iPlS_S_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9arrayTestiPlS_S_PiS_, .-_Z9arrayTestiPlS_S_PiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9arrayTestiPlS_S_PiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9arrayTestiPlS_S_PiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void arrayTest(int n, long *factor, long *arr, long *result, int *const_arr1, long *const_arr2)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i == 0) {
/*
printf("In ArrayTest n=%d factor=%p arr=%p result=%p \n",n,factor,arr,result);
printf("In const %d %d %d\n",const_arr1[0],const_arr1[1],const_arr1[2]);
printf("In const %ld %ld %ld\n",const_arr2[0],const_arr2[1],const_arr2[2]);
*/
}
if (i<n)
{
int idx = i * 3;
result[idx]=arr[idx] * factor[i];
result[idx + 1]=arr[idx + 1] * factor[i];
result[idx + 2]=arr[idx + 2] * factor[i];
/*
printf("ArrayTest [%ld] * [%ld %ld %ld] = [%ld %ld %ld] \n", factor[i],
arr[idx],arr[idx+1],arr[idx+2],
result[idx],result[idx+1],result[idx+2]);
*/
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void arrayTest(int n, long *factor, long *arr, long *result, int *const_arr1, long *const_arr2)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i == 0) {
/*
printf("In ArrayTest n=%d factor=%p arr=%p result=%p \n",n,factor,arr,result);
printf("In const %d %d %d\n",const_arr1[0],const_arr1[1],const_arr1[2]);
printf("In const %ld %ld %ld\n",const_arr2[0],const_arr2[1],const_arr2[2]);
*/
}
if (i<n)
{
int idx = i * 3;
result[idx]=arr[idx] * factor[i];
result[idx + 1]=arr[idx + 1] * factor[i];
result[idx + 2]=arr[idx + 2] * factor[i];
/*
printf("ArrayTest [%ld] * [%ld %ld %ld] = [%ld %ld %ld] \n", factor[i],
arr[idx],arr[idx+1],arr[idx+2],
result[idx],result[idx+1],result[idx+2]);
*/
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void arrayTest(int n, long *factor, long *arr, long *result, int *const_arr1, long *const_arr2)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i == 0) {
/*
printf("In ArrayTest n=%d factor=%p arr=%p result=%p \n",n,factor,arr,result);
printf("In const %d %d %d\n",const_arr1[0],const_arr1[1],const_arr1[2]);
printf("In const %ld %ld %ld\n",const_arr2[0],const_arr2[1],const_arr2[2]);
*/
}
if (i<n)
{
int idx = i * 3;
result[idx]=arr[idx] * factor[i];
result[idx + 1]=arr[idx + 1] * factor[i];
result[idx + 2]=arr[idx + 2] * factor[i];
/*
printf("ArrayTest [%ld] * [%ld %ld %ld] = [%ld %ld %ld] \n", factor[i],
arr[idx],arr[idx+1],arr[idx+2],
result[idx],result[idx+1],result[idx+2]);
*/
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9arrayTestiPlS_S_PiS_
.globl _Z9arrayTestiPlS_S_PiS_
.p2align 8
.type _Z9arrayTestiPlS_S_PiS_,@function
_Z9arrayTestiPlS_S_PiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_lshl_add_u32 v3, v1, 1, v1
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v12, vcc_lo, v3, 8
global_load_b64 v[5:6], v[5:6], off
global_load_b64 v[7:8], v[0:1], off
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v4, vcc_lo
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v8, v5
v_mul_lo_u32 v10, v7, v6
v_mad_u64_u32 v[8:9], null, v7, v5, 0
v_add_co_u32 v5, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_add3_u32 v9, v9, v10, v2
v_add_co_u32 v10, vcc_lo, s6, v12
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v13, vcc_lo
global_store_b64 v[5:6], v[8:9], off
global_load_b64 v[5:6], v[10:11], off
global_load_b64 v[7:8], v[0:1], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v10, v8, v5
v_mul_lo_u32 v6, v7, v6
v_mad_u64_u32 v[8:9], null, v7, v5, 0
v_add_co_u32 v7, vcc_lo, v3, 16
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v4, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v12
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s6, v7
v_add3_u32 v9, v9, v6, v10
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v11, vcc_lo
global_store_b64 v[2:3], v[8:9], off
global_load_b64 v[2:3], v[4:5], off
global_load_b64 v[0:1], v[0:1], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v1, v1, v2
v_mul_lo_u32 v5, v0, v3
v_mad_u64_u32 v[3:4], null, v0, v2, 0
v_add_co_u32 v0, vcc_lo, s0, v7
s_delay_alu instid0(VALU_DEP_2)
v_add3_u32 v4, v4, v5, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v11, vcc_lo
global_store_b64 v[0:1], v[3:4], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9arrayTestiPlS_S_PiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9arrayTestiPlS_S_PiS_, .Lfunc_end0-_Z9arrayTestiPlS_S_PiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9arrayTestiPlS_S_PiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9arrayTestiPlS_S_PiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void arrayTest(int n, long *factor, long *arr, long *result, int *const_arr1, long *const_arr2)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i == 0) {
/*
printf("In ArrayTest n=%d factor=%p arr=%p result=%p \n",n,factor,arr,result);
printf("In const %d %d %d\n",const_arr1[0],const_arr1[1],const_arr1[2]);
printf("In const %ld %ld %ld\n",const_arr2[0],const_arr2[1],const_arr2[2]);
*/
}
if (i<n)
{
int idx = i * 3;
result[idx]=arr[idx] * factor[i];
result[idx + 1]=arr[idx + 1] * factor[i];
result[idx + 2]=arr[idx + 2] * factor[i];
/*
printf("ArrayTest [%ld] * [%ld %ld %ld] = [%ld %ld %ld] \n", factor[i],
arr[idx],arr[idx+1],arr[idx+2],
result[idx],result[idx+1],result[idx+2]);
*/
}
} | .text
.file "arrayTest.hip"
.globl _Z24__device_stub__arrayTestiPlS_S_PiS_ # -- Begin function _Z24__device_stub__arrayTestiPlS_S_PiS_
.p2align 4, 0x90
.type _Z24__device_stub__arrayTestiPlS_S_PiS_,@function
_Z24__device_stub__arrayTestiPlS_S_PiS_: # @_Z24__device_stub__arrayTestiPlS_S_PiS_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 4(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9arrayTestiPlS_S_PiS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z24__device_stub__arrayTestiPlS_S_PiS_, .Lfunc_end0-_Z24__device_stub__arrayTestiPlS_S_PiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9arrayTestiPlS_S_PiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9arrayTestiPlS_S_PiS_,@object # @_Z9arrayTestiPlS_S_PiS_
.section .rodata,"a",@progbits
.globl _Z9arrayTestiPlS_S_PiS_
.p2align 3, 0x0
_Z9arrayTestiPlS_S_PiS_:
.quad _Z24__device_stub__arrayTestiPlS_S_PiS_
.size _Z9arrayTestiPlS_S_PiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9arrayTestiPlS_S_PiS_"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__arrayTestiPlS_S_PiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9arrayTestiPlS_S_PiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9arrayTestiPlS_S_PiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R15, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0f7435 */
/* 0x000fe200000001ff */
/*0070*/ LEA R0, R4, R4, 0x1 ; /* 0x0000000404007211 */
/* 0x000fe200078e08ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R4, R4, R15, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e020f */
/*00a0*/ IMAD.WIDE R2, R0, R15, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fe200078e020f */
/*00b0*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1b00 */
/*00c0*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea4000c1e1b00 */
/*00d0*/ IMAD R7, R7, R8.reuse, RZ ; /* 0x0000000807077224 */
/* 0x084fe400078e02ff */
/*00e0*/ IMAD.WIDE.U32 R10, R6, R8, RZ ; /* 0x00000008060a7225 */
/* 0x000fc800078e00ff */
/*00f0*/ IMAD R7, R6, R9, R7 ; /* 0x0000000906077224 */
/* 0x000fe200078e0207 */
/*0100*/ MOV R12, R10 ; /* 0x0000000a000c7202 */
/* 0x000fc80000000f00 */
/*0110*/ IADD3 R13, R11, R7, RZ ; /* 0x000000070b0d7210 */
/* 0x000fe20007ffe0ff */
/*0120*/ IMAD.WIDE R6, R0, R15, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x000fca00078e020f */
/*0130*/ STG.E.64 [R6.64], R12 ; /* 0x0000000c06007986 */
/* 0x0001e8000c101b04 */
/*0140*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea8000c1e1b00 */
/*0150*/ LDG.E.64 R10, [R2.64+0x8] ; /* 0x00000804020a7981 */
/* 0x000ea4000c1e1b00 */
/*0160*/ IMAD R9, R9, R10, RZ ; /* 0x0000000a09097224 */
/* 0x004fc400078e02ff */
/*0170*/ IMAD.WIDE.U32 R14, R8, R10, RZ ; /* 0x0000000a080e7225 */
/* 0x000fc800078e00ff */
/*0180*/ IMAD R9, R8, R11, R9 ; /* 0x0000000b08097224 */
/* 0x000fca00078e0209 */
/*0190*/ IADD3 R15, R15, R9, RZ ; /* 0x000000090f0f7210 */
/* 0x000fca0007ffe0ff */
/*01a0*/ STG.E.64 [R6.64+0x8], R14 ; /* 0x0000080e06007986 */
/* 0x000fe8000c101b04 */
/*01b0*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea8000c1e1b00 */
/*01c0*/ LDG.E.64 R10, [R2.64+0x10] ; /* 0x00001004020a7981 */
/* 0x000ea4000c1e1b00 */
/*01d0*/ IMAD R9, R9, R10, RZ ; /* 0x0000000a09097224 */
/* 0x004fc400078e02ff */
/*01e0*/ IMAD.WIDE.U32 R12, R8, R10, RZ ; /* 0x0000000a080c7225 */
/* 0x001fc800078e00ff */
/*01f0*/ IMAD R9, R8, R11, R9 ; /* 0x0000000b08097224 */
/* 0x000fca00078e0209 */
/*0200*/ IADD3 R13, R13, R9, RZ ; /* 0x000000090d0d7210 */
/* 0x000fca0007ffe0ff */
/*0210*/ STG.E.64 [R6.64+0x10], R12 ; /* 0x0000100c06007986 */
/* 0x000fe2000c101b04 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9arrayTestiPlS_S_PiS_
.globl _Z9arrayTestiPlS_S_PiS_
.p2align 8
.type _Z9arrayTestiPlS_S_PiS_,@function
_Z9arrayTestiPlS_S_PiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_lshl_add_u32 v3, v1, 1, v1
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v12, vcc_lo, v3, 8
global_load_b64 v[5:6], v[5:6], off
global_load_b64 v[7:8], v[0:1], off
v_add_co_ci_u32_e32 v13, vcc_lo, 0, v4, vcc_lo
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v8, v5
v_mul_lo_u32 v10, v7, v6
v_mad_u64_u32 v[8:9], null, v7, v5, 0
v_add_co_u32 v5, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_add3_u32 v9, v9, v10, v2
v_add_co_u32 v10, vcc_lo, s6, v12
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v13, vcc_lo
global_store_b64 v[5:6], v[8:9], off
global_load_b64 v[5:6], v[10:11], off
global_load_b64 v[7:8], v[0:1], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v10, v8, v5
v_mul_lo_u32 v6, v7, v6
v_mad_u64_u32 v[8:9], null, v7, v5, 0
v_add_co_u32 v7, vcc_lo, v3, 16
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v4, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v12
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s6, v7
v_add3_u32 v9, v9, v6, v10
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v11, vcc_lo
global_store_b64 v[2:3], v[8:9], off
global_load_b64 v[2:3], v[4:5], off
global_load_b64 v[0:1], v[0:1], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v1, v1, v2
v_mul_lo_u32 v5, v0, v3
v_mad_u64_u32 v[3:4], null, v0, v2, 0
v_add_co_u32 v0, vcc_lo, s0, v7
s_delay_alu instid0(VALU_DEP_2)
v_add3_u32 v4, v4, v5, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v11, vcc_lo
global_store_b64 v[0:1], v[3:4], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9arrayTestiPlS_S_PiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9arrayTestiPlS_S_PiS_, .Lfunc_end0-_Z9arrayTestiPlS_S_PiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9arrayTestiPlS_S_PiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9arrayTestiPlS_S_PiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001228bd_00000000-6_arrayTest.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z9arrayTestiPlS_S_PiS_iPlS_S_PiS_
.type _Z37__device_stub__Z9arrayTestiPlS_S_PiS_iPlS_S_PiS_, @function
_Z37__device_stub__Z9arrayTestiPlS_S_PiS_iPlS_S_PiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9arrayTestiPlS_S_PiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z9arrayTestiPlS_S_PiS_iPlS_S_PiS_, .-_Z37__device_stub__Z9arrayTestiPlS_S_PiS_iPlS_S_PiS_
.globl _Z9arrayTestiPlS_S_PiS_
.type _Z9arrayTestiPlS_S_PiS_, @function
_Z9arrayTestiPlS_S_PiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z9arrayTestiPlS_S_PiS_iPlS_S_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9arrayTestiPlS_S_PiS_, .-_Z9arrayTestiPlS_S_PiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9arrayTestiPlS_S_PiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9arrayTestiPlS_S_PiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "arrayTest.hip"
.globl _Z24__device_stub__arrayTestiPlS_S_PiS_ # -- Begin function _Z24__device_stub__arrayTestiPlS_S_PiS_
.p2align 4, 0x90
.type _Z24__device_stub__arrayTestiPlS_S_PiS_,@function
_Z24__device_stub__arrayTestiPlS_S_PiS_: # @_Z24__device_stub__arrayTestiPlS_S_PiS_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 4(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9arrayTestiPlS_S_PiS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z24__device_stub__arrayTestiPlS_S_PiS_, .Lfunc_end0-_Z24__device_stub__arrayTestiPlS_S_PiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9arrayTestiPlS_S_PiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9arrayTestiPlS_S_PiS_,@object # @_Z9arrayTestiPlS_S_PiS_
.section .rodata,"a",@progbits
.globl _Z9arrayTestiPlS_S_PiS_
.p2align 3, 0x0
_Z9arrayTestiPlS_S_PiS_:
.quad _Z24__device_stub__arrayTestiPlS_S_PiS_
.size _Z9arrayTestiPlS_S_PiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9arrayTestiPlS_S_PiS_"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__arrayTestiPlS_S_PiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9arrayTestiPlS_S_PiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cstdio>
void initialize(float* polynomial, const size_t N) {
for (size_t i = 0; i < N; ++i)
polynomial[i] = static_cast<float>(i);
}
__global__ void kernel(float* polynomial, const size_t N) {
int thread = blockIdx.x * blockDim.x + threadIdx.x;
if (thread < N) {
float x = polynomial[thread];
polynomial[thread] = 3 * x * x - 7 * x + 5;
}
}
int main(int argc, char** argv) {
const size_t BLOCK_DIM = 128;
const size_t N_STREAMS = 4;
// Number of elements in the arrays
size_t n_elem = 1u << 27u;
size_t n_bytes = n_elem * sizeof(float);
// Allocating the array in pinned host memory for async memcpy
float* h_polynomial;
cudaHostAlloc(&h_polynomial, n_bytes, cudaHostAllocDefault);
// Initializing data on host
initialize(h_polynomial, n_elem);
// Allocating the device array
float* d_polynomial;
cudaMalloc(&d_polynomial, n_bytes);
// Number of elements per stream
size_t n_elem_per_stream = n_elem / N_STREAMS;
size_t n_bytes_per_stream = n_elem_per_stream * sizeof(float);
// Events for time recording
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Grid and block
dim3 block(BLOCK_DIM);
dim3 grid((n_elem_per_stream + block.x - 1) / block.x);
// Creating streams
cudaStream_t* streams = new cudaStream_t[N_STREAMS];
for (size_t i = 0; i < N_STREAMS; ++i)
cudaStreamCreate(&streams[i]);
cudaEventRecord(start, 0);
//------------------------------------------------------- Asynchronous work
for (size_t i = 0; i < N_STREAMS; ++i) {
size_t offset = i * n_elem_per_stream;
cudaMemcpyAsync(&d_polynomial[offset], &h_polynomial[offset],
n_bytes_per_stream, cudaMemcpyHostToDevice, streams[i]);
kernel<<<grid, block>>>(d_polynomial + offset, n_elem_per_stream);
cudaMemcpyAsync(&h_polynomial[offset], &d_polynomial[offset],
n_bytes_per_stream, cudaMemcpyDeviceToHost, streams[i]);
}
//-------------------------------------------------------------------------
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float time;
cudaEventElapsedTime(&time, start, stop);
printf("Elapsed time: %.5f\n", time);
// Destroying events
cudaEventDestroy(stop);
cudaEventDestroy(start);
// Freeing memory
delete[] streams;
cudaFree(d_polynomial);
cudaFreeHost(h_polynomial);
} | code for sm_80
Function : _Z6kernelPfm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x16c], PT, P0 ; /* 0x00005b0003007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ LEA R2, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000027a11 */
/* 0x000fe200078010ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ LEA.HI.X R3, R0, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f1403 */
/*00b0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FMUL R5, R0.reuse, 3 ; /* 0x4040000000057820 */
/* 0x044fe40000400000 */
/*00d0*/ FMUL R4, R0, -7 ; /* 0xc0e0000000047820 */
/* 0x000fc80000400000 */
/*00e0*/ FFMA R4, R0, R5, R4 ; /* 0x0000000500047223 */
/* 0x000fc80000000004 */
/*00f0*/ FADD R5, R4, 5 ; /* 0x40a0000004057421 */
/* 0x000fca0000000000 */
/*0100*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdio>
void initialize(float* polynomial, const size_t N) {
for (size_t i = 0; i < N; ++i)
polynomial[i] = static_cast<float>(i);
}
__global__ void kernel(float* polynomial, const size_t N) {
int thread = blockIdx.x * blockDim.x + threadIdx.x;
if (thread < N) {
float x = polynomial[thread];
polynomial[thread] = 3 * x * x - 7 * x + 5;
}
}
int main(int argc, char** argv) {
const size_t BLOCK_DIM = 128;
const size_t N_STREAMS = 4;
// Number of elements in the arrays
size_t n_elem = 1u << 27u;
size_t n_bytes = n_elem * sizeof(float);
// Allocating the array in pinned host memory for async memcpy
float* h_polynomial;
cudaHostAlloc(&h_polynomial, n_bytes, cudaHostAllocDefault);
// Initializing data on host
initialize(h_polynomial, n_elem);
// Allocating the device array
float* d_polynomial;
cudaMalloc(&d_polynomial, n_bytes);
// Number of elements per stream
size_t n_elem_per_stream = n_elem / N_STREAMS;
size_t n_bytes_per_stream = n_elem_per_stream * sizeof(float);
// Events for time recording
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Grid and block
dim3 block(BLOCK_DIM);
dim3 grid((n_elem_per_stream + block.x - 1) / block.x);
// Creating streams
cudaStream_t* streams = new cudaStream_t[N_STREAMS];
for (size_t i = 0; i < N_STREAMS; ++i)
cudaStreamCreate(&streams[i]);
cudaEventRecord(start, 0);
//------------------------------------------------------- Asynchronous work
for (size_t i = 0; i < N_STREAMS; ++i) {
size_t offset = i * n_elem_per_stream;
cudaMemcpyAsync(&d_polynomial[offset], &h_polynomial[offset],
n_bytes_per_stream, cudaMemcpyHostToDevice, streams[i]);
kernel<<<grid, block>>>(d_polynomial + offset, n_elem_per_stream);
cudaMemcpyAsync(&h_polynomial[offset], &d_polynomial[offset],
n_bytes_per_stream, cudaMemcpyDeviceToHost, streams[i]);
}
//-------------------------------------------------------------------------
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float time;
cudaEventElapsedTime(&time, start, stop);
printf("Elapsed time: %.5f\n", time);
// Destroying events
cudaEventDestroy(stop);
cudaEventDestroy(start);
// Freeing memory
delete[] streams;
cudaFree(d_polynomial);
cudaFreeHost(h_polynomial);
} | .file "tmpxft_0011c85b_00000000-6_streamedPoly.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10initializePfm
.type _Z10initializePfm, @function
_Z10initializePfm:
.LFB2057:
.cfi_startproc
endbr64
testq %rsi, %rsi
je .L3
movl $0, %eax
jmp .L7
.L5:
movq %rax, %rdx
shrq %rdx
movq %rax, %rcx
andl $1, %ecx
orq %rcx, %rdx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
addss %xmm0, %xmm0
.L6:
movss %xmm0, (%rdi,%rax,4)
addq $1, %rax
cmpq %rax, %rsi
je .L3
.L7:
testq %rax, %rax
js .L5
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
jmp .L6
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z10initializePfm, .-_Z10initializePfm
.globl _Z26__device_stub__Z6kernelPfmPfm
.type _Z26__device_stub__Z6kernelPfmPfm, @function
_Z26__device_stub__Z6kernelPfmPfm:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPfm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z26__device_stub__Z6kernelPfmPfm, .-_Z26__device_stub__Z6kernelPfmPfm
.globl _Z6kernelPfm
.type _Z6kernelPfm, @function
_Z6kernelPfm:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6kernelPfmPfm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z6kernelPfm, .-_Z6kernelPfm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Elapsed time: %.5f\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $0, %edx
movl $536870912, %esi
call cudaHostAlloc@PLT
movl $134217728, %esi
movq 16(%rsp), %rdi
call _Z10initializePfm
leaq 24(%rsp), %rdi
movl $536870912, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $262144, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $32, %edi
call _Znam@PLT
movq %rax, %r12
movq %rax, %rdi
call cudaStreamCreate@PLT
leaq 8(%r12), %rdi
call cudaStreamCreate@PLT
leaq 16(%r12), %rdi
call cudaStreamCreate@PLT
leaq 24(%r12), %rdi
call cudaStreamCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %ebp
jmp .L19
.L18:
movq %rbx, %rsi
addq 24(%rsp), %rsi
addq 16(%rsp), %rbx
movq %rbx, %rdi
movq (%r12,%rbp,8), %r8
movl $2, %ecx
movl $134217728, %edx
call cudaMemcpyAsync@PLT
addq $1, %rbp
cmpq $4, %rbp
je .L23
.L19:
movq %rbp, %rbx
salq $27, %rbx
movq %rbx, %rsi
addq 16(%rsp), %rsi
movq %rbx, %rdi
addq 24(%rsp), %rdi
movq (%r12,%rbp,8), %r8
movl $1, %ecx
movl $134217728, %edx
call cudaMemcpyAsync@PLT
movl $128, 48(%rsp)
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L18
movq %rbx, %rdi
addq 24(%rsp), %rdi
movl $33554432, %esi
call _Z26__device_stub__Z6kernelPfmPfm
jmp .L18
.L23:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFreeHost@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6kernelPfm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPfm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
void initialize(float* polynomial, const size_t N) {
for (size_t i = 0; i < N; ++i)
polynomial[i] = static_cast<float>(i);
}
__global__ void kernel(float* polynomial, const size_t N) {
int thread = blockIdx.x * blockDim.x + threadIdx.x;
if (thread < N) {
float x = polynomial[thread];
polynomial[thread] = 3 * x * x - 7 * x + 5;
}
}
int main(int argc, char** argv) {
const size_t BLOCK_DIM = 128;
const size_t N_STREAMS = 4;
// Number of elements in the arrays
size_t n_elem = 1u << 27u;
size_t n_bytes = n_elem * sizeof(float);
// Allocating the array in pinned host memory for async memcpy
float* h_polynomial;
cudaHostAlloc(&h_polynomial, n_bytes, cudaHostAllocDefault);
// Initializing data on host
initialize(h_polynomial, n_elem);
// Allocating the device array
float* d_polynomial;
cudaMalloc(&d_polynomial, n_bytes);
// Number of elements per stream
size_t n_elem_per_stream = n_elem / N_STREAMS;
size_t n_bytes_per_stream = n_elem_per_stream * sizeof(float);
// Events for time recording
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
// Grid and block
dim3 block(BLOCK_DIM);
dim3 grid((n_elem_per_stream + block.x - 1) / block.x);
// Creating streams
cudaStream_t* streams = new cudaStream_t[N_STREAMS];
for (size_t i = 0; i < N_STREAMS; ++i)
cudaStreamCreate(&streams[i]);
cudaEventRecord(start, 0);
//------------------------------------------------------- Asynchronous work
for (size_t i = 0; i < N_STREAMS; ++i) {
size_t offset = i * n_elem_per_stream;
cudaMemcpyAsync(&d_polynomial[offset], &h_polynomial[offset],
n_bytes_per_stream, cudaMemcpyHostToDevice, streams[i]);
kernel<<<grid, block>>>(d_polynomial + offset, n_elem_per_stream);
cudaMemcpyAsync(&h_polynomial[offset], &d_polynomial[offset],
n_bytes_per_stream, cudaMemcpyDeviceToHost, streams[i]);
}
//-------------------------------------------------------------------------
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float time;
cudaEventElapsedTime(&time, start, stop);
printf("Elapsed time: %.5f\n", time);
// Destroying events
cudaEventDestroy(stop);
cudaEventDestroy(start);
// Freeing memory
delete[] streams;
cudaFree(d_polynomial);
cudaFreeHost(h_polynomial);
} | #include <hip/hip_runtime.h>
#include <cstdio>
void initialize(float* polynomial, const size_t N) {
for (size_t i = 0; i < N; ++i)
polynomial[i] = static_cast<float>(i);
}
__global__ void kernel(float* polynomial, const size_t N) {
int thread = blockIdx.x * blockDim.x + threadIdx.x;
if (thread < N) {
float x = polynomial[thread];
polynomial[thread] = 3 * x * x - 7 * x + 5;
}
}
int main(int argc, char** argv) {
const size_t BLOCK_DIM = 128;
const size_t N_STREAMS = 4;
// Number of elements in the arrays
size_t n_elem = 1u << 27u;
size_t n_bytes = n_elem * sizeof(float);
// Allocating the array in pinned host memory for async memcpy
float* h_polynomial;
hipHostAlloc(&h_polynomial, n_bytes, hipHostMallocDefault);
// Initializing data on host
initialize(h_polynomial, n_elem);
// Allocating the device array
float* d_polynomial;
hipMalloc(&d_polynomial, n_bytes);
// Number of elements per stream
size_t n_elem_per_stream = n_elem / N_STREAMS;
size_t n_bytes_per_stream = n_elem_per_stream * sizeof(float);
// Events for time recording
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Grid and block
dim3 block(BLOCK_DIM);
dim3 grid((n_elem_per_stream + block.x - 1) / block.x);
// Creating streams
hipStream_t* streams = new hipStream_t[N_STREAMS];
for (size_t i = 0; i < N_STREAMS; ++i)
hipStreamCreate(&streams[i]);
hipEventRecord(start, 0);
//------------------------------------------------------- Asynchronous work
for (size_t i = 0; i < N_STREAMS; ++i) {
size_t offset = i * n_elem_per_stream;
hipMemcpyAsync(&d_polynomial[offset], &h_polynomial[offset],
n_bytes_per_stream, hipMemcpyHostToDevice, streams[i]);
kernel<<<grid, block>>>(d_polynomial + offset, n_elem_per_stream);
hipMemcpyAsync(&h_polynomial[offset], &d_polynomial[offset],
n_bytes_per_stream, hipMemcpyDeviceToHost, streams[i]);
}
//-------------------------------------------------------------------------
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float time;
hipEventElapsedTime(&time, start, stop);
printf("Elapsed time: %.5f\n", time);
// Destroying events
hipEventDestroy(stop);
hipEventDestroy(start);
// Freeing memory
delete[] streams;
hipFree(d_polynomial);
hipHostFree(h_polynomial);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
void initialize(float* polynomial, const size_t N) {
for (size_t i = 0; i < N; ++i)
polynomial[i] = static_cast<float>(i);
}
__global__ void kernel(float* polynomial, const size_t N) {
int thread = blockIdx.x * blockDim.x + threadIdx.x;
if (thread < N) {
float x = polynomial[thread];
polynomial[thread] = 3 * x * x - 7 * x + 5;
}
}
int main(int argc, char** argv) {
const size_t BLOCK_DIM = 128;
const size_t N_STREAMS = 4;
// Number of elements in the arrays
size_t n_elem = 1u << 27u;
size_t n_bytes = n_elem * sizeof(float);
// Allocating the array in pinned host memory for async memcpy
float* h_polynomial;
hipHostAlloc(&h_polynomial, n_bytes, hipHostMallocDefault);
// Initializing data on host
initialize(h_polynomial, n_elem);
// Allocating the device array
float* d_polynomial;
hipMalloc(&d_polynomial, n_bytes);
// Number of elements per stream
size_t n_elem_per_stream = n_elem / N_STREAMS;
size_t n_bytes_per_stream = n_elem_per_stream * sizeof(float);
// Events for time recording
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Grid and block
dim3 block(BLOCK_DIM);
dim3 grid((n_elem_per_stream + block.x - 1) / block.x);
// Creating streams
hipStream_t* streams = new hipStream_t[N_STREAMS];
for (size_t i = 0; i < N_STREAMS; ++i)
hipStreamCreate(&streams[i]);
hipEventRecord(start, 0);
//------------------------------------------------------- Asynchronous work
for (size_t i = 0; i < N_STREAMS; ++i) {
size_t offset = i * n_elem_per_stream;
hipMemcpyAsync(&d_polynomial[offset], &h_polynomial[offset],
n_bytes_per_stream, hipMemcpyHostToDevice, streams[i]);
kernel<<<grid, block>>>(d_polynomial + offset, n_elem_per_stream);
hipMemcpyAsync(&h_polynomial[offset], &d_polynomial[offset],
n_bytes_per_stream, hipMemcpyDeviceToHost, streams[i]);
}
//-------------------------------------------------------------------------
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float time;
hipEventElapsedTime(&time, start, stop);
printf("Elapsed time: %.5f\n", time);
// Destroying events
hipEventDestroy(stop);
hipEventDestroy(start);
// Freeing memory
delete[] streams;
hipFree(d_polynomial);
hipHostFree(h_polynomial);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPfm
.globl _Z6kernelPfm
.p2align 8
.type _Z6kernelPfm,@function
_Z6kernelPfm:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v3, 0x40400000, v2
v_mul_f32_e32 v4, 0xc0e00000, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v2, v3
v_add_f32_e32 v2, 0x40a00000, v4
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPfm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPfm, .Lfunc_end0-_Z6kernelPfm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPfm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPfm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
void initialize(float* polynomial, const size_t N) {
for (size_t i = 0; i < N; ++i)
polynomial[i] = static_cast<float>(i);
}
__global__ void kernel(float* polynomial, const size_t N) {
int thread = blockIdx.x * blockDim.x + threadIdx.x;
if (thread < N) {
float x = polynomial[thread];
polynomial[thread] = 3 * x * x - 7 * x + 5;
}
}
int main(int argc, char** argv) {
const size_t BLOCK_DIM = 128;
const size_t N_STREAMS = 4;
// Number of elements in the arrays
size_t n_elem = 1u << 27u;
size_t n_bytes = n_elem * sizeof(float);
// Allocating the array in pinned host memory for async memcpy
float* h_polynomial;
hipHostAlloc(&h_polynomial, n_bytes, hipHostMallocDefault);
// Initializing data on host
initialize(h_polynomial, n_elem);
// Allocating the device array
float* d_polynomial;
hipMalloc(&d_polynomial, n_bytes);
// Number of elements per stream
size_t n_elem_per_stream = n_elem / N_STREAMS;
size_t n_bytes_per_stream = n_elem_per_stream * sizeof(float);
// Events for time recording
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
// Grid and block
dim3 block(BLOCK_DIM);
dim3 grid((n_elem_per_stream + block.x - 1) / block.x);
// Creating streams
hipStream_t* streams = new hipStream_t[N_STREAMS];
for (size_t i = 0; i < N_STREAMS; ++i)
hipStreamCreate(&streams[i]);
hipEventRecord(start, 0);
//------------------------------------------------------- Asynchronous work
for (size_t i = 0; i < N_STREAMS; ++i) {
size_t offset = i * n_elem_per_stream;
hipMemcpyAsync(&d_polynomial[offset], &h_polynomial[offset],
n_bytes_per_stream, hipMemcpyHostToDevice, streams[i]);
kernel<<<grid, block>>>(d_polynomial + offset, n_elem_per_stream);
hipMemcpyAsync(&h_polynomial[offset], &d_polynomial[offset],
n_bytes_per_stream, hipMemcpyDeviceToHost, streams[i]);
}
//-------------------------------------------------------------------------
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
float time;
hipEventElapsedTime(&time, start, stop);
printf("Elapsed time: %.5f\n", time);
// Destroying events
hipEventDestroy(stop);
hipEventDestroy(start);
// Freeing memory
delete[] streams;
hipFree(d_polynomial);
hipHostFree(h_polynomial);
} | .text
.file "streamedPoly.hip"
.globl _Z10initializePfm # -- Begin function _Z10initializePfm
.p2align 4, 0x90
.type _Z10initializePfm,@function
_Z10initializePfm: # @_Z10initializePfm
.cfi_startproc
# %bb.0:
testq %rsi, %rsi
je .LBB0_6
# %bb.1: # %.lr.ph.preheader
xorl %eax, %eax
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_4: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
.LBB0_5: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movss %xmm0, (%rdi,%rax,4)
incq %rax
cmpq %rax, %rsi
je .LBB0_6
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
testq %rax, %rax
jns .LBB0_4
# %bb.3: # in Loop: Header=BB0_2 Depth=1
movq %rax, %rcx
shrq %rcx
movl %eax, %edx
andl $1, %edx
orq %rcx, %rdx
xorps %xmm0, %xmm0
cvtsi2ss %rdx, %xmm0
addss %xmm0, %xmm0
jmp .LBB0_5
.LBB0_6: # %._crit_edge
retq
.Lfunc_end0:
.size _Z10initializePfm, .Lfunc_end0-_Z10initializePfm
.cfi_endproc
# -- End function
.globl _Z21__device_stub__kernelPfm # -- Begin function _Z21__device_stub__kernelPfm
.p2align 4, 0x90
.type _Z21__device_stub__kernelPfm,@function
_Z21__device_stub__kernelPfm: # @_Z21__device_stub__kernelPfm
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPfm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z21__device_stub__kernelPfm, .Lfunc_end1-_Z21__device_stub__kernelPfm
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 16(%rsp), %rdi
xorl %ebx, %ebx
movl $536870912, %esi # imm = 0x20000000
xorl %edx, %edx
callq hipHostAlloc
movq 16(%rsp), %rax
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i
# in Loop: Header=BB2_1 Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %rbx, %xmm0
.LBB2_4: # %.lr.ph.i
# in Loop: Header=BB2_1 Depth=1
movss %xmm0, (%rax,%rbx,4)
incq %rbx
cmpq $134217728, %rbx # imm = 0x8000000
je .LBB2_5
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
testq %rbx, %rbx
jns .LBB2_3
# %bb.2: # in Loop: Header=BB2_1 Depth=1
movq %rbx, %rcx
shrq %rcx
movl %ebx, %edx
andl $1, %edx
orq %rcx, %rdx
xorps %xmm0, %xmm0
cvtsi2ss %rdx, %xmm0
addss %xmm0, %xmm0
jmp .LBB2_4
.LBB2_5: # %_Z10initializePfm.exit
leaq 8(%rsp), %rdi
movl $536870912, %esi # imm = 0x20000000
callq hipMalloc
leaq 24(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movl $32, %edi
callq _Znam
movq %rax, %r12
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_6: # =>This Inner Loop Header: Depth=1
leaq (%r12,%rbx), %rdi
callq hipStreamCreate
addq $8, %rbx
cmpq $32, %rbx
jne .LBB2_6
# %bb.7:
movabsq $4294967424, %r14 # imm = 0x100000080
movq 24(%rsp), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
callq hipEventRecord
leaq 262016(%r14), %r15
leaq 32(%rsp), %r13
movq %r12, %rbx
jmp .LBB2_8
.p2align 4, 0x90
.LBB2_10: # in Loop: Header=BB2_8 Depth=1
movq 16(%rsp), %rdi
addq %rbp, %rdi
movq 8(%rsp), %rsi
addq %rbp, %rsi
movq (%rbx), %r8
movl $134217728, %edx # imm = 0x8000000
movl $2, %ecx
callq hipMemcpyAsync
addq $134217728, %rbp # imm = 0x8000000
addq $8, %rbx
cmpq $536870912, %rbp # imm = 0x20000000
je .LBB2_11
.LBB2_8: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rdi
addq %rbp, %rdi
movq 16(%rsp), %rsi
addq %rbp, %rsi
movq (%rbx), %r8
movl $134217728, %edx # imm = 0x8000000
movl $1, %ecx
callq hipMemcpyAsync
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9: # in Loop: Header=BB2_8 Depth=1
movq 8(%rsp), %rax
addq %rbp, %rax
movq %rax, 112(%rsp)
movq $33554432, 104(%rsp) # imm = 0x2000000
leaq 112(%rsp), %rax
movq %rax, 32(%rsp)
leaq 104(%rsp), %rax
movq %rax, 40(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
movl $_Z6kernelPfm, %edi
movq %r13, %r9
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_10
.LBB2_11:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq (%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq (%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rdi
callq hipEventDestroy
movq %r12, %rdi
callq _ZdaPv
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipHostFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPfm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPfm,@object # @_Z6kernelPfm
.section .rodata,"a",@progbits
.globl _Z6kernelPfm
.p2align 3, 0x0
_Z6kernelPfm:
.quad _Z21__device_stub__kernelPfm
.size _Z6kernelPfm, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Elapsed time: %.5f\n"
.size .L.str, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPfm"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPfm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPfm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelPfm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x16c], PT, P0 ; /* 0x00005b0003007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ LEA R2, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000027a11 */
/* 0x000fe200078010ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ LEA.HI.X R3, R0, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f1403 */
/*00b0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FMUL R5, R0.reuse, 3 ; /* 0x4040000000057820 */
/* 0x044fe40000400000 */
/*00d0*/ FMUL R4, R0, -7 ; /* 0xc0e0000000047820 */
/* 0x000fc80000400000 */
/*00e0*/ FFMA R4, R0, R5, R4 ; /* 0x0000000500047223 */
/* 0x000fc80000000004 */
/*00f0*/ FADD R5, R4, 5 ; /* 0x40a0000004057421 */
/* 0x000fca0000000000 */
/*0100*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPfm
.globl _Z6kernelPfm
.p2align 8
.type _Z6kernelPfm,@function
_Z6kernelPfm:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v3, 0x40400000, v2
v_mul_f32_e32 v4, 0xc0e00000, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v2, v3
v_add_f32_e32 v2, 0x40a00000, v4
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPfm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPfm, .Lfunc_end0-_Z6kernelPfm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPfm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPfm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011c85b_00000000-6_streamedPoly.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10initializePfm
.type _Z10initializePfm, @function
_Z10initializePfm:
.LFB2057:
.cfi_startproc
endbr64
testq %rsi, %rsi
je .L3
movl $0, %eax
jmp .L7
.L5:
movq %rax, %rdx
shrq %rdx
movq %rax, %rcx
andl $1, %ecx
orq %rcx, %rdx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
addss %xmm0, %xmm0
.L6:
movss %xmm0, (%rdi,%rax,4)
addq $1, %rax
cmpq %rax, %rsi
je .L3
.L7:
testq %rax, %rax
js .L5
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
jmp .L6
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z10initializePfm, .-_Z10initializePfm
.globl _Z26__device_stub__Z6kernelPfmPfm
.type _Z26__device_stub__Z6kernelPfmPfm, @function
_Z26__device_stub__Z6kernelPfmPfm:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPfm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z26__device_stub__Z6kernelPfmPfm, .-_Z26__device_stub__Z6kernelPfmPfm
.globl _Z6kernelPfm
.type _Z6kernelPfm, @function
_Z6kernelPfm:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6kernelPfmPfm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z6kernelPfm, .-_Z6kernelPfm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Elapsed time: %.5f\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $0, %edx
movl $536870912, %esi
call cudaHostAlloc@PLT
movl $134217728, %esi
movq 16(%rsp), %rdi
call _Z10initializePfm
leaq 24(%rsp), %rdi
movl $536870912, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $262144, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $32, %edi
call _Znam@PLT
movq %rax, %r12
movq %rax, %rdi
call cudaStreamCreate@PLT
leaq 8(%r12), %rdi
call cudaStreamCreate@PLT
leaq 16(%r12), %rdi
call cudaStreamCreate@PLT
leaq 24(%r12), %rdi
call cudaStreamCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %ebp
jmp .L19
.L18:
movq %rbx, %rsi
addq 24(%rsp), %rsi
addq 16(%rsp), %rbx
movq %rbx, %rdi
movq (%r12,%rbp,8), %r8
movl $2, %ecx
movl $134217728, %edx
call cudaMemcpyAsync@PLT
addq $1, %rbp
cmpq $4, %rbp
je .L23
.L19:
movq %rbp, %rbx
salq $27, %rbx
movq %rbx, %rsi
addq 16(%rsp), %rsi
movq %rbx, %rdi
addq 24(%rsp), %rdi
movq (%r12,%rbp,8), %r8
movl $1, %ecx
movl $134217728, %edx
call cudaMemcpyAsync@PLT
movl $128, 48(%rsp)
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L18
movq %rbx, %rdi
addq 24(%rsp), %rdi
movl $33554432, %esi
call _Z26__device_stub__Z6kernelPfmPfm
jmp .L18
.L23:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFreeHost@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6kernelPfm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPfm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "streamedPoly.hip"
.globl _Z10initializePfm # -- Begin function _Z10initializePfm
.p2align 4, 0x90
.type _Z10initializePfm,@function
_Z10initializePfm: # @_Z10initializePfm
.cfi_startproc
# %bb.0:
testq %rsi, %rsi
je .LBB0_6
# %bb.1: # %.lr.ph.preheader
xorl %eax, %eax
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_4: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
.LBB0_5: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movss %xmm0, (%rdi,%rax,4)
incq %rax
cmpq %rax, %rsi
je .LBB0_6
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
testq %rax, %rax
jns .LBB0_4
# %bb.3: # in Loop: Header=BB0_2 Depth=1
movq %rax, %rcx
shrq %rcx
movl %eax, %edx
andl $1, %edx
orq %rcx, %rdx
xorps %xmm0, %xmm0
cvtsi2ss %rdx, %xmm0
addss %xmm0, %xmm0
jmp .LBB0_5
.LBB0_6: # %._crit_edge
retq
.Lfunc_end0:
.size _Z10initializePfm, .Lfunc_end0-_Z10initializePfm
.cfi_endproc
# -- End function
.globl _Z21__device_stub__kernelPfm # -- Begin function _Z21__device_stub__kernelPfm
.p2align 4, 0x90
.type _Z21__device_stub__kernelPfm,@function
_Z21__device_stub__kernelPfm: # @_Z21__device_stub__kernelPfm
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPfm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z21__device_stub__kernelPfm, .Lfunc_end1-_Z21__device_stub__kernelPfm
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 16(%rsp), %rdi
xorl %ebx, %ebx
movl $536870912, %esi # imm = 0x20000000
xorl %edx, %edx
callq hipHostAlloc
movq 16(%rsp), %rax
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i
# in Loop: Header=BB2_1 Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %rbx, %xmm0
.LBB2_4: # %.lr.ph.i
# in Loop: Header=BB2_1 Depth=1
movss %xmm0, (%rax,%rbx,4)
incq %rbx
cmpq $134217728, %rbx # imm = 0x8000000
je .LBB2_5
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
testq %rbx, %rbx
jns .LBB2_3
# %bb.2: # in Loop: Header=BB2_1 Depth=1
movq %rbx, %rcx
shrq %rcx
movl %ebx, %edx
andl $1, %edx
orq %rcx, %rdx
xorps %xmm0, %xmm0
cvtsi2ss %rdx, %xmm0
addss %xmm0, %xmm0
jmp .LBB2_4
.LBB2_5: # %_Z10initializePfm.exit
leaq 8(%rsp), %rdi
movl $536870912, %esi # imm = 0x20000000
callq hipMalloc
leaq 24(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movl $32, %edi
callq _Znam
movq %rax, %r12
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_6: # =>This Inner Loop Header: Depth=1
leaq (%r12,%rbx), %rdi
callq hipStreamCreate
addq $8, %rbx
cmpq $32, %rbx
jne .LBB2_6
# %bb.7:
movabsq $4294967424, %r14 # imm = 0x100000080
movq 24(%rsp), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
callq hipEventRecord
leaq 262016(%r14), %r15
leaq 32(%rsp), %r13
movq %r12, %rbx
jmp .LBB2_8
.p2align 4, 0x90
.LBB2_10: # in Loop: Header=BB2_8 Depth=1
movq 16(%rsp), %rdi
addq %rbp, %rdi
movq 8(%rsp), %rsi
addq %rbp, %rsi
movq (%rbx), %r8
movl $134217728, %edx # imm = 0x8000000
movl $2, %ecx
callq hipMemcpyAsync
addq $134217728, %rbp # imm = 0x8000000
addq $8, %rbx
cmpq $536870912, %rbp # imm = 0x20000000
je .LBB2_11
.LBB2_8: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rdi
addq %rbp, %rdi
movq 16(%rsp), %rsi
addq %rbp, %rsi
movq (%rbx), %r8
movl $134217728, %edx # imm = 0x8000000
movl $1, %ecx
callq hipMemcpyAsync
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9: # in Loop: Header=BB2_8 Depth=1
movq 8(%rsp), %rax
addq %rbp, %rax
movq %rax, 112(%rsp)
movq $33554432, 104(%rsp) # imm = 0x2000000
leaq 112(%rsp), %rax
movq %rax, 32(%rsp)
leaq 104(%rsp), %rax
movq %rax, 40(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
movl $_Z6kernelPfm, %edi
movq %r13, %r9
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_10
.LBB2_11:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq (%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq (%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rdi
callq hipEventDestroy
movq %r12, %rdi
callq _ZdaPv
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipHostFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPfm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPfm,@object # @_Z6kernelPfm
.section .rodata,"a",@progbits
.globl _Z6kernelPfm
.p2align 3, 0x0
_Z6kernelPfm:
.quad _Z21__device_stub__kernelPfm
.size _Z6kernelPfm, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Elapsed time: %.5f\n"
.size .L.str, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPfm"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPfm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPfm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* simulator_kernel_impl.cu
*
* Created on: Jul 18, 2014
* Author: bqian
*/ | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* simulator_kernel_impl.cu
*
* Created on: Jul 18, 2014
* Author: bqian
*/ | .file "tmpxft_000a622e_00000000-6_simulator_kernel_impl.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* simulator_kernel_impl.cu
*
* Created on: Jul 18, 2014
* Author: bqian
*/ | #include <hip/hip_runtime.h>
/*
* simulator_kernel_impl.cu
*
* Created on: Jul 18, 2014
* Author: bqian
*/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*
* simulator_kernel_impl.cu
*
* Created on: Jul 18, 2014
* Author: bqian
*/ | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*
* simulator_kernel_impl.cu
*
* Created on: Jul 18, 2014
* Author: bqian
*/ | .text
.file "simulator_kernel_impl.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a622e_00000000-6_simulator_kernel_impl.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "simulator_kernel_impl.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __device__ inline void add(int4& a, const uchar4& b) {
a.x += b.x;
a.y += b.y;
a.z += b.z;
}
extern "C" __global__
void smooth1(const uchar4* d_input, uchar4* d_output,
const int width, const int height, const int depth,
const int windowSize) {
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
const int z = blockIdx.z * blockDim.z + threadIdx.z;
if (x < width && y < height && z < depth) {
int4 a = make_int4(0, 0, 0, 0);
int count = 0;
for (int dz = -windowSize; dz <= windowSize; dz ++) {
for (int dy = -windowSize; dy <= windowSize; dy ++) {
for (int dx = -windowSize; dx <= windowSize; dx ++) {
const int nx = x + dx;
const int ny = y + dy;
const int nz = z + dz;
if (0 <= nx && nx < width
&& 0 <= ny && ny < height
&& 0 <= nz && nz < depth) {
const long idx = nz * (width*height) + ny * width + nx;
#ifdef READ
add(a, d_input[idx]);
#endif
count++;
}
}
}
}
const long idx = z * (width*height) + y * width + x;
#ifdef WRITE
d_output[idx] = make_uchar4(a.x/count, a.y/count, a.z/count, 255);
#endif
}
}
extern "C" __global__
void smooth3(void) {
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
const int z = blockIdx.z * blockDim.z + threadIdx.z;
}
extern "C" __global__
void smooth2(const uchar4* d_input, uchar4* d_output) {
const int width = 1024;
const int height= 1024;
const int depth = 1;
const int windowSize = 1;
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
const int z = blockIdx.z * blockDim.z + threadIdx.z;
/*
if (x < width && y < height && z < depth) {
int4 a = make_int4(0, 0, 0, 0);
int count = 0;
for (int dz = -windowSize; dz <= windowSize; dz ++) {
for (int dy = -windowSize; dy <= windowSize; dy ++) {
for (int dx = -windowSize; dx <= windowSize; dx ++) {
const int nx = x + dx;
const int ny = y + dy;
const int nz = z + dz;
if (0 <= nx && nx < width
&& 0 <= ny && ny < height
&& 0 <= nz && nz < depth) {
const long idx = nz * (width*height) + ny * width + nx;
#ifdef READ
add(a, d_input[idx]);
#endif
count++;
}
}
}
}
const long idx = z * (width*height) + y * width + x;
#ifdef WRITE
d_output[idx] = make_uchar4(a.x/count, a.y/count, a.z/count, 255);
#endif
}
*/
} | code for sm_80
Function : smooth2
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : smooth3
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : smooth1
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e680000002100 */
/*0050*/ S2R R4, SR_CTAID.Z ; /* 0x0000000000047919 */
/* 0x000ea80000002700 */
/*0060*/ S2R R7, SR_TID.Z ; /* 0x0000000000077919 */
/* 0x000ea20000002300 */
/*0070*/ IMAD R2, R2, c[0x0][0x4], R5 ; /* 0x0000010002027a24 */
/* 0x001fca00078e0205 */
/*0080*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x174], PT ; /* 0x00005d0002007a0c */
/* 0x000fe20003f06270 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*00a0*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fe20000706670 */
/*00b0*/ IMAD R2, R4, c[0x0][0x8], R7 ; /* 0x0000020004027a24 */
/* 0x004fca00078e0207 */
/*00c0*/ ISETP.GE.OR P0, PT, R2, c[0x0][0x178], P0 ; /* 0x00005e0002007a0c */
/* 0x000fda0000706670 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R0, RZ, -c[0x0][0x17c], RZ ; /* 0x80005f00ff007a10 */
/* 0x000fc80007ffe0ff */
/*00f0*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fda0003f04270 */
/*0100*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __device__ inline void add(int4& a, const uchar4& b) {
a.x += b.x;
a.y += b.y;
a.z += b.z;
}
extern "C" __global__
void smooth1(const uchar4* d_input, uchar4* d_output,
const int width, const int height, const int depth,
const int windowSize) {
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
const int z = blockIdx.z * blockDim.z + threadIdx.z;
if (x < width && y < height && z < depth) {
int4 a = make_int4(0, 0, 0, 0);
int count = 0;
for (int dz = -windowSize; dz <= windowSize; dz ++) {
for (int dy = -windowSize; dy <= windowSize; dy ++) {
for (int dx = -windowSize; dx <= windowSize; dx ++) {
const int nx = x + dx;
const int ny = y + dy;
const int nz = z + dz;
if (0 <= nx && nx < width
&& 0 <= ny && ny < height
&& 0 <= nz && nz < depth) {
const long idx = nz * (width*height) + ny * width + nx;
#ifdef READ
add(a, d_input[idx]);
#endif
count++;
}
}
}
}
const long idx = z * (width*height) + y * width + x;
#ifdef WRITE
d_output[idx] = make_uchar4(a.x/count, a.y/count, a.z/count, 255);
#endif
}
}
extern "C" __global__
void smooth3(void) {
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
const int z = blockIdx.z * blockDim.z + threadIdx.z;
}
extern "C" __global__
void smooth2(const uchar4* d_input, uchar4* d_output) {
const int width = 1024;
const int height= 1024;
const int depth = 1;
const int windowSize = 1;
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
const int z = blockIdx.z * blockDim.z + threadIdx.z;
/*
if (x < width && y < height && z < depth) {
int4 a = make_int4(0, 0, 0, 0);
int count = 0;
for (int dz = -windowSize; dz <= windowSize; dz ++) {
for (int dy = -windowSize; dy <= windowSize; dy ++) {
for (int dx = -windowSize; dx <= windowSize; dx ++) {
const int nx = x + dx;
const int ny = y + dy;
const int nz = z + dz;
if (0 <= nx && nx < width
&& 0 <= ny && ny < height
&& 0 <= nz && nz < depth) {
const long idx = nz * (width*height) + ny * width + nx;
#ifdef READ
add(a, d_input[idx]);
#endif
count++;
}
}
}
}
const long idx = z * (width*height) + y * width + x;
#ifdef WRITE
d_output[idx] = make_uchar4(a.x/count, a.y/count, a.z/count, 255);
#endif
}
*/
} | .file "tmpxft_00122922_00000000-6_smooth1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z7smooth1PK6uchar4PS_iiiiPK6uchar4PS_iiii
.type _Z40__device_stub__Z7smooth1PK6uchar4PS_iiiiPK6uchar4PS_iiii, @function
_Z40__device_stub__Z7smooth1PK6uchar4PS_iiiiPK6uchar4PS_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq smooth1(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z40__device_stub__Z7smooth1PK6uchar4PS_iiiiPK6uchar4PS_iiii, .-_Z40__device_stub__Z7smooth1PK6uchar4PS_iiiiPK6uchar4PS_iiii
.globl smooth1
.type smooth1, @function
smooth1:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z7smooth1PK6uchar4PS_iiiiPK6uchar4PS_iiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size smooth1, .-smooth1
.globl _Z25__device_stub__Z7smooth3vv
.type _Z25__device_stub__Z7smooth3vv, @function
_Z25__device_stub__Z7smooth3vv:
.LFB2054:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq smooth3(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z25__device_stub__Z7smooth3vv, .-_Z25__device_stub__Z7smooth3vv
.globl smooth3
.type smooth3, @function
smooth3:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z7smooth3vv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size smooth3, .-smooth3
.globl _Z36__device_stub__Z7smooth2PK6uchar4PS_PK6uchar4PS_
.type _Z36__device_stub__Z7smooth2PK6uchar4PS_PK6uchar4PS_, @function
_Z36__device_stub__Z7smooth2PK6uchar4PS_PK6uchar4PS_:
.LFB2056:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq smooth2(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2056:
.size _Z36__device_stub__Z7smooth2PK6uchar4PS_PK6uchar4PS_, .-_Z36__device_stub__Z7smooth2PK6uchar4PS_PK6uchar4PS_
.globl smooth2
.type smooth2, @function
smooth2:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z7smooth2PK6uchar4PS_PK6uchar4PS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size smooth2, .-smooth2
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "smooth2"
.LC1:
.string "smooth3"
.LC2:
.string "smooth1"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq smooth2(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq smooth3(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq smooth1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __device__ inline void add(int4& a, const uchar4& b) {
a.x += b.x;
a.y += b.y;
a.z += b.z;
}
extern "C" __global__
void smooth1(const uchar4* d_input, uchar4* d_output,
const int width, const int height, const int depth,
const int windowSize) {
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
const int z = blockIdx.z * blockDim.z + threadIdx.z;
if (x < width && y < height && z < depth) {
int4 a = make_int4(0, 0, 0, 0);
int count = 0;
for (int dz = -windowSize; dz <= windowSize; dz ++) {
for (int dy = -windowSize; dy <= windowSize; dy ++) {
for (int dx = -windowSize; dx <= windowSize; dx ++) {
const int nx = x + dx;
const int ny = y + dy;
const int nz = z + dz;
if (0 <= nx && nx < width
&& 0 <= ny && ny < height
&& 0 <= nz && nz < depth) {
const long idx = nz * (width*height) + ny * width + nx;
#ifdef READ
add(a, d_input[idx]);
#endif
count++;
}
}
}
}
const long idx = z * (width*height) + y * width + x;
#ifdef WRITE
d_output[idx] = make_uchar4(a.x/count, a.y/count, a.z/count, 255);
#endif
}
}
extern "C" __global__
void smooth3(void) {
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
const int z = blockIdx.z * blockDim.z + threadIdx.z;
}
extern "C" __global__
void smooth2(const uchar4* d_input, uchar4* d_output) {
const int width = 1024;
const int height= 1024;
const int depth = 1;
const int windowSize = 1;
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
const int z = blockIdx.z * blockDim.z + threadIdx.z;
/*
if (x < width && y < height && z < depth) {
int4 a = make_int4(0, 0, 0, 0);
int count = 0;
for (int dz = -windowSize; dz <= windowSize; dz ++) {
for (int dy = -windowSize; dy <= windowSize; dy ++) {
for (int dx = -windowSize; dx <= windowSize; dx ++) {
const int nx = x + dx;
const int ny = y + dy;
const int nz = z + dz;
if (0 <= nx && nx < width
&& 0 <= ny && ny < height
&& 0 <= nz && nz < depth) {
const long idx = nz * (width*height) + ny * width + nx;
#ifdef READ
add(a, d_input[idx]);
#endif
count++;
}
}
}
}
const long idx = z * (width*height) + y * width + x;
#ifdef WRITE
d_output[idx] = make_uchar4(a.x/count, a.y/count, a.z/count, 255);
#endif
}
*/
} | #include <hip/hip_runtime.h>
__device__ inline void add(int4& a, const uchar4& b) {
a.x += b.x;
a.y += b.y;
a.z += b.z;
}
extern "C" __global__
void smooth1(const uchar4* d_input, uchar4* d_output,
const int width, const int height, const int depth,
const int windowSize) {
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
const int z = blockIdx.z * blockDim.z + threadIdx.z;
if (x < width && y < height && z < depth) {
int4 a = make_int4(0, 0, 0, 0);
int count = 0;
for (int dz = -windowSize; dz <= windowSize; dz ++) {
for (int dy = -windowSize; dy <= windowSize; dy ++) {
for (int dx = -windowSize; dx <= windowSize; dx ++) {
const int nx = x + dx;
const int ny = y + dy;
const int nz = z + dz;
if (0 <= nx && nx < width
&& 0 <= ny && ny < height
&& 0 <= nz && nz < depth) {
const long idx = nz * (width*height) + ny * width + nx;
#ifdef READ
add(a, d_input[idx]);
#endif
count++;
}
}
}
}
const long idx = z * (width*height) + y * width + x;
#ifdef WRITE
d_output[idx] = make_uchar4(a.x/count, a.y/count, a.z/count, 255);
#endif
}
}
extern "C" __global__
void smooth3(void) {
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
const int z = blockIdx.z * blockDim.z + threadIdx.z;
}
extern "C" __global__
void smooth2(const uchar4* d_input, uchar4* d_output) {
const int width = 1024;
const int height= 1024;
const int depth = 1;
const int windowSize = 1;
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
const int z = blockIdx.z * blockDim.z + threadIdx.z;
/*
if (x < width && y < height && z < depth) {
int4 a = make_int4(0, 0, 0, 0);
int count = 0;
for (int dz = -windowSize; dz <= windowSize; dz ++) {
for (int dy = -windowSize; dy <= windowSize; dy ++) {
for (int dx = -windowSize; dx <= windowSize; dx ++) {
const int nx = x + dx;
const int ny = y + dy;
const int nz = z + dz;
if (0 <= nx && nx < width
&& 0 <= ny && ny < height
&& 0 <= nz && nz < depth) {
const long idx = nz * (width*height) + ny * width + nx;
#ifdef READ
add(a, d_input[idx]);
#endif
count++;
}
}
}
}
const long idx = z * (width*height) + y * width + x;
#ifdef WRITE
d_output[idx] = make_uchar4(a.x/count, a.y/count, a.z/count, 255);
#endif
}
*/
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__device__ inline void add(int4& a, const uchar4& b) {
a.x += b.x;
a.y += b.y;
a.z += b.z;
}
extern "C" __global__
void smooth1(const uchar4* d_input, uchar4* d_output,
const int width, const int height, const int depth,
const int windowSize) {
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
const int z = blockIdx.z * blockDim.z + threadIdx.z;
if (x < width && y < height && z < depth) {
int4 a = make_int4(0, 0, 0, 0);
int count = 0;
for (int dz = -windowSize; dz <= windowSize; dz ++) {
for (int dy = -windowSize; dy <= windowSize; dy ++) {
for (int dx = -windowSize; dx <= windowSize; dx ++) {
const int nx = x + dx;
const int ny = y + dy;
const int nz = z + dz;
if (0 <= nx && nx < width
&& 0 <= ny && ny < height
&& 0 <= nz && nz < depth) {
const long idx = nz * (width*height) + ny * width + nx;
#ifdef READ
add(a, d_input[idx]);
#endif
count++;
}
}
}
}
const long idx = z * (width*height) + y * width + x;
#ifdef WRITE
d_output[idx] = make_uchar4(a.x/count, a.y/count, a.z/count, 255);
#endif
}
}
extern "C" __global__
void smooth3(void) {
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
const int z = blockIdx.z * blockDim.z + threadIdx.z;
}
extern "C" __global__
void smooth2(const uchar4* d_input, uchar4* d_output) {
const int width = 1024;
const int height= 1024;
const int depth = 1;
const int windowSize = 1;
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
const int z = blockIdx.z * blockDim.z + threadIdx.z;
/*
if (x < width && y < height && z < depth) {
int4 a = make_int4(0, 0, 0, 0);
int count = 0;
for (int dz = -windowSize; dz <= windowSize; dz ++) {
for (int dy = -windowSize; dy <= windowSize; dy ++) {
for (int dx = -windowSize; dx <= windowSize; dx ++) {
const int nx = x + dx;
const int ny = y + dy;
const int nz = z + dz;
if (0 <= nx && nx < width
&& 0 <= ny && ny < height
&& 0 <= nz && nz < depth) {
const long idx = nz * (width*height) + ny * width + nx;
#ifdef READ
add(a, d_input[idx]);
#endif
count++;
}
}
}
}
const long idx = z * (width*height) + y * width + x;
#ifdef WRITE
d_output[idx] = make_uchar4(a.x/count, a.y/count, a.z/count, 255);
#endif
}
*/
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected smooth1
.globl smooth1
.p2align 8
.type smooth1,@function
smooth1:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel smooth1
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size smooth1, .Lfunc_end0-smooth1
.section .AMDGPU.csdata,"",@progbits
.text
.protected smooth3
.globl smooth3
.p2align 8
.type smooth3,@function
smooth3:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel smooth3
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size smooth3, .Lfunc_end1-smooth3
.section .AMDGPU.csdata,"",@progbits
.text
.protected smooth2
.globl smooth2
.p2align 8
.type smooth2,@function
smooth2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel smooth2
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size smooth2, .Lfunc_end2-smooth2
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: smooth1
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: smooth1.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: smooth3
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: smooth3.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: smooth2
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: smooth2.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__device__ inline void add(int4& a, const uchar4& b) {
a.x += b.x;
a.y += b.y;
a.z += b.z;
}
extern "C" __global__
void smooth1(const uchar4* d_input, uchar4* d_output,
const int width, const int height, const int depth,
const int windowSize) {
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
const int z = blockIdx.z * blockDim.z + threadIdx.z;
if (x < width && y < height && z < depth) {
int4 a = make_int4(0, 0, 0, 0);
int count = 0;
for (int dz = -windowSize; dz <= windowSize; dz ++) {
for (int dy = -windowSize; dy <= windowSize; dy ++) {
for (int dx = -windowSize; dx <= windowSize; dx ++) {
const int nx = x + dx;
const int ny = y + dy;
const int nz = z + dz;
if (0 <= nx && nx < width
&& 0 <= ny && ny < height
&& 0 <= nz && nz < depth) {
const long idx = nz * (width*height) + ny * width + nx;
#ifdef READ
add(a, d_input[idx]);
#endif
count++;
}
}
}
}
const long idx = z * (width*height) + y * width + x;
#ifdef WRITE
d_output[idx] = make_uchar4(a.x/count, a.y/count, a.z/count, 255);
#endif
}
}
extern "C" __global__
void smooth3(void) {
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
const int z = blockIdx.z * blockDim.z + threadIdx.z;
}
extern "C" __global__
void smooth2(const uchar4* d_input, uchar4* d_output) {
const int width = 1024;
const int height= 1024;
const int depth = 1;
const int windowSize = 1;
const int x = blockIdx.x * blockDim.x + threadIdx.x;
const int y = blockIdx.y * blockDim.y + threadIdx.y;
const int z = blockIdx.z * blockDim.z + threadIdx.z;
/*
if (x < width && y < height && z < depth) {
int4 a = make_int4(0, 0, 0, 0);
int count = 0;
for (int dz = -windowSize; dz <= windowSize; dz ++) {
for (int dy = -windowSize; dy <= windowSize; dy ++) {
for (int dx = -windowSize; dx <= windowSize; dx ++) {
const int nx = x + dx;
const int ny = y + dy;
const int nz = z + dz;
if (0 <= nx && nx < width
&& 0 <= ny && ny < height
&& 0 <= nz && nz < depth) {
const long idx = nz * (width*height) + ny * width + nx;
#ifdef READ
add(a, d_input[idx]);
#endif
count++;
}
}
}
}
const long idx = z * (width*height) + y * width + x;
#ifdef WRITE
d_output[idx] = make_uchar4(a.x/count, a.y/count, a.z/count, 255);
#endif
}
*/
} | .text
.file "smooth1.hip"
.globl __device_stub__smooth1 # -- Begin function __device_stub__smooth1
.p2align 4, 0x90
.type __device_stub__smooth1,@function
__device_stub__smooth1: # @__device_stub__smooth1
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $smooth1, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size __device_stub__smooth1, .Lfunc_end0-__device_stub__smooth1
.cfi_endproc
# -- End function
.globl __device_stub__smooth3 # -- Begin function __device_stub__smooth3
.p2align 4, 0x90
.type __device_stub__smooth3,@function
__device_stub__smooth3: # @__device_stub__smooth3
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $smooth3, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size __device_stub__smooth3, .Lfunc_end1-__device_stub__smooth3
.cfi_endproc
# -- End function
.globl __device_stub__smooth2 # -- Begin function __device_stub__smooth2
.p2align 4, 0x90
.type __device_stub__smooth2,@function
__device_stub__smooth2: # @__device_stub__smooth2
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $smooth2, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size __device_stub__smooth2, .Lfunc_end2-__device_stub__smooth2
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $smooth1, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $smooth3, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $smooth2, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type smooth1,@object # @smooth1
.section .rodata,"a",@progbits
.globl smooth1
.p2align 3, 0x0
smooth1:
.quad __device_stub__smooth1
.size smooth1, 8
.type smooth3,@object # @smooth3
.globl smooth3
.p2align 3, 0x0
smooth3:
.quad __device_stub__smooth3
.size smooth3, 8
.type smooth2,@object # @smooth2
.globl smooth2
.p2align 3, 0x0
smooth2:
.quad __device_stub__smooth2
.size smooth2, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "smooth1"
.size .L__unnamed_1, 8
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "smooth3"
.size .L__unnamed_2, 8
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "smooth2"
.size .L__unnamed_3, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__smooth1
.addrsig_sym __device_stub__smooth3
.addrsig_sym __device_stub__smooth2
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym smooth1
.addrsig_sym smooth3
.addrsig_sym smooth2
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : smooth2
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : smooth3
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : smooth1
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e680000002100 */
/*0050*/ S2R R4, SR_CTAID.Z ; /* 0x0000000000047919 */
/* 0x000ea80000002700 */
/*0060*/ S2R R7, SR_TID.Z ; /* 0x0000000000077919 */
/* 0x000ea20000002300 */
/*0070*/ IMAD R2, R2, c[0x0][0x4], R5 ; /* 0x0000010002027a24 */
/* 0x001fca00078e0205 */
/*0080*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x174], PT ; /* 0x00005d0002007a0c */
/* 0x000fe20003f06270 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0203 */
/*00a0*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fe20000706670 */
/*00b0*/ IMAD R2, R4, c[0x0][0x8], R7 ; /* 0x0000020004027a24 */
/* 0x004fca00078e0207 */
/*00c0*/ ISETP.GE.OR P0, PT, R2, c[0x0][0x178], P0 ; /* 0x00005e0002007a0c */
/* 0x000fda0000706670 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ IADD3 R0, RZ, -c[0x0][0x17c], RZ ; /* 0x80005f00ff007a10 */
/* 0x000fc80007ffe0ff */
/*00f0*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fda0003f04270 */
/*0100*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected smooth1
.globl smooth1
.p2align 8
.type smooth1,@function
smooth1:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel smooth1
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size smooth1, .Lfunc_end0-smooth1
.section .AMDGPU.csdata,"",@progbits
.text
.protected smooth3
.globl smooth3
.p2align 8
.type smooth3,@function
smooth3:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel smooth3
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size smooth3, .Lfunc_end1-smooth3
.section .AMDGPU.csdata,"",@progbits
.text
.protected smooth2
.globl smooth2
.p2align 8
.type smooth2,@function
smooth2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel smooth2
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size smooth2, .Lfunc_end2-smooth2
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: smooth1
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: smooth1.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: smooth3
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: smooth3.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: smooth2
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: smooth2.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00122922_00000000-6_smooth1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z7smooth1PK6uchar4PS_iiiiPK6uchar4PS_iiii
.type _Z40__device_stub__Z7smooth1PK6uchar4PS_iiiiPK6uchar4PS_iiii, @function
_Z40__device_stub__Z7smooth1PK6uchar4PS_iiiiPK6uchar4PS_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq smooth1(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z40__device_stub__Z7smooth1PK6uchar4PS_iiiiPK6uchar4PS_iiii, .-_Z40__device_stub__Z7smooth1PK6uchar4PS_iiiiPK6uchar4PS_iiii
.globl smooth1
.type smooth1, @function
smooth1:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z7smooth1PK6uchar4PS_iiiiPK6uchar4PS_iiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size smooth1, .-smooth1
.globl _Z25__device_stub__Z7smooth3vv
.type _Z25__device_stub__Z7smooth3vv, @function
_Z25__device_stub__Z7smooth3vv:
.LFB2054:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq smooth3(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z25__device_stub__Z7smooth3vv, .-_Z25__device_stub__Z7smooth3vv
.globl smooth3
.type smooth3, @function
smooth3:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z7smooth3vv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size smooth3, .-smooth3
.globl _Z36__device_stub__Z7smooth2PK6uchar4PS_PK6uchar4PS_
.type _Z36__device_stub__Z7smooth2PK6uchar4PS_PK6uchar4PS_, @function
_Z36__device_stub__Z7smooth2PK6uchar4PS_PK6uchar4PS_:
.LFB2056:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq smooth2(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2056:
.size _Z36__device_stub__Z7smooth2PK6uchar4PS_PK6uchar4PS_, .-_Z36__device_stub__Z7smooth2PK6uchar4PS_PK6uchar4PS_
.globl smooth2
.type smooth2, @function
smooth2:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z7smooth2PK6uchar4PS_PK6uchar4PS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size smooth2, .-smooth2
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "smooth2"
.LC1:
.string "smooth3"
.LC2:
.string "smooth1"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq smooth2(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq smooth3(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq smooth1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "smooth1.hip"
.globl __device_stub__smooth1 # -- Begin function __device_stub__smooth1
.p2align 4, 0x90
.type __device_stub__smooth1,@function
__device_stub__smooth1: # @__device_stub__smooth1
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $smooth1, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size __device_stub__smooth1, .Lfunc_end0-__device_stub__smooth1
.cfi_endproc
# -- End function
.globl __device_stub__smooth3 # -- Begin function __device_stub__smooth3
.p2align 4, 0x90
.type __device_stub__smooth3,@function
__device_stub__smooth3: # @__device_stub__smooth3
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $smooth3, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size __device_stub__smooth3, .Lfunc_end1-__device_stub__smooth3
.cfi_endproc
# -- End function
.globl __device_stub__smooth2 # -- Begin function __device_stub__smooth2
.p2align 4, 0x90
.type __device_stub__smooth2,@function
__device_stub__smooth2: # @__device_stub__smooth2
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $smooth2, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size __device_stub__smooth2, .Lfunc_end2-__device_stub__smooth2
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $smooth1, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $smooth3, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $smooth2, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type smooth1,@object # @smooth1
.section .rodata,"a",@progbits
.globl smooth1
.p2align 3, 0x0
smooth1:
.quad __device_stub__smooth1
.size smooth1, 8
.type smooth3,@object # @smooth3
.globl smooth3
.p2align 3, 0x0
smooth3:
.quad __device_stub__smooth3
.size smooth3, 8
.type smooth2,@object # @smooth2
.globl smooth2
.p2align 3, 0x0
smooth2:
.quad __device_stub__smooth2
.size smooth2, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "smooth1"
.size .L__unnamed_1, 8
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "smooth3"
.size .L__unnamed_2, 8
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "smooth2"
.size .L__unnamed_3, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__smooth1
.addrsig_sym __device_stub__smooth3
.addrsig_sym __device_stub__smooth2
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym smooth1
.addrsig_sym smooth3
.addrsig_sym smooth2
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <algorithm>
#include <assert.h>
#include <iostream>
#include <math.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <sys/time.h>
#include <cuda_runtime.h>
int N = 1024; // length of vector A
float* d_A = NULL; // Pointer to vector A in device memory
double time_memcpy = 0;
double time_compute = 0; // Timers
/////////////////////////////////////////////////////////////////////////
// Matrix-matrix Multiplication on CPU: Policy 1
/////////////////////////////////////////////////////////////////////////
void inc_cpu(float* A, int n, int inc_count) {
for (int i=0; i<n; i++) {
for (int j=0; j<inc_count; j++) {
A[i] += 1;
}
}
}
/////////////////////////////////////////////////////////////////////////
// Matrix-matrix Multiplication on GPU: Policy 2
/////////////////////////////////////////////////////////////////////////
__global__ void inc_gpu(float* A, int n, int inc_count)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
for (int j=0; j<inc_count; j++) {
A[i] += 1;
}
}
/////////////////////////////////////////////////////////////////////////
// Macro to check that CUDA API calls are successful
/////////////////////////////////////////////////////////////////////////
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
/////////////////////////////////////////////////////////////////////////
// Allocate device memory and copy from host to device memory
/////////////////////////////////////////////////////////////////////////
void copy_host_to_device(float* A, int n)
{
double time_start, time_end;
struct timeval tv;
struct timezone tz;
gettimeofday (&tv , &tz);
time_start = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
cudaMalloc((void**) &d_A, sizeof(float) * n * n);
assert(d_A);
cudaMemcpy(d_A, A, sizeof(float) * n, cudaMemcpyHostToDevice);
gettimeofday (&tv , &tz);
time_end = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
time_memcpy += time_end - time_start;
}
/////////////////////////////////////////////////////////////////////////
// Copy result from device to host memory and free device memory
/////////////////////////////////////////////////////////////////////////
void copy_device_to_host(float* A, int n)
{
double time_start, time_end;
struct timeval tv;
struct timezone tz;
gettimeofday (&tv , &tz);
time_start = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
// TODO:
// 1. Copy result array d_C to C using cudaMemcpy.
// 2. Free memory allocated for d_A, d_B, d_C using cudaFree.
cudaMemcpy(A, d_A, sizeof(float) * n, cudaMemcpyDeviceToHost);
cudaFree(d_A);
gettimeofday (&tv , &tz);
time_end = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
time_memcpy += time_end - time_start;
}
/////////////////////////////////////////////////////////////////////////
// Program main
/////////////////////////////////////////////////////////////////////////
int main(int argc, char** argv)
{
double time_start, time_end;
struct timeval tv;
struct timezone tz;
if(argc != 5) {printf("Usage: mat_mul_gpu <array size> <block size> <policy (1|2|3)> <(debug|nodebug)>\n") ; exit(2) ;}
int inc_count = atoi(argv[1]) ; // number of times to increment each element
int block_size = atoi(argv[2]) ; // size of thread block
int policy = atoi(argv[3]) ; // 1 or 2
bool debug = (!strcmp(argv[4], "debug")) ? true : false;
// allocate host memory for vector A
float* h_A = (float*)malloc(sizeof(float) * N);
// initialize host memory with zeros
for (int i = 0; i < N; ++i){
h_A[i] = 0;
}
//call the relevant policy
if(policy==1){ // CPU baseline
gettimeofday (&tv , &tz);
time_start = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
inc_cpu(h_A, N, inc_count);
gettimeofday (&tv , &tz);
time_end = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
time_compute = time_end - time_start;
}
else if(policy==2){ // GPU
copy_host_to_device(h_A, N);
gettimeofday (&tv , &tz);
time_start = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
dim3 dimBlock(block_size);
dim3 dimGrid(N / dimBlock.x);
inc_gpu <<<dimGrid, dimBlock>>> (d_A, N, inc_count);
gpuErrchk( cudaPeekAtLastError() );
gpuErrchk( cudaDeviceSynchronize() );
gettimeofday (&tv , &tz);
time_end = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
time_compute = time_end - time_start;
copy_device_to_host(h_A, N);
}
if (debug) {
// print selected results (for checking correctness)
for (int i=0; i<N; i+=N/10) { printf(" %10.6f",h_A[i]); }
printf("\n");
}
if(!debug) {
printf("Memcpy Time: %f seconds\n", time_memcpy);
printf("Compute Time: %f seconds\n", time_compute);
}
// clean up memory allocated
free(h_A);
cudaDeviceReset();
} | code for sm_80
Function : _Z7inc_gpuPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R4, c[0x0][0x16c] ; /* 0x00005b0000047a02 */
/* 0x000fc80000000f00 */
/*0020*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0060*/ IADD3 R0, R4, -0x1, RZ ; /* 0xffffffff04007810 */
/* 0x000fe20007ffe0ff */
/*0070*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0090*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f06070 */
/*00a0*/ LOP3.LUT R0, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304007812 */
/* 0x000fe200078ec0ff */
/*00b0*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fc800078e0202 */
/*00c0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*00d0*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000162000c1e1900 */
/*00e0*/ @!P0 BRA 0x3e0 ; /* 0x000002f000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R4, -R0, c[0x0][0x16c], RZ ; /* 0x00005b0000047a10 */
/* 0x000fc80007ffe1ff */
/*0100*/ ISETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f04270 */
/*0110*/ @!P0 BRA 0x370 ; /* 0x0000025000008947 */
/* 0x000fea0003800000 */
/*0120*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*0130*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0140*/ @!P1 BRA 0x290 ; /* 0x0000014000009947 */
/* 0x000fea0003800000 */
/*0150*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0160*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x020fe20000000000 */
/*0170*/ IADD3 R4, R4, -0x10, RZ ; /* 0xfffffff004047810 */
/* 0x000fc60007ffe0ff */
/*0180*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fe20000000000 */
/*0190*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fc60003f24270 */
/*01a0*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*01b0*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*01c0*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*01d0*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*01e0*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*01f0*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*0200*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*0210*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*0220*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*0230*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*0240*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*0250*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*0260*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*0270*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fe20000000000 */
/*0280*/ @P1 BRA 0x160 ; /* 0xfffffed000001947 */
/* 0x000fea000383ffff */
/*0290*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*02a0*/ @!P1 BRA 0x350 ; /* 0x000000a000009947 */
/* 0x000fea0003800000 */
/*02b0*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x020fe20000000000 */
/*02c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*02d0*/ IADD3 R4, R4, -0x8, RZ ; /* 0xfffffff804047810 */
/* 0x000fe20007ffe0ff */
/*02e0*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*02f0*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*0300*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*0310*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*0320*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*0330*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*0340*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fe40000000000 */
/*0350*/ ISETP.NE.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0000705670 */
/*0360*/ @!P0 BRA 0x3e0 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*0370*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fe20007ffe0ff */
/*0380*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x020fc60000000000 */
/*0390*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*03a0*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*03b0*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*03c0*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*03d0*/ @P0 BRA 0x370 ; /* 0xffffff9000000947 */
/* 0x001fea000383ffff */
/*03e0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*03f0*/ @!P0 BRA 0x440 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0400*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*0410*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x020fc60000000000 */
/*0420*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0430*/ @P0 BRA 0x400 ; /* 0xffffffc000000947 */
/* 0x000fea000383ffff */
/*0440*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x020fe2000c101904 */
/*0450*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0460*/ BRA 0x460; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <algorithm>
#include <assert.h>
#include <iostream>
#include <math.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <sys/time.h>
#include <cuda_runtime.h>
int N = 1024; // length of vector A
float* d_A = NULL; // Pointer to vector A in device memory
double time_memcpy = 0;
double time_compute = 0; // Timers
/////////////////////////////////////////////////////////////////////////
// Matrix-matrix Multiplication on CPU: Policy 1
/////////////////////////////////////////////////////////////////////////
void inc_cpu(float* A, int n, int inc_count) {
for (int i=0; i<n; i++) {
for (int j=0; j<inc_count; j++) {
A[i] += 1;
}
}
}
/////////////////////////////////////////////////////////////////////////
// Matrix-matrix Multiplication on GPU: Policy 2
/////////////////////////////////////////////////////////////////////////
__global__ void inc_gpu(float* A, int n, int inc_count)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
for (int j=0; j<inc_count; j++) {
A[i] += 1;
}
}
/////////////////////////////////////////////////////////////////////////
// Macro to check that CUDA API calls are successful
/////////////////////////////////////////////////////////////////////////
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
/////////////////////////////////////////////////////////////////////////
// Allocate device memory and copy from host to device memory
/////////////////////////////////////////////////////////////////////////
void copy_host_to_device(float* A, int n)
{
double time_start, time_end;
struct timeval tv;
struct timezone tz;
gettimeofday (&tv , &tz);
time_start = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
cudaMalloc((void**) &d_A, sizeof(float) * n * n);
assert(d_A);
cudaMemcpy(d_A, A, sizeof(float) * n, cudaMemcpyHostToDevice);
gettimeofday (&tv , &tz);
time_end = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
time_memcpy += time_end - time_start;
}
/////////////////////////////////////////////////////////////////////////
// Copy result from device to host memory and free device memory
/////////////////////////////////////////////////////////////////////////
void copy_device_to_host(float* A, int n)
{
double time_start, time_end;
struct timeval tv;
struct timezone tz;
gettimeofday (&tv , &tz);
time_start = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
// TODO:
// 1. Copy result array d_C to C using cudaMemcpy.
// 2. Free memory allocated for d_A, d_B, d_C using cudaFree.
cudaMemcpy(A, d_A, sizeof(float) * n, cudaMemcpyDeviceToHost);
cudaFree(d_A);
gettimeofday (&tv , &tz);
time_end = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
time_memcpy += time_end - time_start;
}
/////////////////////////////////////////////////////////////////////////
// Program main
/////////////////////////////////////////////////////////////////////////
int main(int argc, char** argv)
{
double time_start, time_end;
struct timeval tv;
struct timezone tz;
if(argc != 5) {printf("Usage: mat_mul_gpu <array size> <block size> <policy (1|2|3)> <(debug|nodebug)>\n") ; exit(2) ;}
int inc_count = atoi(argv[1]) ; // number of times to increment each element
int block_size = atoi(argv[2]) ; // size of thread block
int policy = atoi(argv[3]) ; // 1 or 2
bool debug = (!strcmp(argv[4], "debug")) ? true : false;
// allocate host memory for vector A
float* h_A = (float*)malloc(sizeof(float) * N);
// initialize host memory with zeros
for (int i = 0; i < N; ++i){
h_A[i] = 0;
}
//call the relevant policy
if(policy==1){ // CPU baseline
gettimeofday (&tv , &tz);
time_start = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
inc_cpu(h_A, N, inc_count);
gettimeofday (&tv , &tz);
time_end = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
time_compute = time_end - time_start;
}
else if(policy==2){ // GPU
copy_host_to_device(h_A, N);
gettimeofday (&tv , &tz);
time_start = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
dim3 dimBlock(block_size);
dim3 dimGrid(N / dimBlock.x);
inc_gpu <<<dimGrid, dimBlock>>> (d_A, N, inc_count);
gpuErrchk( cudaPeekAtLastError() );
gpuErrchk( cudaDeviceSynchronize() );
gettimeofday (&tv , &tz);
time_end = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
time_compute = time_end - time_start;
copy_device_to_host(h_A, N);
}
if (debug) {
// print selected results (for checking correctness)
for (int i=0; i<N; i+=N/10) { printf(" %10.6f",h_A[i]); }
printf("\n");
}
if(!debug) {
printf("Memcpy Time: %f seconds\n", time_memcpy);
printf("Compute Time: %f seconds\n", time_compute);
}
// clean up memory allocated
free(h_A);
cudaDeviceReset();
} | .file "tmpxft_0012cbf5_00000000-6_vec_inc_gpu.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3930:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3930:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7inc_cpuPfii
.type _Z7inc_cpuPfii, @function
_Z7inc_cpuPfii:
.LFB3923:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L3
movq %rdi, %rcx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rdi
movss .LC0(%rip), %xmm1
jmp .L5
.L7:
movq %rcx, %rsi
movss (%rcx), %xmm0
movl $0, %eax
.L6:
addss %xmm1, %xmm0
addl $1, %eax
cmpl %eax, %edx
jne .L6
movss %xmm0, (%rsi)
.L8:
addq $4, %rcx
cmpq %rdi, %rcx
je .L3
.L5:
testl %edx, %edx
jg .L7
jmp .L8
.L3:
ret
.cfi_endproc
.LFE3923:
.size _Z7inc_cpuPfii, .-_Z7inc_cpuPfii
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC1:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB3924:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L16
ret
.L16:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L17
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE3924:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z19copy_host_to_devicePfi
.type _Z19copy_host_to_devicePfi, @function
_Z19copy_host_to_devicePfi:
.LFB3925:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %rbp
movl %esi, %ebx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %r13
leaq 32(%rsp), %r12
movq %r13, %rsi
movq %r12, %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 40(%rsp), %xmm0
divsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 32(%rsp), %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, 8(%rsp)
movslq %ebx, %rbx
movq %rbx, %rsi
imulq %rbx, %rsi
salq $2, %rsi
leaq d_A(%rip), %rdi
call cudaMalloc@PLT
leaq 0(,%rbx,4), %rdx
movl $1, %ecx
movq %rbp, %rsi
movq d_A(%rip), %rdi
call cudaMemcpy@PLT
movq %r13, %rsi
movq %r12, %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 40(%rsp), %xmm0
divsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 32(%rsp), %xmm1
addsd %xmm1, %xmm0
subsd 8(%rsp), %xmm0
addsd time_memcpy(%rip), %xmm0
movsd %xmm0, time_memcpy(%rip)
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3925:
.size _Z19copy_host_to_devicePfi, .-_Z19copy_host_to_devicePfi
.globl _Z19copy_device_to_hostPfi
.type _Z19copy_device_to_hostPfi, @function
_Z19copy_device_to_hostPfi:
.LFB3926:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %rbp
movl %esi, %ebx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %r13
leaq 32(%rsp), %r12
movq %r13, %rsi
movq %r12, %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 40(%rsp), %xmm0
divsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 32(%rsp), %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, 8(%rsp)
movslq %ebx, %rdx
salq $2, %rdx
movl $2, %ecx
movq d_A(%rip), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq d_A(%rip), %rdi
call cudaFree@PLT
movq %r13, %rsi
movq %r12, %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 40(%rsp), %xmm0
divsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 32(%rsp), %xmm1
addsd %xmm1, %xmm0
subsd 8(%rsp), %xmm0
addsd time_memcpy(%rip), %xmm0
movsd %xmm0, time_memcpy(%rip)
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3926:
.size _Z19copy_device_to_hostPfi, .-_Z19copy_device_to_hostPfi
.globl _Z28__device_stub__Z7inc_gpuPfiiPfii
.type _Z28__device_stub__Z7inc_gpuPfiiPfii, @function
_Z28__device_stub__Z7inc_gpuPfiiPfii:
.LFB3952:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7inc_gpuPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3952:
.size _Z28__device_stub__Z7inc_gpuPfiiPfii, .-_Z28__device_stub__Z7inc_gpuPfiiPfii
.globl _Z7inc_gpuPfii
.type _Z7inc_gpuPfii, @function
_Z7inc_gpuPfii:
.LFB3953:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7inc_gpuPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3953:
.size _Z7inc_gpuPfii, .-_Z7inc_gpuPfii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Usage: mat_mul_gpu <array size> <block size> <policy (1|2|3)> <(debug|nodebug)>\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "debug"
.section .rodata.str1.8
.align 8
.LC6:
.string "/home/ubuntu/Datasets/stackv2/train-structured/Jchuk99/CS1541_Fall2020/master/study_guides/midterm_2_review/vec_inc_gpu.cu"
.section .rodata.str1.1
.LC7:
.string "Memcpy Time: %f seconds\n"
.LC8:
.string "Compute Time: %f seconds\n"
.LC9:
.string " %10.6f"
.LC10:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3927:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
cmpl $5, %edi
jne .L50
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 4(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movq 32(%rbx), %rdi
leaq .LC4(%rip), %rsi
call strcmp@PLT
movl %eax, %ebx
movl N(%rip), %r15d
movslq %r15d, %rbp
salq $2, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
testl %r15d, %r15d
jle .L36
addq %rax, %rbp
.L37:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rbp, %rax
jne .L37
.L36:
cmpl $1, %r13d
je .L51
cmpl $2, %r13d
je .L52
.L39:
testl %ebx, %ebx
jne .L41
leaq .LC9(%rip), %rbp
cmpl $0, N(%rip)
jle .L43
.L42:
movslq %ebx, %rax
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rax,4), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl N(%rip), %edx
movslq %edx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
movl %edx, %ecx
sarl $31, %ecx
subl %ecx, %eax
addl %eax, %ebx
cmpl %ebx, %edx
jg .L42
.L43:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L44:
movq %r12, %rdi
call free@PLT
call cudaDeviceReset@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L53
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $2, %edi
call exit@PLT
.L51:
leaq 16(%rsp), %r13
leaq 48(%rsp), %rbp
movq %r13, %rsi
movq %rbp, %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 56(%rsp), %xmm0
divsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 48(%rsp), %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, 8(%rsp)
movl 4(%rsp), %edx
movl N(%rip), %esi
movq %r12, %rdi
call _Z7inc_cpuPfii
movq %r13, %rsi
movq %rbp, %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 56(%rsp), %xmm0
divsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 48(%rsp), %xmm1
addsd %xmm1, %xmm0
subsd 8(%rsp), %xmm0
movsd %xmm0, time_compute(%rip)
jmp .L39
.L52:
movl %r15d, %esi
movq %r12, %rdi
call _Z19copy_host_to_devicePfi
leaq 16(%rsp), %rsi
leaq 48(%rsp), %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 56(%rsp), %xmm0
divsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 48(%rsp), %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, 8(%rsp)
movl $1, 28(%rsp)
movl N(%rip), %eax
movl $0, %edx
divl %r14d
movl %eax, 36(%rsp)
movl $1, 40(%rsp)
movl %r14d, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L40:
call cudaPeekAtLastError@PLT
movl %eax, %edi
movl $1, %ecx
movl $144, %edx
leaq .LC6(%rip), %rbp
movq %rbp, %rsi
call _Z9gpuAssert9cudaErrorPKcib
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $145, %edx
movq %rbp, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 16(%rsp), %rsi
leaq 48(%rsp), %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 56(%rsp), %xmm0
divsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 48(%rsp), %xmm1
addsd %xmm1, %xmm0
subsd 8(%rsp), %xmm0
movsd %xmm0, time_compute(%rip)
movl N(%rip), %esi
movq %r12, %rdi
call _Z19copy_device_to_hostPfi
jmp .L39
.L54:
movl 4(%rsp), %edx
movl N(%rip), %esi
movq d_A(%rip), %rdi
call _Z28__device_stub__Z7inc_gpuPfiiPfii
jmp .L40
.L41:
movsd time_memcpy(%rip), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd time_compute(%rip), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L44
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3927:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z7inc_gpuPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3955:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z7inc_gpuPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3955:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl time_compute
.bss
.align 8
.type time_compute, @object
.size time_compute, 8
time_compute:
.zero 8
.globl time_memcpy
.align 8
.type time_memcpy, @object
.size time_memcpy, 8
time_memcpy:
.zero 8
.globl d_A
.align 8
.type d_A, @object
.size d_A, 8
d_A:
.zero 8
.globl N
.data
.align 4
.type N, @object
.size N, 4
N:
.long 1024
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <algorithm>
#include <assert.h>
#include <iostream>
#include <math.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <sys/time.h>
#include <cuda_runtime.h>
int N = 1024; // length of vector A
float* d_A = NULL; // Pointer to vector A in device memory
double time_memcpy = 0;
double time_compute = 0; // Timers
/////////////////////////////////////////////////////////////////////////
// Matrix-matrix Multiplication on CPU: Policy 1
/////////////////////////////////////////////////////////////////////////
void inc_cpu(float* A, int n, int inc_count) {
for (int i=0; i<n; i++) {
for (int j=0; j<inc_count; j++) {
A[i] += 1;
}
}
}
/////////////////////////////////////////////////////////////////////////
// Matrix-matrix Multiplication on GPU: Policy 2
/////////////////////////////////////////////////////////////////////////
__global__ void inc_gpu(float* A, int n, int inc_count)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
for (int j=0; j<inc_count; j++) {
A[i] += 1;
}
}
/////////////////////////////////////////////////////////////////////////
// Macro to check that CUDA API calls are successful
/////////////////////////////////////////////////////////////////////////
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
/////////////////////////////////////////////////////////////////////////
// Allocate device memory and copy from host to device memory
/////////////////////////////////////////////////////////////////////////
void copy_host_to_device(float* A, int n)
{
double time_start, time_end;
struct timeval tv;
struct timezone tz;
gettimeofday (&tv , &tz);
time_start = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
cudaMalloc((void**) &d_A, sizeof(float) * n * n);
assert(d_A);
cudaMemcpy(d_A, A, sizeof(float) * n, cudaMemcpyHostToDevice);
gettimeofday (&tv , &tz);
time_end = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
time_memcpy += time_end - time_start;
}
/////////////////////////////////////////////////////////////////////////
// Copy result from device to host memory and free device memory
/////////////////////////////////////////////////////////////////////////
void copy_device_to_host(float* A, int n)
{
double time_start, time_end;
struct timeval tv;
struct timezone tz;
gettimeofday (&tv , &tz);
time_start = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
// TODO:
// 1. Copy result array d_C to C using cudaMemcpy.
// 2. Free memory allocated for d_A, d_B, d_C using cudaFree.
cudaMemcpy(A, d_A, sizeof(float) * n, cudaMemcpyDeviceToHost);
cudaFree(d_A);
gettimeofday (&tv , &tz);
time_end = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
time_memcpy += time_end - time_start;
}
/////////////////////////////////////////////////////////////////////////
// Program main
/////////////////////////////////////////////////////////////////////////
int main(int argc, char** argv)
{
double time_start, time_end;
struct timeval tv;
struct timezone tz;
if(argc != 5) {printf("Usage: mat_mul_gpu <array size> <block size> <policy (1|2|3)> <(debug|nodebug)>\n") ; exit(2) ;}
int inc_count = atoi(argv[1]) ; // number of times to increment each element
int block_size = atoi(argv[2]) ; // size of thread block
int policy = atoi(argv[3]) ; // 1 or 2
bool debug = (!strcmp(argv[4], "debug")) ? true : false;
// allocate host memory for vector A
float* h_A = (float*)malloc(sizeof(float) * N);
// initialize host memory with zeros
for (int i = 0; i < N; ++i){
h_A[i] = 0;
}
//call the relevant policy
if(policy==1){ // CPU baseline
gettimeofday (&tv , &tz);
time_start = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
inc_cpu(h_A, N, inc_count);
gettimeofday (&tv , &tz);
time_end = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
time_compute = time_end - time_start;
}
else if(policy==2){ // GPU
copy_host_to_device(h_A, N);
gettimeofday (&tv , &tz);
time_start = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
dim3 dimBlock(block_size);
dim3 dimGrid(N / dimBlock.x);
inc_gpu <<<dimGrid, dimBlock>>> (d_A, N, inc_count);
gpuErrchk( cudaPeekAtLastError() );
gpuErrchk( cudaDeviceSynchronize() );
gettimeofday (&tv , &tz);
time_end = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
time_compute = time_end - time_start;
copy_device_to_host(h_A, N);
}
if (debug) {
// print selected results (for checking correctness)
for (int i=0; i<N; i+=N/10) { printf(" %10.6f",h_A[i]); }
printf("\n");
}
if(!debug) {
printf("Memcpy Time: %f seconds\n", time_memcpy);
printf("Compute Time: %f seconds\n", time_compute);
}
// clean up memory allocated
free(h_A);
cudaDeviceReset();
} | #include <algorithm>
#include <assert.h>
#include <iostream>
#include <math.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
int N = 1024; // length of vector A
float* d_A = NULL; // Pointer to vector A in device memory
double time_memcpy = 0;
double time_compute = 0; // Timers
/////////////////////////////////////////////////////////////////////////
// Matrix-matrix Multiplication on CPU: Policy 1
/////////////////////////////////////////////////////////////////////////
void inc_cpu(float* A, int n, int inc_count) {
for (int i=0; i<n; i++) {
for (int j=0; j<inc_count; j++) {
A[i] += 1;
}
}
}
/////////////////////////////////////////////////////////////////////////
// Matrix-matrix Multiplication on GPU: Policy 2
/////////////////////////////////////////////////////////////////////////
__global__ void inc_gpu(float* A, int n, int inc_count)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
for (int j=0; j<inc_count; j++) {
A[i] += 1;
}
}
/////////////////////////////////////////////////////////////////////////
// Macro to check that CUDA API calls are successful
/////////////////////////////////////////////////////////////////////////
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
/////////////////////////////////////////////////////////////////////////
// Allocate device memory and copy from host to device memory
/////////////////////////////////////////////////////////////////////////
void copy_host_to_device(float* A, int n)
{
double time_start, time_end;
struct timeval tv;
struct timezone tz;
gettimeofday (&tv , &tz);
time_start = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
hipMalloc((void**) &d_A, sizeof(float) * n * n);
assert(d_A);
hipMemcpy(d_A, A, sizeof(float) * n, hipMemcpyHostToDevice);
gettimeofday (&tv , &tz);
time_end = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
time_memcpy += time_end - time_start;
}
/////////////////////////////////////////////////////////////////////////
// Copy result from device to host memory and free device memory
/////////////////////////////////////////////////////////////////////////
void copy_device_to_host(float* A, int n)
{
double time_start, time_end;
struct timeval tv;
struct timezone tz;
gettimeofday (&tv , &tz);
time_start = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
// TODO:
// 1. Copy result array d_C to C using cudaMemcpy.
// 2. Free memory allocated for d_A, d_B, d_C using cudaFree.
hipMemcpy(A, d_A, sizeof(float) * n, hipMemcpyDeviceToHost);
hipFree(d_A);
gettimeofday (&tv , &tz);
time_end = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
time_memcpy += time_end - time_start;
}
/////////////////////////////////////////////////////////////////////////
// Program main
/////////////////////////////////////////////////////////////////////////
int main(int argc, char** argv)
{
double time_start, time_end;
struct timeval tv;
struct timezone tz;
if(argc != 5) {printf("Usage: mat_mul_gpu <array size> <block size> <policy (1|2|3)> <(debug|nodebug)>\n") ; exit(2) ;}
int inc_count = atoi(argv[1]) ; // number of times to increment each element
int block_size = atoi(argv[2]) ; // size of thread block
int policy = atoi(argv[3]) ; // 1 or 2
bool debug = (!strcmp(argv[4], "debug")) ? true : false;
// allocate host memory for vector A
float* h_A = (float*)malloc(sizeof(float) * N);
// initialize host memory with zeros
for (int i = 0; i < N; ++i){
h_A[i] = 0;
}
//call the relevant policy
if(policy==1){ // CPU baseline
gettimeofday (&tv , &tz);
time_start = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
inc_cpu(h_A, N, inc_count);
gettimeofday (&tv , &tz);
time_end = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
time_compute = time_end - time_start;
}
else if(policy==2){ // GPU
copy_host_to_device(h_A, N);
gettimeofday (&tv , &tz);
time_start = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
dim3 dimBlock(block_size);
dim3 dimGrid(N / dimBlock.x);
inc_gpu <<<dimGrid, dimBlock>>> (d_A, N, inc_count);
gpuErrchk( hipPeekAtLastError() );
gpuErrchk( hipDeviceSynchronize() );
gettimeofday (&tv , &tz);
time_end = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
time_compute = time_end - time_start;
copy_device_to_host(h_A, N);
}
if (debug) {
// print selected results (for checking correctness)
for (int i=0; i<N; i+=N/10) { printf(" %10.6f",h_A[i]); }
printf("\n");
}
if(!debug) {
printf("Memcpy Time: %f seconds\n", time_memcpy);
printf("Compute Time: %f seconds\n", time_compute);
}
// clean up memory allocated
free(h_A);
hipDeviceReset();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <algorithm>
#include <assert.h>
#include <iostream>
#include <math.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
int N = 1024; // length of vector A
float* d_A = NULL; // Pointer to vector A in device memory
double time_memcpy = 0;
double time_compute = 0; // Timers
/////////////////////////////////////////////////////////////////////////
// Matrix-matrix Multiplication on CPU: Policy 1
/////////////////////////////////////////////////////////////////////////
void inc_cpu(float* A, int n, int inc_count) {
for (int i=0; i<n; i++) {
for (int j=0; j<inc_count; j++) {
A[i] += 1;
}
}
}
/////////////////////////////////////////////////////////////////////////
// Matrix-matrix Multiplication on GPU: Policy 2
/////////////////////////////////////////////////////////////////////////
__global__ void inc_gpu(float* A, int n, int inc_count)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
for (int j=0; j<inc_count; j++) {
A[i] += 1;
}
}
/////////////////////////////////////////////////////////////////////////
// Macro to check that CUDA API calls are successful
/////////////////////////////////////////////////////////////////////////
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
/////////////////////////////////////////////////////////////////////////
// Allocate device memory and copy from host to device memory
/////////////////////////////////////////////////////////////////////////
void copy_host_to_device(float* A, int n)
{
double time_start, time_end;
struct timeval tv;
struct timezone tz;
gettimeofday (&tv , &tz);
time_start = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
hipMalloc((void**) &d_A, sizeof(float) * n * n);
assert(d_A);
hipMemcpy(d_A, A, sizeof(float) * n, hipMemcpyHostToDevice);
gettimeofday (&tv , &tz);
time_end = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
time_memcpy += time_end - time_start;
}
/////////////////////////////////////////////////////////////////////////
// Copy result from device to host memory and free device memory
/////////////////////////////////////////////////////////////////////////
void copy_device_to_host(float* A, int n)
{
double time_start, time_end;
struct timeval tv;
struct timezone tz;
gettimeofday (&tv , &tz);
time_start = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
// TODO:
// 1. Copy result array d_C to C using cudaMemcpy.
// 2. Free memory allocated for d_A, d_B, d_C using cudaFree.
hipMemcpy(A, d_A, sizeof(float) * n, hipMemcpyDeviceToHost);
hipFree(d_A);
gettimeofday (&tv , &tz);
time_end = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
time_memcpy += time_end - time_start;
}
/////////////////////////////////////////////////////////////////////////
// Program main
/////////////////////////////////////////////////////////////////////////
int main(int argc, char** argv)
{
double time_start, time_end;
struct timeval tv;
struct timezone tz;
if(argc != 5) {printf("Usage: mat_mul_gpu <array size> <block size> <policy (1|2|3)> <(debug|nodebug)>\n") ; exit(2) ;}
int inc_count = atoi(argv[1]) ; // number of times to increment each element
int block_size = atoi(argv[2]) ; // size of thread block
int policy = atoi(argv[3]) ; // 1 or 2
bool debug = (!strcmp(argv[4], "debug")) ? true : false;
// allocate host memory for vector A
float* h_A = (float*)malloc(sizeof(float) * N);
// initialize host memory with zeros
for (int i = 0; i < N; ++i){
h_A[i] = 0;
}
//call the relevant policy
if(policy==1){ // CPU baseline
gettimeofday (&tv , &tz);
time_start = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
inc_cpu(h_A, N, inc_count);
gettimeofday (&tv , &tz);
time_end = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
time_compute = time_end - time_start;
}
else if(policy==2){ // GPU
copy_host_to_device(h_A, N);
gettimeofday (&tv , &tz);
time_start = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
dim3 dimBlock(block_size);
dim3 dimGrid(N / dimBlock.x);
inc_gpu <<<dimGrid, dimBlock>>> (d_A, N, inc_count);
gpuErrchk( hipPeekAtLastError() );
gpuErrchk( hipDeviceSynchronize() );
gettimeofday (&tv , &tz);
time_end = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
time_compute = time_end - time_start;
copy_device_to_host(h_A, N);
}
if (debug) {
// print selected results (for checking correctness)
for (int i=0; i<N; i+=N/10) { printf(" %10.6f",h_A[i]); }
printf("\n");
}
if(!debug) {
printf("Memcpy Time: %f seconds\n", time_memcpy);
printf("Compute Time: %f seconds\n", time_compute);
}
// clean up memory allocated
free(h_A);
hipDeviceReset();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7inc_gpuPfii
.globl _Z7inc_gpuPfii
.p2align 8
.type _Z7inc_gpuPfii,@function
_Z7inc_gpuPfii:
s_load_b32 s2, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
.LBB0_2:
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, 1.0, v2
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 0
s_cbranch_scc0 .LBB0_2
global_store_b32 v[0:1], v2, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7inc_gpuPfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7inc_gpuPfii, .Lfunc_end0-_Z7inc_gpuPfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7inc_gpuPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7inc_gpuPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <algorithm>
#include <assert.h>
#include <iostream>
#include <math.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
int N = 1024; // length of vector A
float* d_A = NULL; // Pointer to vector A in device memory
double time_memcpy = 0;
double time_compute = 0; // Timers
/////////////////////////////////////////////////////////////////////////
// Matrix-matrix Multiplication on CPU: Policy 1
/////////////////////////////////////////////////////////////////////////
void inc_cpu(float* A, int n, int inc_count) {
for (int i=0; i<n; i++) {
for (int j=0; j<inc_count; j++) {
A[i] += 1;
}
}
}
/////////////////////////////////////////////////////////////////////////
// Matrix-matrix Multiplication on GPU: Policy 2
/////////////////////////////////////////////////////////////////////////
__global__ void inc_gpu(float* A, int n, int inc_count)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
for (int j=0; j<inc_count; j++) {
A[i] += 1;
}
}
/////////////////////////////////////////////////////////////////////////
// Macro to check that CUDA API calls are successful
/////////////////////////////////////////////////////////////////////////
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
/////////////////////////////////////////////////////////////////////////
// Allocate device memory and copy from host to device memory
/////////////////////////////////////////////////////////////////////////
void copy_host_to_device(float* A, int n)
{
double time_start, time_end;
struct timeval tv;
struct timezone tz;
gettimeofday (&tv , &tz);
time_start = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
hipMalloc((void**) &d_A, sizeof(float) * n * n);
assert(d_A);
hipMemcpy(d_A, A, sizeof(float) * n, hipMemcpyHostToDevice);
gettimeofday (&tv , &tz);
time_end = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
time_memcpy += time_end - time_start;
}
/////////////////////////////////////////////////////////////////////////
// Copy result from device to host memory and free device memory
/////////////////////////////////////////////////////////////////////////
void copy_device_to_host(float* A, int n)
{
double time_start, time_end;
struct timeval tv;
struct timezone tz;
gettimeofday (&tv , &tz);
time_start = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
// TODO:
// 1. Copy result array d_C to C using cudaMemcpy.
// 2. Free memory allocated for d_A, d_B, d_C using cudaFree.
hipMemcpy(A, d_A, sizeof(float) * n, hipMemcpyDeviceToHost);
hipFree(d_A);
gettimeofday (&tv , &tz);
time_end = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
time_memcpy += time_end - time_start;
}
/////////////////////////////////////////////////////////////////////////
// Program main
/////////////////////////////////////////////////////////////////////////
int main(int argc, char** argv)
{
double time_start, time_end;
struct timeval tv;
struct timezone tz;
if(argc != 5) {printf("Usage: mat_mul_gpu <array size> <block size> <policy (1|2|3)> <(debug|nodebug)>\n") ; exit(2) ;}
int inc_count = atoi(argv[1]) ; // number of times to increment each element
int block_size = atoi(argv[2]) ; // size of thread block
int policy = atoi(argv[3]) ; // 1 or 2
bool debug = (!strcmp(argv[4], "debug")) ? true : false;
// allocate host memory for vector A
float* h_A = (float*)malloc(sizeof(float) * N);
// initialize host memory with zeros
for (int i = 0; i < N; ++i){
h_A[i] = 0;
}
//call the relevant policy
if(policy==1){ // CPU baseline
gettimeofday (&tv , &tz);
time_start = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
inc_cpu(h_A, N, inc_count);
gettimeofday (&tv , &tz);
time_end = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
time_compute = time_end - time_start;
}
else if(policy==2){ // GPU
copy_host_to_device(h_A, N);
gettimeofday (&tv , &tz);
time_start = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
dim3 dimBlock(block_size);
dim3 dimGrid(N / dimBlock.x);
inc_gpu <<<dimGrid, dimBlock>>> (d_A, N, inc_count);
gpuErrchk( hipPeekAtLastError() );
gpuErrchk( hipDeviceSynchronize() );
gettimeofday (&tv , &tz);
time_end = (double)tv.tv_sec + (double)tv.tv_usec / 1000000.0;
time_compute = time_end - time_start;
copy_device_to_host(h_A, N);
}
if (debug) {
// print selected results (for checking correctness)
for (int i=0; i<N; i+=N/10) { printf(" %10.6f",h_A[i]); }
printf("\n");
}
if(!debug) {
printf("Memcpy Time: %f seconds\n", time_memcpy);
printf("Compute Time: %f seconds\n", time_compute);
}
// clean up memory allocated
free(h_A);
hipDeviceReset();
} | .text
.file "vec_inc_gpu.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z7inc_cpuPfii
.LCPI0_0:
.long 0x3f800000 # float 1
.text
.globl _Z7inc_cpuPfii
.p2align 4, 0x90
.type _Z7inc_cpuPfii,@function
_Z7inc_cpuPfii: # @_Z7inc_cpuPfii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_7
# %bb.1: # %.preheader.lr.ph
movl %esi, %eax
xorl %ecx, %ecx
movss .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_6: # in Loop: Header=BB0_2 Depth=1
incq %rcx
cmpq %rax, %rcx
je .LBB0_7
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
testl %edx, %edx
jle .LBB0_6
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movss (%rdi,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movl %edx, %esi
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
addss %xmm0, %xmm1
decl %esi
jne .LBB0_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
movss %xmm1, (%rdi,%rcx,4)
jmp .LBB0_6
.LBB0_7: # %._crit_edge10
retq
.Lfunc_end0:
.size _Z7inc_cpuPfii, .Lfunc_end0-_Z7inc_cpuPfii
.cfi_endproc
# -- End function
.globl _Z22__device_stub__inc_gpuPfii # -- Begin function _Z22__device_stub__inc_gpuPfii
.p2align 4, 0x90
.type _Z22__device_stub__inc_gpuPfii,@function
_Z22__device_stub__inc_gpuPfii: # @_Z22__device_stub__inc_gpuPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7inc_gpuPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z22__device_stub__inc_gpuPfii, .Lfunc_end1-_Z22__device_stub__inc_gpuPfii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z19copy_host_to_devicePfi
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z19copy_host_to_devicePfi
.p2align 4, 0x90
.type _Z19copy_host_to_devicePfi,@function
_Z19copy_host_to_devicePfi: # @_Z19copy_host_to_devicePfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %r15
movq %rsp, %rbx
leaq 24(%rsp), %r14
movq %rbx, %rdi
movq %r14, %rsi
callq gettimeofday
cvtsi2sdq (%rsp), %xmm0
cvtsi2sdq 8(%rsp), %xmm1
divsd .LCPI2_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 16(%rsp) # 8-byte Spill
movslq %ebp, %rsi
leaq (,%rsi,4), %r12
imulq %r12, %rsi
movl $d_A, %edi
callq hipMalloc
movq d_A(%rip), %rdi
movq %r15, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq %rbx, %rdi
movq %r14, %rsi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq (%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 8(%rsp), %xmm1
divsd .LCPI2_0(%rip), %xmm1
addsd %xmm0, %xmm1
subsd 16(%rsp), %xmm1 # 8-byte Folded Reload
addsd time_memcpy(%rip), %xmm1
movsd %xmm1, time_memcpy(%rip)
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z19copy_host_to_devicePfi, .Lfunc_end2-_Z19copy_host_to_devicePfi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z19copy_device_to_hostPfi
.LCPI3_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z19copy_device_to_hostPfi
.p2align 4, 0x90
.type _Z19copy_device_to_hostPfi,@function
_Z19copy_device_to_hostPfi: # @_Z19copy_device_to_hostPfi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $40, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %ebx
movq %rdi, %r14
leaq 8(%rsp), %r15
leaq 32(%rsp), %r12
movq %r15, %rdi
movq %r12, %rsi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm0
cvtsi2sdq 16(%rsp), %xmm1
divsd .LCPI3_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 24(%rsp) # 8-byte Spill
movq d_A(%rip), %rsi
movslq %ebx, %rdx
shlq $2, %rdx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq d_A(%rip), %rdi
callq hipFree
movq %r15, %rdi
movq %r12, %rsi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
divsd .LCPI3_0(%rip), %xmm1
addsd %xmm0, %xmm1
subsd 24(%rsp), %xmm1 # 8-byte Folded Reload
addsd time_memcpy(%rip), %xmm1
movsd %xmm1, time_memcpy(%rip)
addq $40, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z19copy_device_to_hostPfi, .Lfunc_end3-_Z19copy_device_to_hostPfi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x412e848000000000 # double 1.0E+6
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI4_1:
.long 0x3f800000 # float 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $5, %edi
jne .LBB4_28
# %bb.1:
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
movq 32(%rbx), %rdi
movl $.L.str.1, %esi
callq strcmp
movl %eax, 28(%rsp) # 4-byte Spill
movslq N(%rip), %r13
leaq (,%r13,4), %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
testq %r13, %r13
jle .LBB4_3
# %bb.2: # %.lr.ph.preheader
movl %r13d, %edx
shlq $2, %rdx
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
.LBB4_3: # %._crit_edge
cmpl $2, %ebp
je .LBB4_13
# %bb.4: # %._crit_edge
cmpl $1, %ebp
movl 28(%rsp), %ebp # 4-byte Reload
jne .LBB4_21
# %bb.5:
leaq 8(%rsp), %rdi
leaq 56(%rsp), %rsi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm0
cvtsi2sdq 16(%rsp), %xmm1
divsd .LCPI4_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
movl N(%rip), %eax
testl %eax, %eax
jle .LBB4_12
# %bb.6: # %.preheader.lr.ph.i
xorl %ecx, %ecx
movss .LCPI4_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
jmp .LBB4_7
.p2align 4, 0x90
.LBB4_11: # in Loop: Header=BB4_7 Depth=1
incq %rcx
cmpq %rax, %rcx
je .LBB4_12
.LBB4_7: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_9 Depth 2
testl %r14d, %r14d
jle .LBB4_11
# %bb.8: # %.lr.ph.i
# in Loop: Header=BB4_7 Depth=1
movss (%rbx,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movl %r14d, %edx
.p2align 4, 0x90
.LBB4_9: # Parent Loop BB4_7 Depth=1
# => This Inner Loop Header: Depth=2
addss %xmm0, %xmm1
decl %edx
jne .LBB4_9
# %bb.10: # %._crit_edge.i
# in Loop: Header=BB4_7 Depth=1
movss %xmm1, (%rbx,%rcx,4)
jmp .LBB4_11
.LBB4_12: # %_Z7inc_cpuPfii.exit
leaq 8(%rsp), %rdi
leaq 56(%rsp), %rsi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
divsd .LCPI4_0(%rip), %xmm1
addsd %xmm0, %xmm1
subsd (%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, time_compute(%rip)
.LBB4_21:
testl %ebp, %ebp
jne .LBB4_26
jmp .LBB4_22
.LBB4_13:
leaq 32(%rsp), %rbp
leaq 8(%rsp), %rsi
movq %rbp, %rdi
callq gettimeofday
cvtsi2sdq 32(%rsp), %xmm0
cvtsi2sdq 40(%rsp), %xmm1
divsd .LCPI4_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
imulq %r12, %r13
movl $d_A, %edi
movq %r13, %rsi
callq hipMalloc
movq d_A(%rip), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq %rbp, %rdi
leaq 8(%rsp), %rsi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 32(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 40(%rsp), %xmm1
divsd .LCPI4_0(%rip), %xmm1
addsd %xmm0, %xmm1
subsd (%rsp), %xmm1 # 8-byte Folded Reload
addsd time_memcpy(%rip), %xmm1
movsd %xmm1, time_memcpy(%rip)
leaq 8(%rsp), %rdi
leaq 56(%rsp), %rsi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
movsd %xmm0, 88(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
movl %r15d, %ecx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rcx
movl N(%rip), %eax
xorl %edx, %edx
divl %r15d
# kill: def $eax killed $eax def $rax
orq %rax, %rdi
movl $1, %esi
movq %rcx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_15
# %bb.14:
movq d_A(%rip), %rax
movl N(%rip), %ecx
movq %rax, 128(%rsp)
movl %ecx, 68(%rsp)
movl %r14d, 64(%rsp)
leaq 128(%rsp), %rax
movq %rax, 32(%rsp)
leaq 68(%rsp), %rax
movq %rax, 40(%rsp)
leaq 64(%rsp), %rax
movq %rax, 48(%rsp)
leaq 72(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z7inc_gpuPfii, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_15:
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB4_16
# %bb.18: # %_Z9gpuAssert10hipError_tPKcib.exit
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB4_19
# %bb.20: # %_Z9gpuAssert10hipError_tPKcib.exit40
movsd .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd (%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
divsd %xmm0, %xmm1
addsd 88(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, (%rsp) # 8-byte Spill
leaq 8(%rsp), %rdi
leaq 56(%rsp), %rsi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
divsd .LCPI4_0(%rip), %xmm1
addsd %xmm0, %xmm1
subsd (%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, time_compute(%rip)
movslq N(%rip), %r14
leaq 32(%rsp), %r15
leaq 72(%rsp), %r12
movq %r15, %rdi
movq %r12, %rsi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 32(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 40(%rsp), %xmm1
divsd .LCPI4_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
movq d_A(%rip), %rsi
shlq $2, %r14
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq d_A(%rip), %rdi
callq hipFree
movq %r15, %rdi
movq %r12, %rsi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 32(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 40(%rsp), %xmm1
divsd .LCPI4_0(%rip), %xmm1
addsd %xmm0, %xmm1
subsd (%rsp), %xmm1 # 8-byte Folded Reload
addsd time_memcpy(%rip), %xmm1
movsd %xmm1, time_memcpy(%rip)
movl 28(%rsp), %ebp # 4-byte Reload
testl %ebp, %ebp
jne .LBB4_26
.LBB4_22: # %.preheader
cmpl $0, N(%rip)
jle .LBB4_25
# %bb.23: # %.lr.ph45.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_24: # %.lr.ph45
# =>This Inner Loop Header: Depth=1
movslq %r14d, %r14
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movslq N(%rip), %rax
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %r14d
cmpl %eax, %r14d
jl .LBB4_24
.LBB4_25: # %._crit_edge46
movl $10, %edi
callq putchar@PLT
testl %ebp, %ebp
je .LBB4_27
.LBB4_26: # %.critedge
movsd time_memcpy(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.5, %edi
movb $1, %al
callq printf
movsd time_compute(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.6, %edi
movb $1, %al
callq printf
.LBB4_27:
movq %rbx, %rdi
callq free
callq hipDeviceReset
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_28:
.cfi_def_cfa_offset 192
movl $.Lstr, %edi
callq puts@PLT
movl $2, %edi
callq exit
.LBB4_16:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $144, %r8d
jmp .LBB4_17
.LBB4_19:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $145, %r8d
.LBB4_17:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7inc_gpuPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type N,@object # @N
.data
.globl N
.p2align 2, 0x0
N:
.long 1024 # 0x400
.size N, 4
.type d_A,@object # @d_A
.bss
.globl d_A
.p2align 3, 0x0
d_A:
.quad 0
.size d_A, 8
.type time_memcpy,@object # @time_memcpy
.globl time_memcpy
.p2align 3, 0x0
time_memcpy:
.quad 0x0000000000000000 # double 0
.size time_memcpy, 8
.type time_compute,@object # @time_compute
.globl time_compute
.p2align 3, 0x0
time_compute:
.quad 0x0000000000000000 # double 0
.size time_compute, 8
.type _Z7inc_gpuPfii,@object # @_Z7inc_gpuPfii
.section .rodata,"a",@progbits
.globl _Z7inc_gpuPfii
.p2align 3, 0x0
_Z7inc_gpuPfii:
.quad _Z22__device_stub__inc_gpuPfii
.size _Z7inc_gpuPfii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "debug"
.size .L.str.1, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/Jchuk99/CS1541_Fall2020/master/study_guides/midterm_2_review/vec_inc_gpu.hip"
.size .L.str.2, 134
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " %10.6f"
.size .L.str.3, 8
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Memcpy Time: %f seconds\n"
.size .L.str.5, 25
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Compute Time: %f seconds\n"
.size .L.str.6, 26
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.7, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7inc_gpuPfii"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Usage: mat_mul_gpu <array size> <block size> <policy (1|2|3)> <(debug|nodebug)>"
.size .Lstr, 80
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__inc_gpuPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_A
.addrsig_sym _Z7inc_gpuPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7inc_gpuPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R4, c[0x0][0x16c] ; /* 0x00005b0000047a02 */
/* 0x000fc80000000f00 */
/*0020*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0060*/ IADD3 R0, R4, -0x1, RZ ; /* 0xffffffff04007810 */
/* 0x000fe20007ffe0ff */
/*0070*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0090*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f06070 */
/*00a0*/ LOP3.LUT R0, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304007812 */
/* 0x000fe200078ec0ff */
/*00b0*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fc800078e0202 */
/*00c0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*00d0*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000162000c1e1900 */
/*00e0*/ @!P0 BRA 0x3e0 ; /* 0x000002f000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R4, -R0, c[0x0][0x16c], RZ ; /* 0x00005b0000047a10 */
/* 0x000fc80007ffe1ff */
/*0100*/ ISETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f04270 */
/*0110*/ @!P0 BRA 0x370 ; /* 0x0000025000008947 */
/* 0x000fea0003800000 */
/*0120*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*0130*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0140*/ @!P1 BRA 0x290 ; /* 0x0000014000009947 */
/* 0x000fea0003800000 */
/*0150*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0160*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x020fe20000000000 */
/*0170*/ IADD3 R4, R4, -0x10, RZ ; /* 0xfffffff004047810 */
/* 0x000fc60007ffe0ff */
/*0180*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fe20000000000 */
/*0190*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fc60003f24270 */
/*01a0*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*01b0*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*01c0*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*01d0*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*01e0*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*01f0*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*0200*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*0210*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*0220*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*0230*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*0240*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*0250*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*0260*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*0270*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fe20000000000 */
/*0280*/ @P1 BRA 0x160 ; /* 0xfffffed000001947 */
/* 0x000fea000383ffff */
/*0290*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*02a0*/ @!P1 BRA 0x350 ; /* 0x000000a000009947 */
/* 0x000fea0003800000 */
/*02b0*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x020fe20000000000 */
/*02c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*02d0*/ IADD3 R4, R4, -0x8, RZ ; /* 0xfffffff804047810 */
/* 0x000fe20007ffe0ff */
/*02e0*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*02f0*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*0300*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*0310*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*0320*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*0330*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*0340*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fe40000000000 */
/*0350*/ ISETP.NE.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0000705670 */
/*0360*/ @!P0 BRA 0x3e0 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*0370*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fe20007ffe0ff */
/*0380*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x020fc60000000000 */
/*0390*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*03a0*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*03b0*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*03c0*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x000fc80000000000 */
/*03d0*/ @P0 BRA 0x370 ; /* 0xffffff9000000947 */
/* 0x001fea000383ffff */
/*03e0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*03f0*/ @!P0 BRA 0x440 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0400*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*0410*/ FADD R5, R5, 1 ; /* 0x3f80000005057421 */
/* 0x020fc60000000000 */
/*0420*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0430*/ @P0 BRA 0x400 ; /* 0xffffffc000000947 */
/* 0x000fea000383ffff */
/*0440*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x020fe2000c101904 */
/*0450*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0460*/ BRA 0x460; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7inc_gpuPfii
.globl _Z7inc_gpuPfii
.p2align 8
.type _Z7inc_gpuPfii,@function
_Z7inc_gpuPfii:
s_load_b32 s2, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
.LBB0_2:
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, 1.0, v2
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 0
s_cbranch_scc0 .LBB0_2
global_store_b32 v[0:1], v2, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7inc_gpuPfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7inc_gpuPfii, .Lfunc_end0-_Z7inc_gpuPfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7inc_gpuPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7inc_gpuPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012cbf5_00000000-6_vec_inc_gpu.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3930:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3930:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7inc_cpuPfii
.type _Z7inc_cpuPfii, @function
_Z7inc_cpuPfii:
.LFB3923:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L3
movq %rdi, %rcx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rdi
movss .LC0(%rip), %xmm1
jmp .L5
.L7:
movq %rcx, %rsi
movss (%rcx), %xmm0
movl $0, %eax
.L6:
addss %xmm1, %xmm0
addl $1, %eax
cmpl %eax, %edx
jne .L6
movss %xmm0, (%rsi)
.L8:
addq $4, %rcx
cmpq %rdi, %rcx
je .L3
.L5:
testl %edx, %edx
jg .L7
jmp .L8
.L3:
ret
.cfi_endproc
.LFE3923:
.size _Z7inc_cpuPfii, .-_Z7inc_cpuPfii
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC1:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB3924:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L16
ret
.L16:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L17
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE3924:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z19copy_host_to_devicePfi
.type _Z19copy_host_to_devicePfi, @function
_Z19copy_host_to_devicePfi:
.LFB3925:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %rbp
movl %esi, %ebx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %r13
leaq 32(%rsp), %r12
movq %r13, %rsi
movq %r12, %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 40(%rsp), %xmm0
divsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 32(%rsp), %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, 8(%rsp)
movslq %ebx, %rbx
movq %rbx, %rsi
imulq %rbx, %rsi
salq $2, %rsi
leaq d_A(%rip), %rdi
call cudaMalloc@PLT
leaq 0(,%rbx,4), %rdx
movl $1, %ecx
movq %rbp, %rsi
movq d_A(%rip), %rdi
call cudaMemcpy@PLT
movq %r13, %rsi
movq %r12, %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 40(%rsp), %xmm0
divsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 32(%rsp), %xmm1
addsd %xmm1, %xmm0
subsd 8(%rsp), %xmm0
addsd time_memcpy(%rip), %xmm0
movsd %xmm0, time_memcpy(%rip)
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L21
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3925:
.size _Z19copy_host_to_devicePfi, .-_Z19copy_host_to_devicePfi
.globl _Z19copy_device_to_hostPfi
.type _Z19copy_device_to_hostPfi, @function
_Z19copy_device_to_hostPfi:
.LFB3926:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %rbp
movl %esi, %ebx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %r13
leaq 32(%rsp), %r12
movq %r13, %rsi
movq %r12, %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 40(%rsp), %xmm0
divsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 32(%rsp), %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, 8(%rsp)
movslq %ebx, %rdx
salq $2, %rdx
movl $2, %ecx
movq d_A(%rip), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq d_A(%rip), %rdi
call cudaFree@PLT
movq %r13, %rsi
movq %r12, %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 40(%rsp), %xmm0
divsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 32(%rsp), %xmm1
addsd %xmm1, %xmm0
subsd 8(%rsp), %xmm0
addsd time_memcpy(%rip), %xmm0
movsd %xmm0, time_memcpy(%rip)
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3926:
.size _Z19copy_device_to_hostPfi, .-_Z19copy_device_to_hostPfi
.globl _Z28__device_stub__Z7inc_gpuPfiiPfii
.type _Z28__device_stub__Z7inc_gpuPfiiPfii, @function
_Z28__device_stub__Z7inc_gpuPfiiPfii:
.LFB3952:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7inc_gpuPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3952:
.size _Z28__device_stub__Z7inc_gpuPfiiPfii, .-_Z28__device_stub__Z7inc_gpuPfiiPfii
.globl _Z7inc_gpuPfii
.type _Z7inc_gpuPfii, @function
_Z7inc_gpuPfii:
.LFB3953:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7inc_gpuPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3953:
.size _Z7inc_gpuPfii, .-_Z7inc_gpuPfii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Usage: mat_mul_gpu <array size> <block size> <policy (1|2|3)> <(debug|nodebug)>\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "debug"
.section .rodata.str1.8
.align 8
.LC6:
.string "/home/ubuntu/Datasets/stackv2/train-structured/Jchuk99/CS1541_Fall2020/master/study_guides/midterm_2_review/vec_inc_gpu.cu"
.section .rodata.str1.1
.LC7:
.string "Memcpy Time: %f seconds\n"
.LC8:
.string "Compute Time: %f seconds\n"
.LC9:
.string " %10.6f"
.LC10:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB3927:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
cmpl $5, %edi
jne .L50
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 4(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movq 32(%rbx), %rdi
leaq .LC4(%rip), %rsi
call strcmp@PLT
movl %eax, %ebx
movl N(%rip), %r15d
movslq %r15d, %rbp
salq $2, %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r12
testl %r15d, %r15d
jle .L36
addq %rax, %rbp
.L37:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rbp, %rax
jne .L37
.L36:
cmpl $1, %r13d
je .L51
cmpl $2, %r13d
je .L52
.L39:
testl %ebx, %ebx
jne .L41
leaq .LC9(%rip), %rbp
cmpl $0, N(%rip)
jle .L43
.L42:
movslq %ebx, %rax
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rax,4), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl N(%rip), %edx
movslq %edx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
movl %edx, %ecx
sarl $31, %ecx
subl %ecx, %eax
addl %eax, %ebx
cmpl %ebx, %edx
jg .L42
.L43:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L44:
movq %r12, %rdi
call free@PLT
call cudaDeviceReset@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L53
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $2, %edi
call exit@PLT
.L51:
leaq 16(%rsp), %r13
leaq 48(%rsp), %rbp
movq %r13, %rsi
movq %rbp, %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 56(%rsp), %xmm0
divsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 48(%rsp), %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, 8(%rsp)
movl 4(%rsp), %edx
movl N(%rip), %esi
movq %r12, %rdi
call _Z7inc_cpuPfii
movq %r13, %rsi
movq %rbp, %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 56(%rsp), %xmm0
divsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 48(%rsp), %xmm1
addsd %xmm1, %xmm0
subsd 8(%rsp), %xmm0
movsd %xmm0, time_compute(%rip)
jmp .L39
.L52:
movl %r15d, %esi
movq %r12, %rdi
call _Z19copy_host_to_devicePfi
leaq 16(%rsp), %rsi
leaq 48(%rsp), %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 56(%rsp), %xmm0
divsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 48(%rsp), %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, 8(%rsp)
movl $1, 28(%rsp)
movl N(%rip), %eax
movl $0, %edx
divl %r14d
movl %eax, 36(%rsp)
movl $1, 40(%rsp)
movl %r14d, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L40:
call cudaPeekAtLastError@PLT
movl %eax, %edi
movl $1, %ecx
movl $144, %edx
leaq .LC6(%rip), %rbp
movq %rbp, %rsi
call _Z9gpuAssert9cudaErrorPKcib
call cudaDeviceSynchronize@PLT
movl %eax, %edi
movl $1, %ecx
movl $145, %edx
movq %rbp, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 16(%rsp), %rsi
leaq 48(%rsp), %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 56(%rsp), %xmm0
divsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 48(%rsp), %xmm1
addsd %xmm1, %xmm0
subsd 8(%rsp), %xmm0
movsd %xmm0, time_compute(%rip)
movl N(%rip), %esi
movq %r12, %rdi
call _Z19copy_device_to_hostPfi
jmp .L39
.L54:
movl 4(%rsp), %edx
movl N(%rip), %esi
movq d_A(%rip), %rdi
call _Z28__device_stub__Z7inc_gpuPfiiPfii
jmp .L40
.L41:
movsd time_memcpy(%rip), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd time_compute(%rip), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
jmp .L44
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3927:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z7inc_gpuPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3955:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z7inc_gpuPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3955:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl time_compute
.bss
.align 8
.type time_compute, @object
.size time_compute, 8
time_compute:
.zero 8
.globl time_memcpy
.align 8
.type time_memcpy, @object
.size time_memcpy, 8
time_memcpy:
.zero 8
.globl d_A
.align 8
.type d_A, @object
.size d_A, 8
d_A:
.zero 8
.globl N
.data
.align 4
.type N, @object
.size N, 4
N:
.long 1024
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vec_inc_gpu.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z7inc_cpuPfii
.LCPI0_0:
.long 0x3f800000 # float 1
.text
.globl _Z7inc_cpuPfii
.p2align 4, 0x90
.type _Z7inc_cpuPfii,@function
_Z7inc_cpuPfii: # @_Z7inc_cpuPfii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_7
# %bb.1: # %.preheader.lr.ph
movl %esi, %eax
xorl %ecx, %ecx
movss .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_6: # in Loop: Header=BB0_2 Depth=1
incq %rcx
cmpq %rax, %rcx
je .LBB0_7
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
testl %edx, %edx
jle .LBB0_6
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movss (%rdi,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movl %edx, %esi
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
addss %xmm0, %xmm1
decl %esi
jne .LBB0_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
movss %xmm1, (%rdi,%rcx,4)
jmp .LBB0_6
.LBB0_7: # %._crit_edge10
retq
.Lfunc_end0:
.size _Z7inc_cpuPfii, .Lfunc_end0-_Z7inc_cpuPfii
.cfi_endproc
# -- End function
.globl _Z22__device_stub__inc_gpuPfii # -- Begin function _Z22__device_stub__inc_gpuPfii
.p2align 4, 0x90
.type _Z22__device_stub__inc_gpuPfii,@function
_Z22__device_stub__inc_gpuPfii: # @_Z22__device_stub__inc_gpuPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7inc_gpuPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z22__device_stub__inc_gpuPfii, .Lfunc_end1-_Z22__device_stub__inc_gpuPfii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z19copy_host_to_devicePfi
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z19copy_host_to_devicePfi
.p2align 4, 0x90
.type _Z19copy_host_to_devicePfi,@function
_Z19copy_host_to_devicePfi: # @_Z19copy_host_to_devicePfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %r15
movq %rsp, %rbx
leaq 24(%rsp), %r14
movq %rbx, %rdi
movq %r14, %rsi
callq gettimeofday
cvtsi2sdq (%rsp), %xmm0
cvtsi2sdq 8(%rsp), %xmm1
divsd .LCPI2_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 16(%rsp) # 8-byte Spill
movslq %ebp, %rsi
leaq (,%rsi,4), %r12
imulq %r12, %rsi
movl $d_A, %edi
callq hipMalloc
movq d_A(%rip), %rdi
movq %r15, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq %rbx, %rdi
movq %r14, %rsi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq (%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 8(%rsp), %xmm1
divsd .LCPI2_0(%rip), %xmm1
addsd %xmm0, %xmm1
subsd 16(%rsp), %xmm1 # 8-byte Folded Reload
addsd time_memcpy(%rip), %xmm1
movsd %xmm1, time_memcpy(%rip)
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z19copy_host_to_devicePfi, .Lfunc_end2-_Z19copy_host_to_devicePfi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z19copy_device_to_hostPfi
.LCPI3_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z19copy_device_to_hostPfi
.p2align 4, 0x90
.type _Z19copy_device_to_hostPfi,@function
_Z19copy_device_to_hostPfi: # @_Z19copy_device_to_hostPfi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $40, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %ebx
movq %rdi, %r14
leaq 8(%rsp), %r15
leaq 32(%rsp), %r12
movq %r15, %rdi
movq %r12, %rsi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm0
cvtsi2sdq 16(%rsp), %xmm1
divsd .LCPI3_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 24(%rsp) # 8-byte Spill
movq d_A(%rip), %rsi
movslq %ebx, %rdx
shlq $2, %rdx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq d_A(%rip), %rdi
callq hipFree
movq %r15, %rdi
movq %r12, %rsi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
divsd .LCPI3_0(%rip), %xmm1
addsd %xmm0, %xmm1
subsd 24(%rsp), %xmm1 # 8-byte Folded Reload
addsd time_memcpy(%rip), %xmm1
movsd %xmm1, time_memcpy(%rip)
addq $40, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z19copy_device_to_hostPfi, .Lfunc_end3-_Z19copy_device_to_hostPfi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x412e848000000000 # double 1.0E+6
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI4_1:
.long 0x3f800000 # float 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $5, %edi
jne .LBB4_28
# %bb.1:
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
movq 32(%rbx), %rdi
movl $.L.str.1, %esi
callq strcmp
movl %eax, 28(%rsp) # 4-byte Spill
movslq N(%rip), %r13
leaq (,%r13,4), %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
testq %r13, %r13
jle .LBB4_3
# %bb.2: # %.lr.ph.preheader
movl %r13d, %edx
shlq $2, %rdx
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
.LBB4_3: # %._crit_edge
cmpl $2, %ebp
je .LBB4_13
# %bb.4: # %._crit_edge
cmpl $1, %ebp
movl 28(%rsp), %ebp # 4-byte Reload
jne .LBB4_21
# %bb.5:
leaq 8(%rsp), %rdi
leaq 56(%rsp), %rsi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm0
cvtsi2sdq 16(%rsp), %xmm1
divsd .LCPI4_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
movl N(%rip), %eax
testl %eax, %eax
jle .LBB4_12
# %bb.6: # %.preheader.lr.ph.i
xorl %ecx, %ecx
movss .LCPI4_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
jmp .LBB4_7
.p2align 4, 0x90
.LBB4_11: # in Loop: Header=BB4_7 Depth=1
incq %rcx
cmpq %rax, %rcx
je .LBB4_12
.LBB4_7: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_9 Depth 2
testl %r14d, %r14d
jle .LBB4_11
# %bb.8: # %.lr.ph.i
# in Loop: Header=BB4_7 Depth=1
movss (%rbx,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movl %r14d, %edx
.p2align 4, 0x90
.LBB4_9: # Parent Loop BB4_7 Depth=1
# => This Inner Loop Header: Depth=2
addss %xmm0, %xmm1
decl %edx
jne .LBB4_9
# %bb.10: # %._crit_edge.i
# in Loop: Header=BB4_7 Depth=1
movss %xmm1, (%rbx,%rcx,4)
jmp .LBB4_11
.LBB4_12: # %_Z7inc_cpuPfii.exit
leaq 8(%rsp), %rdi
leaq 56(%rsp), %rsi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
divsd .LCPI4_0(%rip), %xmm1
addsd %xmm0, %xmm1
subsd (%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, time_compute(%rip)
.LBB4_21:
testl %ebp, %ebp
jne .LBB4_26
jmp .LBB4_22
.LBB4_13:
leaq 32(%rsp), %rbp
leaq 8(%rsp), %rsi
movq %rbp, %rdi
callq gettimeofday
cvtsi2sdq 32(%rsp), %xmm0
cvtsi2sdq 40(%rsp), %xmm1
divsd .LCPI4_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
imulq %r12, %r13
movl $d_A, %edi
movq %r13, %rsi
callq hipMalloc
movq d_A(%rip), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq %rbp, %rdi
leaq 8(%rsp), %rsi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 32(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 40(%rsp), %xmm1
divsd .LCPI4_0(%rip), %xmm1
addsd %xmm0, %xmm1
subsd (%rsp), %xmm1 # 8-byte Folded Reload
addsd time_memcpy(%rip), %xmm1
movsd %xmm1, time_memcpy(%rip)
leaq 8(%rsp), %rdi
leaq 56(%rsp), %rsi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
movsd %xmm0, 88(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
movl %r15d, %ecx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rcx
movl N(%rip), %eax
xorl %edx, %edx
divl %r15d
# kill: def $eax killed $eax def $rax
orq %rax, %rdi
movl $1, %esi
movq %rcx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_15
# %bb.14:
movq d_A(%rip), %rax
movl N(%rip), %ecx
movq %rax, 128(%rsp)
movl %ecx, 68(%rsp)
movl %r14d, 64(%rsp)
leaq 128(%rsp), %rax
movq %rax, 32(%rsp)
leaq 68(%rsp), %rax
movq %rax, 40(%rsp)
leaq 64(%rsp), %rax
movq %rax, 48(%rsp)
leaq 72(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z7inc_gpuPfii, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_15:
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB4_16
# %bb.18: # %_Z9gpuAssert10hipError_tPKcib.exit
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB4_19
# %bb.20: # %_Z9gpuAssert10hipError_tPKcib.exit40
movsd .LCPI4_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd (%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
divsd %xmm0, %xmm1
addsd 88(%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, (%rsp) # 8-byte Spill
leaq 8(%rsp), %rdi
leaq 56(%rsp), %rsi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
divsd .LCPI4_0(%rip), %xmm1
addsd %xmm0, %xmm1
subsd (%rsp), %xmm1 # 8-byte Folded Reload
movsd %xmm1, time_compute(%rip)
movslq N(%rip), %r14
leaq 32(%rsp), %r15
leaq 72(%rsp), %r12
movq %r15, %rdi
movq %r12, %rsi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 32(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 40(%rsp), %xmm1
divsd .LCPI4_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
movq d_A(%rip), %rsi
shlq $2, %r14
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq d_A(%rip), %rdi
callq hipFree
movq %r15, %rdi
movq %r12, %rsi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 32(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 40(%rsp), %xmm1
divsd .LCPI4_0(%rip), %xmm1
addsd %xmm0, %xmm1
subsd (%rsp), %xmm1 # 8-byte Folded Reload
addsd time_memcpy(%rip), %xmm1
movsd %xmm1, time_memcpy(%rip)
movl 28(%rsp), %ebp # 4-byte Reload
testl %ebp, %ebp
jne .LBB4_26
.LBB4_22: # %.preheader
cmpl $0, N(%rip)
jle .LBB4_25
# %bb.23: # %.lr.ph45.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_24: # %.lr.ph45
# =>This Inner Loop Header: Depth=1
movslq %r14d, %r14
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movslq N(%rip), %rax
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %r14d
cmpl %eax, %r14d
jl .LBB4_24
.LBB4_25: # %._crit_edge46
movl $10, %edi
callq putchar@PLT
testl %ebp, %ebp
je .LBB4_27
.LBB4_26: # %.critedge
movsd time_memcpy(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.5, %edi
movb $1, %al
callq printf
movsd time_compute(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.6, %edi
movb $1, %al
callq printf
.LBB4_27:
movq %rbx, %rdi
callq free
callq hipDeviceReset
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_28:
.cfi_def_cfa_offset 192
movl $.Lstr, %edi
callq puts@PLT
movl $2, %edi
callq exit
.LBB4_16:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $144, %r8d
jmp .LBB4_17
.LBB4_19:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.7, %esi
movl $.L.str.2, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $145, %r8d
.LBB4_17:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7inc_gpuPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type N,@object # @N
.data
.globl N
.p2align 2, 0x0
N:
.long 1024 # 0x400
.size N, 4
.type d_A,@object # @d_A
.bss
.globl d_A
.p2align 3, 0x0
d_A:
.quad 0
.size d_A, 8
.type time_memcpy,@object # @time_memcpy
.globl time_memcpy
.p2align 3, 0x0
time_memcpy:
.quad 0x0000000000000000 # double 0
.size time_memcpy, 8
.type time_compute,@object # @time_compute
.globl time_compute
.p2align 3, 0x0
time_compute:
.quad 0x0000000000000000 # double 0
.size time_compute, 8
.type _Z7inc_gpuPfii,@object # @_Z7inc_gpuPfii
.section .rodata,"a",@progbits
.globl _Z7inc_gpuPfii
.p2align 3, 0x0
_Z7inc_gpuPfii:
.quad _Z22__device_stub__inc_gpuPfii
.size _Z7inc_gpuPfii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "debug"
.size .L.str.1, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/Jchuk99/CS1541_Fall2020/master/study_guides/midterm_2_review/vec_inc_gpu.hip"
.size .L.str.2, 134
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " %10.6f"
.size .L.str.3, 8
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Memcpy Time: %f seconds\n"
.size .L.str.5, 25
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Compute Time: %f seconds\n"
.size .L.str.6, 26
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.7, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7inc_gpuPfii"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Usage: mat_mul_gpu <array size> <block size> <policy (1|2|3)> <(debug|nodebug)>"
.size .Lstr, 80
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__inc_gpuPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_A
.addrsig_sym _Z7inc_gpuPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void cuda_mul(int* A, int* B, int* C, int w)
{
int tid,tx,ty;
//range of tx,ty 0 ~ w
tx = blockDim.x * blockIdx.x + threadIdx.x;
ty = blockDim.y * blockIdx.y + threadIdx.y;
tid = w*ty + tx;
int v = 0;
int a = 0;
int b = 0;
/*
oooo oxo
xxxx X oxo
oooo oxo
oxo
*/
for(int i=0;i< w;i++)
{
a = A[ty * w + i];
b = B[i * w + tx];
v += a+b;
}
C[tid]= v;
} | code for sm_80
Function : _Z8cuda_mulPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R28, RZ, RZ, RZ ; /* 0x000000ffff1c7224 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e240000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe40003f06270 */
/*0070*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0080*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R4, R4, c[0x0][0x4], R5 ; /* 0x0000010004047a24 */
/* 0x001fc800078e0205 */
/*00a0*/ IMAD R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a24 */
/* 0x000fe400078e02ff */
/*00b0*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x002fe200078e0203 */
/*00c0*/ @!P0 BRA 0xbc0 ; /* 0x00000af000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R3, R0.reuse, -0x1, RZ ; /* 0xffffffff00037810 */
/* 0x040fe20007ffe0ff */
/*00e0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00f0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300057812 */
/* 0x000fe400078ec0ff */
/*0100*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe20003f06070 */
/*0110*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fd800078e00ff */
/*0120*/ @!P0 BRA 0xac0 ; /* 0x0000099000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ IMAD.MOV.U32 R25, RZ, RZ, 0x4 ; /* 0x00000004ff197424 */
/* 0x000fe200078e00ff */
/*0150*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0160*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*0170*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f04270 */
/*0180*/ IMAD.WIDE R24, R2, R25, c[0x0][0x168] ; /* 0x00005a0002187625 */
/* 0x000fd800078e0219 */
/*0190*/ @!P0 BRA 0x930 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01a0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01c0*/ @!P1 BRA 0x670 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01e0*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fe20008000f00 */
/*01f0*/ IMAD.U32 R12, RZ, RZ, UR6 ; /* 0x00000006ff0c7e24 */
/* 0x000fe2000f8e00ff */
/*0200*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a6000c1e1900 */
/*0210*/ IMAD.WIDE R12, R4, 0x4, R12 ; /* 0x00000004040c7825 */
/* 0x000fca00078e020c */
/*0220*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0230*/ IMAD.WIDE R10, R0, 0x4, R24 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0218 */
/*0240*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0250*/ IMAD.WIDE R18, R0.reuse, 0x4, R10 ; /* 0x0000000400127825 */
/* 0x040fe200078e020a */
/*0260*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*0270*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*0280*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*0290*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02a0*/ IMAD.WIDE R20, R0.reuse, 0x4, R14 ; /* 0x0000000400147825 */
/* 0x040fe200078e020e */
/*02b0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*02c0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*02e0*/ IMAD.WIDE R14, R0, 0x4, R20 ; /* 0x00000004000e7825 */
/* 0x001fc600078e0214 */
/*02f0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0300*/ IMAD.WIDE R22, R0.reuse, 0x4, R14 ; /* 0x0000000400167825 */
/* 0x040fe200078e020e */
/*0310*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0320*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0330*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x000fc600078e0216 */
/*0340*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0350*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0360*/ IADD3 R29, R29, R27, R28 ; /* 0x0000001b1d1d7210 */
/* 0x004fc60007ffe01c */
/*0370*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*0380*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*0390*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fe200078e0218 */
/*03a0*/ IADD3 R29, R16, R17, R29 ; /* 0x00000011101d7210 */
/* 0x008fca0007ffe01d */
/*03b0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fe400078e020e */
/*03c0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a2000c1e1900 */
/*03d0*/ IADD3 R29, R18, R19, R29 ; /* 0x00000013121d7210 */
/* 0x010fc60007ffe01d */
/*03e0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fe400078e0210 */
/*03f0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a2000c1e1900 */
/*0400*/ IADD3 R26, R26, R7, R29 ; /* 0x000000071a1a7210 */
/* 0x000fc60007ffe01d */
/*0410*/ IMAD.WIDE R22, R0, 0x4, R18 ; /* 0x0000000400167825 */
/* 0x002fe200078e0212 */
/*0420*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea2000c1e1900 */
/*0430*/ IADD3 R9, R20, R9, R26 ; /* 0x0000000914097210 */
/* 0x020fc60007ffe01a */
/*0440*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000f62000c1e1900 */
/*0450*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x001fe200078e0216 */
/*0460*/ IADD3 R11, R8, R11, R9 ; /* 0x0000000b080b7210 */
/* 0x000fe40007ffe009 */
/*0470*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*0480*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*0490*/ IMAD.WIDE R8, R0, 0x4, R24 ; /* 0x0000000400087825 */
/* 0x000fc600078e0218 */
/*04a0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000362000c1e1900 */
/*04b0*/ IADD3 R21, R10, R21, R11 ; /* 0x000000150a157210 */
/* 0x000fc60007ffe00b */
/*04c0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*04d0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*04e0*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008728000c1e1900 */
/*04f0*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0500*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0510*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0520*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0530*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0540*/ IADD3 R9, R28, R27, R21 ; /* 0x0000001b1c097210 */
/* 0x004fc60007ffe015 */
/*0550*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0560*/ IMAD.WIDE R20, R0, 0x4, R10 ; /* 0x0000000400147825 */
/* 0x000fca00078e020a */
/*0570*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*0580*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*0590*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*05a0*/ IADD3 R7, R14, R7, R9 ; /* 0x000000070e077210 */
/* 0x000fc80007ffe009 */
/*05b0*/ IADD3 R7, R16, R29, R7 ; /* 0x0000001d10077210 */
/* 0x020fc80007ffe007 */
/*05c0*/ IADD3 R7, R18, R26, R7 ; /* 0x0000001a12077210 */
/* 0x000fc80007ffe007 */
/*05d0*/ IADD3 R7, R22, R17, R7 ; /* 0x0000001116077210 */
/* 0x010fe20007ffe007 */
/*05e0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*05f0*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc60007ffe0ff */
/*0600*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0610*/ IADD3 R7, R15, R24, R7 ; /* 0x000000180f077210 */
/* 0x008fc80007ffe007 */
/*0620*/ IADD3 R28, R19, R28, R7 ; /* 0x0000001c131c7210 */
/* 0x004fc80007ffe007 */
/*0630*/ IADD3 R28, R23, R25, R28 ; /* 0x00000019171c7210 */
/* 0x000fe20007ffe01c */
/*0640*/ IMAD.WIDE R24, R0, 0x4, R20 ; /* 0x0000000400187825 */
/* 0x000fc600078e0214 */
/*0650*/ IADD3 R28, R27, R8, R28 ; /* 0x000000081b1c7210 */
/* 0x000fe20007ffe01c */
/*0660*/ @P1 BRA 0x1e0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0670*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0680*/ @!P1 BRA 0x910 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*0690*/ IMAD.WIDE R16, R0.reuse, 0x4, R24 ; /* 0x0000000400107825 */
/* 0x040fe200078e0218 */
/*06a0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a6000c1e1900 */
/*06b0*/ IMAD.U32 R8, RZ, RZ, UR6 ; /* 0x00000006ff087e24 */
/* 0x000fe2000f8e00ff */
/*06c0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e2000c1e1900 */
/*06d0*/ IMAD.U32 R9, RZ, RZ, UR7 ; /* 0x00000007ff097e24 */
/* 0x000fe4000f8e00ff */
/*06e0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0210 */
/*06f0*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fe200078e0208 */
/*0700*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0710*/ IMAD.WIDE R14, R0.reuse, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x040fe200078e020c */
/*0720*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0730*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0740*/ IMAD.WIDE R10, R0, 0x4, R14 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020e */
/*0750*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0760*/ IMAD.WIDE R16, R0.reuse, 0x4, R10 ; /* 0x0000000400107825 */
/* 0x042fe200078e020a */
/*0770*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0780*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*0790*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*07a0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07b0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*07c0*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x010fc600078e0212 */
/*07d0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*07e0*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0800*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0810*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0830*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0840*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0850*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*0860*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0870*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0880*/ IADD3 R7, R7, R20, R28 ; /* 0x0000001407077210 */
/* 0x004fc80007ffe01c */
/*0890*/ IADD3 R7, R21, R22, R7 ; /* 0x0000001615077210 */
/* 0x008fc80007ffe007 */
/*08a0*/ IADD3 R7, R23, R26, R7 ; /* 0x0000001a17077210 */
/* 0x020fc80007ffe007 */
/*08b0*/ IADD3 R7, R14, R27, R7 ; /* 0x0000001b0e077210 */
/* 0x000fc80007ffe007 */
/*08c0*/ IADD3 R7, R10, R25, R7 ; /* 0x000000190a077210 */
/* 0x000fc80007ffe007 */
/*08d0*/ IADD3 R7, R16, R29, R7 ; /* 0x0000001d10077210 */
/* 0x010fc80007ffe007 */
/*08e0*/ IADD3 R7, R24, R11, R7 ; /* 0x0000000b18077210 */
/* 0x000fe20007ffe007 */
/*08f0*/ IMAD.WIDE R24, R0, 0x4, R12 ; /* 0x0000000400187825 */
/* 0x000fc600078e020c */
/*0900*/ IADD3 R28, R15, R18, R7 ; /* 0x000000120f1c7210 */
/* 0x000fe40007ffe007 */
/*0910*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0920*/ @!P0 BRA 0xac0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0930*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0940*/ IMAD.U32 R8, RZ, RZ, UR6 ; /* 0x00000006ff087e24 */
/* 0x000fe4000f8e00ff */
/*0950*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fe400078e0218 */
/*0960*/ LDG.E R24, [R24.64] ; /* 0x0000000418187981 */
/* 0x000ea4000c1e1900 */
/*0970*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fc800078e0208 */
/*0980*/ IMAD.WIDE R12, R0.reuse, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x040fe200078e020e */
/*0990*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09b0*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020c */
/*09c0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*09d0*/ LDG.E R17, [R12.64] ; /* 0x000000040c117981 */
/* 0x000f28000c1e1900 */
/*09e0*/ LDG.E R18, [R8.64+0x8] ; /* 0x0000080408127981 */
/* 0x000f28000c1e1900 */
/*09f0*/ LDG.E R20, [R8.64+0xc] ; /* 0x00000c0408147981 */
/* 0x000f68000c1e1900 */
/*0a00*/ LDG.E R19, [R10.64] ; /* 0x000000040a137981 */
/* 0x000f62000c1e1900 */
/*0a10*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a20*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a30*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a40*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc60007ffe0ff */
/*0a50*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a60*/ IADD3 R7, R24, R7, R28 ; /* 0x0000000718077210 */
/* 0x004fc80007ffe01c */
/*0a70*/ IADD3 R7, R14, R16, R7 ; /* 0x000000100e077210 */
/* 0x008fe20007ffe007 */
/*0a80*/ IMAD.WIDE R24, R0, 0x4, R10 ; /* 0x0000000400187825 */
/* 0x000fc600078e020a */
/*0a90*/ IADD3 R7, R17, R18, R7 ; /* 0x0000001211077210 */
/* 0x010fc80007ffe007 */
/*0aa0*/ IADD3 R28, R19, R20, R7 ; /* 0x00000014131c7210 */
/* 0x020fe20007ffe007 */
/*0ab0*/ @P0 BRA 0x930 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0ac0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0ad0*/ @!P0 BRA 0xbc0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0ae0*/ IMAD.IADD R6, R4, 0x1, R3 ; /* 0x0000000104067824 */
/* 0x000fe400078e0203 */
/*0af0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fe400078e00ff */
/*0b00*/ IMAD R3, R3, c[0x0][0x178], R2 ; /* 0x00005e0003037a24 */
/* 0x000fe400078e0202 */
/*0b10*/ IMAD.WIDE R6, R6, R8, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0208 */
/*0b20*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fca00078e0208 */
/*0b30*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x0000a8000c1e1900 */
/*0b40*/ LDG.E R3, [R6.64] ; /* 0x0000000406037981 */
/* 0x0002a2000c1e1900 */
/*0b50*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0b60*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0b70*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0b80*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fca0007f3e0ff */
/*0b90*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x000fe200008e0607 */
/*0ba0*/ IADD3 R28, R10, R3, R28 ; /* 0x000000030a1c7210 */
/* 0x004fca0007ffe01c */
/*0bb0*/ @P0 BRA 0xb30 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0bc0*/ IADD3 R2, R2, R4, RZ ; /* 0x0000000402027210 */
/* 0x000fe20007ffe0ff */
/*0bd0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0be0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0bf0*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c00*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c10*/ BRA 0xc10; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void cuda_mul(int* A, int* B, int* C, int w)
{
int tid,tx,ty;
//range of tx,ty 0 ~ w
tx = blockDim.x * blockIdx.x + threadIdx.x;
ty = blockDim.y * blockIdx.y + threadIdx.y;
tid = w*ty + tx;
int v = 0;
int a = 0;
int b = 0;
/*
oooo oxo
xxxx X oxo
oooo oxo
oxo
*/
for(int i=0;i< w;i++)
{
a = A[ty * w + i];
b = B[i * w + tx];
v += a+b;
}
C[tid]= v;
} | .file "tmpxft_00121f3d_00000000-6_cuda_mul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z8cuda_mulPiS_S_iPiS_S_i
.type _Z32__device_stub__Z8cuda_mulPiS_S_iPiS_S_i, @function
_Z32__device_stub__Z8cuda_mulPiS_S_iPiS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8cuda_mulPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z8cuda_mulPiS_S_iPiS_S_i, .-_Z32__device_stub__Z8cuda_mulPiS_S_iPiS_S_i
.globl _Z8cuda_mulPiS_S_i
.type _Z8cuda_mulPiS_S_i, @function
_Z8cuda_mulPiS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8cuda_mulPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8cuda_mulPiS_S_i, .-_Z8cuda_mulPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8cuda_mulPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8cuda_mulPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void cuda_mul(int* A, int* B, int* C, int w)
{
int tid,tx,ty;
//range of tx,ty 0 ~ w
tx = blockDim.x * blockIdx.x + threadIdx.x;
ty = blockDim.y * blockIdx.y + threadIdx.y;
tid = w*ty + tx;
int v = 0;
int a = 0;
int b = 0;
/*
oooo oxo
xxxx X oxo
oooo oxo
oxo
*/
for(int i=0;i< w;i++)
{
a = A[ty * w + i];
b = B[i * w + tx];
v += a+b;
}
C[tid]= v;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuda_mul(int* A, int* B, int* C, int w)
{
int tid,tx,ty;
//range of tx,ty 0 ~ w
tx = blockDim.x * blockIdx.x + threadIdx.x;
ty = blockDim.y * blockIdx.y + threadIdx.y;
tid = w*ty + tx;
int v = 0;
int a = 0;
int b = 0;
/*
oooo oxo
xxxx X oxo
oooo oxo
oxo
*/
for(int i=0;i< w;i++)
{
a = A[ty * w + i];
b = B[i * w + tx];
v += a+b;
}
C[tid]= v;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuda_mul(int* A, int* B, int* C, int w)
{
int tid,tx,ty;
//range of tx,ty 0 ~ w
tx = blockDim.x * blockIdx.x + threadIdx.x;
ty = blockDim.y * blockIdx.y + threadIdx.y;
tid = w*ty + tx;
int v = 0;
int a = 0;
int b = 0;
/*
oooo oxo
xxxx X oxo
oooo oxo
oxo
*/
for(int i=0;i< w;i++)
{
a = A[ty * w + i];
b = B[i * w + tx];
v += a+b;
}
C[tid]= v;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8cuda_mulPiS_S_i
.globl _Z8cuda_mulPiS_S_i
.p2align 8
.type _Z8cuda_mulPiS_S_i,@function
_Z8cuda_mulPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
v_and_b32_e32 v3, 0x3ff, v0
s_cmp_lt_i32 s2, 1
v_mad_u64_u32 v[0:1], null, s14, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_3)
v_mul_lo_u32 v1, v2, s2
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add3_u32 v6, v5, v6, v7
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v1, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8cuda_mulPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8cuda_mulPiS_S_i, .Lfunc_end0-_Z8cuda_mulPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8cuda_mulPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8cuda_mulPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuda_mul(int* A, int* B, int* C, int w)
{
int tid,tx,ty;
//range of tx,ty 0 ~ w
tx = blockDim.x * blockIdx.x + threadIdx.x;
ty = blockDim.y * blockIdx.y + threadIdx.y;
tid = w*ty + tx;
int v = 0;
int a = 0;
int b = 0;
/*
oooo oxo
xxxx X oxo
oooo oxo
oxo
*/
for(int i=0;i< w;i++)
{
a = A[ty * w + i];
b = B[i * w + tx];
v += a+b;
}
C[tid]= v;
} | .text
.file "cuda_mul.hip"
.globl _Z23__device_stub__cuda_mulPiS_S_i # -- Begin function _Z23__device_stub__cuda_mulPiS_S_i
.p2align 4, 0x90
.type _Z23__device_stub__cuda_mulPiS_S_i,@function
_Z23__device_stub__cuda_mulPiS_S_i: # @_Z23__device_stub__cuda_mulPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8cuda_mulPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__cuda_mulPiS_S_i, .Lfunc_end0-_Z23__device_stub__cuda_mulPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8cuda_mulPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8cuda_mulPiS_S_i,@object # @_Z8cuda_mulPiS_S_i
.section .rodata,"a",@progbits
.globl _Z8cuda_mulPiS_S_i
.p2align 3, 0x0
_Z8cuda_mulPiS_S_i:
.quad _Z23__device_stub__cuda_mulPiS_S_i
.size _Z8cuda_mulPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8cuda_mulPiS_S_i"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__cuda_mulPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8cuda_mulPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8cuda_mulPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R28, RZ, RZ, RZ ; /* 0x000000ffff1c7224 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e240000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe40003f06270 */
/*0070*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0080*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R4, R4, c[0x0][0x4], R5 ; /* 0x0000010004047a24 */
/* 0x001fc800078e0205 */
/*00a0*/ IMAD R4, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a24 */
/* 0x000fe400078e02ff */
/*00b0*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x002fe200078e0203 */
/*00c0*/ @!P0 BRA 0xbc0 ; /* 0x00000af000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R3, R0.reuse, -0x1, RZ ; /* 0xffffffff00037810 */
/* 0x040fe20007ffe0ff */
/*00e0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00f0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300057812 */
/* 0x000fe400078ec0ff */
/*0100*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe20003f06070 */
/*0110*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fd800078e00ff */
/*0120*/ @!P0 BRA 0xac0 ; /* 0x0000099000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ IMAD.MOV.U32 R25, RZ, RZ, 0x4 ; /* 0x00000004ff197424 */
/* 0x000fe200078e00ff */
/*0150*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0160*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*0170*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f04270 */
/*0180*/ IMAD.WIDE R24, R2, R25, c[0x0][0x168] ; /* 0x00005a0002187625 */
/* 0x000fd800078e0219 */
/*0190*/ @!P0 BRA 0x930 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01a0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01c0*/ @!P1 BRA 0x670 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01e0*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fe20008000f00 */
/*01f0*/ IMAD.U32 R12, RZ, RZ, UR6 ; /* 0x00000006ff0c7e24 */
/* 0x000fe2000f8e00ff */
/*0200*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a6000c1e1900 */
/*0210*/ IMAD.WIDE R12, R4, 0x4, R12 ; /* 0x00000004040c7825 */
/* 0x000fca00078e020c */
/*0220*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0230*/ IMAD.WIDE R10, R0, 0x4, R24 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0218 */
/*0240*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0250*/ IMAD.WIDE R18, R0.reuse, 0x4, R10 ; /* 0x0000000400127825 */
/* 0x040fe200078e020a */
/*0260*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*0270*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*0280*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*0290*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02a0*/ IMAD.WIDE R20, R0.reuse, 0x4, R14 ; /* 0x0000000400147825 */
/* 0x040fe200078e020e */
/*02b0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*02c0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*02d0*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*02e0*/ IMAD.WIDE R14, R0, 0x4, R20 ; /* 0x00000004000e7825 */
/* 0x001fc600078e0214 */
/*02f0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0300*/ IMAD.WIDE R22, R0.reuse, 0x4, R14 ; /* 0x0000000400167825 */
/* 0x040fe200078e020e */
/*0310*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0320*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0330*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x000fc600078e0216 */
/*0340*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0350*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0360*/ IADD3 R29, R29, R27, R28 ; /* 0x0000001b1d1d7210 */
/* 0x004fc60007ffe01c */
/*0370*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*0380*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*0390*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fe200078e0218 */
/*03a0*/ IADD3 R29, R16, R17, R29 ; /* 0x00000011101d7210 */
/* 0x008fca0007ffe01d */
/*03b0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fe400078e020e */
/*03c0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a2000c1e1900 */
/*03d0*/ IADD3 R29, R18, R19, R29 ; /* 0x00000013121d7210 */
/* 0x010fc60007ffe01d */
/*03e0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fe400078e0210 */
/*03f0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a2000c1e1900 */
/*0400*/ IADD3 R26, R26, R7, R29 ; /* 0x000000071a1a7210 */
/* 0x000fc60007ffe01d */
/*0410*/ IMAD.WIDE R22, R0, 0x4, R18 ; /* 0x0000000400167825 */
/* 0x002fe200078e0212 */
/*0420*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea2000c1e1900 */
/*0430*/ IADD3 R9, R20, R9, R26 ; /* 0x0000000914097210 */
/* 0x020fc60007ffe01a */
/*0440*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000f62000c1e1900 */
/*0450*/ IMAD.WIDE R24, R0, 0x4, R22 ; /* 0x0000000400187825 */
/* 0x001fe200078e0216 */
/*0460*/ IADD3 R11, R8, R11, R9 ; /* 0x0000000b080b7210 */
/* 0x000fe40007ffe009 */
/*0470*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*0480*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*0490*/ IMAD.WIDE R8, R0, 0x4, R24 ; /* 0x0000000400087825 */
/* 0x000fc600078e0218 */
/*04a0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000362000c1e1900 */
/*04b0*/ IADD3 R21, R10, R21, R11 ; /* 0x000000150a157210 */
/* 0x000fc60007ffe00b */
/*04c0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*04d0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0208 */
/*04e0*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008728000c1e1900 */
/*04f0*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0500*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0510*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0520*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0530*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0540*/ IADD3 R9, R28, R27, R21 ; /* 0x0000001b1c097210 */
/* 0x004fc60007ffe015 */
/*0550*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0560*/ IMAD.WIDE R20, R0, 0x4, R10 ; /* 0x0000000400147825 */
/* 0x000fca00078e020a */
/*0570*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*0580*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*0590*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*05a0*/ IADD3 R7, R14, R7, R9 ; /* 0x000000070e077210 */
/* 0x000fc80007ffe009 */
/*05b0*/ IADD3 R7, R16, R29, R7 ; /* 0x0000001d10077210 */
/* 0x020fc80007ffe007 */
/*05c0*/ IADD3 R7, R18, R26, R7 ; /* 0x0000001a12077210 */
/* 0x000fc80007ffe007 */
/*05d0*/ IADD3 R7, R22, R17, R7 ; /* 0x0000001116077210 */
/* 0x010fe20007ffe007 */
/*05e0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*05f0*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc60007ffe0ff */
/*0600*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0610*/ IADD3 R7, R15, R24, R7 ; /* 0x000000180f077210 */
/* 0x008fc80007ffe007 */
/*0620*/ IADD3 R28, R19, R28, R7 ; /* 0x0000001c131c7210 */
/* 0x004fc80007ffe007 */
/*0630*/ IADD3 R28, R23, R25, R28 ; /* 0x00000019171c7210 */
/* 0x000fe20007ffe01c */
/*0640*/ IMAD.WIDE R24, R0, 0x4, R20 ; /* 0x0000000400187825 */
/* 0x000fc600078e0214 */
/*0650*/ IADD3 R28, R27, R8, R28 ; /* 0x000000081b1c7210 */
/* 0x000fe20007ffe01c */
/*0660*/ @P1 BRA 0x1e0 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0670*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0680*/ @!P1 BRA 0x910 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*0690*/ IMAD.WIDE R16, R0.reuse, 0x4, R24 ; /* 0x0000000400107825 */
/* 0x040fe200078e0218 */
/*06a0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a6000c1e1900 */
/*06b0*/ IMAD.U32 R8, RZ, RZ, UR6 ; /* 0x00000006ff087e24 */
/* 0x000fe2000f8e00ff */
/*06c0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e2000c1e1900 */
/*06d0*/ IMAD.U32 R9, RZ, RZ, UR7 ; /* 0x00000007ff097e24 */
/* 0x000fe4000f8e00ff */
/*06e0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0210 */
/*06f0*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fe200078e0208 */
/*0700*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0710*/ IMAD.WIDE R14, R0.reuse, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x040fe200078e020c */
/*0720*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0730*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0740*/ IMAD.WIDE R10, R0, 0x4, R14 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020e */
/*0750*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0760*/ IMAD.WIDE R16, R0.reuse, 0x4, R10 ; /* 0x0000000400107825 */
/* 0x042fe200078e020a */
/*0770*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*0780*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*0790*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*07a0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07b0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*07c0*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x010fc600078e0212 */
/*07d0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*07e0*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*07f0*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0800*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0810*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0830*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0840*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0850*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*0860*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0870*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0880*/ IADD3 R7, R7, R20, R28 ; /* 0x0000001407077210 */
/* 0x004fc80007ffe01c */
/*0890*/ IADD3 R7, R21, R22, R7 ; /* 0x0000001615077210 */
/* 0x008fc80007ffe007 */
/*08a0*/ IADD3 R7, R23, R26, R7 ; /* 0x0000001a17077210 */
/* 0x020fc80007ffe007 */
/*08b0*/ IADD3 R7, R14, R27, R7 ; /* 0x0000001b0e077210 */
/* 0x000fc80007ffe007 */
/*08c0*/ IADD3 R7, R10, R25, R7 ; /* 0x000000190a077210 */
/* 0x000fc80007ffe007 */
/*08d0*/ IADD3 R7, R16, R29, R7 ; /* 0x0000001d10077210 */
/* 0x010fc80007ffe007 */
/*08e0*/ IADD3 R7, R24, R11, R7 ; /* 0x0000000b18077210 */
/* 0x000fe20007ffe007 */
/*08f0*/ IMAD.WIDE R24, R0, 0x4, R12 ; /* 0x0000000400187825 */
/* 0x000fc600078e020c */
/*0900*/ IADD3 R28, R15, R18, R7 ; /* 0x000000120f1c7210 */
/* 0x000fe40007ffe007 */
/*0910*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0920*/ @!P0 BRA 0xac0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0930*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0940*/ IMAD.U32 R8, RZ, RZ, UR6 ; /* 0x00000006ff087e24 */
/* 0x000fe4000f8e00ff */
/*0950*/ IMAD.WIDE R14, R0, 0x4, R24 ; /* 0x00000004000e7825 */
/* 0x000fe400078e0218 */
/*0960*/ LDG.E R24, [R24.64] ; /* 0x0000000418187981 */
/* 0x000ea4000c1e1900 */
/*0970*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fc800078e0208 */
/*0980*/ IMAD.WIDE R12, R0.reuse, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x040fe200078e020e */
/*0990*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09b0*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020c */
/*09c0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*09d0*/ LDG.E R17, [R12.64] ; /* 0x000000040c117981 */
/* 0x000f28000c1e1900 */
/*09e0*/ LDG.E R18, [R8.64+0x8] ; /* 0x0000080408127981 */
/* 0x000f28000c1e1900 */
/*09f0*/ LDG.E R20, [R8.64+0xc] ; /* 0x00000c0408147981 */
/* 0x000f68000c1e1900 */
/*0a00*/ LDG.E R19, [R10.64] ; /* 0x000000040a137981 */
/* 0x000f62000c1e1900 */
/*0a10*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a20*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a30*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a40*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc60007ffe0ff */
/*0a50*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a60*/ IADD3 R7, R24, R7, R28 ; /* 0x0000000718077210 */
/* 0x004fc80007ffe01c */
/*0a70*/ IADD3 R7, R14, R16, R7 ; /* 0x000000100e077210 */
/* 0x008fe20007ffe007 */
/*0a80*/ IMAD.WIDE R24, R0, 0x4, R10 ; /* 0x0000000400187825 */
/* 0x000fc600078e020a */
/*0a90*/ IADD3 R7, R17, R18, R7 ; /* 0x0000001211077210 */
/* 0x010fc80007ffe007 */
/*0aa0*/ IADD3 R28, R19, R20, R7 ; /* 0x00000014131c7210 */
/* 0x020fe20007ffe007 */
/*0ab0*/ @P0 BRA 0x930 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0ac0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0ad0*/ @!P0 BRA 0xbc0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0ae0*/ IMAD.IADD R6, R4, 0x1, R3 ; /* 0x0000000104067824 */
/* 0x000fe400078e0203 */
/*0af0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fe400078e00ff */
/*0b00*/ IMAD R3, R3, c[0x0][0x178], R2 ; /* 0x00005e0003037a24 */
/* 0x000fe400078e0202 */
/*0b10*/ IMAD.WIDE R6, R6, R8, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0208 */
/*0b20*/ IMAD.WIDE R8, R3, R8, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fca00078e0208 */
/*0b30*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x0000a8000c1e1900 */
/*0b40*/ LDG.E R3, [R6.64] ; /* 0x0000000406037981 */
/* 0x0002a2000c1e1900 */
/*0b50*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0b60*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0b70*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0b80*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fca0007f3e0ff */
/*0b90*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x000fe200008e0607 */
/*0ba0*/ IADD3 R28, R10, R3, R28 ; /* 0x000000030a1c7210 */
/* 0x004fca0007ffe01c */
/*0bb0*/ @P0 BRA 0xb30 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0bc0*/ IADD3 R2, R2, R4, RZ ; /* 0x0000000402027210 */
/* 0x000fe20007ffe0ff */
/*0bd0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0be0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0bf0*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c00*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c10*/ BRA 0xc10; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8cuda_mulPiS_S_i
.globl _Z8cuda_mulPiS_S_i
.p2align 8
.type _Z8cuda_mulPiS_S_i,@function
_Z8cuda_mulPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
v_and_b32_e32 v3, 0x3ff, v0
s_cmp_lt_i32 s2, 1
v_mad_u64_u32 v[0:1], null, s14, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_3)
v_mul_lo_u32 v1, v2, s2
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add3_u32 v6, v5, v6, v7
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v1, v0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8cuda_mulPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8cuda_mulPiS_S_i, .Lfunc_end0-_Z8cuda_mulPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8cuda_mulPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8cuda_mulPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00121f3d_00000000-6_cuda_mul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z8cuda_mulPiS_S_iPiS_S_i
.type _Z32__device_stub__Z8cuda_mulPiS_S_iPiS_S_i, @function
_Z32__device_stub__Z8cuda_mulPiS_S_iPiS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8cuda_mulPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z8cuda_mulPiS_S_iPiS_S_i, .-_Z32__device_stub__Z8cuda_mulPiS_S_iPiS_S_i
.globl _Z8cuda_mulPiS_S_i
.type _Z8cuda_mulPiS_S_i, @function
_Z8cuda_mulPiS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8cuda_mulPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8cuda_mulPiS_S_i, .-_Z8cuda_mulPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8cuda_mulPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8cuda_mulPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_mul.hip"
.globl _Z23__device_stub__cuda_mulPiS_S_i # -- Begin function _Z23__device_stub__cuda_mulPiS_S_i
.p2align 4, 0x90
.type _Z23__device_stub__cuda_mulPiS_S_i,@function
_Z23__device_stub__cuda_mulPiS_S_i: # @_Z23__device_stub__cuda_mulPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8cuda_mulPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__cuda_mulPiS_S_i, .Lfunc_end0-_Z23__device_stub__cuda_mulPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8cuda_mulPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8cuda_mulPiS_S_i,@object # @_Z8cuda_mulPiS_S_i
.section .rodata,"a",@progbits
.globl _Z8cuda_mulPiS_S_i
.p2align 3, 0x0
_Z8cuda_mulPiS_S_i:
.quad _Z23__device_stub__cuda_mulPiS_S_i
.size _Z8cuda_mulPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8cuda_mulPiS_S_i"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__cuda_mulPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8cuda_mulPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ int is_source_gpu(int i, int j, int radius, int source_active, int src_x, int src_y)
{
if (!source_active)
return 0;
if (sqrt(pow((float)(src_x - i), 2) + pow((float)(src_y - j), 2)) <= radius)
return 1;
return 0;
}
__global__ void wireless_src_pulse_kernel(int step, double amp, double MAX_TIME, double TIME_STEP, int radius, int source_active, int src_x, int src_y, double *ua_gpu, double *ub_gpu, double *uc_gpu)
{
int i, j;
int i_start, j_start;
int i_final, j_final;
int line_length;
int global_thread_x, global_thread_y;
int thread_work = 32;
line_length = gridDim.y * blockDim.y;
global_thread_x = blockDim.x * blockIdx.x + threadIdx.x;
global_thread_y = blockDim.y * blockIdx.y + threadIdx.y;
i_start = global_thread_x * thread_work;
j_start = global_thread_y * thread_work;
i_final = global_thread_x * (thread_work + 1);
j_final = global_thread_y * (thread_work + 1);
if (step < (int)(MAX_TIME / TIME_STEP) / 2){
// Pulse source
for (i = i_start; i < i_final; i++){
for (j = j_start; j < j_final; j++){
if (is_source_gpu(i, j, radius, 1, src_x, src_y))
uc_gpu[i * line_length + j] = amp * fabs(sin(step * M_PI/4));
}
}
} else if (source_active){
for (i = i_start; i < i_final; i++) {
for (j = j_start; j < j_final; j++) {
if (is_source_gpu(i, j, radius, source_active, src_x, src_y)) {
ua_gpu[i * line_length + j] = 0;
ub_gpu[i * line_length + j] = 0;
uc_gpu[i * line_length + j] = 0;
}
}
}
}
// All threads should reach this point before setting source_active.
// Option 1: need a thread barrier here -> not done, I chose option 2
// Option 2: simply write 2 kernels and syncCPU -> done, I chose this option
// CPU is setting source_active = 0 after this kernel is done executing.
} | .file "tmpxft_00007c81_00000000-6_wireless_src_pulse_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13is_source_gpuiiiiii
.type _Z13is_source_gpuiiiiii, @function
_Z13is_source_gpuiiiiii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z13is_source_gpuiiiiii, .-_Z13is_source_gpuiiiiii
.globl _Z57__device_stub__Z25wireless_src_pulse_kernelidddiiiiPdS_S_idddiiiiPdS_S_
.type _Z57__device_stub__Z25wireless_src_pulse_kernelidddiiiiPdS_S_idddiiiiPdS_S_, @function
_Z57__device_stub__Z25wireless_src_pulse_kernelidddiiiiPdS_S_idddiiiiPdS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movl %edi, 76(%rsp)
movsd %xmm0, 64(%rsp)
movsd %xmm1, 56(%rsp)
movsd %xmm2, 48(%rsp)
movl %esi, 72(%rsp)
movl %edx, 44(%rsp)
movl %ecx, 40(%rsp)
movl %r8d, 36(%rsp)
movq %r9, 24(%rsp)
movq 256(%rsp), %rax
movq %rax, 16(%rsp)
movq 264(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 76(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 72(%rsp), %rax
movq %rax, 176(%rsp)
leaq 44(%rsp), %rax
movq %rax, 184(%rsp)
leaq 40(%rsp), %rax
movq %rax, 192(%rsp)
leaq 36(%rsp), %rax
movq %rax, 200(%rsp)
leaq 24(%rsp), %rax
movq %rax, 208(%rsp)
leaq 16(%rsp), %rax
movq %rax, 216(%rsp)
leaq 8(%rsp), %rax
movq %rax, 224(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 264
pushq 88(%rsp)
.cfi_def_cfa_offset 272
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z25wireless_src_pulse_kernelidddiiiiPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z57__device_stub__Z25wireless_src_pulse_kernelidddiiiiPdS_S_idddiiiiPdS_S_, .-_Z57__device_stub__Z25wireless_src_pulse_kernelidddiiiiPdS_S_idddiiiiPdS_S_
.globl _Z25wireless_src_pulse_kernelidddiiiiPdS_S_
.type _Z25wireless_src_pulse_kernelidddiiiiPdS_S_, @function
_Z25wireless_src_pulse_kernelidddiiiiPdS_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z57__device_stub__Z25wireless_src_pulse_kernelidddiiiiPdS_S_idddiiiiPdS_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z25wireless_src_pulse_kernelidddiiiiPdS_S_, .-_Z25wireless_src_pulse_kernelidddiiiiPdS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z25wireless_src_pulse_kernelidddiiiiPdS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z25wireless_src_pulse_kernelidddiiiiPdS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ int is_source_gpu(int i, int j, int radius, int source_active, int src_x, int src_y)
{
if (!source_active)
return 0;
if (sqrt(pow((float)(src_x - i), 2) + pow((float)(src_y - j), 2)) <= radius)
return 1;
return 0;
}
__global__ void wireless_src_pulse_kernel(int step, double amp, double MAX_TIME, double TIME_STEP, int radius, int source_active, int src_x, int src_y, double *ua_gpu, double *ub_gpu, double *uc_gpu)
{
int i, j;
int i_start, j_start;
int i_final, j_final;
int line_length;
int global_thread_x, global_thread_y;
int thread_work = 32;
line_length = gridDim.y * blockDim.y;
global_thread_x = blockDim.x * blockIdx.x + threadIdx.x;
global_thread_y = blockDim.y * blockIdx.y + threadIdx.y;
i_start = global_thread_x * thread_work;
j_start = global_thread_y * thread_work;
i_final = global_thread_x * (thread_work + 1);
j_final = global_thread_y * (thread_work + 1);
if (step < (int)(MAX_TIME / TIME_STEP) / 2){
// Pulse source
for (i = i_start; i < i_final; i++){
for (j = j_start; j < j_final; j++){
if (is_source_gpu(i, j, radius, 1, src_x, src_y))
uc_gpu[i * line_length + j] = amp * fabs(sin(step * M_PI/4));
}
}
} else if (source_active){
for (i = i_start; i < i_final; i++) {
for (j = j_start; j < j_final; j++) {
if (is_source_gpu(i, j, radius, source_active, src_x, src_y)) {
ua_gpu[i * line_length + j] = 0;
ub_gpu[i * line_length + j] = 0;
uc_gpu[i * line_length + j] = 0;
}
}
}
}
// All threads should reach this point before setting source_active.
// Option 1: need a thread barrier here -> not done, I chose option 2
// Option 2: simply write 2 kernels and syncCPU -> done, I chose this option
// CPU is setting source_active = 0 after this kernel is done executing.
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ int is_source_gpu(int i, int j, int radius, int source_active, int src_x, int src_y)
{
if (!source_active)
return 0;
if (sqrt(pow((float)(src_x - i), 2) + pow((float)(src_y - j), 2)) <= radius)
return 1;
return 0;
}
__global__ void wireless_src_pulse_kernel(int step, double amp, double MAX_TIME, double TIME_STEP, int radius, int source_active, int src_x, int src_y, double *ua_gpu, double *ub_gpu, double *uc_gpu)
{
int i, j;
int i_start, j_start;
int i_final, j_final;
int line_length;
int global_thread_x, global_thread_y;
int thread_work = 32;
line_length = gridDim.y * blockDim.y;
global_thread_x = blockDim.x * blockIdx.x + threadIdx.x;
global_thread_y = blockDim.y * blockIdx.y + threadIdx.y;
i_start = global_thread_x * thread_work;
j_start = global_thread_y * thread_work;
i_final = global_thread_x * (thread_work + 1);
j_final = global_thread_y * (thread_work + 1);
if (step < (int)(MAX_TIME / TIME_STEP) / 2){
// Pulse source
for (i = i_start; i < i_final; i++){
for (j = j_start; j < j_final; j++){
if (is_source_gpu(i, j, radius, 1, src_x, src_y))
uc_gpu[i * line_length + j] = amp * fabs(sin(step * M_PI/4));
}
}
} else if (source_active){
for (i = i_start; i < i_final; i++) {
for (j = j_start; j < j_final; j++) {
if (is_source_gpu(i, j, radius, source_active, src_x, src_y)) {
ua_gpu[i * line_length + j] = 0;
ub_gpu[i * line_length + j] = 0;
uc_gpu[i * line_length + j] = 0;
}
}
}
}
// All threads should reach this point before setting source_active.
// Option 1: need a thread barrier here -> not done, I chose option 2
// Option 2: simply write 2 kernels and syncCPU -> done, I chose this option
// CPU is setting source_active = 0 after this kernel is done executing.
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ int is_source_gpu(int i, int j, int radius, int source_active, int src_x, int src_y)
{
if (!source_active)
return 0;
if (sqrt(pow((float)(src_x - i), 2) + pow((float)(src_y - j), 2)) <= radius)
return 1;
return 0;
}
__global__ void wireless_src_pulse_kernel(int step, double amp, double MAX_TIME, double TIME_STEP, int radius, int source_active, int src_x, int src_y, double *ua_gpu, double *ub_gpu, double *uc_gpu)
{
int i, j;
int i_start, j_start;
int i_final, j_final;
int line_length;
int global_thread_x, global_thread_y;
int thread_work = 32;
line_length = gridDim.y * blockDim.y;
global_thread_x = blockDim.x * blockIdx.x + threadIdx.x;
global_thread_y = blockDim.y * blockIdx.y + threadIdx.y;
i_start = global_thread_x * thread_work;
j_start = global_thread_y * thread_work;
i_final = global_thread_x * (thread_work + 1);
j_final = global_thread_y * (thread_work + 1);
if (step < (int)(MAX_TIME / TIME_STEP) / 2){
// Pulse source
for (i = i_start; i < i_final; i++){
for (j = j_start; j < j_final; j++){
if (is_source_gpu(i, j, radius, 1, src_x, src_y))
uc_gpu[i * line_length + j] = amp * fabs(sin(step * M_PI/4));
}
}
} else if (source_active){
for (i = i_start; i < i_final; i++) {
for (j = j_start; j < j_final; j++) {
if (is_source_gpu(i, j, radius, source_active, src_x, src_y)) {
ua_gpu[i * line_length + j] = 0;
ub_gpu[i * line_length + j] = 0;
uc_gpu[i * line_length + j] = 0;
}
}
}
}
// All threads should reach this point before setting source_active.
// Option 1: need a thread barrier here -> not done, I chose option 2
// Option 2: simply write 2 kernels and syncCPU -> done, I chose this option
// CPU is setting source_active = 0 after this kernel is done executing.
} | .text
.file "wireless_src_pulse_kernel.hip"
.globl _Z40__device_stub__wireless_src_pulse_kernelidddiiiiPdS_S_ # -- Begin function _Z40__device_stub__wireless_src_pulse_kernelidddiiiiPdS_S_
.p2align 4, 0x90
.type _Z40__device_stub__wireless_src_pulse_kernelidddiiiiPdS_S_,@function
_Z40__device_stub__wireless_src_pulse_kernelidddiiiiPdS_S_: # @_Z40__device_stub__wireless_src_pulse_kernelidddiiiiPdS_S_
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 28(%rsp)
movsd %xmm0, 104(%rsp)
movsd %xmm1, 96(%rsp)
movsd %xmm2, 88(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %r9, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 104(%rsp), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 80(%rsp), %rax
movq %rax, 176(%rsp)
leaq 208(%rsp), %rax
movq %rax, 184(%rsp)
leaq 216(%rsp), %rax
movq %rax, 192(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z25wireless_src_pulse_kernelidddiiiiPdS_S_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z40__device_stub__wireless_src_pulse_kernelidddiiiiPdS_S_, .Lfunc_end0-_Z40__device_stub__wireless_src_pulse_kernelidddiiiiPdS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25wireless_src_pulse_kernelidddiiiiPdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25wireless_src_pulse_kernelidddiiiiPdS_S_,@object # @_Z25wireless_src_pulse_kernelidddiiiiPdS_S_
.section .rodata,"a",@progbits
.globl _Z25wireless_src_pulse_kernelidddiiiiPdS_S_
.p2align 3, 0x0
_Z25wireless_src_pulse_kernelidddiiiiPdS_S_:
.quad _Z40__device_stub__wireless_src_pulse_kernelidddiiiiPdS_S_
.size _Z25wireless_src_pulse_kernelidddiiiiPdS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25wireless_src_pulse_kernelidddiiiiPdS_S_"
.size .L__unnamed_1, 44
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__wireless_src_pulse_kernelidddiiiiPdS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25wireless_src_pulse_kernelidddiiiiPdS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00007c81_00000000-6_wireless_src_pulse_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13is_source_gpuiiiiii
.type _Z13is_source_gpuiiiiii, @function
_Z13is_source_gpuiiiiii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z13is_source_gpuiiiiii, .-_Z13is_source_gpuiiiiii
.globl _Z57__device_stub__Z25wireless_src_pulse_kernelidddiiiiPdS_S_idddiiiiPdS_S_
.type _Z57__device_stub__Z25wireless_src_pulse_kernelidddiiiiPdS_S_idddiiiiPdS_S_, @function
_Z57__device_stub__Z25wireless_src_pulse_kernelidddiiiiPdS_S_idddiiiiPdS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movl %edi, 76(%rsp)
movsd %xmm0, 64(%rsp)
movsd %xmm1, 56(%rsp)
movsd %xmm2, 48(%rsp)
movl %esi, 72(%rsp)
movl %edx, 44(%rsp)
movl %ecx, 40(%rsp)
movl %r8d, 36(%rsp)
movq %r9, 24(%rsp)
movq 256(%rsp), %rax
movq %rax, 16(%rsp)
movq 264(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 76(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 72(%rsp), %rax
movq %rax, 176(%rsp)
leaq 44(%rsp), %rax
movq %rax, 184(%rsp)
leaq 40(%rsp), %rax
movq %rax, 192(%rsp)
leaq 36(%rsp), %rax
movq %rax, 200(%rsp)
leaq 24(%rsp), %rax
movq %rax, 208(%rsp)
leaq 16(%rsp), %rax
movq %rax, 216(%rsp)
leaq 8(%rsp), %rax
movq %rax, 224(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 264
pushq 88(%rsp)
.cfi_def_cfa_offset 272
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z25wireless_src_pulse_kernelidddiiiiPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z57__device_stub__Z25wireless_src_pulse_kernelidddiiiiPdS_S_idddiiiiPdS_S_, .-_Z57__device_stub__Z25wireless_src_pulse_kernelidddiiiiPdS_S_idddiiiiPdS_S_
.globl _Z25wireless_src_pulse_kernelidddiiiiPdS_S_
.type _Z25wireless_src_pulse_kernelidddiiiiPdS_S_, @function
_Z25wireless_src_pulse_kernelidddiiiiPdS_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z57__device_stub__Z25wireless_src_pulse_kernelidddiiiiPdS_S_idddiiiiPdS_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z25wireless_src_pulse_kernelidddiiiiPdS_S_, .-_Z25wireless_src_pulse_kernelidddiiiiPdS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z25wireless_src_pulse_kernelidddiiiiPdS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z25wireless_src_pulse_kernelidddiiiiPdS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "wireless_src_pulse_kernel.hip"
.globl _Z40__device_stub__wireless_src_pulse_kernelidddiiiiPdS_S_ # -- Begin function _Z40__device_stub__wireless_src_pulse_kernelidddiiiiPdS_S_
.p2align 4, 0x90
.type _Z40__device_stub__wireless_src_pulse_kernelidddiiiiPdS_S_,@function
_Z40__device_stub__wireless_src_pulse_kernelidddiiiiPdS_S_: # @_Z40__device_stub__wireless_src_pulse_kernelidddiiiiPdS_S_
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 28(%rsp)
movsd %xmm0, 104(%rsp)
movsd %xmm1, 96(%rsp)
movsd %xmm2, 88(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %r9, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 104(%rsp), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 80(%rsp), %rax
movq %rax, 176(%rsp)
leaq 208(%rsp), %rax
movq %rax, 184(%rsp)
leaq 216(%rsp), %rax
movq %rax, 192(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z25wireless_src_pulse_kernelidddiiiiPdS_S_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end0:
.size _Z40__device_stub__wireless_src_pulse_kernelidddiiiiPdS_S_, .Lfunc_end0-_Z40__device_stub__wireless_src_pulse_kernelidddiiiiPdS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25wireless_src_pulse_kernelidddiiiiPdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25wireless_src_pulse_kernelidddiiiiPdS_S_,@object # @_Z25wireless_src_pulse_kernelidddiiiiPdS_S_
.section .rodata,"a",@progbits
.globl _Z25wireless_src_pulse_kernelidddiiiiPdS_S_
.p2align 3, 0x0
_Z25wireless_src_pulse_kernelidddiiiiPdS_S_:
.quad _Z40__device_stub__wireless_src_pulse_kernelidddiiiiPdS_S_
.size _Z25wireless_src_pulse_kernelidddiiiiPdS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25wireless_src_pulse_kernelidddiiiiPdS_S_"
.size .L__unnamed_1, 44
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__wireless_src_pulse_kernelidddiiiiPdS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25wireless_src_pulse_kernelidddiiiiPdS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/count.h>
#include <thrust/device_vector.h>
#include <iostream>
int main(int argc, char* argv[]) {
// put three 1s in a device_vector
thrust::device_vector<int> vec(5,0);
vec[1] = 1;
vec[3] = 1;
vec[4] = 1;
// count the 1s
int result = thrust::count(vec.begin(), vec.end(), 1);
// result is three
std::cout << result << std::endl;
return 0;
} | #include <hip/hip_runtime.h>
#include <thrust/count.h>
#include <thrust/device_vector.h>
#include <iostream>
int main(int argc, char* argv[]) {
// put three 1s in a device_vector
thrust::device_vector<int> vec(5,0);
vec[1] = 1;
vec[3] = 1;
vec[4] = 1;
// count the 1s
int result = thrust::count(vec.begin(), vec.end(), 1);
// result is three
std::cout << result << std::endl;
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
using namespace std;
static void HandleError( cudaError_t err,
const char *file,
int line ) {
if (err != cudaSuccess) {
cout << cudaGetErrorString(err)
<< file << line << endl;
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
int main( void ) {
cudaDeviceProp prop;
int dev;
HANDLE_ERROR( cudaGetDevice( &dev ) );
printf( "ID of current CUDA device: %d\n", dev );
memset( &prop, 0, sizeof( cudaDeviceProp ) );
prop.major = 1;
prop.minor = 3;
HANDLE_ERROR( cudaChooseDevice( &dev, &prop ) );
printf( "ID of CUDA device closest to revision 1.3: %d\n", dev );
HANDLE_ERROR( cudaSetDevice( dev ) );
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
using namespace std;
static void HandleError( cudaError_t err,
const char *file,
int line ) {
if (err != cudaSuccess) {
cout << cudaGetErrorString(err)
<< file << line << endl;
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
int main( void ) {
cudaDeviceProp prop;
int dev;
HANDLE_ERROR( cudaGetDevice( &dev ) );
printf( "ID of current CUDA device: %d\n", dev );
memset( &prop, 0, sizeof( cudaDeviceProp ) );
prop.major = 1;
prop.minor = 3;
HANDLE_ERROR( cudaChooseDevice( &dev, &prop ) );
printf( "ID of CUDA device closest to revision 1.3: %d\n", dev );
HANDLE_ERROR( cudaSetDevice( dev ) );
} | .file "tmpxft_00111042_00000000-6_select_set_gpu.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL11HandleError9cudaErrorPKci, @function
_ZL11HandleError9cudaErrorPKci:
.LFB3669:
.cfi_startproc
testl %edi, %edi
jne .L6
ret
.L6:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbp
movl %edx, %ebx
call cudaGetErrorString@PLT
movq %rax, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _ZL11HandleError9cudaErrorPKci, .-_ZL11HandleError9cudaErrorPKci
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/SPLURGE831/practice/master/codes/multiParrel/cuda/select_set_gpu.cu"
.align 8
.LC1:
.string "ID of current CUDA device: %d\n"
.align 8
.LC2:
.string "ID of CUDA device closest to revision 1.3: %d\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1064, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rbp
movq %rbp, %rdi
call cudaGetDevice@PLT
movl %eax, %edi
movl $20, %edx
leaq .LC0(%rip), %rbx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movl 12(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rsi
movl $129, %ecx
movl $0, %eax
movq %rsi, %rdi
rep stosq
movl $1, 376(%rsp)
movl $3, 380(%rsp)
movq %rbp, %rdi
call cudaChooseDevice@PLT
movl %eax, %edi
movl $26, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movl 12(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rsp), %edi
call cudaSetDevice@PLT
movl %eax, %edi
movl $29, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L12
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
using namespace std;
static void HandleError( cudaError_t err,
const char *file,
int line ) {
if (err != cudaSuccess) {
cout << cudaGetErrorString(err)
<< file << line << endl;
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
int main( void ) {
cudaDeviceProp prop;
int dev;
HANDLE_ERROR( cudaGetDevice( &dev ) );
printf( "ID of current CUDA device: %d\n", dev );
memset( &prop, 0, sizeof( cudaDeviceProp ) );
prop.major = 1;
prop.minor = 3;
HANDLE_ERROR( cudaChooseDevice( &dev, &prop ) );
printf( "ID of CUDA device closest to revision 1.3: %d\n", dev );
HANDLE_ERROR( cudaSetDevice( dev ) );
} | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
static void HandleError( hipError_t err,
const char *file,
int line ) {
if (err != hipSuccess) {
cout << hipGetErrorString(err)
<< file << line << endl;
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
int main( void ) {
hipDeviceProp_t prop;
int dev;
HANDLE_ERROR( hipGetDevice( &dev ) );
printf( "ID of current CUDA device: %d\n", dev );
memset( &prop, 0, sizeof( hipDeviceProp_t ) );
prop.major = 1;
prop.minor = 3;
HANDLE_ERROR( hipChooseDevice( &dev, &prop ) );
printf( "ID of CUDA device closest to revision 1.3: %d\n", dev );
HANDLE_ERROR( hipSetDevice( dev ) );
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
static void HandleError( hipError_t err,
const char *file,
int line ) {
if (err != hipSuccess) {
cout << hipGetErrorString(err)
<< file << line << endl;
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
int main( void ) {
hipDeviceProp_t prop;
int dev;
HANDLE_ERROR( hipGetDevice( &dev ) );
printf( "ID of current CUDA device: %d\n", dev );
memset( &prop, 0, sizeof( hipDeviceProp_t ) );
prop.major = 1;
prop.minor = 3;
HANDLE_ERROR( hipChooseDevice( &dev, &prop ) );
printf( "ID of CUDA device closest to revision 1.3: %d\n", dev );
HANDLE_ERROR( hipSetDevice( dev ) );
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
static void HandleError( hipError_t err,
const char *file,
int line ) {
if (err != hipSuccess) {
cout << hipGetErrorString(err)
<< file << line << endl;
exit( EXIT_FAILURE );
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
int main( void ) {
hipDeviceProp_t prop;
int dev;
HANDLE_ERROR( hipGetDevice( &dev ) );
printf( "ID of current CUDA device: %d\n", dev );
memset( &prop, 0, sizeof( hipDeviceProp_t ) );
prop.major = 1;
prop.minor = 3;
HANDLE_ERROR( hipChooseDevice( &dev, &prop ) );
printf( "ID of CUDA device closest to revision 1.3: %d\n", dev );
HANDLE_ERROR( hipSetDevice( dev ) );
} | .text
.file "select_set_gpu.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -16
leaq 12(%rsp), %rdi
callq hipGetDevice
testl %eax, %eax
jne .LBB0_1
# %bb.3: # %_ZL11HandleError10hipError_tPKci.exit
movl 12(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
leaq 16(%rsp), %rbx
movl $1472, %edx # imm = 0x5C0
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
movabsq $12884901889, %rax # imm = 0x300000001
movq %rax, 376(%rsp)
leaq 12(%rsp), %rdi
movq %rbx, %rsi
callq hipChooseDeviceR0600
testl %eax, %eax
jne .LBB0_4
# %bb.5: # %_ZL11HandleError10hipError_tPKci.exit2
movl 12(%rsp), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl 12(%rsp), %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB0_6
# %bb.7: # %_ZL11HandleError10hipError_tPKci.exit4
xorl %eax, %eax
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_1:
.cfi_def_cfa_offset 1504
movl %eax, %edi
callq hipGetErrorString
movl $_ZSt4cout, %edi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $22, %esi
jmp .LBB0_2
.LBB0_4:
movl %eax, %edi
callq hipGetErrorString
movl $_ZSt4cout, %edi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $28, %esi
jmp .LBB0_2
.LBB0_6:
movl %eax, %edi
callq hipGetErrorString
movl $_ZSt4cout, %edi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $31, %esi
.LBB0_2:
callq _ZNSolsEi
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/SPLURGE831/practice/master/codes/multiParrel/cuda/select_set_gpu.hip"
.size .L.str, 126
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "ID of current CUDA device: %d\n"
.size .L.str.1, 32
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ID of CUDA device closest to revision 1.3: %d\n"
.size .L.str.2, 48
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00111042_00000000-6_select_set_gpu.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL11HandleError9cudaErrorPKci, @function
_ZL11HandleError9cudaErrorPKci:
.LFB3669:
.cfi_startproc
testl %edi, %edi
jne .L6
ret
.L6:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbp
movl %edx, %ebx
call cudaGetErrorString@PLT
movq %rax, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _ZL11HandleError9cudaErrorPKci, .-_ZL11HandleError9cudaErrorPKci
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/SPLURGE831/practice/master/codes/multiParrel/cuda/select_set_gpu.cu"
.align 8
.LC1:
.string "ID of current CUDA device: %d\n"
.align 8
.LC2:
.string "ID of CUDA device closest to revision 1.3: %d\n"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1064, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rbp
movq %rbp, %rdi
call cudaGetDevice@PLT
movl %eax, %edi
movl $20, %edx
leaq .LC0(%rip), %rbx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movl 12(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rsi
movl $129, %ecx
movl $0, %eax
movq %rsi, %rdi
rep stosq
movl $1, 376(%rsp)
movl $3, 380(%rsp)
movq %rbp, %rdi
call cudaChooseDevice@PLT
movl %eax, %edi
movl $26, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movl 12(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rsp), %edi
call cudaSetDevice@PLT
movl %eax, %edi
movl $29, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L12
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "select_set_gpu.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -16
leaq 12(%rsp), %rdi
callq hipGetDevice
testl %eax, %eax
jne .LBB0_1
# %bb.3: # %_ZL11HandleError10hipError_tPKci.exit
movl 12(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
leaq 16(%rsp), %rbx
movl $1472, %edx # imm = 0x5C0
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
movabsq $12884901889, %rax # imm = 0x300000001
movq %rax, 376(%rsp)
leaq 12(%rsp), %rdi
movq %rbx, %rsi
callq hipChooseDeviceR0600
testl %eax, %eax
jne .LBB0_4
# %bb.5: # %_ZL11HandleError10hipError_tPKci.exit2
movl 12(%rsp), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl 12(%rsp), %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB0_6
# %bb.7: # %_ZL11HandleError10hipError_tPKci.exit4
xorl %eax, %eax
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_1:
.cfi_def_cfa_offset 1504
movl %eax, %edi
callq hipGetErrorString
movl $_ZSt4cout, %edi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $22, %esi
jmp .LBB0_2
.LBB0_4:
movl %eax, %edi
callq hipGetErrorString
movl $_ZSt4cout, %edi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $28, %esi
jmp .LBB0_2
.LBB0_6:
movl %eax, %edi
callq hipGetErrorString
movl $_ZSt4cout, %edi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $31, %esi
.LBB0_2:
callq _ZNSolsEi
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/SPLURGE831/practice/master/codes/multiParrel/cuda/select_set_gpu.hip"
.size .L.str, 126
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "ID of current CUDA device: %d\n"
.size .L.str.1, 32
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ID of CUDA device closest to revision 1.3: %d\n"
.size .L.str.2, 48
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //----------------------------------------------------------------------
/*!\file gpu_algorithmsn/BasicComplexMath.cu
*
* \author Felix Laufer
*
*
* CUDA: Output methods for debugging
*
*/
//----------------------------------------------------------------------
#include <math.h>
#include <cufft.h>
#include <stdio.h>
namespace gpu_algorithms
{
namespace cuda
{
typedef cufftComplex Complex;
typedef cufftReal Real;
// Convert real data stream to complex data stream
static __global__ void Real2Complex(const Real *idata, Complex *odata, const unsigned int stream_size)
{
const unsigned int numThreads = blockDim.x * gridDim.x;
const unsigned int threadID = blockIdx.x * blockDim.x + threadIdx.x;
for (unsigned int i = threadID; i < stream_size; i += numThreads)
{
odata[i].x = idata[i];
odata[i].y = 0.0f;
}
}
// Convert complex data stream to real data stream
static __global__ void Complex2Real(const Complex *idata, Real *odata, const unsigned int stream_size)
{
const unsigned int numThreads = blockDim.x * gridDim.x;
const unsigned int threadID = blockIdx.x * blockDim.x + threadIdx.x;
for (unsigned int i = threadID; i < stream_size; i += numThreads)
{
odata[i] = idata[i].x;
}
}
// Print a real data stream located in host memory in matrix form
static __host__ void PrintHostMatrix(const Real* idata, const unsigned int nx, const unsigned ny)
{
for(unsigned int i = 0; i < nx * ny; ++i)
{
printf("%10.8lf ", idata[i]);
if ((i+1) % nx == 0)
{
printf("%s\n", "");
}
}
printf("%s\n", "-----------------------------------------------");
}
// Print a complex data stream located in device memory in matrix form
static __host__ void PrintDeviceComplexMatrix(const Complex* idata, const unsigned int nx, const unsigned int ny)
{
unsigned int stream_size = nx * ny;
unsigned int stream_size_real = stream_size * sizeof(Real);
Real* result;
cudaMalloc((void**)&result, stream_size_real);
const dim3 grid(ceil(stream_size / 256.0f));
const dim3 block(256.0f);
Complex2Real<<<grid, block>>>(idata, result, stream_size);
Real* result_host = new Real[stream_size];
cudaMemcpy(result_host, result, stream_size_real, cudaMemcpyDeviceToHost);
PrintHostMatrix(result_host, nx, ny);
cudaFree(result);
delete result_host;
}
// Print a complex real stream located in device memory in matrix form
static __host__ void PrintDeviceRealMatrix(const Real* idata, const unsigned int nx, const unsigned int ny)
{
unsigned int stream_size = nx * ny;
unsigned int stream_size_real = stream_size * sizeof(Real);
Real* result_host = new Real[stream_size];
cudaMemcpy(result_host, idata, stream_size_real, cudaMemcpyDeviceToHost);
PrintHostMatrix(result_host, nx, ny);
delete result_host;
}
}
} | code for sm_80
Function : _ZN14gpu_algorithms4cuda12Complex2RealEPK6float2Pfj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0003 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fe40000000f00 */
/*00b0*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x000fc60000000f00 */
/*00c0*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0005 */
/*00d0*/ IMAD R0, R7, c[0x0][0xc], R0 ; /* 0x0000030007007a24 */
/* 0x000fca00078e0200 */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06070 */
/*00f0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0041d8000c101904 */
/*0100*/ @!P0 BRA 0x70 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN14gpu_algorithms4cuda12Real2ComplexEPKfP6float2j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0080*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0003 */
/*0090*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x001ea2000c1e1900 */
/*00a0*/ MOV R5, 0x8 ; /* 0x0000000800057802 */
/* 0x000fe20000000f00 */
/*00b0*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*00c0*/ MOV R9, c[0x0][0x0] ; /* 0x0000000000097a02 */
/* 0x000fc60000000f00 */
/*00d0*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0005 */
/*00e0*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06070 */
/*0100*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x0041d8000c101b04 */
/*0110*/ @!P0 BRA 0x70 ; /* 0xffffff5000008947 */
/* 0x000fea000383ffff */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //----------------------------------------------------------------------
/*!\file gpu_algorithmsn/BasicComplexMath.cu
*
* \author Felix Laufer
*
*
* CUDA: Output methods for debugging
*
*/
//----------------------------------------------------------------------
#include <math.h>
#include <cufft.h>
#include <stdio.h>
namespace gpu_algorithms
{
namespace cuda
{
typedef cufftComplex Complex;
typedef cufftReal Real;
// Convert real data stream to complex data stream
static __global__ void Real2Complex(const Real *idata, Complex *odata, const unsigned int stream_size)
{
const unsigned int numThreads = blockDim.x * gridDim.x;
const unsigned int threadID = blockIdx.x * blockDim.x + threadIdx.x;
for (unsigned int i = threadID; i < stream_size; i += numThreads)
{
odata[i].x = idata[i];
odata[i].y = 0.0f;
}
}
// Convert complex data stream to real data stream
static __global__ void Complex2Real(const Complex *idata, Real *odata, const unsigned int stream_size)
{
const unsigned int numThreads = blockDim.x * gridDim.x;
const unsigned int threadID = blockIdx.x * blockDim.x + threadIdx.x;
for (unsigned int i = threadID; i < stream_size; i += numThreads)
{
odata[i] = idata[i].x;
}
}
// Print a real data stream located in host memory in matrix form
static __host__ void PrintHostMatrix(const Real* idata, const unsigned int nx, const unsigned ny)
{
for(unsigned int i = 0; i < nx * ny; ++i)
{
printf("%10.8lf ", idata[i]);
if ((i+1) % nx == 0)
{
printf("%s\n", "");
}
}
printf("%s\n", "-----------------------------------------------");
}
// Print a complex data stream located in device memory in matrix form
static __host__ void PrintDeviceComplexMatrix(const Complex* idata, const unsigned int nx, const unsigned int ny)
{
unsigned int stream_size = nx * ny;
unsigned int stream_size_real = stream_size * sizeof(Real);
Real* result;
cudaMalloc((void**)&result, stream_size_real);
const dim3 grid(ceil(stream_size / 256.0f));
const dim3 block(256.0f);
Complex2Real<<<grid, block>>>(idata, result, stream_size);
Real* result_host = new Real[stream_size];
cudaMemcpy(result_host, result, stream_size_real, cudaMemcpyDeviceToHost);
PrintHostMatrix(result_host, nx, ny);
cudaFree(result);
delete result_host;
}
// Print a complex real stream located in device memory in matrix form
static __host__ void PrintDeviceRealMatrix(const Real* idata, const unsigned int nx, const unsigned int ny)
{
unsigned int stream_size = nx * ny;
unsigned int stream_size_real = stream_size * sizeof(Real);
Real* result_host = new Real[stream_size];
cudaMemcpy(result_host, idata, stream_size_real, cudaMemcpyDeviceToHost);
PrintHostMatrix(result_host, nx, ny);
delete result_host;
}
}
} | .file "tmpxft_000498b3_00000000-6_debugPrint.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZN14gpu_algorithms4cudaL12Real2ComplexEPKfP6float2j, @function
_ZN14gpu_algorithms4cudaL12Real2ComplexEPKfP6float2j:
.LFB2108:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
movq %rsi, 24(%rsp)
movl %edx, 12(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZN14gpu_algorithms4cudaL12Real2ComplexEPKfP6float2j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2108:
.size _ZN14gpu_algorithms4cudaL12Real2ComplexEPKfP6float2j, .-_ZN14gpu_algorithms4cudaL12Real2ComplexEPKfP6float2j
.type _ZN14gpu_algorithms4cudaL12Complex2RealEPK6float2Pfj, @function
_ZN14gpu_algorithms4cudaL12Complex2RealEPK6float2Pfj:
.LFB2110:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
movq %rsi, 24(%rsp)
movl %edx, 12(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZN14gpu_algorithms4cudaL12Complex2RealEPK6float2Pfj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2110:
.size _ZN14gpu_algorithms4cudaL12Complex2RealEPK6float2Pfj, .-_ZN14gpu_algorithms4cudaL12Complex2RealEPK6float2Pfj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_ZN14gpu_algorithms4cuda12Complex2RealEPK6float2Pfj"
.align 8
.LC1:
.string "_ZN14gpu_algorithms4cuda12Real2ComplexEPKfP6float2j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2112:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZN14gpu_algorithms4cudaL12Complex2RealEPK6float2Pfj(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZN14gpu_algorithms4cudaL12Real2ComplexEPKfP6float2j(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2112:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //----------------------------------------------------------------------
/*!\file gpu_algorithmsn/BasicComplexMath.cu
*
* \author Felix Laufer
*
*
* CUDA: Output methods for debugging
*
*/
//----------------------------------------------------------------------
#include <math.h>
#include <cufft.h>
#include <stdio.h>
namespace gpu_algorithms
{
namespace cuda
{
typedef cufftComplex Complex;
typedef cufftReal Real;
// Convert real data stream to complex data stream
static __global__ void Real2Complex(const Real *idata, Complex *odata, const unsigned int stream_size)
{
const unsigned int numThreads = blockDim.x * gridDim.x;
const unsigned int threadID = blockIdx.x * blockDim.x + threadIdx.x;
for (unsigned int i = threadID; i < stream_size; i += numThreads)
{
odata[i].x = idata[i];
odata[i].y = 0.0f;
}
}
// Convert complex data stream to real data stream
static __global__ void Complex2Real(const Complex *idata, Real *odata, const unsigned int stream_size)
{
const unsigned int numThreads = blockDim.x * gridDim.x;
const unsigned int threadID = blockIdx.x * blockDim.x + threadIdx.x;
for (unsigned int i = threadID; i < stream_size; i += numThreads)
{
odata[i] = idata[i].x;
}
}
// Print a real data stream located in host memory in matrix form
static __host__ void PrintHostMatrix(const Real* idata, const unsigned int nx, const unsigned ny)
{
for(unsigned int i = 0; i < nx * ny; ++i)
{
printf("%10.8lf ", idata[i]);
if ((i+1) % nx == 0)
{
printf("%s\n", "");
}
}
printf("%s\n", "-----------------------------------------------");
}
// Print a complex data stream located in device memory in matrix form
static __host__ void PrintDeviceComplexMatrix(const Complex* idata, const unsigned int nx, const unsigned int ny)
{
unsigned int stream_size = nx * ny;
unsigned int stream_size_real = stream_size * sizeof(Real);
Real* result;
cudaMalloc((void**)&result, stream_size_real);
const dim3 grid(ceil(stream_size / 256.0f));
const dim3 block(256.0f);
Complex2Real<<<grid, block>>>(idata, result, stream_size);
Real* result_host = new Real[stream_size];
cudaMemcpy(result_host, result, stream_size_real, cudaMemcpyDeviceToHost);
PrintHostMatrix(result_host, nx, ny);
cudaFree(result);
delete result_host;
}
// Print a complex real stream located in device memory in matrix form
static __host__ void PrintDeviceRealMatrix(const Real* idata, const unsigned int nx, const unsigned int ny)
{
unsigned int stream_size = nx * ny;
unsigned int stream_size_real = stream_size * sizeof(Real);
Real* result_host = new Real[stream_size];
cudaMemcpy(result_host, idata, stream_size_real, cudaMemcpyDeviceToHost);
PrintHostMatrix(result_host, nx, ny);
delete result_host;
}
}
} | //----------------------------------------------------------------------
/*!\file gpu_algorithmsn/BasicComplexMath.cu
*
* \author Felix Laufer
*
*
* CUDA: Output methods for debugging
*
*/
//----------------------------------------------------------------------
#include <hip/hip_runtime.h>
#include <math.h>
#include <hipfft/hipfft.h>
#include <stdio.h>
namespace gpu_algorithms
{
namespace cuda
{
typedef hipfftComplex Complex;
typedef hipfftReal Real;
// Convert real data stream to complex data stream
static __global__ void Real2Complex(const Real *idata, Complex *odata, const unsigned int stream_size)
{
const unsigned int numThreads = blockDim.x * gridDim.x;
const unsigned int threadID = blockIdx.x * blockDim.x + threadIdx.x;
for (unsigned int i = threadID; i < stream_size; i += numThreads)
{
odata[i].x = idata[i];
odata[i].y = 0.0f;
}
}
// Convert complex data stream to real data stream
static __global__ void Complex2Real(const Complex *idata, Real *odata, const unsigned int stream_size)
{
const unsigned int numThreads = blockDim.x * gridDim.x;
const unsigned int threadID = blockIdx.x * blockDim.x + threadIdx.x;
for (unsigned int i = threadID; i < stream_size; i += numThreads)
{
odata[i] = idata[i].x;
}
}
// Print a real data stream located in host memory in matrix form
static __host__ void PrintHostMatrix(const Real* idata, const unsigned int nx, const unsigned ny)
{
for(unsigned int i = 0; i < nx * ny; ++i)
{
printf("%10.8lf ", idata[i]);
if ((i+1) % nx == 0)
{
printf("%s\n", "");
}
}
printf("%s\n", "-----------------------------------------------");
}
// Print a complex data stream located in device memory in matrix form
static __host__ void PrintDeviceComplexMatrix(const Complex* idata, const unsigned int nx, const unsigned int ny)
{
unsigned int stream_size = nx * ny;
unsigned int stream_size_real = stream_size * sizeof(Real);
Real* result;
hipMalloc((void**)&result, stream_size_real);
const dim3 grid(ceil(stream_size / 256.0f));
const dim3 block(256.0f);
Complex2Real<<<grid, block>>>(idata, result, stream_size);
Real* result_host = new Real[stream_size];
hipMemcpy(result_host, result, stream_size_real, hipMemcpyDeviceToHost);
PrintHostMatrix(result_host, nx, ny);
hipFree(result);
delete result_host;
}
// Print a complex real stream located in device memory in matrix form
static __host__ void PrintDeviceRealMatrix(const Real* idata, const unsigned int nx, const unsigned int ny)
{
unsigned int stream_size = nx * ny;
unsigned int stream_size_real = stream_size * sizeof(Real);
Real* result_host = new Real[stream_size];
hipMemcpy(result_host, idata, stream_size_real, hipMemcpyDeviceToHost);
PrintHostMatrix(result_host, nx, ny);
delete result_host;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //----------------------------------------------------------------------
/*!\file gpu_algorithmsn/BasicComplexMath.cu
*
* \author Felix Laufer
*
*
* CUDA: Output methods for debugging
*
*/
//----------------------------------------------------------------------
#include <hip/hip_runtime.h>
#include <math.h>
#include <hipfft/hipfft.h>
#include <stdio.h>
namespace gpu_algorithms
{
namespace cuda
{
typedef hipfftComplex Complex;
typedef hipfftReal Real;
// Convert real data stream to complex data stream
static __global__ void Real2Complex(const Real *idata, Complex *odata, const unsigned int stream_size)
{
const unsigned int numThreads = blockDim.x * gridDim.x;
const unsigned int threadID = blockIdx.x * blockDim.x + threadIdx.x;
for (unsigned int i = threadID; i < stream_size; i += numThreads)
{
odata[i].x = idata[i];
odata[i].y = 0.0f;
}
}
// Convert complex data stream to real data stream
static __global__ void Complex2Real(const Complex *idata, Real *odata, const unsigned int stream_size)
{
const unsigned int numThreads = blockDim.x * gridDim.x;
const unsigned int threadID = blockIdx.x * blockDim.x + threadIdx.x;
for (unsigned int i = threadID; i < stream_size; i += numThreads)
{
odata[i] = idata[i].x;
}
}
// Print a real data stream located in host memory in matrix form
static __host__ void PrintHostMatrix(const Real* idata, const unsigned int nx, const unsigned ny)
{
for(unsigned int i = 0; i < nx * ny; ++i)
{
printf("%10.8lf ", idata[i]);
if ((i+1) % nx == 0)
{
printf("%s\n", "");
}
}
printf("%s\n", "-----------------------------------------------");
}
// Print a complex data stream located in device memory in matrix form
static __host__ void PrintDeviceComplexMatrix(const Complex* idata, const unsigned int nx, const unsigned int ny)
{
unsigned int stream_size = nx * ny;
unsigned int stream_size_real = stream_size * sizeof(Real);
Real* result;
hipMalloc((void**)&result, stream_size_real);
const dim3 grid(ceil(stream_size / 256.0f));
const dim3 block(256.0f);
Complex2Real<<<grid, block>>>(idata, result, stream_size);
Real* result_host = new Real[stream_size];
hipMemcpy(result_host, result, stream_size_real, hipMemcpyDeviceToHost);
PrintHostMatrix(result_host, nx, ny);
hipFree(result);
delete result_host;
}
// Print a complex real stream located in device memory in matrix form
static __host__ void PrintDeviceRealMatrix(const Real* idata, const unsigned int nx, const unsigned int ny)
{
unsigned int stream_size = nx * ny;
unsigned int stream_size_real = stream_size * sizeof(Real);
Real* result_host = new Real[stream_size];
hipMemcpy(result_host, idata, stream_size_real, hipMemcpyDeviceToHost);
PrintHostMatrix(result_host, nx, ny);
delete result_host;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN14gpu_algorithms4cudaL12Real2ComplexEPKfP15HIP_vector_typeIfLj2EEj,"axG",@progbits,_ZN14gpu_algorithms4cudaL12Real2ComplexEPKfP15HIP_vector_typeIfLj2EEj,comdat
.globl _ZN14gpu_algorithms4cudaL12Real2ComplexEPKfP15HIP_vector_typeIfLj2EEj
.p2align 8
.type _ZN14gpu_algorithms4cudaL12Real2ComplexEPKfP15HIP_vector_typeIfLj2EEj,@function
_ZN14gpu_algorithms4cudaL12Real2ComplexEPKfP15HIP_vector_typeIfLj2EEj:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s8, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s2, s9
s_mov_b32 s2, 0
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_lshlrev_b64 v[5:6], 3, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v5, s0, s6, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s0, s7, v6, s0
global_load_b32 v3, v[3:4], off
v_mov_b32_e32 v4, v2
v_cmp_le_u32_e32 vcc_lo, s8, v1
s_or_b32 s2, vcc_lo, s2
s_waitcnt vmcnt(0)
global_store_b64 v[5:6], v[3:4], off
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN14gpu_algorithms4cudaL12Real2ComplexEPKfP15HIP_vector_typeIfLj2EEj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN14gpu_algorithms4cudaL12Real2ComplexEPKfP15HIP_vector_typeIfLj2EEj,"axG",@progbits,_ZN14gpu_algorithms4cudaL12Real2ComplexEPKfP15HIP_vector_typeIfLj2EEj,comdat
.Lfunc_end0:
.size _ZN14gpu_algorithms4cudaL12Real2ComplexEPKfP15HIP_vector_typeIfLj2EEj, .Lfunc_end0-_ZN14gpu_algorithms4cudaL12Real2ComplexEPKfP15HIP_vector_typeIfLj2EEj
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN14gpu_algorithms4cudaL12Complex2RealEPK15HIP_vector_typeIfLj2EEPfj,"axG",@progbits,_ZN14gpu_algorithms4cudaL12Complex2RealEPK15HIP_vector_typeIfLj2EEPfj,comdat
.globl _ZN14gpu_algorithms4cudaL12Complex2RealEPK15HIP_vector_typeIfLj2EEPfj
.p2align 8
.type _ZN14gpu_algorithms4cudaL12Complex2RealEPK15HIP_vector_typeIfLj2EEPfj,@function
_ZN14gpu_algorithms4cudaL12Complex2RealEPK15HIP_vector_typeIfLj2EEPfj:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s8, v1
s_cbranch_execz .LBB1_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s2, s9
s_mov_b32 s2, 0
.p2align 6
.LBB1_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v0, v[3:4], off
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_cmp_le_u32_e32 vcc_lo, s8, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s0, s6, v3
v_add_co_ci_u32_e64 v4, s0, s7, v4, s0
s_or_b32 s2, vcc_lo, s2
s_waitcnt vmcnt(0)
global_store_b32 v[3:4], v0, off
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN14gpu_algorithms4cudaL12Complex2RealEPK15HIP_vector_typeIfLj2EEPfj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN14gpu_algorithms4cudaL12Complex2RealEPK15HIP_vector_typeIfLj2EEPfj,"axG",@progbits,_ZN14gpu_algorithms4cudaL12Complex2RealEPK15HIP_vector_typeIfLj2EEPfj,comdat
.Lfunc_end1:
.size _ZN14gpu_algorithms4cudaL12Complex2RealEPK15HIP_vector_typeIfLj2EEPfj, .Lfunc_end1-_ZN14gpu_algorithms4cudaL12Complex2RealEPK15HIP_vector_typeIfLj2EEPfj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
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- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
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- 0
.max_flat_workgroup_size: 1024
.name: _ZN14gpu_algorithms4cudaL12Real2ComplexEPKfP15HIP_vector_typeIfLj2EEj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN14gpu_algorithms4cudaL12Real2ComplexEPKfP15HIP_vector_typeIfLj2EEj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
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.value_kind: global_buffer
- .address_space: global
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.size: 8
.value_kind: global_buffer
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.vgpr_spill_count: 0
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.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //----------------------------------------------------------------------
/*!\file gpu_algorithmsn/BasicComplexMath.cu
*
* \author Felix Laufer
*
*
* CUDA: Output methods for debugging
*
*/
//----------------------------------------------------------------------
#include <hip/hip_runtime.h>
#include <math.h>
#include <hipfft/hipfft.h>
#include <stdio.h>
namespace gpu_algorithms
{
namespace cuda
{
typedef hipfftComplex Complex;
typedef hipfftReal Real;
// Convert real data stream to complex data stream
static __global__ void Real2Complex(const Real *idata, Complex *odata, const unsigned int stream_size)
{
const unsigned int numThreads = blockDim.x * gridDim.x;
const unsigned int threadID = blockIdx.x * blockDim.x + threadIdx.x;
for (unsigned int i = threadID; i < stream_size; i += numThreads)
{
odata[i].x = idata[i];
odata[i].y = 0.0f;
}
}
// Convert complex data stream to real data stream
static __global__ void Complex2Real(const Complex *idata, Real *odata, const unsigned int stream_size)
{
const unsigned int numThreads = blockDim.x * gridDim.x;
const unsigned int threadID = blockIdx.x * blockDim.x + threadIdx.x;
for (unsigned int i = threadID; i < stream_size; i += numThreads)
{
odata[i] = idata[i].x;
}
}
// Print a real data stream located in host memory in matrix form
static __host__ void PrintHostMatrix(const Real* idata, const unsigned int nx, const unsigned ny)
{
for(unsigned int i = 0; i < nx * ny; ++i)
{
printf("%10.8lf ", idata[i]);
if ((i+1) % nx == 0)
{
printf("%s\n", "");
}
}
printf("%s\n", "-----------------------------------------------");
}
// Print a complex data stream located in device memory in matrix form
static __host__ void PrintDeviceComplexMatrix(const Complex* idata, const unsigned int nx, const unsigned int ny)
{
unsigned int stream_size = nx * ny;
unsigned int stream_size_real = stream_size * sizeof(Real);
Real* result;
hipMalloc((void**)&result, stream_size_real);
const dim3 grid(ceil(stream_size / 256.0f));
const dim3 block(256.0f);
Complex2Real<<<grid, block>>>(idata, result, stream_size);
Real* result_host = new Real[stream_size];
hipMemcpy(result_host, result, stream_size_real, hipMemcpyDeviceToHost);
PrintHostMatrix(result_host, nx, ny);
hipFree(result);
delete result_host;
}
// Print a complex real stream located in device memory in matrix form
static __host__ void PrintDeviceRealMatrix(const Real* idata, const unsigned int nx, const unsigned int ny)
{
unsigned int stream_size = nx * ny;
unsigned int stream_size_real = stream_size * sizeof(Real);
Real* result_host = new Real[stream_size];
hipMemcpy(result_host, idata, stream_size_real, hipMemcpyDeviceToHost);
PrintHostMatrix(result_host, nx, ny);
delete result_host;
}
}
} | .text
.file "debugPrint.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN14gpu_algorithms4cuda12Complex2RealEPK6float2Pfj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0003 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fe40000000f00 */
/*00b0*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x000fc60000000f00 */
/*00c0*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0005 */
/*00d0*/ IMAD R0, R7, c[0x0][0xc], R0 ; /* 0x0000030007007a24 */
/* 0x000fca00078e0200 */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06070 */
/*00f0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0041d8000c101904 */
/*0100*/ @!P0 BRA 0x70 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN14gpu_algorithms4cuda12Real2ComplexEPKfP6float2j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0080*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0003 */
/*0090*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x001ea2000c1e1900 */
/*00a0*/ MOV R5, 0x8 ; /* 0x0000000800057802 */
/* 0x000fe20000000f00 */
/*00b0*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*00c0*/ MOV R9, c[0x0][0x0] ; /* 0x0000000000097a02 */
/* 0x000fc60000000f00 */
/*00d0*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0005 */
/*00e0*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06070 */
/*0100*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x0041d8000c101b04 */
/*0110*/ @!P0 BRA 0x70 ; /* 0xffffff5000008947 */
/* 0x000fea000383ffff */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN14gpu_algorithms4cudaL12Real2ComplexEPKfP15HIP_vector_typeIfLj2EEj,"axG",@progbits,_ZN14gpu_algorithms4cudaL12Real2ComplexEPKfP15HIP_vector_typeIfLj2EEj,comdat
.globl _ZN14gpu_algorithms4cudaL12Real2ComplexEPKfP15HIP_vector_typeIfLj2EEj
.p2align 8
.type _ZN14gpu_algorithms4cudaL12Real2ComplexEPKfP15HIP_vector_typeIfLj2EEj,@function
_ZN14gpu_algorithms4cudaL12Real2ComplexEPKfP15HIP_vector_typeIfLj2EEj:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s8, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s2, s9
s_mov_b32 s2, 0
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_lshlrev_b64 v[5:6], 3, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v5, s0, s6, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s0, s7, v6, s0
global_load_b32 v3, v[3:4], off
v_mov_b32_e32 v4, v2
v_cmp_le_u32_e32 vcc_lo, s8, v1
s_or_b32 s2, vcc_lo, s2
s_waitcnt vmcnt(0)
global_store_b64 v[5:6], v[3:4], off
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN14gpu_algorithms4cudaL12Real2ComplexEPKfP15HIP_vector_typeIfLj2EEj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN14gpu_algorithms4cudaL12Real2ComplexEPKfP15HIP_vector_typeIfLj2EEj,"axG",@progbits,_ZN14gpu_algorithms4cudaL12Real2ComplexEPKfP15HIP_vector_typeIfLj2EEj,comdat
.Lfunc_end0:
.size _ZN14gpu_algorithms4cudaL12Real2ComplexEPKfP15HIP_vector_typeIfLj2EEj, .Lfunc_end0-_ZN14gpu_algorithms4cudaL12Real2ComplexEPKfP15HIP_vector_typeIfLj2EEj
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN14gpu_algorithms4cudaL12Complex2RealEPK15HIP_vector_typeIfLj2EEPfj,"axG",@progbits,_ZN14gpu_algorithms4cudaL12Complex2RealEPK15HIP_vector_typeIfLj2EEPfj,comdat
.globl _ZN14gpu_algorithms4cudaL12Complex2RealEPK15HIP_vector_typeIfLj2EEPfj
.p2align 8
.type _ZN14gpu_algorithms4cudaL12Complex2RealEPK15HIP_vector_typeIfLj2EEPfj,@function
_ZN14gpu_algorithms4cudaL12Complex2RealEPK15HIP_vector_typeIfLj2EEPfj:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s8, v1
s_cbranch_execz .LBB1_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s2, s9
s_mov_b32 s2, 0
.p2align 6
.LBB1_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v0, v[3:4], off
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_cmp_le_u32_e32 vcc_lo, s8, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s0, s6, v3
v_add_co_ci_u32_e64 v4, s0, s7, v4, s0
s_or_b32 s2, vcc_lo, s2
s_waitcnt vmcnt(0)
global_store_b32 v[3:4], v0, off
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN14gpu_algorithms4cudaL12Complex2RealEPK15HIP_vector_typeIfLj2EEPfj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN14gpu_algorithms4cudaL12Complex2RealEPK15HIP_vector_typeIfLj2EEPfj,"axG",@progbits,_ZN14gpu_algorithms4cudaL12Complex2RealEPK15HIP_vector_typeIfLj2EEPfj,comdat
.Lfunc_end1:
.size _ZN14gpu_algorithms4cudaL12Complex2RealEPK15HIP_vector_typeIfLj2EEPfj, .Lfunc_end1-_ZN14gpu_algorithms4cudaL12Complex2RealEPK15HIP_vector_typeIfLj2EEPfj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZN14gpu_algorithms4cudaL12Real2ComplexEPKfP15HIP_vector_typeIfLj2EEj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN14gpu_algorithms4cudaL12Real2ComplexEPKfP15HIP_vector_typeIfLj2EEj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZN14gpu_algorithms4cudaL12Complex2RealEPK15HIP_vector_typeIfLj2EEPfj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN14gpu_algorithms4cudaL12Complex2RealEPK15HIP_vector_typeIfLj2EEPfj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000498b3_00000000-6_debugPrint.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZN14gpu_algorithms4cudaL12Real2ComplexEPKfP6float2j, @function
_ZN14gpu_algorithms4cudaL12Real2ComplexEPKfP6float2j:
.LFB2108:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
movq %rsi, 24(%rsp)
movl %edx, 12(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZN14gpu_algorithms4cudaL12Real2ComplexEPKfP6float2j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2108:
.size _ZN14gpu_algorithms4cudaL12Real2ComplexEPKfP6float2j, .-_ZN14gpu_algorithms4cudaL12Real2ComplexEPKfP6float2j
.type _ZN14gpu_algorithms4cudaL12Complex2RealEPK6float2Pfj, @function
_ZN14gpu_algorithms4cudaL12Complex2RealEPK6float2Pfj:
.LFB2110:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
movq %rsi, 24(%rsp)
movl %edx, 12(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZN14gpu_algorithms4cudaL12Complex2RealEPK6float2Pfj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2110:
.size _ZN14gpu_algorithms4cudaL12Complex2RealEPK6float2Pfj, .-_ZN14gpu_algorithms4cudaL12Complex2RealEPK6float2Pfj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_ZN14gpu_algorithms4cuda12Complex2RealEPK6float2Pfj"
.align 8
.LC1:
.string "_ZN14gpu_algorithms4cuda12Real2ComplexEPKfP6float2j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2112:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZN14gpu_algorithms4cudaL12Complex2RealEPK6float2Pfj(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZN14gpu_algorithms4cudaL12Real2ComplexEPKfP6float2j(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2112:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "debugPrint.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
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