system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<iostream>
using namespace std;
//programs ran on GPU, called device
//func itself is a kernel
//global identifier indicates func ran on device, not host
//main code -> compiled via host, kernel code -> compiled via device
__global__ void add(int a, int b, int *c) {
*c = a + b;
}
//programs run on CPU, called host
int main(void) {
//invoke code from host
//angled brackets indicate args to runtime, influence how code executes on GPU
//local host int c
int c;
//create device ptr which creates mem via cudaMalloc
int *dev_c;
//allocate device memory via cudaMalloc, first arg = ptr to ptr that holds new mem addr, second arg = size mem
//cast as addr of pointer to int c as void double ptr
//handle error micro to return error code if exists
//cudaMalloc returns ptr to mem, cannot use this ptr to read from or write to memory from code that executes on host
//CAN pass mem ptr to func exec on device, or to read/write to device, and to func that execute on host
//important error, C compiler won't notify
//cannot deref dev_c
hipMalloc ( (void**)&dev_c, sizeof(int) );
//run kernel call, pass ptr for device to use
add<<<1,1>>>(2, 7, dev_c);
//copy block of memory at address of ptr c inside device, to local int c inside host
//number of bytes copied indicated by sizeof(int), and define type of copy is to host
hipMemcpy(&c, dev_c, sizeof(int), hipMemcpyDeviceToHost);
printf("2 + 7 = %d\n", c);
hipFree(dev_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiiPi
.globl _Z3addiiPi
.p2align 8
.type _Z3addiiPi,@function
_Z3addiiPi:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiiPi, .Lfunc_end0-_Z3addiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiiPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z3addiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<iostream>
using namespace std;
//programs ran on GPU, called device
//func itself is a kernel
//global identifier indicates func ran on device, not host
//main code -> compiled via host, kernel code -> compiled via device
__global__ void add(int a, int b, int *c) {
*c = a + b;
}
//programs run on CPU, called host
int main(void) {
//invoke code from host
//angled brackets indicate args to runtime, influence how code executes on GPU
//local host int c
int c;
//create device ptr which creates mem via cudaMalloc
int *dev_c;
//allocate device memory via cudaMalloc, first arg = ptr to ptr that holds new mem addr, second arg = size mem
//cast as addr of pointer to int c as void double ptr
//handle error micro to return error code if exists
//cudaMalloc returns ptr to mem, cannot use this ptr to read from or write to memory from code that executes on host
//CAN pass mem ptr to func exec on device, or to read/write to device, and to func that execute on host
//important error, C compiler won't notify
//cannot deref dev_c
hipMalloc ( (void**)&dev_c, sizeof(int) );
//run kernel call, pass ptr for device to use
add<<<1,1>>>(2, 7, dev_c);
//copy block of memory at address of ptr c inside device, to local int c inside host
//number of bytes copied indicated by sizeof(int), and define type of copy is to host
hipMemcpy(&c, dev_c, sizeof(int), hipMemcpyDeviceToHost);
printf("2 + 7 = %d\n", c);
hipFree(dev_c);
return 0;
} | .text
.file "intro.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addiiPi # -- Begin function _Z18__device_stub__addiiPi
.p2align 4, 0x90
.type _Z18__device_stub__addiiPi,@function
_Z18__device_stub__addiiPi: # @_Z18__device_stub__addiiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__addiiPi, .Lfunc_end0-_Z18__device_stub__addiiPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rax
movl $2, 12(%rsp)
movl $7, 8(%rsp)
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 8(%rsp), %rax
movq %rax, 24(%rsp)
leaq 96(%rsp), %rax
movq %rax, 32(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z3addiiPi, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
leaq 16(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 16(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiiPi,@object # @_Z3addiiPi
.section .rodata,"a",@progbits
.globl _Z3addiiPi
.p2align 3, 0x0
_Z3addiiPi:
.quad _Z18__device_stub__addiiPi
.size _Z3addiiPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "2 + 7 = %d\n"
.size .L.str, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addiiPi"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe40000000f00 */
/*0050*/ IADD3 R5, R5, c[0x0][0x160], RZ ; /* 0x0000580005057a10 */
/* 0x000fca0007ffe0ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiiPi
.globl _Z3addiiPi
.p2align 8
.type _Z3addiiPi,@function
_Z3addiiPi:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiiPi, .Lfunc_end0-_Z3addiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiiPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z3addiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008a683_00000000-6_intro.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3addiiPiiiPi
.type _Z24__device_stub__Z3addiiPiiiPi, @function
_Z24__device_stub__Z3addiiPiiiPi:
.LFB3694:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z24__device_stub__Z3addiiPiiiPi, .-_Z24__device_stub__Z3addiiPiiiPi
.globl _Z3addiiPi
.type _Z3addiiPi, @function
_Z3addiiPi:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3addiiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3addiiPi, .-_Z3addiiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "2 + 7 = %d\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 28(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
movl 28(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdx
movl $7, %esi
movl $2, %edi
call _Z24__device_stub__Z3addiiPiiiPi
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "intro.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addiiPi # -- Begin function _Z18__device_stub__addiiPi
.p2align 4, 0x90
.type _Z18__device_stub__addiiPi,@function
_Z18__device_stub__addiiPi: # @_Z18__device_stub__addiiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__addiiPi, .Lfunc_end0-_Z18__device_stub__addiiPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rax
movl $2, 12(%rsp)
movl $7, 8(%rsp)
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 8(%rsp), %rax
movq %rax, 24(%rsp)
leaq 96(%rsp), %rax
movq %rax, 32(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z3addiiPi, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
leaq 16(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 16(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiiPi,@object # @_Z3addiiPi
.section .rodata,"a",@progbits
.globl _Z3addiiPi
.p2align 3, 0x0
_Z3addiiPi:
.quad _Z18__device_stub__addiiPi
.size _Z3addiiPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "2 + 7 = %d\n"
.size .L.str, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addiiPi"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kernel_End(int *g_stochastic, int *g_count_blocks, int *g_counter)
{
int thid = blockIdx.x * blockDim.x + threadIdx.x;
if (thid < (*g_counter))
{
if (g_stochastic[thid] == 1)
atomicAdd(g_count_blocks, 1);
//(*g_count_blocks) = (*g_count_blocks) + 1 ;
}
} | code for sm_80
Function : _Z10kernel_EndPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0050*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0060*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0080*/ ISETP.GE.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x004fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0203 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00d0*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x004fda0003f05270 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000e220000000000 */
/*0100*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe200038e0100 */
/*0110*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0120*/ UFLO.U32 UR7, UR6 ; /* 0x00000006000772bd */
/* 0x000fe200080e0000 */
/*0130*/ POPC R5, UR6 ; /* 0x0000000600057d09 */
/* 0x000e620008000000 */
/*0140*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fc80000000f00 */
/*0150*/ ISETP.EQ.U32.AND P0, PT, R0, UR7, PT ; /* 0x0000000700007c0c */
/* 0x001fda000bf02070 */
/*0160*/ @P0 RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200098e */
/* 0x002fe2000c10e184 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kernel_End(int *g_stochastic, int *g_count_blocks, int *g_counter)
{
int thid = blockIdx.x * blockDim.x + threadIdx.x;
if (thid < (*g_counter))
{
if (g_stochastic[thid] == 1)
atomicAdd(g_count_blocks, 1);
//(*g_count_blocks) = (*g_count_blocks) + 1 ;
}
} | .file "tmpxft_0003423c_00000000-6_kernel_End.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10kernel_EndPiS_S_PiS_S_
.type _Z34__device_stub__Z10kernel_EndPiS_S_PiS_S_, @function
_Z34__device_stub__Z10kernel_EndPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10kernel_EndPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z10kernel_EndPiS_S_PiS_S_, .-_Z34__device_stub__Z10kernel_EndPiS_S_PiS_S_
.globl _Z10kernel_EndPiS_S_
.type _Z10kernel_EndPiS_S_, @function
_Z10kernel_EndPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10kernel_EndPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10kernel_EndPiS_S_, .-_Z10kernel_EndPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10kernel_EndPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10kernel_EndPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kernel_End(int *g_stochastic, int *g_count_blocks, int *g_counter)
{
int thid = blockIdx.x * blockDim.x + threadIdx.x;
if (thid < (*g_counter))
{
if (g_stochastic[thid] == 1)
atomicAdd(g_count_blocks, 1);
//(*g_count_blocks) = (*g_count_blocks) + 1 ;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_End(int *g_stochastic, int *g_count_blocks, int *g_counter)
{
int thid = blockIdx.x * blockDim.x + threadIdx.x;
if (thid < (*g_counter))
{
if (g_stochastic[thid] == 1)
atomicAdd(g_count_blocks, 1);
//(*g_count_blocks) = (*g_count_blocks) + 1 ;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_End(int *g_stochastic, int *g_count_blocks, int *g_counter)
{
int thid = blockIdx.x * blockDim.x + threadIdx.x;
if (thid < (*g_counter))
{
if (g_stochastic[thid] == 1)
atomicAdd(g_count_blocks, 1);
//(*g_count_blocks) = (*g_count_blocks) + 1 ;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10kernel_EndPiS_S_
.globl _Z10kernel_EndPiS_S_
.p2align 8
.type _Z10kernel_EndPiS_S_,@function
_Z10kernel_EndPiS_S_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s4, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[2:3], 0x0
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 1, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_4
s_mov_b32 s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v0, s2, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 s3, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s3
s_cbranch_execz .LBB0_4
s_load_b64 s[0:1], s[0:1], 0x8
s_bcnt1_i32_b32 s2, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10kernel_EndPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10kernel_EndPiS_S_, .Lfunc_end0-_Z10kernel_EndPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10kernel_EndPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10kernel_EndPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_End(int *g_stochastic, int *g_count_blocks, int *g_counter)
{
int thid = blockIdx.x * blockDim.x + threadIdx.x;
if (thid < (*g_counter))
{
if (g_stochastic[thid] == 1)
atomicAdd(g_count_blocks, 1);
//(*g_count_blocks) = (*g_count_blocks) + 1 ;
}
} | .text
.file "kernel_End.hip"
.globl _Z25__device_stub__kernel_EndPiS_S_ # -- Begin function _Z25__device_stub__kernel_EndPiS_S_
.p2align 4, 0x90
.type _Z25__device_stub__kernel_EndPiS_S_,@function
_Z25__device_stub__kernel_EndPiS_S_: # @_Z25__device_stub__kernel_EndPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10kernel_EndPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__kernel_EndPiS_S_, .Lfunc_end0-_Z25__device_stub__kernel_EndPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10kernel_EndPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10kernel_EndPiS_S_,@object # @_Z10kernel_EndPiS_S_
.section .rodata,"a",@progbits
.globl _Z10kernel_EndPiS_S_
.p2align 3, 0x0
_Z10kernel_EndPiS_S_:
.quad _Z25__device_stub__kernel_EndPiS_S_
.size _Z10kernel_EndPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10kernel_EndPiS_S_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__kernel_EndPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10kernel_EndPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10kernel_EndPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0050*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0060*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0080*/ ISETP.GE.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x004fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0203 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00d0*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x004fda0003f05270 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000e220000000000 */
/*0100*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe200038e0100 */
/*0110*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0120*/ UFLO.U32 UR7, UR6 ; /* 0x00000006000772bd */
/* 0x000fe200080e0000 */
/*0130*/ POPC R5, UR6 ; /* 0x0000000600057d09 */
/* 0x000e620008000000 */
/*0140*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fc80000000f00 */
/*0150*/ ISETP.EQ.U32.AND P0, PT, R0, UR7, PT ; /* 0x0000000700007c0c */
/* 0x001fda000bf02070 */
/*0160*/ @P0 RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200098e */
/* 0x002fe2000c10e184 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10kernel_EndPiS_S_
.globl _Z10kernel_EndPiS_S_
.p2align 8
.type _Z10kernel_EndPiS_S_,@function
_Z10kernel_EndPiS_S_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s4, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[2:3], 0x0
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 1, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_4
s_mov_b32 s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v0, s2, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 s3, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s3
s_cbranch_execz .LBB0_4
s_load_b64 s[0:1], s[0:1], 0x8
s_bcnt1_i32_b32 s2, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10kernel_EndPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10kernel_EndPiS_S_, .Lfunc_end0-_Z10kernel_EndPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10kernel_EndPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10kernel_EndPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003423c_00000000-6_kernel_End.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10kernel_EndPiS_S_PiS_S_
.type _Z34__device_stub__Z10kernel_EndPiS_S_PiS_S_, @function
_Z34__device_stub__Z10kernel_EndPiS_S_PiS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10kernel_EndPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z10kernel_EndPiS_S_PiS_S_, .-_Z34__device_stub__Z10kernel_EndPiS_S_PiS_S_
.globl _Z10kernel_EndPiS_S_
.type _Z10kernel_EndPiS_S_, @function
_Z10kernel_EndPiS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10kernel_EndPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10kernel_EndPiS_S_, .-_Z10kernel_EndPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10kernel_EndPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10kernel_EndPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel_End.hip"
.globl _Z25__device_stub__kernel_EndPiS_S_ # -- Begin function _Z25__device_stub__kernel_EndPiS_S_
.p2align 4, 0x90
.type _Z25__device_stub__kernel_EndPiS_S_,@function
_Z25__device_stub__kernel_EndPiS_S_: # @_Z25__device_stub__kernel_EndPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10kernel_EndPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__kernel_EndPiS_S_, .Lfunc_end0-_Z25__device_stub__kernel_EndPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10kernel_EndPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10kernel_EndPiS_S_,@object # @_Z10kernel_EndPiS_S_
.section .rodata,"a",@progbits
.globl _Z10kernel_EndPiS_S_
.p2align 3, 0x0
_Z10kernel_EndPiS_S_:
.quad _Z25__device_stub__kernel_EndPiS_S_
.size _Z10kernel_EndPiS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10kernel_EndPiS_S_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__kernel_EndPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10kernel_EndPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h> // for calloc();
#include <assert.h> // ensure successfull allocation
#include <stdbool.h> // bool variables
#include <stdio.h> // printf...
#include <string.h>
#include <dirent.h> // Directory management
#include <sys/stat.h> // system commands ?
#include <sys/types.h> // Extra types of variables, google it
#include <unistd.h> // standard symbolic constants and types
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////// 1D array allocators /////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
// This function creates a 1D Array (vector) :: INT
// It returns a pointer
int *Create1DArrayInt(int length)
{
int *MyArray;
MyArray = (int *)calloc(length,sizeof(int));
assert(MyArray != NULL);
return MyArray;
}
// This function creates a 1D Array (vector) :: FLOAT
// It returns a pointer
float *Create1DArrayFloat(int length)
{
float *MyArray;
MyArray = (float *)calloc(length,sizeof(float));
assert(MyArray != NULL);
return MyArray;
}
// This function creates a 1D Array (vector) :: DOUBLE
// It returns a pointer
double *Create1DArrayDouble(int length)
{
double *MyArray;
MyArray = (double *)calloc(length,sizeof(double));
assert(MyArray != NULL);
return MyArray;
}
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////// 2D array allocators /////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
// This function creates a 2D Array (matrix) :: FLOAT
// It returns a pointer
int **Create2DArrayInt(int width, int height)
{
int **MyMatrix;
int i;
MyMatrix = (int **)calloc(height,sizeof(int*));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
MyMatrix[i] = (int *)calloc(width,sizeof(int));
assert(MyMatrix != NULL);
return MyMatrix;
}
// This function creates a 2D Array (matrix) :: FLOAT
// It returns a pointer
float **Create2DArrayFloat(int width, int height)
{
float **MyMatrix;
int i;
MyMatrix = (float **)calloc(height,sizeof(float*));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
MyMatrix[i] = (float *)calloc(width,sizeof(float));
assert(MyMatrix != NULL);
return MyMatrix;
}
// This function creates a 2D Array (matrix) :: DOUBLE
// It returns a pointer
double **Create2DArrayDouble(int width, int height)
{
double **MyMatrix;
int i;
MyMatrix = (double **)calloc(height,sizeof(double*));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
MyMatrix[i] = (double *)calloc(width,sizeof(double));
assert(MyMatrix != NULL);
return MyMatrix;
}
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////// 3D array allocators /////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
// This function creates a 3D Array (matrix of vectors) :: INT
// It returns a pointer
int ***Create3DArrayInt(int width, int height, int depth)
{
int ***MyMatrix;
int i, j, k;
MyMatrix = (int ***)calloc(height,sizeof(int**));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
{
MyMatrix[i] = (int **)calloc(width,sizeof(int*));
assert(MyMatrix != NULL);
for (j = 0; j < width; j++)
{
MyMatrix[i][j] = (int *)calloc(depth,sizeof(int));
assert(MyMatrix != NULL);
for (k = 0; k < depth; k++)
MyMatrix[i][j][k] = 0;
}
}
return MyMatrix;
}
// This function creates a 3D Array (matrix of vectors) :: FLOAT
// It returns a pointer
float ***Create3DArrayFloat(int width, int height, int depth)
{
float ***MyMatrix;
int i, j, k;
MyMatrix = (float ***)calloc(height,sizeof(float**));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
{
MyMatrix[i] = (float **)calloc(width,sizeof(float*));
assert(MyMatrix != NULL);
for (j = 0; j < width; j++)
{
MyMatrix[i][j] = (float *)calloc(depth,sizeof(float));
assert(MyMatrix != NULL);
for (k = 0; k < depth; k++)
MyMatrix[i][j][k] = 0;
}
}
return MyMatrix;
}
// This function creates a 3D Array (matrix of vectors) :: DOUBLE
// It returns a pointer
double ***Create3DArrayDouble(int width, int height, int depth)
{
double ***MyMatrix;
int i, j, k;
MyMatrix = (double ***)calloc(height,sizeof(double**));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
{
MyMatrix[i] = (double **)calloc(width,sizeof(double*));
assert(MyMatrix != NULL);
for (j = 0; j < width; j++)
{
MyMatrix[i][j] = (double *)calloc(depth,sizeof(double));
assert(MyMatrix != NULL);
for (k = 0; k < depth; k++)
MyMatrix[i][j][k] = 0;
}
}
return MyMatrix;
}
// This function creates a 3D Array (matrix of vectors) :: DOUBLE
// It returns a pointer
bool ***Create3DArrayBool(int width, int height, int depth)
{
bool ***MyMatrix;
int i, j, k;
MyMatrix = (bool ***)calloc(height,sizeof(bool**));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
{
MyMatrix[i] = (bool **)calloc(width,sizeof(bool*));
assert(MyMatrix != NULL);
for (j = 0; j < width; j++)
{
MyMatrix[i][j] = (bool *)calloc(depth,sizeof(bool));
assert(MyMatrix != NULL);
for (k = 0; k < depth; k++)
MyMatrix[i][j][k] = 0;
}
}
return MyMatrix;
}
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
//////////////////////////// Create directory ///////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
void CreateDirectory(char* MainWorkDir)
{
// Create the working directory, exit if it already exist!
DIR *MyDirVar;
MyDirVar = opendir (MainWorkDir); // Open the following directory
if (MyDirVar != NULL) // if dp equals to NULL dir does not exist
{
//printf("Directory %s already exist, move on.\n", MainWorkDir);
}
else
{
mkdir(MainWorkDir, S_IRWXU|S_IRGRP|S_IXGRP); // Create the directiory
//printf("Directory does not exist yet... creating: %s\n", MainWorkDir);
}
}
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////////// Add string //////////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
void StringAddition(char* first, char* second, char* result)
{
strcat(result, first);
strcat(result, second);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h> // for calloc();
#include <assert.h> // ensure successfull allocation
#include <stdbool.h> // bool variables
#include <stdio.h> // printf...
#include <string.h>
#include <dirent.h> // Directory management
#include <sys/stat.h> // system commands ?
#include <sys/types.h> // Extra types of variables, google it
#include <unistd.h> // standard symbolic constants and types
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////// 1D array allocators /////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
// This function creates a 1D Array (vector) :: INT
// It returns a pointer
int *Create1DArrayInt(int length)
{
int *MyArray;
MyArray = (int *)calloc(length,sizeof(int));
assert(MyArray != NULL);
return MyArray;
}
// This function creates a 1D Array (vector) :: FLOAT
// It returns a pointer
float *Create1DArrayFloat(int length)
{
float *MyArray;
MyArray = (float *)calloc(length,sizeof(float));
assert(MyArray != NULL);
return MyArray;
}
// This function creates a 1D Array (vector) :: DOUBLE
// It returns a pointer
double *Create1DArrayDouble(int length)
{
double *MyArray;
MyArray = (double *)calloc(length,sizeof(double));
assert(MyArray != NULL);
return MyArray;
}
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////// 2D array allocators /////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
// This function creates a 2D Array (matrix) :: FLOAT
// It returns a pointer
int **Create2DArrayInt(int width, int height)
{
int **MyMatrix;
int i;
MyMatrix = (int **)calloc(height,sizeof(int*));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
MyMatrix[i] = (int *)calloc(width,sizeof(int));
assert(MyMatrix != NULL);
return MyMatrix;
}
// This function creates a 2D Array (matrix) :: FLOAT
// It returns a pointer
float **Create2DArrayFloat(int width, int height)
{
float **MyMatrix;
int i;
MyMatrix = (float **)calloc(height,sizeof(float*));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
MyMatrix[i] = (float *)calloc(width,sizeof(float));
assert(MyMatrix != NULL);
return MyMatrix;
}
// This function creates a 2D Array (matrix) :: DOUBLE
// It returns a pointer
double **Create2DArrayDouble(int width, int height)
{
double **MyMatrix;
int i;
MyMatrix = (double **)calloc(height,sizeof(double*));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
MyMatrix[i] = (double *)calloc(width,sizeof(double));
assert(MyMatrix != NULL);
return MyMatrix;
}
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////// 3D array allocators /////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
// This function creates a 3D Array (matrix of vectors) :: INT
// It returns a pointer
int ***Create3DArrayInt(int width, int height, int depth)
{
int ***MyMatrix;
int i, j, k;
MyMatrix = (int ***)calloc(height,sizeof(int**));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
{
MyMatrix[i] = (int **)calloc(width,sizeof(int*));
assert(MyMatrix != NULL);
for (j = 0; j < width; j++)
{
MyMatrix[i][j] = (int *)calloc(depth,sizeof(int));
assert(MyMatrix != NULL);
for (k = 0; k < depth; k++)
MyMatrix[i][j][k] = 0;
}
}
return MyMatrix;
}
// This function creates a 3D Array (matrix of vectors) :: FLOAT
// It returns a pointer
float ***Create3DArrayFloat(int width, int height, int depth)
{
float ***MyMatrix;
int i, j, k;
MyMatrix = (float ***)calloc(height,sizeof(float**));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
{
MyMatrix[i] = (float **)calloc(width,sizeof(float*));
assert(MyMatrix != NULL);
for (j = 0; j < width; j++)
{
MyMatrix[i][j] = (float *)calloc(depth,sizeof(float));
assert(MyMatrix != NULL);
for (k = 0; k < depth; k++)
MyMatrix[i][j][k] = 0;
}
}
return MyMatrix;
}
// This function creates a 3D Array (matrix of vectors) :: DOUBLE
// It returns a pointer
double ***Create3DArrayDouble(int width, int height, int depth)
{
double ***MyMatrix;
int i, j, k;
MyMatrix = (double ***)calloc(height,sizeof(double**));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
{
MyMatrix[i] = (double **)calloc(width,sizeof(double*));
assert(MyMatrix != NULL);
for (j = 0; j < width; j++)
{
MyMatrix[i][j] = (double *)calloc(depth,sizeof(double));
assert(MyMatrix != NULL);
for (k = 0; k < depth; k++)
MyMatrix[i][j][k] = 0;
}
}
return MyMatrix;
}
// This function creates a 3D Array (matrix of vectors) :: DOUBLE
// It returns a pointer
bool ***Create3DArrayBool(int width, int height, int depth)
{
bool ***MyMatrix;
int i, j, k;
MyMatrix = (bool ***)calloc(height,sizeof(bool**));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
{
MyMatrix[i] = (bool **)calloc(width,sizeof(bool*));
assert(MyMatrix != NULL);
for (j = 0; j < width; j++)
{
MyMatrix[i][j] = (bool *)calloc(depth,sizeof(bool));
assert(MyMatrix != NULL);
for (k = 0; k < depth; k++)
MyMatrix[i][j][k] = 0;
}
}
return MyMatrix;
}
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
//////////////////////////// Create directory ///////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
void CreateDirectory(char* MainWorkDir)
{
// Create the working directory, exit if it already exist!
DIR *MyDirVar;
MyDirVar = opendir (MainWorkDir); // Open the following directory
if (MyDirVar != NULL) // if dp equals to NULL dir does not exist
{
//printf("Directory %s already exist, move on.\n", MainWorkDir);
}
else
{
mkdir(MainWorkDir, S_IRWXU|S_IRGRP|S_IXGRP); // Create the directiory
//printf("Directory does not exist yet... creating: %s\n", MainWorkDir);
}
}
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////////// Add string //////////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
void StringAddition(char* first, char* second, char* result)
{
strcat(result, first);
strcat(result, second);
} | .file "tmpxft_001522da_00000000-6_ShellFunctions.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16Create1DArrayInti
.type _Z16Create1DArrayInti, @function
_Z16Create1DArrayInti:
.LFB2070:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movslq %edi, %rdi
movl $4, %esi
call calloc@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2070:
.size _Z16Create1DArrayInti, .-_Z16Create1DArrayInti
.globl _Z18Create1DArrayFloati
.type _Z18Create1DArrayFloati, @function
_Z18Create1DArrayFloati:
.LFB2071:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movslq %edi, %rdi
movl $4, %esi
call calloc@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2071:
.size _Z18Create1DArrayFloati, .-_Z18Create1DArrayFloati
.globl _Z19Create1DArrayDoublei
.type _Z19Create1DArrayDoublei, @function
_Z19Create1DArrayDoublei:
.LFB2072:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movslq %edi, %rdi
movl $8, %esi
call calloc@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2072:
.size _Z19Create1DArrayDoublei, .-_Z19Create1DArrayDoublei
.globl _Z16Create2DArrayIntii
.type _Z16Create2DArrayIntii, @function
_Z16Create2DArrayIntii:
.LFB2073:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebp
movl %esi, %ebx
movslq %esi, %r12
movl $8, %esi
movq %r12, %rdi
call calloc@PLT
movq %rax, %r13
testl %ebx, %ebx
jle .L9
movq %rax, %rbx
leaq (%rax,%r12,8), %r12
movslq %ebp, %rbp
.L11:
movl $4, %esi
movq %rbp, %rdi
call calloc@PLT
movq %rax, (%rbx)
addq $8, %rbx
cmpq %r12, %rbx
jne .L11
.L9:
movq %r13, %rax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _Z16Create2DArrayIntii, .-_Z16Create2DArrayIntii
.globl _Z18Create2DArrayFloatii
.type _Z18Create2DArrayFloatii, @function
_Z18Create2DArrayFloatii:
.LFB2074:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebp
movl %esi, %ebx
movslq %esi, %r12
movl $8, %esi
movq %r12, %rdi
call calloc@PLT
movq %rax, %r13
testl %ebx, %ebx
jle .L14
movq %rax, %rbx
leaq (%rax,%r12,8), %r12
movslq %ebp, %rbp
.L16:
movl $4, %esi
movq %rbp, %rdi
call calloc@PLT
movq %rax, (%rbx)
addq $8, %rbx
cmpq %r12, %rbx
jne .L16
.L14:
movq %r13, %rax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _Z18Create2DArrayFloatii, .-_Z18Create2DArrayFloatii
.globl _Z19Create2DArrayDoubleii
.type _Z19Create2DArrayDoubleii, @function
_Z19Create2DArrayDoubleii:
.LFB2075:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebp
movl %esi, %ebx
movslq %esi, %r12
movl $8, %esi
movq %r12, %rdi
call calloc@PLT
movq %rax, %r13
testl %ebx, %ebx
jle .L19
movq %rax, %rbx
leaq (%rax,%r12,8), %r12
movslq %ebp, %rbp
.L21:
movl $8, %esi
movq %rbp, %rdi
call calloc@PLT
movq %rax, (%rbx)
addq $8, %rbx
cmpq %r12, %rbx
jne .L21
.L19:
movq %r13, %rax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2075:
.size _Z19Create2DArrayDoubleii, .-_Z19Create2DArrayDoubleii
.globl _Z16Create3DArrayIntiii
.type _Z16Create3DArrayIntiii, @function
_Z16Create3DArrayIntiii:
.LFB2076:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %edi, %r14d
movl %edi, 28(%rsp)
movl %esi, %ebx
movl %edx, %r12d
movslq %esi, %rbp
movl $8, %esi
movq %rbp, %rdi
call calloc@PLT
movq %rax, 40(%rsp)
testl %ebx, %ebx
jle .L24
movq %rax, %r15
leaq (%rax,%rbp,8), %rax
movq %rax, 16(%rsp)
movslq %r14d, %rax
movq %rax, 8(%rsp)
salq $3, %rax
movq %rax, 32(%rsp)
movslq %r12d, %r13
leaq 0(,%r13,4), %r14
.L30:
movl $8, %esi
movq 8(%rsp), %rdi
call calloc@PLT
movq %rax, (%r15)
cmpl $0, 28(%rsp)
jle .L26
movq %rax, %rbx
movq 32(%rsp), %rcx
leaq (%rax,%rcx), %rbp
.L29:
movl $4, %esi
movq %r13, %rdi
call calloc@PLT
movq %rax, (%rbx)
testl %r12d, %r12d
jle .L27
movq %rax, %rdx
addq %r14, %rax
.L28:
movl $0, (%rdx)
addq $4, %rdx
cmpq %rax, %rdx
jne .L28
.L27:
addq $8, %rbx
cmpq %rbp, %rbx
jne .L29
.L26:
addq $8, %r15
movq 16(%rsp), %rax
cmpq %rax, %r15
jne .L30
.L24:
movq 40(%rsp), %rax
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2076:
.size _Z16Create3DArrayIntiii, .-_Z16Create3DArrayIntiii
.globl _Z18Create3DArrayFloatiii
.type _Z18Create3DArrayFloatiii, @function
_Z18Create3DArrayFloatiii:
.LFB2077:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %edi, %r14d
movl %edi, 28(%rsp)
movl %esi, %ebx
movl %edx, %r12d
movslq %esi, %rbp
movl $8, %esi
movq %rbp, %rdi
call calloc@PLT
movq %rax, 40(%rsp)
testl %ebx, %ebx
jle .L35
movq %rax, %r15
leaq (%rax,%rbp,8), %rax
movq %rax, 16(%rsp)
movslq %r14d, %rax
movq %rax, 8(%rsp)
salq $3, %rax
movq %rax, 32(%rsp)
movslq %r12d, %r13
leaq 0(,%r13,4), %r14
.L41:
movl $8, %esi
movq 8(%rsp), %rdi
call calloc@PLT
movq %rax, (%r15)
cmpl $0, 28(%rsp)
jle .L37
movq %rax, %rbx
movq 32(%rsp), %rcx
leaq (%rax,%rcx), %rbp
.L40:
movl $4, %esi
movq %r13, %rdi
call calloc@PLT
movq %rax, (%rbx)
testl %r12d, %r12d
jle .L38
movq %rax, %rdx
addq %r14, %rax
.L39:
movl $0x00000000, (%rdx)
addq $4, %rdx
cmpq %rax, %rdx
jne .L39
.L38:
addq $8, %rbx
cmpq %rbp, %rbx
jne .L40
.L37:
addq $8, %r15
movq 16(%rsp), %rax
cmpq %rax, %r15
jne .L41
.L35:
movq 40(%rsp), %rax
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2077:
.size _Z18Create3DArrayFloatiii, .-_Z18Create3DArrayFloatiii
.globl _Z19Create3DArrayDoubleiii
.type _Z19Create3DArrayDoubleiii, @function
_Z19Create3DArrayDoubleiii:
.LFB2078:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %edi, %r14d
movl %edi, 28(%rsp)
movl %esi, %ebx
movl %edx, %r12d
movslq %esi, %rbp
movl $8, %esi
movq %rbp, %rdi
call calloc@PLT
movq %rax, 40(%rsp)
testl %ebx, %ebx
jle .L46
movq %rax, %r15
leaq (%rax,%rbp,8), %rax
movq %rax, 16(%rsp)
movslq %r14d, %rax
movq %rax, 8(%rsp)
salq $3, %rax
movq %rax, 32(%rsp)
movslq %r12d, %r13
leaq 0(,%r13,8), %r14
.L52:
movl $8, %esi
movq 8(%rsp), %rdi
call calloc@PLT
movq %rax, (%r15)
cmpl $0, 28(%rsp)
jle .L48
movq %rax, %rbx
movq 32(%rsp), %rcx
leaq (%rax,%rcx), %rbp
.L51:
movl $8, %esi
movq %r13, %rdi
call calloc@PLT
movq %rax, (%rbx)
testl %r12d, %r12d
jle .L49
movq %rax, %rdx
addq %r14, %rax
.L50:
movq $0x000000000, (%rdx)
addq $8, %rdx
cmpq %rax, %rdx
jne .L50
.L49:
addq $8, %rbx
cmpq %rbp, %rbx
jne .L51
.L48:
addq $8, %r15
movq 16(%rsp), %rax
cmpq %rax, %r15
jne .L52
.L46:
movq 40(%rsp), %rax
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2078:
.size _Z19Create3DArrayDoubleiii, .-_Z19Create3DArrayDoubleiii
.globl _Z17Create3DArrayBooliii
.type _Z17Create3DArrayBooliii, @function
_Z17Create3DArrayBooliii:
.LFB2079:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %r12d
movl %edi, 12(%rsp)
movl %esi, %ebx
movl %edx, %r13d
movslq %esi, %rbp
movl $8, %esi
movq %rbp, %rdi
call calloc@PLT
movq %rax, 24(%rsp)
testl %ebx, %ebx
jle .L57
movq %rax, %r14
leaq (%rax,%rbp,8), %r15
movslq %r12d, %rax
movq %rax, (%rsp)
salq $3, %rax
movq %rax, 16(%rsp)
movslq %r13d, %rbp
.L63:
movl $8, %esi
movq (%rsp), %rdi
call calloc@PLT
movq %rax, (%r14)
cmpl $0, 12(%rsp)
jle .L59
movq %rax, %rbx
movq 16(%rsp), %rcx
leaq (%rax,%rcx), %r12
.L62:
movl $1, %esi
movq %rbp, %rdi
call calloc@PLT
movq %rax, (%rbx)
testl %r13d, %r13d
jle .L60
movq %rax, %rdx
addq %rbp, %rax
.L61:
movb $0, (%rdx)
addq $1, %rdx
cmpq %rax, %rdx
jne .L61
.L60:
addq $8, %rbx
cmpq %r12, %rbx
jne .L62
.L59:
addq $8, %r14
cmpq %r15, %r14
jne .L63
.L57:
movq 24(%rsp), %rax
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2079:
.size _Z17Create3DArrayBooliii, .-_Z17Create3DArrayBooliii
.globl _Z15CreateDirectoryPc
.type _Z15CreateDirectoryPc, @function
_Z15CreateDirectoryPc:
.LFB2080:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call opendir@PLT
testq %rax, %rax
je .L71
.L68:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L71:
.cfi_restore_state
movl $488, %esi
movq %rbx, %rdi
call mkdir@PLT
jmp .L68
.cfi_endproc
.LFE2080:
.size _Z15CreateDirectoryPc, .-_Z15CreateDirectoryPc
.globl _Z14StringAdditionPcS_S_
.type _Z14StringAdditionPcS_S_, @function
_Z14StringAdditionPcS_S_:
.LFB2081:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbp
movq %rdx, %rbx
movq %rdi, %rsi
movq %rdx, %rdi
call strcat@PLT
movq %rbp, %rsi
movq %rbx, %rdi
call strcat@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2081:
.size _Z14StringAdditionPcS_S_, .-_Z14StringAdditionPcS_S_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2107:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2107:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h> // for calloc();
#include <assert.h> // ensure successfull allocation
#include <stdbool.h> // bool variables
#include <stdio.h> // printf...
#include <string.h>
#include <dirent.h> // Directory management
#include <sys/stat.h> // system commands ?
#include <sys/types.h> // Extra types of variables, google it
#include <unistd.h> // standard symbolic constants and types
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////// 1D array allocators /////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
// This function creates a 1D Array (vector) :: INT
// It returns a pointer
int *Create1DArrayInt(int length)
{
int *MyArray;
MyArray = (int *)calloc(length,sizeof(int));
assert(MyArray != NULL);
return MyArray;
}
// This function creates a 1D Array (vector) :: FLOAT
// It returns a pointer
float *Create1DArrayFloat(int length)
{
float *MyArray;
MyArray = (float *)calloc(length,sizeof(float));
assert(MyArray != NULL);
return MyArray;
}
// This function creates a 1D Array (vector) :: DOUBLE
// It returns a pointer
double *Create1DArrayDouble(int length)
{
double *MyArray;
MyArray = (double *)calloc(length,sizeof(double));
assert(MyArray != NULL);
return MyArray;
}
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////// 2D array allocators /////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
// This function creates a 2D Array (matrix) :: FLOAT
// It returns a pointer
int **Create2DArrayInt(int width, int height)
{
int **MyMatrix;
int i;
MyMatrix = (int **)calloc(height,sizeof(int*));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
MyMatrix[i] = (int *)calloc(width,sizeof(int));
assert(MyMatrix != NULL);
return MyMatrix;
}
// This function creates a 2D Array (matrix) :: FLOAT
// It returns a pointer
float **Create2DArrayFloat(int width, int height)
{
float **MyMatrix;
int i;
MyMatrix = (float **)calloc(height,sizeof(float*));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
MyMatrix[i] = (float *)calloc(width,sizeof(float));
assert(MyMatrix != NULL);
return MyMatrix;
}
// This function creates a 2D Array (matrix) :: DOUBLE
// It returns a pointer
double **Create2DArrayDouble(int width, int height)
{
double **MyMatrix;
int i;
MyMatrix = (double **)calloc(height,sizeof(double*));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
MyMatrix[i] = (double *)calloc(width,sizeof(double));
assert(MyMatrix != NULL);
return MyMatrix;
}
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////// 3D array allocators /////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
// This function creates a 3D Array (matrix of vectors) :: INT
// It returns a pointer
int ***Create3DArrayInt(int width, int height, int depth)
{
int ***MyMatrix;
int i, j, k;
MyMatrix = (int ***)calloc(height,sizeof(int**));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
{
MyMatrix[i] = (int **)calloc(width,sizeof(int*));
assert(MyMatrix != NULL);
for (j = 0; j < width; j++)
{
MyMatrix[i][j] = (int *)calloc(depth,sizeof(int));
assert(MyMatrix != NULL);
for (k = 0; k < depth; k++)
MyMatrix[i][j][k] = 0;
}
}
return MyMatrix;
}
// This function creates a 3D Array (matrix of vectors) :: FLOAT
// It returns a pointer
float ***Create3DArrayFloat(int width, int height, int depth)
{
float ***MyMatrix;
int i, j, k;
MyMatrix = (float ***)calloc(height,sizeof(float**));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
{
MyMatrix[i] = (float **)calloc(width,sizeof(float*));
assert(MyMatrix != NULL);
for (j = 0; j < width; j++)
{
MyMatrix[i][j] = (float *)calloc(depth,sizeof(float));
assert(MyMatrix != NULL);
for (k = 0; k < depth; k++)
MyMatrix[i][j][k] = 0;
}
}
return MyMatrix;
}
// This function creates a 3D Array (matrix of vectors) :: DOUBLE
// It returns a pointer
double ***Create3DArrayDouble(int width, int height, int depth)
{
double ***MyMatrix;
int i, j, k;
MyMatrix = (double ***)calloc(height,sizeof(double**));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
{
MyMatrix[i] = (double **)calloc(width,sizeof(double*));
assert(MyMatrix != NULL);
for (j = 0; j < width; j++)
{
MyMatrix[i][j] = (double *)calloc(depth,sizeof(double));
assert(MyMatrix != NULL);
for (k = 0; k < depth; k++)
MyMatrix[i][j][k] = 0;
}
}
return MyMatrix;
}
// This function creates a 3D Array (matrix of vectors) :: DOUBLE
// It returns a pointer
bool ***Create3DArrayBool(int width, int height, int depth)
{
bool ***MyMatrix;
int i, j, k;
MyMatrix = (bool ***)calloc(height,sizeof(bool**));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
{
MyMatrix[i] = (bool **)calloc(width,sizeof(bool*));
assert(MyMatrix != NULL);
for (j = 0; j < width; j++)
{
MyMatrix[i][j] = (bool *)calloc(depth,sizeof(bool));
assert(MyMatrix != NULL);
for (k = 0; k < depth; k++)
MyMatrix[i][j][k] = 0;
}
}
return MyMatrix;
}
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
//////////////////////////// Create directory ///////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
void CreateDirectory(char* MainWorkDir)
{
// Create the working directory, exit if it already exist!
DIR *MyDirVar;
MyDirVar = opendir (MainWorkDir); // Open the following directory
if (MyDirVar != NULL) // if dp equals to NULL dir does not exist
{
//printf("Directory %s already exist, move on.\n", MainWorkDir);
}
else
{
mkdir(MainWorkDir, S_IRWXU|S_IRGRP|S_IXGRP); // Create the directiory
//printf("Directory does not exist yet... creating: %s\n", MainWorkDir);
}
}
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////////// Add string //////////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
void StringAddition(char* first, char* second, char* result)
{
strcat(result, first);
strcat(result, second);
} | #include <hip/hip_runtime.h>
#include <stdlib.h> // for calloc();
#include <assert.h> // ensure successfull allocation
#include <stdbool.h> // bool variables
#include <stdio.h> // printf...
#include <string.h>
#include <dirent.h> // Directory management
#include <sys/stat.h> // system commands ?
#include <sys/types.h> // Extra types of variables, google it
#include <unistd.h> // standard symbolic constants and types
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////// 1D array allocators /////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
// This function creates a 1D Array (vector) :: INT
// It returns a pointer
int *Create1DArrayInt(int length)
{
int *MyArray;
MyArray = (int *)calloc(length,sizeof(int));
assert(MyArray != NULL);
return MyArray;
}
// This function creates a 1D Array (vector) :: FLOAT
// It returns a pointer
float *Create1DArrayFloat(int length)
{
float *MyArray;
MyArray = (float *)calloc(length,sizeof(float));
assert(MyArray != NULL);
return MyArray;
}
// This function creates a 1D Array (vector) :: DOUBLE
// It returns a pointer
double *Create1DArrayDouble(int length)
{
double *MyArray;
MyArray = (double *)calloc(length,sizeof(double));
assert(MyArray != NULL);
return MyArray;
}
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////// 2D array allocators /////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
// This function creates a 2D Array (matrix) :: FLOAT
// It returns a pointer
int **Create2DArrayInt(int width, int height)
{
int **MyMatrix;
int i;
MyMatrix = (int **)calloc(height,sizeof(int*));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
MyMatrix[i] = (int *)calloc(width,sizeof(int));
assert(MyMatrix != NULL);
return MyMatrix;
}
// This function creates a 2D Array (matrix) :: FLOAT
// It returns a pointer
float **Create2DArrayFloat(int width, int height)
{
float **MyMatrix;
int i;
MyMatrix = (float **)calloc(height,sizeof(float*));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
MyMatrix[i] = (float *)calloc(width,sizeof(float));
assert(MyMatrix != NULL);
return MyMatrix;
}
// This function creates a 2D Array (matrix) :: DOUBLE
// It returns a pointer
double **Create2DArrayDouble(int width, int height)
{
double **MyMatrix;
int i;
MyMatrix = (double **)calloc(height,sizeof(double*));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
MyMatrix[i] = (double *)calloc(width,sizeof(double));
assert(MyMatrix != NULL);
return MyMatrix;
}
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////// 3D array allocators /////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
// This function creates a 3D Array (matrix of vectors) :: INT
// It returns a pointer
int ***Create3DArrayInt(int width, int height, int depth)
{
int ***MyMatrix;
int i, j, k;
MyMatrix = (int ***)calloc(height,sizeof(int**));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
{
MyMatrix[i] = (int **)calloc(width,sizeof(int*));
assert(MyMatrix != NULL);
for (j = 0; j < width; j++)
{
MyMatrix[i][j] = (int *)calloc(depth,sizeof(int));
assert(MyMatrix != NULL);
for (k = 0; k < depth; k++)
MyMatrix[i][j][k] = 0;
}
}
return MyMatrix;
}
// This function creates a 3D Array (matrix of vectors) :: FLOAT
// It returns a pointer
float ***Create3DArrayFloat(int width, int height, int depth)
{
float ***MyMatrix;
int i, j, k;
MyMatrix = (float ***)calloc(height,sizeof(float**));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
{
MyMatrix[i] = (float **)calloc(width,sizeof(float*));
assert(MyMatrix != NULL);
for (j = 0; j < width; j++)
{
MyMatrix[i][j] = (float *)calloc(depth,sizeof(float));
assert(MyMatrix != NULL);
for (k = 0; k < depth; k++)
MyMatrix[i][j][k] = 0;
}
}
return MyMatrix;
}
// This function creates a 3D Array (matrix of vectors) :: DOUBLE
// It returns a pointer
double ***Create3DArrayDouble(int width, int height, int depth)
{
double ***MyMatrix;
int i, j, k;
MyMatrix = (double ***)calloc(height,sizeof(double**));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
{
MyMatrix[i] = (double **)calloc(width,sizeof(double*));
assert(MyMatrix != NULL);
for (j = 0; j < width; j++)
{
MyMatrix[i][j] = (double *)calloc(depth,sizeof(double));
assert(MyMatrix != NULL);
for (k = 0; k < depth; k++)
MyMatrix[i][j][k] = 0;
}
}
return MyMatrix;
}
// This function creates a 3D Array (matrix of vectors) :: DOUBLE
// It returns a pointer
bool ***Create3DArrayBool(int width, int height, int depth)
{
bool ***MyMatrix;
int i, j, k;
MyMatrix = (bool ***)calloc(height,sizeof(bool**));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
{
MyMatrix[i] = (bool **)calloc(width,sizeof(bool*));
assert(MyMatrix != NULL);
for (j = 0; j < width; j++)
{
MyMatrix[i][j] = (bool *)calloc(depth,sizeof(bool));
assert(MyMatrix != NULL);
for (k = 0; k < depth; k++)
MyMatrix[i][j][k] = 0;
}
}
return MyMatrix;
}
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
//////////////////////////// Create directory ///////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
void CreateDirectory(char* MainWorkDir)
{
// Create the working directory, exit if it already exist!
DIR *MyDirVar;
MyDirVar = opendir (MainWorkDir); // Open the following directory
if (MyDirVar != NULL) // if dp equals to NULL dir does not exist
{
//printf("Directory %s already exist, move on.\n", MainWorkDir);
}
else
{
mkdir(MainWorkDir, S_IRWXU|S_IRGRP|S_IXGRP); // Create the directiory
//printf("Directory does not exist yet... creating: %s\n", MainWorkDir);
}
}
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////////// Add string //////////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
void StringAddition(char* first, char* second, char* result)
{
strcat(result, first);
strcat(result, second);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h> // for calloc();
#include <assert.h> // ensure successfull allocation
#include <stdbool.h> // bool variables
#include <stdio.h> // printf...
#include <string.h>
#include <dirent.h> // Directory management
#include <sys/stat.h> // system commands ?
#include <sys/types.h> // Extra types of variables, google it
#include <unistd.h> // standard symbolic constants and types
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////// 1D array allocators /////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
// This function creates a 1D Array (vector) :: INT
// It returns a pointer
int *Create1DArrayInt(int length)
{
int *MyArray;
MyArray = (int *)calloc(length,sizeof(int));
assert(MyArray != NULL);
return MyArray;
}
// This function creates a 1D Array (vector) :: FLOAT
// It returns a pointer
float *Create1DArrayFloat(int length)
{
float *MyArray;
MyArray = (float *)calloc(length,sizeof(float));
assert(MyArray != NULL);
return MyArray;
}
// This function creates a 1D Array (vector) :: DOUBLE
// It returns a pointer
double *Create1DArrayDouble(int length)
{
double *MyArray;
MyArray = (double *)calloc(length,sizeof(double));
assert(MyArray != NULL);
return MyArray;
}
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////// 2D array allocators /////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
// This function creates a 2D Array (matrix) :: FLOAT
// It returns a pointer
int **Create2DArrayInt(int width, int height)
{
int **MyMatrix;
int i;
MyMatrix = (int **)calloc(height,sizeof(int*));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
MyMatrix[i] = (int *)calloc(width,sizeof(int));
assert(MyMatrix != NULL);
return MyMatrix;
}
// This function creates a 2D Array (matrix) :: FLOAT
// It returns a pointer
float **Create2DArrayFloat(int width, int height)
{
float **MyMatrix;
int i;
MyMatrix = (float **)calloc(height,sizeof(float*));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
MyMatrix[i] = (float *)calloc(width,sizeof(float));
assert(MyMatrix != NULL);
return MyMatrix;
}
// This function creates a 2D Array (matrix) :: DOUBLE
// It returns a pointer
double **Create2DArrayDouble(int width, int height)
{
double **MyMatrix;
int i;
MyMatrix = (double **)calloc(height,sizeof(double*));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
MyMatrix[i] = (double *)calloc(width,sizeof(double));
assert(MyMatrix != NULL);
return MyMatrix;
}
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////// 3D array allocators /////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
// This function creates a 3D Array (matrix of vectors) :: INT
// It returns a pointer
int ***Create3DArrayInt(int width, int height, int depth)
{
int ***MyMatrix;
int i, j, k;
MyMatrix = (int ***)calloc(height,sizeof(int**));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
{
MyMatrix[i] = (int **)calloc(width,sizeof(int*));
assert(MyMatrix != NULL);
for (j = 0; j < width; j++)
{
MyMatrix[i][j] = (int *)calloc(depth,sizeof(int));
assert(MyMatrix != NULL);
for (k = 0; k < depth; k++)
MyMatrix[i][j][k] = 0;
}
}
return MyMatrix;
}
// This function creates a 3D Array (matrix of vectors) :: FLOAT
// It returns a pointer
float ***Create3DArrayFloat(int width, int height, int depth)
{
float ***MyMatrix;
int i, j, k;
MyMatrix = (float ***)calloc(height,sizeof(float**));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
{
MyMatrix[i] = (float **)calloc(width,sizeof(float*));
assert(MyMatrix != NULL);
for (j = 0; j < width; j++)
{
MyMatrix[i][j] = (float *)calloc(depth,sizeof(float));
assert(MyMatrix != NULL);
for (k = 0; k < depth; k++)
MyMatrix[i][j][k] = 0;
}
}
return MyMatrix;
}
// This function creates a 3D Array (matrix of vectors) :: DOUBLE
// It returns a pointer
double ***Create3DArrayDouble(int width, int height, int depth)
{
double ***MyMatrix;
int i, j, k;
MyMatrix = (double ***)calloc(height,sizeof(double**));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
{
MyMatrix[i] = (double **)calloc(width,sizeof(double*));
assert(MyMatrix != NULL);
for (j = 0; j < width; j++)
{
MyMatrix[i][j] = (double *)calloc(depth,sizeof(double));
assert(MyMatrix != NULL);
for (k = 0; k < depth; k++)
MyMatrix[i][j][k] = 0;
}
}
return MyMatrix;
}
// This function creates a 3D Array (matrix of vectors) :: DOUBLE
// It returns a pointer
bool ***Create3DArrayBool(int width, int height, int depth)
{
bool ***MyMatrix;
int i, j, k;
MyMatrix = (bool ***)calloc(height,sizeof(bool**));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
{
MyMatrix[i] = (bool **)calloc(width,sizeof(bool*));
assert(MyMatrix != NULL);
for (j = 0; j < width; j++)
{
MyMatrix[i][j] = (bool *)calloc(depth,sizeof(bool));
assert(MyMatrix != NULL);
for (k = 0; k < depth; k++)
MyMatrix[i][j][k] = 0;
}
}
return MyMatrix;
}
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
//////////////////////////// Create directory ///////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
void CreateDirectory(char* MainWorkDir)
{
// Create the working directory, exit if it already exist!
DIR *MyDirVar;
MyDirVar = opendir (MainWorkDir); // Open the following directory
if (MyDirVar != NULL) // if dp equals to NULL dir does not exist
{
//printf("Directory %s already exist, move on.\n", MainWorkDir);
}
else
{
mkdir(MainWorkDir, S_IRWXU|S_IRGRP|S_IXGRP); // Create the directiory
//printf("Directory does not exist yet... creating: %s\n", MainWorkDir);
}
}
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////////// Add string //////////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
void StringAddition(char* first, char* second, char* result)
{
strcat(result, first);
strcat(result, second);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h> // for calloc();
#include <assert.h> // ensure successfull allocation
#include <stdbool.h> // bool variables
#include <stdio.h> // printf...
#include <string.h>
#include <dirent.h> // Directory management
#include <sys/stat.h> // system commands ?
#include <sys/types.h> // Extra types of variables, google it
#include <unistd.h> // standard symbolic constants and types
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////// 1D array allocators /////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
// This function creates a 1D Array (vector) :: INT
// It returns a pointer
int *Create1DArrayInt(int length)
{
int *MyArray;
MyArray = (int *)calloc(length,sizeof(int));
assert(MyArray != NULL);
return MyArray;
}
// This function creates a 1D Array (vector) :: FLOAT
// It returns a pointer
float *Create1DArrayFloat(int length)
{
float *MyArray;
MyArray = (float *)calloc(length,sizeof(float));
assert(MyArray != NULL);
return MyArray;
}
// This function creates a 1D Array (vector) :: DOUBLE
// It returns a pointer
double *Create1DArrayDouble(int length)
{
double *MyArray;
MyArray = (double *)calloc(length,sizeof(double));
assert(MyArray != NULL);
return MyArray;
}
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////// 2D array allocators /////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
// This function creates a 2D Array (matrix) :: FLOAT
// It returns a pointer
int **Create2DArrayInt(int width, int height)
{
int **MyMatrix;
int i;
MyMatrix = (int **)calloc(height,sizeof(int*));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
MyMatrix[i] = (int *)calloc(width,sizeof(int));
assert(MyMatrix != NULL);
return MyMatrix;
}
// This function creates a 2D Array (matrix) :: FLOAT
// It returns a pointer
float **Create2DArrayFloat(int width, int height)
{
float **MyMatrix;
int i;
MyMatrix = (float **)calloc(height,sizeof(float*));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
MyMatrix[i] = (float *)calloc(width,sizeof(float));
assert(MyMatrix != NULL);
return MyMatrix;
}
// This function creates a 2D Array (matrix) :: DOUBLE
// It returns a pointer
double **Create2DArrayDouble(int width, int height)
{
double **MyMatrix;
int i;
MyMatrix = (double **)calloc(height,sizeof(double*));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
MyMatrix[i] = (double *)calloc(width,sizeof(double));
assert(MyMatrix != NULL);
return MyMatrix;
}
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////// 3D array allocators /////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
// This function creates a 3D Array (matrix of vectors) :: INT
// It returns a pointer
int ***Create3DArrayInt(int width, int height, int depth)
{
int ***MyMatrix;
int i, j, k;
MyMatrix = (int ***)calloc(height,sizeof(int**));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
{
MyMatrix[i] = (int **)calloc(width,sizeof(int*));
assert(MyMatrix != NULL);
for (j = 0; j < width; j++)
{
MyMatrix[i][j] = (int *)calloc(depth,sizeof(int));
assert(MyMatrix != NULL);
for (k = 0; k < depth; k++)
MyMatrix[i][j][k] = 0;
}
}
return MyMatrix;
}
// This function creates a 3D Array (matrix of vectors) :: FLOAT
// It returns a pointer
float ***Create3DArrayFloat(int width, int height, int depth)
{
float ***MyMatrix;
int i, j, k;
MyMatrix = (float ***)calloc(height,sizeof(float**));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
{
MyMatrix[i] = (float **)calloc(width,sizeof(float*));
assert(MyMatrix != NULL);
for (j = 0; j < width; j++)
{
MyMatrix[i][j] = (float *)calloc(depth,sizeof(float));
assert(MyMatrix != NULL);
for (k = 0; k < depth; k++)
MyMatrix[i][j][k] = 0;
}
}
return MyMatrix;
}
// This function creates a 3D Array (matrix of vectors) :: DOUBLE
// It returns a pointer
double ***Create3DArrayDouble(int width, int height, int depth)
{
double ***MyMatrix;
int i, j, k;
MyMatrix = (double ***)calloc(height,sizeof(double**));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
{
MyMatrix[i] = (double **)calloc(width,sizeof(double*));
assert(MyMatrix != NULL);
for (j = 0; j < width; j++)
{
MyMatrix[i][j] = (double *)calloc(depth,sizeof(double));
assert(MyMatrix != NULL);
for (k = 0; k < depth; k++)
MyMatrix[i][j][k] = 0;
}
}
return MyMatrix;
}
// This function creates a 3D Array (matrix of vectors) :: DOUBLE
// It returns a pointer
bool ***Create3DArrayBool(int width, int height, int depth)
{
bool ***MyMatrix;
int i, j, k;
MyMatrix = (bool ***)calloc(height,sizeof(bool**));
assert(MyMatrix != NULL);
for (i = 0; i < height; i++)
{
MyMatrix[i] = (bool **)calloc(width,sizeof(bool*));
assert(MyMatrix != NULL);
for (j = 0; j < width; j++)
{
MyMatrix[i][j] = (bool *)calloc(depth,sizeof(bool));
assert(MyMatrix != NULL);
for (k = 0; k < depth; k++)
MyMatrix[i][j][k] = 0;
}
}
return MyMatrix;
}
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
//////////////////////////// Create directory ///////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
void CreateDirectory(char* MainWorkDir)
{
// Create the working directory, exit if it already exist!
DIR *MyDirVar;
MyDirVar = opendir (MainWorkDir); // Open the following directory
if (MyDirVar != NULL) // if dp equals to NULL dir does not exist
{
//printf("Directory %s already exist, move on.\n", MainWorkDir);
}
else
{
mkdir(MainWorkDir, S_IRWXU|S_IRGRP|S_IXGRP); // Create the directiory
//printf("Directory does not exist yet... creating: %s\n", MainWorkDir);
}
}
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////////// Add string //////////////////////////////
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
void StringAddition(char* first, char* second, char* result)
{
strcat(result, first);
strcat(result, second);
} | .text
.file "ShellFunctions.hip"
.globl _Z16Create1DArrayInti # -- Begin function _Z16Create1DArrayInti
.p2align 4, 0x90
.type _Z16Create1DArrayInti,@function
_Z16Create1DArrayInti: # @_Z16Create1DArrayInti
.cfi_startproc
# %bb.0:
movslq %edi, %rdi
movl $4, %esi
jmp calloc # TAILCALL
.Lfunc_end0:
.size _Z16Create1DArrayInti, .Lfunc_end0-_Z16Create1DArrayInti
.cfi_endproc
# -- End function
.globl _Z18Create1DArrayFloati # -- Begin function _Z18Create1DArrayFloati
.p2align 4, 0x90
.type _Z18Create1DArrayFloati,@function
_Z18Create1DArrayFloati: # @_Z18Create1DArrayFloati
.cfi_startproc
# %bb.0:
movslq %edi, %rdi
movl $4, %esi
jmp calloc # TAILCALL
.Lfunc_end1:
.size _Z18Create1DArrayFloati, .Lfunc_end1-_Z18Create1DArrayFloati
.cfi_endproc
# -- End function
.globl _Z19Create1DArrayDoublei # -- Begin function _Z19Create1DArrayDoublei
.p2align 4, 0x90
.type _Z19Create1DArrayDoublei,@function
_Z19Create1DArrayDoublei: # @_Z19Create1DArrayDoublei
.cfi_startproc
# %bb.0:
movslq %edi, %rdi
movl $8, %esi
jmp calloc # TAILCALL
.Lfunc_end2:
.size _Z19Create1DArrayDoublei, .Lfunc_end2-_Z19Create1DArrayDoublei
.cfi_endproc
# -- End function
.globl _Z16Create2DArrayIntii # -- Begin function _Z16Create2DArrayIntii
.p2align 4, 0x90
.type _Z16Create2DArrayIntii,@function
_Z16Create2DArrayIntii: # @_Z16Create2DArrayIntii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movl %edi, %r14d
movslq %esi, %r15
movl $8, %esi
movq %r15, %rdi
callq calloc
movq %rax, %rbx
testl %r15d, %r15d
jle .LBB3_3
# %bb.1: # %.lr.ph
movslq %r14d, %r14
movl %ebp, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_2: # =>This Inner Loop Header: Depth=1
movl $4, %esi
movq %r14, %rdi
callq calloc
movq %rax, (%rbx,%r12,8)
incq %r12
cmpq %r12, %r15
jne .LBB3_2
.LBB3_3: # %._crit_edge
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z16Create2DArrayIntii, .Lfunc_end3-_Z16Create2DArrayIntii
.cfi_endproc
# -- End function
.globl _Z18Create2DArrayFloatii # -- Begin function _Z18Create2DArrayFloatii
.p2align 4, 0x90
.type _Z18Create2DArrayFloatii,@function
_Z18Create2DArrayFloatii: # @_Z18Create2DArrayFloatii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movl %edi, %r14d
movslq %esi, %r15
movl $8, %esi
movq %r15, %rdi
callq calloc
movq %rax, %rbx
testl %r15d, %r15d
jle .LBB4_3
# %bb.1: # %.lr.ph
movslq %r14d, %r14
movl %ebp, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_2: # =>This Inner Loop Header: Depth=1
movl $4, %esi
movq %r14, %rdi
callq calloc
movq %rax, (%rbx,%r12,8)
incq %r12
cmpq %r12, %r15
jne .LBB4_2
.LBB4_3: # %._crit_edge
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z18Create2DArrayFloatii, .Lfunc_end4-_Z18Create2DArrayFloatii
.cfi_endproc
# -- End function
.globl _Z19Create2DArrayDoubleii # -- Begin function _Z19Create2DArrayDoubleii
.p2align 4, 0x90
.type _Z19Create2DArrayDoubleii,@function
_Z19Create2DArrayDoubleii: # @_Z19Create2DArrayDoubleii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movl %edi, %r14d
movslq %esi, %r15
movl $8, %esi
movq %r15, %rdi
callq calloc
movq %rax, %rbx
testl %r15d, %r15d
jle .LBB5_3
# %bb.1: # %.lr.ph
movslq %r14d, %r14
movl %ebp, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_2: # =>This Inner Loop Header: Depth=1
movl $8, %esi
movq %r14, %rdi
callq calloc
movq %rax, (%rbx,%r12,8)
incq %r12
cmpq %r12, %r15
jne .LBB5_2
.LBB5_3: # %._crit_edge
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z19Create2DArrayDoubleii, .Lfunc_end5-_Z19Create2DArrayDoubleii
.cfi_endproc
# -- End function
.globl _Z16Create3DArrayIntiii # -- Begin function _Z16Create3DArrayIntiii
.p2align 4, 0x90
.type _Z16Create3DArrayIntiii,@function
_Z16Create3DArrayIntiii: # @_Z16Create3DArrayIntiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r15d
movl %esi, %ebp
movl %edi, %r14d
movslq %esi, %r12
movl $8, %esi
movq %r12, %rdi
callq calloc
movq %rax, (%rsp) # 8-byte Spill
testl %r12d, %r12d
jle .LBB6_8
# %bb.1: # %.lr.ph30
movslq %r14d, %rax
movslq %r15d, %r15
movl %r15d, %r12d
shlq $2, %r12
movl %ebp, %ecx
movq %rcx, 8(%rsp) # 8-byte Spill
movq %rax, 16(%rsp) # 8-byte Spill
movl %eax, %ebx
xorl %ebp, %ebp
jmp .LBB6_2
.p2align 4, 0x90
.LBB6_7: # %._crit_edge27
# in Loop: Header=BB6_2 Depth=1
incq %rbp
cmpq 8(%rsp), %rbp # 8-byte Folded Reload
je .LBB6_8
.LBB6_2: # =>This Loop Header: Depth=1
# Child Loop BB6_4 Depth 2
movl $8, %esi
movq 16(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
callq calloc
movq %rax, %r13
movq (%rsp), %rax # 8-byte Reload
movq %r13, (%rax,%rbp,8)
testl %r14d, %r14d
jle .LBB6_7
# %bb.3: # %.lr.ph26.preheader
# in Loop: Header=BB6_2 Depth=1
xorl %r14d, %r14d
jmp .LBB6_4
.p2align 4, 0x90
.LBB6_6: # %._crit_edge
# in Loop: Header=BB6_4 Depth=2
incq %r14
cmpq %r14, %rbx
je .LBB6_7
.LBB6_4: # %.lr.ph26
# Parent Loop BB6_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $4, %esi
movq %r15, %rdi
callq calloc
movq %rax, (%r13,%r14,8)
testl %r15d, %r15d
jle .LBB6_6
# %bb.5: # %.lr.ph.preheader
# in Loop: Header=BB6_4 Depth=2
movq %rax, %rdi
xorl %esi, %esi
movq %r12, %rdx
callq memset@PLT
jmp .LBB6_6
.LBB6_8: # %._crit_edge31
movq (%rsp), %rax # 8-byte Reload
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z16Create3DArrayIntiii, .Lfunc_end6-_Z16Create3DArrayIntiii
.cfi_endproc
# -- End function
.globl _Z18Create3DArrayFloatiii # -- Begin function _Z18Create3DArrayFloatiii
.p2align 4, 0x90
.type _Z18Create3DArrayFloatiii,@function
_Z18Create3DArrayFloatiii: # @_Z18Create3DArrayFloatiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r15d
movl %esi, %ebp
movl %edi, %r14d
movslq %esi, %r12
movl $8, %esi
movq %r12, %rdi
callq calloc
movq %rax, (%rsp) # 8-byte Spill
testl %r12d, %r12d
jle .LBB7_8
# %bb.1: # %.lr.ph30
movslq %r14d, %rax
movslq %r15d, %r15
movl %r15d, %r12d
shlq $2, %r12
movl %ebp, %ecx
movq %rcx, 8(%rsp) # 8-byte Spill
movq %rax, 16(%rsp) # 8-byte Spill
movl %eax, %ebx
xorl %ebp, %ebp
jmp .LBB7_2
.p2align 4, 0x90
.LBB7_7: # %._crit_edge27
# in Loop: Header=BB7_2 Depth=1
incq %rbp
cmpq 8(%rsp), %rbp # 8-byte Folded Reload
je .LBB7_8
.LBB7_2: # =>This Loop Header: Depth=1
# Child Loop BB7_4 Depth 2
movl $8, %esi
movq 16(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
callq calloc
movq %rax, %r13
movq (%rsp), %rax # 8-byte Reload
movq %r13, (%rax,%rbp,8)
testl %r14d, %r14d
jle .LBB7_7
# %bb.3: # %.lr.ph26.preheader
# in Loop: Header=BB7_2 Depth=1
xorl %r14d, %r14d
jmp .LBB7_4
.p2align 4, 0x90
.LBB7_6: # %._crit_edge
# in Loop: Header=BB7_4 Depth=2
incq %r14
cmpq %r14, %rbx
je .LBB7_7
.LBB7_4: # %.lr.ph26
# Parent Loop BB7_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $4, %esi
movq %r15, %rdi
callq calloc
movq %rax, (%r13,%r14,8)
testl %r15d, %r15d
jle .LBB7_6
# %bb.5: # %.lr.ph.preheader
# in Loop: Header=BB7_4 Depth=2
movq %rax, %rdi
xorl %esi, %esi
movq %r12, %rdx
callq memset@PLT
jmp .LBB7_6
.LBB7_8: # %._crit_edge31
movq (%rsp), %rax # 8-byte Reload
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _Z18Create3DArrayFloatiii, .Lfunc_end7-_Z18Create3DArrayFloatiii
.cfi_endproc
# -- End function
.globl _Z19Create3DArrayDoubleiii # -- Begin function _Z19Create3DArrayDoubleiii
.p2align 4, 0x90
.type _Z19Create3DArrayDoubleiii,@function
_Z19Create3DArrayDoubleiii: # @_Z19Create3DArrayDoubleiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r15d
movl %esi, %ebp
movl %edi, %r14d
movslq %esi, %r12
movl $8, %esi
movq %r12, %rdi
callq calloc
movq %rax, (%rsp) # 8-byte Spill
testl %r12d, %r12d
jle .LBB8_8
# %bb.1: # %.lr.ph30
movslq %r14d, %rax
movslq %r15d, %r15
movl %r15d, %r12d
shlq $3, %r12
movl %ebp, %ecx
movq %rcx, 8(%rsp) # 8-byte Spill
movq %rax, 16(%rsp) # 8-byte Spill
movl %eax, %ebx
xorl %ebp, %ebp
jmp .LBB8_2
.p2align 4, 0x90
.LBB8_7: # %._crit_edge27
# in Loop: Header=BB8_2 Depth=1
incq %rbp
cmpq 8(%rsp), %rbp # 8-byte Folded Reload
je .LBB8_8
.LBB8_2: # =>This Loop Header: Depth=1
# Child Loop BB8_4 Depth 2
movl $8, %esi
movq 16(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
callq calloc
movq %rax, %r13
movq (%rsp), %rax # 8-byte Reload
movq %r13, (%rax,%rbp,8)
testl %r14d, %r14d
jle .LBB8_7
# %bb.3: # %.lr.ph26.preheader
# in Loop: Header=BB8_2 Depth=1
xorl %r14d, %r14d
jmp .LBB8_4
.p2align 4, 0x90
.LBB8_6: # %._crit_edge
# in Loop: Header=BB8_4 Depth=2
incq %r14
cmpq %r14, %rbx
je .LBB8_7
.LBB8_4: # %.lr.ph26
# Parent Loop BB8_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $8, %esi
movq %r15, %rdi
callq calloc
movq %rax, (%r13,%r14,8)
testl %r15d, %r15d
jle .LBB8_6
# %bb.5: # %.lr.ph.preheader
# in Loop: Header=BB8_4 Depth=2
movq %rax, %rdi
xorl %esi, %esi
movq %r12, %rdx
callq memset@PLT
jmp .LBB8_6
.LBB8_8: # %._crit_edge31
movq (%rsp), %rax # 8-byte Reload
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size _Z19Create3DArrayDoubleiii, .Lfunc_end8-_Z19Create3DArrayDoubleiii
.cfi_endproc
# -- End function
.globl _Z17Create3DArrayBooliii # -- Begin function _Z17Create3DArrayBooliii
.p2align 4, 0x90
.type _Z17Create3DArrayBooliii,@function
_Z17Create3DArrayBooliii: # @_Z17Create3DArrayBooliii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r15d
movl %esi, %ebp
movl %edi, %r14d
movslq %esi, %r12
movl $8, %esi
movq %r12, %rdi
callq calloc
movq %rax, (%rsp) # 8-byte Spill
testl %r12d, %r12d
jle .LBB9_8
# %bb.1: # %.lr.ph30
movslq %r14d, %rax
movslq %r15d, %r15
movl %r15d, %r12d
movl %ebp, %ecx
movq %rcx, 8(%rsp) # 8-byte Spill
movq %rax, 16(%rsp) # 8-byte Spill
movl %eax, %ebx
xorl %ebp, %ebp
jmp .LBB9_2
.p2align 4, 0x90
.LBB9_7: # %._crit_edge27
# in Loop: Header=BB9_2 Depth=1
incq %rbp
cmpq 8(%rsp), %rbp # 8-byte Folded Reload
je .LBB9_8
.LBB9_2: # =>This Loop Header: Depth=1
# Child Loop BB9_4 Depth 2
movl $8, %esi
movq 16(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
callq calloc
movq %rax, %r13
movq (%rsp), %rax # 8-byte Reload
movq %r13, (%rax,%rbp,8)
testl %r14d, %r14d
jle .LBB9_7
# %bb.3: # %.lr.ph26.preheader
# in Loop: Header=BB9_2 Depth=1
xorl %r14d, %r14d
jmp .LBB9_4
.p2align 4, 0x90
.LBB9_6: # %._crit_edge
# in Loop: Header=BB9_4 Depth=2
incq %r14
cmpq %r14, %rbx
je .LBB9_7
.LBB9_4: # %.lr.ph26
# Parent Loop BB9_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $1, %esi
movq %r15, %rdi
callq calloc
movq %rax, (%r13,%r14,8)
testl %r15d, %r15d
jle .LBB9_6
# %bb.5: # %.lr.ph.preheader
# in Loop: Header=BB9_4 Depth=2
movq %rax, %rdi
xorl %esi, %esi
movq %r12, %rdx
callq memset@PLT
jmp .LBB9_6
.LBB9_8: # %._crit_edge31
movq (%rsp), %rax # 8-byte Reload
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end9:
.size _Z17Create3DArrayBooliii, .Lfunc_end9-_Z17Create3DArrayBooliii
.cfi_endproc
# -- End function
.globl _Z15CreateDirectoryPc # -- Begin function _Z15CreateDirectoryPc
.p2align 4, 0x90
.type _Z15CreateDirectoryPc,@function
_Z15CreateDirectoryPc: # @_Z15CreateDirectoryPc
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
callq opendir
testq %rax, %rax
je .LBB10_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB10_2:
.cfi_def_cfa_offset 16
movq %rbx, %rdi
movl $488, %esi # imm = 0x1E8
popq %rbx
.cfi_def_cfa_offset 8
jmp mkdir # TAILCALL
.Lfunc_end10:
.size _Z15CreateDirectoryPc, .Lfunc_end10-_Z15CreateDirectoryPc
.cfi_endproc
# -- End function
.globl _Z14StringAdditionPcS_S_ # -- Begin function _Z14StringAdditionPcS_S_
.p2align 4, 0x90
.type _Z14StringAdditionPcS_S_,@function
_Z14StringAdditionPcS_S_: # @_Z14StringAdditionPcS_S_
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %rsi
movq %rdx, %rdi
callq strcat
movq %rbx, %rdi
movq %r14, %rsi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp strcat # TAILCALL
.Lfunc_end11:
.size _Z14StringAdditionPcS_S_, .Lfunc_end11-_Z14StringAdditionPcS_S_
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001522da_00000000-6_ShellFunctions.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16Create1DArrayInti
.type _Z16Create1DArrayInti, @function
_Z16Create1DArrayInti:
.LFB2070:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movslq %edi, %rdi
movl $4, %esi
call calloc@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2070:
.size _Z16Create1DArrayInti, .-_Z16Create1DArrayInti
.globl _Z18Create1DArrayFloati
.type _Z18Create1DArrayFloati, @function
_Z18Create1DArrayFloati:
.LFB2071:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movslq %edi, %rdi
movl $4, %esi
call calloc@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2071:
.size _Z18Create1DArrayFloati, .-_Z18Create1DArrayFloati
.globl _Z19Create1DArrayDoublei
.type _Z19Create1DArrayDoublei, @function
_Z19Create1DArrayDoublei:
.LFB2072:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movslq %edi, %rdi
movl $8, %esi
call calloc@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2072:
.size _Z19Create1DArrayDoublei, .-_Z19Create1DArrayDoublei
.globl _Z16Create2DArrayIntii
.type _Z16Create2DArrayIntii, @function
_Z16Create2DArrayIntii:
.LFB2073:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebp
movl %esi, %ebx
movslq %esi, %r12
movl $8, %esi
movq %r12, %rdi
call calloc@PLT
movq %rax, %r13
testl %ebx, %ebx
jle .L9
movq %rax, %rbx
leaq (%rax,%r12,8), %r12
movslq %ebp, %rbp
.L11:
movl $4, %esi
movq %rbp, %rdi
call calloc@PLT
movq %rax, (%rbx)
addq $8, %rbx
cmpq %r12, %rbx
jne .L11
.L9:
movq %r13, %rax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _Z16Create2DArrayIntii, .-_Z16Create2DArrayIntii
.globl _Z18Create2DArrayFloatii
.type _Z18Create2DArrayFloatii, @function
_Z18Create2DArrayFloatii:
.LFB2074:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebp
movl %esi, %ebx
movslq %esi, %r12
movl $8, %esi
movq %r12, %rdi
call calloc@PLT
movq %rax, %r13
testl %ebx, %ebx
jle .L14
movq %rax, %rbx
leaq (%rax,%r12,8), %r12
movslq %ebp, %rbp
.L16:
movl $4, %esi
movq %rbp, %rdi
call calloc@PLT
movq %rax, (%rbx)
addq $8, %rbx
cmpq %r12, %rbx
jne .L16
.L14:
movq %r13, %rax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _Z18Create2DArrayFloatii, .-_Z18Create2DArrayFloatii
.globl _Z19Create2DArrayDoubleii
.type _Z19Create2DArrayDoubleii, @function
_Z19Create2DArrayDoubleii:
.LFB2075:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebp
movl %esi, %ebx
movslq %esi, %r12
movl $8, %esi
movq %r12, %rdi
call calloc@PLT
movq %rax, %r13
testl %ebx, %ebx
jle .L19
movq %rax, %rbx
leaq (%rax,%r12,8), %r12
movslq %ebp, %rbp
.L21:
movl $8, %esi
movq %rbp, %rdi
call calloc@PLT
movq %rax, (%rbx)
addq $8, %rbx
cmpq %r12, %rbx
jne .L21
.L19:
movq %r13, %rax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2075:
.size _Z19Create2DArrayDoubleii, .-_Z19Create2DArrayDoubleii
.globl _Z16Create3DArrayIntiii
.type _Z16Create3DArrayIntiii, @function
_Z16Create3DArrayIntiii:
.LFB2076:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %edi, %r14d
movl %edi, 28(%rsp)
movl %esi, %ebx
movl %edx, %r12d
movslq %esi, %rbp
movl $8, %esi
movq %rbp, %rdi
call calloc@PLT
movq %rax, 40(%rsp)
testl %ebx, %ebx
jle .L24
movq %rax, %r15
leaq (%rax,%rbp,8), %rax
movq %rax, 16(%rsp)
movslq %r14d, %rax
movq %rax, 8(%rsp)
salq $3, %rax
movq %rax, 32(%rsp)
movslq %r12d, %r13
leaq 0(,%r13,4), %r14
.L30:
movl $8, %esi
movq 8(%rsp), %rdi
call calloc@PLT
movq %rax, (%r15)
cmpl $0, 28(%rsp)
jle .L26
movq %rax, %rbx
movq 32(%rsp), %rcx
leaq (%rax,%rcx), %rbp
.L29:
movl $4, %esi
movq %r13, %rdi
call calloc@PLT
movq %rax, (%rbx)
testl %r12d, %r12d
jle .L27
movq %rax, %rdx
addq %r14, %rax
.L28:
movl $0, (%rdx)
addq $4, %rdx
cmpq %rax, %rdx
jne .L28
.L27:
addq $8, %rbx
cmpq %rbp, %rbx
jne .L29
.L26:
addq $8, %r15
movq 16(%rsp), %rax
cmpq %rax, %r15
jne .L30
.L24:
movq 40(%rsp), %rax
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2076:
.size _Z16Create3DArrayIntiii, .-_Z16Create3DArrayIntiii
.globl _Z18Create3DArrayFloatiii
.type _Z18Create3DArrayFloatiii, @function
_Z18Create3DArrayFloatiii:
.LFB2077:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %edi, %r14d
movl %edi, 28(%rsp)
movl %esi, %ebx
movl %edx, %r12d
movslq %esi, %rbp
movl $8, %esi
movq %rbp, %rdi
call calloc@PLT
movq %rax, 40(%rsp)
testl %ebx, %ebx
jle .L35
movq %rax, %r15
leaq (%rax,%rbp,8), %rax
movq %rax, 16(%rsp)
movslq %r14d, %rax
movq %rax, 8(%rsp)
salq $3, %rax
movq %rax, 32(%rsp)
movslq %r12d, %r13
leaq 0(,%r13,4), %r14
.L41:
movl $8, %esi
movq 8(%rsp), %rdi
call calloc@PLT
movq %rax, (%r15)
cmpl $0, 28(%rsp)
jle .L37
movq %rax, %rbx
movq 32(%rsp), %rcx
leaq (%rax,%rcx), %rbp
.L40:
movl $4, %esi
movq %r13, %rdi
call calloc@PLT
movq %rax, (%rbx)
testl %r12d, %r12d
jle .L38
movq %rax, %rdx
addq %r14, %rax
.L39:
movl $0x00000000, (%rdx)
addq $4, %rdx
cmpq %rax, %rdx
jne .L39
.L38:
addq $8, %rbx
cmpq %rbp, %rbx
jne .L40
.L37:
addq $8, %r15
movq 16(%rsp), %rax
cmpq %rax, %r15
jne .L41
.L35:
movq 40(%rsp), %rax
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2077:
.size _Z18Create3DArrayFloatiii, .-_Z18Create3DArrayFloatiii
.globl _Z19Create3DArrayDoubleiii
.type _Z19Create3DArrayDoubleiii, @function
_Z19Create3DArrayDoubleiii:
.LFB2078:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %edi, %r14d
movl %edi, 28(%rsp)
movl %esi, %ebx
movl %edx, %r12d
movslq %esi, %rbp
movl $8, %esi
movq %rbp, %rdi
call calloc@PLT
movq %rax, 40(%rsp)
testl %ebx, %ebx
jle .L46
movq %rax, %r15
leaq (%rax,%rbp,8), %rax
movq %rax, 16(%rsp)
movslq %r14d, %rax
movq %rax, 8(%rsp)
salq $3, %rax
movq %rax, 32(%rsp)
movslq %r12d, %r13
leaq 0(,%r13,8), %r14
.L52:
movl $8, %esi
movq 8(%rsp), %rdi
call calloc@PLT
movq %rax, (%r15)
cmpl $0, 28(%rsp)
jle .L48
movq %rax, %rbx
movq 32(%rsp), %rcx
leaq (%rax,%rcx), %rbp
.L51:
movl $8, %esi
movq %r13, %rdi
call calloc@PLT
movq %rax, (%rbx)
testl %r12d, %r12d
jle .L49
movq %rax, %rdx
addq %r14, %rax
.L50:
movq $0x000000000, (%rdx)
addq $8, %rdx
cmpq %rax, %rdx
jne .L50
.L49:
addq $8, %rbx
cmpq %rbp, %rbx
jne .L51
.L48:
addq $8, %r15
movq 16(%rsp), %rax
cmpq %rax, %r15
jne .L52
.L46:
movq 40(%rsp), %rax
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2078:
.size _Z19Create3DArrayDoubleiii, .-_Z19Create3DArrayDoubleiii
.globl _Z17Create3DArrayBooliii
.type _Z17Create3DArrayBooliii, @function
_Z17Create3DArrayBooliii:
.LFB2079:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %r12d
movl %edi, 12(%rsp)
movl %esi, %ebx
movl %edx, %r13d
movslq %esi, %rbp
movl $8, %esi
movq %rbp, %rdi
call calloc@PLT
movq %rax, 24(%rsp)
testl %ebx, %ebx
jle .L57
movq %rax, %r14
leaq (%rax,%rbp,8), %r15
movslq %r12d, %rax
movq %rax, (%rsp)
salq $3, %rax
movq %rax, 16(%rsp)
movslq %r13d, %rbp
.L63:
movl $8, %esi
movq (%rsp), %rdi
call calloc@PLT
movq %rax, (%r14)
cmpl $0, 12(%rsp)
jle .L59
movq %rax, %rbx
movq 16(%rsp), %rcx
leaq (%rax,%rcx), %r12
.L62:
movl $1, %esi
movq %rbp, %rdi
call calloc@PLT
movq %rax, (%rbx)
testl %r13d, %r13d
jle .L60
movq %rax, %rdx
addq %rbp, %rax
.L61:
movb $0, (%rdx)
addq $1, %rdx
cmpq %rax, %rdx
jne .L61
.L60:
addq $8, %rbx
cmpq %r12, %rbx
jne .L62
.L59:
addq $8, %r14
cmpq %r15, %r14
jne .L63
.L57:
movq 24(%rsp), %rax
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2079:
.size _Z17Create3DArrayBooliii, .-_Z17Create3DArrayBooliii
.globl _Z15CreateDirectoryPc
.type _Z15CreateDirectoryPc, @function
_Z15CreateDirectoryPc:
.LFB2080:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call opendir@PLT
testq %rax, %rax
je .L71
.L68:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L71:
.cfi_restore_state
movl $488, %esi
movq %rbx, %rdi
call mkdir@PLT
jmp .L68
.cfi_endproc
.LFE2080:
.size _Z15CreateDirectoryPc, .-_Z15CreateDirectoryPc
.globl _Z14StringAdditionPcS_S_
.type _Z14StringAdditionPcS_S_, @function
_Z14StringAdditionPcS_S_:
.LFB2081:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbp
movq %rdx, %rbx
movq %rdi, %rsi
movq %rdx, %rdi
call strcat@PLT
movq %rbp, %rsi
movq %rbx, %rdi
call strcat@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2081:
.size _Z14StringAdditionPcS_S_, .-_Z14StringAdditionPcS_S_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2107:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2107:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ShellFunctions.hip"
.globl _Z16Create1DArrayInti # -- Begin function _Z16Create1DArrayInti
.p2align 4, 0x90
.type _Z16Create1DArrayInti,@function
_Z16Create1DArrayInti: # @_Z16Create1DArrayInti
.cfi_startproc
# %bb.0:
movslq %edi, %rdi
movl $4, %esi
jmp calloc # TAILCALL
.Lfunc_end0:
.size _Z16Create1DArrayInti, .Lfunc_end0-_Z16Create1DArrayInti
.cfi_endproc
# -- End function
.globl _Z18Create1DArrayFloati # -- Begin function _Z18Create1DArrayFloati
.p2align 4, 0x90
.type _Z18Create1DArrayFloati,@function
_Z18Create1DArrayFloati: # @_Z18Create1DArrayFloati
.cfi_startproc
# %bb.0:
movslq %edi, %rdi
movl $4, %esi
jmp calloc # TAILCALL
.Lfunc_end1:
.size _Z18Create1DArrayFloati, .Lfunc_end1-_Z18Create1DArrayFloati
.cfi_endproc
# -- End function
.globl _Z19Create1DArrayDoublei # -- Begin function _Z19Create1DArrayDoublei
.p2align 4, 0x90
.type _Z19Create1DArrayDoublei,@function
_Z19Create1DArrayDoublei: # @_Z19Create1DArrayDoublei
.cfi_startproc
# %bb.0:
movslq %edi, %rdi
movl $8, %esi
jmp calloc # TAILCALL
.Lfunc_end2:
.size _Z19Create1DArrayDoublei, .Lfunc_end2-_Z19Create1DArrayDoublei
.cfi_endproc
# -- End function
.globl _Z16Create2DArrayIntii # -- Begin function _Z16Create2DArrayIntii
.p2align 4, 0x90
.type _Z16Create2DArrayIntii,@function
_Z16Create2DArrayIntii: # @_Z16Create2DArrayIntii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movl %edi, %r14d
movslq %esi, %r15
movl $8, %esi
movq %r15, %rdi
callq calloc
movq %rax, %rbx
testl %r15d, %r15d
jle .LBB3_3
# %bb.1: # %.lr.ph
movslq %r14d, %r14
movl %ebp, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_2: # =>This Inner Loop Header: Depth=1
movl $4, %esi
movq %r14, %rdi
callq calloc
movq %rax, (%rbx,%r12,8)
incq %r12
cmpq %r12, %r15
jne .LBB3_2
.LBB3_3: # %._crit_edge
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z16Create2DArrayIntii, .Lfunc_end3-_Z16Create2DArrayIntii
.cfi_endproc
# -- End function
.globl _Z18Create2DArrayFloatii # -- Begin function _Z18Create2DArrayFloatii
.p2align 4, 0x90
.type _Z18Create2DArrayFloatii,@function
_Z18Create2DArrayFloatii: # @_Z18Create2DArrayFloatii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movl %edi, %r14d
movslq %esi, %r15
movl $8, %esi
movq %r15, %rdi
callq calloc
movq %rax, %rbx
testl %r15d, %r15d
jle .LBB4_3
# %bb.1: # %.lr.ph
movslq %r14d, %r14
movl %ebp, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_2: # =>This Inner Loop Header: Depth=1
movl $4, %esi
movq %r14, %rdi
callq calloc
movq %rax, (%rbx,%r12,8)
incq %r12
cmpq %r12, %r15
jne .LBB4_2
.LBB4_3: # %._crit_edge
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z18Create2DArrayFloatii, .Lfunc_end4-_Z18Create2DArrayFloatii
.cfi_endproc
# -- End function
.globl _Z19Create2DArrayDoubleii # -- Begin function _Z19Create2DArrayDoubleii
.p2align 4, 0x90
.type _Z19Create2DArrayDoubleii,@function
_Z19Create2DArrayDoubleii: # @_Z19Create2DArrayDoubleii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movl %edi, %r14d
movslq %esi, %r15
movl $8, %esi
movq %r15, %rdi
callq calloc
movq %rax, %rbx
testl %r15d, %r15d
jle .LBB5_3
# %bb.1: # %.lr.ph
movslq %r14d, %r14
movl %ebp, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_2: # =>This Inner Loop Header: Depth=1
movl $8, %esi
movq %r14, %rdi
callq calloc
movq %rax, (%rbx,%r12,8)
incq %r12
cmpq %r12, %r15
jne .LBB5_2
.LBB5_3: # %._crit_edge
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z19Create2DArrayDoubleii, .Lfunc_end5-_Z19Create2DArrayDoubleii
.cfi_endproc
# -- End function
.globl _Z16Create3DArrayIntiii # -- Begin function _Z16Create3DArrayIntiii
.p2align 4, 0x90
.type _Z16Create3DArrayIntiii,@function
_Z16Create3DArrayIntiii: # @_Z16Create3DArrayIntiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r15d
movl %esi, %ebp
movl %edi, %r14d
movslq %esi, %r12
movl $8, %esi
movq %r12, %rdi
callq calloc
movq %rax, (%rsp) # 8-byte Spill
testl %r12d, %r12d
jle .LBB6_8
# %bb.1: # %.lr.ph30
movslq %r14d, %rax
movslq %r15d, %r15
movl %r15d, %r12d
shlq $2, %r12
movl %ebp, %ecx
movq %rcx, 8(%rsp) # 8-byte Spill
movq %rax, 16(%rsp) # 8-byte Spill
movl %eax, %ebx
xorl %ebp, %ebp
jmp .LBB6_2
.p2align 4, 0x90
.LBB6_7: # %._crit_edge27
# in Loop: Header=BB6_2 Depth=1
incq %rbp
cmpq 8(%rsp), %rbp # 8-byte Folded Reload
je .LBB6_8
.LBB6_2: # =>This Loop Header: Depth=1
# Child Loop BB6_4 Depth 2
movl $8, %esi
movq 16(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
callq calloc
movq %rax, %r13
movq (%rsp), %rax # 8-byte Reload
movq %r13, (%rax,%rbp,8)
testl %r14d, %r14d
jle .LBB6_7
# %bb.3: # %.lr.ph26.preheader
# in Loop: Header=BB6_2 Depth=1
xorl %r14d, %r14d
jmp .LBB6_4
.p2align 4, 0x90
.LBB6_6: # %._crit_edge
# in Loop: Header=BB6_4 Depth=2
incq %r14
cmpq %r14, %rbx
je .LBB6_7
.LBB6_4: # %.lr.ph26
# Parent Loop BB6_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $4, %esi
movq %r15, %rdi
callq calloc
movq %rax, (%r13,%r14,8)
testl %r15d, %r15d
jle .LBB6_6
# %bb.5: # %.lr.ph.preheader
# in Loop: Header=BB6_4 Depth=2
movq %rax, %rdi
xorl %esi, %esi
movq %r12, %rdx
callq memset@PLT
jmp .LBB6_6
.LBB6_8: # %._crit_edge31
movq (%rsp), %rax # 8-byte Reload
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z16Create3DArrayIntiii, .Lfunc_end6-_Z16Create3DArrayIntiii
.cfi_endproc
# -- End function
.globl _Z18Create3DArrayFloatiii # -- Begin function _Z18Create3DArrayFloatiii
.p2align 4, 0x90
.type _Z18Create3DArrayFloatiii,@function
_Z18Create3DArrayFloatiii: # @_Z18Create3DArrayFloatiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r15d
movl %esi, %ebp
movl %edi, %r14d
movslq %esi, %r12
movl $8, %esi
movq %r12, %rdi
callq calloc
movq %rax, (%rsp) # 8-byte Spill
testl %r12d, %r12d
jle .LBB7_8
# %bb.1: # %.lr.ph30
movslq %r14d, %rax
movslq %r15d, %r15
movl %r15d, %r12d
shlq $2, %r12
movl %ebp, %ecx
movq %rcx, 8(%rsp) # 8-byte Spill
movq %rax, 16(%rsp) # 8-byte Spill
movl %eax, %ebx
xorl %ebp, %ebp
jmp .LBB7_2
.p2align 4, 0x90
.LBB7_7: # %._crit_edge27
# in Loop: Header=BB7_2 Depth=1
incq %rbp
cmpq 8(%rsp), %rbp # 8-byte Folded Reload
je .LBB7_8
.LBB7_2: # =>This Loop Header: Depth=1
# Child Loop BB7_4 Depth 2
movl $8, %esi
movq 16(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
callq calloc
movq %rax, %r13
movq (%rsp), %rax # 8-byte Reload
movq %r13, (%rax,%rbp,8)
testl %r14d, %r14d
jle .LBB7_7
# %bb.3: # %.lr.ph26.preheader
# in Loop: Header=BB7_2 Depth=1
xorl %r14d, %r14d
jmp .LBB7_4
.p2align 4, 0x90
.LBB7_6: # %._crit_edge
# in Loop: Header=BB7_4 Depth=2
incq %r14
cmpq %r14, %rbx
je .LBB7_7
.LBB7_4: # %.lr.ph26
# Parent Loop BB7_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $4, %esi
movq %r15, %rdi
callq calloc
movq %rax, (%r13,%r14,8)
testl %r15d, %r15d
jle .LBB7_6
# %bb.5: # %.lr.ph.preheader
# in Loop: Header=BB7_4 Depth=2
movq %rax, %rdi
xorl %esi, %esi
movq %r12, %rdx
callq memset@PLT
jmp .LBB7_6
.LBB7_8: # %._crit_edge31
movq (%rsp), %rax # 8-byte Reload
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _Z18Create3DArrayFloatiii, .Lfunc_end7-_Z18Create3DArrayFloatiii
.cfi_endproc
# -- End function
.globl _Z19Create3DArrayDoubleiii # -- Begin function _Z19Create3DArrayDoubleiii
.p2align 4, 0x90
.type _Z19Create3DArrayDoubleiii,@function
_Z19Create3DArrayDoubleiii: # @_Z19Create3DArrayDoubleiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r15d
movl %esi, %ebp
movl %edi, %r14d
movslq %esi, %r12
movl $8, %esi
movq %r12, %rdi
callq calloc
movq %rax, (%rsp) # 8-byte Spill
testl %r12d, %r12d
jle .LBB8_8
# %bb.1: # %.lr.ph30
movslq %r14d, %rax
movslq %r15d, %r15
movl %r15d, %r12d
shlq $3, %r12
movl %ebp, %ecx
movq %rcx, 8(%rsp) # 8-byte Spill
movq %rax, 16(%rsp) # 8-byte Spill
movl %eax, %ebx
xorl %ebp, %ebp
jmp .LBB8_2
.p2align 4, 0x90
.LBB8_7: # %._crit_edge27
# in Loop: Header=BB8_2 Depth=1
incq %rbp
cmpq 8(%rsp), %rbp # 8-byte Folded Reload
je .LBB8_8
.LBB8_2: # =>This Loop Header: Depth=1
# Child Loop BB8_4 Depth 2
movl $8, %esi
movq 16(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
callq calloc
movq %rax, %r13
movq (%rsp), %rax # 8-byte Reload
movq %r13, (%rax,%rbp,8)
testl %r14d, %r14d
jle .LBB8_7
# %bb.3: # %.lr.ph26.preheader
# in Loop: Header=BB8_2 Depth=1
xorl %r14d, %r14d
jmp .LBB8_4
.p2align 4, 0x90
.LBB8_6: # %._crit_edge
# in Loop: Header=BB8_4 Depth=2
incq %r14
cmpq %r14, %rbx
je .LBB8_7
.LBB8_4: # %.lr.ph26
# Parent Loop BB8_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $8, %esi
movq %r15, %rdi
callq calloc
movq %rax, (%r13,%r14,8)
testl %r15d, %r15d
jle .LBB8_6
# %bb.5: # %.lr.ph.preheader
# in Loop: Header=BB8_4 Depth=2
movq %rax, %rdi
xorl %esi, %esi
movq %r12, %rdx
callq memset@PLT
jmp .LBB8_6
.LBB8_8: # %._crit_edge31
movq (%rsp), %rax # 8-byte Reload
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size _Z19Create3DArrayDoubleiii, .Lfunc_end8-_Z19Create3DArrayDoubleiii
.cfi_endproc
# -- End function
.globl _Z17Create3DArrayBooliii # -- Begin function _Z17Create3DArrayBooliii
.p2align 4, 0x90
.type _Z17Create3DArrayBooliii,@function
_Z17Create3DArrayBooliii: # @_Z17Create3DArrayBooliii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r15d
movl %esi, %ebp
movl %edi, %r14d
movslq %esi, %r12
movl $8, %esi
movq %r12, %rdi
callq calloc
movq %rax, (%rsp) # 8-byte Spill
testl %r12d, %r12d
jle .LBB9_8
# %bb.1: # %.lr.ph30
movslq %r14d, %rax
movslq %r15d, %r15
movl %r15d, %r12d
movl %ebp, %ecx
movq %rcx, 8(%rsp) # 8-byte Spill
movq %rax, 16(%rsp) # 8-byte Spill
movl %eax, %ebx
xorl %ebp, %ebp
jmp .LBB9_2
.p2align 4, 0x90
.LBB9_7: # %._crit_edge27
# in Loop: Header=BB9_2 Depth=1
incq %rbp
cmpq 8(%rsp), %rbp # 8-byte Folded Reload
je .LBB9_8
.LBB9_2: # =>This Loop Header: Depth=1
# Child Loop BB9_4 Depth 2
movl $8, %esi
movq 16(%rsp), %r14 # 8-byte Reload
movq %r14, %rdi
callq calloc
movq %rax, %r13
movq (%rsp), %rax # 8-byte Reload
movq %r13, (%rax,%rbp,8)
testl %r14d, %r14d
jle .LBB9_7
# %bb.3: # %.lr.ph26.preheader
# in Loop: Header=BB9_2 Depth=1
xorl %r14d, %r14d
jmp .LBB9_4
.p2align 4, 0x90
.LBB9_6: # %._crit_edge
# in Loop: Header=BB9_4 Depth=2
incq %r14
cmpq %r14, %rbx
je .LBB9_7
.LBB9_4: # %.lr.ph26
# Parent Loop BB9_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $1, %esi
movq %r15, %rdi
callq calloc
movq %rax, (%r13,%r14,8)
testl %r15d, %r15d
jle .LBB9_6
# %bb.5: # %.lr.ph.preheader
# in Loop: Header=BB9_4 Depth=2
movq %rax, %rdi
xorl %esi, %esi
movq %r12, %rdx
callq memset@PLT
jmp .LBB9_6
.LBB9_8: # %._crit_edge31
movq (%rsp), %rax # 8-byte Reload
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end9:
.size _Z17Create3DArrayBooliii, .Lfunc_end9-_Z17Create3DArrayBooliii
.cfi_endproc
# -- End function
.globl _Z15CreateDirectoryPc # -- Begin function _Z15CreateDirectoryPc
.p2align 4, 0x90
.type _Z15CreateDirectoryPc,@function
_Z15CreateDirectoryPc: # @_Z15CreateDirectoryPc
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
callq opendir
testq %rax, %rax
je .LBB10_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB10_2:
.cfi_def_cfa_offset 16
movq %rbx, %rdi
movl $488, %esi # imm = 0x1E8
popq %rbx
.cfi_def_cfa_offset 8
jmp mkdir # TAILCALL
.Lfunc_end10:
.size _Z15CreateDirectoryPc, .Lfunc_end10-_Z15CreateDirectoryPc
.cfi_endproc
# -- End function
.globl _Z14StringAdditionPcS_S_ # -- Begin function _Z14StringAdditionPcS_S_
.p2align 4, 0x90
.type _Z14StringAdditionPcS_S_,@function
_Z14StringAdditionPcS_S_: # @_Z14StringAdditionPcS_S_
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %rsi
movq %rdx, %rdi
callq strcat
movq %rbx, %rdi
movq %r14, %rsi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp strcat # TAILCALL
.Lfunc_end11:
.size _Z14StringAdditionPcS_S_, .Lfunc_end11-_Z14StringAdditionPcS_S_
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
#define CUDA_DEVICE (0)
#define NUM_THREADS (1<<13)
#define BLOCK_DIM (64)
#define GRID_DIM (NUM_THREADS/BLOCK_DIM)
#define NUM_BYTES (NUM_THREADS*4*sizeof(float))
// Compile and run with the commands:
// nvcc float4_test.cu
// ./a.out
//
// Failure occurs on my Tesla C870 card when KERNEL_INVOCATIONS is a large
// number (e.g. 100), and TEST_KERNEL is 1 or 3. Kernels 1 and 3 are those
// which write float4 values to device memory. Failure does not occur on
// my Quadro NVS 290 card for any of the kernels.
//
#define KERNEL_INVOCATIONS (100)
#define TEST_KERNEL (1)
__global__ void testKernel1(float4* g_out, float4* g_in) {
const int idx = blockDim.x*blockIdx.x + threadIdx.x;
g_out[idx] = g_in[idx];
}
__global__ void testKernel2(float* g_out, float4* g_in) {
const int idx = BLOCK_DIM*blockIdx.x + threadIdx.x;
float4 f4 = g_in[idx];
g_out[4*idx+0] = f4.x;
g_out[4*idx+1] = f4.y;
g_out[4*idx+2] = f4.z;
g_out[4*idx+3] = f4.w;
}
__global__ void testKernel3(float4* g_out, float* g_in) {
const int idx = BLOCK_DIM*blockIdx.x + threadIdx.x;
float x = g_in[4*idx+0];
float y = g_in[4*idx+1];
float z = g_in[4*idx+2];
float w = g_in[4*idx+3];
g_out[idx] = make_float4(x, y, z, w);
}
__global__ void testKernel4(float* g_out, float* g_in) {
const int idx = BLOCK_DIM*blockIdx.x + threadIdx.x;
g_out[NUM_THREADS*0 + idx] = g_in[NUM_THREADS*0 + idx];
g_out[NUM_THREADS*1 + idx] = g_in[NUM_THREADS*1 + idx];
g_out[NUM_THREADS*2 + idx] = g_in[NUM_THREADS*2 + idx];
g_out[NUM_THREADS*3 + idx] = g_in[NUM_THREADS*3 + idx];
}
int main( int argc, char** argv) {
cudaSetDevice(CUDA_DEVICE);
float *input = (float *)malloc(NUM_BYTES);
float *output = (float *)malloc(NUM_BYTES);
void* d_input;
void* d_output;
cudaMalloc(&d_input, NUM_BYTES);
cudaMalloc(&d_output, NUM_BYTES);
for (int i = 0; i < NUM_THREADS*4; i++) {
input[i] = i;
}
cudaMemcpy(d_input, input, NUM_BYTES, cudaMemcpyHostToDevice);
dim3 gridDim(GRID_DIM, 1, 1);
dim3 blockDim(BLOCK_DIM, 1, 1);
for (int i = 0; i < KERNEL_INVOCATIONS; i++) {
switch (TEST_KERNEL) {
case 1:
testKernel1 <<<gridDim, blockDim>>> ((float4 *)d_output, (float4 *)d_input);
break;
case 2:
testKernel2 <<<gridDim, blockDim>>> ((float *)d_output, (float4 *)d_input);
break;
case 3:
testKernel3 <<<gridDim, blockDim>>> ((float4 *)d_output, (float *)d_input);
break;
case 4:
testKernel4 <<<gridDim, blockDim>>> ((float *)d_output, (float *)d_input);
break;
}
cudaThreadSynchronize();
}
cudaMemcpy(output, d_output, NUM_BYTES, cudaMemcpyDeviceToHost);
for (int i = 0; i < NUM_THREADS*4; i++) {
if (output[i] != i) {
printf("KERNEL=%d FAILED: elem #%d = %f\n", TEST_KERNEL, i, output[i]);
}
}
free(input);
free(output);
cudaFree(d_input);
cudaFree(d_output);
} | code for sm_80
Function : _Z11testKernel4PfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ LEA R4, R4, R3, 0x6 ; /* 0x0000000304047211 */
/* 0x001fca00078e30ff */
/*0060*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*0090*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x004fe8000c101904 */
/*00a0*/ LDG.E R9, [R2.64+0x8000] ; /* 0x0080000402097981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ STG.E [R4.64+0x8000], R9 ; /* 0x0080000904007986 */
/* 0x004fe8000c101904 */
/*00c0*/ LDG.E R11, [R2.64+0x10000] ; /* 0x01000004020b7981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ STG.E [R4.64+0x10000], R11 ; /* 0x0100000b04007986 */
/* 0x004fe8000c101904 */
/*00e0*/ LDG.E R13, [R2.64+0x18000] ; /* 0x01800004020d7981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ STG.E [R4.64+0x18000], R13 ; /* 0x0180000d04007986 */
/* 0x004fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11testKernel3P6float4Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ LEA R4, R4, R3, 0x6 ; /* 0x0000000304047211 */
/* 0x001fe200078e30ff */
/*0050*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fc600000001ff */
/*0060*/ SHF.L.U32 R2, R4, 0x2, RZ ; /* 0x0000000204027819 */
/* 0x000fce00000006ff */
/*0070*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*0080*/ LDG.E R11, [R2.64+0xc] ; /* 0x00000c04020b7981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R10, [R2.64+0x8] ; /* 0x00000804020a7981 */
/* 0x000ea8000c1e1900 */
/*00a0*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040402097981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ HFMA2.MMA R5, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff057435 */
/* 0x000fd400000001ff */
/*00d0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*00e0*/ STG.E.128 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x004fe2000c101d04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11testKernel2PfP6float4
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ LEA R0, R0, R3, 0x6 ; /* 0x0000000300007211 */
/* 0x001fca00078e30ff */
/*0060*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E.128 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1d00 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0090*/ SHF.L.U32 R4, R0, 0x2, RZ ; /* 0x0000000200047819 */
/* 0x000fd200000006ff */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*00b0*/ STG.E [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x004fe8000c101904 */
/*00c0*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x000fe8000c101904 */
/*00d0*/ STG.E [R4.64+0x8], R10 ; /* 0x0000080a04007986 */
/* 0x000fe8000c101904 */
/*00e0*/ STG.E [R4.64+0xc], R11 ; /* 0x00000c0b04007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11testKernel1P6float4S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R4, R2, R9, c[0x0][0x168] ; /* 0x00005a0002047625 */
/* 0x000fcc00078e0209 */
/*0070*/ LDG.E.128 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1d00 */
/*0080*/ IMAD.WIDE R2, R2, R9, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0209 */
/*0090*/ STG.E.128 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x004fe2000c101d04 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#define CUDA_DEVICE (0)
#define NUM_THREADS (1<<13)
#define BLOCK_DIM (64)
#define GRID_DIM (NUM_THREADS/BLOCK_DIM)
#define NUM_BYTES (NUM_THREADS*4*sizeof(float))
// Compile and run with the commands:
// nvcc float4_test.cu
// ./a.out
//
// Failure occurs on my Tesla C870 card when KERNEL_INVOCATIONS is a large
// number (e.g. 100), and TEST_KERNEL is 1 or 3. Kernels 1 and 3 are those
// which write float4 values to device memory. Failure does not occur on
// my Quadro NVS 290 card for any of the kernels.
//
#define KERNEL_INVOCATIONS (100)
#define TEST_KERNEL (1)
__global__ void testKernel1(float4* g_out, float4* g_in) {
const int idx = blockDim.x*blockIdx.x + threadIdx.x;
g_out[idx] = g_in[idx];
}
__global__ void testKernel2(float* g_out, float4* g_in) {
const int idx = BLOCK_DIM*blockIdx.x + threadIdx.x;
float4 f4 = g_in[idx];
g_out[4*idx+0] = f4.x;
g_out[4*idx+1] = f4.y;
g_out[4*idx+2] = f4.z;
g_out[4*idx+3] = f4.w;
}
__global__ void testKernel3(float4* g_out, float* g_in) {
const int idx = BLOCK_DIM*blockIdx.x + threadIdx.x;
float x = g_in[4*idx+0];
float y = g_in[4*idx+1];
float z = g_in[4*idx+2];
float w = g_in[4*idx+3];
g_out[idx] = make_float4(x, y, z, w);
}
__global__ void testKernel4(float* g_out, float* g_in) {
const int idx = BLOCK_DIM*blockIdx.x + threadIdx.x;
g_out[NUM_THREADS*0 + idx] = g_in[NUM_THREADS*0 + idx];
g_out[NUM_THREADS*1 + idx] = g_in[NUM_THREADS*1 + idx];
g_out[NUM_THREADS*2 + idx] = g_in[NUM_THREADS*2 + idx];
g_out[NUM_THREADS*3 + idx] = g_in[NUM_THREADS*3 + idx];
}
int main( int argc, char** argv) {
cudaSetDevice(CUDA_DEVICE);
float *input = (float *)malloc(NUM_BYTES);
float *output = (float *)malloc(NUM_BYTES);
void* d_input;
void* d_output;
cudaMalloc(&d_input, NUM_BYTES);
cudaMalloc(&d_output, NUM_BYTES);
for (int i = 0; i < NUM_THREADS*4; i++) {
input[i] = i;
}
cudaMemcpy(d_input, input, NUM_BYTES, cudaMemcpyHostToDevice);
dim3 gridDim(GRID_DIM, 1, 1);
dim3 blockDim(BLOCK_DIM, 1, 1);
for (int i = 0; i < KERNEL_INVOCATIONS; i++) {
switch (TEST_KERNEL) {
case 1:
testKernel1 <<<gridDim, blockDim>>> ((float4 *)d_output, (float4 *)d_input);
break;
case 2:
testKernel2 <<<gridDim, blockDim>>> ((float *)d_output, (float4 *)d_input);
break;
case 3:
testKernel3 <<<gridDim, blockDim>>> ((float4 *)d_output, (float *)d_input);
break;
case 4:
testKernel4 <<<gridDim, blockDim>>> ((float *)d_output, (float *)d_input);
break;
}
cudaThreadSynchronize();
}
cudaMemcpy(output, d_output, NUM_BYTES, cudaMemcpyDeviceToHost);
for (int i = 0; i < NUM_THREADS*4; i++) {
if (output[i] != i) {
printf("KERNEL=%d FAILED: elem #%d = %f\n", TEST_KERNEL, i, output[i]);
}
}
free(input);
free(output);
cudaFree(d_input);
cudaFree(d_output);
} | .file "tmpxft_0016f5bc_00000000-6_float4_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z11testKernel1P6float4S0_P6float4S0_
.type _Z40__device_stub__Z11testKernel1P6float4S0_P6float4S0_, @function
_Z40__device_stub__Z11testKernel1P6float4S0_P6float4S0_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11testKernel1P6float4S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z40__device_stub__Z11testKernel1P6float4S0_P6float4S0_, .-_Z40__device_stub__Z11testKernel1P6float4S0_P6float4S0_
.globl _Z11testKernel1P6float4S0_
.type _Z11testKernel1P6float4S0_, @function
_Z11testKernel1P6float4S0_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z11testKernel1P6float4S0_P6float4S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11testKernel1P6float4S0_, .-_Z11testKernel1P6float4S0_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "KERNEL=%d FAILED: elem #%d = %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
movl $131072, %edi
call malloc@PLT
movq %rax, %r12
movl $131072, %edi
call malloc@PLT
movq %rax, %rbp
movq %rsp, %rdi
movl $131072, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $131072, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r12,%rax,4)
addq $1, %rax
cmpq $32768, %rax
jne .L12
movl $1, %ecx
movl $131072, %edx
movq %r12, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $64, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $100, %ebx
jmp .L14
.L13:
call cudaThreadSynchronize@PLT
subl $1, %ebx
je .L24
.L14:
movl 36(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movq 16(%rsp), %rdi
movl 24(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z40__device_stub__Z11testKernel1P6float4S0_P6float4S0_
jmp .L13
.L24:
movl $2, %ecx
movl $131072, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %r13
jmp .L17
.L19:
cvtss2sd %xmm0, %xmm0
movl $1, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L15:
addq $1, %rbx
cmpq $32768, %rbx
je .L25
.L17:
movl %ebx, %ecx
movss 0(%rbp,%rbx,4), %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %ebx, %xmm1
ucomiss %xmm1, %xmm0
jp .L19
je .L15
jmp .L19
.L25:
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z39__device_stub__Z11testKernel2PfP6float4PfP6float4
.type _Z39__device_stub__Z11testKernel2PfP6float4PfP6float4, @function
_Z39__device_stub__Z11testKernel2PfP6float4PfP6float4:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11testKernel2PfP6float4(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z39__device_stub__Z11testKernel2PfP6float4PfP6float4, .-_Z39__device_stub__Z11testKernel2PfP6float4PfP6float4
.globl _Z11testKernel2PfP6float4
.type _Z11testKernel2PfP6float4, @function
_Z11testKernel2PfP6float4:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z11testKernel2PfP6float4PfP6float4
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z11testKernel2PfP6float4, .-_Z11testKernel2PfP6float4
.globl _Z39__device_stub__Z11testKernel3P6float4PfP6float4Pf
.type _Z39__device_stub__Z11testKernel3P6float4PfP6float4Pf, @function
_Z39__device_stub__Z11testKernel3P6float4PfP6float4Pf:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11testKernel3P6float4Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z39__device_stub__Z11testKernel3P6float4PfP6float4Pf, .-_Z39__device_stub__Z11testKernel3P6float4PfP6float4Pf
.globl _Z11testKernel3P6float4Pf
.type _Z11testKernel3P6float4Pf, @function
_Z11testKernel3P6float4Pf:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z11testKernel3P6float4PfP6float4Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z11testKernel3P6float4Pf, .-_Z11testKernel3P6float4Pf
.globl _Z33__device_stub__Z11testKernel4PfS_PfS_
.type _Z33__device_stub__Z11testKernel4PfS_PfS_, @function
_Z33__device_stub__Z11testKernel4PfS_PfS_:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11testKernel4PfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z33__device_stub__Z11testKernel4PfS_PfS_, .-_Z33__device_stub__Z11testKernel4PfS_PfS_
.globl _Z11testKernel4PfS_
.type _Z11testKernel4PfS_, @function
_Z11testKernel4PfS_:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z11testKernel4PfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z11testKernel4PfS_, .-_Z11testKernel4PfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z11testKernel4PfS_"
.LC2:
.string "_Z11testKernel3P6float4Pf"
.LC3:
.string "_Z11testKernel2PfP6float4"
.LC4:
.string "_Z11testKernel1P6float4S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z11testKernel4PfS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z11testKernel3P6float4Pf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z11testKernel2PfP6float4(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z11testKernel1P6float4S0_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
#define CUDA_DEVICE (0)
#define NUM_THREADS (1<<13)
#define BLOCK_DIM (64)
#define GRID_DIM (NUM_THREADS/BLOCK_DIM)
#define NUM_BYTES (NUM_THREADS*4*sizeof(float))
// Compile and run with the commands:
// nvcc float4_test.cu
// ./a.out
//
// Failure occurs on my Tesla C870 card when KERNEL_INVOCATIONS is a large
// number (e.g. 100), and TEST_KERNEL is 1 or 3. Kernels 1 and 3 are those
// which write float4 values to device memory. Failure does not occur on
// my Quadro NVS 290 card for any of the kernels.
//
#define KERNEL_INVOCATIONS (100)
#define TEST_KERNEL (1)
__global__ void testKernel1(float4* g_out, float4* g_in) {
const int idx = blockDim.x*blockIdx.x + threadIdx.x;
g_out[idx] = g_in[idx];
}
__global__ void testKernel2(float* g_out, float4* g_in) {
const int idx = BLOCK_DIM*blockIdx.x + threadIdx.x;
float4 f4 = g_in[idx];
g_out[4*idx+0] = f4.x;
g_out[4*idx+1] = f4.y;
g_out[4*idx+2] = f4.z;
g_out[4*idx+3] = f4.w;
}
__global__ void testKernel3(float4* g_out, float* g_in) {
const int idx = BLOCK_DIM*blockIdx.x + threadIdx.x;
float x = g_in[4*idx+0];
float y = g_in[4*idx+1];
float z = g_in[4*idx+2];
float w = g_in[4*idx+3];
g_out[idx] = make_float4(x, y, z, w);
}
__global__ void testKernel4(float* g_out, float* g_in) {
const int idx = BLOCK_DIM*blockIdx.x + threadIdx.x;
g_out[NUM_THREADS*0 + idx] = g_in[NUM_THREADS*0 + idx];
g_out[NUM_THREADS*1 + idx] = g_in[NUM_THREADS*1 + idx];
g_out[NUM_THREADS*2 + idx] = g_in[NUM_THREADS*2 + idx];
g_out[NUM_THREADS*3 + idx] = g_in[NUM_THREADS*3 + idx];
}
int main( int argc, char** argv) {
cudaSetDevice(CUDA_DEVICE);
float *input = (float *)malloc(NUM_BYTES);
float *output = (float *)malloc(NUM_BYTES);
void* d_input;
void* d_output;
cudaMalloc(&d_input, NUM_BYTES);
cudaMalloc(&d_output, NUM_BYTES);
for (int i = 0; i < NUM_THREADS*4; i++) {
input[i] = i;
}
cudaMemcpy(d_input, input, NUM_BYTES, cudaMemcpyHostToDevice);
dim3 gridDim(GRID_DIM, 1, 1);
dim3 blockDim(BLOCK_DIM, 1, 1);
for (int i = 0; i < KERNEL_INVOCATIONS; i++) {
switch (TEST_KERNEL) {
case 1:
testKernel1 <<<gridDim, blockDim>>> ((float4 *)d_output, (float4 *)d_input);
break;
case 2:
testKernel2 <<<gridDim, blockDim>>> ((float *)d_output, (float4 *)d_input);
break;
case 3:
testKernel3 <<<gridDim, blockDim>>> ((float4 *)d_output, (float *)d_input);
break;
case 4:
testKernel4 <<<gridDim, blockDim>>> ((float *)d_output, (float *)d_input);
break;
}
cudaThreadSynchronize();
}
cudaMemcpy(output, d_output, NUM_BYTES, cudaMemcpyDeviceToHost);
for (int i = 0; i < NUM_THREADS*4; i++) {
if (output[i] != i) {
printf("KERNEL=%d FAILED: elem #%d = %f\n", TEST_KERNEL, i, output[i]);
}
}
free(input);
free(output);
cudaFree(d_input);
cudaFree(d_output);
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#define CUDA_DEVICE (0)
#define NUM_THREADS (1<<13)
#define BLOCK_DIM (64)
#define GRID_DIM (NUM_THREADS/BLOCK_DIM)
#define NUM_BYTES (NUM_THREADS*4*sizeof(float))
// Compile and run with the commands:
// nvcc float4_test.cu
// ./a.out
//
// Failure occurs on my Tesla C870 card when KERNEL_INVOCATIONS is a large
// number (e.g. 100), and TEST_KERNEL is 1 or 3. Kernels 1 and 3 are those
// which write float4 values to device memory. Failure does not occur on
// my Quadro NVS 290 card for any of the kernels.
//
#define KERNEL_INVOCATIONS (100)
#define TEST_KERNEL (1)
__global__ void testKernel1(float4* g_out, float4* g_in) {
const int idx = blockDim.x*blockIdx.x + threadIdx.x;
g_out[idx] = g_in[idx];
}
__global__ void testKernel2(float* g_out, float4* g_in) {
const int idx = BLOCK_DIM*blockIdx.x + threadIdx.x;
float4 f4 = g_in[idx];
g_out[4*idx+0] = f4.x;
g_out[4*idx+1] = f4.y;
g_out[4*idx+2] = f4.z;
g_out[4*idx+3] = f4.w;
}
__global__ void testKernel3(float4* g_out, float* g_in) {
const int idx = BLOCK_DIM*blockIdx.x + threadIdx.x;
float x = g_in[4*idx+0];
float y = g_in[4*idx+1];
float z = g_in[4*idx+2];
float w = g_in[4*idx+3];
g_out[idx] = make_float4(x, y, z, w);
}
__global__ void testKernel4(float* g_out, float* g_in) {
const int idx = BLOCK_DIM*blockIdx.x + threadIdx.x;
g_out[NUM_THREADS*0 + idx] = g_in[NUM_THREADS*0 + idx];
g_out[NUM_THREADS*1 + idx] = g_in[NUM_THREADS*1 + idx];
g_out[NUM_THREADS*2 + idx] = g_in[NUM_THREADS*2 + idx];
g_out[NUM_THREADS*3 + idx] = g_in[NUM_THREADS*3 + idx];
}
int main( int argc, char** argv) {
hipSetDevice(CUDA_DEVICE);
float *input = (float *)malloc(NUM_BYTES);
float *output = (float *)malloc(NUM_BYTES);
void* d_input;
void* d_output;
hipMalloc(&d_input, NUM_BYTES);
hipMalloc(&d_output, NUM_BYTES);
for (int i = 0; i < NUM_THREADS*4; i++) {
input[i] = i;
}
hipMemcpy(d_input, input, NUM_BYTES, hipMemcpyHostToDevice);
dim3 gridDim(GRID_DIM, 1, 1);
dim3 blockDim(BLOCK_DIM, 1, 1);
for (int i = 0; i < KERNEL_INVOCATIONS; i++) {
switch (TEST_KERNEL) {
case 1:
testKernel1 <<<gridDim, blockDim>>> ((float4 *)d_output, (float4 *)d_input);
break;
case 2:
testKernel2 <<<gridDim, blockDim>>> ((float *)d_output, (float4 *)d_input);
break;
case 3:
testKernel3 <<<gridDim, blockDim>>> ((float4 *)d_output, (float *)d_input);
break;
case 4:
testKernel4 <<<gridDim, blockDim>>> ((float *)d_output, (float *)d_input);
break;
}
hipDeviceSynchronize();
}
hipMemcpy(output, d_output, NUM_BYTES, hipMemcpyDeviceToHost);
for (int i = 0; i < NUM_THREADS*4; i++) {
if (output[i] != i) {
printf("KERNEL=%d FAILED: elem #%d = %f\n", TEST_KERNEL, i, output[i]);
}
}
free(input);
free(output);
hipFree(d_input);
hipFree(d_output);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#define CUDA_DEVICE (0)
#define NUM_THREADS (1<<13)
#define BLOCK_DIM (64)
#define GRID_DIM (NUM_THREADS/BLOCK_DIM)
#define NUM_BYTES (NUM_THREADS*4*sizeof(float))
// Compile and run with the commands:
// nvcc float4_test.cu
// ./a.out
//
// Failure occurs on my Tesla C870 card when KERNEL_INVOCATIONS is a large
// number (e.g. 100), and TEST_KERNEL is 1 or 3. Kernels 1 and 3 are those
// which write float4 values to device memory. Failure does not occur on
// my Quadro NVS 290 card for any of the kernels.
//
#define KERNEL_INVOCATIONS (100)
#define TEST_KERNEL (1)
__global__ void testKernel1(float4* g_out, float4* g_in) {
const int idx = blockDim.x*blockIdx.x + threadIdx.x;
g_out[idx] = g_in[idx];
}
__global__ void testKernel2(float* g_out, float4* g_in) {
const int idx = BLOCK_DIM*blockIdx.x + threadIdx.x;
float4 f4 = g_in[idx];
g_out[4*idx+0] = f4.x;
g_out[4*idx+1] = f4.y;
g_out[4*idx+2] = f4.z;
g_out[4*idx+3] = f4.w;
}
__global__ void testKernel3(float4* g_out, float* g_in) {
const int idx = BLOCK_DIM*blockIdx.x + threadIdx.x;
float x = g_in[4*idx+0];
float y = g_in[4*idx+1];
float z = g_in[4*idx+2];
float w = g_in[4*idx+3];
g_out[idx] = make_float4(x, y, z, w);
}
__global__ void testKernel4(float* g_out, float* g_in) {
const int idx = BLOCK_DIM*blockIdx.x + threadIdx.x;
g_out[NUM_THREADS*0 + idx] = g_in[NUM_THREADS*0 + idx];
g_out[NUM_THREADS*1 + idx] = g_in[NUM_THREADS*1 + idx];
g_out[NUM_THREADS*2 + idx] = g_in[NUM_THREADS*2 + idx];
g_out[NUM_THREADS*3 + idx] = g_in[NUM_THREADS*3 + idx];
}
int main( int argc, char** argv) {
hipSetDevice(CUDA_DEVICE);
float *input = (float *)malloc(NUM_BYTES);
float *output = (float *)malloc(NUM_BYTES);
void* d_input;
void* d_output;
hipMalloc(&d_input, NUM_BYTES);
hipMalloc(&d_output, NUM_BYTES);
for (int i = 0; i < NUM_THREADS*4; i++) {
input[i] = i;
}
hipMemcpy(d_input, input, NUM_BYTES, hipMemcpyHostToDevice);
dim3 gridDim(GRID_DIM, 1, 1);
dim3 blockDim(BLOCK_DIM, 1, 1);
for (int i = 0; i < KERNEL_INVOCATIONS; i++) {
switch (TEST_KERNEL) {
case 1:
testKernel1 <<<gridDim, blockDim>>> ((float4 *)d_output, (float4 *)d_input);
break;
case 2:
testKernel2 <<<gridDim, blockDim>>> ((float *)d_output, (float4 *)d_input);
break;
case 3:
testKernel3 <<<gridDim, blockDim>>> ((float4 *)d_output, (float *)d_input);
break;
case 4:
testKernel4 <<<gridDim, blockDim>>> ((float *)d_output, (float *)d_input);
break;
}
hipDeviceSynchronize();
}
hipMemcpy(output, d_output, NUM_BYTES, hipMemcpyDeviceToHost);
for (int i = 0; i < NUM_THREADS*4; i++) {
if (output[i] != i) {
printf("KERNEL=%d FAILED: elem #%d = %f\n", TEST_KERNEL, i, output[i]);
}
}
free(input);
free(output);
hipFree(d_input);
hipFree(d_output);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11testKernel1P15HIP_vector_typeIfLj4EES1_
.globl _Z11testKernel1P15HIP_vector_typeIfLj4EES1_
.p2align 8
.type _Z11testKernel1P15HIP_vector_typeIfLj4EES1_,@function
_Z11testKernel1P15HIP_vector_typeIfLj4EES1_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 4, v[1:2]
v_add_co_u32 v0, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_load_b128 v[0:3], v[0:1], off
s_waitcnt vmcnt(0)
global_store_b128 v[4:5], v[0:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11testKernel1P15HIP_vector_typeIfLj4EES1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11testKernel1P15HIP_vector_typeIfLj4EES1_, .Lfunc_end0-_Z11testKernel1P15HIP_vector_typeIfLj4EES1_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11testKernel2PfP15HIP_vector_typeIfLj4EE
.globl _Z11testKernel2PfP15HIP_vector_typeIfLj4EE
.p2align 8
.type _Z11testKernel2PfP15HIP_vector_typeIfLj4EE,@function
_Z11testKernel2PfP15HIP_vector_typeIfLj4EE:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshl_add_u32 v4, s15, 6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[0:1], 4, v[4:5]
v_lshlrev_b32_e32 v4, 2, v4
s_delay_alu instid0(VALU_DEP_1)
v_or_b32_e32 v6, 1, v4
v_ashrrev_i32_e32 v5, 31, v4
v_or_b32_e32 v8, 2, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_ashrrev_i32_e32 v7, 31, v6
v_or_b32_e32 v10, 3, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
global_load_b128 v[0:3], v[0:1], off
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_ashrrev_i32_e32 v11, 31, v10
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
v_lshlrev_b64 v[10:11], 2, v[10:11]
v_add_co_u32 v6, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, s0, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v9, vcc_lo
v_add_co_u32 v10, vcc_lo, s0, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s1, v11, vcc_lo
s_waitcnt vmcnt(0)
s_clause 0x3
global_store_b32 v[4:5], v0, off
global_store_b32 v[6:7], v1, off
global_store_b32 v[8:9], v2, off
global_store_b32 v[10:11], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11testKernel2PfP15HIP_vector_typeIfLj4EE
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z11testKernel2PfP15HIP_vector_typeIfLj4EE, .Lfunc_end1-_Z11testKernel2PfP15HIP_vector_typeIfLj4EE
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11testKernel3P15HIP_vector_typeIfLj4EEPf
.globl _Z11testKernel3P15HIP_vector_typeIfLj4EEPf
.p2align 8
.type _Z11testKernel3P15HIP_vector_typeIfLj4EEPf,@function
_Z11testKernel3P15HIP_vector_typeIfLj4EEPf:
v_lshl_add_u32 v4, s15, 6, v0
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v0, 2, v4
v_or_b32_e32 v2, 1, v0
v_ashrrev_i32_e32 v1, 31, v0
v_or_b32_e32 v5, 2, v0
v_or_b32_e32 v7, 3, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
s_clause 0x3
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[2:3], off
global_load_b32 v2, v[5:6], off
global_load_b32 v3, v[7:8], off
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 4, v[4:5]
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_waitcnt vmcnt(0)
global_store_b128 v[4:5], v[0:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11testKernel3P15HIP_vector_typeIfLj4EEPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z11testKernel3P15HIP_vector_typeIfLj4EEPf, .Lfunc_end2-_Z11testKernel3P15HIP_vector_typeIfLj4EEPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11testKernel4PfS_
.globl _Z11testKernel4PfS_
.p2align 8
.type _Z11testKernel4PfS_,@function
_Z11testKernel4PfS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshl_add_u32 v0, s15, 6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v7, vcc_lo, v0, 0x8000
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v1, vcc_lo
global_load_b32 v6, v[2:3], off
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v8, vcc_lo
v_add_co_u32 v9, vcc_lo, v0, 0x10000
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v6, off
global_load_b32 v6, v[4:5], off
v_add_co_u32 v2, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v8, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v9
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v10, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v6, off
global_load_b32 v4, v[4:5], off
v_add_co_u32 v5, vcc_lo, v0, 0x18000
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v9
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v6, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
global_load_b32 v2, v[2:3], off
v_add_co_u32 v0, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v6, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11testKernel4PfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z11testKernel4PfS_, .Lfunc_end3-_Z11testKernel4PfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11testKernel1P15HIP_vector_typeIfLj4EES1_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11testKernel1P15HIP_vector_typeIfLj4EES1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11testKernel2PfP15HIP_vector_typeIfLj4EE
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11testKernel2PfP15HIP_vector_typeIfLj4EE.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11testKernel3P15HIP_vector_typeIfLj4EEPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11testKernel3P15HIP_vector_typeIfLj4EEPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11testKernel4PfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11testKernel4PfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#define CUDA_DEVICE (0)
#define NUM_THREADS (1<<13)
#define BLOCK_DIM (64)
#define GRID_DIM (NUM_THREADS/BLOCK_DIM)
#define NUM_BYTES (NUM_THREADS*4*sizeof(float))
// Compile and run with the commands:
// nvcc float4_test.cu
// ./a.out
//
// Failure occurs on my Tesla C870 card when KERNEL_INVOCATIONS is a large
// number (e.g. 100), and TEST_KERNEL is 1 or 3. Kernels 1 and 3 are those
// which write float4 values to device memory. Failure does not occur on
// my Quadro NVS 290 card for any of the kernels.
//
#define KERNEL_INVOCATIONS (100)
#define TEST_KERNEL (1)
__global__ void testKernel1(float4* g_out, float4* g_in) {
const int idx = blockDim.x*blockIdx.x + threadIdx.x;
g_out[idx] = g_in[idx];
}
__global__ void testKernel2(float* g_out, float4* g_in) {
const int idx = BLOCK_DIM*blockIdx.x + threadIdx.x;
float4 f4 = g_in[idx];
g_out[4*idx+0] = f4.x;
g_out[4*idx+1] = f4.y;
g_out[4*idx+2] = f4.z;
g_out[4*idx+3] = f4.w;
}
__global__ void testKernel3(float4* g_out, float* g_in) {
const int idx = BLOCK_DIM*blockIdx.x + threadIdx.x;
float x = g_in[4*idx+0];
float y = g_in[4*idx+1];
float z = g_in[4*idx+2];
float w = g_in[4*idx+3];
g_out[idx] = make_float4(x, y, z, w);
}
__global__ void testKernel4(float* g_out, float* g_in) {
const int idx = BLOCK_DIM*blockIdx.x + threadIdx.x;
g_out[NUM_THREADS*0 + idx] = g_in[NUM_THREADS*0 + idx];
g_out[NUM_THREADS*1 + idx] = g_in[NUM_THREADS*1 + idx];
g_out[NUM_THREADS*2 + idx] = g_in[NUM_THREADS*2 + idx];
g_out[NUM_THREADS*3 + idx] = g_in[NUM_THREADS*3 + idx];
}
int main( int argc, char** argv) {
hipSetDevice(CUDA_DEVICE);
float *input = (float *)malloc(NUM_BYTES);
float *output = (float *)malloc(NUM_BYTES);
void* d_input;
void* d_output;
hipMalloc(&d_input, NUM_BYTES);
hipMalloc(&d_output, NUM_BYTES);
for (int i = 0; i < NUM_THREADS*4; i++) {
input[i] = i;
}
hipMemcpy(d_input, input, NUM_BYTES, hipMemcpyHostToDevice);
dim3 gridDim(GRID_DIM, 1, 1);
dim3 blockDim(BLOCK_DIM, 1, 1);
for (int i = 0; i < KERNEL_INVOCATIONS; i++) {
switch (TEST_KERNEL) {
case 1:
testKernel1 <<<gridDim, blockDim>>> ((float4 *)d_output, (float4 *)d_input);
break;
case 2:
testKernel2 <<<gridDim, blockDim>>> ((float *)d_output, (float4 *)d_input);
break;
case 3:
testKernel3 <<<gridDim, blockDim>>> ((float4 *)d_output, (float *)d_input);
break;
case 4:
testKernel4 <<<gridDim, blockDim>>> ((float *)d_output, (float *)d_input);
break;
}
hipDeviceSynchronize();
}
hipMemcpy(output, d_output, NUM_BYTES, hipMemcpyDeviceToHost);
for (int i = 0; i < NUM_THREADS*4; i++) {
if (output[i] != i) {
printf("KERNEL=%d FAILED: elem #%d = %f\n", TEST_KERNEL, i, output[i]);
}
}
free(input);
free(output);
hipFree(d_input);
hipFree(d_output);
} | .text
.file "float4_test.hip"
.globl _Z26__device_stub__testKernel1P15HIP_vector_typeIfLj4EES1_ # -- Begin function _Z26__device_stub__testKernel1P15HIP_vector_typeIfLj4EES1_
.p2align 4, 0x90
.type _Z26__device_stub__testKernel1P15HIP_vector_typeIfLj4EES1_,@function
_Z26__device_stub__testKernel1P15HIP_vector_typeIfLj4EES1_: # @_Z26__device_stub__testKernel1P15HIP_vector_typeIfLj4EES1_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11testKernel1P15HIP_vector_typeIfLj4EES1_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__testKernel1P15HIP_vector_typeIfLj4EES1_, .Lfunc_end0-_Z26__device_stub__testKernel1P15HIP_vector_typeIfLj4EES1_
.cfi_endproc
# -- End function
.globl _Z26__device_stub__testKernel2PfP15HIP_vector_typeIfLj4EE # -- Begin function _Z26__device_stub__testKernel2PfP15HIP_vector_typeIfLj4EE
.p2align 4, 0x90
.type _Z26__device_stub__testKernel2PfP15HIP_vector_typeIfLj4EE,@function
_Z26__device_stub__testKernel2PfP15HIP_vector_typeIfLj4EE: # @_Z26__device_stub__testKernel2PfP15HIP_vector_typeIfLj4EE
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11testKernel2PfP15HIP_vector_typeIfLj4EE, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z26__device_stub__testKernel2PfP15HIP_vector_typeIfLj4EE, .Lfunc_end1-_Z26__device_stub__testKernel2PfP15HIP_vector_typeIfLj4EE
.cfi_endproc
# -- End function
.globl _Z26__device_stub__testKernel3P15HIP_vector_typeIfLj4EEPf # -- Begin function _Z26__device_stub__testKernel3P15HIP_vector_typeIfLj4EEPf
.p2align 4, 0x90
.type _Z26__device_stub__testKernel3P15HIP_vector_typeIfLj4EEPf,@function
_Z26__device_stub__testKernel3P15HIP_vector_typeIfLj4EEPf: # @_Z26__device_stub__testKernel3P15HIP_vector_typeIfLj4EEPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11testKernel3P15HIP_vector_typeIfLj4EEPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z26__device_stub__testKernel3P15HIP_vector_typeIfLj4EEPf, .Lfunc_end2-_Z26__device_stub__testKernel3P15HIP_vector_typeIfLj4EEPf
.cfi_endproc
# -- End function
.globl _Z26__device_stub__testKernel4PfS_ # -- Begin function _Z26__device_stub__testKernel4PfS_
.p2align 4, 0x90
.type _Z26__device_stub__testKernel4PfS_,@function
_Z26__device_stub__testKernel4PfS_: # @_Z26__device_stub__testKernel4PfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11testKernel4PfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z26__device_stub__testKernel4PfS_, .Lfunc_end3-_Z26__device_stub__testKernel4PfS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %r15d, %r15d
xorl %edi, %edi
callq hipSetDevice
movl $131072, %edi # imm = 0x20000
callq malloc
movq %rax, %rbx
movl $131072, %edi # imm = 0x20000
callq malloc
movq %rax, %r14
leaq 8(%rsp), %rdi
movl $131072, %esi # imm = 0x20000
callq hipMalloc
movq %rsp, %rdi
movl $131072, %esi # imm = 0x20000
callq hipMalloc
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %r15d, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq $32768, %r15 # imm = 0x8000
jne .LBB4_1
# %bb.2:
movabsq $4294967360, %r15 # imm = 0x100000040
movq 8(%rsp), %rdi
movl $131072, %edx # imm = 0x20000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $100, %ebp
leaq 64(%r15), %r12
leaq 80(%rsp), %r13
jmp .LBB4_3
.p2align 4, 0x90
.LBB4_5: # in Loop: Header=BB4_3 Depth=1
callq hipDeviceSynchronize
decl %ebp
je .LBB4_6
.LBB4_3: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_5
# %bb.4: # in Loop: Header=BB4_3 Depth=1
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z11testKernel1P15HIP_vector_typeIfLj4EES1_, %edi
movq %r13, %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB4_5
.LBB4_6:
movq (%rsp), %rsi
movl $131072, %edx # imm = 0x20000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
jmp .LBB4_7
.p2align 4, 0x90
.LBB4_9: # in Loop: Header=BB4_7 Depth=1
incq %r15
cmpq $32768, %r15 # imm = 0x8000
je .LBB4_10
.LBB4_7: # =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2ss %r15d, %xmm1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jne .LBB4_8
jnp .LBB4_9
.LBB4_8: # in Loop: Header=BB4_7 Depth=1
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movl $1, %esi
movl %r15d, %edx
movb $1, %al
callq printf
jmp .LBB4_9
.LBB4_10:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11testKernel1P15HIP_vector_typeIfLj4EES1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11testKernel2PfP15HIP_vector_typeIfLj4EE, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11testKernel3P15HIP_vector_typeIfLj4EEPf, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11testKernel4PfS_, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11testKernel1P15HIP_vector_typeIfLj4EES1_,@object # @_Z11testKernel1P15HIP_vector_typeIfLj4EES1_
.section .rodata,"a",@progbits
.globl _Z11testKernel1P15HIP_vector_typeIfLj4EES1_
.p2align 3, 0x0
_Z11testKernel1P15HIP_vector_typeIfLj4EES1_:
.quad _Z26__device_stub__testKernel1P15HIP_vector_typeIfLj4EES1_
.size _Z11testKernel1P15HIP_vector_typeIfLj4EES1_, 8
.type _Z11testKernel2PfP15HIP_vector_typeIfLj4EE,@object # @_Z11testKernel2PfP15HIP_vector_typeIfLj4EE
.globl _Z11testKernel2PfP15HIP_vector_typeIfLj4EE
.p2align 3, 0x0
_Z11testKernel2PfP15HIP_vector_typeIfLj4EE:
.quad _Z26__device_stub__testKernel2PfP15HIP_vector_typeIfLj4EE
.size _Z11testKernel2PfP15HIP_vector_typeIfLj4EE, 8
.type _Z11testKernel3P15HIP_vector_typeIfLj4EEPf,@object # @_Z11testKernel3P15HIP_vector_typeIfLj4EEPf
.globl _Z11testKernel3P15HIP_vector_typeIfLj4EEPf
.p2align 3, 0x0
_Z11testKernel3P15HIP_vector_typeIfLj4EEPf:
.quad _Z26__device_stub__testKernel3P15HIP_vector_typeIfLj4EEPf
.size _Z11testKernel3P15HIP_vector_typeIfLj4EEPf, 8
.type _Z11testKernel4PfS_,@object # @_Z11testKernel4PfS_
.globl _Z11testKernel4PfS_
.p2align 3, 0x0
_Z11testKernel4PfS_:
.quad _Z26__device_stub__testKernel4PfS_
.size _Z11testKernel4PfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "KERNEL=%d FAILED: elem #%d = %f\n"
.size .L.str, 33
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11testKernel1P15HIP_vector_typeIfLj4EES1_"
.size .L__unnamed_1, 44
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11testKernel2PfP15HIP_vector_typeIfLj4EE"
.size .L__unnamed_2, 43
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z11testKernel3P15HIP_vector_typeIfLj4EEPf"
.size .L__unnamed_3, 43
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z11testKernel4PfS_"
.size .L__unnamed_4, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__testKernel1P15HIP_vector_typeIfLj4EES1_
.addrsig_sym _Z26__device_stub__testKernel2PfP15HIP_vector_typeIfLj4EE
.addrsig_sym _Z26__device_stub__testKernel3P15HIP_vector_typeIfLj4EEPf
.addrsig_sym _Z26__device_stub__testKernel4PfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11testKernel1P15HIP_vector_typeIfLj4EES1_
.addrsig_sym _Z11testKernel2PfP15HIP_vector_typeIfLj4EE
.addrsig_sym _Z11testKernel3P15HIP_vector_typeIfLj4EEPf
.addrsig_sym _Z11testKernel4PfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11testKernel4PfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ LEA R4, R4, R3, 0x6 ; /* 0x0000000304047211 */
/* 0x001fca00078e30ff */
/*0060*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*0090*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x004fe8000c101904 */
/*00a0*/ LDG.E R9, [R2.64+0x8000] ; /* 0x0080000402097981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ STG.E [R4.64+0x8000], R9 ; /* 0x0080000904007986 */
/* 0x004fe8000c101904 */
/*00c0*/ LDG.E R11, [R2.64+0x10000] ; /* 0x01000004020b7981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ STG.E [R4.64+0x10000], R11 ; /* 0x0100000b04007986 */
/* 0x004fe8000c101904 */
/*00e0*/ LDG.E R13, [R2.64+0x18000] ; /* 0x01800004020d7981 */
/* 0x000ea8000c1e1900 */
/*00f0*/ STG.E [R4.64+0x18000], R13 ; /* 0x0180000d04007986 */
/* 0x004fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11testKernel3P6float4Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ LEA R4, R4, R3, 0x6 ; /* 0x0000000304047211 */
/* 0x001fe200078e30ff */
/*0050*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fc600000001ff */
/*0060*/ SHF.L.U32 R2, R4, 0x2, RZ ; /* 0x0000000204027819 */
/* 0x000fce00000006ff */
/*0070*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*0080*/ LDG.E R11, [R2.64+0xc] ; /* 0x00000c04020b7981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R10, [R2.64+0x8] ; /* 0x00000804020a7981 */
/* 0x000ea8000c1e1900 */
/*00a0*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040402097981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ HFMA2.MMA R5, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff057435 */
/* 0x000fd400000001ff */
/*00d0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*00e0*/ STG.E.128 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x004fe2000c101d04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11testKernel2PfP6float4
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ LEA R0, R0, R3, 0x6 ; /* 0x0000000300007211 */
/* 0x001fca00078e30ff */
/*0060*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E.128 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1d00 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0090*/ SHF.L.U32 R4, R0, 0x2, RZ ; /* 0x0000000200047819 */
/* 0x000fd200000006ff */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*00b0*/ STG.E [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x004fe8000c101904 */
/*00c0*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x000fe8000c101904 */
/*00d0*/ STG.E [R4.64+0x8], R10 ; /* 0x0000080a04007986 */
/* 0x000fe8000c101904 */
/*00e0*/ STG.E [R4.64+0xc], R11 ; /* 0x00000c0b04007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11testKernel1P6float4S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R4, R2, R9, c[0x0][0x168] ; /* 0x00005a0002047625 */
/* 0x000fcc00078e0209 */
/*0070*/ LDG.E.128 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1d00 */
/*0080*/ IMAD.WIDE R2, R2, R9, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0209 */
/*0090*/ STG.E.128 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x004fe2000c101d04 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11testKernel1P15HIP_vector_typeIfLj4EES1_
.globl _Z11testKernel1P15HIP_vector_typeIfLj4EES1_
.p2align 8
.type _Z11testKernel1P15HIP_vector_typeIfLj4EES1_,@function
_Z11testKernel1P15HIP_vector_typeIfLj4EES1_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 4, v[1:2]
v_add_co_u32 v0, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_load_b128 v[0:3], v[0:1], off
s_waitcnt vmcnt(0)
global_store_b128 v[4:5], v[0:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11testKernel1P15HIP_vector_typeIfLj4EES1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11testKernel1P15HIP_vector_typeIfLj4EES1_, .Lfunc_end0-_Z11testKernel1P15HIP_vector_typeIfLj4EES1_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11testKernel2PfP15HIP_vector_typeIfLj4EE
.globl _Z11testKernel2PfP15HIP_vector_typeIfLj4EE
.p2align 8
.type _Z11testKernel2PfP15HIP_vector_typeIfLj4EE,@function
_Z11testKernel2PfP15HIP_vector_typeIfLj4EE:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshl_add_u32 v4, s15, 6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[0:1], 4, v[4:5]
v_lshlrev_b32_e32 v4, 2, v4
s_delay_alu instid0(VALU_DEP_1)
v_or_b32_e32 v6, 1, v4
v_ashrrev_i32_e32 v5, 31, v4
v_or_b32_e32 v8, 2, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_ashrrev_i32_e32 v7, 31, v6
v_or_b32_e32 v10, 3, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
global_load_b128 v[0:3], v[0:1], off
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_ashrrev_i32_e32 v11, 31, v10
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
v_lshlrev_b64 v[10:11], 2, v[10:11]
v_add_co_u32 v6, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, s0, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v9, vcc_lo
v_add_co_u32 v10, vcc_lo, s0, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s1, v11, vcc_lo
s_waitcnt vmcnt(0)
s_clause 0x3
global_store_b32 v[4:5], v0, off
global_store_b32 v[6:7], v1, off
global_store_b32 v[8:9], v2, off
global_store_b32 v[10:11], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11testKernel2PfP15HIP_vector_typeIfLj4EE
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z11testKernel2PfP15HIP_vector_typeIfLj4EE, .Lfunc_end1-_Z11testKernel2PfP15HIP_vector_typeIfLj4EE
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11testKernel3P15HIP_vector_typeIfLj4EEPf
.globl _Z11testKernel3P15HIP_vector_typeIfLj4EEPf
.p2align 8
.type _Z11testKernel3P15HIP_vector_typeIfLj4EEPf,@function
_Z11testKernel3P15HIP_vector_typeIfLj4EEPf:
v_lshl_add_u32 v4, s15, 6, v0
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v0, 2, v4
v_or_b32_e32 v2, 1, v0
v_ashrrev_i32_e32 v1, 31, v0
v_or_b32_e32 v5, 2, v0
v_or_b32_e32 v7, 3, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
s_clause 0x3
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[2:3], off
global_load_b32 v2, v[5:6], off
global_load_b32 v3, v[7:8], off
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 4, v[4:5]
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_waitcnt vmcnt(0)
global_store_b128 v[4:5], v[0:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11testKernel3P15HIP_vector_typeIfLj4EEPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z11testKernel3P15HIP_vector_typeIfLj4EEPf, .Lfunc_end2-_Z11testKernel3P15HIP_vector_typeIfLj4EEPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11testKernel4PfS_
.globl _Z11testKernel4PfS_
.p2align 8
.type _Z11testKernel4PfS_,@function
_Z11testKernel4PfS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshl_add_u32 v0, s15, 6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v7, vcc_lo, v0, 0x8000
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v1, vcc_lo
global_load_b32 v6, v[2:3], off
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v8, vcc_lo
v_add_co_u32 v9, vcc_lo, v0, 0x10000
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v6, off
global_load_b32 v6, v[4:5], off
v_add_co_u32 v2, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v8, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v9
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v10, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v6, off
global_load_b32 v4, v[4:5], off
v_add_co_u32 v5, vcc_lo, v0, 0x18000
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v9
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v6, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
global_load_b32 v2, v[2:3], off
v_add_co_u32 v0, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v6, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11testKernel4PfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z11testKernel4PfS_, .Lfunc_end3-_Z11testKernel4PfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11testKernel1P15HIP_vector_typeIfLj4EES1_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11testKernel1P15HIP_vector_typeIfLj4EES1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11testKernel2PfP15HIP_vector_typeIfLj4EE
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11testKernel2PfP15HIP_vector_typeIfLj4EE.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11testKernel3P15HIP_vector_typeIfLj4EEPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11testKernel3P15HIP_vector_typeIfLj4EEPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11testKernel4PfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11testKernel4PfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016f5bc_00000000-6_float4_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z11testKernel1P6float4S0_P6float4S0_
.type _Z40__device_stub__Z11testKernel1P6float4S0_P6float4S0_, @function
_Z40__device_stub__Z11testKernel1P6float4S0_P6float4S0_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11testKernel1P6float4S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z40__device_stub__Z11testKernel1P6float4S0_P6float4S0_, .-_Z40__device_stub__Z11testKernel1P6float4S0_P6float4S0_
.globl _Z11testKernel1P6float4S0_
.type _Z11testKernel1P6float4S0_, @function
_Z11testKernel1P6float4S0_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z11testKernel1P6float4S0_P6float4S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11testKernel1P6float4S0_, .-_Z11testKernel1P6float4S0_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "KERNEL=%d FAILED: elem #%d = %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
movl $131072, %edi
call malloc@PLT
movq %rax, %r12
movl $131072, %edi
call malloc@PLT
movq %rax, %rbp
movq %rsp, %rdi
movl $131072, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $131072, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%r12,%rax,4)
addq $1, %rax
cmpq $32768, %rax
jne .L12
movl $1, %ecx
movl $131072, %edx
movq %r12, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $64, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $100, %ebx
jmp .L14
.L13:
call cudaThreadSynchronize@PLT
subl $1, %ebx
je .L24
.L14:
movl 36(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movq 16(%rsp), %rdi
movl 24(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z40__device_stub__Z11testKernel1P6float4S0_P6float4S0_
jmp .L13
.L24:
movl $2, %ecx
movl $131072, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %r13
jmp .L17
.L19:
cvtss2sd %xmm0, %xmm0
movl $1, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L15:
addq $1, %rbx
cmpq $32768, %rbx
je .L25
.L17:
movl %ebx, %ecx
movss 0(%rbp,%rbx,4), %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %ebx, %xmm1
ucomiss %xmm1, %xmm0
jp .L19
je .L15
jmp .L19
.L25:
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z39__device_stub__Z11testKernel2PfP6float4PfP6float4
.type _Z39__device_stub__Z11testKernel2PfP6float4PfP6float4, @function
_Z39__device_stub__Z11testKernel2PfP6float4PfP6float4:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11testKernel2PfP6float4(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z39__device_stub__Z11testKernel2PfP6float4PfP6float4, .-_Z39__device_stub__Z11testKernel2PfP6float4PfP6float4
.globl _Z11testKernel2PfP6float4
.type _Z11testKernel2PfP6float4, @function
_Z11testKernel2PfP6float4:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z11testKernel2PfP6float4PfP6float4
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z11testKernel2PfP6float4, .-_Z11testKernel2PfP6float4
.globl _Z39__device_stub__Z11testKernel3P6float4PfP6float4Pf
.type _Z39__device_stub__Z11testKernel3P6float4PfP6float4Pf, @function
_Z39__device_stub__Z11testKernel3P6float4PfP6float4Pf:
.LFB2086:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11testKernel3P6float4Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z39__device_stub__Z11testKernel3P6float4PfP6float4Pf, .-_Z39__device_stub__Z11testKernel3P6float4PfP6float4Pf
.globl _Z11testKernel3P6float4Pf
.type _Z11testKernel3P6float4Pf, @function
_Z11testKernel3P6float4Pf:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z11testKernel3P6float4PfP6float4Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z11testKernel3P6float4Pf, .-_Z11testKernel3P6float4Pf
.globl _Z33__device_stub__Z11testKernel4PfS_PfS_
.type _Z33__device_stub__Z11testKernel4PfS_PfS_, @function
_Z33__device_stub__Z11testKernel4PfS_PfS_:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11testKernel4PfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z33__device_stub__Z11testKernel4PfS_PfS_, .-_Z33__device_stub__Z11testKernel4PfS_PfS_
.globl _Z11testKernel4PfS_
.type _Z11testKernel4PfS_, @function
_Z11testKernel4PfS_:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z11testKernel4PfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z11testKernel4PfS_, .-_Z11testKernel4PfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z11testKernel4PfS_"
.LC2:
.string "_Z11testKernel3P6float4Pf"
.LC3:
.string "_Z11testKernel2PfP6float4"
.LC4:
.string "_Z11testKernel1P6float4S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z11testKernel4PfS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z11testKernel3P6float4Pf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z11testKernel2PfP6float4(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z11testKernel1P6float4S0_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "float4_test.hip"
.globl _Z26__device_stub__testKernel1P15HIP_vector_typeIfLj4EES1_ # -- Begin function _Z26__device_stub__testKernel1P15HIP_vector_typeIfLj4EES1_
.p2align 4, 0x90
.type _Z26__device_stub__testKernel1P15HIP_vector_typeIfLj4EES1_,@function
_Z26__device_stub__testKernel1P15HIP_vector_typeIfLj4EES1_: # @_Z26__device_stub__testKernel1P15HIP_vector_typeIfLj4EES1_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11testKernel1P15HIP_vector_typeIfLj4EES1_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__testKernel1P15HIP_vector_typeIfLj4EES1_, .Lfunc_end0-_Z26__device_stub__testKernel1P15HIP_vector_typeIfLj4EES1_
.cfi_endproc
# -- End function
.globl _Z26__device_stub__testKernel2PfP15HIP_vector_typeIfLj4EE # -- Begin function _Z26__device_stub__testKernel2PfP15HIP_vector_typeIfLj4EE
.p2align 4, 0x90
.type _Z26__device_stub__testKernel2PfP15HIP_vector_typeIfLj4EE,@function
_Z26__device_stub__testKernel2PfP15HIP_vector_typeIfLj4EE: # @_Z26__device_stub__testKernel2PfP15HIP_vector_typeIfLj4EE
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11testKernel2PfP15HIP_vector_typeIfLj4EE, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z26__device_stub__testKernel2PfP15HIP_vector_typeIfLj4EE, .Lfunc_end1-_Z26__device_stub__testKernel2PfP15HIP_vector_typeIfLj4EE
.cfi_endproc
# -- End function
.globl _Z26__device_stub__testKernel3P15HIP_vector_typeIfLj4EEPf # -- Begin function _Z26__device_stub__testKernel3P15HIP_vector_typeIfLj4EEPf
.p2align 4, 0x90
.type _Z26__device_stub__testKernel3P15HIP_vector_typeIfLj4EEPf,@function
_Z26__device_stub__testKernel3P15HIP_vector_typeIfLj4EEPf: # @_Z26__device_stub__testKernel3P15HIP_vector_typeIfLj4EEPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11testKernel3P15HIP_vector_typeIfLj4EEPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z26__device_stub__testKernel3P15HIP_vector_typeIfLj4EEPf, .Lfunc_end2-_Z26__device_stub__testKernel3P15HIP_vector_typeIfLj4EEPf
.cfi_endproc
# -- End function
.globl _Z26__device_stub__testKernel4PfS_ # -- Begin function _Z26__device_stub__testKernel4PfS_
.p2align 4, 0x90
.type _Z26__device_stub__testKernel4PfS_,@function
_Z26__device_stub__testKernel4PfS_: # @_Z26__device_stub__testKernel4PfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11testKernel4PfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z26__device_stub__testKernel4PfS_, .Lfunc_end3-_Z26__device_stub__testKernel4PfS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %r15d, %r15d
xorl %edi, %edi
callq hipSetDevice
movl $131072, %edi # imm = 0x20000
callq malloc
movq %rax, %rbx
movl $131072, %edi # imm = 0x20000
callq malloc
movq %rax, %r14
leaq 8(%rsp), %rdi
movl $131072, %esi # imm = 0x20000
callq hipMalloc
movq %rsp, %rdi
movl $131072, %esi # imm = 0x20000
callq hipMalloc
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %r15d, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq $32768, %r15 # imm = 0x8000
jne .LBB4_1
# %bb.2:
movabsq $4294967360, %r15 # imm = 0x100000040
movq 8(%rsp), %rdi
movl $131072, %edx # imm = 0x20000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $100, %ebp
leaq 64(%r15), %r12
leaq 80(%rsp), %r13
jmp .LBB4_3
.p2align 4, 0x90
.LBB4_5: # in Loop: Header=BB4_3 Depth=1
callq hipDeviceSynchronize
decl %ebp
je .LBB4_6
.LBB4_3: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_5
# %bb.4: # in Loop: Header=BB4_3 Depth=1
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z11testKernel1P15HIP_vector_typeIfLj4EES1_, %edi
movq %r13, %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB4_5
.LBB4_6:
movq (%rsp), %rsi
movl $131072, %edx # imm = 0x20000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
jmp .LBB4_7
.p2align 4, 0x90
.LBB4_9: # in Loop: Header=BB4_7 Depth=1
incq %r15
cmpq $32768, %r15 # imm = 0x8000
je .LBB4_10
.LBB4_7: # =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2ss %r15d, %xmm1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jne .LBB4_8
jnp .LBB4_9
.LBB4_8: # in Loop: Header=BB4_7 Depth=1
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movl $1, %esi
movl %r15d, %edx
movb $1, %al
callq printf
jmp .LBB4_9
.LBB4_10:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11testKernel1P15HIP_vector_typeIfLj4EES1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11testKernel2PfP15HIP_vector_typeIfLj4EE, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11testKernel3P15HIP_vector_typeIfLj4EEPf, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11testKernel4PfS_, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11testKernel1P15HIP_vector_typeIfLj4EES1_,@object # @_Z11testKernel1P15HIP_vector_typeIfLj4EES1_
.section .rodata,"a",@progbits
.globl _Z11testKernel1P15HIP_vector_typeIfLj4EES1_
.p2align 3, 0x0
_Z11testKernel1P15HIP_vector_typeIfLj4EES1_:
.quad _Z26__device_stub__testKernel1P15HIP_vector_typeIfLj4EES1_
.size _Z11testKernel1P15HIP_vector_typeIfLj4EES1_, 8
.type _Z11testKernel2PfP15HIP_vector_typeIfLj4EE,@object # @_Z11testKernel2PfP15HIP_vector_typeIfLj4EE
.globl _Z11testKernel2PfP15HIP_vector_typeIfLj4EE
.p2align 3, 0x0
_Z11testKernel2PfP15HIP_vector_typeIfLj4EE:
.quad _Z26__device_stub__testKernel2PfP15HIP_vector_typeIfLj4EE
.size _Z11testKernel2PfP15HIP_vector_typeIfLj4EE, 8
.type _Z11testKernel3P15HIP_vector_typeIfLj4EEPf,@object # @_Z11testKernel3P15HIP_vector_typeIfLj4EEPf
.globl _Z11testKernel3P15HIP_vector_typeIfLj4EEPf
.p2align 3, 0x0
_Z11testKernel3P15HIP_vector_typeIfLj4EEPf:
.quad _Z26__device_stub__testKernel3P15HIP_vector_typeIfLj4EEPf
.size _Z11testKernel3P15HIP_vector_typeIfLj4EEPf, 8
.type _Z11testKernel4PfS_,@object # @_Z11testKernel4PfS_
.globl _Z11testKernel4PfS_
.p2align 3, 0x0
_Z11testKernel4PfS_:
.quad _Z26__device_stub__testKernel4PfS_
.size _Z11testKernel4PfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "KERNEL=%d FAILED: elem #%d = %f\n"
.size .L.str, 33
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11testKernel1P15HIP_vector_typeIfLj4EES1_"
.size .L__unnamed_1, 44
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11testKernel2PfP15HIP_vector_typeIfLj4EE"
.size .L__unnamed_2, 43
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z11testKernel3P15HIP_vector_typeIfLj4EEPf"
.size .L__unnamed_3, 43
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z11testKernel4PfS_"
.size .L__unnamed_4, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__testKernel1P15HIP_vector_typeIfLj4EES1_
.addrsig_sym _Z26__device_stub__testKernel2PfP15HIP_vector_typeIfLj4EE
.addrsig_sym _Z26__device_stub__testKernel3P15HIP_vector_typeIfLj4EEPf
.addrsig_sym _Z26__device_stub__testKernel4PfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11testKernel1P15HIP_vector_typeIfLj4EES1_
.addrsig_sym _Z11testKernel2PfP15HIP_vector_typeIfLj4EE
.addrsig_sym _Z11testKernel3P15HIP_vector_typeIfLj4EEPf
.addrsig_sym _Z11testKernel4PfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <random>
#include <cuda.h>
#include <stdio.h>
#include <curand.h>
#include <time.h>
int main()
{
curandGenerator_t gen;
// default (WOWXOR) or Mersenne-Trister pseudo random number generator
curandCreateGenerator(&gen, CURAND_RNG_PSEUDO_DEFAULT);
// curandCreateGenerator(&gen, CURAND_RNG_PSEUDO_MT19937);
// initialize the PRNG with seed
// std::random_device rd;
// unsigned int seed = rd();
unsigned int seed = time(0);
printf("seed = %u\n", seed);
curandSetPseudoRandomGeneratorSeed(gen, seed);
float *hostData, *devData;
int n=1<<24;
size_t memSize=sizeof(float)*n;
// host and device memory allocation
hostData = (float *)malloc(memSize);
cudaMalloc(&devData, memSize);
// generate n random numbers in (0,1] on the device array
curandGenerateUniform(gen, devData, n);
cudaMemcpy(hostData, devData, memSize, cudaMemcpyDeviceToHost);
for(int i=0; i<10; i++) printf("%d %e\n", i, hostData[i]);
curandDestroyGenerator(gen);
cudaFree(devData); free(hostData);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <random>
#include <cuda.h>
#include <stdio.h>
#include <curand.h>
#include <time.h>
int main()
{
curandGenerator_t gen;
// default (WOWXOR) or Mersenne-Trister pseudo random number generator
curandCreateGenerator(&gen, CURAND_RNG_PSEUDO_DEFAULT);
// curandCreateGenerator(&gen, CURAND_RNG_PSEUDO_MT19937);
// initialize the PRNG with seed
// std::random_device rd;
// unsigned int seed = rd();
unsigned int seed = time(0);
printf("seed = %u\n", seed);
curandSetPseudoRandomGeneratorSeed(gen, seed);
float *hostData, *devData;
int n=1<<24;
size_t memSize=sizeof(float)*n;
// host and device memory allocation
hostData = (float *)malloc(memSize);
cudaMalloc(&devData, memSize);
// generate n random numbers in (0,1] on the device array
curandGenerateUniform(gen, devData, n);
cudaMemcpy(hostData, devData, memSize, cudaMemcpyDeviceToHost);
for(int i=0; i<10; i++) printf("%d %e\n", i, hostData[i]);
curandDestroyGenerator(gen);
cudaFree(devData); free(hostData);
} | .file "tmpxft_00196fb5_00000000-6_rngHost.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4144:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4144:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "seed = %u\n"
.LC1:
.string "%d %e\n"
.text
.globl main
.type main, @function
main:
.LFB4141:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $100, %esi
call curandCreateGenerator@PLT
movl $0, %edi
call time@PLT
movq %rax, %rbx
movl %eax, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %esi
movq 8(%rsp), %rdi
call curandSetPseudoRandomGeneratorSeed@PLT
movl $67108864, %edi
call malloc@PLT
movq %rax, %rbp
leaq 16(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl $16777216, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call curandGenerateUniform@PLT
movl $2, %ecx
movl $67108864, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC1(%rip), %r12
.L4:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L4
movq 8(%rsp), %rdi
call curandDestroyGenerator@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L8
movl $0, %eax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4141:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4167:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4167:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <random>
#include <cuda.h>
#include <stdio.h>
#include <curand.h>
#include <time.h>
int main()
{
curandGenerator_t gen;
// default (WOWXOR) or Mersenne-Trister pseudo random number generator
curandCreateGenerator(&gen, CURAND_RNG_PSEUDO_DEFAULT);
// curandCreateGenerator(&gen, CURAND_RNG_PSEUDO_MT19937);
// initialize the PRNG with seed
// std::random_device rd;
// unsigned int seed = rd();
unsigned int seed = time(0);
printf("seed = %u\n", seed);
curandSetPseudoRandomGeneratorSeed(gen, seed);
float *hostData, *devData;
int n=1<<24;
size_t memSize=sizeof(float)*n;
// host and device memory allocation
hostData = (float *)malloc(memSize);
cudaMalloc(&devData, memSize);
// generate n random numbers in (0,1] on the device array
curandGenerateUniform(gen, devData, n);
cudaMemcpy(hostData, devData, memSize, cudaMemcpyDeviceToHost);
for(int i=0; i<10; i++) printf("%d %e\n", i, hostData[i]);
curandDestroyGenerator(gen);
cudaFree(devData); free(hostData);
} | #include <random>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <hiprand/hiprand.h>
#include <time.h>
int main()
{
hiprandGenerator_t gen;
// default (WOWXOR) or Mersenne-Trister pseudo random number generator
hiprandCreateGenerator(&gen, HIPRAND_RNG_PSEUDO_DEFAULT);
// curandCreateGenerator(&gen, CURAND_RNG_PSEUDO_MT19937);
// initialize the PRNG with seed
// std::random_device rd;
// unsigned int seed = rd();
unsigned int seed = time(0);
printf("seed = %u\n", seed);
hiprandSetPseudoRandomGeneratorSeed(gen, seed);
float *hostData, *devData;
int n=1<<24;
size_t memSize=sizeof(float)*n;
// host and device memory allocation
hostData = (float *)malloc(memSize);
hipMalloc(&devData, memSize);
// generate n random numbers in (0,1] on the device array
hiprandGenerateUniform(gen, devData, n);
hipMemcpy(hostData, devData, memSize, hipMemcpyDeviceToHost);
for(int i=0; i<10; i++) printf("%d %e\n", i, hostData[i]);
hiprandDestroyGenerator(gen);
hipFree(devData); free(hostData);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <random>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <hiprand/hiprand.h>
#include <time.h>
int main()
{
hiprandGenerator_t gen;
// default (WOWXOR) or Mersenne-Trister pseudo random number generator
hiprandCreateGenerator(&gen, HIPRAND_RNG_PSEUDO_DEFAULT);
// curandCreateGenerator(&gen, CURAND_RNG_PSEUDO_MT19937);
// initialize the PRNG with seed
// std::random_device rd;
// unsigned int seed = rd();
unsigned int seed = time(0);
printf("seed = %u\n", seed);
hiprandSetPseudoRandomGeneratorSeed(gen, seed);
float *hostData, *devData;
int n=1<<24;
size_t memSize=sizeof(float)*n;
// host and device memory allocation
hostData = (float *)malloc(memSize);
hipMalloc(&devData, memSize);
// generate n random numbers in (0,1] on the device array
hiprandGenerateUniform(gen, devData, n);
hipMemcpy(hostData, devData, memSize, hipMemcpyDeviceToHost);
for(int i=0; i<10; i++) printf("%d %e\n", i, hostData[i]);
hiprandDestroyGenerator(gen);
hipFree(devData); free(hostData);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <random>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <hiprand/hiprand.h>
#include <time.h>
int main()
{
hiprandGenerator_t gen;
// default (WOWXOR) or Mersenne-Trister pseudo random number generator
hiprandCreateGenerator(&gen, HIPRAND_RNG_PSEUDO_DEFAULT);
// curandCreateGenerator(&gen, CURAND_RNG_PSEUDO_MT19937);
// initialize the PRNG with seed
// std::random_device rd;
// unsigned int seed = rd();
unsigned int seed = time(0);
printf("seed = %u\n", seed);
hiprandSetPseudoRandomGeneratorSeed(gen, seed);
float *hostData, *devData;
int n=1<<24;
size_t memSize=sizeof(float)*n;
// host and device memory allocation
hostData = (float *)malloc(memSize);
hipMalloc(&devData, memSize);
// generate n random numbers in (0,1] on the device array
hiprandGenerateUniform(gen, devData, n);
hipMemcpy(hostData, devData, memSize, hipMemcpyDeviceToHost);
for(int i=0; i<10; i++) printf("%d %e\n", i, hostData[i]);
hiprandDestroyGenerator(gen);
hipFree(devData); free(hostData);
} | .text
.file "rngHost.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 16(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hiprandCreateGenerator
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movq %rax, %r14
movl $.L.str, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
movl %r14d, %esi
callq hiprandSetPseudoRandomGeneratorSeed
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r14
leaq 8(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
movl $16777216, %edx # imm = 0x1000000
callq hiprandGenerateUniform
movq 8(%rsp), %rsi
movl $67108864, %edx # imm = 0x4000000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movss (%r14,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %ebx, %esi
movb $1, %al
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB0_1
# %bb.2:
movq 16(%rsp), %rdi
callq hiprandDestroyGenerator
movq 8(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "seed = %u\n"
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d %e\n"
.size .L.str.1, 7
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00196fb5_00000000-6_rngHost.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4144:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4144:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "seed = %u\n"
.LC1:
.string "%d %e\n"
.text
.globl main
.type main, @function
main:
.LFB4141:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $100, %esi
call curandCreateGenerator@PLT
movl $0, %edi
call time@PLT
movq %rax, %rbx
movl %eax, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %esi
movq 8(%rsp), %rdi
call curandSetPseudoRandomGeneratorSeed@PLT
movl $67108864, %edi
call malloc@PLT
movq %rax, %rbp
leaq 16(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl $16777216, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call curandGenerateUniform@PLT
movl $2, %ecx
movl $67108864, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC1(%rip), %r12
.L4:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $10, %rbx
jne .L4
movq 8(%rsp), %rdi
call curandDestroyGenerator@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L8
movl $0, %eax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4141:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4167:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4167:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "rngHost.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $24, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 16(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hiprandCreateGenerator
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movq %rax, %r14
movl $.L.str, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
movl %r14d, %esi
callq hiprandSetPseudoRandomGeneratorSeed
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r14
leaq 8(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
movl $16777216, %edx # imm = 0x1000000
callq hiprandGenerateUniform
movq 8(%rsp), %rsi
movl $67108864, %edx # imm = 0x4000000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movss (%r14,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %ebx, %esi
movb $1, %al
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB0_1
# %bb.2:
movq 16(%rsp), %rdi
callq hiprandDestroyGenerator
movq 8(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "seed = %u\n"
.size .L.str, 11
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d %e\n"
.size .L.str.1, 7
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <fstream>
#include <vector>
#include <stdlib.h>
//#include <common\book.h>
#define DIM 512
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"\nGPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
using namespace std;
#define min(a,b) (a<b)?a:b
__global__ void kernel(float *index,int *min_holder)
{
__shared__ float tmp[DIM];
int idx = threadIdx.x+blockIdx.x*blockDim.x;
int local_index = threadIdx.x;
int row_idx = blockIdx.x;
__shared__ int min_index[DIM];
int size = DIM/2;
tmp[local_index] = index[idx];
min_index[local_index] = local_index;
__syncthreads();
while(size)
{
if(local_index<size)
{
if(tmp[local_index+size]<tmp[local_index])
{
tmp[local_index]= tmp[local_index+size];
min_index[local_index] = min_index[local_index+size];
}
}
size/=2;
__syncthreads();
}
if(local_index==0)
{
min_holder[row_idx] = min_index[0];
}
}
int main()
{
char file_name[255];// = "in.txt";
ofstream fout("out.txt");
cout<<"Please enter the file path to the distance matrix: ";
cin.getline(file_name,255);
std::vector<char> buffer(64 * 1024 * 1024);
fstream fin;
fin.rdbuf()->pubsetbuf(&buffer[0],buffer.size());
fin.open(file_name);
//cudaDeviceProp deviceProp;
//cudaGetDeviceProperties(&deviceProp, 0);
//cout<<deviceProp.name<<" has compute capability "<<deviceProp.major<<","<< deviceProp.minor<<endl;
int size = INT_MIN;
int r=0,c=0;
fin>>size;
int pitch=ceil((double)size/DIM);
float *indexs=new float[size*size];
int *min_holder = new int[size*pitch];
float *indexes_d;
int *min_holder_d;
cudaMalloc(&indexes_d,size*size*sizeof(float));
cudaMalloc(&min_holder_d,(size*pitch)*sizeof(int));
bool *mark = new bool[size+1];
for(int i=0; i<2000; i++)
{
indexs[i]=INT_MAX;
}
for(int i=0; i<size+1; i++)
mark[i]=true;
r=c=0;
char tmp[255];
cout<<"Reading input file";
fin>>tmp;
//cout<<tmp;
while(1)
{
/*fin>>r>>c;
r--;
c--;*/
fin>>indexs[r*size+c];
c++; //:D
//cout<<".";
if(c==size)
{
mark[r]=false;
r++;
c=0;
//cout<<endl;
if(r<size)
{
fin>>tmp;
}
else
break;
}
}
cout<<" ..."<<endl;
//cout<<size<<endl;
//size--;
int index=0;
int handler=size;
float min;
float time;
float time_total=0;
cout<<"Working ";
dim3 blocks(size*pitch);
dim3 threads(512);
while(handler)
{
cout<<".";
min= INT_MAX;
cudaEvent_t start,stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start,0);
//GPU code
cudaMemcpy(indexes_d,indexs,size*size*sizeof(float),cudaMemcpyHostToDevice);
kernel<<<blocks,threads>>>(indexes_d,min_holder_d);
gpuErrchk(cudaMemcpy(min_holder,min_holder_d,(size*pitch)*sizeof(int),cudaMemcpyDeviceToHost));// end of GPU code
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time,start,stop);
time_total+=time;
if(time==0)
{
cout<<"\nSomething went wrong on GPU."<<endl;
exit(0);
}
//cout<<"Time this round: "<<time<<endl;
//for(int i=0; i<size*size ; i ++ )
//cout<<i<<": "<<indexs[i]<<" ";
//cout<<endl;
//getwchar();
bool flag=false;
int trow=-1;
int row=0;
int col=0;
for(int k=0; k<size*pitch; k++)
{
if((k%(pitch))==0)
trow++;
int i = trow*size + min_holder[k];
if(indexs[i]<min)
{
min=indexs[i];
col = pitch*DIM+min_holder[k];
row = trow;
flag=true;
}
}
//cout<<min<<endl;
if(flag)
{
//cout<<row+1<<endl;
fout<<row+1<<endl;
//cout<<col+1<<endl;
fout<<col+1<<endl;
}
//merging two rows and columns
for(int i=0; i<size; i++)
{
indexs[col*size+i]= indexs[row*size+i]=(indexs[row*size+i]+indexs[col*size+i])/2;
indexs[i*size+row]= indexs[i*size+col]=(indexs[i*size+row]+indexs[i*size+col])/2;
indexs[i*size+i]=INT_MAX;
}
indexs[row*size+col] = indexs[col*size+row] = INT_MAX;
handler--;
}
cout<<"\nTime: "<<time_total<<"ms"<<endl;
cout<<"Press Enter to exit.";
getchar();
return 0;
} | code for sm_80
Function : _Z6kernelPfPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R5, R3, c[0x0][0x0], R0 ; /* 0x0000000003057a24 */
/* 0x001fc800078e0200 */
/*0060*/ IMAD.WIDE R4, R5, R2, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fcc00078e0202 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ ISETP.GT.AND P5, PT, R0.reuse, 0xff, PT ; /* 0x000000ff0000780c */
/* 0x040fe20003fa4270 */
/*0090*/ BSSY B0, 0x1b0 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*00a0*/ ISETP.GT.AND P6, PT, R0.reuse, 0x7f, PT ; /* 0x0000007f0000780c */
/* 0x040fe20003fc4270 */
/*00b0*/ STS [R0.X4+0x800], R0 ; /* 0x0008000000007388 */
/* 0x0001e20000004800 */
/*00c0*/ ISETP.GT.AND P0, PT, R0.reuse, 0x3f, PT ; /* 0x0000003f0000780c */
/* 0x040fe40003f04270 */
/*00d0*/ ISETP.GT.AND P1, PT, R0.reuse, 0x1f, PT ; /* 0x0000001f0000780c */
/* 0x040fe40003f24270 */
/*00e0*/ ISETP.GT.AND P2, PT, R0.reuse, 0xf, PT ; /* 0x0000000f0000780c */
/* 0x040fe40003f44270 */
/*00f0*/ ISETP.GT.AND P3, PT, R0, 0x7, PT ; /* 0x000000070000780c */
/* 0x000fc40003f64270 */
/*0100*/ ISETP.GT.AND P4, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f84270 */
/*0110*/ STS [R0.X4], R5 ; /* 0x0000000500007388 */
/* 0x0041e80000004800 */
/*0120*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0130*/ @P5 BRA 0x1a0 ; /* 0x0000006000005947 */
/* 0x000fea0003800000 */
/*0140*/ LDS R4, [R0.X4] ; /* 0x0000000000047984 */
/* 0x001fe80000004800 */
/*0150*/ LDS R5, [R0.X4+0x400] ; /* 0x0004000000057984 */
/* 0x000e240000004800 */
/*0160*/ FSETP.GEU.AND P5, PT, R5, R4, PT ; /* 0x000000040500720b */
/* 0x001fda0003fae000 */
/*0170*/ @!P5 LDS R7, [R0.X4+0xc00] ; /* 0x000c00000007d984 */
/* 0x000e280000004800 */
/*0180*/ @!P5 STS [R0.X4], R5 ; /* 0x000000050000d388 */
/* 0x0003e80000004800 */
/*0190*/ @!P5 STS [R0.X4+0x800], R7 ; /* 0x000800070000d388 */
/* 0x0013e40000004800 */
/*01a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01c0*/ ISETP.GT.AND P5, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fca0003fa4270 */
/*01d0*/ BSSY B0, 0x260 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*01e0*/ @P6 BRA 0x250 ; /* 0x0000006000006947 */
/* 0x000fea0003800000 */
/*01f0*/ LDS R4, [R0.X4] ; /* 0x0000000000047984 */
/* 0x000fe80000004800 */
/*0200*/ LDS R5, [R0.X4+0x200] ; /* 0x0002000000057984 */
/* 0x002e240000004800 */
/*0210*/ FSETP.GEU.AND P6, PT, R5, R4, PT ; /* 0x000000040500720b */
/* 0x001fda0003fce000 */
/*0220*/ @!P6 LDS R7, [R0.X4+0xa00] ; /* 0x000a00000007e984 */
/* 0x000e280000004800 */
/*0230*/ @!P6 STS [R0.X4], R5 ; /* 0x000000050000e388 */
/* 0x0003e80000004800 */
/*0240*/ @!P6 STS [R0.X4+0x800], R7 ; /* 0x000800070000e388 */
/* 0x0013e40000004800 */
/*0250*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0260*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0270*/ ISETP.GT.AND P6, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fca0003fc4270 */
/*0280*/ BSSY B0, 0x310 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0290*/ @P0 BRA 0x300 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*02a0*/ LDS R4, [R0.X4] ; /* 0x0000000000047984 */
/* 0x000fe80000004800 */
/*02b0*/ LDS R5, [R0.X4+0x100] ; /* 0x0001000000057984 */
/* 0x002e240000004800 */
/*02c0*/ FSETP.GEU.AND P0, PT, R5, R4, PT ; /* 0x000000040500720b */
/* 0x001fda0003f0e000 */
/*02d0*/ @!P0 LDS R7, [R0.X4+0x900] ; /* 0x0009000000078984 */
/* 0x000e280000004800 */
/*02e0*/ @!P0 STS [R0.X4], R5 ; /* 0x0000000500008388 */
/* 0x0003e80000004800 */
/*02f0*/ @!P0 STS [R0.X4+0x800], R7 ; /* 0x0008000700008388 */
/* 0x0013e40000004800 */
/*0300*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0310*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0320*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fca0003f05270 */
/*0330*/ BSSY B0, 0x3c0 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0340*/ @P1 BRA 0x3b0 ; /* 0x0000006000001947 */
/* 0x000fea0003800000 */
/*0350*/ LDS R4, [R0.X4] ; /* 0x0000000000047984 */
/* 0x000fe80000004800 */
/*0360*/ LDS R5, [R0.X4+0x80] ; /* 0x0000800000057984 */
/* 0x002e240000004800 */
/*0370*/ FSETP.GEU.AND P1, PT, R5, R4, PT ; /* 0x000000040500720b */
/* 0x001fda0003f2e000 */
/*0380*/ @!P1 LDS R7, [R0.X4+0x880] ; /* 0x0008800000079984 */
/* 0x000e280000004800 */
/*0390*/ @!P1 STS [R0.X4], R5 ; /* 0x0000000500009388 */
/* 0x0003e80000004800 */
/*03a0*/ @!P1 STS [R0.X4+0x800], R7 ; /* 0x0008000700009388 */
/* 0x0013e40000004800 */
/*03b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03d0*/ BSSY B0, 0x460 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*03e0*/ @P2 BRA 0x450 ; /* 0x0000006000002947 */
/* 0x000fea0003800000 */
/*03f0*/ LDS R4, [R0.X4] ; /* 0x0000000000047984 */
/* 0x000fe80000004800 */
/*0400*/ LDS R5, [R0.X4+0x40] ; /* 0x0000400000057984 */
/* 0x002e240000004800 */
/*0410*/ FSETP.GEU.AND P1, PT, R5, R4, PT ; /* 0x000000040500720b */
/* 0x001fda0003f2e000 */
/*0420*/ @!P1 LDS R7, [R0.X4+0x840] ; /* 0x0008400000079984 */
/* 0x000e280000004800 */
/*0430*/ @!P1 STS [R0.X4], R5 ; /* 0x0000000500009388 */
/* 0x0003e80000004800 */
/*0440*/ @!P1 STS [R0.X4+0x800], R7 ; /* 0x0008000700009388 */
/* 0x0013e40000004800 */
/*0450*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0460*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0470*/ BSSY B0, 0x500 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0480*/ @P3 BRA 0x4f0 ; /* 0x0000006000003947 */
/* 0x000fea0003800000 */
/*0490*/ LDS R4, [R0.X4] ; /* 0x0000000000047984 */
/* 0x000fe80000004800 */
/*04a0*/ LDS R5, [R0.X4+0x20] ; /* 0x0000200000057984 */
/* 0x002e240000004800 */
/*04b0*/ FSETP.GEU.AND P1, PT, R5, R4, PT ; /* 0x000000040500720b */
/* 0x001fda0003f2e000 */
/*04c0*/ @!P1 LDS R7, [R0.X4+0x820] ; /* 0x0008200000079984 */
/* 0x000e280000004800 */
/*04d0*/ @!P1 STS [R0.X4], R5 ; /* 0x0000000500009388 */
/* 0x0003e80000004800 */
/*04e0*/ @!P1 STS [R0.X4+0x800], R7 ; /* 0x0008000700009388 */
/* 0x0013e40000004800 */
/*04f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0500*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0510*/ BSSY B0, 0x5a0 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0520*/ @P4 BRA 0x590 ; /* 0x0000006000004947 */
/* 0x000fea0003800000 */
/*0530*/ LDS R4, [R0.X4] ; /* 0x0000000000047984 */
/* 0x000fe80000004800 */
/*0540*/ LDS R5, [R0.X4+0x10] ; /* 0x0000100000057984 */
/* 0x002e240000004800 */
/*0550*/ FSETP.GEU.AND P1, PT, R5, R4, PT ; /* 0x000000040500720b */
/* 0x001fda0003f2e000 */
/*0560*/ @!P1 LDS R7, [R0.X4+0x810] ; /* 0x0008100000079984 */
/* 0x000e280000004800 */
/*0570*/ @!P1 STS [R0.X4], R5 ; /* 0x0000000500009388 */
/* 0x0003e80000004800 */
/*0580*/ @!P1 STS [R0.X4+0x800], R7 ; /* 0x0008000700009388 */
/* 0x0013e40000004800 */
/*0590*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*05b0*/ BSSY B0, 0x640 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*05c0*/ @P5 BRA 0x630 ; /* 0x0000006000005947 */
/* 0x000fea0003800000 */
/*05d0*/ LDS R4, [R0.X4] ; /* 0x0000000000047984 */
/* 0x000fe80000004800 */
/*05e0*/ LDS R5, [R0.X4+0x8] ; /* 0x0000080000057984 */
/* 0x002e240000004800 */
/*05f0*/ FSETP.GEU.AND P1, PT, R5, R4, PT ; /* 0x000000040500720b */
/* 0x001fda0003f2e000 */
/*0600*/ @!P1 LDS R7, [R0.X4+0x808] ; /* 0x0008080000079984 */
/* 0x000e280000004800 */
/*0610*/ @!P1 STS [R0.X4], R5 ; /* 0x0000000500009388 */
/* 0x0003e80000004800 */
/*0620*/ @!P1 STS [R0.X4+0x800], R7 ; /* 0x0008000700009388 */
/* 0x0013e40000004800 */
/*0630*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0640*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0650*/ BSSY B0, 0x6e0 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0660*/ @P6 BRA 0x6d0 ; /* 0x0000006000006947 */
/* 0x000fea0003800000 */
/*0670*/ LDS R4, [R0.X4] ; /* 0x0000000000047984 */
/* 0x000fe80000004800 */
/*0680*/ LDS R5, [R0.X4+0x4] ; /* 0x0000040000057984 */
/* 0x002e240000004800 */
/*0690*/ FSETP.GEU.AND P1, PT, R5, R4, PT ; /* 0x000000040500720b */
/* 0x001fda0003f2e000 */
/*06a0*/ @!P1 LDS R7, [R0.X4+0x804] ; /* 0x0008040000079984 */
/* 0x000e280000004800 */
/*06b0*/ @!P1 STS [R0.X4], R5 ; /* 0x0000000500009388 */
/* 0x0003e80000004800 */
/*06c0*/ @!P1 STS [R0.X4+0x800], R7 ; /* 0x0008000700009388 */
/* 0x0013e40000004800 */
/*06d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*06f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0700*/ LDS R5, [0x800] ; /* 0x00080000ff057984 */
/* 0x002e220000000800 */
/*0710*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0202 */
/*0720*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0730*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0740*/ BRA 0x740; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <fstream>
#include <vector>
#include <stdlib.h>
//#include <common\book.h>
#define DIM 512
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"\nGPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
using namespace std;
#define min(a,b) (a<b)?a:b
__global__ void kernel(float *index,int *min_holder)
{
__shared__ float tmp[DIM];
int idx = threadIdx.x+blockIdx.x*blockDim.x;
int local_index = threadIdx.x;
int row_idx = blockIdx.x;
__shared__ int min_index[DIM];
int size = DIM/2;
tmp[local_index] = index[idx];
min_index[local_index] = local_index;
__syncthreads();
while(size)
{
if(local_index<size)
{
if(tmp[local_index+size]<tmp[local_index])
{
tmp[local_index]= tmp[local_index+size];
min_index[local_index] = min_index[local_index+size];
}
}
size/=2;
__syncthreads();
}
if(local_index==0)
{
min_holder[row_idx] = min_index[0];
}
}
int main()
{
char file_name[255];// = "in.txt";
ofstream fout("out.txt");
cout<<"Please enter the file path to the distance matrix: ";
cin.getline(file_name,255);
std::vector<char> buffer(64 * 1024 * 1024);
fstream fin;
fin.rdbuf()->pubsetbuf(&buffer[0],buffer.size());
fin.open(file_name);
//cudaDeviceProp deviceProp;
//cudaGetDeviceProperties(&deviceProp, 0);
//cout<<deviceProp.name<<" has compute capability "<<deviceProp.major<<","<< deviceProp.minor<<endl;
int size = INT_MIN;
int r=0,c=0;
fin>>size;
int pitch=ceil((double)size/DIM);
float *indexs=new float[size*size];
int *min_holder = new int[size*pitch];
float *indexes_d;
int *min_holder_d;
cudaMalloc(&indexes_d,size*size*sizeof(float));
cudaMalloc(&min_holder_d,(size*pitch)*sizeof(int));
bool *mark = new bool[size+1];
for(int i=0; i<2000; i++)
{
indexs[i]=INT_MAX;
}
for(int i=0; i<size+1; i++)
mark[i]=true;
r=c=0;
char tmp[255];
cout<<"Reading input file";
fin>>tmp;
//cout<<tmp;
while(1)
{
/*fin>>r>>c;
r--;
c--;*/
fin>>indexs[r*size+c];
c++; //:D
//cout<<".";
if(c==size)
{
mark[r]=false;
r++;
c=0;
//cout<<endl;
if(r<size)
{
fin>>tmp;
}
else
break;
}
}
cout<<" ..."<<endl;
//cout<<size<<endl;
//size--;
int index=0;
int handler=size;
float min;
float time;
float time_total=0;
cout<<"Working ";
dim3 blocks(size*pitch);
dim3 threads(512);
while(handler)
{
cout<<".";
min= INT_MAX;
cudaEvent_t start,stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start,0);
//GPU code
cudaMemcpy(indexes_d,indexs,size*size*sizeof(float),cudaMemcpyHostToDevice);
kernel<<<blocks,threads>>>(indexes_d,min_holder_d);
gpuErrchk(cudaMemcpy(min_holder,min_holder_d,(size*pitch)*sizeof(int),cudaMemcpyDeviceToHost));// end of GPU code
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time,start,stop);
time_total+=time;
if(time==0)
{
cout<<"\nSomething went wrong on GPU."<<endl;
exit(0);
}
//cout<<"Time this round: "<<time<<endl;
//for(int i=0; i<size*size ; i ++ )
//cout<<i<<": "<<indexs[i]<<" ";
//cout<<endl;
//getwchar();
bool flag=false;
int trow=-1;
int row=0;
int col=0;
for(int k=0; k<size*pitch; k++)
{
if((k%(pitch))==0)
trow++;
int i = trow*size + min_holder[k];
if(indexs[i]<min)
{
min=indexs[i];
col = pitch*DIM+min_holder[k];
row = trow;
flag=true;
}
}
//cout<<min<<endl;
if(flag)
{
//cout<<row+1<<endl;
fout<<row+1<<endl;
//cout<<col+1<<endl;
fout<<col+1<<endl;
}
//merging two rows and columns
for(int i=0; i<size; i++)
{
indexs[col*size+i]= indexs[row*size+i]=(indexs[row*size+i]+indexs[col*size+i])/2;
indexs[i*size+row]= indexs[i*size+col]=(indexs[i*size+row]+indexs[i*size+col])/2;
indexs[i*size+i]=INT_MAX;
}
indexs[row*size+col] = indexs[col*size+row] = INT_MAX;
handler--;
}
cout<<"\nTime: "<<time_total<<"ms"<<endl;
cout<<"Press Enter to exit.";
getchar();
return 0;
} | .file "tmpxft_00074d4d_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4167:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4167:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6kernelPfPiPfPi
.type _Z27__device_stub__Z6kernelPfPiPfPi, @function
_Z27__device_stub__Z6kernelPfPiPfPi:
.LFB4189:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPfPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4189:
.size _Z27__device_stub__Z6kernelPfPiPfPi, .-_Z27__device_stub__Z6kernelPfPiPfPi
.globl _Z6kernelPfPi
.type _Z6kernelPfPi, @function
_Z6kernelPfPi:
.LFB4190:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6kernelPfPiPfPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4190:
.size _Z6kernelPfPi, .-_Z6kernelPfPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelPfPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4192:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPfPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4192:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIcSaIcEED2Ev,"axG",@progbits,_ZNSt6vectorIcSaIcEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIcSaIcEED2Ev
.type _ZNSt6vectorIcSaIcEED2Ev, @function
_ZNSt6vectorIcSaIcEED2Ev:
.LFB4521:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L16
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L16:
ret
.cfi_endproc
.LFE4521:
.size _ZNSt6vectorIcSaIcEED2Ev, .-_ZNSt6vectorIcSaIcEED2Ev
.weak _ZNSt6vectorIcSaIcEED1Ev
.set _ZNSt6vectorIcSaIcEED1Ev,_ZNSt6vectorIcSaIcEED2Ev
.section .rodata.str1.1
.LC3:
.string "out.txt"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Please enter the file path to the distance matrix: "
.section .rodata.str1.1
.LC9:
.string "Reading input file"
.LC10:
.string " ..."
.LC11:
.string "Working "
.LC12:
.string "."
.section .rodata.str1.8
.align 8
.LC13:
.string "/home/ubuntu/Datasets/stackv2/train-structured/Soroosh129/GPU-UPGMA/master/main.cu"
.section .rodata.str1.1
.LC14:
.string "\nGPUassert: %s %s %d\n"
.LC15:
.string "\nSomething went wrong on GPU."
.LC17:
.string "\nTime: "
.LC18:
.string "ms"
.LC19:
.string "Press Enter to exit."
.text
.globl main
.type main, @function
main:
.LFB4164:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4164
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1704, %rsp
.cfi_def_cfa_offset 1760
movq %fs:40, %rax
movq %rax, 1688(%rsp)
xorl %eax, %eax
leaq 128(%rsp), %rdi
movl $16, %edx
leaq .LC3(%rip), %rsi
.LEHB0:
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE0:
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB1:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq 1168(%rsp), %rsi
movl $255, %edx
leaq _ZSt3cin(%rip), %rdi
call _ZNSi7getlineEPcl@PLT
movq $0, 96(%rsp)
movq $0, 104(%rsp)
movq $0, 112(%rsp)
movl $67108864, %edi
call _Znwm@PLT
.LEHE1:
movq %rax, 96(%rsp)
leaq 67108864(%rax), %rbx
movq %rbx, 112(%rsp)
movb $0, (%rax)
leaq 1(%rax), %rdi
movl $67108863, %edx
movl $0, %esi
call memset@PLT
movq %rbx, 104(%rsp)
leaq 640(%rsp), %rdi
.LEHB2:
call _ZNSt13basic_fstreamIcSt11char_traitsIcEEC1Ev@PLT
.LEHE2:
movq 96(%rsp), %rsi
movq 104(%rsp), %rdx
subq %rsi, %rdx
leaq 664(%rsp), %rdi
movq 664(%rsp), %rax
.LEHB3:
call *24(%rax)
leaq 1168(%rsp), %rsi
leaq 640(%rsp), %rdi
movl $24, %edx
call _ZNSt13basic_fstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode@PLT
movl $-2147483648, 32(%rsp)
leaq 32(%rsp), %rsi
leaq 640(%rsp), %rdi
call _ZNSirsERi@PLT
movl 32(%rsp), %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd .LC5(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC20(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC6(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L20
cvttsd2siq %xmm0, %rdx
pxor %xmm1, %xmm1
cvtsi2sdq %rdx, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC8(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L20:
cvttsd2sil %xmm3, %r14d
imull %eax, %eax
movslq %eax, %rdi
salq $2, %rdi
call _Znam@PLT
movq %rax, %r12
movl %r14d, %eax
imull 32(%rsp), %eax
cltq
movabsq $2305843009213693950, %rdx
cmpq %rax, %rdx
jb .L21
leaq 0(,%rax,4), %rdi
call _Znam@PLT
movq %rax, 8(%rsp)
movl 32(%rsp), %eax
imull %eax, %eax
movslq %eax, %rsi
salq $2, %rsi
leaq 40(%rsp), %rdi
call cudaMalloc@PLT
jmp .L75
.L21:
movq 1688(%rsp), %rax
subq %fs:40, %rax
je .L23
call __stack_chk_fail@PLT
.L23:
call __cxa_throw_bad_array_new_length@PLT
.L75:
movl %r14d, %esi
imull 32(%rsp), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 48(%rsp), %rdi
call cudaMalloc@PLT
movl 32(%rsp), %eax
leal 1(%rax), %edi
movslq %edi, %rdi
call _Znam@PLT
movq %rax, %r15
leaq 8000(%r12), %rdx
movq %r12, %rax
movss .LC2(%rip), %xmm0
.L24:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L24
movl 32(%rsp), %edx
testl %edx, %edx
js .L25
movq %r15, %rax
leal 1(%rdx), %edx
addq %r15, %rdx
.L26:
movb $1, (%rax)
addq $1, %rax
cmpq %rdx, %rax
jne .L26
.L25:
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 640(%rsp), %rax
movq -24(%rax), %rax
movq 656(%rsp,%rax), %rbx
leaq 1424(%rsp), %rsi
leaq 640(%rsp), %rdi
movl $255, %edx
call _ZSt17__istream_extractRSiPcl@PLT
movq 640(%rsp), %rax
movq -24(%rax), %rax
leaq 640(%rsp,%rax), %rax
cmpl $0, 32(%rax)
je .L27
.L29:
movl $0, %ebp
leaq 640(%rsp), %r13
jmp .L28
.L27:
subq $1, %rbx
cmpq $254, %rbx
jbe .L29
movq 232(%rax), %rdi
movq 24(%rdi), %rax
cmpq %rax, 16(%rdi)
jb .L29
movq (%rdi), %rax
call *72(%rax)
cmpl $-1, %eax
jne .L29
movq 640(%rsp), %rax
movq -24(%rax), %rax
leaq 640(%rsp,%rax), %rdi
movl 32(%rdi), %esi
orl $2, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L29
.L77:
addl $1, %ebx
movl 32(%rsp), %eax
cmpl %ebx, %eax
je .L76
.L30:
movl %ebp, %eax
imull 32(%rsp), %eax
addl %ebx, %eax
cltq
leaq (%r12,%rax,4), %rsi
movq %r13, %rdi
call _ZNSi10_M_extractIfEERSiRT_@PLT
jmp .L77
.L76:
movb $0, (%r15)
addl $1, %ebp
cmpl %ebp, %eax
jle .L31
movq 640(%rsp), %rax
movq -24(%rax), %rax
movq 656(%rsp,%rax), %rbx
leaq 1424(%rsp), %rsi
movl $255, %edx
movq %r13, %rdi
call _ZSt17__istream_extractRSiPcl@PLT
movq 640(%rsp), %rax
movq %r13, %rcx
addq -24(%rax), %rcx
cmpl $0, 32(%rcx)
jne .L32
subq $1, %rbx
cmpq $254, %rbx
ja .L78
.L32:
addq $1, %r15
.L28:
movl $0, %ebx
jmp .L30
.L78:
movq 232(%rcx), %rdi
movq 24(%rdi), %rax
cmpq %rax, 16(%rdi)
jb .L32
movq (%rdi), %rax
call *72(%rax)
cmpl $-1, %eax
jne .L32
movq 640(%rsp), %rax
movq %r13, %rdi
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $2, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L32
.L31:
leaq .LC10(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl 32(%rsp), %ebx
movl %ebx, 20(%rsp)
leaq .LC11(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %r14d, %eax
imull 32(%rsp), %eax
movl %eax, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $512, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
testl %ebx, %ebx
je .L60
movl %r14d, %r13d
sall $9, %r13d
movl $0x00000000, 16(%rsp)
jmp .L54
.L83:
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movl 32(%rsp), %eax
imull %eax, %eax
movslq %eax, %rdx
salq $2, %rdx
movl $1, %ecx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl 92(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movq 72(%rsp), %rdi
movl 80(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L34
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z27__device_stub__Z6kernelPfPiPfPi
.L34:
movl %r14d, %edx
imull 32(%rsp), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $2, %ecx
movq 48(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L79
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
jmp .L80
.L79:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $150, %r9d
leaq .LC13(%rip), %r8
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L80:
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 36(%rsp), %rdi
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 36(%rsp), %xmm0
movss 16(%rsp), %xmm5
addss %xmm0, %xmm5
movss %xmm5, 16(%rsp)
pxor %xmm1, %xmm1
ucomiss %xmm1, %xmm0
jp .L64
je .L36
.L64:
movl 32(%rsp), %r9d
movl %r14d, %edi
imull %r9d, %edi
movl $0, %ebx
movl $0, %r15d
testl %edi, %edi
jle .L39
movslq %edi, %rdi
movl $0, %ecx
movl $0, %ebx
movl $0, %r15d
movl $-1, %esi
movl $0, %r8d
movss .LC2(%rip), %xmm1
movq 8(%rsp), %r10
jmp .L43
.L36:
leaq .LC15(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %edi
call exit@PLT
.L41:
addq $1, %rcx
cmpq %rcx, %rdi
je .L81
.L43:
movl %ecx, %eax
cltd
idivl %r14d
cmpl $1, %edx
adcl $0, %esi
movl (%r10,%rcx,4), %edx
movl %esi, %eax
imull %r9d, %eax
addl %edx, %eax
cltq
movss (%r12,%rax,4), %xmm0
comiss %xmm0, %xmm1
jbe .L41
leal (%rdx,%r13), %ebx
movl %esi, %r15d
movaps %xmm0, %xmm1
movl $1, %r8d
jmp .L41
.L81:
testb %r8b, %r8b
jne .L82
.L39:
movl 32(%rsp), %r11d
testl %r11d, %r11d
jle .L52
movl %ebx, %esi
imull %r11d, %esi
movl %r15d, %edi
imull %r11d, %edi
movslq %edi, %rdi
leaq (%r12,%rdi,4), %rax
movslq %r11d, %rcx
leaq 0(,%rcx,4), %r8
movslq %r15d, %rbp
leaq (%r12,%rbp,4), %rdx
leaq 4(%r8), %r10
addq %rdi, %rcx
leaq (%r12,%rcx,4), %r9
movq %r12, %rcx
movslq %esi, %rsi
subq %rdi, %rsi
movslq %ebx, %rdi
subq %rbp, %rdi
movss .LC2(%rip), %xmm1
.L53:
movss (%rax), %xmm0
addss (%rax,%rsi,4), %xmm0
mulss .LC16(%rip), %xmm0
movss %xmm0, (%rax)
movss %xmm0, (%rax,%rsi,4)
movss (%rdx), %xmm0
addss (%rdx,%rdi,4), %xmm0
mulss .LC16(%rip), %xmm0
movss %xmm0, (%rdx,%rdi,4)
movss %xmm0, (%rdx)
movss %xmm1, (%rcx)
addq $4, %rax
addq %r8, %rdx
addq %r10, %rcx
cmpq %r9, %rax
jne .L53
.L52:
movl %ebx, %eax
imull %r11d, %eax
addl %r15d, %eax
cltq
movss .LC2(%rip), %xmm0
movss %xmm0, (%r12,%rax,4)
imull %r11d, %r15d
leal (%r15,%rbx), %eax
cltq
movss %xmm0, (%r12,%rax,4)
subl $1, 20(%rsp)
je .L33
.L54:
movl $1, %edx
leaq .LC12(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L83
.L82:
leal 1(%r15), %esi
leaq 128(%rsp), %rdi
call _ZNSolsEi@PLT
movq %rax, %rcx
movq %rax, 24(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rcx,%rax), %rbp
testq %rbp, %rbp
je .L84
cmpb $0, 56(%rbp)
je .L46
movzbl 67(%rbp), %esi
.L47:
movsbl %sil, %esi
movq 24(%rsp), %rdi
call _ZNSo3putEc@PLT
jmp .L85
.L84:
movq 1688(%rsp), %rax
subq %fs:40, %rax
jne .L86
call _ZSt16__throw_bad_castv@PLT
.L63:
endbr64
movq %rax, %rbx
leaq 640(%rsp), %rdi
call _ZNSt13basic_fstreamIcSt11char_traitsIcEED1Ev@PLT
.L56:
leaq 96(%rsp), %rdi
call _ZNSt6vectorIcSaIcEED1Ev
.L57:
leaq 128(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 1688(%rsp), %rax
subq %fs:40, %rax
je .L58
call __stack_chk_fail@PLT
.L86:
call __stack_chk_fail@PLT
.L46:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L47
.L85:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leal 1(%rbx), %esi
leaq 128(%rsp), %rdi
call _ZNSolsEi@PLT
movq %rax, %rcx
movq %rax, 24(%rsp)
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rcx,%rax), %rbp
testq %rbp, %rbp
je .L87
cmpb $0, 56(%rbp)
je .L50
movzbl 67(%rbp), %esi
.L51:
movsbl %sil, %esi
movq 24(%rsp), %rdi
call _ZNSo3putEc@PLT
jmp .L88
.L87:
movq 1688(%rsp), %rax
subq %fs:40, %rax
jne .L89
call _ZSt16__throw_bad_castv@PLT
.L89:
call __stack_chk_fail@PLT
.L50:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L51
.L88:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L39
.L60:
movl $0x00000000, 16(%rsp)
.L33:
leaq .LC17(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 16(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC18(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC19(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq stdin(%rip), %rdi
call getc@PLT
.LEHE3:
leaq 640(%rsp), %rdi
call _ZNSt13basic_fstreamIcSt11char_traitsIcEED1Ev@PLT
leaq 96(%rsp), %rdi
call _ZNSt6vectorIcSaIcEED1Ev
leaq 128(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 1688(%rsp), %rax
subq %fs:40, %rax
jne .L90
movl $0, %eax
addq $1704, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L62:
.cfi_restore_state
endbr64
movq %rax, %rbx
jmp .L56
.L61:
endbr64
movq %rax, %rbx
jmp .L57
.L58:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L90:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4164:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4164:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4164-.LLSDACSB4164
.LLSDACSB4164:
.uleb128 .LEHB0-.LFB4164
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4164
.uleb128 .LEHE1-.LEHB1
.uleb128 .L61-.LFB4164
.uleb128 0
.uleb128 .LEHB2-.LFB4164
.uleb128 .LEHE2-.LEHB2
.uleb128 .L62-.LFB4164
.uleb128 0
.uleb128 .LEHB3-.LFB4164
.uleb128 .LEHE3-.LEHB3
.uleb128 .L63-.LFB4164
.uleb128 0
.uleb128 .LEHB4-.LFB4164
.uleb128 .LEHE4-.LEHB4
.uleb128 0
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.LLSDACSE4164:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1325400064
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1063256064
.align 8
.LC6:
.long 0
.long 1127219200
.align 8
.LC8:
.long 0
.long 1072693248
.section .rodata.cst4
.align 4
.LC16:
.long 1056964608
.section .rodata.cst8
.align 8
.LC20:
.long -1
.long 2147483647
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <fstream>
#include <vector>
#include <stdlib.h>
//#include <common\book.h>
#define DIM 512
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"\nGPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
using namespace std;
#define min(a,b) (a<b)?a:b
__global__ void kernel(float *index,int *min_holder)
{
__shared__ float tmp[DIM];
int idx = threadIdx.x+blockIdx.x*blockDim.x;
int local_index = threadIdx.x;
int row_idx = blockIdx.x;
__shared__ int min_index[DIM];
int size = DIM/2;
tmp[local_index] = index[idx];
min_index[local_index] = local_index;
__syncthreads();
while(size)
{
if(local_index<size)
{
if(tmp[local_index+size]<tmp[local_index])
{
tmp[local_index]= tmp[local_index+size];
min_index[local_index] = min_index[local_index+size];
}
}
size/=2;
__syncthreads();
}
if(local_index==0)
{
min_holder[row_idx] = min_index[0];
}
}
int main()
{
char file_name[255];// = "in.txt";
ofstream fout("out.txt");
cout<<"Please enter the file path to the distance matrix: ";
cin.getline(file_name,255);
std::vector<char> buffer(64 * 1024 * 1024);
fstream fin;
fin.rdbuf()->pubsetbuf(&buffer[0],buffer.size());
fin.open(file_name);
//cudaDeviceProp deviceProp;
//cudaGetDeviceProperties(&deviceProp, 0);
//cout<<deviceProp.name<<" has compute capability "<<deviceProp.major<<","<< deviceProp.minor<<endl;
int size = INT_MIN;
int r=0,c=0;
fin>>size;
int pitch=ceil((double)size/DIM);
float *indexs=new float[size*size];
int *min_holder = new int[size*pitch];
float *indexes_d;
int *min_holder_d;
cudaMalloc(&indexes_d,size*size*sizeof(float));
cudaMalloc(&min_holder_d,(size*pitch)*sizeof(int));
bool *mark = new bool[size+1];
for(int i=0; i<2000; i++)
{
indexs[i]=INT_MAX;
}
for(int i=0; i<size+1; i++)
mark[i]=true;
r=c=0;
char tmp[255];
cout<<"Reading input file";
fin>>tmp;
//cout<<tmp;
while(1)
{
/*fin>>r>>c;
r--;
c--;*/
fin>>indexs[r*size+c];
c++; //:D
//cout<<".";
if(c==size)
{
mark[r]=false;
r++;
c=0;
//cout<<endl;
if(r<size)
{
fin>>tmp;
}
else
break;
}
}
cout<<" ..."<<endl;
//cout<<size<<endl;
//size--;
int index=0;
int handler=size;
float min;
float time;
float time_total=0;
cout<<"Working ";
dim3 blocks(size*pitch);
dim3 threads(512);
while(handler)
{
cout<<".";
min= INT_MAX;
cudaEvent_t start,stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start,0);
//GPU code
cudaMemcpy(indexes_d,indexs,size*size*sizeof(float),cudaMemcpyHostToDevice);
kernel<<<blocks,threads>>>(indexes_d,min_holder_d);
gpuErrchk(cudaMemcpy(min_holder,min_holder_d,(size*pitch)*sizeof(int),cudaMemcpyDeviceToHost));// end of GPU code
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time,start,stop);
time_total+=time;
if(time==0)
{
cout<<"\nSomething went wrong on GPU."<<endl;
exit(0);
}
//cout<<"Time this round: "<<time<<endl;
//for(int i=0; i<size*size ; i ++ )
//cout<<i<<": "<<indexs[i]<<" ";
//cout<<endl;
//getwchar();
bool flag=false;
int trow=-1;
int row=0;
int col=0;
for(int k=0; k<size*pitch; k++)
{
if((k%(pitch))==0)
trow++;
int i = trow*size + min_holder[k];
if(indexs[i]<min)
{
min=indexs[i];
col = pitch*DIM+min_holder[k];
row = trow;
flag=true;
}
}
//cout<<min<<endl;
if(flag)
{
//cout<<row+1<<endl;
fout<<row+1<<endl;
//cout<<col+1<<endl;
fout<<col+1<<endl;
}
//merging two rows and columns
for(int i=0; i<size; i++)
{
indexs[col*size+i]= indexs[row*size+i]=(indexs[row*size+i]+indexs[col*size+i])/2;
indexs[i*size+row]= indexs[i*size+col]=(indexs[i*size+row]+indexs[i*size+col])/2;
indexs[i*size+i]=INT_MAX;
}
indexs[row*size+col] = indexs[col*size+row] = INT_MAX;
handler--;
}
cout<<"\nTime: "<<time_total<<"ms"<<endl;
cout<<"Press Enter to exit.";
getchar();
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
#include <vector>
#include <stdlib.h>
//#include <common\book.h>
#define DIM 512
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"\nGPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
using namespace std;
#define min(a,b) (a<b)?a:b
__global__ void kernel(float *index,int *min_holder)
{
__shared__ float tmp[DIM];
int idx = threadIdx.x+blockIdx.x*blockDim.x;
int local_index = threadIdx.x;
int row_idx = blockIdx.x;
__shared__ int min_index[DIM];
int size = DIM/2;
tmp[local_index] = index[idx];
min_index[local_index] = local_index;
__syncthreads();
while(size)
{
if(local_index<size)
{
if(tmp[local_index+size]<tmp[local_index])
{
tmp[local_index]= tmp[local_index+size];
min_index[local_index] = min_index[local_index+size];
}
}
size/=2;
__syncthreads();
}
if(local_index==0)
{
min_holder[row_idx] = min_index[0];
}
}
int main()
{
char file_name[255];// = "in.txt";
ofstream fout("out.txt");
cout<<"Please enter the file path to the distance matrix: ";
cin.getline(file_name,255);
std::vector<char> buffer(64 * 1024 * 1024);
fstream fin;
fin.rdbuf()->pubsetbuf(&buffer[0],buffer.size());
fin.open(file_name);
//cudaDeviceProp deviceProp;
//cudaGetDeviceProperties(&deviceProp, 0);
//cout<<deviceProp.name<<" has compute capability "<<deviceProp.major<<","<< deviceProp.minor<<endl;
int size = INT_MIN;
int r=0,c=0;
fin>>size;
int pitch=ceil((double)size/DIM);
float *indexs=new float[size*size];
int *min_holder = new int[size*pitch];
float *indexes_d;
int *min_holder_d;
hipMalloc(&indexes_d,size*size*sizeof(float));
hipMalloc(&min_holder_d,(size*pitch)*sizeof(int));
bool *mark = new bool[size+1];
for(int i=0; i<2000; i++)
{
indexs[i]=INT_MAX;
}
for(int i=0; i<size+1; i++)
mark[i]=true;
r=c=0;
char tmp[255];
cout<<"Reading input file";
fin>>tmp;
//cout<<tmp;
while(1)
{
/*fin>>r>>c;
r--;
c--;*/
fin>>indexs[r*size+c];
c++; //:D
//cout<<".";
if(c==size)
{
mark[r]=false;
r++;
c=0;
//cout<<endl;
if(r<size)
{
fin>>tmp;
}
else
break;
}
}
cout<<" ..."<<endl;
//cout<<size<<endl;
//size--;
int index=0;
int handler=size;
float min;
float time;
float time_total=0;
cout<<"Working ";
dim3 blocks(size*pitch);
dim3 threads(512);
while(handler)
{
cout<<".";
min= INT_MAX;
hipEvent_t start,stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
//GPU code
hipMemcpy(indexes_d,indexs,size*size*sizeof(float),hipMemcpyHostToDevice);
kernel<<<blocks,threads>>>(indexes_d,min_holder_d);
gpuErrchk(hipMemcpy(min_holder,min_holder_d,(size*pitch)*sizeof(int),hipMemcpyDeviceToHost));// end of GPU code
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time,start,stop);
time_total+=time;
if(time==0)
{
cout<<"\nSomething went wrong on GPU."<<endl;
exit(0);
}
//cout<<"Time this round: "<<time<<endl;
//for(int i=0; i<size*size ; i ++ )
//cout<<i<<": "<<indexs[i]<<" ";
//cout<<endl;
//getwchar();
bool flag=false;
int trow=-1;
int row=0;
int col=0;
for(int k=0; k<size*pitch; k++)
{
if((k%(pitch))==0)
trow++;
int i = trow*size + min_holder[k];
if(indexs[i]<min)
{
min=indexs[i];
col = pitch*DIM+min_holder[k];
row = trow;
flag=true;
}
}
//cout<<min<<endl;
if(flag)
{
//cout<<row+1<<endl;
fout<<row+1<<endl;
//cout<<col+1<<endl;
fout<<col+1<<endl;
}
//merging two rows and columns
for(int i=0; i<size; i++)
{
indexs[col*size+i]= indexs[row*size+i]=(indexs[row*size+i]+indexs[col*size+i])/2;
indexs[i*size+row]= indexs[i*size+col]=(indexs[i*size+row]+indexs[i*size+col])/2;
indexs[i*size+i]=INT_MAX;
}
indexs[row*size+col] = indexs[col*size+row] = INT_MAX;
handler--;
}
cout<<"\nTime: "<<time_total<<"ms"<<endl;
cout<<"Press Enter to exit.";
getchar();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
#include <vector>
#include <stdlib.h>
//#include <common\book.h>
#define DIM 512
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"\nGPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
using namespace std;
#define min(a,b) (a<b)?a:b
__global__ void kernel(float *index,int *min_holder)
{
__shared__ float tmp[DIM];
int idx = threadIdx.x+blockIdx.x*blockDim.x;
int local_index = threadIdx.x;
int row_idx = blockIdx.x;
__shared__ int min_index[DIM];
int size = DIM/2;
tmp[local_index] = index[idx];
min_index[local_index] = local_index;
__syncthreads();
while(size)
{
if(local_index<size)
{
if(tmp[local_index+size]<tmp[local_index])
{
tmp[local_index]= tmp[local_index+size];
min_index[local_index] = min_index[local_index+size];
}
}
size/=2;
__syncthreads();
}
if(local_index==0)
{
min_holder[row_idx] = min_index[0];
}
}
int main()
{
char file_name[255];// = "in.txt";
ofstream fout("out.txt");
cout<<"Please enter the file path to the distance matrix: ";
cin.getline(file_name,255);
std::vector<char> buffer(64 * 1024 * 1024);
fstream fin;
fin.rdbuf()->pubsetbuf(&buffer[0],buffer.size());
fin.open(file_name);
//cudaDeviceProp deviceProp;
//cudaGetDeviceProperties(&deviceProp, 0);
//cout<<deviceProp.name<<" has compute capability "<<deviceProp.major<<","<< deviceProp.minor<<endl;
int size = INT_MIN;
int r=0,c=0;
fin>>size;
int pitch=ceil((double)size/DIM);
float *indexs=new float[size*size];
int *min_holder = new int[size*pitch];
float *indexes_d;
int *min_holder_d;
hipMalloc(&indexes_d,size*size*sizeof(float));
hipMalloc(&min_holder_d,(size*pitch)*sizeof(int));
bool *mark = new bool[size+1];
for(int i=0; i<2000; i++)
{
indexs[i]=INT_MAX;
}
for(int i=0; i<size+1; i++)
mark[i]=true;
r=c=0;
char tmp[255];
cout<<"Reading input file";
fin>>tmp;
//cout<<tmp;
while(1)
{
/*fin>>r>>c;
r--;
c--;*/
fin>>indexs[r*size+c];
c++; //:D
//cout<<".";
if(c==size)
{
mark[r]=false;
r++;
c=0;
//cout<<endl;
if(r<size)
{
fin>>tmp;
}
else
break;
}
}
cout<<" ..."<<endl;
//cout<<size<<endl;
//size--;
int index=0;
int handler=size;
float min;
float time;
float time_total=0;
cout<<"Working ";
dim3 blocks(size*pitch);
dim3 threads(512);
while(handler)
{
cout<<".";
min= INT_MAX;
hipEvent_t start,stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
//GPU code
hipMemcpy(indexes_d,indexs,size*size*sizeof(float),hipMemcpyHostToDevice);
kernel<<<blocks,threads>>>(indexes_d,min_holder_d);
gpuErrchk(hipMemcpy(min_holder,min_holder_d,(size*pitch)*sizeof(int),hipMemcpyDeviceToHost));// end of GPU code
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time,start,stop);
time_total+=time;
if(time==0)
{
cout<<"\nSomething went wrong on GPU."<<endl;
exit(0);
}
//cout<<"Time this round: "<<time<<endl;
//for(int i=0; i<size*size ; i ++ )
//cout<<i<<": "<<indexs[i]<<" ";
//cout<<endl;
//getwchar();
bool flag=false;
int trow=-1;
int row=0;
int col=0;
for(int k=0; k<size*pitch; k++)
{
if((k%(pitch))==0)
trow++;
int i = trow*size + min_holder[k];
if(indexs[i]<min)
{
min=indexs[i];
col = pitch*DIM+min_holder[k];
row = trow;
flag=true;
}
}
//cout<<min<<endl;
if(flag)
{
//cout<<row+1<<endl;
fout<<row+1<<endl;
//cout<<col+1<<endl;
fout<<col+1<<endl;
}
//merging two rows and columns
for(int i=0; i<size; i++)
{
indexs[col*size+i]= indexs[row*size+i]=(indexs[row*size+i]+indexs[col*size+i])/2;
indexs[i*size+row]= indexs[i*size+col]=(indexs[i*size+row]+indexs[i*size+col])/2;
indexs[i*size+i]=INT_MAX;
}
indexs[row*size+col] = indexs[col*size+row] = INT_MAX;
handler--;
}
cout<<"\nTime: "<<time_total<<"ms"<<endl;
cout<<"Press Enter to exit.";
getchar();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPfPi
.globl _Z6kernelPfPi
.p2align 8
.type _Z6kernelPfPi,@function
_Z6kernelPfPi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_movk_i32 s3, 0x100
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v3, v[1:2], off
v_lshlrev_b32_e32 v1, 2, v0
v_add_nc_u32_e32 v2, 0x800, v1
s_waitcnt vmcnt(0)
ds_store_2addr_stride64_b32 v1, v3, v0 offset1:8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 31
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s3, s4
s_add_i32 s3, s3, 1
s_ashr_i32 s4, s4, 1
s_cmp_gt_u32 s3, 2
s_mov_b32 s3, s4
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_5
.LBB0_2:
s_mov_b32 s4, exec_lo
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_1
v_add_nc_u32_e32 v3, s3, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v4, 2, v3
ds_load_b32 v3, v4
ds_load_b32 v5, v1
s_waitcnt lgkmcnt(0)
v_cmp_lt_f32_e32 vcc_lo, v3, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_1
ds_load_b32 v4, v4 offset:2048
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(1)
ds_store_b32 v2, v4
s_branch .LBB0_1
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0 offset:2048
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPfPi
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPfPi, .Lfunc_end0-_Z6kernelPfPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPfPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPfPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
#include <vector>
#include <stdlib.h>
//#include <common\book.h>
#define DIM 512
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"\nGPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
using namespace std;
#define min(a,b) (a<b)?a:b
__global__ void kernel(float *index,int *min_holder)
{
__shared__ float tmp[DIM];
int idx = threadIdx.x+blockIdx.x*blockDim.x;
int local_index = threadIdx.x;
int row_idx = blockIdx.x;
__shared__ int min_index[DIM];
int size = DIM/2;
tmp[local_index] = index[idx];
min_index[local_index] = local_index;
__syncthreads();
while(size)
{
if(local_index<size)
{
if(tmp[local_index+size]<tmp[local_index])
{
tmp[local_index]= tmp[local_index+size];
min_index[local_index] = min_index[local_index+size];
}
}
size/=2;
__syncthreads();
}
if(local_index==0)
{
min_holder[row_idx] = min_index[0];
}
}
int main()
{
char file_name[255];// = "in.txt";
ofstream fout("out.txt");
cout<<"Please enter the file path to the distance matrix: ";
cin.getline(file_name,255);
std::vector<char> buffer(64 * 1024 * 1024);
fstream fin;
fin.rdbuf()->pubsetbuf(&buffer[0],buffer.size());
fin.open(file_name);
//cudaDeviceProp deviceProp;
//cudaGetDeviceProperties(&deviceProp, 0);
//cout<<deviceProp.name<<" has compute capability "<<deviceProp.major<<","<< deviceProp.minor<<endl;
int size = INT_MIN;
int r=0,c=0;
fin>>size;
int pitch=ceil((double)size/DIM);
float *indexs=new float[size*size];
int *min_holder = new int[size*pitch];
float *indexes_d;
int *min_holder_d;
hipMalloc(&indexes_d,size*size*sizeof(float));
hipMalloc(&min_holder_d,(size*pitch)*sizeof(int));
bool *mark = new bool[size+1];
for(int i=0; i<2000; i++)
{
indexs[i]=INT_MAX;
}
for(int i=0; i<size+1; i++)
mark[i]=true;
r=c=0;
char tmp[255];
cout<<"Reading input file";
fin>>tmp;
//cout<<tmp;
while(1)
{
/*fin>>r>>c;
r--;
c--;*/
fin>>indexs[r*size+c];
c++; //:D
//cout<<".";
if(c==size)
{
mark[r]=false;
r++;
c=0;
//cout<<endl;
if(r<size)
{
fin>>tmp;
}
else
break;
}
}
cout<<" ..."<<endl;
//cout<<size<<endl;
//size--;
int index=0;
int handler=size;
float min;
float time;
float time_total=0;
cout<<"Working ";
dim3 blocks(size*pitch);
dim3 threads(512);
while(handler)
{
cout<<".";
min= INT_MAX;
hipEvent_t start,stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start,0);
//GPU code
hipMemcpy(indexes_d,indexs,size*size*sizeof(float),hipMemcpyHostToDevice);
kernel<<<blocks,threads>>>(indexes_d,min_holder_d);
gpuErrchk(hipMemcpy(min_holder,min_holder_d,(size*pitch)*sizeof(int),hipMemcpyDeviceToHost));// end of GPU code
hipEventRecord(stop,0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time,start,stop);
time_total+=time;
if(time==0)
{
cout<<"\nSomething went wrong on GPU."<<endl;
exit(0);
}
//cout<<"Time this round: "<<time<<endl;
//for(int i=0; i<size*size ; i ++ )
//cout<<i<<": "<<indexs[i]<<" ";
//cout<<endl;
//getwchar();
bool flag=false;
int trow=-1;
int row=0;
int col=0;
for(int k=0; k<size*pitch; k++)
{
if((k%(pitch))==0)
trow++;
int i = trow*size + min_holder[k];
if(indexs[i]<min)
{
min=indexs[i];
col = pitch*DIM+min_holder[k];
row = trow;
flag=true;
}
}
//cout<<min<<endl;
if(flag)
{
//cout<<row+1<<endl;
fout<<row+1<<endl;
//cout<<col+1<<endl;
fout<<col+1<<endl;
}
//merging two rows and columns
for(int i=0; i<size; i++)
{
indexs[col*size+i]= indexs[row*size+i]=(indexs[row*size+i]+indexs[col*size+i])/2;
indexs[i*size+row]= indexs[i*size+col]=(indexs[i*size+row]+indexs[i*size+col])/2;
indexs[i*size+i]=INT_MAX;
}
indexs[row*size+col] = indexs[col*size+row] = INT_MAX;
handler--;
}
cout<<"\nTime: "<<time_total<<"ms"<<endl;
cout<<"Press Enter to exit.";
getchar();
return 0;
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__kernelPfPi # -- Begin function _Z21__device_stub__kernelPfPi
.p2align 4, 0x90
.type _Z21__device_stub__kernelPfPi,@function
_Z21__device_stub__kernelPfPi: # @_Z21__device_stub__kernelPfPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelPfPi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPfPi, .Lfunc_end0-_Z21__device_stub__kernelPfPi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3f60000000000000 # double 0.001953125
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI1_1:
.long 0x4f000000 # float 2.14748365E+9
.LCPI1_2:
.long 0x3f000000 # float 0.5
.LCPI1_3:
.long 0x00000000 # float 0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1736, %rsp # imm = 0x6C8
.cfi_def_cfa_offset 1792
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
.cfi_escape 0x2e, 0x00
leaq 704(%rsp), %rdi
movl $.L.str, %esi
movl $16, %edx
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $51, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp1:
# %bb.1: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq _ZSt3cin(%rip), %rax
movq -24(%rax), %rax
movq _ZSt3cin+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_2
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_6
# %bb.5:
movzbl 67(%rbx), %eax
jmp .LBB1_8
.LBB1_6:
.Ltmp2:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp3:
# %bb.7: # %.noexc147
movq (%rbx), %rax
.Ltmp4:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp5:
.LBB1_8: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp6:
.cfi_escape 0x2e, 0x00
movsbl %al, %ecx
leaq 1472(%rsp), %rsi
movl $_ZSt3cin, %edi
movl $255, %edx
callq _ZNSi7getlineEPclc
.Ltmp7:
# %bb.9: # %_ZNSi7getlineEPcl.exit
.Ltmp8:
.cfi_escape 0x2e, 0x00
movl $67108864, %edi # imm = 0x4000000
callq _Znwm
.Ltmp9:
# %bb.10: # %_ZNSt6vectorIcSaIcEEC2EmRKS0_.exit
.cfi_escape 0x2e, 0x00
movl $67108864, %edx # imm = 0x4000000
movq %rax, %r15
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.Ltmp11:
.cfi_escape 0x2e, 0x00
leaq 176(%rsp), %rbx
movq %rbx, %rdi
movq %r15, 48(%rsp) # 8-byte Spill
callq _ZNSt13basic_fstreamIcSt11char_traitsIcEEC1Ev
.Ltmp12:
# %bb.11:
leaq 200(%rsp), %r14
movq 200(%rsp), %rax
.Ltmp14:
.cfi_escape 0x2e, 0x00
movl $67108864, %edx # imm = 0x4000000
movq %r14, %rdi
movq %r15, %rsi
callq *24(%rax)
.Ltmp15:
# %bb.12: # %_ZNSt15basic_streambufIcSt11char_traitsIcEE9pubsetbufEPcl.exit
.Ltmp16:
.cfi_escape 0x2e, 0x00
leaq 1472(%rsp), %rsi
movq %r14, %rdi
movl $24, %edx
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode
.Ltmp17:
# %bb.13: # %.noexc152
movq 176(%rsp), %rcx
addq -24(%rcx), %rbx
xorl %esi, %esi
testq %rax, %rax
jne .LBB1_15
# %bb.14:
movl 32(%rbx), %esi
orl $4, %esi
.LBB1_15: # %.invoke
.Ltmp18:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp19:
# %bb.16: # %_ZNSt13basic_fstreamIcSt11char_traitsIcEE4openEPKcSt13_Ios_Openmode.exit
movl $-2147483648, 4(%rsp) # imm = 0x80000000
.Ltmp21:
.cfi_escape 0x2e, 0x00
leaq 176(%rsp), %rdi
leaq 4(%rsp), %rsi
callq _ZNSirsERi
.Ltmp22:
# %bb.17:
movl 4(%rsp), %ebp
cvtsi2sd %ebp, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
.cfi_escape 0x2e, 0x00
callq ceil@PLT
movsd %xmm0, 8(%rsp) # 8-byte Spill
movl %ebp, %ebx
imull %ebx, %ebx
shlq $2, %rbx
.Ltmp24:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Znam
.Ltmp25:
# %bb.18:
movq %rax, %r14
cvttsd2si 8(%rsp), %eax # 8-byte Folded Reload
movl %eax, 8(%rsp) # 4-byte Spill
imull %eax, %ebp
movslq %ebp, %rax
leaq (,%rax,4), %rcx
testl %eax, %eax
movq $-1, %rdi
cmovnsq %rcx, %rdi
.Ltmp27:
.cfi_escape 0x2e, 0x00
callq _Znam
.Ltmp28:
# %bb.19:
.Ltmp30:
movq %rax, %r15
.cfi_escape 0x2e, 0x00
leaq 72(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
.Ltmp31:
# %bb.20: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit
movslq 4(%rsp), %rsi
movslq 8(%rsp), %rax # 4-byte Folded Reload
movq %rax, 88(%rsp) # 8-byte Spill
imulq %rax, %rsi
shlq $2, %rsi
.Ltmp32:
.cfi_escape 0x2e, 0x00
leaq 64(%rsp), %rdi
callq hipMalloc
.Ltmp33:
# %bb.21: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_22: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit
# =>This Inner Loop Header: Depth=1
movl $1325400064, (%r14,%rax,4) # imm = 0x4F000000
incq %rax
cmpq $2000, %rax # imm = 0x7D0
jne .LBB1_22
# %bb.23: # %.preheader259
.Ltmp35:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp36:
# %bb.24: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit158
.Ltmp37:
.cfi_escape 0x2e, 0x00
leaq 176(%rsp), %rdi
leaq 1216(%rsp), %rsi
movl $255, %edx
callq _ZSt17__istream_extractRSiPcl
.Ltmp38:
# %bb.25: # %_ZStrsIcSt11char_traitsIcELm255EERSt13basic_istreamIT_T0_ES6_RAT1__S3_.exit.outer.preheader
xorl %r13d, %r13d
leaq 176(%rsp), %rbx
.p2align 4, 0x90
.LBB1_26: # %_ZStrsIcSt11char_traitsIcELm255EERSt13basic_istreamIT_T0_ES6_RAT1__S3_.exit.outer
# =>This Loop Header: Depth=1
# Child Loop BB1_27 Depth 2
movslq %r13d, %rbp
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_27: # %_ZStrsIcSt11char_traitsIcELm255EERSt13basic_istreamIT_T0_ES6_RAT1__S3_.exit
# Parent Loop BB1_26 Depth=1
# => This Inner Loop Header: Depth=2
movslq 4(%rsp), %rax
imulq %rbp, %rax
addq %r12, %rax
leaq (%r14,%rax,4), %rsi
.Ltmp39:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNSi10_M_extractIfEERSiRT_
.Ltmp40:
# %bb.28: # %_ZNSirsERf.exit
# in Loop: Header=BB1_27 Depth=2
movl 4(%rsp), %eax
incq %r12
cmpl %eax, %r12d
jne .LBB1_27
# %bb.29: # in Loop: Header=BB1_26 Depth=1
incl %r13d
cmpl %eax, %r13d
jge .LBB1_42
# %bb.30: # in Loop: Header=BB1_26 Depth=1
.Ltmp134:
.cfi_escape 0x2e, 0x00
movl $255, %edx
movq %rbx, %rdi
leaq 1216(%rsp), %rsi
callq _ZSt17__istream_extractRSiPcl
.Ltmp135:
jmp .LBB1_26
.LBB1_42:
.Ltmp42:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp43:
# %bb.43: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit164
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_44
# %bb.46: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i195
cmpb $0, 56(%rbx)
je .LBB1_48
# %bb.47:
movzbl 67(%rbx), %eax
jmp .LBB1_50
.LBB1_48:
.Ltmp44:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp45:
# %bb.49: # %.noexc200
movq (%rbx), %rax
.Ltmp46:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp47:
.LBB1_50: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i197
.Ltmp48:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp49:
# %bb.51: # %.noexc202
.Ltmp50:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp51:
# %bb.52: # %_ZNSolsEPFRSoS_E.exit
movl 4(%rsp), %ebx
.Ltmp52:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp53:
# %bb.53: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit167
testl %ebx, %ebx
je .LBB1_54
# %bb.55: # %.lr.ph288
movl 4(%rsp), %eax
movl 8(%rsp), %ecx # 4-byte Reload
imull %ecx, %eax
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rax, %rdx
movq %rdx, 80(%rsp) # 8-byte Spill
shll $9, %ecx
movl %ecx, 40(%rsp) # 4-byte Spill
xorpd %xmm0, %xmm0
movss %xmm0, 20(%rsp) # 4-byte Spill
jmp .LBB1_56
.p2align 4, 0x90
.LBB1_108: # %._crit_edge283
# in Loop: Header=BB1_56 Depth=1
movss 20(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
addss 32(%rsp), %xmm0 # 4-byte Folded Reload
movss %xmm0, 20(%rsp) # 4-byte Spill
movl %eax, %ecx
imull %r12d, %ecx
addl %ebp, %ecx
movslq %ecx, %rcx
movl $1325400064, (%r14,%rcx,4) # imm = 0x4F000000
imull %ebp, %eax
addl %r12d, %eax
cltq
movl $1325400064, (%r14,%rax,4) # imm = 0x4F000000
movl 36(%rsp), %ebx # 4-byte Reload
decl %ebx
je .LBB1_109
.LBB1_56: # =>This Loop Header: Depth=1
# Child Loop BB1_83 Depth 2
# Child Loop BB1_107 Depth 2
.Ltmp55:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp56:
# %bb.57: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit169
# in Loop: Header=BB1_56 Depth=1
.Ltmp58:
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
callq hipEventCreate
.Ltmp59:
# %bb.58: # in Loop: Header=BB1_56 Depth=1
.Ltmp60:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
callq hipEventCreate
.Ltmp61:
# %bb.59: # in Loop: Header=BB1_56 Depth=1
movq 56(%rsp), %rdi
.Ltmp62:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp63:
# %bb.60: # in Loop: Header=BB1_56 Depth=1
movq 72(%rsp), %rdi
movl 4(%rsp), %edx
imull %edx, %edx
shlq $2, %rdx
.Ltmp64:
.cfi_escape 0x2e, 0x00
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp65:
# %bb.61: # in Loop: Header=BB1_56 Depth=1
.Ltmp66:
.cfi_escape 0x2e, 0x00
movq 80(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movabsq $4294967808, %rdx # imm = 0x100000200
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp67:
# %bb.62: # in Loop: Header=BB1_56 Depth=1
testl %eax, %eax
jne .LBB1_65
# %bb.63: # in Loop: Header=BB1_56 Depth=1
movq 72(%rsp), %rax
movq 64(%rsp), %rcx
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
.Ltmp68:
.cfi_escape 0x2e, 0x00
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp69:
# %bb.64: # %.noexc170
# in Loop: Header=BB1_56 Depth=1
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
.Ltmp70:
.cfi_escape 0x2e, 0x10
movl $_Z6kernelPfPi, %edi
leaq 160(%rsp), %r9
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp71:
.LBB1_65: # in Loop: Header=BB1_56 Depth=1
movq 64(%rsp), %rsi
movslq 4(%rsp), %rdx
imulq 88(%rsp), %rdx # 8-byte Folded Reload
shlq $2, %rdx
.Ltmp72:
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp73:
# %bb.66: # in Loop: Header=BB1_56 Depth=1
testl %eax, %eax
jne .LBB1_67
# %bb.73: # %_Z9gpuAssert10hipError_tPcib.exit
# in Loop: Header=BB1_56 Depth=1
movq 24(%rsp), %rdi
.Ltmp76:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp77:
# %bb.74: # in Loop: Header=BB1_56 Depth=1
movq 24(%rsp), %rdi
.Ltmp78:
.cfi_escape 0x2e, 0x00
callq hipEventSynchronize
.Ltmp79:
# %bb.75: # in Loop: Header=BB1_56 Depth=1
movq 56(%rsp), %rsi
movq 24(%rsp), %rdx
.Ltmp80:
.cfi_escape 0x2e, 0x00
leaq 44(%rsp), %rdi
callq hipEventElapsedTime
.Ltmp81:
# %bb.76: # in Loop: Header=BB1_56 Depth=1
movss 44(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss .LCPI1_3(%rip), %xmm0
jne .LBB1_77
jnp .LBB1_79
.LBB1_77: # %.preheader
# in Loop: Header=BB1_56 Depth=1
movss %xmm0, 32(%rsp) # 4-byte Spill
movl %ebx, 36(%rsp) # 4-byte Spill
movl 4(%rsp), %esi
movl %esi, %eax
imull 8(%rsp), %eax # 4-byte Folded Reload
testl %eax, %eax
jle .LBB1_78
# %bb.82: # %.lr.ph.preheader
# in Loop: Header=BB1_56 Depth=1
movl %eax, %edi
movl $-1, %r8d
xorl %ecx, %ecx
xorl %r12d, %r12d
xorl %ebp, %ebp
xorl %r9d, %r9d
movss .LCPI1_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
jmp .LBB1_83
.p2align 4, 0x90
.LBB1_85: # in Loop: Header=BB1_83 Depth=2
incq %rcx
cmpq %rcx, %rdi
je .LBB1_86
.LBB1_83: # %.lr.ph
# Parent Loop BB1_56 Depth=1
# => This Inner Loop Header: Depth=2
movl %ecx, %eax
cltd
idivl 8(%rsp) # 4-byte Folded Reload
cmpl $1, %edx
adcl $0, %r8d
movl %r8d, %edx
imull %esi, %edx
movl (%r15,%rcx,4), %eax
addl %eax, %edx
movslq %edx, %rdx
movss (%r14,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jbe .LBB1_85
# %bb.84: # in Loop: Header=BB1_83 Depth=2
addl 40(%rsp), %eax # 4-byte Folded Reload
movb $1, %r9b
movaps %xmm1, %xmm0
movl %r8d, %ebp
movl %eax, %r12d
jmp .LBB1_85
.p2align 4, 0x90
.LBB1_78: # in Loop: Header=BB1_56 Depth=1
xorl %r9d, %r9d
xorl %ebp, %ebp
xorl %r12d, %r12d
.LBB1_86: # %._crit_edge
# in Loop: Header=BB1_56 Depth=1
testb $1, %r9b
je .LBB1_105
# %bb.87: # in Loop: Header=BB1_56 Depth=1
leal 1(%rbp), %esi
.Ltmp83:
.cfi_escape 0x2e, 0x00
leaq 704(%rsp), %rdi
callq _ZNSolsEi
.Ltmp84:
# %bb.88: # in Loop: Header=BB1_56 Depth=1
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r13
testq %r13, %r13
je .LBB1_89
# %bb.91: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i205
# in Loop: Header=BB1_56 Depth=1
cmpb $0, 56(%r13)
je .LBB1_93
# %bb.92: # in Loop: Header=BB1_56 Depth=1
movzbl 67(%r13), %eax
jmp .LBB1_95
.LBB1_93: # in Loop: Header=BB1_56 Depth=1
.Ltmp85:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp86:
# %bb.94: # %.noexc210
# in Loop: Header=BB1_56 Depth=1
movq (%r13), %rax
.Ltmp87:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp88:
.LBB1_95: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i207
# in Loop: Header=BB1_56 Depth=1
.Ltmp89:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp90:
# %bb.96: # %.noexc212
# in Loop: Header=BB1_56 Depth=1
.Ltmp91:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp92:
# %bb.97: # %_ZNSolsEPFRSoS_E.exit179
# in Loop: Header=BB1_56 Depth=1
leal 1(%r12), %esi
.Ltmp93:
.cfi_escape 0x2e, 0x00
leaq 704(%rsp), %rdi
callq _ZNSolsEi
.Ltmp94:
# %bb.98: # in Loop: Header=BB1_56 Depth=1
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r13
testq %r13, %r13
je .LBB1_89
# %bb.99: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i216
# in Loop: Header=BB1_56 Depth=1
cmpb $0, 56(%r13)
je .LBB1_101
# %bb.100: # in Loop: Header=BB1_56 Depth=1
movzbl 67(%r13), %eax
jmp .LBB1_103
.LBB1_101: # in Loop: Header=BB1_56 Depth=1
.Ltmp95:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp96:
# %bb.102: # %.noexc221
# in Loop: Header=BB1_56 Depth=1
movq (%r13), %rax
.Ltmp97:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp98:
.LBB1_103: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i218
# in Loop: Header=BB1_56 Depth=1
.Ltmp99:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp100:
# %bb.104: # %.noexc223
# in Loop: Header=BB1_56 Depth=1
.Ltmp101:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp102:
.LBB1_105: # %_ZNSolsEPFRSoS_E.exit181
# in Loop: Header=BB1_56 Depth=1
movl 4(%rsp), %eax
testl %eax, %eax
movss .LCPI1_2(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
jle .LBB1_108
# %bb.106: # %.lr.ph282
# in Loop: Header=BB1_56 Depth=1
movl %eax, %edx
imull %ebp, %edx
movl %eax, %esi
imull %r12d, %esi
leal 1(%rax), %ecx
movslq %edx, %rdi
movslq %esi, %r8
movslq %ebp, %rdx
movslq %r12d, %rsi
leaq (%r14,%rdi,4), %rdi
leaq (%r14,%r8,4), %r8
leaq (,%rax,4), %r9
xorl %r10d, %r10d
movq %r14, %r11
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_107: # Parent Loop BB1_56 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdi,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%r8,%rbx,4), %xmm0
mulss %xmm1, %xmm0
movss %xmm0, (%rdi,%rbx,4)
movss %xmm0, (%r8,%rbx,4)
movss (%r11,%rdx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%r11,%rsi,4), %xmm0
mulss %xmm1, %xmm0
movss %xmm0, (%r11,%rsi,4)
movss %xmm0, (%r11,%rdx,4)
movslq %r10d, %r10
movl $1325400064, (%r14,%r10,4) # imm = 0x4F000000
incq %rbx
addq %r9, %r11
addl %ecx, %r10d
cmpq %rbx, %rax
jne .LBB1_107
jmp .LBB1_108
.LBB1_109: # %._crit_edge289.loopexit
movss 20(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
jmp .LBB1_110
.LBB1_54:
xorpd %xmm0, %xmm0
.LBB1_110: # %._crit_edge289
movsd %xmm0, 8(%rsp) # 8-byte Spill
.Ltmp112:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp113:
# %bb.111: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit183
.Ltmp114:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp115:
# %bb.112: # %_ZNSolsEf.exit
.Ltmp116:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $.L.str.9, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp117:
# %bb.113: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit186
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB1_114
# %bb.118: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i227
cmpb $0, 56(%r14)
je .LBB1_120
# %bb.119:
movzbl 67(%r14), %eax
jmp .LBB1_122
.LBB1_120:
.Ltmp118:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp119:
# %bb.121: # %.noexc232
movq (%r14), %rax
.Ltmp120:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp121:
.LBB1_122: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i229
.Ltmp122:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp123:
# %bb.123: # %.noexc234
.Ltmp124:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp125:
# %bb.124: # %_ZNSolsEPFRSoS_E.exit188
.Ltmp126:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.10, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp127:
# %bb.125: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit190
movq stdin(%rip), %rdi
.cfi_escape 0x2e, 0x00
callq getc
.cfi_escape 0x2e, 0x00
leaq 176(%rsp), %rdi
movl $_ZTTSt13basic_fstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt13basic_fstreamIcSt11char_traitsIcEED2Ev
leaq 440(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
.cfi_escape 0x2e, 0x00
movq 48(%rsp), %rdi # 8-byte Reload
callq _ZdlPv
.cfi_escape 0x2e, 0x00
leaq 704(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
xorl %eax, %eax
addq $1736, %rsp # imm = 0x6C8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_79:
.cfi_def_cfa_offset 1792
.Ltmp107:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $29, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp108:
# %bb.80: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit175
.Ltmp109:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
.Ltmp110:
# %bb.81: # %_ZNSolsEPFRSoS_E.exit177
.cfi_escape 0x2e, 0x00
xorl %edi, %edi
callq exit
.LBB1_67:
movq stderr(%rip), %r14
.Ltmp74:
.cfi_escape 0x2e, 0x00
movl %eax, %ebx
movl %eax, %edi
callq hipGetErrorString
.Ltmp75:
# %bb.68: # %.noexc173
.cfi_escape 0x2e, 0x00
movl $.L.str.12, %esi
movl $.L.str.6, %ecx
movq %r14, %rdi
movq %rax, %rdx
movl $152, %r8d
xorl %eax, %eax
callq fprintf
.cfi_escape 0x2e, 0x00
movl %ebx, %edi
callq exit
.LBB1_89: # %.invoke320
.Ltmp104:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp105:
# %bb.90: # %.cont
.LBB1_2:
.Ltmp137:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp138:
# %bb.3: # %.noexc
.LBB1_44:
.Ltmp131:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp132:
# %bb.45: # %.noexc199
.LBB1_114:
.Ltmp128:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp129:
# %bb.117: # %.noexc231
.LBB1_126:
.Ltmp54:
jmp .LBB1_127
.LBB1_37:
.Ltmp29:
jmp .LBB1_127
.LBB1_36:
.Ltmp26:
jmp .LBB1_127
.LBB1_35:
.Ltmp23:
jmp .LBB1_127
.LBB1_33:
.Ltmp13:
movq %rax, %rbx
jmp .LBB1_128
.LBB1_32:
.Ltmp10:
movq %rax, %rbx
jmp .LBB1_129
.LBB1_38:
.Ltmp34:
jmp .LBB1_127
.LBB1_34:
.Ltmp20:
jmp .LBB1_127
.LBB1_31:
.Ltmp139:
movq %rax, %rbx
jmp .LBB1_129
.LBB1_41: # %.loopexit.split-lp255
.Ltmp133:
jmp .LBB1_127
.LBB1_70: # %.loopexit.split-lp
.Ltmp130:
jmp .LBB1_127
.LBB1_116: # %.loopexit.split-lp250
.Ltmp106:
jmp .LBB1_127
.LBB1_69: # %.loopexit
.Ltmp57:
jmp .LBB1_127
.LBB1_72: # %.loopexit.split-lp245
.Ltmp111:
jmp .LBB1_127
.LBB1_40: # %.loopexit254.loopexit.split-lp
.Ltmp136:
jmp .LBB1_127
.LBB1_115: # %.loopexit249
.Ltmp103:
jmp .LBB1_127
.LBB1_71: # %.loopexit244
.Ltmp82:
jmp .LBB1_127
.LBB1_39: # %.loopexit254.loopexit
.Ltmp41:
.LBB1_127:
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
leaq 176(%rsp), %rdi
movl $_ZTTSt13basic_fstreamIcSt11char_traitsIcEE, %esi
callq _ZNSt13basic_fstreamIcSt11char_traitsIcEED2Ev
leaq 440(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq _ZNSt8ios_baseD2Ev
.LBB1_128: # %_ZNSt6vectorIcSaIcEED2Ev.exit193
.cfi_escape 0x2e, 0x00
movq 48(%rsp), %rdi # 8-byte Reload
callq _ZdlPv
.LBB1_129:
.cfi_escape 0x2e, 0x00
leaq 704(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp7-.Ltmp0 # Call between .Ltmp0 and .Ltmp7
.uleb128 .Ltmp139-.Lfunc_begin0 # jumps to .Ltmp139
.byte 0 # On action: cleanup
.uleb128 .Ltmp8-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp9-.Ltmp8 # Call between .Ltmp8 and .Ltmp9
.uleb128 .Ltmp10-.Lfunc_begin0 # jumps to .Ltmp10
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp11-.Ltmp9 # Call between .Ltmp9 and .Ltmp11
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp11-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp12-.Ltmp11 # Call between .Ltmp11 and .Ltmp12
.uleb128 .Ltmp13-.Lfunc_begin0 # jumps to .Ltmp13
.byte 0 # On action: cleanup
.uleb128 .Ltmp14-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp19-.Ltmp14 # Call between .Ltmp14 and .Ltmp19
.uleb128 .Ltmp20-.Lfunc_begin0 # jumps to .Ltmp20
.byte 0 # On action: cleanup
.uleb128 .Ltmp21-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp22-.Ltmp21 # Call between .Ltmp21 and .Ltmp22
.uleb128 .Ltmp23-.Lfunc_begin0 # jumps to .Ltmp23
.byte 0 # On action: cleanup
.uleb128 .Ltmp22-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp24-.Ltmp22 # Call between .Ltmp22 and .Ltmp24
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp24-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp25-.Ltmp24 # Call between .Ltmp24 and .Ltmp25
.uleb128 .Ltmp26-.Lfunc_begin0 # jumps to .Ltmp26
.byte 0 # On action: cleanup
.uleb128 .Ltmp27-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp28-.Ltmp27 # Call between .Ltmp27 and .Ltmp28
.uleb128 .Ltmp29-.Lfunc_begin0 # jumps to .Ltmp29
.byte 0 # On action: cleanup
.uleb128 .Ltmp30-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp33-.Ltmp30 # Call between .Ltmp30 and .Ltmp33
.uleb128 .Ltmp34-.Lfunc_begin0 # jumps to .Ltmp34
.byte 0 # On action: cleanup
.uleb128 .Ltmp35-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp38-.Ltmp35 # Call between .Ltmp35 and .Ltmp38
.uleb128 .Ltmp133-.Lfunc_begin0 # jumps to .Ltmp133
.byte 0 # On action: cleanup
.uleb128 .Ltmp39-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Ltmp40-.Ltmp39 # Call between .Ltmp39 and .Ltmp40
.uleb128 .Ltmp41-.Lfunc_begin0 # jumps to .Ltmp41
.byte 0 # On action: cleanup
.uleb128 .Ltmp134-.Lfunc_begin0 # >> Call Site 14 <<
.uleb128 .Ltmp135-.Ltmp134 # Call between .Ltmp134 and .Ltmp135
.uleb128 .Ltmp136-.Lfunc_begin0 # jumps to .Ltmp136
.byte 0 # On action: cleanup
.uleb128 .Ltmp42-.Lfunc_begin0 # >> Call Site 15 <<
.uleb128 .Ltmp51-.Ltmp42 # Call between .Ltmp42 and .Ltmp51
.uleb128 .Ltmp133-.Lfunc_begin0 # jumps to .Ltmp133
.byte 0 # On action: cleanup
.uleb128 .Ltmp52-.Lfunc_begin0 # >> Call Site 16 <<
.uleb128 .Ltmp53-.Ltmp52 # Call between .Ltmp52 and .Ltmp53
.uleb128 .Ltmp54-.Lfunc_begin0 # jumps to .Ltmp54
.byte 0 # On action: cleanup
.uleb128 .Ltmp55-.Lfunc_begin0 # >> Call Site 17 <<
.uleb128 .Ltmp56-.Ltmp55 # Call between .Ltmp55 and .Ltmp56
.uleb128 .Ltmp57-.Lfunc_begin0 # jumps to .Ltmp57
.byte 0 # On action: cleanup
.uleb128 .Ltmp58-.Lfunc_begin0 # >> Call Site 18 <<
.uleb128 .Ltmp81-.Ltmp58 # Call between .Ltmp58 and .Ltmp81
.uleb128 .Ltmp82-.Lfunc_begin0 # jumps to .Ltmp82
.byte 0 # On action: cleanup
.uleb128 .Ltmp83-.Lfunc_begin0 # >> Call Site 19 <<
.uleb128 .Ltmp102-.Ltmp83 # Call between .Ltmp83 and .Ltmp102
.uleb128 .Ltmp103-.Lfunc_begin0 # jumps to .Ltmp103
.byte 0 # On action: cleanup
.uleb128 .Ltmp112-.Lfunc_begin0 # >> Call Site 20 <<
.uleb128 .Ltmp127-.Ltmp112 # Call between .Ltmp112 and .Ltmp127
.uleb128 .Ltmp130-.Lfunc_begin0 # jumps to .Ltmp130
.byte 0 # On action: cleanup
.uleb128 .Ltmp107-.Lfunc_begin0 # >> Call Site 21 <<
.uleb128 .Ltmp75-.Ltmp107 # Call between .Ltmp107 and .Ltmp75
.uleb128 .Ltmp111-.Lfunc_begin0 # jumps to .Ltmp111
.byte 0 # On action: cleanup
.uleb128 .Ltmp104-.Lfunc_begin0 # >> Call Site 22 <<
.uleb128 .Ltmp105-.Ltmp104 # Call between .Ltmp104 and .Ltmp105
.uleb128 .Ltmp106-.Lfunc_begin0 # jumps to .Ltmp106
.byte 0 # On action: cleanup
.uleb128 .Ltmp137-.Lfunc_begin0 # >> Call Site 23 <<
.uleb128 .Ltmp138-.Ltmp137 # Call between .Ltmp137 and .Ltmp138
.uleb128 .Ltmp139-.Lfunc_begin0 # jumps to .Ltmp139
.byte 0 # On action: cleanup
.uleb128 .Ltmp131-.Lfunc_begin0 # >> Call Site 24 <<
.uleb128 .Ltmp132-.Ltmp131 # Call between .Ltmp131 and .Ltmp132
.uleb128 .Ltmp133-.Lfunc_begin0 # jumps to .Ltmp133
.byte 0 # On action: cleanup
.uleb128 .Ltmp128-.Lfunc_begin0 # >> Call Site 25 <<
.uleb128 .Ltmp129-.Ltmp128 # Call between .Ltmp128 and .Ltmp129
.uleb128 .Ltmp130-.Lfunc_begin0 # jumps to .Ltmp130
.byte 0 # On action: cleanup
.uleb128 .Ltmp129-.Lfunc_begin0 # >> Call Site 26 <<
.uleb128 .Lfunc_end1-.Ltmp129 # Call between .Ltmp129 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPfPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPfPi,@object # @_Z6kernelPfPi
.section .rodata,"a",@progbits
.globl _Z6kernelPfPi
.p2align 3, 0x0
_Z6kernelPfPi:
.quad _Z21__device_stub__kernelPfPi
.size _Z6kernelPfPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "out.txt"
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Please enter the file path to the distance matrix: "
.size .L.str.1, 52
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Reading input file"
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " ..."
.size .L.str.3, 5
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Working "
.size .L.str.4, 9
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "."
.size .L.str.5, 2
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/Soroosh129/GPU-UPGMA/master/main.hip"
.size .L.str.6, 94
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\nSomething went wrong on GPU."
.size .L.str.7, 30
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\nTime: "
.size .L.str.8, 8
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "ms"
.size .L.str.9, 3
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Press Enter to exit."
.size .L.str.10, 21
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "\nGPUassert: %s %s %d\n"
.size .L.str.12, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPfPi"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPfPi
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z6kernelPfPi
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelPfPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R5, R3, c[0x0][0x0], R0 ; /* 0x0000000003057a24 */
/* 0x001fc800078e0200 */
/*0060*/ IMAD.WIDE R4, R5, R2, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fcc00078e0202 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ ISETP.GT.AND P5, PT, R0.reuse, 0xff, PT ; /* 0x000000ff0000780c */
/* 0x040fe20003fa4270 */
/*0090*/ BSSY B0, 0x1b0 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*00a0*/ ISETP.GT.AND P6, PT, R0.reuse, 0x7f, PT ; /* 0x0000007f0000780c */
/* 0x040fe20003fc4270 */
/*00b0*/ STS [R0.X4+0x800], R0 ; /* 0x0008000000007388 */
/* 0x0001e20000004800 */
/*00c0*/ ISETP.GT.AND P0, PT, R0.reuse, 0x3f, PT ; /* 0x0000003f0000780c */
/* 0x040fe40003f04270 */
/*00d0*/ ISETP.GT.AND P1, PT, R0.reuse, 0x1f, PT ; /* 0x0000001f0000780c */
/* 0x040fe40003f24270 */
/*00e0*/ ISETP.GT.AND P2, PT, R0.reuse, 0xf, PT ; /* 0x0000000f0000780c */
/* 0x040fe40003f44270 */
/*00f0*/ ISETP.GT.AND P3, PT, R0, 0x7, PT ; /* 0x000000070000780c */
/* 0x000fc40003f64270 */
/*0100*/ ISETP.GT.AND P4, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f84270 */
/*0110*/ STS [R0.X4], R5 ; /* 0x0000000500007388 */
/* 0x0041e80000004800 */
/*0120*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0130*/ @P5 BRA 0x1a0 ; /* 0x0000006000005947 */
/* 0x000fea0003800000 */
/*0140*/ LDS R4, [R0.X4] ; /* 0x0000000000047984 */
/* 0x001fe80000004800 */
/*0150*/ LDS R5, [R0.X4+0x400] ; /* 0x0004000000057984 */
/* 0x000e240000004800 */
/*0160*/ FSETP.GEU.AND P5, PT, R5, R4, PT ; /* 0x000000040500720b */
/* 0x001fda0003fae000 */
/*0170*/ @!P5 LDS R7, [R0.X4+0xc00] ; /* 0x000c00000007d984 */
/* 0x000e280000004800 */
/*0180*/ @!P5 STS [R0.X4], R5 ; /* 0x000000050000d388 */
/* 0x0003e80000004800 */
/*0190*/ @!P5 STS [R0.X4+0x800], R7 ; /* 0x000800070000d388 */
/* 0x0013e40000004800 */
/*01a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01c0*/ ISETP.GT.AND P5, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fca0003fa4270 */
/*01d0*/ BSSY B0, 0x260 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*01e0*/ @P6 BRA 0x250 ; /* 0x0000006000006947 */
/* 0x000fea0003800000 */
/*01f0*/ LDS R4, [R0.X4] ; /* 0x0000000000047984 */
/* 0x000fe80000004800 */
/*0200*/ LDS R5, [R0.X4+0x200] ; /* 0x0002000000057984 */
/* 0x002e240000004800 */
/*0210*/ FSETP.GEU.AND P6, PT, R5, R4, PT ; /* 0x000000040500720b */
/* 0x001fda0003fce000 */
/*0220*/ @!P6 LDS R7, [R0.X4+0xa00] ; /* 0x000a00000007e984 */
/* 0x000e280000004800 */
/*0230*/ @!P6 STS [R0.X4], R5 ; /* 0x000000050000e388 */
/* 0x0003e80000004800 */
/*0240*/ @!P6 STS [R0.X4+0x800], R7 ; /* 0x000800070000e388 */
/* 0x0013e40000004800 */
/*0250*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0260*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0270*/ ISETP.GT.AND P6, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fca0003fc4270 */
/*0280*/ BSSY B0, 0x310 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0290*/ @P0 BRA 0x300 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*02a0*/ LDS R4, [R0.X4] ; /* 0x0000000000047984 */
/* 0x000fe80000004800 */
/*02b0*/ LDS R5, [R0.X4+0x100] ; /* 0x0001000000057984 */
/* 0x002e240000004800 */
/*02c0*/ FSETP.GEU.AND P0, PT, R5, R4, PT ; /* 0x000000040500720b */
/* 0x001fda0003f0e000 */
/*02d0*/ @!P0 LDS R7, [R0.X4+0x900] ; /* 0x0009000000078984 */
/* 0x000e280000004800 */
/*02e0*/ @!P0 STS [R0.X4], R5 ; /* 0x0000000500008388 */
/* 0x0003e80000004800 */
/*02f0*/ @!P0 STS [R0.X4+0x800], R7 ; /* 0x0008000700008388 */
/* 0x0013e40000004800 */
/*0300*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0310*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0320*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fca0003f05270 */
/*0330*/ BSSY B0, 0x3c0 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0340*/ @P1 BRA 0x3b0 ; /* 0x0000006000001947 */
/* 0x000fea0003800000 */
/*0350*/ LDS R4, [R0.X4] ; /* 0x0000000000047984 */
/* 0x000fe80000004800 */
/*0360*/ LDS R5, [R0.X4+0x80] ; /* 0x0000800000057984 */
/* 0x002e240000004800 */
/*0370*/ FSETP.GEU.AND P1, PT, R5, R4, PT ; /* 0x000000040500720b */
/* 0x001fda0003f2e000 */
/*0380*/ @!P1 LDS R7, [R0.X4+0x880] ; /* 0x0008800000079984 */
/* 0x000e280000004800 */
/*0390*/ @!P1 STS [R0.X4], R5 ; /* 0x0000000500009388 */
/* 0x0003e80000004800 */
/*03a0*/ @!P1 STS [R0.X4+0x800], R7 ; /* 0x0008000700009388 */
/* 0x0013e40000004800 */
/*03b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03d0*/ BSSY B0, 0x460 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*03e0*/ @P2 BRA 0x450 ; /* 0x0000006000002947 */
/* 0x000fea0003800000 */
/*03f0*/ LDS R4, [R0.X4] ; /* 0x0000000000047984 */
/* 0x000fe80000004800 */
/*0400*/ LDS R5, [R0.X4+0x40] ; /* 0x0000400000057984 */
/* 0x002e240000004800 */
/*0410*/ FSETP.GEU.AND P1, PT, R5, R4, PT ; /* 0x000000040500720b */
/* 0x001fda0003f2e000 */
/*0420*/ @!P1 LDS R7, [R0.X4+0x840] ; /* 0x0008400000079984 */
/* 0x000e280000004800 */
/*0430*/ @!P1 STS [R0.X4], R5 ; /* 0x0000000500009388 */
/* 0x0003e80000004800 */
/*0440*/ @!P1 STS [R0.X4+0x800], R7 ; /* 0x0008000700009388 */
/* 0x0013e40000004800 */
/*0450*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0460*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0470*/ BSSY B0, 0x500 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0480*/ @P3 BRA 0x4f0 ; /* 0x0000006000003947 */
/* 0x000fea0003800000 */
/*0490*/ LDS R4, [R0.X4] ; /* 0x0000000000047984 */
/* 0x000fe80000004800 */
/*04a0*/ LDS R5, [R0.X4+0x20] ; /* 0x0000200000057984 */
/* 0x002e240000004800 */
/*04b0*/ FSETP.GEU.AND P1, PT, R5, R4, PT ; /* 0x000000040500720b */
/* 0x001fda0003f2e000 */
/*04c0*/ @!P1 LDS R7, [R0.X4+0x820] ; /* 0x0008200000079984 */
/* 0x000e280000004800 */
/*04d0*/ @!P1 STS [R0.X4], R5 ; /* 0x0000000500009388 */
/* 0x0003e80000004800 */
/*04e0*/ @!P1 STS [R0.X4+0x800], R7 ; /* 0x0008000700009388 */
/* 0x0013e40000004800 */
/*04f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0500*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0510*/ BSSY B0, 0x5a0 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0520*/ @P4 BRA 0x590 ; /* 0x0000006000004947 */
/* 0x000fea0003800000 */
/*0530*/ LDS R4, [R0.X4] ; /* 0x0000000000047984 */
/* 0x000fe80000004800 */
/*0540*/ LDS R5, [R0.X4+0x10] ; /* 0x0000100000057984 */
/* 0x002e240000004800 */
/*0550*/ FSETP.GEU.AND P1, PT, R5, R4, PT ; /* 0x000000040500720b */
/* 0x001fda0003f2e000 */
/*0560*/ @!P1 LDS R7, [R0.X4+0x810] ; /* 0x0008100000079984 */
/* 0x000e280000004800 */
/*0570*/ @!P1 STS [R0.X4], R5 ; /* 0x0000000500009388 */
/* 0x0003e80000004800 */
/*0580*/ @!P1 STS [R0.X4+0x800], R7 ; /* 0x0008000700009388 */
/* 0x0013e40000004800 */
/*0590*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*05b0*/ BSSY B0, 0x640 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*05c0*/ @P5 BRA 0x630 ; /* 0x0000006000005947 */
/* 0x000fea0003800000 */
/*05d0*/ LDS R4, [R0.X4] ; /* 0x0000000000047984 */
/* 0x000fe80000004800 */
/*05e0*/ LDS R5, [R0.X4+0x8] ; /* 0x0000080000057984 */
/* 0x002e240000004800 */
/*05f0*/ FSETP.GEU.AND P1, PT, R5, R4, PT ; /* 0x000000040500720b */
/* 0x001fda0003f2e000 */
/*0600*/ @!P1 LDS R7, [R0.X4+0x808] ; /* 0x0008080000079984 */
/* 0x000e280000004800 */
/*0610*/ @!P1 STS [R0.X4], R5 ; /* 0x0000000500009388 */
/* 0x0003e80000004800 */
/*0620*/ @!P1 STS [R0.X4+0x800], R7 ; /* 0x0008000700009388 */
/* 0x0013e40000004800 */
/*0630*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0640*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0650*/ BSSY B0, 0x6e0 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0660*/ @P6 BRA 0x6d0 ; /* 0x0000006000006947 */
/* 0x000fea0003800000 */
/*0670*/ LDS R4, [R0.X4] ; /* 0x0000000000047984 */
/* 0x000fe80000004800 */
/*0680*/ LDS R5, [R0.X4+0x4] ; /* 0x0000040000057984 */
/* 0x002e240000004800 */
/*0690*/ FSETP.GEU.AND P1, PT, R5, R4, PT ; /* 0x000000040500720b */
/* 0x001fda0003f2e000 */
/*06a0*/ @!P1 LDS R7, [R0.X4+0x804] ; /* 0x0008040000079984 */
/* 0x000e280000004800 */
/*06b0*/ @!P1 STS [R0.X4], R5 ; /* 0x0000000500009388 */
/* 0x0003e80000004800 */
/*06c0*/ @!P1 STS [R0.X4+0x800], R7 ; /* 0x0008000700009388 */
/* 0x0013e40000004800 */
/*06d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*06f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0700*/ LDS R5, [0x800] ; /* 0x00080000ff057984 */
/* 0x002e220000000800 */
/*0710*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0202 */
/*0720*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0730*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0740*/ BRA 0x740; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPfPi
.globl _Z6kernelPfPi
.p2align 8
.type _Z6kernelPfPi,@function
_Z6kernelPfPi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_movk_i32 s3, 0x100
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v3, v[1:2], off
v_lshlrev_b32_e32 v1, 2, v0
v_add_nc_u32_e32 v2, 0x800, v1
s_waitcnt vmcnt(0)
ds_store_2addr_stride64_b32 v1, v3, v0 offset1:8
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s4
s_lshr_b32 s4, s3, 31
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s3, s4
s_add_i32 s3, s3, 1
s_ashr_i32 s4, s4, 1
s_cmp_gt_u32 s3, 2
s_mov_b32 s3, s4
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_5
.LBB0_2:
s_mov_b32 s4, exec_lo
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_1
v_add_nc_u32_e32 v3, s3, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v4, 2, v3
ds_load_b32 v3, v4
ds_load_b32 v5, v1
s_waitcnt lgkmcnt(0)
v_cmp_lt_f32_e32 vcc_lo, v3, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_1
ds_load_b32 v4, v4 offset:2048
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(1)
ds_store_b32 v2, v4
s_branch .LBB0_1
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0 offset:2048
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPfPi
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPfPi, .Lfunc_end0-_Z6kernelPfPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPfPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPfPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void ker_gkylCartFieldScale(unsigned s, unsigned nv, double fact, double *out)
{
for (int n = blockIdx.x*blockDim.x + threadIdx.x + s; n < s + nv; n += blockDim.x * gridDim.x)
out[n] *= fact;
} | code for sm_80
Function : _Z22ker_gkylCartFieldScalejjdPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIADD3 UR4, UR5, UR4, URZ ; /* 0x0000000405047290 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ IADD3 R0, R0, c[0x0][0x160], RZ ; /* 0x0000580000007a10 */
/* 0x000fc80007ffe0ff */
/*0070*/ ISETP.GE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06070 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*00a0*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x001fd400000001ff */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0203 */
/*00c0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000602047981 */
/* 0x000ea2000c1e1b00 */
/*00d0*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x000fca0000000f00 */
/*00e0*/ IMAD R0, R7, c[0x0][0xc], R0 ; /* 0x0000030007007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fe2000bf06070 */
/*0100*/ DMUL R4, R4, c[0x0][0x168] ; /* 0x00005a0004047a28 */
/* 0x004e0e0000000000 */
/*0110*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x0011ea000c101b06 */
/*0120*/ @!P0 BRA 0xa0 ; /* 0xffffff7000008947 */
/* 0x000fea000383ffff */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void ker_gkylCartFieldScale(unsigned s, unsigned nv, double fact, double *out)
{
for (int n = blockIdx.x*blockDim.x + threadIdx.x + s; n < s + nv; n += blockDim.x * gridDim.x)
out[n] *= fact;
} | .file "tmpxft_00074f10_00000000-6_ker_gkylCartFieldScale.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z22ker_gkylCartFieldScalejjdPdjjdPd
.type _Z45__device_stub__Z22ker_gkylCartFieldScalejjdPdjjdPd, @function
_Z45__device_stub__Z22ker_gkylCartFieldScalejjdPdjjdPd:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movsd %xmm0, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22ker_gkylCartFieldScalejjdPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z22ker_gkylCartFieldScalejjdPdjjdPd, .-_Z45__device_stub__Z22ker_gkylCartFieldScalejjdPdjjdPd
.globl _Z22ker_gkylCartFieldScalejjdPd
.type _Z22ker_gkylCartFieldScalejjdPd, @function
_Z22ker_gkylCartFieldScalejjdPd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z22ker_gkylCartFieldScalejjdPdjjdPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z22ker_gkylCartFieldScalejjdPd, .-_Z22ker_gkylCartFieldScalejjdPd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22ker_gkylCartFieldScalejjdPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22ker_gkylCartFieldScalejjdPd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void ker_gkylCartFieldScale(unsigned s, unsigned nv, double fact, double *out)
{
for (int n = blockIdx.x*blockDim.x + threadIdx.x + s; n < s + nv; n += blockDim.x * gridDim.x)
out[n] *= fact;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ker_gkylCartFieldScale(unsigned s, unsigned nv, double fact, double *out)
{
for (int n = blockIdx.x*blockDim.x + threadIdx.x + s; n < s + nv; n += blockDim.x * gridDim.x)
out[n] *= fact;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ker_gkylCartFieldScale(unsigned s, unsigned nv, double fact, double *out)
{
for (int n = blockIdx.x*blockDim.x + threadIdx.x + s; n < s + nv; n += blockDim.x * gridDim.x)
out[n] *= fact;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22ker_gkylCartFieldScalejjdPd
.globl _Z22ker_gkylCartFieldScalejjdPd
.p2align 8
.type _Z22ker_gkylCartFieldScalejjdPd,@function
_Z22ker_gkylCartFieldScalejjdPd:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[6:7], s[0:1], 0x0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_add_i32 s4, s7, s6
s_mul_i32 s15, s15, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add3_u32 v0, s15, s6, v0
s_mov_b32 s6, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_3
s_load_b32 s6, s[2:3], 0x0
s_load_b128 s[0:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_mul_i32 s5, s6, s5
s_mov_b32 s6, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 3, v[0:1]
v_add_nc_u32_e32 v0, s5, v0
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s4, v0
global_load_b64 v[3:4], v[1:2], off
s_or_b32 s6, vcc_lo, s6
s_waitcnt vmcnt(0)
v_mul_f64 v[3:4], v[3:4], s[0:1]
global_store_b64 v[1:2], v[3:4], off
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22ker_gkylCartFieldScalejjdPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22ker_gkylCartFieldScalejjdPd, .Lfunc_end0-_Z22ker_gkylCartFieldScalejjdPd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22ker_gkylCartFieldScalejjdPd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22ker_gkylCartFieldScalejjdPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ker_gkylCartFieldScale(unsigned s, unsigned nv, double fact, double *out)
{
for (int n = blockIdx.x*blockDim.x + threadIdx.x + s; n < s + nv; n += blockDim.x * gridDim.x)
out[n] *= fact;
} | .text
.file "ker_gkylCartFieldScale.hip"
.globl _Z37__device_stub__ker_gkylCartFieldScalejjdPd # -- Begin function _Z37__device_stub__ker_gkylCartFieldScalejjdPd
.p2align 4, 0x90
.type _Z37__device_stub__ker_gkylCartFieldScalejjdPd,@function
_Z37__device_stub__ker_gkylCartFieldScalejjdPd: # @_Z37__device_stub__ker_gkylCartFieldScalejjdPd
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movsd %xmm0, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22ker_gkylCartFieldScalejjdPd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z37__device_stub__ker_gkylCartFieldScalejjdPd, .Lfunc_end0-_Z37__device_stub__ker_gkylCartFieldScalejjdPd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22ker_gkylCartFieldScalejjdPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22ker_gkylCartFieldScalejjdPd,@object # @_Z22ker_gkylCartFieldScalejjdPd
.section .rodata,"a",@progbits
.globl _Z22ker_gkylCartFieldScalejjdPd
.p2align 3, 0x0
_Z22ker_gkylCartFieldScalejjdPd:
.quad _Z37__device_stub__ker_gkylCartFieldScalejjdPd
.size _Z22ker_gkylCartFieldScalejjdPd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22ker_gkylCartFieldScalejjdPd"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__ker_gkylCartFieldScalejjdPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22ker_gkylCartFieldScalejjdPd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z22ker_gkylCartFieldScalejjdPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIADD3 UR4, UR5, UR4, URZ ; /* 0x0000000405047290 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ IADD3 R0, R0, c[0x0][0x160], RZ ; /* 0x0000580000007a10 */
/* 0x000fc80007ffe0ff */
/*0070*/ ISETP.GE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06070 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*00a0*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x001fd400000001ff */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0203 */
/*00c0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000602047981 */
/* 0x000ea2000c1e1b00 */
/*00d0*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x000fca0000000f00 */
/*00e0*/ IMAD R0, R7, c[0x0][0xc], R0 ; /* 0x0000030007007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fe2000bf06070 */
/*0100*/ DMUL R4, R4, c[0x0][0x168] ; /* 0x00005a0004047a28 */
/* 0x004e0e0000000000 */
/*0110*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x0011ea000c101b06 */
/*0120*/ @!P0 BRA 0xa0 ; /* 0xffffff7000008947 */
/* 0x000fea000383ffff */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22ker_gkylCartFieldScalejjdPd
.globl _Z22ker_gkylCartFieldScalejjdPd
.p2align 8
.type _Z22ker_gkylCartFieldScalejjdPd,@function
_Z22ker_gkylCartFieldScalejjdPd:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[6:7], s[0:1], 0x0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_add_i32 s4, s7, s6
s_mul_i32 s15, s15, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add3_u32 v0, s15, s6, v0
s_mov_b32 s6, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_3
s_load_b32 s6, s[2:3], 0x0
s_load_b128 s[0:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_mul_i32 s5, s6, s5
s_mov_b32 s6, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 3, v[0:1]
v_add_nc_u32_e32 v0, s5, v0
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s4, v0
global_load_b64 v[3:4], v[1:2], off
s_or_b32 s6, vcc_lo, s6
s_waitcnt vmcnt(0)
v_mul_f64 v[3:4], v[3:4], s[0:1]
global_store_b64 v[1:2], v[3:4], off
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22ker_gkylCartFieldScalejjdPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22ker_gkylCartFieldScalejjdPd, .Lfunc_end0-_Z22ker_gkylCartFieldScalejjdPd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22ker_gkylCartFieldScalejjdPd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22ker_gkylCartFieldScalejjdPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00074f10_00000000-6_ker_gkylCartFieldScale.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z22ker_gkylCartFieldScalejjdPdjjdPd
.type _Z45__device_stub__Z22ker_gkylCartFieldScalejjdPdjjdPd, @function
_Z45__device_stub__Z22ker_gkylCartFieldScalejjdPdjjdPd:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movsd %xmm0, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22ker_gkylCartFieldScalejjdPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z22ker_gkylCartFieldScalejjdPdjjdPd, .-_Z45__device_stub__Z22ker_gkylCartFieldScalejjdPdjjdPd
.globl _Z22ker_gkylCartFieldScalejjdPd
.type _Z22ker_gkylCartFieldScalejjdPd, @function
_Z22ker_gkylCartFieldScalejjdPd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z22ker_gkylCartFieldScalejjdPdjjdPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z22ker_gkylCartFieldScalejjdPd, .-_Z22ker_gkylCartFieldScalejjdPd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z22ker_gkylCartFieldScalejjdPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z22ker_gkylCartFieldScalejjdPd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ker_gkylCartFieldScale.hip"
.globl _Z37__device_stub__ker_gkylCartFieldScalejjdPd # -- Begin function _Z37__device_stub__ker_gkylCartFieldScalejjdPd
.p2align 4, 0x90
.type _Z37__device_stub__ker_gkylCartFieldScalejjdPd,@function
_Z37__device_stub__ker_gkylCartFieldScalejjdPd: # @_Z37__device_stub__ker_gkylCartFieldScalejjdPd
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movsd %xmm0, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22ker_gkylCartFieldScalejjdPd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z37__device_stub__ker_gkylCartFieldScalejjdPd, .Lfunc_end0-_Z37__device_stub__ker_gkylCartFieldScalejjdPd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22ker_gkylCartFieldScalejjdPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z22ker_gkylCartFieldScalejjdPd,@object # @_Z22ker_gkylCartFieldScalejjdPd
.section .rodata,"a",@progbits
.globl _Z22ker_gkylCartFieldScalejjdPd
.p2align 3, 0x0
_Z22ker_gkylCartFieldScalejjdPd:
.quad _Z37__device_stub__ker_gkylCartFieldScalejjdPd
.size _Z22ker_gkylCartFieldScalejjdPd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z22ker_gkylCartFieldScalejjdPd"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__ker_gkylCartFieldScalejjdPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z22ker_gkylCartFieldScalejjdPd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Copyright (c) Microsoft Corporation.
// Licensed under the MIT License.
// GPU SM copy benchmark tests dtoh/htod data transfer bandwidth initiated by GPU SM.
#include <chrono>
#include <cstdio>
#include <cstring>
#include <string>
#include <cuda.h>
#include <cuda_runtime.h>
// Argurment index used in argument parsing.
enum class ArgIdx { kGpuId = 1, kCopyDirection, kSize, kNumLoops, kNumArgs };
// Stored arguments for this program.
struct Args {
// ID of GPU used in this benchmark.
int gpu_id = 0;
// Data transfer direction, can be "dtoh" or "htod".
std::string copy_direction;
// Data buffer size used.
uint64_t size = 0;
// Number of loops in data transfer benchmark.
uint64_t num_loops = 0;
};
struct Buffers {
// Original data buffer.
uint8_t *data_buf = nullptr;
// Buffer to validate the correctness of data transfer.
uint8_t *check_buf = nullptr;
// Data buffer in host memory.
uint8_t *host_buf = nullptr;
// Device pointer of the data buffer in host memory.
uint8_t *host_buf_dev_ptr = nullptr;
// Data buffer in device memory
uint8_t *dev_buf = nullptr;
};
// Pring usage of this program.
void PrintUsage() {
printf("Usage: gpu_sm_copy "
"<gpu-id> "
"<copy-direction: dtoh|htod> "
"<size> "
"<num_loops>\n");
}
// Prepare data buffers to be used.
int PrepareBuf(const Args &args, Buffers *buffers) {
cudaError_t cuda_err = cudaSuccess;
// Generate data to copy
buffers->data_buf = static_cast<uint8_t *>(malloc(args.size));
for (int i = 0; i < args.size; i++) {
buffers->data_buf[i] = static_cast<uint8_t>(i % 256);
}
// Reset check buffer
buffers->check_buf = static_cast<uint8_t *>(malloc(args.size));
memset(buffers->check_buf, 0, args.size);
// Allocate host buffer
buffers->host_buf = static_cast<uint8_t *>(malloc(args.size));
cuda_err = cudaHostRegister(buffers->host_buf, args.size, cudaHostRegisterMapped);
if (cuda_err != cudaSuccess) {
fprintf(stderr, "PrepareBuf::cudaHostRegister error: %d\n", cuda_err);
return -1;
}
cuda_err = cudaHostGetDevicePointer((void **)(&(buffers->host_buf_dev_ptr)), buffers->host_buf, 0);
if (cuda_err != cudaSuccess) {
fprintf(stderr, "PrepareBuf::cudaHostGetDevicePointer error: %d\n", cuda_err);
return -1;
}
// Allocate device buffer
cuda_err = cudaMalloc(&(buffers->dev_buf), args.size);
if (cuda_err != cudaSuccess) {
fprintf(stderr, "PrepareBuf::cudaMalloc error: %d\n", cuda_err);
return -1;
}
// Initialize source buffer
if (args.copy_direction == "dtoh") {
cuda_err = cudaMemcpy(buffers->dev_buf, buffers->data_buf, args.size, cudaMemcpyDefault);
} else if (args.copy_direction == "htod") {
cuda_err = cudaMemcpy(buffers->host_buf, buffers->data_buf, args.size, cudaMemcpyDefault);
} else {
fprintf(stderr, "Unrecognized copy direction: %s\n", args.copy_direction.c_str());
return -1;
}
if (cuda_err != cudaSuccess) {
fprintf(stderr, "PrepareBuf::cudaMemcpy error: %d\n", cuda_err);
return -1;
}
return 0;
}
// Validate the result of data transfer.
int CheckBuf(const Args &args, Buffers *buffers) {
cudaError_t cuda_err = cudaSuccess;
// Copy result
if (args.copy_direction == "dtoh") {
cuda_err = cudaMemcpy(buffers->check_buf, buffers->host_buf, args.size, cudaMemcpyDefault);
} else if (args.copy_direction == "htod") {
cuda_err = cudaMemcpy(buffers->check_buf, buffers->dev_buf, args.size, cudaMemcpyDefault);
}
if (cuda_err != cudaSuccess) {
fprintf(stderr, "CheckBuf::cudaMemcpy error: %d\n", cuda_err);
return -1;
}
// Validate result
int memcmp_result = memcmp(buffers->data_buf, buffers->check_buf, args.size);
if (memcmp_result) {
fprintf(stderr, "Memory check failed\n");
return -1;
}
return 0;
}
// Destroy data buffers
int DestroyBuf(Buffers *buffers) {
int ret = 0;
cudaError_t cuda_err = cudaSuccess;
// Destroy original data buffer and check buffer
if (buffers->data_buf != nullptr)
free(buffers->data_buf);
if (buffers->check_buf != nullptr)
free(buffers->check_buf);
// Destroy device buffer
if (buffers->dev_buf != nullptr) {
cuda_err = cudaFree(buffers->dev_buf);
if (cuda_err != cudaSuccess) {
fprintf(stderr, "DestroyBuf::cudaFree error: %d\n", cuda_err);
ret = -1;
}
}
// Destroy host buffer
if (buffers->host_buf != nullptr) {
cuda_err = cudaHostUnregister(buffers->host_buf);
if (cuda_err != cudaSuccess) {
fprintf(stderr, "DestroyBuf::cudaHostUnregister error: %d\n", cuda_err);
ret = -1;
}
free(buffers->host_buf);
buffers->host_buf_dev_ptr = nullptr;
}
return ret;
}
// Unroll depth in SM copy kernel
#define NUM_LOOP_UNROLL 2
// Thread block size
#define NUM_THREADS_IN_BLOCK 128
// Fetch a ulong2 from source memory and write to register
// This kernel references the implementation in
// 1) NCCL:
// https://github.com/NVIDIA/nccl/blob/7e515921295adaab72adf56ea71a0fafb0ecb5f3/src/collectives/device/common_kernel.h#L483
// 2) RCCL:
// https://github.com/ROCmSoftwarePlatform/rccl/blob/5c8380ff5b5925cae4bce00b1879a5f930226e8d/src/collectives/device/common_kernel.h#L268
inline __device__ void FetchULong2(ulong2 &v, const ulong2 *p) {
#if defined(__HIP_PLATFORM_HCC__) || defined(__HCC__) || defined(__HIPCC__)
v.x = p->x;
v.y = p->y;
#else
asm volatile("ld.volatile.global.v2.u64 {%0,%1}, [%2];" : "=l"(v.x), "=l"(v.y) : "l"(p) : "memory");
#endif
}
// Store a ulong2 from register and write to target memory
// This kernel references the implementation in
// 1) NCCL:
// https://github.com/NVIDIA/nccl/blob/7e515921295adaab72adf56ea71a0fafb0ecb5f3/src/collectives/device/common_kernel.h#L486
// 2) RCCL:
// https://github.com/ROCmSoftwarePlatform/rccl/blob/5c8380ff5b5925cae4bce00b1879a5f930226e8d/src/collectives/device/common_kernel.h#L276
inline __device__ void StoreULong2(ulong2 *p, ulong2 &v) {
#if defined(__HIP_PLATFORM_HCC__) || defined(__HCC__) || defined(__HIPCC__)
p->x = v.x;
p->y = v.y;
#else
asm volatile("st.volatile.global.v2.u64 [%0], {%1,%2};" ::"l"(p), "l"(v.x), "l"(v.y) : "memory");
#endif
}
// Fetch data from source memory into register first, and then write them to target memory
// Stride set to thread block size to best utilize cache
__global__ void SMCopyKernel(ulong2 *tgt, const ulong2 *src) {
uint64_t index = blockIdx.x * blockDim.x * NUM_LOOP_UNROLL + threadIdx.x;
ulong2 val[NUM_LOOP_UNROLL];
#pragma unroll
for (uint64_t i = 0; i < NUM_LOOP_UNROLL; i++)
FetchULong2(val[i], src + index + i * blockDim.x);
#pragma unroll
for (uint64_t i = 0; i < NUM_LOOP_UNROLL; i++)
StoreULong2(tgt + index + i * blockDim.x, val[i]);
}
// Run SM copy kernel benchmark
int BenchSMCopyKernel(const Args &args, Buffers *buffers) {
cudaError_t cuda_err = cudaSuccess;
cudaStream_t stream;
uint8_t *src_buf = nullptr;
uint8_t *tgt_buf = nullptr;
// Determine source buffer and target buff
if (args.copy_direction == "dtoh") {
src_buf = buffers->dev_buf;
tgt_buf = buffers->host_buf_dev_ptr;
} else {
src_buf = buffers->host_buf_dev_ptr;
tgt_buf = buffers->dev_buf;
}
// Validate data size
uint64_t num_elements_in_thread_block = NUM_LOOP_UNROLL * NUM_THREADS_IN_BLOCK;
uint64_t num_bytes_in_thread_block = num_elements_in_thread_block * sizeof(ulong2);
if (args.size % num_bytes_in_thread_block) {
fprintf(stderr, "Data size should be multiple of %lu\n", num_bytes_in_thread_block);
return -1;
}
// Create stream to launch kernels
cuda_err = cudaStreamCreate(&stream);
if (cuda_err != cudaSuccess) {
fprintf(stderr, "BenchSMCopyKernel::cudaStreamCreate error: %d\n", cuda_err);
return -1;
}
// Launch kernels and collect running time
uint64_t num_thread_blocks = args.size / num_bytes_in_thread_block;
auto start = std::chrono::steady_clock::now();
for (int i = 0; i < args.num_loops; i++) {
SMCopyKernel<<<num_thread_blocks, NUM_THREADS_IN_BLOCK, 0, stream>>>(reinterpret_cast<ulong2 *>(tgt_buf),
reinterpret_cast<ulong2 *>(src_buf));
}
cuda_err = cudaStreamSynchronize(stream);
auto end = std::chrono::steady_clock::now();
if (cuda_err != cudaSuccess) {
fprintf(stderr, "BenchSMCopyKernel::cudaStreamSynchronize error: %d\n", cuda_err);
return -1;
}
// Destroy stream
cuda_err = cudaStreamDestroy(stream);
if (cuda_err != cudaSuccess) {
fprintf(stderr, "BenchSMCopyKernel::cudaStreamDestroy error: %d\n", cuda_err);
return -1;
}
// Calculate and display bandwidth if no problem
double time_in_sec = std::chrono::duration_cast<std::chrono::duration<double>>(end - start).count();
printf("Bandwidth (GB/s): %g\n", args.size * args.num_loops / time_in_sec / 1e9);
return 0;
}
int main(int argc, char **argv) {
int ret = 0;
int destroy_buf_ret = 0;
cudaError_t cuda_err = cudaSuccess;
Args args;
Buffers buffers;
if (argc != static_cast<int>(ArgIdx::kNumArgs)) {
PrintUsage();
return -1;
}
args.gpu_id = std::stoi(argv[static_cast<int>(ArgIdx::kGpuId)]);
args.copy_direction = argv[static_cast<int>(ArgIdx::kCopyDirection)];
args.size = std::stoul(argv[static_cast<int>(ArgIdx::kSize)]);
args.num_loops = std::stoul(argv[static_cast<int>(ArgIdx::kNumLoops)]);
// Set device context
cuda_err = cudaSetDevice(args.gpu_id);
if (cuda_err != cudaSuccess) {
fprintf(stderr, "cudaSetDevice error: %d\n", cuda_err);
goto destroy_buf;
}
// Prepare data buffers
ret = PrepareBuf(args, &buffers);
if (ret != 0) {
goto destroy_buf;
}
// Run benchmark
ret = BenchSMCopyKernel(args, &buffers);
if (ret != 0) {
goto destroy_buf;
}
// Validate data
ret = CheckBuf(args, &buffers);
destroy_buf:
// Destroy buffers
destroy_buf_ret = DestroyBuf(&buffers);
if (ret == 0) {
ret = destroy_buf_ret;
}
return ret;
} | code for sm_80
Function : _Z12SMCopyKernelP6ulong2PKS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0030*/ MOV R13, c[0x0][0x0] ; /* 0x00000000000d7a02 */
/* 0x000fe20000000f00 */
/*0040*/ HFMA2.MMA R15, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff0f7435 */
/* 0x000fc600000001ff */
/*0050*/ SHF.L.U32 R0, R13, 0x1, RZ ; /* 0x000000010d007819 */
/* 0x000fca00000006ff */
/*0060*/ IMAD R0, R0, UR4, R3 ; /* 0x0000000400007c24 */
/* 0x001fe2000f8e0203 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE.U32 R4, R0, R15, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fcc00078e000f */
/*0090*/ IMAD.WIDE.U32 R8, R13, 0x10, R4 ; /* 0x000000100d087825 */
/* 0x000fe400078e0004 */
/*00a0*/ LDG.E.128.STRONG.SYS R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1f5d00 */
/*00b0*/ LDG.E.128.STRONG.SYS R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee2000c1f5d00 */
/*00c0*/ IMAD.WIDE.U32 R2, R0, R15, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e000f */
/*00d0*/ IMAD.WIDE.U32 R12, R13, 0x10, R2 ; /* 0x000000100d0c7825 */
/* 0x000fe200078e0002 */
/*00e0*/ STG.E.128.STRONG.SYS [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x004fe8000c115d04 */
/*00f0*/ STG.E.128.STRONG.SYS [R12.64], R8 ; /* 0x000000080c007986 */
/* 0x008fe2000c115d04 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Copyright (c) Microsoft Corporation.
// Licensed under the MIT License.
// GPU SM copy benchmark tests dtoh/htod data transfer bandwidth initiated by GPU SM.
#include <chrono>
#include <cstdio>
#include <cstring>
#include <string>
#include <cuda.h>
#include <cuda_runtime.h>
// Argurment index used in argument parsing.
enum class ArgIdx { kGpuId = 1, kCopyDirection, kSize, kNumLoops, kNumArgs };
// Stored arguments for this program.
struct Args {
// ID of GPU used in this benchmark.
int gpu_id = 0;
// Data transfer direction, can be "dtoh" or "htod".
std::string copy_direction;
// Data buffer size used.
uint64_t size = 0;
// Number of loops in data transfer benchmark.
uint64_t num_loops = 0;
};
struct Buffers {
// Original data buffer.
uint8_t *data_buf = nullptr;
// Buffer to validate the correctness of data transfer.
uint8_t *check_buf = nullptr;
// Data buffer in host memory.
uint8_t *host_buf = nullptr;
// Device pointer of the data buffer in host memory.
uint8_t *host_buf_dev_ptr = nullptr;
// Data buffer in device memory
uint8_t *dev_buf = nullptr;
};
// Pring usage of this program.
void PrintUsage() {
printf("Usage: gpu_sm_copy "
"<gpu-id> "
"<copy-direction: dtoh|htod> "
"<size> "
"<num_loops>\n");
}
// Prepare data buffers to be used.
int PrepareBuf(const Args &args, Buffers *buffers) {
cudaError_t cuda_err = cudaSuccess;
// Generate data to copy
buffers->data_buf = static_cast<uint8_t *>(malloc(args.size));
for (int i = 0; i < args.size; i++) {
buffers->data_buf[i] = static_cast<uint8_t>(i % 256);
}
// Reset check buffer
buffers->check_buf = static_cast<uint8_t *>(malloc(args.size));
memset(buffers->check_buf, 0, args.size);
// Allocate host buffer
buffers->host_buf = static_cast<uint8_t *>(malloc(args.size));
cuda_err = cudaHostRegister(buffers->host_buf, args.size, cudaHostRegisterMapped);
if (cuda_err != cudaSuccess) {
fprintf(stderr, "PrepareBuf::cudaHostRegister error: %d\n", cuda_err);
return -1;
}
cuda_err = cudaHostGetDevicePointer((void **)(&(buffers->host_buf_dev_ptr)), buffers->host_buf, 0);
if (cuda_err != cudaSuccess) {
fprintf(stderr, "PrepareBuf::cudaHostGetDevicePointer error: %d\n", cuda_err);
return -1;
}
// Allocate device buffer
cuda_err = cudaMalloc(&(buffers->dev_buf), args.size);
if (cuda_err != cudaSuccess) {
fprintf(stderr, "PrepareBuf::cudaMalloc error: %d\n", cuda_err);
return -1;
}
// Initialize source buffer
if (args.copy_direction == "dtoh") {
cuda_err = cudaMemcpy(buffers->dev_buf, buffers->data_buf, args.size, cudaMemcpyDefault);
} else if (args.copy_direction == "htod") {
cuda_err = cudaMemcpy(buffers->host_buf, buffers->data_buf, args.size, cudaMemcpyDefault);
} else {
fprintf(stderr, "Unrecognized copy direction: %s\n", args.copy_direction.c_str());
return -1;
}
if (cuda_err != cudaSuccess) {
fprintf(stderr, "PrepareBuf::cudaMemcpy error: %d\n", cuda_err);
return -1;
}
return 0;
}
// Validate the result of data transfer.
int CheckBuf(const Args &args, Buffers *buffers) {
cudaError_t cuda_err = cudaSuccess;
// Copy result
if (args.copy_direction == "dtoh") {
cuda_err = cudaMemcpy(buffers->check_buf, buffers->host_buf, args.size, cudaMemcpyDefault);
} else if (args.copy_direction == "htod") {
cuda_err = cudaMemcpy(buffers->check_buf, buffers->dev_buf, args.size, cudaMemcpyDefault);
}
if (cuda_err != cudaSuccess) {
fprintf(stderr, "CheckBuf::cudaMemcpy error: %d\n", cuda_err);
return -1;
}
// Validate result
int memcmp_result = memcmp(buffers->data_buf, buffers->check_buf, args.size);
if (memcmp_result) {
fprintf(stderr, "Memory check failed\n");
return -1;
}
return 0;
}
// Destroy data buffers
int DestroyBuf(Buffers *buffers) {
int ret = 0;
cudaError_t cuda_err = cudaSuccess;
// Destroy original data buffer and check buffer
if (buffers->data_buf != nullptr)
free(buffers->data_buf);
if (buffers->check_buf != nullptr)
free(buffers->check_buf);
// Destroy device buffer
if (buffers->dev_buf != nullptr) {
cuda_err = cudaFree(buffers->dev_buf);
if (cuda_err != cudaSuccess) {
fprintf(stderr, "DestroyBuf::cudaFree error: %d\n", cuda_err);
ret = -1;
}
}
// Destroy host buffer
if (buffers->host_buf != nullptr) {
cuda_err = cudaHostUnregister(buffers->host_buf);
if (cuda_err != cudaSuccess) {
fprintf(stderr, "DestroyBuf::cudaHostUnregister error: %d\n", cuda_err);
ret = -1;
}
free(buffers->host_buf);
buffers->host_buf_dev_ptr = nullptr;
}
return ret;
}
// Unroll depth in SM copy kernel
#define NUM_LOOP_UNROLL 2
// Thread block size
#define NUM_THREADS_IN_BLOCK 128
// Fetch a ulong2 from source memory and write to register
// This kernel references the implementation in
// 1) NCCL:
// https://github.com/NVIDIA/nccl/blob/7e515921295adaab72adf56ea71a0fafb0ecb5f3/src/collectives/device/common_kernel.h#L483
// 2) RCCL:
// https://github.com/ROCmSoftwarePlatform/rccl/blob/5c8380ff5b5925cae4bce00b1879a5f930226e8d/src/collectives/device/common_kernel.h#L268
inline __device__ void FetchULong2(ulong2 &v, const ulong2 *p) {
#if defined(__HIP_PLATFORM_HCC__) || defined(__HCC__) || defined(__HIPCC__)
v.x = p->x;
v.y = p->y;
#else
asm volatile("ld.volatile.global.v2.u64 {%0,%1}, [%2];" : "=l"(v.x), "=l"(v.y) : "l"(p) : "memory");
#endif
}
// Store a ulong2 from register and write to target memory
// This kernel references the implementation in
// 1) NCCL:
// https://github.com/NVIDIA/nccl/blob/7e515921295adaab72adf56ea71a0fafb0ecb5f3/src/collectives/device/common_kernel.h#L486
// 2) RCCL:
// https://github.com/ROCmSoftwarePlatform/rccl/blob/5c8380ff5b5925cae4bce00b1879a5f930226e8d/src/collectives/device/common_kernel.h#L276
inline __device__ void StoreULong2(ulong2 *p, ulong2 &v) {
#if defined(__HIP_PLATFORM_HCC__) || defined(__HCC__) || defined(__HIPCC__)
p->x = v.x;
p->y = v.y;
#else
asm volatile("st.volatile.global.v2.u64 [%0], {%1,%2};" ::"l"(p), "l"(v.x), "l"(v.y) : "memory");
#endif
}
// Fetch data from source memory into register first, and then write them to target memory
// Stride set to thread block size to best utilize cache
__global__ void SMCopyKernel(ulong2 *tgt, const ulong2 *src) {
uint64_t index = blockIdx.x * blockDim.x * NUM_LOOP_UNROLL + threadIdx.x;
ulong2 val[NUM_LOOP_UNROLL];
#pragma unroll
for (uint64_t i = 0; i < NUM_LOOP_UNROLL; i++)
FetchULong2(val[i], src + index + i * blockDim.x);
#pragma unroll
for (uint64_t i = 0; i < NUM_LOOP_UNROLL; i++)
StoreULong2(tgt + index + i * blockDim.x, val[i]);
}
// Run SM copy kernel benchmark
int BenchSMCopyKernel(const Args &args, Buffers *buffers) {
cudaError_t cuda_err = cudaSuccess;
cudaStream_t stream;
uint8_t *src_buf = nullptr;
uint8_t *tgt_buf = nullptr;
// Determine source buffer and target buff
if (args.copy_direction == "dtoh") {
src_buf = buffers->dev_buf;
tgt_buf = buffers->host_buf_dev_ptr;
} else {
src_buf = buffers->host_buf_dev_ptr;
tgt_buf = buffers->dev_buf;
}
// Validate data size
uint64_t num_elements_in_thread_block = NUM_LOOP_UNROLL * NUM_THREADS_IN_BLOCK;
uint64_t num_bytes_in_thread_block = num_elements_in_thread_block * sizeof(ulong2);
if (args.size % num_bytes_in_thread_block) {
fprintf(stderr, "Data size should be multiple of %lu\n", num_bytes_in_thread_block);
return -1;
}
// Create stream to launch kernels
cuda_err = cudaStreamCreate(&stream);
if (cuda_err != cudaSuccess) {
fprintf(stderr, "BenchSMCopyKernel::cudaStreamCreate error: %d\n", cuda_err);
return -1;
}
// Launch kernels and collect running time
uint64_t num_thread_blocks = args.size / num_bytes_in_thread_block;
auto start = std::chrono::steady_clock::now();
for (int i = 0; i < args.num_loops; i++) {
SMCopyKernel<<<num_thread_blocks, NUM_THREADS_IN_BLOCK, 0, stream>>>(reinterpret_cast<ulong2 *>(tgt_buf),
reinterpret_cast<ulong2 *>(src_buf));
}
cuda_err = cudaStreamSynchronize(stream);
auto end = std::chrono::steady_clock::now();
if (cuda_err != cudaSuccess) {
fprintf(stderr, "BenchSMCopyKernel::cudaStreamSynchronize error: %d\n", cuda_err);
return -1;
}
// Destroy stream
cuda_err = cudaStreamDestroy(stream);
if (cuda_err != cudaSuccess) {
fprintf(stderr, "BenchSMCopyKernel::cudaStreamDestroy error: %d\n", cuda_err);
return -1;
}
// Calculate and display bandwidth if no problem
double time_in_sec = std::chrono::duration_cast<std::chrono::duration<double>>(end - start).count();
printf("Bandwidth (GB/s): %g\n", args.size * args.num_loops / time_in_sec / 1e9);
return 0;
}
int main(int argc, char **argv) {
int ret = 0;
int destroy_buf_ret = 0;
cudaError_t cuda_err = cudaSuccess;
Args args;
Buffers buffers;
if (argc != static_cast<int>(ArgIdx::kNumArgs)) {
PrintUsage();
return -1;
}
args.gpu_id = std::stoi(argv[static_cast<int>(ArgIdx::kGpuId)]);
args.copy_direction = argv[static_cast<int>(ArgIdx::kCopyDirection)];
args.size = std::stoul(argv[static_cast<int>(ArgIdx::kSize)]);
args.num_loops = std::stoul(argv[static_cast<int>(ArgIdx::kNumLoops)]);
// Set device context
cuda_err = cudaSetDevice(args.gpu_id);
if (cuda_err != cudaSuccess) {
fprintf(stderr, "cudaSetDevice error: %d\n", cuda_err);
goto destroy_buf;
}
// Prepare data buffers
ret = PrepareBuf(args, &buffers);
if (ret != 0) {
goto destroy_buf;
}
// Run benchmark
ret = BenchSMCopyKernel(args, &buffers);
if (ret != 0) {
goto destroy_buf;
}
// Validate data
ret = CheckBuf(args, &buffers);
destroy_buf:
// Destroy buffers
destroy_buf_ret = DestroyBuf(&buffers);
if (ret == 0) {
ret = destroy_buf_ret;
}
return ret;
} | .file "tmpxft_0013932b_00000000-6_gpu_sm_copy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3178:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3178:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Usage: gpu_sm_copy <gpu-id> <copy-direction: dtoh|htod> <size> <num_loops>\n"
.text
.globl _Z10PrintUsagev
.type _Z10PrintUsagev, @function
_Z10PrintUsagev:
.LFB3155:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3155:
.size _Z10PrintUsagev, .-_Z10PrintUsagev
.section .rodata.str1.8
.align 8
.LC1:
.string "PrepareBuf::cudaHostRegister error: %d\n"
.align 8
.LC2:
.string "PrepareBuf::cudaHostGetDevicePointer error: %d\n"
.align 8
.LC3:
.string "PrepareBuf::cudaMalloc error: %d\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "dtoh"
.LC5:
.string "htod"
.section .rodata.str1.8
.align 8
.LC6:
.string "Unrecognized copy direction: %s\n"
.align 8
.LC7:
.string "PrepareBuf::cudaMemcpy error: %d\n"
.text
.globl _Z10PrepareBufRK4ArgsP7Buffers
.type _Z10PrepareBufRK4ArgsP7Buffers, @function
_Z10PrepareBufRK4ArgsP7Buffers:
.LFB3156:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movq %rsi, %rbx
movq 40(%rdi), %rdi
call malloc@PLT
movq %rax, (%rbx)
movq 40(%rbp), %r12
testq %r12, %r12
je .L6
movl $0, %eax
.L7:
movq (%rbx), %rsi
movl %eax, %ecx
sarl $31, %ecx
shrl $24, %ecx
leal (%rcx,%rax), %edx
movzbl %dl, %edx
subl %ecx, %edx
movb %dl, (%rsi,%rax)
addq $1, %rax
movq 40(%rbp), %r12
cmpq %r12, %rax
jb .L7
.L6:
movq %r12, %rdi
call malloc@PLT
movq %rax, %rdi
movq %rax, 8(%rbx)
movq 40(%rbp), %r13
movq %r12, %rcx
movq %r13, %rdx
movl $0, %esi
call __memset_chk@PLT
movq %r13, %rdi
call malloc@PLT
movq %rax, %rdi
movq %rax, 16(%rbx)
movq 40(%rbp), %rsi
movl $2, %edx
call cudaHostRegister@PLT
testl %eax, %eax
jne .L18
movq 16(%rbx), %rsi
leaq 24(%rbx), %rdi
movl $0, %edx
call cudaHostGetDevicePointer@PLT
testl %eax, %eax
jne .L19
movq 40(%rbp), %rsi
leaq 32(%rbx), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L20
cmpq $4, 16(%rbp)
je .L21
.L12:
movq 8(%rbp), %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %eax
jmp .L5
.L18:
movl %eax, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %eax
jmp .L5
.L19:
movl %eax, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %eax
jmp .L5
.L20:
movl %eax, %ecx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %eax
jmp .L5
.L21:
movq 8(%rbp), %r12
movl $4, %edx
leaq .LC4(%rip), %rsi
movq %r12, %rdi
call memcmp@PLT
testl %eax, %eax
jne .L13
movq 40(%rbp), %rdx
movq (%rbx), %rsi
movq 32(%rbx), %rdi
movl $4, %ecx
call cudaMemcpy@PLT
jmp .L14
.L13:
movl $4, %edx
leaq .LC5(%rip), %rsi
movq %r12, %rdi
call memcmp@PLT
testl %eax, %eax
jne .L12
movq 40(%rbp), %rdx
movq (%rbx), %rsi
movq 16(%rbx), %rdi
movl $4, %ecx
call cudaMemcpy@PLT
.L14:
testl %eax, %eax
jne .L22
movl $0, %eax
.L5:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movl %eax, %ecx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %eax
jmp .L5
.cfi_endproc
.LFE3156:
.size _Z10PrepareBufRK4ArgsP7Buffers, .-_Z10PrepareBufRK4ArgsP7Buffers
.section .rodata.str1.8
.align 8
.LC8:
.string "CheckBuf::cudaMemcpy error: %d\n"
.section .rodata.str1.1
.LC9:
.string "Memory check failed\n"
.text
.globl _Z8CheckBufRK4ArgsP7Buffers
.type _Z8CheckBufRK4ArgsP7Buffers, @function
_Z8CheckBufRK4ArgsP7Buffers:
.LFB3157:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbp
movq %rsi, %rbx
cmpq $4, 16(%rdi)
je .L29
.L24:
movq 40(%rbp), %rdx
movq 8(%rbx), %rsi
movq (%rbx), %rdi
call memcmp@PLT
movl %eax, %edx
testl %eax, %eax
jne .L30
.L23:
movl %edx, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movq 8(%rdi), %r12
movl $4, %edx
leaq .LC4(%rip), %rsi
movq %r12, %rdi
call memcmp@PLT
testl %eax, %eax
jne .L25
movq 40(%rbp), %rdx
movq 16(%rbx), %rsi
movq 8(%rbx), %rdi
movl $4, %ecx
call cudaMemcpy@PLT
.L26:
testl %eax, %eax
je .L24
movl %eax, %ecx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edx
jmp .L23
.L25:
movl $4, %edx
leaq .LC5(%rip), %rsi
movq %r12, %rdi
call memcmp@PLT
testl %eax, %eax
jne .L24
movq 40(%rbp), %rdx
movq 32(%rbx), %rsi
movq 8(%rbx), %rdi
movl $4, %ecx
call cudaMemcpy@PLT
jmp .L26
.L30:
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edx
jmp .L23
.cfi_endproc
.LFE3157:
.size _Z8CheckBufRK4ArgsP7Buffers, .-_Z8CheckBufRK4ArgsP7Buffers
.section .rodata.str1.8
.align 8
.LC10:
.string "DestroyBuf::cudaFree error: %d\n"
.align 8
.LC11:
.string "DestroyBuf::cudaHostUnregister error: %d\n"
.text
.globl _Z10DestroyBufP7Buffers
.type _Z10DestroyBufP7Buffers, @function
_Z10DestroyBufP7Buffers:
.LFB3158:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movq (%rdi), %rdi
testq %rdi, %rdi
je .L32
call free@PLT
.L32:
movq 8(%rbx), %rdi
testq %rdi, %rdi
je .L33
call free@PLT
.L33:
movq 32(%rbx), %rdi
movl $0, %ebp
testq %rdi, %rdi
je .L34
call cudaFree@PLT
testl %eax, %eax
jne .L40
.L34:
movq 16(%rbx), %rdi
testq %rdi, %rdi
je .L31
call cudaHostUnregister@PLT
testl %eax, %eax
jne .L41
.L36:
movq 16(%rbx), %rdi
call free@PLT
movq $0, 24(%rbx)
.L31:
movl %ebp, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
movl %eax, %ecx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %ebp
jmp .L34
.L41:
movl %eax, %ecx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %ebp
jmp .L36
.cfi_endproc
.LFE3158:
.size _Z10DestroyBufP7Buffers, .-_Z10DestroyBufP7Buffers
.globl _Z42__device_stub__Z12SMCopyKernelP6ulong2PKS_P6ulong2PKS_
.type _Z42__device_stub__Z12SMCopyKernelP6ulong2PKS_P6ulong2PKS_, @function
_Z42__device_stub__Z12SMCopyKernelP6ulong2PKS_P6ulong2PKS_:
.LFB3200:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L46
.L42:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L47
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12SMCopyKernelP6ulong2PKS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L42
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3200:
.size _Z42__device_stub__Z12SMCopyKernelP6ulong2PKS_P6ulong2PKS_, .-_Z42__device_stub__Z12SMCopyKernelP6ulong2PKS_P6ulong2PKS_
.globl _Z12SMCopyKernelP6ulong2PKS_
.type _Z12SMCopyKernelP6ulong2PKS_, @function
_Z12SMCopyKernelP6ulong2PKS_:
.LFB3201:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z12SMCopyKernelP6ulong2PKS_P6ulong2PKS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3201:
.size _Z12SMCopyKernelP6ulong2PKS_, .-_Z12SMCopyKernelP6ulong2PKS_
.section .rodata.str1.8
.align 8
.LC12:
.string "Data size should be multiple of %lu\n"
.align 8
.LC13:
.string "BenchSMCopyKernel::cudaStreamCreate error: %d\n"
.align 8
.LC14:
.string "BenchSMCopyKernel::cudaStreamSynchronize error: %d\n"
.align 8
.LC15:
.string "BenchSMCopyKernel::cudaStreamDestroy error: %d\n"
.section .rodata.str1.1
.LC17:
.string "Bandwidth (GB/s): %g\n"
.text
.globl _Z17BenchSMCopyKernelRK4ArgsP7Buffers
.type _Z17BenchSMCopyKernelRK4ArgsP7Buffers, @function
_Z17BenchSMCopyKernelRK4ArgsP7Buffers:
.LFB3161:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %rbp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
cmpq $4, 16(%rdi)
je .L66
.L51:
movq 24(%rbx), %r14
movq 32(%rbx), %r15
jmp .L52
.L66:
movq 8(%rdi), %rdi
movl $4, %edx
leaq .LC4(%rip), %rsi
call memcmp@PLT
testl %eax, %eax
jne .L51
movq 32(%rbx), %r14
movq 24(%rbx), %r15
.L52:
movq 40(%rbp), %rbx
andl $4095, %ebx
jne .L67
leaq 8(%rsp), %rdi
call cudaStreamCreate@PLT
testl %eax, %eax
jne .L68
movq 40(%rbp), %r12
shrq $12, %r12
call _ZNSt6chrono3_V212steady_clock3nowEv@PLT
movq %rax, %r13
cmpq $0, 48(%rbp)
jne .L58
.L56:
movq 8(%rsp), %rdi
call cudaStreamSynchronize@PLT
movl %eax, %r12d
call _ZNSt6chrono3_V212steady_clock3nowEv@PLT
movq %rax, %rbx
testl %r12d, %r12d
jne .L69
movq 8(%rsp), %rdi
call cudaStreamDestroy@PLT
testl %eax, %eax
jne .L70
movq 40(%rbp), %rax
imulq 48(%rbp), %rax
testq %rax, %rax
js .L61
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
.L62:
subq %r13, %rbx
pxor %xmm1, %xmm1
cvtsi2sdq %rbx, %xmm1
movsd .LC16(%rip), %xmm2
divsd %xmm2, %xmm1
divsd %xmm1, %xmm0
divsd %xmm2, %xmm0
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %eax
.L50:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L71
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L67:
.cfi_restore_state
movl $4096, %ecx
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %eax
jmp .L50
.L68:
movl %eax, %ecx
leaq .LC13(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %eax
jmp .L50
.L57:
addq $1, %rbx
cmpq 48(%rbp), %rbx
jnb .L56
.L58:
movl $128, 28(%rsp)
movl $1, 32(%rsp)
movl %r12d, 16(%rsp)
movl $1, 20(%rsp)
movq 8(%rsp), %r9
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L57
movq %r14, %rsi
movq %r15, %rdi
call _Z42__device_stub__Z12SMCopyKernelP6ulong2PKS_P6ulong2PKS_
jmp .L57
.L69:
movl %r12d, %ecx
leaq .LC14(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %eax
jmp .L50
.L70:
movl %eax, %ecx
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %eax
jmp .L50
.L61:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
jmp .L62
.L71:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3161:
.size _Z17BenchSMCopyKernelRK4ArgsP7Buffers, .-_Z17BenchSMCopyKernelRK4ArgsP7Buffers
.section .rodata.str1.1
.LC18:
.string "_Z12SMCopyKernelP6ulong2PKS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3203:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z12SMCopyKernelP6ulong2PKS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3203:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZN9__gnu_cxx6__stoaImmcJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"axG",@progbits,_ZN9__gnu_cxx6__stoaImmcJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat
.weak _ZN9__gnu_cxx6__stoaImmcJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.type _ZN9__gnu_cxx6__stoaImmcJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_, @function
_ZN9__gnu_cxx6__stoaImmcJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_:
.LFB3323:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3323
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r13
movq %rsi, 8(%rsp)
movq %rdx, %rbp
movq %rcx, %r12
movl %r8d, %r14d
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
call __errno_location@PLT
movq %rax, %rbx
movl (%rax), %r15d
movl $0, (%rax)
leaq 16(%rsp), %rsi
movl %r14d, %edx
movq %rbp, %rdi
.LEHB0:
call *%r13
movq 16(%rsp), %rdx
cmpq %rbp, %rdx
je .L87
cmpl $34, (%rbx)
je .L88
testq %r12, %r12
je .L79
subq %rbp, %rdx
movq %rdx, (%r12)
.L79:
cmpl $0, (%rbx)
jne .L74
movl %r15d, (%rbx)
.L74:
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L89
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L87:
.cfi_restore_state
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L90
movq 8(%rsp), %rdi
call _ZSt24__throw_invalid_argumentPKc@PLT
.L85:
endbr64
movq %rax, %rdi
cmpl $0, (%rbx)
jne .L82
movl %r15d, (%rbx)
.L82:
movq 24(%rsp), %rax
subq %fs:40, %rax
je .L83
call __stack_chk_fail@PLT
.L90:
call __stack_chk_fail@PLT
.L88:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L91
movq 8(%rsp), %rdi
call _ZSt20__throw_out_of_rangePKc@PLT
.LEHE0:
.L91:
call __stack_chk_fail@PLT
.L83:
.LEHB1:
call _Unwind_Resume@PLT
.LEHE1:
.L89:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3323:
.globl __gxx_personality_v0
.section .gcc_except_table._ZN9__gnu_cxx6__stoaImmcJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"aG",@progbits,_ZN9__gnu_cxx6__stoaImmcJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat
.LLSDA3323:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3323-.LLSDACSB3323
.LLSDACSB3323:
.uleb128 .LEHB0-.LFB3323
.uleb128 .LEHE0-.LEHB0
.uleb128 .L85-.LFB3323
.uleb128 0
.uleb128 .LEHB1-.LFB3323
.uleb128 .LEHE1-.LEHB1
.uleb128 0
.uleb128 0
.LLSDACSE3323:
.section .text._ZN9__gnu_cxx6__stoaImmcJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,"axG",@progbits,_ZN9__gnu_cxx6__stoaImmcJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_,comdat
.size _ZN9__gnu_cxx6__stoaImmcJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_, .-_ZN9__gnu_cxx6__stoaImmcJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.section .rodata._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.str1.8,"aMS",@progbits,1
.align 8
.LC19:
.string "basic_string: construction from null is not valid"
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC5IS3_EEPKcRKS3_,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_:
.LFB3535:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 16(%rdi), %r12
movq %r12, (%rdi)
testq %rsi, %rsi
je .L101
movq %rdi, %rbx
movq %rsi, %r13
movq %rsi, %rdi
call strlen@PLT
movq %rax, %rbp
movq %rax, (%rsp)
cmpq $15, %rax
ja .L102
cmpq $1, %rax
jne .L97
movzbl 0(%r13), %eax
movb %al, 16(%rbx)
.L98:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L103
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L101:
.cfi_restore_state
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L104
leaq .LC19(%rip), %rdi
call _ZSt19__throw_logic_errorPKc@PLT
.L104:
call __stack_chk_fail@PLT
.L102:
movq %rsp, %rsi
movl $0, %edx
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %r12
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L96:
movq %rbp, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memcpy@PLT
jmp .L98
.L97:
testq %rax, %rax
je .L98
jmp .L96
.L103:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3535:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.set _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.section .rodata.str1.1
.LC20:
.string "stoi"
.LC21:
.string "stoul"
.LC22:
.string "cudaSetDevice error: %d\n"
.text
.globl main
.type main, @function
main:
.LFB3164:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3164
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $168, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movl $0, 96(%rsp)
leaq 120(%rsp), %rax
movq %rax, 104(%rsp)
movq $0, 112(%rsp)
movb $0, 120(%rsp)
movq $0, 136(%rsp)
movq $0, 144(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
movq $0, 32(%rsp)
movq $0, 40(%rsp)
movq $0, 48(%rsp)
cmpl $5, %edi
jne .L135
movq %rsi, %rbx
leaq 7(%rsp), %rdx
movq 8(%rsi), %rsi
leaq 64(%rsp), %rdi
.LEHB2:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
jmp .L136
.L135:
call _Z10PrintUsagev
jmp .L137
.L136:
movq 64(%rsp), %r13
call __errno_location@PLT
movq %rax, %rbp
movl (%rax), %r12d
movl $0, (%rax)
leaq 8(%rsp), %rsi
movl $10, %edx
movq %r13, %rdi
call __isoc23_strtol@PLT
cmpq 8(%rsp), %r13
je .L138
movl 0(%rbp), %ecx
cmpl $34, %ecx
je .L110
movl $2147483648, %edx
addq %rax, %rdx
shrq $32, %rdx
jne .L110
testl %ecx, %ecx
jne .L113
movl %r12d, 0(%rbp)
.L113:
movl %eax, 96(%rsp)
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 16(%rbx), %rsi
leaq 104(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6assignEPKc@PLT
.LEHE2:
jmp .L139
.L138:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L140
leaq .LC20(%rip), %rdi
.LEHB3:
call _ZSt24__throw_invalid_argumentPKc@PLT
.L140:
call __stack_chk_fail@PLT
.L110:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L141
leaq .LC20(%rip), %rdi
call _ZSt20__throw_out_of_rangePKc@PLT
.LEHE3:
.L129:
endbr64
movq %rax, %rbx
cmpl $0, 0(%rbp)
jne .L116
movl %r12d, 0(%rbp)
.L116:
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L117:
leaq 104(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
je .L122
call __stack_chk_fail@PLT
.L141:
call __stack_chk_fail@PLT
.L139:
leaq 8(%rsp), %rdx
movq 24(%rbx), %rsi
leaq 64(%rsp), %rdi
.LEHB4:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE4:
movl $10, %r8d
movl $0, %ecx
movq 64(%rsp), %rdx
leaq .LC21(%rip), %rsi
movq __isoc23_strtoul@GOTPCREL(%rip), %rdi
.LEHB5:
call _ZN9__gnu_cxx6__stoaImmcJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.LEHE5:
movq %rax, 136(%rsp)
leaq 64(%rsp), %rbp
movq %rbp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 8(%rsp), %rdx
movq 32(%rbx), %rsi
movq %rbp, %rdi
.LEHB6:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE6:
movl $10, %r8d
movl $0, %ecx
movq 64(%rsp), %rdx
leaq .LC21(%rip), %rsi
movq __isoc23_strtoul@GOTPCREL(%rip), %rdi
.LEHB7:
call _ZN9__gnu_cxx6__stoaImmcJiEEET0_PFT_PKT1_PPS3_DpT2_EPKcS5_PmS9_
.LEHE7:
movq %rax, 144(%rsp)
movq %rbp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl 96(%rsp), %edi
.LEHB8:
call cudaSetDevice@PLT
testl %eax, %eax
jne .L142
leaq 16(%rsp), %rsi
leaq 96(%rsp), %rdi
call _Z10PrepareBufRK4ArgsP7Buffers
jmp .L143
.L142:
movl %eax, %ecx
leaq .LC22(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L144
.L143:
movl %eax, %ebx
testl %eax, %eax
jne .L119
leaq 16(%rsp), %rsi
leaq 96(%rsp), %rdi
call _Z17BenchSMCopyKernelRK4ArgsP7Buffers
movl %eax, %ebx
testl %eax, %eax
jne .L119
leaq 16(%rsp), %rsi
leaq 96(%rsp), %rdi
call _Z8CheckBufRK4ArgsP7Buffers
movl %eax, %ebx
jmp .L119
.L144:
movl $0, %ebx
.L119:
leaq 16(%rsp), %rdi
call _Z10DestroyBufP7Buffers
.LEHE8:
testl %ebx, %ebx
cmove %eax, %ebx
.L107:
leaq 104(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L145
movl %ebx, %eax
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L137:
.cfi_restore_state
movl $-1, %ebx
jmp .L107
.L127:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
jmp .L117
.L128:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
jmp .L117
.L126:
endbr64
movq %rax, %rbx
jmp .L117
.L122:
movq %rbx, %rdi
.LEHB9:
call _Unwind_Resume@PLT
.LEHE9:
.L145:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3164:
.section .gcc_except_table,"a",@progbits
.LLSDA3164:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3164-.LLSDACSB3164
.LLSDACSB3164:
.uleb128 .LEHB2-.LFB3164
.uleb128 .LEHE2-.LEHB2
.uleb128 .L126-.LFB3164
.uleb128 0
.uleb128 .LEHB3-.LFB3164
.uleb128 .LEHE3-.LEHB3
.uleb128 .L129-.LFB3164
.uleb128 0
.uleb128 .LEHB4-.LFB3164
.uleb128 .LEHE4-.LEHB4
.uleb128 .L126-.LFB3164
.uleb128 0
.uleb128 .LEHB5-.LFB3164
.uleb128 .LEHE5-.LEHB5
.uleb128 .L127-.LFB3164
.uleb128 0
.uleb128 .LEHB6-.LFB3164
.uleb128 .LEHE6-.LEHB6
.uleb128 .L126-.LFB3164
.uleb128 0
.uleb128 .LEHB7-.LFB3164
.uleb128 .LEHE7-.LEHB7
.uleb128 .L128-.LFB3164
.uleb128 0
.uleb128 .LEHB8-.LFB3164
.uleb128 .LEHE8-.LEHB8
.uleb128 .L126-.LFB3164
.uleb128 0
.uleb128 .LEHB9-.LFB3164
.uleb128 .LEHE9-.LEHB9
.uleb128 0
.uleb128 0
.LLSDACSE3164:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC16:
.long 0
.long 1104006501
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Copyright (c) Microsoft Corporation.
// Licensed under the MIT License.
// GPU SM copy benchmark tests dtoh/htod data transfer bandwidth initiated by GPU SM.
#include <chrono>
#include <cstdio>
#include <cstring>
#include <string>
#include <cuda.h>
#include <cuda_runtime.h>
// Argurment index used in argument parsing.
enum class ArgIdx { kGpuId = 1, kCopyDirection, kSize, kNumLoops, kNumArgs };
// Stored arguments for this program.
struct Args {
// ID of GPU used in this benchmark.
int gpu_id = 0;
// Data transfer direction, can be "dtoh" or "htod".
std::string copy_direction;
// Data buffer size used.
uint64_t size = 0;
// Number of loops in data transfer benchmark.
uint64_t num_loops = 0;
};
struct Buffers {
// Original data buffer.
uint8_t *data_buf = nullptr;
// Buffer to validate the correctness of data transfer.
uint8_t *check_buf = nullptr;
// Data buffer in host memory.
uint8_t *host_buf = nullptr;
// Device pointer of the data buffer in host memory.
uint8_t *host_buf_dev_ptr = nullptr;
// Data buffer in device memory
uint8_t *dev_buf = nullptr;
};
// Pring usage of this program.
void PrintUsage() {
printf("Usage: gpu_sm_copy "
"<gpu-id> "
"<copy-direction: dtoh|htod> "
"<size> "
"<num_loops>\n");
}
// Prepare data buffers to be used.
int PrepareBuf(const Args &args, Buffers *buffers) {
cudaError_t cuda_err = cudaSuccess;
// Generate data to copy
buffers->data_buf = static_cast<uint8_t *>(malloc(args.size));
for (int i = 0; i < args.size; i++) {
buffers->data_buf[i] = static_cast<uint8_t>(i % 256);
}
// Reset check buffer
buffers->check_buf = static_cast<uint8_t *>(malloc(args.size));
memset(buffers->check_buf, 0, args.size);
// Allocate host buffer
buffers->host_buf = static_cast<uint8_t *>(malloc(args.size));
cuda_err = cudaHostRegister(buffers->host_buf, args.size, cudaHostRegisterMapped);
if (cuda_err != cudaSuccess) {
fprintf(stderr, "PrepareBuf::cudaHostRegister error: %d\n", cuda_err);
return -1;
}
cuda_err = cudaHostGetDevicePointer((void **)(&(buffers->host_buf_dev_ptr)), buffers->host_buf, 0);
if (cuda_err != cudaSuccess) {
fprintf(stderr, "PrepareBuf::cudaHostGetDevicePointer error: %d\n", cuda_err);
return -1;
}
// Allocate device buffer
cuda_err = cudaMalloc(&(buffers->dev_buf), args.size);
if (cuda_err != cudaSuccess) {
fprintf(stderr, "PrepareBuf::cudaMalloc error: %d\n", cuda_err);
return -1;
}
// Initialize source buffer
if (args.copy_direction == "dtoh") {
cuda_err = cudaMemcpy(buffers->dev_buf, buffers->data_buf, args.size, cudaMemcpyDefault);
} else if (args.copy_direction == "htod") {
cuda_err = cudaMemcpy(buffers->host_buf, buffers->data_buf, args.size, cudaMemcpyDefault);
} else {
fprintf(stderr, "Unrecognized copy direction: %s\n", args.copy_direction.c_str());
return -1;
}
if (cuda_err != cudaSuccess) {
fprintf(stderr, "PrepareBuf::cudaMemcpy error: %d\n", cuda_err);
return -1;
}
return 0;
}
// Validate the result of data transfer.
int CheckBuf(const Args &args, Buffers *buffers) {
cudaError_t cuda_err = cudaSuccess;
// Copy result
if (args.copy_direction == "dtoh") {
cuda_err = cudaMemcpy(buffers->check_buf, buffers->host_buf, args.size, cudaMemcpyDefault);
} else if (args.copy_direction == "htod") {
cuda_err = cudaMemcpy(buffers->check_buf, buffers->dev_buf, args.size, cudaMemcpyDefault);
}
if (cuda_err != cudaSuccess) {
fprintf(stderr, "CheckBuf::cudaMemcpy error: %d\n", cuda_err);
return -1;
}
// Validate result
int memcmp_result = memcmp(buffers->data_buf, buffers->check_buf, args.size);
if (memcmp_result) {
fprintf(stderr, "Memory check failed\n");
return -1;
}
return 0;
}
// Destroy data buffers
int DestroyBuf(Buffers *buffers) {
int ret = 0;
cudaError_t cuda_err = cudaSuccess;
// Destroy original data buffer and check buffer
if (buffers->data_buf != nullptr)
free(buffers->data_buf);
if (buffers->check_buf != nullptr)
free(buffers->check_buf);
// Destroy device buffer
if (buffers->dev_buf != nullptr) {
cuda_err = cudaFree(buffers->dev_buf);
if (cuda_err != cudaSuccess) {
fprintf(stderr, "DestroyBuf::cudaFree error: %d\n", cuda_err);
ret = -1;
}
}
// Destroy host buffer
if (buffers->host_buf != nullptr) {
cuda_err = cudaHostUnregister(buffers->host_buf);
if (cuda_err != cudaSuccess) {
fprintf(stderr, "DestroyBuf::cudaHostUnregister error: %d\n", cuda_err);
ret = -1;
}
free(buffers->host_buf);
buffers->host_buf_dev_ptr = nullptr;
}
return ret;
}
// Unroll depth in SM copy kernel
#define NUM_LOOP_UNROLL 2
// Thread block size
#define NUM_THREADS_IN_BLOCK 128
// Fetch a ulong2 from source memory and write to register
// This kernel references the implementation in
// 1) NCCL:
// https://github.com/NVIDIA/nccl/blob/7e515921295adaab72adf56ea71a0fafb0ecb5f3/src/collectives/device/common_kernel.h#L483
// 2) RCCL:
// https://github.com/ROCmSoftwarePlatform/rccl/blob/5c8380ff5b5925cae4bce00b1879a5f930226e8d/src/collectives/device/common_kernel.h#L268
inline __device__ void FetchULong2(ulong2 &v, const ulong2 *p) {
#if defined(__HIP_PLATFORM_HCC__) || defined(__HCC__) || defined(__HIPCC__)
v.x = p->x;
v.y = p->y;
#else
asm volatile("ld.volatile.global.v2.u64 {%0,%1}, [%2];" : "=l"(v.x), "=l"(v.y) : "l"(p) : "memory");
#endif
}
// Store a ulong2 from register and write to target memory
// This kernel references the implementation in
// 1) NCCL:
// https://github.com/NVIDIA/nccl/blob/7e515921295adaab72adf56ea71a0fafb0ecb5f3/src/collectives/device/common_kernel.h#L486
// 2) RCCL:
// https://github.com/ROCmSoftwarePlatform/rccl/blob/5c8380ff5b5925cae4bce00b1879a5f930226e8d/src/collectives/device/common_kernel.h#L276
inline __device__ void StoreULong2(ulong2 *p, ulong2 &v) {
#if defined(__HIP_PLATFORM_HCC__) || defined(__HCC__) || defined(__HIPCC__)
p->x = v.x;
p->y = v.y;
#else
asm volatile("st.volatile.global.v2.u64 [%0], {%1,%2};" ::"l"(p), "l"(v.x), "l"(v.y) : "memory");
#endif
}
// Fetch data from source memory into register first, and then write them to target memory
// Stride set to thread block size to best utilize cache
__global__ void SMCopyKernel(ulong2 *tgt, const ulong2 *src) {
uint64_t index = blockIdx.x * blockDim.x * NUM_LOOP_UNROLL + threadIdx.x;
ulong2 val[NUM_LOOP_UNROLL];
#pragma unroll
for (uint64_t i = 0; i < NUM_LOOP_UNROLL; i++)
FetchULong2(val[i], src + index + i * blockDim.x);
#pragma unroll
for (uint64_t i = 0; i < NUM_LOOP_UNROLL; i++)
StoreULong2(tgt + index + i * blockDim.x, val[i]);
}
// Run SM copy kernel benchmark
int BenchSMCopyKernel(const Args &args, Buffers *buffers) {
cudaError_t cuda_err = cudaSuccess;
cudaStream_t stream;
uint8_t *src_buf = nullptr;
uint8_t *tgt_buf = nullptr;
// Determine source buffer and target buff
if (args.copy_direction == "dtoh") {
src_buf = buffers->dev_buf;
tgt_buf = buffers->host_buf_dev_ptr;
} else {
src_buf = buffers->host_buf_dev_ptr;
tgt_buf = buffers->dev_buf;
}
// Validate data size
uint64_t num_elements_in_thread_block = NUM_LOOP_UNROLL * NUM_THREADS_IN_BLOCK;
uint64_t num_bytes_in_thread_block = num_elements_in_thread_block * sizeof(ulong2);
if (args.size % num_bytes_in_thread_block) {
fprintf(stderr, "Data size should be multiple of %lu\n", num_bytes_in_thread_block);
return -1;
}
// Create stream to launch kernels
cuda_err = cudaStreamCreate(&stream);
if (cuda_err != cudaSuccess) {
fprintf(stderr, "BenchSMCopyKernel::cudaStreamCreate error: %d\n", cuda_err);
return -1;
}
// Launch kernels and collect running time
uint64_t num_thread_blocks = args.size / num_bytes_in_thread_block;
auto start = std::chrono::steady_clock::now();
for (int i = 0; i < args.num_loops; i++) {
SMCopyKernel<<<num_thread_blocks, NUM_THREADS_IN_BLOCK, 0, stream>>>(reinterpret_cast<ulong2 *>(tgt_buf),
reinterpret_cast<ulong2 *>(src_buf));
}
cuda_err = cudaStreamSynchronize(stream);
auto end = std::chrono::steady_clock::now();
if (cuda_err != cudaSuccess) {
fprintf(stderr, "BenchSMCopyKernel::cudaStreamSynchronize error: %d\n", cuda_err);
return -1;
}
// Destroy stream
cuda_err = cudaStreamDestroy(stream);
if (cuda_err != cudaSuccess) {
fprintf(stderr, "BenchSMCopyKernel::cudaStreamDestroy error: %d\n", cuda_err);
return -1;
}
// Calculate and display bandwidth if no problem
double time_in_sec = std::chrono::duration_cast<std::chrono::duration<double>>(end - start).count();
printf("Bandwidth (GB/s): %g\n", args.size * args.num_loops / time_in_sec / 1e9);
return 0;
}
int main(int argc, char **argv) {
int ret = 0;
int destroy_buf_ret = 0;
cudaError_t cuda_err = cudaSuccess;
Args args;
Buffers buffers;
if (argc != static_cast<int>(ArgIdx::kNumArgs)) {
PrintUsage();
return -1;
}
args.gpu_id = std::stoi(argv[static_cast<int>(ArgIdx::kGpuId)]);
args.copy_direction = argv[static_cast<int>(ArgIdx::kCopyDirection)];
args.size = std::stoul(argv[static_cast<int>(ArgIdx::kSize)]);
args.num_loops = std::stoul(argv[static_cast<int>(ArgIdx::kNumLoops)]);
// Set device context
cuda_err = cudaSetDevice(args.gpu_id);
if (cuda_err != cudaSuccess) {
fprintf(stderr, "cudaSetDevice error: %d\n", cuda_err);
goto destroy_buf;
}
// Prepare data buffers
ret = PrepareBuf(args, &buffers);
if (ret != 0) {
goto destroy_buf;
}
// Run benchmark
ret = BenchSMCopyKernel(args, &buffers);
if (ret != 0) {
goto destroy_buf;
}
// Validate data
ret = CheckBuf(args, &buffers);
destroy_buf:
// Destroy buffers
destroy_buf_ret = DestroyBuf(&buffers);
if (ret == 0) {
ret = destroy_buf_ret;
}
return ret;
} | // Copyright (c) Microsoft Corporation.
// Licensed under the MIT License.
// GPU SM copy benchmark tests dtoh/htod data transfer bandwidth initiated by GPU SM.
#include <chrono>
#include <cstdio>
#include <cstring>
#include <string>
#include <hip/hip_runtime.h>
// Argurment index used in argument parsing.
enum class ArgIdx { kGpuId = 1, kCopyDirection, kSize, kNumLoops, kNumArgs };
// Stored arguments for this program.
struct Args {
// ID of GPU used in this benchmark.
int gpu_id = 0;
// Data transfer direction, can be "dtoh" or "htod".
std::string copy_direction;
// Data buffer size used.
uint64_t size = 0;
// Number of loops in data transfer benchmark.
uint64_t num_loops = 0;
};
struct Buffers {
// Original data buffer.
uint8_t *data_buf = nullptr;
// Buffer to validate the correctness of data transfer.
uint8_t *check_buf = nullptr;
// Data buffer in host memory.
uint8_t *host_buf = nullptr;
// Device pointer of the data buffer in host memory.
uint8_t *host_buf_dev_ptr = nullptr;
// Data buffer in device memory
uint8_t *dev_buf = nullptr;
};
// Pring usage of this program.
void PrintUsage() {
printf("Usage: gpu_sm_copy "
"<gpu-id> "
"<copy-direction: dtoh|htod> "
"<size> "
"<num_loops>\n");
}
// Prepare data buffers to be used.
int PrepareBuf(const Args &args, Buffers *buffers) {
hipError_t cuda_err = hipSuccess;
// Generate data to copy
buffers->data_buf = static_cast<uint8_t *>(malloc(args.size));
for (int i = 0; i < args.size; i++) {
buffers->data_buf[i] = static_cast<uint8_t>(i % 256);
}
// Reset check buffer
buffers->check_buf = static_cast<uint8_t *>(malloc(args.size));
memset(buffers->check_buf, 0, args.size);
// Allocate host buffer
buffers->host_buf = static_cast<uint8_t *>(malloc(args.size));
cuda_err = hipHostRegister(buffers->host_buf, args.size, hipHostRegisterMapped);
if (cuda_err != hipSuccess) {
fprintf(stderr, "PrepareBuf::hipHostRegister error: %d\n", cuda_err);
return -1;
}
cuda_err = hipHostGetDevicePointer((void **)(&(buffers->host_buf_dev_ptr)), buffers->host_buf, 0);
if (cuda_err != hipSuccess) {
fprintf(stderr, "PrepareBuf::hipHostGetDevicePointer error: %d\n", cuda_err);
return -1;
}
// Allocate device buffer
cuda_err = hipMalloc(&(buffers->dev_buf), args.size);
if (cuda_err != hipSuccess) {
fprintf(stderr, "PrepareBuf::hipMalloc error: %d\n", cuda_err);
return -1;
}
// Initialize source buffer
if (args.copy_direction == "dtoh") {
cuda_err = hipMemcpy(buffers->dev_buf, buffers->data_buf, args.size, hipMemcpyDefault);
} else if (args.copy_direction == "htod") {
cuda_err = hipMemcpy(buffers->host_buf, buffers->data_buf, args.size, hipMemcpyDefault);
} else {
fprintf(stderr, "Unrecognized copy direction: %s\n", args.copy_direction.c_str());
return -1;
}
if (cuda_err != hipSuccess) {
fprintf(stderr, "PrepareBuf::hipMemcpy error: %d\n", cuda_err);
return -1;
}
return 0;
}
// Validate the result of data transfer.
int CheckBuf(const Args &args, Buffers *buffers) {
hipError_t cuda_err = hipSuccess;
// Copy result
if (args.copy_direction == "dtoh") {
cuda_err = hipMemcpy(buffers->check_buf, buffers->host_buf, args.size, hipMemcpyDefault);
} else if (args.copy_direction == "htod") {
cuda_err = hipMemcpy(buffers->check_buf, buffers->dev_buf, args.size, hipMemcpyDefault);
}
if (cuda_err != hipSuccess) {
fprintf(stderr, "CheckBuf::hipMemcpy error: %d\n", cuda_err);
return -1;
}
// Validate result
int memcmp_result = memcmp(buffers->data_buf, buffers->check_buf, args.size);
if (memcmp_result) {
fprintf(stderr, "Memory check failed\n");
return -1;
}
return 0;
}
// Destroy data buffers
int DestroyBuf(Buffers *buffers) {
int ret = 0;
hipError_t cuda_err = hipSuccess;
// Destroy original data buffer and check buffer
if (buffers->data_buf != nullptr)
free(buffers->data_buf);
if (buffers->check_buf != nullptr)
free(buffers->check_buf);
// Destroy device buffer
if (buffers->dev_buf != nullptr) {
cuda_err = hipFree(buffers->dev_buf);
if (cuda_err != hipSuccess) {
fprintf(stderr, "DestroyBuf::hipFree error: %d\n", cuda_err);
ret = -1;
}
}
// Destroy host buffer
if (buffers->host_buf != nullptr) {
cuda_err = hipHostUnregister(buffers->host_buf);
if (cuda_err != hipSuccess) {
fprintf(stderr, "DestroyBuf::hipHostUnregister error: %d\n", cuda_err);
ret = -1;
}
free(buffers->host_buf);
buffers->host_buf_dev_ptr = nullptr;
}
return ret;
}
// Unroll depth in SM copy kernel
#define NUM_LOOP_UNROLL 2
// Thread block size
#define NUM_THREADS_IN_BLOCK 128
// Fetch a ulong2 from source memory and write to register
// This kernel references the implementation in
// 1) NCCL:
// https://github.com/NVIDIA/nccl/blob/7e515921295adaab72adf56ea71a0fafb0ecb5f3/src/collectives/device/common_kernel.h#L483
// 2) RCCL:
// https://github.com/ROCmSoftwarePlatform/rccl/blob/5c8380ff5b5925cae4bce00b1879a5f930226e8d/src/collectives/device/common_kernel.h#L268
inline __device__ void FetchULong2(ulong2 &v, const ulong2 *p) {
#if defined(__HIP_PLATFORM_HCC__) || defined(__HCC__) || defined(__HIPCC__)
v.x = p->x;
v.y = p->y;
#else
asm volatile("ld.volatile.global.v2.u64 {%0,%1}, [%2];" : "=l"(v.x), "=l"(v.y) : "l"(p) : "memory");
#endif
}
// Store a ulong2 from register and write to target memory
// This kernel references the implementation in
// 1) NCCL:
// https://github.com/NVIDIA/nccl/blob/7e515921295adaab72adf56ea71a0fafb0ecb5f3/src/collectives/device/common_kernel.h#L486
// 2) RCCL:
// https://github.com/ROCmSoftwarePlatform/rccl/blob/5c8380ff5b5925cae4bce00b1879a5f930226e8d/src/collectives/device/common_kernel.h#L276
inline __device__ void StoreULong2(ulong2 *p, ulong2 &v) {
#if defined(__HIP_PLATFORM_HCC__) || defined(__HCC__) || defined(__HIPCC__)
p->x = v.x;
p->y = v.y;
#else
asm volatile("st.volatile.global.v2.u64 [%0], {%1,%2};" ::"l"(p), "l"(v.x), "l"(v.y) : "memory");
#endif
}
// Fetch data from source memory into register first, and then write them to target memory
// Stride set to thread block size to best utilize cache
__global__ void SMCopyKernel(ulong2 *tgt, const ulong2 *src) {
uint64_t index = blockIdx.x * blockDim.x * NUM_LOOP_UNROLL + threadIdx.x;
ulong2 val[NUM_LOOP_UNROLL];
#pragma unroll
for (uint64_t i = 0; i < NUM_LOOP_UNROLL; i++)
FetchULong2(val[i], src + index + i * blockDim.x);
#pragma unroll
for (uint64_t i = 0; i < NUM_LOOP_UNROLL; i++)
StoreULong2(tgt + index + i * blockDim.x, val[i]);
}
// Run SM copy kernel benchmark
int BenchSMCopyKernel(const Args &args, Buffers *buffers) {
hipError_t cuda_err = hipSuccess;
hipStream_t stream;
uint8_t *src_buf = nullptr;
uint8_t *tgt_buf = nullptr;
// Determine source buffer and target buff
if (args.copy_direction == "dtoh") {
src_buf = buffers->dev_buf;
tgt_buf = buffers->host_buf_dev_ptr;
} else {
src_buf = buffers->host_buf_dev_ptr;
tgt_buf = buffers->dev_buf;
}
// Validate data size
uint64_t num_elements_in_thread_block = NUM_LOOP_UNROLL * NUM_THREADS_IN_BLOCK;
uint64_t num_bytes_in_thread_block = num_elements_in_thread_block * sizeof(ulong2);
if (args.size % num_bytes_in_thread_block) {
fprintf(stderr, "Data size should be multiple of %lu\n", num_bytes_in_thread_block);
return -1;
}
// Create stream to launch kernels
cuda_err = hipStreamCreate(&stream);
if (cuda_err != hipSuccess) {
fprintf(stderr, "BenchSMCopyKernel::hipStreamCreate error: %d\n", cuda_err);
return -1;
}
// Launch kernels and collect running time
uint64_t num_thread_blocks = args.size / num_bytes_in_thread_block;
auto start = std::chrono::steady_clock::now();
for (int i = 0; i < args.num_loops; i++) {
SMCopyKernel<<<num_thread_blocks, NUM_THREADS_IN_BLOCK, 0, stream>>>(reinterpret_cast<ulong2 *>(tgt_buf),
reinterpret_cast<ulong2 *>(src_buf));
}
cuda_err = hipStreamSynchronize(stream);
auto end = std::chrono::steady_clock::now();
if (cuda_err != hipSuccess) {
fprintf(stderr, "BenchSMCopyKernel::hipStreamSynchronize error: %d\n", cuda_err);
return -1;
}
// Destroy stream
cuda_err = hipStreamDestroy(stream);
if (cuda_err != hipSuccess) {
fprintf(stderr, "BenchSMCopyKernel::hipStreamDestroy error: %d\n", cuda_err);
return -1;
}
// Calculate and display bandwidth if no problem
double time_in_sec = std::chrono::duration_cast<std::chrono::duration<double>>(end - start).count();
printf("Bandwidth (GB/s): %g\n", args.size * args.num_loops / time_in_sec / 1e9);
return 0;
}
int main(int argc, char **argv) {
int ret = 0;
int destroy_buf_ret = 0;
hipError_t cuda_err = hipSuccess;
Args args;
Buffers buffers;
if (argc != static_cast<int>(ArgIdx::kNumArgs)) {
PrintUsage();
return -1;
}
args.gpu_id = std::stoi(argv[static_cast<int>(ArgIdx::kGpuId)]);
args.copy_direction = argv[static_cast<int>(ArgIdx::kCopyDirection)];
args.size = std::stoul(argv[static_cast<int>(ArgIdx::kSize)]);
args.num_loops = std::stoul(argv[static_cast<int>(ArgIdx::kNumLoops)]);
// Set device context
cuda_err = hipSetDevice(args.gpu_id);
if (cuda_err != hipSuccess) {
fprintf(stderr, "hipSetDevice error: %d\n", cuda_err);
goto destroy_buf;
}
// Prepare data buffers
ret = PrepareBuf(args, &buffers);
if (ret != 0) {
goto destroy_buf;
}
// Run benchmark
ret = BenchSMCopyKernel(args, &buffers);
if (ret != 0) {
goto destroy_buf;
}
// Validate data
ret = CheckBuf(args, &buffers);
destroy_buf:
// Destroy buffers
destroy_buf_ret = DestroyBuf(&buffers);
if (ret == 0) {
ret = destroy_buf_ret;
}
return ret;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Copyright (c) Microsoft Corporation.
// Licensed under the MIT License.
// GPU SM copy benchmark tests dtoh/htod data transfer bandwidth initiated by GPU SM.
#include <chrono>
#include <cstdio>
#include <cstring>
#include <string>
#include <hip/hip_runtime.h>
// Argurment index used in argument parsing.
enum class ArgIdx { kGpuId = 1, kCopyDirection, kSize, kNumLoops, kNumArgs };
// Stored arguments for this program.
struct Args {
// ID of GPU used in this benchmark.
int gpu_id = 0;
// Data transfer direction, can be "dtoh" or "htod".
std::string copy_direction;
// Data buffer size used.
uint64_t size = 0;
// Number of loops in data transfer benchmark.
uint64_t num_loops = 0;
};
struct Buffers {
// Original data buffer.
uint8_t *data_buf = nullptr;
// Buffer to validate the correctness of data transfer.
uint8_t *check_buf = nullptr;
// Data buffer in host memory.
uint8_t *host_buf = nullptr;
// Device pointer of the data buffer in host memory.
uint8_t *host_buf_dev_ptr = nullptr;
// Data buffer in device memory
uint8_t *dev_buf = nullptr;
};
// Pring usage of this program.
void PrintUsage() {
printf("Usage: gpu_sm_copy "
"<gpu-id> "
"<copy-direction: dtoh|htod> "
"<size> "
"<num_loops>\n");
}
// Prepare data buffers to be used.
int PrepareBuf(const Args &args, Buffers *buffers) {
hipError_t cuda_err = hipSuccess;
// Generate data to copy
buffers->data_buf = static_cast<uint8_t *>(malloc(args.size));
for (int i = 0; i < args.size; i++) {
buffers->data_buf[i] = static_cast<uint8_t>(i % 256);
}
// Reset check buffer
buffers->check_buf = static_cast<uint8_t *>(malloc(args.size));
memset(buffers->check_buf, 0, args.size);
// Allocate host buffer
buffers->host_buf = static_cast<uint8_t *>(malloc(args.size));
cuda_err = hipHostRegister(buffers->host_buf, args.size, hipHostRegisterMapped);
if (cuda_err != hipSuccess) {
fprintf(stderr, "PrepareBuf::hipHostRegister error: %d\n", cuda_err);
return -1;
}
cuda_err = hipHostGetDevicePointer((void **)(&(buffers->host_buf_dev_ptr)), buffers->host_buf, 0);
if (cuda_err != hipSuccess) {
fprintf(stderr, "PrepareBuf::hipHostGetDevicePointer error: %d\n", cuda_err);
return -1;
}
// Allocate device buffer
cuda_err = hipMalloc(&(buffers->dev_buf), args.size);
if (cuda_err != hipSuccess) {
fprintf(stderr, "PrepareBuf::hipMalloc error: %d\n", cuda_err);
return -1;
}
// Initialize source buffer
if (args.copy_direction == "dtoh") {
cuda_err = hipMemcpy(buffers->dev_buf, buffers->data_buf, args.size, hipMemcpyDefault);
} else if (args.copy_direction == "htod") {
cuda_err = hipMemcpy(buffers->host_buf, buffers->data_buf, args.size, hipMemcpyDefault);
} else {
fprintf(stderr, "Unrecognized copy direction: %s\n", args.copy_direction.c_str());
return -1;
}
if (cuda_err != hipSuccess) {
fprintf(stderr, "PrepareBuf::hipMemcpy error: %d\n", cuda_err);
return -1;
}
return 0;
}
// Validate the result of data transfer.
int CheckBuf(const Args &args, Buffers *buffers) {
hipError_t cuda_err = hipSuccess;
// Copy result
if (args.copy_direction == "dtoh") {
cuda_err = hipMemcpy(buffers->check_buf, buffers->host_buf, args.size, hipMemcpyDefault);
} else if (args.copy_direction == "htod") {
cuda_err = hipMemcpy(buffers->check_buf, buffers->dev_buf, args.size, hipMemcpyDefault);
}
if (cuda_err != hipSuccess) {
fprintf(stderr, "CheckBuf::hipMemcpy error: %d\n", cuda_err);
return -1;
}
// Validate result
int memcmp_result = memcmp(buffers->data_buf, buffers->check_buf, args.size);
if (memcmp_result) {
fprintf(stderr, "Memory check failed\n");
return -1;
}
return 0;
}
// Destroy data buffers
int DestroyBuf(Buffers *buffers) {
int ret = 0;
hipError_t cuda_err = hipSuccess;
// Destroy original data buffer and check buffer
if (buffers->data_buf != nullptr)
free(buffers->data_buf);
if (buffers->check_buf != nullptr)
free(buffers->check_buf);
// Destroy device buffer
if (buffers->dev_buf != nullptr) {
cuda_err = hipFree(buffers->dev_buf);
if (cuda_err != hipSuccess) {
fprintf(stderr, "DestroyBuf::hipFree error: %d\n", cuda_err);
ret = -1;
}
}
// Destroy host buffer
if (buffers->host_buf != nullptr) {
cuda_err = hipHostUnregister(buffers->host_buf);
if (cuda_err != hipSuccess) {
fprintf(stderr, "DestroyBuf::hipHostUnregister error: %d\n", cuda_err);
ret = -1;
}
free(buffers->host_buf);
buffers->host_buf_dev_ptr = nullptr;
}
return ret;
}
// Unroll depth in SM copy kernel
#define NUM_LOOP_UNROLL 2
// Thread block size
#define NUM_THREADS_IN_BLOCK 128
// Fetch a ulong2 from source memory and write to register
// This kernel references the implementation in
// 1) NCCL:
// https://github.com/NVIDIA/nccl/blob/7e515921295adaab72adf56ea71a0fafb0ecb5f3/src/collectives/device/common_kernel.h#L483
// 2) RCCL:
// https://github.com/ROCmSoftwarePlatform/rccl/blob/5c8380ff5b5925cae4bce00b1879a5f930226e8d/src/collectives/device/common_kernel.h#L268
inline __device__ void FetchULong2(ulong2 &v, const ulong2 *p) {
#if defined(__HIP_PLATFORM_HCC__) || defined(__HCC__) || defined(__HIPCC__)
v.x = p->x;
v.y = p->y;
#else
asm volatile("ld.volatile.global.v2.u64 {%0,%1}, [%2];" : "=l"(v.x), "=l"(v.y) : "l"(p) : "memory");
#endif
}
// Store a ulong2 from register and write to target memory
// This kernel references the implementation in
// 1) NCCL:
// https://github.com/NVIDIA/nccl/blob/7e515921295adaab72adf56ea71a0fafb0ecb5f3/src/collectives/device/common_kernel.h#L486
// 2) RCCL:
// https://github.com/ROCmSoftwarePlatform/rccl/blob/5c8380ff5b5925cae4bce00b1879a5f930226e8d/src/collectives/device/common_kernel.h#L276
inline __device__ void StoreULong2(ulong2 *p, ulong2 &v) {
#if defined(__HIP_PLATFORM_HCC__) || defined(__HCC__) || defined(__HIPCC__)
p->x = v.x;
p->y = v.y;
#else
asm volatile("st.volatile.global.v2.u64 [%0], {%1,%2};" ::"l"(p), "l"(v.x), "l"(v.y) : "memory");
#endif
}
// Fetch data from source memory into register first, and then write them to target memory
// Stride set to thread block size to best utilize cache
__global__ void SMCopyKernel(ulong2 *tgt, const ulong2 *src) {
uint64_t index = blockIdx.x * blockDim.x * NUM_LOOP_UNROLL + threadIdx.x;
ulong2 val[NUM_LOOP_UNROLL];
#pragma unroll
for (uint64_t i = 0; i < NUM_LOOP_UNROLL; i++)
FetchULong2(val[i], src + index + i * blockDim.x);
#pragma unroll
for (uint64_t i = 0; i < NUM_LOOP_UNROLL; i++)
StoreULong2(tgt + index + i * blockDim.x, val[i]);
}
// Run SM copy kernel benchmark
int BenchSMCopyKernel(const Args &args, Buffers *buffers) {
hipError_t cuda_err = hipSuccess;
hipStream_t stream;
uint8_t *src_buf = nullptr;
uint8_t *tgt_buf = nullptr;
// Determine source buffer and target buff
if (args.copy_direction == "dtoh") {
src_buf = buffers->dev_buf;
tgt_buf = buffers->host_buf_dev_ptr;
} else {
src_buf = buffers->host_buf_dev_ptr;
tgt_buf = buffers->dev_buf;
}
// Validate data size
uint64_t num_elements_in_thread_block = NUM_LOOP_UNROLL * NUM_THREADS_IN_BLOCK;
uint64_t num_bytes_in_thread_block = num_elements_in_thread_block * sizeof(ulong2);
if (args.size % num_bytes_in_thread_block) {
fprintf(stderr, "Data size should be multiple of %lu\n", num_bytes_in_thread_block);
return -1;
}
// Create stream to launch kernels
cuda_err = hipStreamCreate(&stream);
if (cuda_err != hipSuccess) {
fprintf(stderr, "BenchSMCopyKernel::hipStreamCreate error: %d\n", cuda_err);
return -1;
}
// Launch kernels and collect running time
uint64_t num_thread_blocks = args.size / num_bytes_in_thread_block;
auto start = std::chrono::steady_clock::now();
for (int i = 0; i < args.num_loops; i++) {
SMCopyKernel<<<num_thread_blocks, NUM_THREADS_IN_BLOCK, 0, stream>>>(reinterpret_cast<ulong2 *>(tgt_buf),
reinterpret_cast<ulong2 *>(src_buf));
}
cuda_err = hipStreamSynchronize(stream);
auto end = std::chrono::steady_clock::now();
if (cuda_err != hipSuccess) {
fprintf(stderr, "BenchSMCopyKernel::hipStreamSynchronize error: %d\n", cuda_err);
return -1;
}
// Destroy stream
cuda_err = hipStreamDestroy(stream);
if (cuda_err != hipSuccess) {
fprintf(stderr, "BenchSMCopyKernel::hipStreamDestroy error: %d\n", cuda_err);
return -1;
}
// Calculate and display bandwidth if no problem
double time_in_sec = std::chrono::duration_cast<std::chrono::duration<double>>(end - start).count();
printf("Bandwidth (GB/s): %g\n", args.size * args.num_loops / time_in_sec / 1e9);
return 0;
}
int main(int argc, char **argv) {
int ret = 0;
int destroy_buf_ret = 0;
hipError_t cuda_err = hipSuccess;
Args args;
Buffers buffers;
if (argc != static_cast<int>(ArgIdx::kNumArgs)) {
PrintUsage();
return -1;
}
args.gpu_id = std::stoi(argv[static_cast<int>(ArgIdx::kGpuId)]);
args.copy_direction = argv[static_cast<int>(ArgIdx::kCopyDirection)];
args.size = std::stoul(argv[static_cast<int>(ArgIdx::kSize)]);
args.num_loops = std::stoul(argv[static_cast<int>(ArgIdx::kNumLoops)]);
// Set device context
cuda_err = hipSetDevice(args.gpu_id);
if (cuda_err != hipSuccess) {
fprintf(stderr, "hipSetDevice error: %d\n", cuda_err);
goto destroy_buf;
}
// Prepare data buffers
ret = PrepareBuf(args, &buffers);
if (ret != 0) {
goto destroy_buf;
}
// Run benchmark
ret = BenchSMCopyKernel(args, &buffers);
if (ret != 0) {
goto destroy_buf;
}
// Validate data
ret = CheckBuf(args, &buffers);
destroy_buf:
// Destroy buffers
destroy_buf_ret = DestroyBuf(&buffers);
if (ret == 0) {
ret = destroy_buf_ret;
}
return ret;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12SMCopyKernelP15HIP_vector_typeImLj2EEPKS0_
.globl _Z12SMCopyKernelP15HIP_vector_typeImLj2EEPKS0_
.p2align 8
.type _Z12SMCopyKernelP15HIP_vector_typeImLj2EEPKS0_,@function
_Z12SMCopyKernelP15HIP_vector_typeImLj2EEPKS0_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s4
v_lshl_add_u32 v0, s15, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 4, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v9, vcc_lo
s_lshl_b32 s2, s4, 4
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_add_co_u32 v4, vcc_lo, v0, s2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v8, vcc_lo, s0, v8
s_clause 0x1
global_load_b128 v[0:3], v[0:1], off
global_load_b128 v[4:7], v[4:5], off
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v9, vcc_lo
v_add_co_u32 v10, vcc_lo, v8, s2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v9, vcc_lo
s_waitcnt vmcnt(1)
global_store_b128 v[8:9], v[0:3], off
s_waitcnt vmcnt(0)
global_store_b128 v[10:11], v[4:7], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12SMCopyKernelP15HIP_vector_typeImLj2EEPKS0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12SMCopyKernelP15HIP_vector_typeImLj2EEPKS0_, .Lfunc_end0-_Z12SMCopyKernelP15HIP_vector_typeImLj2EEPKS0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12SMCopyKernelP15HIP_vector_typeImLj2EEPKS0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12SMCopyKernelP15HIP_vector_typeImLj2EEPKS0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12SMCopyKernelP6ulong2PKS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0030*/ MOV R13, c[0x0][0x0] ; /* 0x00000000000d7a02 */
/* 0x000fe20000000f00 */
/*0040*/ HFMA2.MMA R15, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff0f7435 */
/* 0x000fc600000001ff */
/*0050*/ SHF.L.U32 R0, R13, 0x1, RZ ; /* 0x000000010d007819 */
/* 0x000fca00000006ff */
/*0060*/ IMAD R0, R0, UR4, R3 ; /* 0x0000000400007c24 */
/* 0x001fe2000f8e0203 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE.U32 R4, R0, R15, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fcc00078e000f */
/*0090*/ IMAD.WIDE.U32 R8, R13, 0x10, R4 ; /* 0x000000100d087825 */
/* 0x000fe400078e0004 */
/*00a0*/ LDG.E.128.STRONG.SYS R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1f5d00 */
/*00b0*/ LDG.E.128.STRONG.SYS R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee2000c1f5d00 */
/*00c0*/ IMAD.WIDE.U32 R2, R0, R15, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e000f */
/*00d0*/ IMAD.WIDE.U32 R12, R13, 0x10, R2 ; /* 0x000000100d0c7825 */
/* 0x000fe200078e0002 */
/*00e0*/ STG.E.128.STRONG.SYS [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x004fe8000c115d04 */
/*00f0*/ STG.E.128.STRONG.SYS [R12.64], R8 ; /* 0x000000080c007986 */
/* 0x008fe2000c115d04 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12SMCopyKernelP15HIP_vector_typeImLj2EEPKS0_
.globl _Z12SMCopyKernelP15HIP_vector_typeImLj2EEPKS0_
.p2align 8
.type _Z12SMCopyKernelP15HIP_vector_typeImLj2EEPKS0_,@function
_Z12SMCopyKernelP15HIP_vector_typeImLj2EEPKS0_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s15, s15, s4
v_lshl_add_u32 v0, s15, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 4, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v9, vcc_lo
s_lshl_b32 s2, s4, 4
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_add_co_u32 v4, vcc_lo, v0, s2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
v_add_co_u32 v8, vcc_lo, s0, v8
s_clause 0x1
global_load_b128 v[0:3], v[0:1], off
global_load_b128 v[4:7], v[4:5], off
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v9, vcc_lo
v_add_co_u32 v10, vcc_lo, v8, s2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v9, vcc_lo
s_waitcnt vmcnt(1)
global_store_b128 v[8:9], v[0:3], off
s_waitcnt vmcnt(0)
global_store_b128 v[10:11], v[4:7], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12SMCopyKernelP15HIP_vector_typeImLj2EEPKS0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12SMCopyKernelP15HIP_vector_typeImLj2EEPKS0_, .Lfunc_end0-_Z12SMCopyKernelP15HIP_vector_typeImLj2EEPKS0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12SMCopyKernelP15HIP_vector_typeImLj2EEPKS0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12SMCopyKernelP15HIP_vector_typeImLj2EEPKS0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void VectorMultiplicationKernel(int *array, int arrayCount)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < arrayCount)
{
array[idx] *= array[idx];
}
} | code for sm_80
Function : _Z26VectorMultiplicationKernelPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ IMAD R5, R0, R0, RZ ; /* 0x0000000000057224 */
/* 0x004fca00078e02ff */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void VectorMultiplicationKernel(int *array, int arrayCount)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < arrayCount)
{
array[idx] *= array[idx];
}
} | .file "tmpxft_000bbe06_00000000-6_VectorMultiplicationKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z26VectorMultiplicationKernelPiiPii
.type _Z47__device_stub__Z26VectorMultiplicationKernelPiiPii, @function
_Z47__device_stub__Z26VectorMultiplicationKernelPiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z26VectorMultiplicationKernelPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z26VectorMultiplicationKernelPiiPii, .-_Z47__device_stub__Z26VectorMultiplicationKernelPiiPii
.globl _Z26VectorMultiplicationKernelPii
.type _Z26VectorMultiplicationKernelPii, @function
_Z26VectorMultiplicationKernelPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z26VectorMultiplicationKernelPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26VectorMultiplicationKernelPii, .-_Z26VectorMultiplicationKernelPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26VectorMultiplicationKernelPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26VectorMultiplicationKernelPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void VectorMultiplicationKernel(int *array, int arrayCount)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < arrayCount)
{
array[idx] *= array[idx];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void VectorMultiplicationKernel(int *array, int arrayCount)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < arrayCount)
{
array[idx] *= array[idx];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void VectorMultiplicationKernel(int *array, int arrayCount)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < arrayCount)
{
array[idx] *= array[idx];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26VectorMultiplicationKernelPii
.globl _Z26VectorMultiplicationKernelPii
.p2align 8
.type _Z26VectorMultiplicationKernelPii,@function
_Z26VectorMultiplicationKernelPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26VectorMultiplicationKernelPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26VectorMultiplicationKernelPii, .Lfunc_end0-_Z26VectorMultiplicationKernelPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26VectorMultiplicationKernelPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26VectorMultiplicationKernelPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void VectorMultiplicationKernel(int *array, int arrayCount)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < arrayCount)
{
array[idx] *= array[idx];
}
} | .text
.file "VectorMultiplicationKernel.hip"
.globl _Z41__device_stub__VectorMultiplicationKernelPii # -- Begin function _Z41__device_stub__VectorMultiplicationKernelPii
.p2align 4, 0x90
.type _Z41__device_stub__VectorMultiplicationKernelPii,@function
_Z41__device_stub__VectorMultiplicationKernelPii: # @_Z41__device_stub__VectorMultiplicationKernelPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z26VectorMultiplicationKernelPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z41__device_stub__VectorMultiplicationKernelPii, .Lfunc_end0-_Z41__device_stub__VectorMultiplicationKernelPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26VectorMultiplicationKernelPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26VectorMultiplicationKernelPii,@object # @_Z26VectorMultiplicationKernelPii
.section .rodata,"a",@progbits
.globl _Z26VectorMultiplicationKernelPii
.p2align 3, 0x0
_Z26VectorMultiplicationKernelPii:
.quad _Z41__device_stub__VectorMultiplicationKernelPii
.size _Z26VectorMultiplicationKernelPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26VectorMultiplicationKernelPii"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__VectorMultiplicationKernelPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26VectorMultiplicationKernelPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z26VectorMultiplicationKernelPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ IMAD R5, R0, R0, RZ ; /* 0x0000000000057224 */
/* 0x004fca00078e02ff */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26VectorMultiplicationKernelPii
.globl _Z26VectorMultiplicationKernelPii
.p2align 8
.type _Z26VectorMultiplicationKernelPii,@function
_Z26VectorMultiplicationKernelPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26VectorMultiplicationKernelPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26VectorMultiplicationKernelPii, .Lfunc_end0-_Z26VectorMultiplicationKernelPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26VectorMultiplicationKernelPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26VectorMultiplicationKernelPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000bbe06_00000000-6_VectorMultiplicationKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z26VectorMultiplicationKernelPiiPii
.type _Z47__device_stub__Z26VectorMultiplicationKernelPiiPii, @function
_Z47__device_stub__Z26VectorMultiplicationKernelPiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z26VectorMultiplicationKernelPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z26VectorMultiplicationKernelPiiPii, .-_Z47__device_stub__Z26VectorMultiplicationKernelPiiPii
.globl _Z26VectorMultiplicationKernelPii
.type _Z26VectorMultiplicationKernelPii, @function
_Z26VectorMultiplicationKernelPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z26VectorMultiplicationKernelPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26VectorMultiplicationKernelPii, .-_Z26VectorMultiplicationKernelPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26VectorMultiplicationKernelPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26VectorMultiplicationKernelPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "VectorMultiplicationKernel.hip"
.globl _Z41__device_stub__VectorMultiplicationKernelPii # -- Begin function _Z41__device_stub__VectorMultiplicationKernelPii
.p2align 4, 0x90
.type _Z41__device_stub__VectorMultiplicationKernelPii,@function
_Z41__device_stub__VectorMultiplicationKernelPii: # @_Z41__device_stub__VectorMultiplicationKernelPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z26VectorMultiplicationKernelPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z41__device_stub__VectorMultiplicationKernelPii, .Lfunc_end0-_Z41__device_stub__VectorMultiplicationKernelPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26VectorMultiplicationKernelPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26VectorMultiplicationKernelPii,@object # @_Z26VectorMultiplicationKernelPii
.section .rodata,"a",@progbits
.globl _Z26VectorMultiplicationKernelPii
.p2align 3, 0x0
_Z26VectorMultiplicationKernelPii:
.quad _Z41__device_stub__VectorMultiplicationKernelPii
.size _Z26VectorMultiplicationKernelPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26VectorMultiplicationKernelPii"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__VectorMultiplicationKernelPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26VectorMultiplicationKernelPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <stdio.h>
#include <stdlib.h>
#define TILE_WIDTH 32
using namespace std;
__global__ void multTiled(float *A, float *B, float *C,int rA,int cA,int rB,int cB){
__shared__ int Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ int Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * TILE_WIDTH + ty;
int col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
for(int k = 0; k < (cA+TILE_WIDTH-1)/(TILE_WIDTH); ++k){
if(k*TILE_WIDTH + tx < cA && row < rA){
Mds[ty][tx] = A[row*cA + k*TILE_WIDTH + tx];
}else{
Mds[ty][tx] = 0;
}
if(k*TILE_WIDTH + ty < cA && col < cB){
Nds[ty][tx] = B[(k*TILE_WIDTH + ty) * cB + col];
}else{
Nds[ty][tx] =0;
}
__syncthreads();
for(int k = 0; k < TILE_WIDTH; ++k){
Pvalue += Mds[ty][k] * Nds[k][tx];
}
__syncthreads();
}
if (row < rA && col < cB){
C[row*cB+col] = Pvalue;
}
}
__global__ void matrixMulKernel(float *d_A, float *d_B, float *d_C,int rA,int cA,int rB,int cB){
int row = blockIdx.y*blockDim.y+threadIdx.y;
int col = blockIdx.x*blockDim.x+threadIdx.x;
float Pvalue;
if((row < rA)&&(col < cB)){
Pvalue = 0;
for (int k = 0; k < rB ; ++k){
Pvalue += d_A[row*cA+k] * d_B[k*cB+col];
}
d_C[row*cB+col] = Pvalue;
}
}
void multMxN(float *A,float *B, float *C, int rA,int cA,int rB,int cB){
//El numero de col de A, debe ser igual al numero de row de B;
//Matriz C= FilasAxColumnasB
for(int i=0;i<rA;i++){
for(int j=0;j<cB;j++){
float value=0;
for(int k=0;k<rB;k++){
//h_c[n*i+j]+=h_a[n*i+k]*h_b[n*k+j];
value+=A[cA*i+k]*B[cB*k+j];
}
C[cB*i+j]=value;
}
}
}
void llenar(float *MA,int n,int m){
int tam=n*m;
for(int i = 0; i < tam; i++ )
MA[i] = 1.0;
}
void imprimir(float *MA,int n,int m){
int tam=n*m,cont=0;
for(int i = 0; i < tam; i++ ) {
printf("%f ",MA[i]);
if(cont==m-1){
printf("\n");
cont=-1;
}
cont++;
}
printf("\n");
}
void comparar(float *C1,float *C2,int rC,int cC){
int w=rC*cC;
for(int i=0;i<w;i++){
if(C1[i]!=C2[i]){
cout<<"No son iguales"<<endl;
break;
}
}
cout<<"Son iguales"<<endl;
}
int main(){
int rA=128;
int cA=1024;
int cB=512;
float blockSize = 4;
int rB=cA;
size_t bytesA=(rA*cA)*sizeof(float);
size_t bytesB=(rB*cB)*sizeof(float);
size_t bytesC=(rA*cB)*sizeof(float);
float *A=(float*)malloc(bytesA);
float *B=(float*)malloc(bytesB);
float *C1=(float*)malloc(bytesC);
float *C2=(float*)malloc(bytesC);
float *C3=(float*)malloc(bytesC);
//1.Lleno las matrices
llenar(A,rA,cA);
llenar(B,rB,cB);
//2.imprimo las matrices
//cout<<"Matriz A:"<<endl;
//imprimir(A,rA,cA);
//cout<<"Matriz B:"<<endl;
//imprimir(B,rB,cB);
//3.Multiplico matrices NxM Secuencial
clock_t start = clock();
multMxN(A,B,C1,rA,cA,rB,cB);
clock_t end= clock();
double elapsed_seconds=end-start;
printf("Tiempo transcurrido Secuencial: %lf\n", (elapsed_seconds / CLOCKS_PER_SEC));
//cout<<"Secuencial"<<endl;
//imprimir(C1,rA,cB);
//3.Multiplico matrices NxM Paralelo sin Tile
float *d_A;
float *d_B;
float *d_C;
// Allocate memory for each vector on GPU
cudaMalloc(&d_A,bytesA);
cudaMalloc(&d_B,bytesB);
cudaMalloc(&d_C,bytesC);
// Copy host vectors to device
cudaMemcpy( d_A, A, bytesA, cudaMemcpyHostToDevice);
cudaMemcpy( d_B, B, bytesB, cudaMemcpyHostToDevice);
//bloques
dim3 dimGrid(ceil(cB/blockSize),ceil(rA/blockSize),1);
//hilos
dim3 dimBlock(blockSize,blockSize,1);
//Tiempo de ejecucion Paralelo
clock_t start2 = clock();
// Execute the kernel
matrixMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C,rA,cA,rB,cB);
//multTiled<<<dimGrid, dimBlock>>>(d_A, d_B, d_C,rA,cA,rB,cB);
cudaDeviceSynchronize();
// Copy array back to host
cudaMemcpy( C2, d_C, bytesC, cudaMemcpyDeviceToHost );
clock_t end2= clock();
double elapsed_seconds2=end2-start2;
printf("Tiempo transcurrido Paralelo SinTile: %lf\n", (elapsed_seconds2 / CLOCKS_PER_SEC));
//4.Imprimo matriz C
//cout<<endl<<"Paralelo sin tiling"<<endl;
//imprimir(C2,rA,cB);
//cout<<"Matriz Secuencial-SinTiling: "<<endl;
//cout<<endl;
// Execute the kernel
//Tiempo de ejecucion Paralelo
clock_t start3 = clock();
multTiled<<<dimGrid, dimBlock>>>(d_A, d_B, d_C,rA,cA,rB,cB);
cudaDeviceSynchronize();
// Copy array back to host
cudaMemcpy( C3, d_C, bytesC, cudaMemcpyDeviceToHost );
clock_t end3= clock();
double elapsed_seconds3=end3-start3;
printf("Tiempo transcurrido Paralelo ConTile: %lf\n", (elapsed_seconds3 / CLOCKS_PER_SEC));
//4.Imprimo matriz C
//cout<<endl<<"Paralelo con tiling"<<endl;
//imprimir(C3,rA,cB);
// cout<<"Matriz Secuencial-Tiling: "<<endl;
comparar(C1,C3,rA,cB);
comparar(C1,C2,rA,cB);
// Release device memory
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
// Release host memory
free(A);
free(B);
free(C1);
free(C2);
return 0;
} | .file "tmpxft_00106981_00000000-6_multMatrixTileFloat.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3676:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3676:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7multMxNPfS_S_iiii
.type _Z7multMxNPfS_S_iiii, @function
_Z7multMxNPfS_S_iiii:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rsi, -24(%rsp)
movq %rdx, -16(%rsp)
movl %ecx, -28(%rsp)
movl 56(%rsp), %r14d
testl %ecx, %ecx
jle .L3
movq %rdi, %rbx
movl %r9d, %r11d
movslq %r14d, %rbp
leaq 0(,%rbp,4), %rsi
movl $0, %r13d
movl $0, %r12d
movl $0, %edx
movslq %r9d, %rax
movq %rax, -8(%rsp)
movl %r8d, %ecx
jmp .L5
.L6:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
addq %rsi, %rdx
cmpq %rdi, %rax
jne .L6
.L8:
movss %xmm1, (%r10,%r8,4)
addq $1, %r8
addq $4, %r9
cmpq %r8, %rbp
je .L13
.L9:
movq %r9, %rdx
movq %r15, %rax
pxor %xmm1, %xmm1
testl %r11d, %r11d
jg .L6
jmp .L8
.L13:
movl -32(%rsp), %edx
.L7:
addl $1, %edx
addl %r14d, %r12d
addl %ecx, %r13d
cmpl %edx, -28(%rsp)
je .L3
.L5:
testl %r14d, %r14d
jle .L7
movq -24(%rsp), %r9
movslq %r13d, %rax
leaq (%rbx,%rax,4), %r15
movq -8(%rsp), %rdi
addq %rdi, %rax
leaq (%rbx,%rax,4), %rdi
movslq %r12d, %rax
movq -16(%rsp), %r10
leaq (%r10,%rax,4), %r10
movl $0, %r8d
movl %edx, -32(%rsp)
jmp .L9
.L3:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size _Z7multMxNPfS_S_iiii, .-_Z7multMxNPfS_S_iiii
.globl _Z6llenarPfii
.type _Z6llenarPfii, @function
_Z6llenarPfii:
.LFB3670:
.cfi_startproc
endbr64
imull %edx, %esi
testl %esi, %esi
jle .L16
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rdx
movss .LC1(%rip), %xmm0
.L18:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L18
.L16:
ret
.cfi_endproc
.LFE3670:
.size _Z6llenarPfii, .-_Z6llenarPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%f "
.LC3:
.string "\n"
.text
.globl _Z8imprimirPfii
.type _Z8imprimirPfii, @function
_Z8imprimirPfii:
.LFB3671:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
imull %edx, %esi
testl %esi, %esi
jle .L21
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %r14
movl $0, %ebp
leaq .LC2(%rip), %r13
leal -1(%rdx), %r12d
leaq .LC3(%rip), %r15
jmp .L23
.L22:
addl $1, %ebp
addq $4, %rbx
cmpq %r14, %rbx
je .L21
.L23:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpl %ebp, %r12d
jne .L22
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %ebp
jmp .L22
.L21:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3671:
.size _Z8imprimirPfii, .-_Z8imprimirPfii
.section .rodata.str1.1
.LC4:
.string "No son iguales"
.LC5:
.string "Son iguales"
.text
.globl _Z8compararPfS_ii
.type _Z8compararPfS_ii, @function
_Z8compararPfS_ii:
.LFB3672:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
imull %ecx, %edx
testl %edx, %edx
jle .L27
movslq %edx, %rdx
salq $2, %rdx
movl $0, %eax
.L33:
movss (%rdi,%rax), %xmm0
ucomiss (%rsi,%rax), %xmm0
jp .L37
jne .L37
addq $4, %rax
cmpq %rax, %rdx
jne .L33
jmp .L27
.L37:
movl $14, %edx
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L40
cmpb $0, 56(%rbx)
je .L31
movzbl 67(%rbx), %esi
.L32:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L27:
movl $11, %edx
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L41
cmpb $0, 56(%rbx)
je .L35
movzbl 67(%rbx), %esi
.L36:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L31:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L32
.L41:
call _ZSt16__throw_bad_castv@PLT
.L35:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L36
.cfi_endproc
.LFE3672:
.size _Z8compararPfS_ii, .-_Z8compararPfS_ii
.globl _Z36__device_stub__Z9multTiledPfS_S_iiiiPfS_S_iiii
.type _Z36__device_stub__Z9multTiledPfS_S_iiiiPfS_S_iiii, @function
_Z36__device_stub__Z9multTiledPfS_S_iiiiPfS_S_iiii:
.LFB3698:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L46
.L42:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L47
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9multTiledPfS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L42
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z36__device_stub__Z9multTiledPfS_S_iiiiPfS_S_iiii, .-_Z36__device_stub__Z9multTiledPfS_S_iiiiPfS_S_iiii
.globl _Z9multTiledPfS_S_iiii
.type _Z9multTiledPfS_S_iiii, @function
_Z9multTiledPfS_S_iiii:
.LFB3699:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z36__device_stub__Z9multTiledPfS_S_iiiiPfS_S_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z9multTiledPfS_S_iiii, .-_Z9multTiledPfS_S_iiii
.globl _Z43__device_stub__Z15matrixMulKernelPfS_S_iiiiPfS_S_iiii
.type _Z43__device_stub__Z15matrixMulKernelPfS_S_iiiiPfS_S_iiii, @function
_Z43__device_stub__Z15matrixMulKernelPfS_S_iiiiPfS_S_iiii:
.LFB3700:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L54
.L50:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L55
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15matrixMulKernelPfS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L50
.L55:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3700:
.size _Z43__device_stub__Z15matrixMulKernelPfS_S_iiiiPfS_S_iiii, .-_Z43__device_stub__Z15matrixMulKernelPfS_S_iiiiPfS_S_iiii
.globl _Z15matrixMulKernelPfS_S_iiii
.type _Z15matrixMulKernelPfS_S_iiii, @function
_Z15matrixMulKernelPfS_S_iiii:
.LFB3701:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z43__device_stub__Z15matrixMulKernelPfS_S_iiiiPfS_S_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _Z15matrixMulKernelPfS_S_iiii, .-_Z15matrixMulKernelPfS_S_iiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "Tiempo transcurrido Secuencial: %lf\n"
.align 8
.LC8:
.string "Tiempo transcurrido Paralelo SinTile: %lf\n"
.align 8
.LC9:
.string "Tiempo transcurrido Paralelo ConTile: %lf\n"
.text
.globl main
.type main, @function
main:
.LFB3673:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $524288, %edi
call malloc@PLT
movq %rax, %r12
movl $2097152, %edi
call malloc@PLT
movq %rax, %rbp
movl $262144, %edi
call malloc@PLT
movq %rax, %rbx
movl $262144, %edi
call malloc@PLT
movq %rax, %r13
movl $262144, %edi
call malloc@PLT
movq %rax, %r14
movl $1024, %edx
movl $128, %esi
movq %r12, %rdi
call _Z6llenarPfii
movl $512, %edx
movl $1024, %esi
movq %rbp, %rdi
call _Z6llenarPfii
call clock@PLT
movq %rax, %r15
subq $8, %rsp
.cfi_def_cfa_offset 136
pushq $512
.cfi_def_cfa_offset 144
movl $1024, %r9d
movl $1024, %r8d
movl $128, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq %r12, %rdi
call _Z7multMxNPfS_S_iiii
call clock@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
subq %r15, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC6(%rip), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $524288, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $2097152, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $524288, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $2097152, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 32(%rsp)
movl $32, 36(%rsp)
movl $1, 40(%rsp)
movl $4, 44(%rsp)
movl $4, 48(%rsp)
movl $1, 52(%rsp)
call clock@PLT
movq %rax, %r15
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L63
.L59:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $262144, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
call clock@PLT
subq %r15, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC6(%rip), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call clock@PLT
movq %rax, %r15
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L64
.L60:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $262144, %edx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
call clock@PLT
subq %r15, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC6(%rip), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $512, %ecx
movl $128, %edx
movq %r14, %rsi
movq %rbx, %rdi
call _Z8compararPfS_ii
movl $512, %ecx
movl $128, %edx
movq %r13, %rsi
movq %rbx, %rdi
call _Z8compararPfS_ii
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L65
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L63:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 136
pushq $512
.cfi_def_cfa_offset 144
movl $1024, %r9d
movl $1024, %r8d
movl $128, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z43__device_stub__Z15matrixMulKernelPfS_S_iiiiPfS_S_iiii
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L59
.L64:
subq $8, %rsp
.cfi_def_cfa_offset 136
pushq $512
.cfi_def_cfa_offset 144
movl $1024, %r9d
movl $1024, %r8d
movl $128, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z36__device_stub__Z9multTiledPfS_S_iiiiPfS_S_iiii
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L60
.L65:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3673:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z15matrixMulKernelPfS_S_iiii"
.LC11:
.string "_Z9multTiledPfS_S_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3703:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matrixMulKernelPfS_S_iiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z9multTiledPfS_S_iiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3703:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <stdio.h>
#include <stdlib.h>
#define TILE_WIDTH 32
using namespace std;
__global__ void multTiled(float *A, float *B, float *C,int rA,int cA,int rB,int cB){
__shared__ int Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ int Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * TILE_WIDTH + ty;
int col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
for(int k = 0; k < (cA+TILE_WIDTH-1)/(TILE_WIDTH); ++k){
if(k*TILE_WIDTH + tx < cA && row < rA){
Mds[ty][tx] = A[row*cA + k*TILE_WIDTH + tx];
}else{
Mds[ty][tx] = 0;
}
if(k*TILE_WIDTH + ty < cA && col < cB){
Nds[ty][tx] = B[(k*TILE_WIDTH + ty) * cB + col];
}else{
Nds[ty][tx] =0;
}
__syncthreads();
for(int k = 0; k < TILE_WIDTH; ++k){
Pvalue += Mds[ty][k] * Nds[k][tx];
}
__syncthreads();
}
if (row < rA && col < cB){
C[row*cB+col] = Pvalue;
}
}
__global__ void matrixMulKernel(float *d_A, float *d_B, float *d_C,int rA,int cA,int rB,int cB){
int row = blockIdx.y*blockDim.y+threadIdx.y;
int col = blockIdx.x*blockDim.x+threadIdx.x;
float Pvalue;
if((row < rA)&&(col < cB)){
Pvalue = 0;
for (int k = 0; k < rB ; ++k){
Pvalue += d_A[row*cA+k] * d_B[k*cB+col];
}
d_C[row*cB+col] = Pvalue;
}
}
void multMxN(float *A,float *B, float *C, int rA,int cA,int rB,int cB){
//El numero de col de A, debe ser igual al numero de row de B;
//Matriz C= FilasAxColumnasB
for(int i=0;i<rA;i++){
for(int j=0;j<cB;j++){
float value=0;
for(int k=0;k<rB;k++){
//h_c[n*i+j]+=h_a[n*i+k]*h_b[n*k+j];
value+=A[cA*i+k]*B[cB*k+j];
}
C[cB*i+j]=value;
}
}
}
void llenar(float *MA,int n,int m){
int tam=n*m;
for(int i = 0; i < tam; i++ )
MA[i] = 1.0;
}
void imprimir(float *MA,int n,int m){
int tam=n*m,cont=0;
for(int i = 0; i < tam; i++ ) {
printf("%f ",MA[i]);
if(cont==m-1){
printf("\n");
cont=-1;
}
cont++;
}
printf("\n");
}
void comparar(float *C1,float *C2,int rC,int cC){
int w=rC*cC;
for(int i=0;i<w;i++){
if(C1[i]!=C2[i]){
cout<<"No son iguales"<<endl;
break;
}
}
cout<<"Son iguales"<<endl;
}
int main(){
int rA=128;
int cA=1024;
int cB=512;
float blockSize = 4;
int rB=cA;
size_t bytesA=(rA*cA)*sizeof(float);
size_t bytesB=(rB*cB)*sizeof(float);
size_t bytesC=(rA*cB)*sizeof(float);
float *A=(float*)malloc(bytesA);
float *B=(float*)malloc(bytesB);
float *C1=(float*)malloc(bytesC);
float *C2=(float*)malloc(bytesC);
float *C3=(float*)malloc(bytesC);
//1.Lleno las matrices
llenar(A,rA,cA);
llenar(B,rB,cB);
//2.imprimo las matrices
//cout<<"Matriz A:"<<endl;
//imprimir(A,rA,cA);
//cout<<"Matriz B:"<<endl;
//imprimir(B,rB,cB);
//3.Multiplico matrices NxM Secuencial
clock_t start = clock();
multMxN(A,B,C1,rA,cA,rB,cB);
clock_t end= clock();
double elapsed_seconds=end-start;
printf("Tiempo transcurrido Secuencial: %lf\n", (elapsed_seconds / CLOCKS_PER_SEC));
//cout<<"Secuencial"<<endl;
//imprimir(C1,rA,cB);
//3.Multiplico matrices NxM Paralelo sin Tile
float *d_A;
float *d_B;
float *d_C;
// Allocate memory for each vector on GPU
cudaMalloc(&d_A,bytesA);
cudaMalloc(&d_B,bytesB);
cudaMalloc(&d_C,bytesC);
// Copy host vectors to device
cudaMemcpy( d_A, A, bytesA, cudaMemcpyHostToDevice);
cudaMemcpy( d_B, B, bytesB, cudaMemcpyHostToDevice);
//bloques
dim3 dimGrid(ceil(cB/blockSize),ceil(rA/blockSize),1);
//hilos
dim3 dimBlock(blockSize,blockSize,1);
//Tiempo de ejecucion Paralelo
clock_t start2 = clock();
// Execute the kernel
matrixMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C,rA,cA,rB,cB);
//multTiled<<<dimGrid, dimBlock>>>(d_A, d_B, d_C,rA,cA,rB,cB);
cudaDeviceSynchronize();
// Copy array back to host
cudaMemcpy( C2, d_C, bytesC, cudaMemcpyDeviceToHost );
clock_t end2= clock();
double elapsed_seconds2=end2-start2;
printf("Tiempo transcurrido Paralelo SinTile: %lf\n", (elapsed_seconds2 / CLOCKS_PER_SEC));
//4.Imprimo matriz C
//cout<<endl<<"Paralelo sin tiling"<<endl;
//imprimir(C2,rA,cB);
//cout<<"Matriz Secuencial-SinTiling: "<<endl;
//cout<<endl;
// Execute the kernel
//Tiempo de ejecucion Paralelo
clock_t start3 = clock();
multTiled<<<dimGrid, dimBlock>>>(d_A, d_B, d_C,rA,cA,rB,cB);
cudaDeviceSynchronize();
// Copy array back to host
cudaMemcpy( C3, d_C, bytesC, cudaMemcpyDeviceToHost );
clock_t end3= clock();
double elapsed_seconds3=end3-start3;
printf("Tiempo transcurrido Paralelo ConTile: %lf\n", (elapsed_seconds3 / CLOCKS_PER_SEC));
//4.Imprimo matriz C
//cout<<endl<<"Paralelo con tiling"<<endl;
//imprimir(C3,rA,cB);
// cout<<"Matriz Secuencial-Tiling: "<<endl;
comparar(C1,C3,rA,cB);
comparar(C1,C2,rA,cB);
// Release device memory
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
// Release host memory
free(A);
free(B);
free(C1);
free(C2);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <stdlib.h>
#define TILE_WIDTH 32
using namespace std;
__global__ void multTiled(float *A, float *B, float *C,int rA,int cA,int rB,int cB){
__shared__ int Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ int Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * TILE_WIDTH + ty;
int col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
for(int k = 0; k < (cA+TILE_WIDTH-1)/(TILE_WIDTH); ++k){
if(k*TILE_WIDTH + tx < cA && row < rA){
Mds[ty][tx] = A[row*cA + k*TILE_WIDTH + tx];
}else{
Mds[ty][tx] = 0;
}
if(k*TILE_WIDTH + ty < cA && col < cB){
Nds[ty][tx] = B[(k*TILE_WIDTH + ty) * cB + col];
}else{
Nds[ty][tx] =0;
}
__syncthreads();
for(int k = 0; k < TILE_WIDTH; ++k){
Pvalue += Mds[ty][k] * Nds[k][tx];
}
__syncthreads();
}
if (row < rA && col < cB){
C[row*cB+col] = Pvalue;
}
}
__global__ void matrixMulKernel(float *d_A, float *d_B, float *d_C,int rA,int cA,int rB,int cB){
int row = blockIdx.y*blockDim.y+threadIdx.y;
int col = blockIdx.x*blockDim.x+threadIdx.x;
float Pvalue;
if((row < rA)&&(col < cB)){
Pvalue = 0;
for (int k = 0; k < rB ; ++k){
Pvalue += d_A[row*cA+k] * d_B[k*cB+col];
}
d_C[row*cB+col] = Pvalue;
}
}
void multMxN(float *A,float *B, float *C, int rA,int cA,int rB,int cB){
//El numero de col de A, debe ser igual al numero de row de B;
//Matriz C= FilasAxColumnasB
for(int i=0;i<rA;i++){
for(int j=0;j<cB;j++){
float value=0;
for(int k=0;k<rB;k++){
//h_c[n*i+j]+=h_a[n*i+k]*h_b[n*k+j];
value+=A[cA*i+k]*B[cB*k+j];
}
C[cB*i+j]=value;
}
}
}
void llenar(float *MA,int n,int m){
int tam=n*m;
for(int i = 0; i < tam; i++ )
MA[i] = 1.0;
}
void imprimir(float *MA,int n,int m){
int tam=n*m,cont=0;
for(int i = 0; i < tam; i++ ) {
printf("%f ",MA[i]);
if(cont==m-1){
printf("\n");
cont=-1;
}
cont++;
}
printf("\n");
}
void comparar(float *C1,float *C2,int rC,int cC){
int w=rC*cC;
for(int i=0;i<w;i++){
if(C1[i]!=C2[i]){
cout<<"No son iguales"<<endl;
break;
}
}
cout<<"Son iguales"<<endl;
}
int main(){
int rA=128;
int cA=1024;
int cB=512;
float blockSize = 4;
int rB=cA;
size_t bytesA=(rA*cA)*sizeof(float);
size_t bytesB=(rB*cB)*sizeof(float);
size_t bytesC=(rA*cB)*sizeof(float);
float *A=(float*)malloc(bytesA);
float *B=(float*)malloc(bytesB);
float *C1=(float*)malloc(bytesC);
float *C2=(float*)malloc(bytesC);
float *C3=(float*)malloc(bytesC);
//1.Lleno las matrices
llenar(A,rA,cA);
llenar(B,rB,cB);
//2.imprimo las matrices
//cout<<"Matriz A:"<<endl;
//imprimir(A,rA,cA);
//cout<<"Matriz B:"<<endl;
//imprimir(B,rB,cB);
//3.Multiplico matrices NxM Secuencial
clock_t start = clock();
multMxN(A,B,C1,rA,cA,rB,cB);
clock_t end= clock();
double elapsed_seconds=end-start;
printf("Tiempo transcurrido Secuencial: %lf\n", (elapsed_seconds / CLOCKS_PER_SEC));
//cout<<"Secuencial"<<endl;
//imprimir(C1,rA,cB);
//3.Multiplico matrices NxM Paralelo sin Tile
float *d_A;
float *d_B;
float *d_C;
// Allocate memory for each vector on GPU
hipMalloc(&d_A,bytesA);
hipMalloc(&d_B,bytesB);
hipMalloc(&d_C,bytesC);
// Copy host vectors to device
hipMemcpy( d_A, A, bytesA, hipMemcpyHostToDevice);
hipMemcpy( d_B, B, bytesB, hipMemcpyHostToDevice);
//bloques
dim3 dimGrid(ceil(cB/blockSize),ceil(rA/blockSize),1);
//hilos
dim3 dimBlock(blockSize,blockSize,1);
//Tiempo de ejecucion Paralelo
clock_t start2 = clock();
// Execute the kernel
matrixMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C,rA,cA,rB,cB);
//multTiled<<<dimGrid, dimBlock>>>(d_A, d_B, d_C,rA,cA,rB,cB);
hipDeviceSynchronize();
// Copy array back to host
hipMemcpy( C2, d_C, bytesC, hipMemcpyDeviceToHost );
clock_t end2= clock();
double elapsed_seconds2=end2-start2;
printf("Tiempo transcurrido Paralelo SinTile: %lf\n", (elapsed_seconds2 / CLOCKS_PER_SEC));
//4.Imprimo matriz C
//cout<<endl<<"Paralelo sin tiling"<<endl;
//imprimir(C2,rA,cB);
//cout<<"Matriz Secuencial-SinTiling: "<<endl;
//cout<<endl;
// Execute the kernel
//Tiempo de ejecucion Paralelo
clock_t start3 = clock();
multTiled<<<dimGrid, dimBlock>>>(d_A, d_B, d_C,rA,cA,rB,cB);
hipDeviceSynchronize();
// Copy array back to host
hipMemcpy( C3, d_C, bytesC, hipMemcpyDeviceToHost );
clock_t end3= clock();
double elapsed_seconds3=end3-start3;
printf("Tiempo transcurrido Paralelo ConTile: %lf\n", (elapsed_seconds3 / CLOCKS_PER_SEC));
//4.Imprimo matriz C
//cout<<endl<<"Paralelo con tiling"<<endl;
//imprimir(C3,rA,cB);
// cout<<"Matriz Secuencial-Tiling: "<<endl;
comparar(C1,C3,rA,cB);
comparar(C1,C2,rA,cB);
// Release device memory
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
// Release host memory
free(A);
free(B);
free(C1);
free(C2);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <stdlib.h>
#define TILE_WIDTH 32
using namespace std;
__global__ void multTiled(float *A, float *B, float *C,int rA,int cA,int rB,int cB){
__shared__ int Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ int Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * TILE_WIDTH + ty;
int col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
for(int k = 0; k < (cA+TILE_WIDTH-1)/(TILE_WIDTH); ++k){
if(k*TILE_WIDTH + tx < cA && row < rA){
Mds[ty][tx] = A[row*cA + k*TILE_WIDTH + tx];
}else{
Mds[ty][tx] = 0;
}
if(k*TILE_WIDTH + ty < cA && col < cB){
Nds[ty][tx] = B[(k*TILE_WIDTH + ty) * cB + col];
}else{
Nds[ty][tx] =0;
}
__syncthreads();
for(int k = 0; k < TILE_WIDTH; ++k){
Pvalue += Mds[ty][k] * Nds[k][tx];
}
__syncthreads();
}
if (row < rA && col < cB){
C[row*cB+col] = Pvalue;
}
}
__global__ void matrixMulKernel(float *d_A, float *d_B, float *d_C,int rA,int cA,int rB,int cB){
int row = blockIdx.y*blockDim.y+threadIdx.y;
int col = blockIdx.x*blockDim.x+threadIdx.x;
float Pvalue;
if((row < rA)&&(col < cB)){
Pvalue = 0;
for (int k = 0; k < rB ; ++k){
Pvalue += d_A[row*cA+k] * d_B[k*cB+col];
}
d_C[row*cB+col] = Pvalue;
}
}
void multMxN(float *A,float *B, float *C, int rA,int cA,int rB,int cB){
//El numero de col de A, debe ser igual al numero de row de B;
//Matriz C= FilasAxColumnasB
for(int i=0;i<rA;i++){
for(int j=0;j<cB;j++){
float value=0;
for(int k=0;k<rB;k++){
//h_c[n*i+j]+=h_a[n*i+k]*h_b[n*k+j];
value+=A[cA*i+k]*B[cB*k+j];
}
C[cB*i+j]=value;
}
}
}
void llenar(float *MA,int n,int m){
int tam=n*m;
for(int i = 0; i < tam; i++ )
MA[i] = 1.0;
}
void imprimir(float *MA,int n,int m){
int tam=n*m,cont=0;
for(int i = 0; i < tam; i++ ) {
printf("%f ",MA[i]);
if(cont==m-1){
printf("\n");
cont=-1;
}
cont++;
}
printf("\n");
}
void comparar(float *C1,float *C2,int rC,int cC){
int w=rC*cC;
for(int i=0;i<w;i++){
if(C1[i]!=C2[i]){
cout<<"No son iguales"<<endl;
break;
}
}
cout<<"Son iguales"<<endl;
}
int main(){
int rA=128;
int cA=1024;
int cB=512;
float blockSize = 4;
int rB=cA;
size_t bytesA=(rA*cA)*sizeof(float);
size_t bytesB=(rB*cB)*sizeof(float);
size_t bytesC=(rA*cB)*sizeof(float);
float *A=(float*)malloc(bytesA);
float *B=(float*)malloc(bytesB);
float *C1=(float*)malloc(bytesC);
float *C2=(float*)malloc(bytesC);
float *C3=(float*)malloc(bytesC);
//1.Lleno las matrices
llenar(A,rA,cA);
llenar(B,rB,cB);
//2.imprimo las matrices
//cout<<"Matriz A:"<<endl;
//imprimir(A,rA,cA);
//cout<<"Matriz B:"<<endl;
//imprimir(B,rB,cB);
//3.Multiplico matrices NxM Secuencial
clock_t start = clock();
multMxN(A,B,C1,rA,cA,rB,cB);
clock_t end= clock();
double elapsed_seconds=end-start;
printf("Tiempo transcurrido Secuencial: %lf\n", (elapsed_seconds / CLOCKS_PER_SEC));
//cout<<"Secuencial"<<endl;
//imprimir(C1,rA,cB);
//3.Multiplico matrices NxM Paralelo sin Tile
float *d_A;
float *d_B;
float *d_C;
// Allocate memory for each vector on GPU
hipMalloc(&d_A,bytesA);
hipMalloc(&d_B,bytesB);
hipMalloc(&d_C,bytesC);
// Copy host vectors to device
hipMemcpy( d_A, A, bytesA, hipMemcpyHostToDevice);
hipMemcpy( d_B, B, bytesB, hipMemcpyHostToDevice);
//bloques
dim3 dimGrid(ceil(cB/blockSize),ceil(rA/blockSize),1);
//hilos
dim3 dimBlock(blockSize,blockSize,1);
//Tiempo de ejecucion Paralelo
clock_t start2 = clock();
// Execute the kernel
matrixMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C,rA,cA,rB,cB);
//multTiled<<<dimGrid, dimBlock>>>(d_A, d_B, d_C,rA,cA,rB,cB);
hipDeviceSynchronize();
// Copy array back to host
hipMemcpy( C2, d_C, bytesC, hipMemcpyDeviceToHost );
clock_t end2= clock();
double elapsed_seconds2=end2-start2;
printf("Tiempo transcurrido Paralelo SinTile: %lf\n", (elapsed_seconds2 / CLOCKS_PER_SEC));
//4.Imprimo matriz C
//cout<<endl<<"Paralelo sin tiling"<<endl;
//imprimir(C2,rA,cB);
//cout<<"Matriz Secuencial-SinTiling: "<<endl;
//cout<<endl;
// Execute the kernel
//Tiempo de ejecucion Paralelo
clock_t start3 = clock();
multTiled<<<dimGrid, dimBlock>>>(d_A, d_B, d_C,rA,cA,rB,cB);
hipDeviceSynchronize();
// Copy array back to host
hipMemcpy( C3, d_C, bytesC, hipMemcpyDeviceToHost );
clock_t end3= clock();
double elapsed_seconds3=end3-start3;
printf("Tiempo transcurrido Paralelo ConTile: %lf\n", (elapsed_seconds3 / CLOCKS_PER_SEC));
//4.Imprimo matriz C
//cout<<endl<<"Paralelo con tiling"<<endl;
//imprimir(C3,rA,cB);
// cout<<"Matriz Secuencial-Tiling: "<<endl;
comparar(C1,C3,rA,cB);
comparar(C1,C2,rA,cB);
// Release device memory
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
// Release host memory
free(A);
free(B);
free(C1);
free(C2);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9multTiledPfS_S_iiii
.globl _Z9multTiledPfS_S_iiii
.p2align 8
.type _Z9multTiledPfS_S_iiii,@function
_Z9multTiledPfS_S_iiii:
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x24
v_bfe_u32 v5, v0, 10, 10
v_and_b32_e32 v1, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v4, s15, 5, v5
v_lshl_add_u32 v0, s14, 5, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s8, v4
v_cmp_gt_i32_e64 s2, s3, v0
s_cmp_lt_i32 s9, 1
s_cbranch_scc1 .LBB0_13
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v1
v_lshlrev_b32_e32 v6, 7, v5
s_add_i32 s10, s9, 31
s_mov_b32 s11, 0
s_lshr_b32 s10, s10, 5
v_or_b32_e32 v7, 0x1000, v2
v_add_nc_u32_e32 v8, v6, v2
v_mad_u64_u32 v[2:3], null, v4, s9, v[1:2]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_4)
v_dual_mov_b32 v10, 0 :: v_dual_add_nc_u32 v9, v7, v6
s_max_i32 s10, s10, 1
s_xor_b32 s12, vcc_lo, -1
s_xor_b32 s2, s2, -1
.LBB0_2:
s_lshl_b32 s13, s11, 5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v11, s13, v1
v_cmp_le_i32_e32 vcc_lo, s9, v11
s_or_b32 s14, vcc_lo, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s15, s14
s_xor_b32 s14, exec_lo, s15
s_cbranch_execz .LBB0_4
ds_store_b32 v8, v10
.LBB0_4:
s_and_not1_saveexec_b32 s14, s14
s_cbranch_execz .LBB0_6
v_add_nc_u32_e32 v11, s13, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v11, vcc_lo, s4, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
global_load_b32 v11, v[11:12], off
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v11, v11
ds_store_b32 v8, v11
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s14
v_add_nc_u32_e32 v11, s13, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s9, v11
s_or_b32 s13, vcc_lo, s2
s_and_saveexec_b32 s14, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s13, exec_lo, s14
s_cbranch_execz .LBB0_8
ds_store_b32 v9, v10
.LBB0_8:
s_and_not1_saveexec_b32 s13, s13
s_cbranch_execz .LBB0_10
v_mad_u64_u32 v[12:13], null, v11, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[11:12], 2, v[12:13]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b32 v11, v[11:12], off
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v11, v11
ds_store_b32 v9, v11
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s13
v_mov_b32_e32 v11, v7
s_mov_b32 s13, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_11:
v_add_nc_u32_e32 v12, s13, v6
s_add_i32 s13, s13, 4
ds_load_b32 v13, v11
ds_load_b32 v12, v12
v_add_nc_u32_e32 v11, 0x80, v11
s_cmpk_eq_i32 s13, 0x80
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v12, v13, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v12, v12
v_add_f32_e32 v3, v3, v12
s_cbranch_scc0 .LBB0_11
s_add_i32 s11, s11, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s11, s10
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_14
.LBB0_13:
v_mov_b32_e32 v3, 0
.LBB0_14:
v_cmp_gt_i32_e32 vcc_lo, s8, v4
v_cmp_gt_i32_e64 s2, s3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_16
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[1:2], null, v4, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9multTiledPfS_S_iiii
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9multTiledPfS_S_iiii, .Lfunc_end0-_Z9multTiledPfS_S_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15matrixMulKernelPfS_S_iiii
.globl _Z15matrixMulKernelPfS_S_iiii
.p2align 8
.type _Z15matrixMulKernelPfS_S_iiii,@function
_Z15matrixMulKernelPfS_S_iiii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x24
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB1_6
s_load_b32 s2, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB1_4
s_clause 0x1
s_load_b32 s8, s[0:1], 0x1c
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v2, v0, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB1_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s2, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB1_3
s_branch .LBB1_5
.LBB1_4:
v_mov_b32_e32 v6, 0
.LBB1_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB1_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15matrixMulKernelPfS_S_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z15matrixMulKernelPfS_S_iiii, .Lfunc_end1-_Z15matrixMulKernelPfS_S_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9multTiledPfS_S_iiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9multTiledPfS_S_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15matrixMulKernelPfS_S_iiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15matrixMulKernelPfS_S_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <stdlib.h>
#define TILE_WIDTH 32
using namespace std;
__global__ void multTiled(float *A, float *B, float *C,int rA,int cA,int rB,int cB){
__shared__ int Mds[TILE_WIDTH][TILE_WIDTH];
__shared__ int Nds[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * TILE_WIDTH + ty;
int col = bx * TILE_WIDTH + tx;
float Pvalue = 0;
for(int k = 0; k < (cA+TILE_WIDTH-1)/(TILE_WIDTH); ++k){
if(k*TILE_WIDTH + tx < cA && row < rA){
Mds[ty][tx] = A[row*cA + k*TILE_WIDTH + tx];
}else{
Mds[ty][tx] = 0;
}
if(k*TILE_WIDTH + ty < cA && col < cB){
Nds[ty][tx] = B[(k*TILE_WIDTH + ty) * cB + col];
}else{
Nds[ty][tx] =0;
}
__syncthreads();
for(int k = 0; k < TILE_WIDTH; ++k){
Pvalue += Mds[ty][k] * Nds[k][tx];
}
__syncthreads();
}
if (row < rA && col < cB){
C[row*cB+col] = Pvalue;
}
}
__global__ void matrixMulKernel(float *d_A, float *d_B, float *d_C,int rA,int cA,int rB,int cB){
int row = blockIdx.y*blockDim.y+threadIdx.y;
int col = blockIdx.x*blockDim.x+threadIdx.x;
float Pvalue;
if((row < rA)&&(col < cB)){
Pvalue = 0;
for (int k = 0; k < rB ; ++k){
Pvalue += d_A[row*cA+k] * d_B[k*cB+col];
}
d_C[row*cB+col] = Pvalue;
}
}
void multMxN(float *A,float *B, float *C, int rA,int cA,int rB,int cB){
//El numero de col de A, debe ser igual al numero de row de B;
//Matriz C= FilasAxColumnasB
for(int i=0;i<rA;i++){
for(int j=0;j<cB;j++){
float value=0;
for(int k=0;k<rB;k++){
//h_c[n*i+j]+=h_a[n*i+k]*h_b[n*k+j];
value+=A[cA*i+k]*B[cB*k+j];
}
C[cB*i+j]=value;
}
}
}
void llenar(float *MA,int n,int m){
int tam=n*m;
for(int i = 0; i < tam; i++ )
MA[i] = 1.0;
}
void imprimir(float *MA,int n,int m){
int tam=n*m,cont=0;
for(int i = 0; i < tam; i++ ) {
printf("%f ",MA[i]);
if(cont==m-1){
printf("\n");
cont=-1;
}
cont++;
}
printf("\n");
}
void comparar(float *C1,float *C2,int rC,int cC){
int w=rC*cC;
for(int i=0;i<w;i++){
if(C1[i]!=C2[i]){
cout<<"No son iguales"<<endl;
break;
}
}
cout<<"Son iguales"<<endl;
}
int main(){
int rA=128;
int cA=1024;
int cB=512;
float blockSize = 4;
int rB=cA;
size_t bytesA=(rA*cA)*sizeof(float);
size_t bytesB=(rB*cB)*sizeof(float);
size_t bytesC=(rA*cB)*sizeof(float);
float *A=(float*)malloc(bytesA);
float *B=(float*)malloc(bytesB);
float *C1=(float*)malloc(bytesC);
float *C2=(float*)malloc(bytesC);
float *C3=(float*)malloc(bytesC);
//1.Lleno las matrices
llenar(A,rA,cA);
llenar(B,rB,cB);
//2.imprimo las matrices
//cout<<"Matriz A:"<<endl;
//imprimir(A,rA,cA);
//cout<<"Matriz B:"<<endl;
//imprimir(B,rB,cB);
//3.Multiplico matrices NxM Secuencial
clock_t start = clock();
multMxN(A,B,C1,rA,cA,rB,cB);
clock_t end= clock();
double elapsed_seconds=end-start;
printf("Tiempo transcurrido Secuencial: %lf\n", (elapsed_seconds / CLOCKS_PER_SEC));
//cout<<"Secuencial"<<endl;
//imprimir(C1,rA,cB);
//3.Multiplico matrices NxM Paralelo sin Tile
float *d_A;
float *d_B;
float *d_C;
// Allocate memory for each vector on GPU
hipMalloc(&d_A,bytesA);
hipMalloc(&d_B,bytesB);
hipMalloc(&d_C,bytesC);
// Copy host vectors to device
hipMemcpy( d_A, A, bytesA, hipMemcpyHostToDevice);
hipMemcpy( d_B, B, bytesB, hipMemcpyHostToDevice);
//bloques
dim3 dimGrid(ceil(cB/blockSize),ceil(rA/blockSize),1);
//hilos
dim3 dimBlock(blockSize,blockSize,1);
//Tiempo de ejecucion Paralelo
clock_t start2 = clock();
// Execute the kernel
matrixMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C,rA,cA,rB,cB);
//multTiled<<<dimGrid, dimBlock>>>(d_A, d_B, d_C,rA,cA,rB,cB);
hipDeviceSynchronize();
// Copy array back to host
hipMemcpy( C2, d_C, bytesC, hipMemcpyDeviceToHost );
clock_t end2= clock();
double elapsed_seconds2=end2-start2;
printf("Tiempo transcurrido Paralelo SinTile: %lf\n", (elapsed_seconds2 / CLOCKS_PER_SEC));
//4.Imprimo matriz C
//cout<<endl<<"Paralelo sin tiling"<<endl;
//imprimir(C2,rA,cB);
//cout<<"Matriz Secuencial-SinTiling: "<<endl;
//cout<<endl;
// Execute the kernel
//Tiempo de ejecucion Paralelo
clock_t start3 = clock();
multTiled<<<dimGrid, dimBlock>>>(d_A, d_B, d_C,rA,cA,rB,cB);
hipDeviceSynchronize();
// Copy array back to host
hipMemcpy( C3, d_C, bytesC, hipMemcpyDeviceToHost );
clock_t end3= clock();
double elapsed_seconds3=end3-start3;
printf("Tiempo transcurrido Paralelo ConTile: %lf\n", (elapsed_seconds3 / CLOCKS_PER_SEC));
//4.Imprimo matriz C
//cout<<endl<<"Paralelo con tiling"<<endl;
//imprimir(C3,rA,cB);
// cout<<"Matriz Secuencial-Tiling: "<<endl;
comparar(C1,C3,rA,cB);
comparar(C1,C2,rA,cB);
// Release device memory
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
// Release host memory
free(A);
free(B);
free(C1);
free(C2);
return 0;
} | .text
.file "multMatrixTileFloat.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__multTiledPfS_S_iiii # -- Begin function _Z24__device_stub__multTiledPfS_S_iiii
.p2align 4, 0x90
.type _Z24__device_stub__multTiledPfS_S_iiii,@function
_Z24__device_stub__multTiledPfS_S_iiii: # @_Z24__device_stub__multTiledPfS_S_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9multTiledPfS_S_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z24__device_stub__multTiledPfS_S_iiii, .Lfunc_end0-_Z24__device_stub__multTiledPfS_S_iiii
.cfi_endproc
# -- End function
.globl _Z30__device_stub__matrixMulKernelPfS_S_iiii # -- Begin function _Z30__device_stub__matrixMulKernelPfS_S_iiii
.p2align 4, 0x90
.type _Z30__device_stub__matrixMulKernelPfS_S_iiii,@function
_Z30__device_stub__matrixMulKernelPfS_S_iiii: # @_Z30__device_stub__matrixMulKernelPfS_S_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15matrixMulKernelPfS_S_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z30__device_stub__matrixMulKernelPfS_S_iiii, .Lfunc_end1-_Z30__device_stub__matrixMulKernelPfS_S_iiii
.cfi_endproc
# -- End function
.globl _Z7multMxNPfS_S_iiii # -- Begin function _Z7multMxNPfS_S_iiii
.p2align 4, 0x90
.type _Z7multMxNPfS_S_iiii,@function
_Z7multMxNPfS_S_iiii: # @_Z7multMxNPfS_S_iiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, -8(%rsp) # 8-byte Spill
testl %ecx, %ecx
jle .LBB2_9
# %bb.1: # %.preheader26.lr.ph
movq %rsi, %rdx
movslq 56(%rsp), %r10
movslq %r8d, %r8
movl %ecx, %ecx
movl %r10d, %r11d
movl %r9d, %ebx
shlq $2, %r8
leaq (,%r10,4), %r14
xorl %r15d, %r15d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_8: # %._crit_edge30
# in Loop: Header=BB2_2 Depth=1
incq %r15
addq %r8, %rdi
cmpq %rcx, %r15
je .LBB2_9
.LBB2_2: # %.preheader26
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
# Child Loop BB2_6 Depth 3
cmpl $0, 56(%rsp)
jle .LBB2_8
# %bb.3: # %.preheader.lr.ph
# in Loop: Header=BB2_2 Depth=1
movq %r15, %rax
imulq %r10, %rax
movq -8(%rsp), %rsi # 8-byte Reload
leaq (%rsi,%rax,4), %r12
movq %rdx, %rsi
xorl %ebp, %ebp
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_7: # %._crit_edge
# in Loop: Header=BB2_4 Depth=2
movss %xmm0, (%r12,%rbp,4)
incq %rbp
addq $4, %rsi
cmpq %r11, %rbp
je .LBB2_8
.LBB2_4: # %.preheader
# Parent Loop BB2_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_6 Depth 3
xorps %xmm0, %xmm0
testl %r9d, %r9d
jle .LBB2_7
# %bb.5: # %.lr.ph.preheader
# in Loop: Header=BB2_4 Depth=2
movq %rsi, %r13
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_6: # %.lr.ph
# Parent Loop BB2_2 Depth=1
# Parent Loop BB2_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rdi,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r13), %xmm1
addss %xmm1, %xmm0
incq %rax
addq %r14, %r13
cmpq %rax, %rbx
jne .LBB2_6
jmp .LBB2_7
.LBB2_9: # %._crit_edge32
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z7multMxNPfS_S_iiii, .Lfunc_end2-_Z7multMxNPfS_S_iiii
.cfi_endproc
# -- End function
.globl _Z6llenarPfii # -- Begin function _Z6llenarPfii
.p2align 4, 0x90
.type _Z6llenarPfii,@function
_Z6llenarPfii: # @_Z6llenarPfii
.cfi_startproc
# %bb.0:
imull %edx, %esi
testl %esi, %esi
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%rdi,%rcx,4) # imm = 0x3F800000
incq %rcx
cmpq %rcx, %rax
jne .LBB3_2
.LBB3_3: # %._crit_edge
retq
.Lfunc_end3:
.size _Z6llenarPfii, .Lfunc_end3-_Z6llenarPfii
.cfi_endproc
# -- End function
.globl _Z8imprimirPfii # -- Begin function _Z8imprimirPfii
.p2align 4, 0x90
.type _Z8imprimirPfii,@function
_Z8imprimirPfii: # @_Z8imprimirPfii
.cfi_startproc
# %bb.0:
imull %edx, %esi
testl %esi, %esi
jle .LBB4_6
# %bb.1: # %.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movq %rdi, %r14
decl %ebx
movl %esi, %r15d
xorl %r12d, %r12d
xorl %ebp, %ebp
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_4: # in Loop: Header=BB4_2 Depth=1
incl %ebp
incq %r12
cmpq %r12, %r15
je .LBB4_5
.LBB4_2: # =>This Inner Loop Header: Depth=1
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
cmpl %ebx, %ebp
jne .LBB4_4
# %bb.3: # in Loop: Header=BB4_2 Depth=1
movl $10, %edi
callq putchar@PLT
movl $-1, %ebp
jmp .LBB4_4
.LBB4_5:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB4_6: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end4:
.size _Z8imprimirPfii, .Lfunc_end4-_Z8imprimirPfii
.cfi_endproc
# -- End function
.globl _Z8compararPfS_ii # -- Begin function _Z8compararPfS_ii
.p2align 4, 0x90
.type _Z8compararPfS_ii,@function
_Z8compararPfS_ii: # @_Z8compararPfS_ii
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
imull %ecx, %edx
testl %edx, %edx
jle .LBB5_9
# %bb.1: # %.lr.ph.preheader
movl %edx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB5_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss (%rsi,%rcx,4), %xmm0
jne .LBB5_4
jp .LBB5_4
# %bb.2: # in Loop: Header=BB5_3 Depth=1
incq %rcx
cmpq %rcx, %rax
jne .LBB5_3
jmp .LBB5_9
.LBB5_4:
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB5_14
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB5_7
# %bb.6:
movzbl 67(%rbx), %eax
jmp .LBB5_8
.LBB5_7:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB5_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB5_9: # %.loopexit
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB5_14
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i9
cmpb $0, 56(%rbx)
je .LBB5_12
# %bb.11:
movzbl 67(%rbx), %eax
jmp .LBB5_13
.LBB5_12:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB5_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit12
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB5_14:
.cfi_def_cfa_offset 16
callq _ZSt16__throw_bad_castv
.Lfunc_end5:
.size _Z8compararPfS_ii, .Lfunc_end5-_Z8compararPfS_ii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI6_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $524288, %edi # imm = 0x80000
callq malloc
movq %rax, %rbx
movl $2097152, %edi # imm = 0x200000
callq malloc
movq %rax, %r14
movl $262144, %edi # imm = 0x40000
callq malloc
movq %rax, %r15
movl $262144, %edi # imm = 0x40000
callq malloc
movq %rax, %r12
movl $262144, %edi # imm = 0x40000
callq malloc
movq %rax, 176(%rsp) # 8-byte Spill
xorl %eax, %eax
.p2align 4, 0x90
.LBB6_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $131072, %rax # imm = 0x20000
jne .LBB6_1
# %bb.2: # %.lr.ph.i85.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB6_3: # %.lr.ph.i85
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%r14,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $524288, %rax # imm = 0x80000
jne .LBB6_3
# %bb.4: # %_Z6llenarPfii.exit89
movq %r12, 168(%rsp) # 8-byte Spill
xorl %ebp, %ebp
callq clock
movq %rax, %r13
movq %rbx, %rax
.p2align 4, 0x90
.LBB6_5: # %.preheader26.i
# =>This Loop Header: Depth=1
# Child Loop BB6_6 Depth 2
# Child Loop BB6_7 Depth 3
movq %rbp, %rcx
shlq $11, %rcx
addq %r15, %rcx
movq %r14, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB6_6: # %.preheader.i
# Parent Loop BB6_5 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_7 Depth 3
xorps %xmm0, %xmm0
movq %rdx, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB6_7: # %.lr.ph.i90
# Parent Loop BB6_5 Depth=1
# Parent Loop BB6_6 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rax,%r8,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rdi), %xmm1
addss %xmm1, %xmm0
incq %r8
addq $2048, %rdi # imm = 0x800
cmpq $1024, %r8 # imm = 0x400
jne .LBB6_7
# %bb.8: # %._crit_edge.i
# in Loop: Header=BB6_6 Depth=2
movss %xmm0, (%rcx,%rsi,4)
incq %rsi
addq $4, %rdx
cmpq $512, %rsi # imm = 0x200
jne .LBB6_6
# %bb.9: # %._crit_edge30.i
# in Loop: Header=BB6_5 Depth=1
incq %rbp
addq $4096, %rax # imm = 0x1000
cmpq $128, %rbp
jne .LBB6_5
# %bb.10: # %_Z7multMxNPfS_S_iiii.exit
movabsq $137438953600, %r12 # imm = 0x2000000080
movabsq $17179869188, %rbp # imm = 0x400000004
callq clock
subq %r13, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI6_0(%rip), %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
leaq 32(%rsp), %rdi
movl $524288, %esi # imm = 0x80000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $2097152, %esi # imm = 0x200000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
movq 32(%rsp), %rdi
movl $524288, %edx # imm = 0x80000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $2097152, %edx # imm = 0x200000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
callq clock
movq %rax, %r13
movq %r12, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_12
# %bb.11:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $128, 12(%rsp)
movl $1024, 8(%rsp) # imm = 0x400
movl $1024, 4(%rsp) # imm = 0x400
movl $512, (%rsp) # imm = 0x200
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15matrixMulKernelPfS_S_iiii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_12:
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
movl $262144, %edx # imm = 0x40000
movq 168(%rsp), %r12 # 8-byte Reload
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
callq clock
subq %r13, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI6_0(%rip), %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
callq clock
movq %rax, %r13
movabsq $137438953600, %rdi # imm = 0x2000000080
movl $1, %esi
movabsq $17179869188, %rdx # imm = 0x400000004
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_14
# %bb.13:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $128, 12(%rsp)
movl $1024, 8(%rsp) # imm = 0x400
movl $1024, 4(%rsp) # imm = 0x400
movl $512, (%rsp) # imm = 0x200
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9multTiledPfS_S_iiii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_14:
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
movl $262144, %edx # imm = 0x40000
movq 176(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdi
movl $2, %ecx
callq hipMemcpy
callq clock
subq %r13, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI6_0(%rip), %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movq %r15, %rdi
movq %rbp, %rsi
movl $128, %edx
movl $512, %ecx # imm = 0x200
callq _Z8compararPfS_ii
movq %r15, %rdi
movq %r12, %rsi
movl $128, %edx
movl $512, %ecx # imm = 0x200
callq _Z8compararPfS_ii
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9multTiledPfS_S_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matrixMulKernelPfS_S_iiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9multTiledPfS_S_iiii,@object # @_Z9multTiledPfS_S_iiii
.section .rodata,"a",@progbits
.globl _Z9multTiledPfS_S_iiii
.p2align 3, 0x0
_Z9multTiledPfS_S_iiii:
.quad _Z24__device_stub__multTiledPfS_S_iiii
.size _Z9multTiledPfS_S_iiii, 8
.type _Z15matrixMulKernelPfS_S_iiii,@object # @_Z15matrixMulKernelPfS_S_iiii
.globl _Z15matrixMulKernelPfS_S_iiii
.p2align 3, 0x0
_Z15matrixMulKernelPfS_S_iiii:
.quad _Z30__device_stub__matrixMulKernelPfS_S_iiii
.size _Z15matrixMulKernelPfS_S_iiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "No son iguales"
.size .L.str.2, 15
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Son iguales"
.size .L.str.3, 12
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Tiempo transcurrido Secuencial: %lf\n"
.size .L.str.4, 37
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Tiempo transcurrido Paralelo SinTile: %lf\n"
.size .L.str.5, 43
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Tiempo transcurrido Paralelo ConTile: %lf\n"
.size .L.str.6, 43
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9multTiledPfS_S_iiii"
.size .L__unnamed_1, 23
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15matrixMulKernelPfS_S_iiii"
.size .L__unnamed_2, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__multTiledPfS_S_iiii
.addrsig_sym _Z30__device_stub__matrixMulKernelPfS_S_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9multTiledPfS_S_iiii
.addrsig_sym _Z15matrixMulKernelPfS_S_iiii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00106981_00000000-6_multMatrixTileFloat.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3676:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3676:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7multMxNPfS_S_iiii
.type _Z7multMxNPfS_S_iiii, @function
_Z7multMxNPfS_S_iiii:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rsi, -24(%rsp)
movq %rdx, -16(%rsp)
movl %ecx, -28(%rsp)
movl 56(%rsp), %r14d
testl %ecx, %ecx
jle .L3
movq %rdi, %rbx
movl %r9d, %r11d
movslq %r14d, %rbp
leaq 0(,%rbp,4), %rsi
movl $0, %r13d
movl $0, %r12d
movl $0, %edx
movslq %r9d, %rax
movq %rax, -8(%rsp)
movl %r8d, %ecx
jmp .L5
.L6:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
addss %xmm0, %xmm1
addq $4, %rax
addq %rsi, %rdx
cmpq %rdi, %rax
jne .L6
.L8:
movss %xmm1, (%r10,%r8,4)
addq $1, %r8
addq $4, %r9
cmpq %r8, %rbp
je .L13
.L9:
movq %r9, %rdx
movq %r15, %rax
pxor %xmm1, %xmm1
testl %r11d, %r11d
jg .L6
jmp .L8
.L13:
movl -32(%rsp), %edx
.L7:
addl $1, %edx
addl %r14d, %r12d
addl %ecx, %r13d
cmpl %edx, -28(%rsp)
je .L3
.L5:
testl %r14d, %r14d
jle .L7
movq -24(%rsp), %r9
movslq %r13d, %rax
leaq (%rbx,%rax,4), %r15
movq -8(%rsp), %rdi
addq %rdi, %rax
leaq (%rbx,%rax,4), %rdi
movslq %r12d, %rax
movq -16(%rsp), %r10
leaq (%r10,%rax,4), %r10
movl $0, %r8d
movl %edx, -32(%rsp)
jmp .L9
.L3:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size _Z7multMxNPfS_S_iiii, .-_Z7multMxNPfS_S_iiii
.globl _Z6llenarPfii
.type _Z6llenarPfii, @function
_Z6llenarPfii:
.LFB3670:
.cfi_startproc
endbr64
imull %edx, %esi
testl %esi, %esi
jle .L16
movq %rdi, %rax
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rdx
movss .LC1(%rip), %xmm0
.L18:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L18
.L16:
ret
.cfi_endproc
.LFE3670:
.size _Z6llenarPfii, .-_Z6llenarPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%f "
.LC3:
.string "\n"
.text
.globl _Z8imprimirPfii
.type _Z8imprimirPfii, @function
_Z8imprimirPfii:
.LFB3671:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
imull %edx, %esi
testl %esi, %esi
jle .L21
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %r14
movl $0, %ebp
leaq .LC2(%rip), %r13
leal -1(%rdx), %r12d
leaq .LC3(%rip), %r15
jmp .L23
.L22:
addl $1, %ebp
addq $4, %rbx
cmpq %r14, %rbx
je .L21
.L23:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpl %ebp, %r12d
jne .L22
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %ebp
jmp .L22
.L21:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3671:
.size _Z8imprimirPfii, .-_Z8imprimirPfii
.section .rodata.str1.1
.LC4:
.string "No son iguales"
.LC5:
.string "Son iguales"
.text
.globl _Z8compararPfS_ii
.type _Z8compararPfS_ii, @function
_Z8compararPfS_ii:
.LFB3672:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
imull %ecx, %edx
testl %edx, %edx
jle .L27
movslq %edx, %rdx
salq $2, %rdx
movl $0, %eax
.L33:
movss (%rdi,%rax), %xmm0
ucomiss (%rsi,%rax), %xmm0
jp .L37
jne .L37
addq $4, %rax
cmpq %rax, %rdx
jne .L33
jmp .L27
.L37:
movl $14, %edx
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L40
cmpb $0, 56(%rbx)
je .L31
movzbl 67(%rbx), %esi
.L32:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L27:
movl $11, %edx
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L41
cmpb $0, 56(%rbx)
je .L35
movzbl 67(%rbx), %esi
.L36:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L31:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L32
.L41:
call _ZSt16__throw_bad_castv@PLT
.L35:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L36
.cfi_endproc
.LFE3672:
.size _Z8compararPfS_ii, .-_Z8compararPfS_ii
.globl _Z36__device_stub__Z9multTiledPfS_S_iiiiPfS_S_iiii
.type _Z36__device_stub__Z9multTiledPfS_S_iiiiPfS_S_iiii, @function
_Z36__device_stub__Z9multTiledPfS_S_iiiiPfS_S_iiii:
.LFB3698:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L46
.L42:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L47
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9multTiledPfS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L42
.L47:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z36__device_stub__Z9multTiledPfS_S_iiiiPfS_S_iiii, .-_Z36__device_stub__Z9multTiledPfS_S_iiiiPfS_S_iiii
.globl _Z9multTiledPfS_S_iiii
.type _Z9multTiledPfS_S_iiii, @function
_Z9multTiledPfS_S_iiii:
.LFB3699:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z36__device_stub__Z9multTiledPfS_S_iiiiPfS_S_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z9multTiledPfS_S_iiii, .-_Z9multTiledPfS_S_iiii
.globl _Z43__device_stub__Z15matrixMulKernelPfS_S_iiiiPfS_S_iiii
.type _Z43__device_stub__Z15matrixMulKernelPfS_S_iiiiPfS_S_iiii, @function
_Z43__device_stub__Z15matrixMulKernelPfS_S_iiiiPfS_S_iiii:
.LFB3700:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L54
.L50:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L55
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15matrixMulKernelPfS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L50
.L55:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3700:
.size _Z43__device_stub__Z15matrixMulKernelPfS_S_iiiiPfS_S_iiii, .-_Z43__device_stub__Z15matrixMulKernelPfS_S_iiiiPfS_S_iiii
.globl _Z15matrixMulKernelPfS_S_iiii
.type _Z15matrixMulKernelPfS_S_iiii, @function
_Z15matrixMulKernelPfS_S_iiii:
.LFB3701:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z43__device_stub__Z15matrixMulKernelPfS_S_iiiiPfS_S_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _Z15matrixMulKernelPfS_S_iiii, .-_Z15matrixMulKernelPfS_S_iiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "Tiempo transcurrido Secuencial: %lf\n"
.align 8
.LC8:
.string "Tiempo transcurrido Paralelo SinTile: %lf\n"
.align 8
.LC9:
.string "Tiempo transcurrido Paralelo ConTile: %lf\n"
.text
.globl main
.type main, @function
main:
.LFB3673:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $524288, %edi
call malloc@PLT
movq %rax, %r12
movl $2097152, %edi
call malloc@PLT
movq %rax, %rbp
movl $262144, %edi
call malloc@PLT
movq %rax, %rbx
movl $262144, %edi
call malloc@PLT
movq %rax, %r13
movl $262144, %edi
call malloc@PLT
movq %rax, %r14
movl $1024, %edx
movl $128, %esi
movq %r12, %rdi
call _Z6llenarPfii
movl $512, %edx
movl $1024, %esi
movq %rbp, %rdi
call _Z6llenarPfii
call clock@PLT
movq %rax, %r15
subq $8, %rsp
.cfi_def_cfa_offset 136
pushq $512
.cfi_def_cfa_offset 144
movl $1024, %r9d
movl $1024, %r8d
movl $128, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq %r12, %rdi
call _Z7multMxNPfS_S_iiii
call clock@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
subq %r15, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC6(%rip), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $524288, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $2097152, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $524288, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $2097152, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 32(%rsp)
movl $32, 36(%rsp)
movl $1, 40(%rsp)
movl $4, 44(%rsp)
movl $4, 48(%rsp)
movl $1, 52(%rsp)
call clock@PLT
movq %rax, %r15
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L63
.L59:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $262144, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
call clock@PLT
subq %r15, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC6(%rip), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call clock@PLT
movq %rax, %r15
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L64
.L60:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $262144, %edx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
call clock@PLT
subq %r15, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC6(%rip), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $512, %ecx
movl $128, %edx
movq %r14, %rsi
movq %rbx, %rdi
call _Z8compararPfS_ii
movl $512, %ecx
movl $128, %edx
movq %r13, %rsi
movq %rbx, %rdi
call _Z8compararPfS_ii
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L65
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L63:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 136
pushq $512
.cfi_def_cfa_offset 144
movl $1024, %r9d
movl $1024, %r8d
movl $128, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z43__device_stub__Z15matrixMulKernelPfS_S_iiiiPfS_S_iiii
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L59
.L64:
subq $8, %rsp
.cfi_def_cfa_offset 136
pushq $512
.cfi_def_cfa_offset 144
movl $1024, %r9d
movl $1024, %r8d
movl $128, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z36__device_stub__Z9multTiledPfS_S_iiiiPfS_S_iiii
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L60
.L65:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3673:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z15matrixMulKernelPfS_S_iiii"
.LC11:
.string "_Z9multTiledPfS_S_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3703:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matrixMulKernelPfS_S_iiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z9multTiledPfS_S_iiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3703:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "multMatrixTileFloat.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__multTiledPfS_S_iiii # -- Begin function _Z24__device_stub__multTiledPfS_S_iiii
.p2align 4, 0x90
.type _Z24__device_stub__multTiledPfS_S_iiii,@function
_Z24__device_stub__multTiledPfS_S_iiii: # @_Z24__device_stub__multTiledPfS_S_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9multTiledPfS_S_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z24__device_stub__multTiledPfS_S_iiii, .Lfunc_end0-_Z24__device_stub__multTiledPfS_S_iiii
.cfi_endproc
# -- End function
.globl _Z30__device_stub__matrixMulKernelPfS_S_iiii # -- Begin function _Z30__device_stub__matrixMulKernelPfS_S_iiii
.p2align 4, 0x90
.type _Z30__device_stub__matrixMulKernelPfS_S_iiii,@function
_Z30__device_stub__matrixMulKernelPfS_S_iiii: # @_Z30__device_stub__matrixMulKernelPfS_S_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15matrixMulKernelPfS_S_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z30__device_stub__matrixMulKernelPfS_S_iiii, .Lfunc_end1-_Z30__device_stub__matrixMulKernelPfS_S_iiii
.cfi_endproc
# -- End function
.globl _Z7multMxNPfS_S_iiii # -- Begin function _Z7multMxNPfS_S_iiii
.p2align 4, 0x90
.type _Z7multMxNPfS_S_iiii,@function
_Z7multMxNPfS_S_iiii: # @_Z7multMxNPfS_S_iiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, -8(%rsp) # 8-byte Spill
testl %ecx, %ecx
jle .LBB2_9
# %bb.1: # %.preheader26.lr.ph
movq %rsi, %rdx
movslq 56(%rsp), %r10
movslq %r8d, %r8
movl %ecx, %ecx
movl %r10d, %r11d
movl %r9d, %ebx
shlq $2, %r8
leaq (,%r10,4), %r14
xorl %r15d, %r15d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_8: # %._crit_edge30
# in Loop: Header=BB2_2 Depth=1
incq %r15
addq %r8, %rdi
cmpq %rcx, %r15
je .LBB2_9
.LBB2_2: # %.preheader26
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
# Child Loop BB2_6 Depth 3
cmpl $0, 56(%rsp)
jle .LBB2_8
# %bb.3: # %.preheader.lr.ph
# in Loop: Header=BB2_2 Depth=1
movq %r15, %rax
imulq %r10, %rax
movq -8(%rsp), %rsi # 8-byte Reload
leaq (%rsi,%rax,4), %r12
movq %rdx, %rsi
xorl %ebp, %ebp
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_7: # %._crit_edge
# in Loop: Header=BB2_4 Depth=2
movss %xmm0, (%r12,%rbp,4)
incq %rbp
addq $4, %rsi
cmpq %r11, %rbp
je .LBB2_8
.LBB2_4: # %.preheader
# Parent Loop BB2_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_6 Depth 3
xorps %xmm0, %xmm0
testl %r9d, %r9d
jle .LBB2_7
# %bb.5: # %.lr.ph.preheader
# in Loop: Header=BB2_4 Depth=2
movq %rsi, %r13
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_6: # %.lr.ph
# Parent Loop BB2_2 Depth=1
# Parent Loop BB2_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rdi,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r13), %xmm1
addss %xmm1, %xmm0
incq %rax
addq %r14, %r13
cmpq %rax, %rbx
jne .LBB2_6
jmp .LBB2_7
.LBB2_9: # %._crit_edge32
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z7multMxNPfS_S_iiii, .Lfunc_end2-_Z7multMxNPfS_S_iiii
.cfi_endproc
# -- End function
.globl _Z6llenarPfii # -- Begin function _Z6llenarPfii
.p2align 4, 0x90
.type _Z6llenarPfii,@function
_Z6llenarPfii: # @_Z6llenarPfii
.cfi_startproc
# %bb.0:
imull %edx, %esi
testl %esi, %esi
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%rdi,%rcx,4) # imm = 0x3F800000
incq %rcx
cmpq %rcx, %rax
jne .LBB3_2
.LBB3_3: # %._crit_edge
retq
.Lfunc_end3:
.size _Z6llenarPfii, .Lfunc_end3-_Z6llenarPfii
.cfi_endproc
# -- End function
.globl _Z8imprimirPfii # -- Begin function _Z8imprimirPfii
.p2align 4, 0x90
.type _Z8imprimirPfii,@function
_Z8imprimirPfii: # @_Z8imprimirPfii
.cfi_startproc
# %bb.0:
imull %edx, %esi
testl %esi, %esi
jle .LBB4_6
# %bb.1: # %.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movq %rdi, %r14
decl %ebx
movl %esi, %r15d
xorl %r12d, %r12d
xorl %ebp, %ebp
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_4: # in Loop: Header=BB4_2 Depth=1
incl %ebp
incq %r12
cmpq %r12, %r15
je .LBB4_5
.LBB4_2: # =>This Inner Loop Header: Depth=1
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
cmpl %ebx, %ebp
jne .LBB4_4
# %bb.3: # in Loop: Header=BB4_2 Depth=1
movl $10, %edi
callq putchar@PLT
movl $-1, %ebp
jmp .LBB4_4
.LBB4_5:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB4_6: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end4:
.size _Z8imprimirPfii, .Lfunc_end4-_Z8imprimirPfii
.cfi_endproc
# -- End function
.globl _Z8compararPfS_ii # -- Begin function _Z8compararPfS_ii
.p2align 4, 0x90
.type _Z8compararPfS_ii,@function
_Z8compararPfS_ii: # @_Z8compararPfS_ii
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
imull %ecx, %edx
testl %edx, %edx
jle .LBB5_9
# %bb.1: # %.lr.ph.preheader
movl %edx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB5_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rdi,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss (%rsi,%rcx,4), %xmm0
jne .LBB5_4
jp .LBB5_4
# %bb.2: # in Loop: Header=BB5_3 Depth=1
incq %rcx
cmpq %rcx, %rax
jne .LBB5_3
jmp .LBB5_9
.LBB5_4:
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB5_14
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB5_7
# %bb.6:
movzbl 67(%rbx), %eax
jmp .LBB5_8
.LBB5_7:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB5_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB5_9: # %.loopexit
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB5_14
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i9
cmpb $0, 56(%rbx)
je .LBB5_12
# %bb.11:
movzbl 67(%rbx), %eax
jmp .LBB5_13
.LBB5_12:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB5_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit12
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB5_14:
.cfi_def_cfa_offset 16
callq _ZSt16__throw_bad_castv
.Lfunc_end5:
.size _Z8compararPfS_ii, .Lfunc_end5-_Z8compararPfS_ii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI6_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $524288, %edi # imm = 0x80000
callq malloc
movq %rax, %rbx
movl $2097152, %edi # imm = 0x200000
callq malloc
movq %rax, %r14
movl $262144, %edi # imm = 0x40000
callq malloc
movq %rax, %r15
movl $262144, %edi # imm = 0x40000
callq malloc
movq %rax, %r12
movl $262144, %edi # imm = 0x40000
callq malloc
movq %rax, 176(%rsp) # 8-byte Spill
xorl %eax, %eax
.p2align 4, 0x90
.LBB6_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $131072, %rax # imm = 0x20000
jne .LBB6_1
# %bb.2: # %.lr.ph.i85.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB6_3: # %.lr.ph.i85
# =>This Inner Loop Header: Depth=1
movl $1065353216, (%r14,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $524288, %rax # imm = 0x80000
jne .LBB6_3
# %bb.4: # %_Z6llenarPfii.exit89
movq %r12, 168(%rsp) # 8-byte Spill
xorl %ebp, %ebp
callq clock
movq %rax, %r13
movq %rbx, %rax
.p2align 4, 0x90
.LBB6_5: # %.preheader26.i
# =>This Loop Header: Depth=1
# Child Loop BB6_6 Depth 2
# Child Loop BB6_7 Depth 3
movq %rbp, %rcx
shlq $11, %rcx
addq %r15, %rcx
movq %r14, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB6_6: # %.preheader.i
# Parent Loop BB6_5 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB6_7 Depth 3
xorps %xmm0, %xmm0
movq %rdx, %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB6_7: # %.lr.ph.i90
# Parent Loop BB6_5 Depth=1
# Parent Loop BB6_6 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rax,%r8,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rdi), %xmm1
addss %xmm1, %xmm0
incq %r8
addq $2048, %rdi # imm = 0x800
cmpq $1024, %r8 # imm = 0x400
jne .LBB6_7
# %bb.8: # %._crit_edge.i
# in Loop: Header=BB6_6 Depth=2
movss %xmm0, (%rcx,%rsi,4)
incq %rsi
addq $4, %rdx
cmpq $512, %rsi # imm = 0x200
jne .LBB6_6
# %bb.9: # %._crit_edge30.i
# in Loop: Header=BB6_5 Depth=1
incq %rbp
addq $4096, %rax # imm = 0x1000
cmpq $128, %rbp
jne .LBB6_5
# %bb.10: # %_Z7multMxNPfS_S_iiii.exit
movabsq $137438953600, %r12 # imm = 0x2000000080
movabsq $17179869188, %rbp # imm = 0x400000004
callq clock
subq %r13, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI6_0(%rip), %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
leaq 32(%rsp), %rdi
movl $524288, %esi # imm = 0x80000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $2097152, %esi # imm = 0x200000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
movq 32(%rsp), %rdi
movl $524288, %edx # imm = 0x80000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $2097152, %edx # imm = 0x200000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
callq clock
movq %rax, %r13
movq %r12, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_12
# %bb.11:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $128, 12(%rsp)
movl $1024, 8(%rsp) # imm = 0x400
movl $1024, 4(%rsp) # imm = 0x400
movl $512, (%rsp) # imm = 0x200
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z15matrixMulKernelPfS_S_iiii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_12:
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
movl $262144, %edx # imm = 0x40000
movq 168(%rsp), %r12 # 8-byte Reload
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
callq clock
subq %r13, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI6_0(%rip), %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
callq clock
movq %rax, %r13
movabsq $137438953600, %rdi # imm = 0x2000000080
movl $1, %esi
movabsq $17179869188, %rdx # imm = 0x400000004
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_14
# %bb.13:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $128, 12(%rsp)
movl $1024, 8(%rsp) # imm = 0x400
movl $1024, 4(%rsp) # imm = 0x400
movl $512, (%rsp) # imm = 0x200
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9multTiledPfS_S_iiii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_14:
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
movl $262144, %edx # imm = 0x40000
movq 176(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdi
movl $2, %ecx
callq hipMemcpy
callq clock
subq %r13, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI6_0(%rip), %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
movq %r15, %rdi
movq %rbp, %rsi
movl $128, %edx
movl $512, %ecx # imm = 0x200
callq _Z8compararPfS_ii
movq %r15, %rdi
movq %r12, %rsi
movl $128, %edx
movl $512, %ecx # imm = 0x200
callq _Z8compararPfS_ii
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9multTiledPfS_S_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matrixMulKernelPfS_S_iiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9multTiledPfS_S_iiii,@object # @_Z9multTiledPfS_S_iiii
.section .rodata,"a",@progbits
.globl _Z9multTiledPfS_S_iiii
.p2align 3, 0x0
_Z9multTiledPfS_S_iiii:
.quad _Z24__device_stub__multTiledPfS_S_iiii
.size _Z9multTiledPfS_S_iiii, 8
.type _Z15matrixMulKernelPfS_S_iiii,@object # @_Z15matrixMulKernelPfS_S_iiii
.globl _Z15matrixMulKernelPfS_S_iiii
.p2align 3, 0x0
_Z15matrixMulKernelPfS_S_iiii:
.quad _Z30__device_stub__matrixMulKernelPfS_S_iiii
.size _Z15matrixMulKernelPfS_S_iiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "No son iguales"
.size .L.str.2, 15
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Son iguales"
.size .L.str.3, 12
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Tiempo transcurrido Secuencial: %lf\n"
.size .L.str.4, 37
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Tiempo transcurrido Paralelo SinTile: %lf\n"
.size .L.str.5, 43
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Tiempo transcurrido Paralelo ConTile: %lf\n"
.size .L.str.6, 43
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9multTiledPfS_S_iiii"
.size .L__unnamed_1, 23
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15matrixMulKernelPfS_S_iiii"
.size .L__unnamed_2, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__multTiledPfS_S_iiii
.addrsig_sym _Z30__device_stub__matrixMulKernelPfS_S_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9multTiledPfS_S_iiii
.addrsig_sym _Z15matrixMulKernelPfS_S_iiii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdlib.h>
#include <stdio.h>
__global__ void map_kernel(int *g_data) {
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
g_data[idx] = g_data[idx] * g_data[idx];
}
__global__ void reduce_kernel(int *g_input, int *g_output) {
extern __shared__ int s_data[]; // allocated at kernel launch
// read input into shared memory
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
s_data[threadIdx.x] = g_input[idx];
__syncthreads();
// compute sum for the thread block
for (int dist = blockDim.x / 2; dist > 0; dist /= 2) {
if (threadIdx.x < dist)
s_data[threadIdx.x] += s_data[threadIdx.x + dist];
__syncthreads();
}
// write the block's sum to global memory
if (threadIdx.x == 0)
g_output[blockIdx.x] = s_data[0];
}
int main(int argc, char *argv[]) {
// data set size in elements and bytes
if (argc < 2) {
fprintf(stderr, "Usage: %s <num>\n", argv[1]);
exit(1);
}
unsigned int n = atoi(argv[1]);
unsigned int block_dim = 256;
unsigned int nblocks = (n + block_dim - 1) / block_dim;
unsigned int nbytes = block_dim * nblocks * sizeof(int);
unsigned int smem_bytes = block_dim * sizeof(int);
// allocate and initialize the data on the CPU
int *h_a = (int *)malloc(nbytes);
for (int i = 0; i < n; i++)
h_a[i] = i + 1;
// allocate memory on the GPU device
int *d_a = 0, *d_out = 0;
cudaMalloc((void **)&d_a, nbytes);
cudaMalloc((void **)&d_out, nblocks * sizeof(int));
// copy the input data from CPU to the GPU device
cudaMemcpy(d_a, h_a, nbytes, cudaMemcpyHostToDevice);
/*
* <<< Dg, Db, Ns >>>
* Dg :: dim3 dimension and size of grid
* Db :: dim3 dimension and size of each block
* Ns :: size_t number of bytes in shared memory that dynamically allocated
* per block
*/
map_kernel<<<nblocks, block_dim>>>(d_a);
// two stages of kernel execution
reduce_kernel<<<nblocks, block_dim, smem_bytes>>>(d_a, d_out);
reduce_kernel<<<1, nblocks, nblocks * sizeof(int)>>>(d_out, d_out);
// copy the output from GPU device to CPU and print
cudaMemcpy(h_a, d_out, sizeof(int), cudaMemcpyDeviceToHost);
printf("%d\n", h_a[0]);
// release resources
cudaFree(d_a);
cudaFree(d_out);
free(h_a);
return 0;
} | code for sm_80
Function : _Z13reduce_kernelPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R6, c[0x0][0x0], R7 ; /* 0x0000000006027a24 */
/* 0x001fca00078e0207 */
/*0060*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0003 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0090*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00a0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00b0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*00c0*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x0041e80000004800 */
/*00d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00e0*/ @!P1 BRA 0x1b0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.SHL.U32 R0, R7, 0x4, RZ ; /* 0x0000000407007824 */
/* 0x001fe200078e00ff */
/*0100*/ MOV R3, UR4 ; /* 0x0000000400037c02 */
/* 0x000fc80008000f00 */
/*0110*/ ISETP.GE.U32.AND P1, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f26070 */
/*0120*/ @!P1 IMAD R2, R3, 0x4, R0 ; /* 0x0000000403029824 */
/* 0x000fe200078e0200 */
/*0130*/ @!P1 LDS R4, [R7.X4] ; /* 0x0000000007049984 */
/* 0x000fe20000004800 */
/*0140*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*0150*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0160*/ @!P1 IADD3 R4, R4, R5, RZ ; /* 0x0000000504049210 */
/* 0x001fca0007ffe0ff */
/*0170*/ @!P1 STS [R7.X4], R4 ; /* 0x0000000407009388 */
/* 0x0001e80000004800 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0190*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*01a0*/ @P1 BRA 0x110 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*01b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*01c0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*01d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*01e0*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fca00078e0003 */
/*01f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10map_kernelPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0005 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0080*/ IMAD R5, R0, R0, RZ ; /* 0x0000000000057224 */
/* 0x004fca00078e02ff */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdlib.h>
#include <stdio.h>
__global__ void map_kernel(int *g_data) {
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
g_data[idx] = g_data[idx] * g_data[idx];
}
__global__ void reduce_kernel(int *g_input, int *g_output) {
extern __shared__ int s_data[]; // allocated at kernel launch
// read input into shared memory
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
s_data[threadIdx.x] = g_input[idx];
__syncthreads();
// compute sum for the thread block
for (int dist = blockDim.x / 2; dist > 0; dist /= 2) {
if (threadIdx.x < dist)
s_data[threadIdx.x] += s_data[threadIdx.x + dist];
__syncthreads();
}
// write the block's sum to global memory
if (threadIdx.x == 0)
g_output[blockIdx.x] = s_data[0];
}
int main(int argc, char *argv[]) {
// data set size in elements and bytes
if (argc < 2) {
fprintf(stderr, "Usage: %s <num>\n", argv[1]);
exit(1);
}
unsigned int n = atoi(argv[1]);
unsigned int block_dim = 256;
unsigned int nblocks = (n + block_dim - 1) / block_dim;
unsigned int nbytes = block_dim * nblocks * sizeof(int);
unsigned int smem_bytes = block_dim * sizeof(int);
// allocate and initialize the data on the CPU
int *h_a = (int *)malloc(nbytes);
for (int i = 0; i < n; i++)
h_a[i] = i + 1;
// allocate memory on the GPU device
int *d_a = 0, *d_out = 0;
cudaMalloc((void **)&d_a, nbytes);
cudaMalloc((void **)&d_out, nblocks * sizeof(int));
// copy the input data from CPU to the GPU device
cudaMemcpy(d_a, h_a, nbytes, cudaMemcpyHostToDevice);
/*
* <<< Dg, Db, Ns >>>
* Dg :: dim3 dimension and size of grid
* Db :: dim3 dimension and size of each block
* Ns :: size_t number of bytes in shared memory that dynamically allocated
* per block
*/
map_kernel<<<nblocks, block_dim>>>(d_a);
// two stages of kernel execution
reduce_kernel<<<nblocks, block_dim, smem_bytes>>>(d_a, d_out);
reduce_kernel<<<1, nblocks, nblocks * sizeof(int)>>>(d_out, d_out);
// copy the output from GPU device to CPU and print
cudaMemcpy(h_a, d_out, sizeof(int), cudaMemcpyDeviceToHost);
printf("%d\n", h_a[0]);
// release resources
cudaFree(d_a);
cudaFree(d_out);
free(h_a);
return 0;
} | .file "tmpxft_001497dd_00000000-6_mapreduce.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z10map_kernelPiPi
.type _Z30__device_stub__Z10map_kernelPiPi, @function
_Z30__device_stub__Z10map_kernelPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10map_kernelPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z10map_kernelPiPi, .-_Z30__device_stub__Z10map_kernelPiPi
.globl _Z10map_kernelPi
.type _Z10map_kernelPi, @function
_Z10map_kernelPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10map_kernelPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10map_kernelPi, .-_Z10map_kernelPi
.globl _Z35__device_stub__Z13reduce_kernelPiS_PiS_
.type _Z35__device_stub__Z13reduce_kernelPiS_PiS_, @function
_Z35__device_stub__Z13reduce_kernelPiS_PiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13reduce_kernelPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z35__device_stub__Z13reduce_kernelPiS_PiS_, .-_Z35__device_stub__Z13reduce_kernelPiS_PiS_
.globl _Z13reduce_kernelPiS_
.type _Z13reduce_kernelPiS_, @function
_Z13reduce_kernelPiS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13reduce_kernelPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z13reduce_kernelPiS_, .-_Z13reduce_kernelPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Usage: %s <num>\n"
.LC1:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jle .L29
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
leal 255(%rax), %eax
movl %eax, %r12d
shrl $8, %r12d
leaq 0(,%rax,4), %rbp
andl $4294966272, %ebp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
testl %r13d, %r13d
je .L21
leal -1(%r13), %edx
addq $2, %rdx
movl $1, %eax
.L22:
movl %eax, -4(%rbx,%rax,4)
addq $1, %rax
cmpq %rdx, %rax
jne .L22
.L21:
movq $0, (%rsp)
movq $0, 8(%rsp)
movq %rsp, %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %r12d, %r13d
salq $2, %r13
leaq 8(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %r12d, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L23:
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %r12d, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $1024, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L24:
movl %r12d, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movq %r13, %r8
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L25:
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl (%rbx), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movq 8(%rsi), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L30:
movq (%rsp), %rdi
call _Z30__device_stub__Z10map_kernelPiPi
jmp .L23
.L31:
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z35__device_stub__Z13reduce_kernelPiS_PiS_
jmp .L24
.L32:
movq 8(%rsp), %rdi
movq %rdi, %rsi
call _Z35__device_stub__Z13reduce_kernelPiS_PiS_
jmp .L25
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z13reduce_kernelPiS_"
.LC3:
.string "_Z10map_kernelPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z13reduce_kernelPiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10map_kernelPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdlib.h>
#include <stdio.h>
__global__ void map_kernel(int *g_data) {
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
g_data[idx] = g_data[idx] * g_data[idx];
}
__global__ void reduce_kernel(int *g_input, int *g_output) {
extern __shared__ int s_data[]; // allocated at kernel launch
// read input into shared memory
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
s_data[threadIdx.x] = g_input[idx];
__syncthreads();
// compute sum for the thread block
for (int dist = blockDim.x / 2; dist > 0; dist /= 2) {
if (threadIdx.x < dist)
s_data[threadIdx.x] += s_data[threadIdx.x + dist];
__syncthreads();
}
// write the block's sum to global memory
if (threadIdx.x == 0)
g_output[blockIdx.x] = s_data[0];
}
int main(int argc, char *argv[]) {
// data set size in elements and bytes
if (argc < 2) {
fprintf(stderr, "Usage: %s <num>\n", argv[1]);
exit(1);
}
unsigned int n = atoi(argv[1]);
unsigned int block_dim = 256;
unsigned int nblocks = (n + block_dim - 1) / block_dim;
unsigned int nbytes = block_dim * nblocks * sizeof(int);
unsigned int smem_bytes = block_dim * sizeof(int);
// allocate and initialize the data on the CPU
int *h_a = (int *)malloc(nbytes);
for (int i = 0; i < n; i++)
h_a[i] = i + 1;
// allocate memory on the GPU device
int *d_a = 0, *d_out = 0;
cudaMalloc((void **)&d_a, nbytes);
cudaMalloc((void **)&d_out, nblocks * sizeof(int));
// copy the input data from CPU to the GPU device
cudaMemcpy(d_a, h_a, nbytes, cudaMemcpyHostToDevice);
/*
* <<< Dg, Db, Ns >>>
* Dg :: dim3 dimension and size of grid
* Db :: dim3 dimension and size of each block
* Ns :: size_t number of bytes in shared memory that dynamically allocated
* per block
*/
map_kernel<<<nblocks, block_dim>>>(d_a);
// two stages of kernel execution
reduce_kernel<<<nblocks, block_dim, smem_bytes>>>(d_a, d_out);
reduce_kernel<<<1, nblocks, nblocks * sizeof(int)>>>(d_out, d_out);
// copy the output from GPU device to CPU and print
cudaMemcpy(h_a, d_out, sizeof(int), cudaMemcpyDeviceToHost);
printf("%d\n", h_a[0]);
// release resources
cudaFree(d_a);
cudaFree(d_out);
free(h_a);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
__global__ void map_kernel(int *g_data) {
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
g_data[idx] = g_data[idx] * g_data[idx];
}
__global__ void reduce_kernel(int *g_input, int *g_output) {
extern __shared__ int s_data[]; // allocated at kernel launch
// read input into shared memory
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
s_data[threadIdx.x] = g_input[idx];
__syncthreads();
// compute sum for the thread block
for (int dist = blockDim.x / 2; dist > 0; dist /= 2) {
if (threadIdx.x < dist)
s_data[threadIdx.x] += s_data[threadIdx.x + dist];
__syncthreads();
}
// write the block's sum to global memory
if (threadIdx.x == 0)
g_output[blockIdx.x] = s_data[0];
}
int main(int argc, char *argv[]) {
// data set size in elements and bytes
if (argc < 2) {
fprintf(stderr, "Usage: %s <num>\n", argv[1]);
exit(1);
}
unsigned int n = atoi(argv[1]);
unsigned int block_dim = 256;
unsigned int nblocks = (n + block_dim - 1) / block_dim;
unsigned int nbytes = block_dim * nblocks * sizeof(int);
unsigned int smem_bytes = block_dim * sizeof(int);
// allocate and initialize the data on the CPU
int *h_a = (int *)malloc(nbytes);
for (int i = 0; i < n; i++)
h_a[i] = i + 1;
// allocate memory on the GPU device
int *d_a = 0, *d_out = 0;
hipMalloc((void **)&d_a, nbytes);
hipMalloc((void **)&d_out, nblocks * sizeof(int));
// copy the input data from CPU to the GPU device
hipMemcpy(d_a, h_a, nbytes, hipMemcpyHostToDevice);
/*
* <<< Dg, Db, Ns >>>
* Dg :: dim3 dimension and size of grid
* Db :: dim3 dimension and size of each block
* Ns :: size_t number of bytes in shared memory that dynamically allocated
* per block
*/
map_kernel<<<nblocks, block_dim>>>(d_a);
// two stages of kernel execution
reduce_kernel<<<nblocks, block_dim, smem_bytes>>>(d_a, d_out);
reduce_kernel<<<1, nblocks, nblocks * sizeof(int)>>>(d_out, d_out);
// copy the output from GPU device to CPU and print
hipMemcpy(h_a, d_out, sizeof(int), hipMemcpyDeviceToHost);
printf("%d\n", h_a[0]);
// release resources
hipFree(d_a);
hipFree(d_out);
free(h_a);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
__global__ void map_kernel(int *g_data) {
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
g_data[idx] = g_data[idx] * g_data[idx];
}
__global__ void reduce_kernel(int *g_input, int *g_output) {
extern __shared__ int s_data[]; // allocated at kernel launch
// read input into shared memory
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
s_data[threadIdx.x] = g_input[idx];
__syncthreads();
// compute sum for the thread block
for (int dist = blockDim.x / 2; dist > 0; dist /= 2) {
if (threadIdx.x < dist)
s_data[threadIdx.x] += s_data[threadIdx.x + dist];
__syncthreads();
}
// write the block's sum to global memory
if (threadIdx.x == 0)
g_output[blockIdx.x] = s_data[0];
}
int main(int argc, char *argv[]) {
// data set size in elements and bytes
if (argc < 2) {
fprintf(stderr, "Usage: %s <num>\n", argv[1]);
exit(1);
}
unsigned int n = atoi(argv[1]);
unsigned int block_dim = 256;
unsigned int nblocks = (n + block_dim - 1) / block_dim;
unsigned int nbytes = block_dim * nblocks * sizeof(int);
unsigned int smem_bytes = block_dim * sizeof(int);
// allocate and initialize the data on the CPU
int *h_a = (int *)malloc(nbytes);
for (int i = 0; i < n; i++)
h_a[i] = i + 1;
// allocate memory on the GPU device
int *d_a = 0, *d_out = 0;
hipMalloc((void **)&d_a, nbytes);
hipMalloc((void **)&d_out, nblocks * sizeof(int));
// copy the input data from CPU to the GPU device
hipMemcpy(d_a, h_a, nbytes, hipMemcpyHostToDevice);
/*
* <<< Dg, Db, Ns >>>
* Dg :: dim3 dimension and size of grid
* Db :: dim3 dimension and size of each block
* Ns :: size_t number of bytes in shared memory that dynamically allocated
* per block
*/
map_kernel<<<nblocks, block_dim>>>(d_a);
// two stages of kernel execution
reduce_kernel<<<nblocks, block_dim, smem_bytes>>>(d_a, d_out);
reduce_kernel<<<1, nblocks, nblocks * sizeof(int)>>>(d_out, d_out);
// copy the output from GPU device to CPU and print
hipMemcpy(h_a, d_out, sizeof(int), hipMemcpyDeviceToHost);
printf("%d\n", h_a[0]);
// release resources
hipFree(d_a);
hipFree(d_out);
free(h_a);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10map_kernelPi
.globl _Z10map_kernelPi
.p2align 8
.type _Z10map_kernelPi,@function
_Z10map_kernelPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v2, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10map_kernelPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10map_kernelPi, .Lfunc_end0-_Z10map_kernelPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13reduce_kernelPiS_
.globl _Z13reduce_kernelPiS_
.p2align 8
.type _Z13reduce_kernelPiS_,@function
_Z13reduce_kernelPiS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, 0
s_cmp_lt_u32 s3, 2
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB1_2
.p2align 6
.LBB1_1:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
.LBB1_2:
buffer_gl0_inv
s_cbranch_scc1 .LBB1_5
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB1_1
v_add_nc_u32_e32 v2, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB1_1
.LBB1_5:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_7
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB1_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13reduce_kernelPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13reduce_kernelPiS_, .Lfunc_end1-_Z13reduce_kernelPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10map_kernelPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10map_kernelPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13reduce_kernelPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13reduce_kernelPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
__global__ void map_kernel(int *g_data) {
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
g_data[idx] = g_data[idx] * g_data[idx];
}
__global__ void reduce_kernel(int *g_input, int *g_output) {
extern __shared__ int s_data[]; // allocated at kernel launch
// read input into shared memory
unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
s_data[threadIdx.x] = g_input[idx];
__syncthreads();
// compute sum for the thread block
for (int dist = blockDim.x / 2; dist > 0; dist /= 2) {
if (threadIdx.x < dist)
s_data[threadIdx.x] += s_data[threadIdx.x + dist];
__syncthreads();
}
// write the block's sum to global memory
if (threadIdx.x == 0)
g_output[blockIdx.x] = s_data[0];
}
int main(int argc, char *argv[]) {
// data set size in elements and bytes
if (argc < 2) {
fprintf(stderr, "Usage: %s <num>\n", argv[1]);
exit(1);
}
unsigned int n = atoi(argv[1]);
unsigned int block_dim = 256;
unsigned int nblocks = (n + block_dim - 1) / block_dim;
unsigned int nbytes = block_dim * nblocks * sizeof(int);
unsigned int smem_bytes = block_dim * sizeof(int);
// allocate and initialize the data on the CPU
int *h_a = (int *)malloc(nbytes);
for (int i = 0; i < n; i++)
h_a[i] = i + 1;
// allocate memory on the GPU device
int *d_a = 0, *d_out = 0;
hipMalloc((void **)&d_a, nbytes);
hipMalloc((void **)&d_out, nblocks * sizeof(int));
// copy the input data from CPU to the GPU device
hipMemcpy(d_a, h_a, nbytes, hipMemcpyHostToDevice);
/*
* <<< Dg, Db, Ns >>>
* Dg :: dim3 dimension and size of grid
* Db :: dim3 dimension and size of each block
* Ns :: size_t number of bytes in shared memory that dynamically allocated
* per block
*/
map_kernel<<<nblocks, block_dim>>>(d_a);
// two stages of kernel execution
reduce_kernel<<<nblocks, block_dim, smem_bytes>>>(d_a, d_out);
reduce_kernel<<<1, nblocks, nblocks * sizeof(int)>>>(d_out, d_out);
// copy the output from GPU device to CPU and print
hipMemcpy(h_a, d_out, sizeof(int), hipMemcpyDeviceToHost);
printf("%d\n", h_a[0]);
// release resources
hipFree(d_a);
hipFree(d_out);
free(h_a);
return 0;
} | .text
.file "mapreduce.hip"
.globl _Z25__device_stub__map_kernelPi # -- Begin function _Z25__device_stub__map_kernelPi
.p2align 4, 0x90
.type _Z25__device_stub__map_kernelPi,@function
_Z25__device_stub__map_kernelPi: # @_Z25__device_stub__map_kernelPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10map_kernelPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z25__device_stub__map_kernelPi, .Lfunc_end0-_Z25__device_stub__map_kernelPi
.cfi_endproc
# -- End function
.globl _Z28__device_stub__reduce_kernelPiS_ # -- Begin function _Z28__device_stub__reduce_kernelPiS_
.p2align 4, 0x90
.type _Z28__device_stub__reduce_kernelPiS_,@function
_Z28__device_stub__reduce_kernelPiS_: # @_Z28__device_stub__reduce_kernelPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13reduce_kernelPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z28__device_stub__reduce_kernelPiS_, .Lfunc_end1-_Z28__device_stub__reduce_kernelPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
cmpl $1, %edi
jle .LBB2_11
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
leal 255(%rax), %r13d
shrl $8, %r13d
leal 1020(,%rax,4), %r12d
andl $-1024, %r12d # imm = 0xFC00
movq %r12, %rdi
callq malloc
movq %rax, %rbx
testl %r14d, %r14d
je .LBB2_4
# %bb.2: # %.lr.ph.preheader
movl %r14d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leaq 1(%rcx), %rdx
movl %edx, (%rbx,%rcx,4)
movq %rdx, %rcx
cmpq %rdx, %rax
jne .LBB2_3
.LBB2_4: # %._crit_edge
movabsq $4294967552, %r14 # imm = 0x100000100
movq $0, 24(%rsp)
movq $0, 16(%rsp)
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leal (,%r13,4), %r15d
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r13d, %eax
leaq (%rax,%r14), %r12
addq $-256, %r12
movq %r12, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 24(%rsp), %rax
movq %rax, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 80(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10map_kernelPi, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movl $1024, %r8d # imm = 0x400
movq %r12, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 48(%rsp), %rax
movq %rax, 88(%rsp)
leaq 32(%rsp), %rdi
leaq 64(%rsp), %rsi
movq %rsp, %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13reduce_kernelPiS_, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
addq $-255, %r14
movq %r14, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
movq %r15, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
movq 16(%rsp), %rax
movq %rax, 56(%rsp)
movq %rax, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 48(%rsp), %rax
movq %rax, 88(%rsp)
leaq 32(%rsp), %rdi
leaq 64(%rsp), %rsi
movq %rsp, %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13reduce_kernelPiS_, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_10:
movq 16(%rsp), %rsi
movl $4, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl (%rbx), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_11:
.cfi_def_cfa_offset 160
movq stderr(%rip), %rdi
movq 8(%rsi), %rdx
movl $.L.str, %esi
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10map_kernelPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13reduce_kernelPiS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10map_kernelPi,@object # @_Z10map_kernelPi
.section .rodata,"a",@progbits
.globl _Z10map_kernelPi
.p2align 3, 0x0
_Z10map_kernelPi:
.quad _Z25__device_stub__map_kernelPi
.size _Z10map_kernelPi, 8
.type _Z13reduce_kernelPiS_,@object # @_Z13reduce_kernelPiS_
.globl _Z13reduce_kernelPiS_
.p2align 3, 0x0
_Z13reduce_kernelPiS_:
.quad _Z28__device_stub__reduce_kernelPiS_
.size _Z13reduce_kernelPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Usage: %s <num>\n"
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d\n"
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10map_kernelPi"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13reduce_kernelPiS_"
.size .L__unnamed_2, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__map_kernelPi
.addrsig_sym _Z28__device_stub__reduce_kernelPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10map_kernelPi
.addrsig_sym _Z13reduce_kernelPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13reduce_kernelPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R6, c[0x0][0x0], R7 ; /* 0x0000000006027a24 */
/* 0x001fca00078e0207 */
/*0060*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0003 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0090*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00a0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00b0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*00c0*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x0041e80000004800 */
/*00d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*00e0*/ @!P1 BRA 0x1b0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.SHL.U32 R0, R7, 0x4, RZ ; /* 0x0000000407007824 */
/* 0x001fe200078e00ff */
/*0100*/ MOV R3, UR4 ; /* 0x0000000400037c02 */
/* 0x000fc80008000f00 */
/*0110*/ ISETP.GE.U32.AND P1, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f26070 */
/*0120*/ @!P1 IMAD R2, R3, 0x4, R0 ; /* 0x0000000403029824 */
/* 0x000fe200078e0200 */
/*0130*/ @!P1 LDS R4, [R7.X4] ; /* 0x0000000007049984 */
/* 0x000fe20000004800 */
/*0140*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*0150*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0160*/ @!P1 IADD3 R4, R4, R5, RZ ; /* 0x0000000504049210 */
/* 0x001fca0007ffe0ff */
/*0170*/ @!P1 STS [R7.X4], R4 ; /* 0x0000000407009388 */
/* 0x0001e80000004800 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0190*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*01a0*/ @P1 BRA 0x110 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*01b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*01c0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*01d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*01e0*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fca00078e0003 */
/*01f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10map_kernelPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0005 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0080*/ IMAD R5, R0, R0, RZ ; /* 0x0000000000057224 */
/* 0x004fca00078e02ff */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10map_kernelPi
.globl _Z10map_kernelPi
.p2align 8
.type _Z10map_kernelPi,@function
_Z10map_kernelPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v2, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10map_kernelPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10map_kernelPi, .Lfunc_end0-_Z10map_kernelPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13reduce_kernelPiS_
.globl _Z13reduce_kernelPiS_
.p2align 8
.type _Z13reduce_kernelPiS_,@function
_Z13reduce_kernelPiS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, 0
s_cmp_lt_u32 s3, 2
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshl_add_u32 v1, v0, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB1_2
.p2align 6
.LBB1_1:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
.LBB1_2:
buffer_gl0_inv
s_cbranch_scc1 .LBB1_5
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB1_1
v_add_nc_u32_e32 v2, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB1_1
.LBB1_5:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_7
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB1_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13reduce_kernelPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13reduce_kernelPiS_, .Lfunc_end1-_Z13reduce_kernelPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10map_kernelPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10map_kernelPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13reduce_kernelPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13reduce_kernelPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001497dd_00000000-6_mapreduce.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z10map_kernelPiPi
.type _Z30__device_stub__Z10map_kernelPiPi, @function
_Z30__device_stub__Z10map_kernelPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10map_kernelPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z10map_kernelPiPi, .-_Z30__device_stub__Z10map_kernelPiPi
.globl _Z10map_kernelPi
.type _Z10map_kernelPi, @function
_Z10map_kernelPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z10map_kernelPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10map_kernelPi, .-_Z10map_kernelPi
.globl _Z35__device_stub__Z13reduce_kernelPiS_PiS_
.type _Z35__device_stub__Z13reduce_kernelPiS_PiS_, @function
_Z35__device_stub__Z13reduce_kernelPiS_PiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13reduce_kernelPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z35__device_stub__Z13reduce_kernelPiS_PiS_, .-_Z35__device_stub__Z13reduce_kernelPiS_PiS_
.globl _Z13reduce_kernelPiS_
.type _Z13reduce_kernelPiS_, @function
_Z13reduce_kernelPiS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13reduce_kernelPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z13reduce_kernelPiS_, .-_Z13reduce_kernelPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Usage: %s <num>\n"
.LC1:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jle .L29
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
leal 255(%rax), %eax
movl %eax, %r12d
shrl $8, %r12d
leaq 0(,%rax,4), %rbp
andl $4294966272, %ebp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
testl %r13d, %r13d
je .L21
leal -1(%r13), %edx
addq $2, %rdx
movl $1, %eax
.L22:
movl %eax, -4(%rbx,%rax,4)
addq $1, %rax
cmpq %rdx, %rax
jne .L22
.L21:
movq $0, (%rsp)
movq $0, 8(%rsp)
movq %rsp, %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %r12d, %r13d
salq $2, %r13
leaq 8(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %r12d, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L23:
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %r12d, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $1024, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L24:
movl %r12d, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movq %r13, %r8
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L25:
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl (%rbx), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movq 8(%rsi), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L30:
movq (%rsp), %rdi
call _Z30__device_stub__Z10map_kernelPiPi
jmp .L23
.L31:
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z35__device_stub__Z13reduce_kernelPiS_PiS_
jmp .L24
.L32:
movq 8(%rsp), %rdi
movq %rdi, %rsi
call _Z35__device_stub__Z13reduce_kernelPiS_PiS_
jmp .L25
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z13reduce_kernelPiS_"
.LC3:
.string "_Z10map_kernelPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z13reduce_kernelPiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10map_kernelPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mapreduce.hip"
.globl _Z25__device_stub__map_kernelPi # -- Begin function _Z25__device_stub__map_kernelPi
.p2align 4, 0x90
.type _Z25__device_stub__map_kernelPi,@function
_Z25__device_stub__map_kernelPi: # @_Z25__device_stub__map_kernelPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10map_kernelPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z25__device_stub__map_kernelPi, .Lfunc_end0-_Z25__device_stub__map_kernelPi
.cfi_endproc
# -- End function
.globl _Z28__device_stub__reduce_kernelPiS_ # -- Begin function _Z28__device_stub__reduce_kernelPiS_
.p2align 4, 0x90
.type _Z28__device_stub__reduce_kernelPiS_,@function
_Z28__device_stub__reduce_kernelPiS_: # @_Z28__device_stub__reduce_kernelPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13reduce_kernelPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z28__device_stub__reduce_kernelPiS_, .Lfunc_end1-_Z28__device_stub__reduce_kernelPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
cmpl $1, %edi
jle .LBB2_11
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
leal 255(%rax), %r13d
shrl $8, %r13d
leal 1020(,%rax,4), %r12d
andl $-1024, %r12d # imm = 0xFC00
movq %r12, %rdi
callq malloc
movq %rax, %rbx
testl %r14d, %r14d
je .LBB2_4
# %bb.2: # %.lr.ph.preheader
movl %r14d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leaq 1(%rcx), %rdx
movl %edx, (%rbx,%rcx,4)
movq %rdx, %rcx
cmpq %rdx, %rax
jne .LBB2_3
.LBB2_4: # %._crit_edge
movabsq $4294967552, %r14 # imm = 0x100000100
movq $0, 24(%rsp)
movq $0, 16(%rsp)
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leal (,%r13,4), %r15d
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r13d, %eax
leaq (%rax,%r14), %r12
addq $-256, %r12
movq %r12, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 24(%rsp), %rax
movq %rax, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 80(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10map_kernelPi, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movl $1024, %r8d # imm = 0x400
movq %r12, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 48(%rsp), %rax
movq %rax, 88(%rsp)
leaq 32(%rsp), %rdi
leaq 64(%rsp), %rsi
movq %rsp, %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13reduce_kernelPiS_, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
addq $-255, %r14
movq %r14, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
movq %r15, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_10
# %bb.9:
movq 16(%rsp), %rax
movq %rax, 56(%rsp)
movq %rax, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 48(%rsp), %rax
movq %rax, 88(%rsp)
leaq 32(%rsp), %rdi
leaq 64(%rsp), %rsi
movq %rsp, %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13reduce_kernelPiS_, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_10:
movq 16(%rsp), %rsi
movl $4, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl (%rbx), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_11:
.cfi_def_cfa_offset 160
movq stderr(%rip), %rdi
movq 8(%rsi), %rdx
movl $.L.str, %esi
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10map_kernelPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13reduce_kernelPiS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10map_kernelPi,@object # @_Z10map_kernelPi
.section .rodata,"a",@progbits
.globl _Z10map_kernelPi
.p2align 3, 0x0
_Z10map_kernelPi:
.quad _Z25__device_stub__map_kernelPi
.size _Z10map_kernelPi, 8
.type _Z13reduce_kernelPiS_,@object # @_Z13reduce_kernelPiS_
.globl _Z13reduce_kernelPiS_
.p2align 3, 0x0
_Z13reduce_kernelPiS_:
.quad _Z28__device_stub__reduce_kernelPiS_
.size _Z13reduce_kernelPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Usage: %s <num>\n"
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d\n"
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10map_kernelPi"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13reduce_kernelPiS_"
.size .L__unnamed_2, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__map_kernelPi
.addrsig_sym _Z28__device_stub__reduce_kernelPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10map_kernelPi
.addrsig_sym _Z13reduce_kernelPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda_runtime_api.h>
#include "device_launch_parameters.h"
#define N 10
#define M 5
__global__ void add(int *a, int *b, int *c)
{
int tid = blockIdx.x * blockDim.x+threadIdx.x;
c[tid] = a[tid] + b[tid];
}
__host__ int main(void)
{
int a[N*M], b[N*M], c[N*M];
for (int i = 0; i<N*M; i++)
{
a[i] = -i;
b[i] = i * i;
}
int* devA;
int* devB;
int* devC;
cudaMalloc((void**)&devA, sizeof(int) * N*M);
cudaMalloc((void**)&devB, sizeof(int) * N*M);
cudaMalloc((void**)&devC, sizeof(int) * N*M);
cudaMemcpy(devA, a, sizeof(int) * N*M, cudaMemcpyHostToDevice);
cudaMemcpy(devB, b, sizeof(int) * N*M, cudaMemcpyHostToDevice);
//printf("%d + %d \n", (N + (M - 1) / M),M);
add <<<(N+(M-1)/M),M>>> (devA, devB, devC);
//add <<<(N, M >>>(devA, devB, devC);
cudaEvent_t syncEvent;
cudaEventCreate(&syncEvent);
cudaEventRecord(syncEvent, 0);
cudaEventSynchronize(syncEvent);
cudaMemcpy(c, devC, sizeof(int) * N*M, cudaMemcpyDeviceToHost);
for (int i = 0; i<N*M; i++)
{
printf("%d + %d = %d\n", a[i], b[i], c[i]);
}
cudaEventDestroy(syncEvent);
cudaFree(devA);
cudaFree(devB);
cudaFree(devC);
std::system("pause");
return 0;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime_api.h>
#include "device_launch_parameters.h"
#define N 10
#define M 5
__global__ void add(int *a, int *b, int *c)
{
int tid = blockIdx.x * blockDim.x+threadIdx.x;
c[tid] = a[tid] + b[tid];
}
__host__ int main(void)
{
int a[N*M], b[N*M], c[N*M];
for (int i = 0; i<N*M; i++)
{
a[i] = -i;
b[i] = i * i;
}
int* devA;
int* devB;
int* devC;
cudaMalloc((void**)&devA, sizeof(int) * N*M);
cudaMalloc((void**)&devB, sizeof(int) * N*M);
cudaMalloc((void**)&devC, sizeof(int) * N*M);
cudaMemcpy(devA, a, sizeof(int) * N*M, cudaMemcpyHostToDevice);
cudaMemcpy(devB, b, sizeof(int) * N*M, cudaMemcpyHostToDevice);
//printf("%d + %d \n", (N + (M - 1) / M),M);
add <<<(N+(M-1)/M),M>>> (devA, devB, devC);
//add <<<(N, M >>>(devA, devB, devC);
cudaEvent_t syncEvent;
cudaEventCreate(&syncEvent);
cudaEventRecord(syncEvent, 0);
cudaEventSynchronize(syncEvent);
cudaMemcpy(c, devC, sizeof(int) * N*M, cudaMemcpyDeviceToHost);
for (int i = 0; i<N*M; i++)
{
printf("%d + %d = %d\n", a[i], b[i], c[i]);
}
cudaEventDestroy(syncEvent);
cudaFree(devA);
cudaFree(devB);
cudaFree(devC);
std::system("pause");
return 0;
} | .file "tmpxft_0013901b_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d + %d = %d\n"
.LC1:
.string "pause"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $696, %rsp
.cfi_def_cfa_offset 720
movq %fs:40, %rax
movq %rax, 680(%rsp)
xorl %eax, %eax
.L12:
movl %eax, %edx
negl %edx
movl %edx, 64(%rsp,%rax,4)
movl %eax, %edx
imull %eax, %edx
movl %edx, 272(%rsp,%rax,4)
addq $1, %rax
cmpq $50, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $200, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $200, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $200, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $200, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 272(%rsp), %rsi
movl $1, %ecx
movl $200, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $5, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $10, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 480(%rsp), %rdi
movl $2, %ecx
movl $200, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L14:
movl 272(%rsp,%rbx), %ecx
movl 64(%rsp,%rbx), %edx
movl 480(%rsp,%rbx), %r8d
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $200, %rbx
jne .L14
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
leaq .LC1(%rip), %rdi
call system@PLT
movq 680(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $696, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime_api.h>
#include "device_launch_parameters.h"
#define N 10
#define M 5
__global__ void add(int *a, int *b, int *c)
{
int tid = blockIdx.x * blockDim.x+threadIdx.x;
c[tid] = a[tid] + b[tid];
}
__host__ int main(void)
{
int a[N*M], b[N*M], c[N*M];
for (int i = 0; i<N*M; i++)
{
a[i] = -i;
b[i] = i * i;
}
int* devA;
int* devB;
int* devC;
cudaMalloc((void**)&devA, sizeof(int) * N*M);
cudaMalloc((void**)&devB, sizeof(int) * N*M);
cudaMalloc((void**)&devC, sizeof(int) * N*M);
cudaMemcpy(devA, a, sizeof(int) * N*M, cudaMemcpyHostToDevice);
cudaMemcpy(devB, b, sizeof(int) * N*M, cudaMemcpyHostToDevice);
//printf("%d + %d \n", (N + (M - 1) / M),M);
add <<<(N+(M-1)/M),M>>> (devA, devB, devC);
//add <<<(N, M >>>(devA, devB, devC);
cudaEvent_t syncEvent;
cudaEventCreate(&syncEvent);
cudaEventRecord(syncEvent, 0);
cudaEventSynchronize(syncEvent);
cudaMemcpy(c, devC, sizeof(int) * N*M, cudaMemcpyDeviceToHost);
for (int i = 0; i<N*M; i++)
{
printf("%d + %d = %d\n", a[i], b[i], c[i]);
}
cudaEventDestroy(syncEvent);
cudaFree(devA);
cudaFree(devB);
cudaFree(devC);
std::system("pause");
return 0;
} |
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <hip/hip_runtime_api.h>
#define N 10
#define M 5
__global__ void add(int *a, int *b, int *c)
{
int tid = blockIdx.x * blockDim.x+threadIdx.x;
c[tid] = a[tid] + b[tid];
}
__host__ int main(void)
{
int a[N*M], b[N*M], c[N*M];
for (int i = 0; i<N*M; i++)
{
a[i] = -i;
b[i] = i * i;
}
int* devA;
int* devB;
int* devC;
hipMalloc((void**)&devA, sizeof(int) * N*M);
hipMalloc((void**)&devB, sizeof(int) * N*M);
hipMalloc((void**)&devC, sizeof(int) * N*M);
hipMemcpy(devA, a, sizeof(int) * N*M, hipMemcpyHostToDevice);
hipMemcpy(devB, b, sizeof(int) * N*M, hipMemcpyHostToDevice);
//printf("%d + %d \n", (N + (M - 1) / M),M);
add <<<(N+(M-1)/M),M>>> (devA, devB, devC);
//add <<<(N, M >>>(devA, devB, devC);
hipEvent_t syncEvent;
hipEventCreate(&syncEvent);
hipEventRecord(syncEvent, 0);
hipEventSynchronize(syncEvent);
hipMemcpy(c, devC, sizeof(int) * N*M, hipMemcpyDeviceToHost);
for (int i = 0; i<N*M; i++)
{
printf("%d + %d = %d\n", a[i], b[i], c[i]);
}
hipEventDestroy(syncEvent);
hipFree(devA);
hipFree(devB);
hipFree(devC);
std::system("pause");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. |
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <hip/hip_runtime_api.h>
#define N 10
#define M 5
__global__ void add(int *a, int *b, int *c)
{
int tid = blockIdx.x * blockDim.x+threadIdx.x;
c[tid] = a[tid] + b[tid];
}
__host__ int main(void)
{
int a[N*M], b[N*M], c[N*M];
for (int i = 0; i<N*M; i++)
{
a[i] = -i;
b[i] = i * i;
}
int* devA;
int* devB;
int* devC;
hipMalloc((void**)&devA, sizeof(int) * N*M);
hipMalloc((void**)&devB, sizeof(int) * N*M);
hipMalloc((void**)&devC, sizeof(int) * N*M);
hipMemcpy(devA, a, sizeof(int) * N*M, hipMemcpyHostToDevice);
hipMemcpy(devB, b, sizeof(int) * N*M, hipMemcpyHostToDevice);
//printf("%d + %d \n", (N + (M - 1) / M),M);
add <<<(N+(M-1)/M),M>>> (devA, devB, devC);
//add <<<(N, M >>>(devA, devB, devC);
hipEvent_t syncEvent;
hipEventCreate(&syncEvent);
hipEventRecord(syncEvent, 0);
hipEventSynchronize(syncEvent);
hipMemcpy(c, devC, sizeof(int) * N*M, hipMemcpyDeviceToHost);
for (int i = 0; i<N*M; i++)
{
printf("%d + %d = %d\n", a[i], b[i], c[i]);
}
hipEventDestroy(syncEvent);
hipFree(devA);
hipFree(devB);
hipFree(devC);
std::system("pause");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. |
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <hip/hip_runtime_api.h>
#define N 10
#define M 5
__global__ void add(int *a, int *b, int *c)
{
int tid = blockIdx.x * blockDim.x+threadIdx.x;
c[tid] = a[tid] + b[tid];
}
__host__ int main(void)
{
int a[N*M], b[N*M], c[N*M];
for (int i = 0; i<N*M; i++)
{
a[i] = -i;
b[i] = i * i;
}
int* devA;
int* devB;
int* devC;
hipMalloc((void**)&devA, sizeof(int) * N*M);
hipMalloc((void**)&devB, sizeof(int) * N*M);
hipMalloc((void**)&devC, sizeof(int) * N*M);
hipMemcpy(devA, a, sizeof(int) * N*M, hipMemcpyHostToDevice);
hipMemcpy(devB, b, sizeof(int) * N*M, hipMemcpyHostToDevice);
//printf("%d + %d \n", (N + (M - 1) / M),M);
add <<<(N+(M-1)/M),M>>> (devA, devB, devC);
//add <<<(N, M >>>(devA, devB, devC);
hipEvent_t syncEvent;
hipEventCreate(&syncEvent);
hipEventRecord(syncEvent, 0);
hipEventSynchronize(syncEvent);
hipMemcpy(c, devC, sizeof(int) * N*M, hipMemcpyDeviceToHost);
for (int i = 0; i<N*M; i++)
{
printf("%d + %d = %d\n", a[i], b[i], c[i]);
}
hipEventDestroy(syncEvent);
hipFree(devA);
hipFree(devB);
hipFree(devC);
std::system("pause");
return 0;
} | .text
.file "kernel.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $720, %rsp # imm = 0x2D0
.cfi_def_cfa_offset 736
.cfi_offset %rbx, -16
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, 512(%rsp,%rcx,4)
movl %ecx, %edx
imull %ecx, %edx
movl %edx, 304(%rsp,%rcx,4)
incq %rcx
decl %eax
cmpq $50, %rcx
jne .LBB1_1
# %bb.2:
leaq 32(%rsp), %rdi
movl $200, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $200, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $200, %esi
callq hipMalloc
movq 32(%rsp), %rdi
leaq 512(%rsp), %rsi
movl $200, %edx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
leaq 304(%rsp), %rsi
movl $200, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967301, %rdx # imm = 0x100000005
leaq 5(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq %rsp, %rdi
callq hipEventCreate
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
leaq 96(%rsp), %rdi
movl $200, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 512(%rsp,%rbx,4), %esi
movl 304(%rsp,%rbx,4), %edx
movl 96(%rsp,%rbx,4), %ecx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $50, %rbx
jne .LBB1_5
# %bb.6:
movq (%rsp), %rdi
callq hipEventDestroy
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movl $.L.str.1, %edi
callq system
xorl %eax, %eax
addq $720, %rsp # imm = 0x2D0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d + %d = %d\n"
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "pause"
.size .L.str.1, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013901b_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d + %d = %d\n"
.LC1:
.string "pause"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $696, %rsp
.cfi_def_cfa_offset 720
movq %fs:40, %rax
movq %rax, 680(%rsp)
xorl %eax, %eax
.L12:
movl %eax, %edx
negl %edx
movl %edx, 64(%rsp,%rax,4)
movl %eax, %edx
imull %eax, %edx
movl %edx, 272(%rsp,%rax,4)
addq $1, %rax
cmpq $50, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $200, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $200, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $200, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $200, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 272(%rsp), %rsi
movl $1, %ecx
movl $200, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $5, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $10, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 480(%rsp), %rdi
movl $2, %ecx
movl $200, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L14:
movl 272(%rsp,%rbx), %ecx
movl 64(%rsp,%rbx), %edx
movl 480(%rsp,%rbx), %r8d
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $200, %rbx
jne .L14
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
leaq .LC1(%rip), %rdi
call system@PLT
movq 680(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $696, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $720, %rsp # imm = 0x2D0
.cfi_def_cfa_offset 736
.cfi_offset %rbx, -16
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, 512(%rsp,%rcx,4)
movl %ecx, %edx
imull %ecx, %edx
movl %edx, 304(%rsp,%rcx,4)
incq %rcx
decl %eax
cmpq $50, %rcx
jne .LBB1_1
# %bb.2:
leaq 32(%rsp), %rdi
movl $200, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $200, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $200, %esi
callq hipMalloc
movq 32(%rsp), %rdi
leaq 512(%rsp), %rsi
movl $200, %edx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
leaq 304(%rsp), %rsi
movl $200, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967301, %rdx # imm = 0x100000005
leaq 5(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq %rsp, %rdi
callq hipEventCreate
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
leaq 96(%rsp), %rdi
movl $200, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 512(%rsp,%rbx,4), %esi
movl 304(%rsp,%rbx,4), %edx
movl 96(%rsp,%rbx,4), %ecx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $50, %rbx
jne .LBB1_5
# %bb.6:
movq (%rsp), %rdi
callq hipEventDestroy
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movl $.L.str.1, %edi
callq system
xorl %eax, %eax
addq $720, %rsp # imm = 0x2D0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d + %d = %d\n"
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "pause"
.size .L.str.1, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <algorithm>
#include <cassert>
#include <cstdlib>
#include <functional>
#include <iostream>
#include <vector>
using std::cout;
using std::generate;
using std::vector;
#define SIZE 64
#define THREADS 32
#define CUDA_CALL(x) do { if((x)!=cudaSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
#define CURAND_CALL(x) do { if((x)!=CURAND_STATUS_SUCCESS) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
__global__ void MatrixMul(const int *Md, const int *Nd, int *Pd, int Width) {
// Calculate the row index of the Pd element and M
int row = (blockIdx.y * blockDim.y) + threadIdx.y;
// Calculate the column idenx of Pd and N
int col = (blockIdx.x * blockDim.x) + threadIdx.x;
if((row < Width) && (col < Width)) {
// each thread computes one element of the block sub-matrix
for (int k = 0; k < Width; ++k) {
// dot product or corresponding row and column.
Pd[(row * Width) + col] += Md[(row * Width) + k] * Nd[(k * Width) + col];
}
}
}
// Check result on the CPU (single threaded)
void verify_result(vector<int> &a, vector<int> &b, vector<int> &c, int N) {
// Loop over every row...
float time;
cudaEvent_t start, stop;
// start tracking the time
cudaEventCreate(&start) ;
cudaEventCreate(&stop) ;
cudaEventRecord(start, 0) ;
for (int i = 0; i < N; i++) {
// Loop every column...
for (int j = 0; j < N; j++) {
// For every element in the row-column pair
int tmp = 0;
for (int k = 0; k < N; k++) {
// Accumulate the partial results
tmp += a[i * N + k] * b[k * N + j];
}
// Check against the CPU result
assert(tmp == c[i * N + j]);
}
}
cudaEventRecord(stop, 0) ;
cudaEventSynchronize(stop) ;
cudaEventElapsedTime(&time, start, stop) ;
printf("Compute time on CPU: %3.6f ms \n", time);
}
int main(void){
// initialize event creation for time tracking
float time;
cudaEvent_t start, stop;
// Matrix size of 32 x 32;
int N = SIZE;
printf("Matrix Size: %d x %d\n", N, N);
// size (in bytes) of matrix
size_t size = N * N * sizeof(int);
vector<int> host_a(N * N);
vector<int> host_b(N * N);
vector<int> host_c(N * N);
// generate random indices between 0 and 1.
generate(host_a.begin(), host_a.end(), []() {return rand() % 2; });
generate(host_b.begin(), host_b.end(), []() {return rand() % 2; });
// device memory allocation
int *dev_a, *dev_b, *dev_c;
cudaMalloc(&dev_a, size);
cudaMalloc(&dev_b, size);
cudaMalloc(&dev_c, size);
//copy data from host to device
cudaMemcpy(dev_a, host_a.data(), size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, host_b.data(), size, cudaMemcpyHostToDevice);
int BLOCKS = N/THREADS;
dim3 threads(THREADS, THREADS);
dim3 blocks(BLOCKS, BLOCKS);
// start tracking the time
cudaEventCreate(&start) ;
cudaEventCreate(&stop) ;
cudaEventRecord(start, 0) ;
// launch kernal
printf("No. of blocks: %d x %d\n", BLOCKS, BLOCKS);
printf("No. of therads: %d x %d\n", THREADS, THREADS);
MatrixMul<<<blocks, threads>>> (dev_a, dev_b, dev_c, N);
// stop tracking the time
cudaEventRecord(stop, 0) ;
cudaEventSynchronize(stop) ;
cudaEventElapsedTime(&time, start, stop) ;
cudaMemcpy(host_c.data(), dev_c, size, cudaMemcpyDeviceToHost);
printf("Compute time on GPU: %3.6f ms \n", time);
// verify result on CPU
verify_result(host_a, host_b, host_c, N);
//free device memory
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
return 0;
} | code for sm_80
Function : _Z9MatrixMulPKiS0_Pii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0030*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e680000002600 */
/*0040*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R5, R5, c[0x0][0x0], R2 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R9, R9, c[0x0][0x4], R0 ; /* 0x0000010009097a24 */
/* 0x002fe200078e0200 */
/*0080*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fc80000000f00 */
/*0090*/ ISETP.GE.OR P0, PT, R9, c[0x0][0x178], P0 ; /* 0x00005e0009007a0c */
/* 0x000fc80000706670 */
/*00a0*/ ISETP.LT.OR P0, PT, R0, 0x1, P0 ; /* 0x000000010000780c */
/* 0x000fda0000701670 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R0, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x000fe20007ffe0ff */
/*00d0*/ IMAD R9, R9, c[0x0][0x178], RZ ; /* 0x00005e0009097a24 */
/* 0x000fe200078e02ff */
/*00e0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0100*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0110*/ IADD3 R3, R5, R9, RZ ; /* 0x0000000905037210 */
/* 0x000fe40007ffe0ff */
/*0120*/ LOP3.LUT R4, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300047812 */
/* 0x000fe400078ec0ff */
/*0130*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fc40000000f00 */
/*0140*/ IMAD.WIDE R2, R3, R8, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0208 */
/*0150*/ @!P0 BRA 0xcb0 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R11, -R4, c[0x0][0x178], RZ ; /* 0x00005e00040b7a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000162000c1e1900 */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fe20000000f00 */
/*01a0*/ IMAD.WIDE R12, R5, R8, c[0x0][0x168] ; /* 0x00005a00050c7625 */
/* 0x000fe200078e0208 */
/*01b0*/ ISETP.GT.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fda0003f04270 */
/*01c0*/ @!P0 BRA 0xae0 ; /* 0x0000091000008947 */
/* 0x001fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R11, 0xc, PT ; /* 0x0000000c0b00780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x7a0 ; /* 0x000005a000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*0220*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x004ea2000c1e1900 */
/*0230*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fca0008000f00 */
/*0240*/ IMAD.WIDE R6, R9, 0x4, R6 ; /* 0x0000000409067825 */
/* 0x000fca00078e0206 */
/*0250*/ LDG.E R16, [R6.64] ; /* 0x0000000406107981 */
/* 0x000ea4000c1e1900 */
/*0260*/ IMAD R19, R14, R16, R15 ; /* 0x000000100e137224 */
/* 0x024fe400078e020f */
/*0270*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0280*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0290*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea8000c1e1900 */
/*02a0*/ LDG.E R17, [R6.64+0x4] ; /* 0x0000040406117981 */
/* 0x000ea4000c1e1900 */
/*02b0*/ IMAD R21, R16, R17, R19 ; /* 0x0000001110157224 */
/* 0x004fc400078e0213 */
/*02c0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*02d0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*02e0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*02f0*/ LDG.E R12, [R6.64+0x8] ; /* 0x00000804060c7981 */
/* 0x000ea4000c1e1900 */
/*0300*/ IMAD R23, R18, R12, R21 ; /* 0x0000000c12177224 */
/* 0x004fc400078e0215 */
/*0310*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0210 */
/*0320*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0330*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000e28000c1e1900 */
/*0340*/ LDG.E R14, [R6.64+0xc] ; /* 0x00000c04060e7981 */
/* 0x000e24000c1e1900 */
/*0350*/ IMAD R19, R18, R14, R23 ; /* 0x0000000e12137224 */
/* 0x001fc400078e0217 */
/*0360*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0370*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0380*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e68000c1e1900 */
/*0390*/ LDG.E R16, [R6.64+0x10] ; /* 0x0000100406107981 */
/* 0x000e64000c1e1900 */
/*03a0*/ IMAD R21, R18, R16, R19 ; /* 0x0000001012157224 */
/* 0x002fc400078e0213 */
/*03b0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*03c0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*03d0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*03e0*/ LDG.E R12, [R6.64+0x14] ; /* 0x00001404060c7981 */
/* 0x000ea4000c1e1900 */
/*03f0*/ IMAD R23, R18, R12, R21 ; /* 0x0000000c12177224 */
/* 0x004fc400078e0215 */
/*0400*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0210 */
/*0410*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0420*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000e28000c1e1900 */
/*0430*/ LDG.E R14, [R6.64+0x18] ; /* 0x00001804060e7981 */
/* 0x000e24000c1e1900 */
/*0440*/ IMAD R19, R18, R14, R23 ; /* 0x0000000e12137224 */
/* 0x001fc400078e0217 */
/*0450*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0460*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0470*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e68000c1e1900 */
/*0480*/ LDG.E R16, [R6.64+0x1c] ; /* 0x00001c0406107981 */
/* 0x000e64000c1e1900 */
/*0490*/ IMAD R21, R18, R16, R19 ; /* 0x0000001012157224 */
/* 0x002fc400078e0213 */
/*04a0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*04b0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*04c0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*04d0*/ LDG.E R12, [R6.64+0x20] ; /* 0x00002004060c7981 */
/* 0x000ea4000c1e1900 */
/*04e0*/ IMAD R23, R18, R12, R21 ; /* 0x0000000c12177224 */
/* 0x004fc400078e0215 */
/*04f0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0210 */
/*0500*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0510*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000e28000c1e1900 */
/*0520*/ LDG.E R14, [R6.64+0x24] ; /* 0x00002404060e7981 */
/* 0x000e24000c1e1900 */
/*0530*/ IMAD R19, R18, R14, R23 ; /* 0x0000000e12137224 */
/* 0x001fc400078e0217 */
/*0540*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0550*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x000fe8000c101904 */
/*0560*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e68000c1e1900 */
/*0570*/ LDG.E R16, [R6.64+0x28] ; /* 0x0000280406107981 */
/* 0x000e64000c1e1900 */
/*0580*/ IMAD R21, R18, R16, R19 ; /* 0x0000001012157224 */
/* 0x002fc400078e0213 */
/*0590*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*05a0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*05b0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*05c0*/ LDG.E R12, [R6.64+0x2c] ; /* 0x00002c04060c7981 */
/* 0x000ea4000c1e1900 */
/*05d0*/ IMAD R23, R18, R12, R21 ; /* 0x0000000c12177224 */
/* 0x004fc400078e0215 */
/*05e0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0210 */
/*05f0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*0600*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000ea8000c1e1900 */
/*0610*/ LDG.E R14, [R6.64+0x30] ; /* 0x00003004060e7981 */
/* 0x000ea4000c1e1900 */
/*0620*/ IMAD R25, R18, R14, R23 ; /* 0x0000000e12197224 */
/* 0x004fc400078e0217 */
/*0630*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0640*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*0650*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e28000c1e1900 */
/*0660*/ LDG.E R16, [R6.64+0x34] ; /* 0x0000340406107981 */
/* 0x000e24000c1e1900 */
/*0670*/ IMAD R21, R18, R16, R25 ; /* 0x0000001012157224 */
/* 0x001fc400078e0219 */
/*0680*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*0690*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0005e8000c101904 */
/*06a0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000e68000c1e1900 */
/*06b0*/ LDG.E R12, [R6.64+0x38] ; /* 0x00003804060c7981 */
/* 0x000e62000c1e1900 */
/*06c0*/ IADD3 R11, R11, -0x10, RZ ; /* 0xfffffff00b0b7810 */
/* 0x000fe20007ffe0ff */
/*06d0*/ IMAD R23, R18, R12, R21 ; /* 0x0000000c12177224 */
/* 0x002fc400078e0215 */
/*06e0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*06f0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0700*/ LDG.E R13, [R6.64+0x3c] ; /* 0x00003c04060d7981 */
/* 0x000ee8000c1e1900 */
/*0710*/ LDG.E R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000ee2000c1e1900 */
/*0720*/ ISETP.GT.AND P1, PT, R11, 0xc, PT ; /* 0x0000000c0b00780c */
/* 0x000fe20003f24270 */
/*0730*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0740*/ IADD3 R10, R10, 0x10, RZ ; /* 0x000000100a0a7810 */
/* 0x000fc60007ffe0ff */
/*0750*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0760*/ IMAD R15, R12, R13, R23 ; /* 0x0000000d0c0f7224 */
/* 0x008fe400078e0217 */
/*0770*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0212 */
/*0780*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0005e4000c101904 */
/*0790*/ @P1 BRA 0x210 ; /* 0xfffffa7000001947 */
/* 0x000fea000383ffff */
/*07a0*/ ISETP.GT.AND P1, PT, R11, 0x4, PT ; /* 0x000000040b00780c */
/* 0x000fda0003f24270 */
/*07b0*/ @!P1 BRA 0xac0 ; /* 0x0000030000009947 */
/* 0x000fea0003800000 */
/*07c0*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*07d0*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ee2000c1e1900 */
/*07e0*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fca0008000f00 */
/*07f0*/ IMAD.WIDE R6, R9, 0x4, R6 ; /* 0x0000000409067825 */
/* 0x000fca00078e0206 */
/*0800*/ LDG.E R16, [R6.64] ; /* 0x0000000406107981 */
/* 0x000ee4000c1e1900 */
/*0810*/ IMAD R19, R14, R16, R15 ; /* 0x000000100e137224 */
/* 0x028fe400078e020f */
/*0820*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x004fc600078e020c */
/*0830*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0840*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea8000c1e1900 */
/*0850*/ LDG.E R17, [R6.64+0x4] ; /* 0x0000040406117981 */
/* 0x000ea4000c1e1900 */
/*0860*/ IMAD R21, R16, R17, R19 ; /* 0x0000001110157224 */
/* 0x004fc400078e0213 */
/*0870*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*0880*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0890*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*08a0*/ LDG.E R12, [R6.64+0x8] ; /* 0x00000804060c7981 */
/* 0x000ea4000c1e1900 */
/*08b0*/ IMAD R23, R18, R12, R21 ; /* 0x0000000c12177224 */
/* 0x004fc400078e0215 */
/*08c0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0210 */
/*08d0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*08e0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000e28000c1e1900 */
/*08f0*/ LDG.E R14, [R6.64+0xc] ; /* 0x00000c04060e7981 */
/* 0x000e24000c1e1900 */
/*0900*/ IMAD R19, R18, R14, R23 ; /* 0x0000000e12137224 */
/* 0x001fc400078e0217 */
/*0910*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0920*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0930*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e68000c1e1900 */
/*0940*/ LDG.E R16, [R6.64+0x10] ; /* 0x0000100406107981 */
/* 0x000e64000c1e1900 */
/*0950*/ IMAD R21, R18, R16, R19 ; /* 0x0000001012157224 */
/* 0x002fc400078e0213 */
/*0960*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*0970*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0980*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*0990*/ LDG.E R12, [R6.64+0x14] ; /* 0x00001404060c7981 */
/* 0x000ea4000c1e1900 */
/*09a0*/ IMAD R23, R18, R12, R21 ; /* 0x0000000c12177224 */
/* 0x004fc400078e0215 */
/*09b0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0210 */
/*09c0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*09d0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R14, [R6.64+0x18] ; /* 0x00001804060e7981 */
/* 0x000ea4000c1e1900 */
/*09f0*/ IMAD R25, R18, R14, R23 ; /* 0x0000000e12197224 */
/* 0x004fc400078e0217 */
/*0a00*/ IMAD.WIDE R18, R0, 0x4, R12 ; /* 0x0000000400127825 */
/* 0x001fc600078e020c */
/*0a10*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0a20*/ LDG.E R15, [R6.64+0x1c] ; /* 0x00001c04060f7981 */
/* 0x000ea8000c1e1900 */
/*0a30*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000ea2000c1e1900 */
/*0a40*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0a50*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0a60*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0212 */
/*0a70*/ IADD3 R10, R10, 0x8, RZ ; /* 0x000000080a0a7810 */
/* 0x000fc40007ffe0ff */
/*0a80*/ IADD3 R11, R11, -0x8, RZ ; /* 0xfffffff80b0b7810 */
/* 0x000fe20007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ IMAD R15, R14, R15, R25 ; /* 0x0000000f0e0f7224 */
/* 0x004fca00078e0219 */
/*0ab0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0003e8000c101904 */
/*0ac0*/ ISETP.NE.OR P0, PT, R11, RZ, P0 ; /* 0x000000ff0b00720c */
/* 0x000fda0000705670 */
/*0ad0*/ @!P0 BRA 0xcb0 ; /* 0x000001d000008947 */
/* 0x000fea0003800000 */
/*0ae0*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*0af0*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ee2000c1e1900 */
/*0b00*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fca0008000f00 */
/*0b10*/ IMAD.WIDE R6, R9, 0x4, R6 ; /* 0x0000000409067825 */
/* 0x000fca00078e0206 */
/*0b20*/ LDG.E R16, [R6.64] ; /* 0x0000000406107981 */
/* 0x000ee4000c1e1900 */
/*0b30*/ IMAD R21, R14, R16, R15 ; /* 0x000000100e157224 */
/* 0x02efe400078e020f */
/*0b40*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0b50*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*0b60*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea8000c1e1900 */
/*0b70*/ LDG.E R17, [R6.64+0x4] ; /* 0x0000040406117981 */
/* 0x000ea4000c1e1900 */
/*0b80*/ IMAD R23, R16, R17, R21 ; /* 0x0000001110177224 */
/* 0x004fc400078e0215 */
/*0b90*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*0ba0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0001e8000c101904 */
/*0bb0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*0bc0*/ LDG.E R12, [R6.64+0x8] ; /* 0x00000804060c7981 */
/* 0x000ea2000c1e1900 */
/*0bd0*/ IADD3 R11, R11, -0x4, RZ ; /* 0xfffffffc0b0b7810 */
/* 0x000fe20007ffe0ff */
/*0be0*/ IMAD R25, R18, R12, R23 ; /* 0x0000000c12197224 */
/* 0x004fc400078e0217 */
/*0bf0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*0c00*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0001e8000c101904 */
/*0c10*/ LDG.E R13, [R6.64+0xc] ; /* 0x00000c04060d7981 */
/* 0x000ea8000c1e1900 */
/*0c20*/ LDG.E R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000ea2000c1e1900 */
/*0c30*/ ISETP.NE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f05270 */
/*0c40*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0c50*/ IADD3 R10, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc60007ffe0ff */
/*0c60*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0c70*/ IMAD R15, R12, R13, R25 ; /* 0x0000000d0c0f7224 */
/* 0x004fe400078e0219 */
/*0c80*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0212 */
/*0c90*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0001e4000c101904 */
/*0ca0*/ @P0 BRA 0xae0 ; /* 0xfffffe3000000947 */
/* 0x001fea000383ffff */
/*0cb0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0cc0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0cd0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000162000c1e1900 */
/*0ce0*/ IADD3 R7, R9, R10, RZ ; /* 0x0000000a09077210 */
/* 0x000fe20007ffe0ff */
/*0cf0*/ IMAD R5, R10, c[0x0][0x178], R5 ; /* 0x00005e000a057a24 */
/* 0x000fc800078e0205 */
/*0d00*/ IMAD.WIDE R6, R7, R8, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fc800078e0208 */
/*0d10*/ IMAD.WIDE R8, R5, R8, c[0x0][0x168] ; /* 0x00005a0005087625 */
/* 0x001fca00078e0208 */
/*0d20*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x0010e8000c1e1900 */
/*0d30*/ LDG.E R5, [R6.64] ; /* 0x0000000406057981 */
/* 0x0008e2000c1e1900 */
/*0d40*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fc80007ffe0ff */
/*0d50*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0d60*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0d70*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x010fc80007f3e0ff */
/*0d80*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0d90*/ IMAD R11, R10, R5, R11 ; /* 0x000000050a0b7224 */
/* 0x028fca00078e020b */
/*0da0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e2000c101904 */
/*0db0*/ @P0 BRA 0xd20 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0dc0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0dd0*/ BRA 0xdd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <algorithm>
#include <cassert>
#include <cstdlib>
#include <functional>
#include <iostream>
#include <vector>
using std::cout;
using std::generate;
using std::vector;
#define SIZE 64
#define THREADS 32
#define CUDA_CALL(x) do { if((x)!=cudaSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
#define CURAND_CALL(x) do { if((x)!=CURAND_STATUS_SUCCESS) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
__global__ void MatrixMul(const int *Md, const int *Nd, int *Pd, int Width) {
// Calculate the row index of the Pd element and M
int row = (blockIdx.y * blockDim.y) + threadIdx.y;
// Calculate the column idenx of Pd and N
int col = (blockIdx.x * blockDim.x) + threadIdx.x;
if((row < Width) && (col < Width)) {
// each thread computes one element of the block sub-matrix
for (int k = 0; k < Width; ++k) {
// dot product or corresponding row and column.
Pd[(row * Width) + col] += Md[(row * Width) + k] * Nd[(k * Width) + col];
}
}
}
// Check result on the CPU (single threaded)
void verify_result(vector<int> &a, vector<int> &b, vector<int> &c, int N) {
// Loop over every row...
float time;
cudaEvent_t start, stop;
// start tracking the time
cudaEventCreate(&start) ;
cudaEventCreate(&stop) ;
cudaEventRecord(start, 0) ;
for (int i = 0; i < N; i++) {
// Loop every column...
for (int j = 0; j < N; j++) {
// For every element in the row-column pair
int tmp = 0;
for (int k = 0; k < N; k++) {
// Accumulate the partial results
tmp += a[i * N + k] * b[k * N + j];
}
// Check against the CPU result
assert(tmp == c[i * N + j]);
}
}
cudaEventRecord(stop, 0) ;
cudaEventSynchronize(stop) ;
cudaEventElapsedTime(&time, start, stop) ;
printf("Compute time on CPU: %3.6f ms \n", time);
}
int main(void){
// initialize event creation for time tracking
float time;
cudaEvent_t start, stop;
// Matrix size of 32 x 32;
int N = SIZE;
printf("Matrix Size: %d x %d\n", N, N);
// size (in bytes) of matrix
size_t size = N * N * sizeof(int);
vector<int> host_a(N * N);
vector<int> host_b(N * N);
vector<int> host_c(N * N);
// generate random indices between 0 and 1.
generate(host_a.begin(), host_a.end(), []() {return rand() % 2; });
generate(host_b.begin(), host_b.end(), []() {return rand() % 2; });
// device memory allocation
int *dev_a, *dev_b, *dev_c;
cudaMalloc(&dev_a, size);
cudaMalloc(&dev_b, size);
cudaMalloc(&dev_c, size);
//copy data from host to device
cudaMemcpy(dev_a, host_a.data(), size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, host_b.data(), size, cudaMemcpyHostToDevice);
int BLOCKS = N/THREADS;
dim3 threads(THREADS, THREADS);
dim3 blocks(BLOCKS, BLOCKS);
// start tracking the time
cudaEventCreate(&start) ;
cudaEventCreate(&stop) ;
cudaEventRecord(start, 0) ;
// launch kernal
printf("No. of blocks: %d x %d\n", BLOCKS, BLOCKS);
printf("No. of therads: %d x %d\n", THREADS, THREADS);
MatrixMul<<<blocks, threads>>> (dev_a, dev_b, dev_c, N);
// stop tracking the time
cudaEventRecord(stop, 0) ;
cudaEventSynchronize(stop) ;
cudaEventElapsedTime(&time, start, stop) ;
cudaMemcpy(host_c.data(), dev_c, size, cudaMemcpyDeviceToHost);
printf("Compute time on GPU: %3.6f ms \n", time);
// verify result on CPU
verify_result(host_a, host_b, host_c, N);
//free device memory
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
return 0;
} | .file "tmpxft_0005d73d_00000000-6_matrixMultiply.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4930:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4930:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Compute time on CPU: %3.6f ms \n"
.text
.globl _Z13verify_resultRSt6vectorIiSaIiEES2_S2_i
.type _Z13verify_resultRSt6vectorIiSaIiEES2_S2_i, @function
_Z13verify_resultRSt6vectorIiSaIiEES2_S2_i:
.LFB4920:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movl %ecx, %ebx
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %esi
movl $0, %edi
testl %ebx, %ebx
jg .L4
.L5:
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
leal 1(%rsi), %eax
cmpl %edx, %esi
je .L5
movl %eax, %esi
.L4:
movl %edi, %ecx
.L8:
movl $0, %eax
.L6:
movl %eax, %edx
addl $1, %eax
cmpl %eax, %ebx
jne .L6
leal 1(%rcx), %eax
cmpl %edx, %ecx
je .L7
movl %eax, %ecx
jmp .L8
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4920:
.size _Z13verify_resultRSt6vectorIiSaIiEES2_S2_i, .-_Z13verify_resultRSt6vectorIiSaIiEES2_S2_i
.globl _Z35__device_stub__Z9MatrixMulPKiS0_PiiPKiS0_Pii
.type _Z35__device_stub__Z9MatrixMulPKiS0_PiiPKiS0_Pii, @function
_Z35__device_stub__Z9MatrixMulPKiS0_PiiPKiS0_Pii:
.LFB4952:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9MatrixMulPKiS0_Pii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4952:
.size _Z35__device_stub__Z9MatrixMulPKiS0_PiiPKiS0_Pii, .-_Z35__device_stub__Z9MatrixMulPKiS0_PiiPKiS0_Pii
.globl _Z9MatrixMulPKiS0_Pii
.type _Z9MatrixMulPKiS0_Pii, @function
_Z9MatrixMulPKiS0_Pii:
.LFB4953:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9MatrixMulPKiS0_PiiPKiS0_Pii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4953:
.size _Z9MatrixMulPKiS0_Pii, .-_Z9MatrixMulPKiS0_Pii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z9MatrixMulPKiS0_Pii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4955:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9MatrixMulPKiS0_Pii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4955:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._ZNSt6vectorIiSaIiEEC2EmRKS0_.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "cannot create std::vector larger than max_size()"
.section .text._ZNSt6vectorIiSaIiEEC2EmRKS0_,"axG",@progbits,_ZNSt6vectorIiSaIiEEC5EmRKS0_,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEEC2EmRKS0_
.type _ZNSt6vectorIiSaIiEEC2EmRKS0_, @function
_ZNSt6vectorIiSaIiEEC2EmRKS0_:
.LFB5270:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %rax
shrq $61, %rax
jne .L35
movq %rdi, %rbx
movq %rsi, %rbp
movq $0, (%rdi)
movq $0, 8(%rdi)
movq $0, 16(%rdi)
testq %rsi, %rsi
je .L27
leaq 0(,%rsi,4), %r12
movq %r12, %rdi
call _Znwm@PLT
movq %rax, (%rbx)
movq %rax, 8(%rbx)
leaq (%rax,%r12), %rdx
movq %rdx, 16(%rbx)
movl $0, (%rax)
addq $4, %rax
cmpq $1, %rbp
je .L30
cmpq %rax, %rdx
je .L31
.L29:
movl $0, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L29
jmp .L28
.L35:
leaq .LC2(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L30:
movq %rax, %rdx
jmp .L28
.L31:
movq %rax, %rdx
jmp .L28
.L27:
movq $0, (%rdi)
movq $0, 16(%rdi)
movl $0, %edx
.L28:
movq %rdx, 8(%rbx)
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5270:
.size _ZNSt6vectorIiSaIiEEC2EmRKS0_, .-_ZNSt6vectorIiSaIiEEC2EmRKS0_
.weak _ZNSt6vectorIiSaIiEEC1EmRKS0_
.set _ZNSt6vectorIiSaIiEEC1EmRKS0_,_ZNSt6vectorIiSaIiEEC2EmRKS0_
.section .text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEED2Ev
.type _ZNSt6vectorIiSaIiEED2Ev, @function
_ZNSt6vectorIiSaIiEED2Ev:
.LFB5273:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L39
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L39:
ret
.cfi_endproc
.LFE5273:
.size _ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev
.weak _ZNSt6vectorIiSaIiEED1Ev
.set _ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev
.section .rodata.str1.1
.LC3:
.string "Matrix Size: %d x %d\n"
.LC4:
.string "No. of blocks: %d x %d\n"
.LC5:
.string "No. of therads: %d x %d\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "Compute time on GPU: %3.6f ms \n"
.text
.globl main
.type main, @function
main:
.LFB4921:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4921
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $184, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movl $64, %ecx
movl $64, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
.LEHB0:
call __printf_chk@PLT
leaq 144(%rsp), %rbx
leaq 80(%rsp), %rdi
movq %rbx, %rdx
movl $4096, %esi
call _ZNSt6vectorIiSaIiEEC1EmRKS0_
.LEHE0:
leaq 112(%rsp), %rdi
movq %rbx, %rdx
movl $4096, %esi
.LEHB1:
call _ZNSt6vectorIiSaIiEEC1EmRKS0_
.LEHE1:
leaq 68(%rsp), %rdx
movq %rbx, %rdi
movl $4096, %esi
.LEHB2:
call _ZNSt6vectorIiSaIiEEC1EmRKS0_
.LEHE2:
movq 88(%rsp), %rbp
movq 80(%rsp), %r13
cmpq %rbp, %r13
je .L43
movq %r13, %rbx
.L44:
call rand@PLT
movl %eax, %edx
shrl $31, %edx
addl %edx, %eax
andl $1, %eax
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbx, %rbp
jne .L44
.L43:
movq 120(%rsp), %rbp
movq 112(%rsp), %r12
cmpq %rbp, %r12
je .L45
movq %r12, %rbx
.L46:
call rand@PLT
movl %eax, %edx
shrl $31, %edx
addl %edx, %eax
andl $1, %eax
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbx, %rbp
jne .L46
.L45:
leaq 32(%rsp), %rdi
movl $16384, %esi
.LEHB3:
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $16384, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $16384, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $16384, %edx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16384, %edx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 56(%rsp)
movl $32, 60(%rsp)
movl $1, 64(%rsp)
movl $2, 68(%rsp)
movl $2, 72(%rsp)
movl $1, 76(%rsp)
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $2, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $32, %ecx
movl $32, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 64(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movq 68(%rsp), %rdi
movl 76(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L47
movl $64, %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z35__device_stub__Z9MatrixMulPKiS0_PiiPKiS0_Pii
.L47:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $2, %ecx
movl $16384, %edx
movq 48(%rsp), %rsi
movq 144(%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 144(%rsp), %rdx
leaq 112(%rsp), %rsi
leaq 80(%rsp), %rdi
movl $64, %ecx
call _Z13verify_resultRSt6vectorIiSaIiEES2_S2_i
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
.LEHE3:
leaq 144(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
leaq 112(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
leaq 80(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L60
movl $0, %eax
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 144(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
.L49:
leaq 112(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
.L50:
leaq 80(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 168(%rsp), %rax
subq %fs:40, %rax
je .L51
call __stack_chk_fail@PLT
.L54:
endbr64
movq %rax, %rbx
jmp .L49
.L53:
endbr64
movq %rax, %rbx
jmp .L50
.L51:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L60:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4921:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4921:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4921-.LLSDACSB4921
.LLSDACSB4921:
.uleb128 .LEHB0-.LFB4921
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4921
.uleb128 .LEHE1-.LEHB1
.uleb128 .L53-.LFB4921
.uleb128 0
.uleb128 .LEHB2-.LFB4921
.uleb128 .LEHE2-.LEHB2
.uleb128 .L54-.LFB4921
.uleb128 0
.uleb128 .LEHB3-.LFB4921
.uleb128 .LEHE3-.LEHB3
.uleb128 .L55-.LFB4921
.uleb128 0
.uleb128 .LEHB4-.LFB4921
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE4921:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <algorithm>
#include <cassert>
#include <cstdlib>
#include <functional>
#include <iostream>
#include <vector>
using std::cout;
using std::generate;
using std::vector;
#define SIZE 64
#define THREADS 32
#define CUDA_CALL(x) do { if((x)!=cudaSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
#define CURAND_CALL(x) do { if((x)!=CURAND_STATUS_SUCCESS) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
__global__ void MatrixMul(const int *Md, const int *Nd, int *Pd, int Width) {
// Calculate the row index of the Pd element and M
int row = (blockIdx.y * blockDim.y) + threadIdx.y;
// Calculate the column idenx of Pd and N
int col = (blockIdx.x * blockDim.x) + threadIdx.x;
if((row < Width) && (col < Width)) {
// each thread computes one element of the block sub-matrix
for (int k = 0; k < Width; ++k) {
// dot product or corresponding row and column.
Pd[(row * Width) + col] += Md[(row * Width) + k] * Nd[(k * Width) + col];
}
}
}
// Check result on the CPU (single threaded)
void verify_result(vector<int> &a, vector<int> &b, vector<int> &c, int N) {
// Loop over every row...
float time;
cudaEvent_t start, stop;
// start tracking the time
cudaEventCreate(&start) ;
cudaEventCreate(&stop) ;
cudaEventRecord(start, 0) ;
for (int i = 0; i < N; i++) {
// Loop every column...
for (int j = 0; j < N; j++) {
// For every element in the row-column pair
int tmp = 0;
for (int k = 0; k < N; k++) {
// Accumulate the partial results
tmp += a[i * N + k] * b[k * N + j];
}
// Check against the CPU result
assert(tmp == c[i * N + j]);
}
}
cudaEventRecord(stop, 0) ;
cudaEventSynchronize(stop) ;
cudaEventElapsedTime(&time, start, stop) ;
printf("Compute time on CPU: %3.6f ms \n", time);
}
int main(void){
// initialize event creation for time tracking
float time;
cudaEvent_t start, stop;
// Matrix size of 32 x 32;
int N = SIZE;
printf("Matrix Size: %d x %d\n", N, N);
// size (in bytes) of matrix
size_t size = N * N * sizeof(int);
vector<int> host_a(N * N);
vector<int> host_b(N * N);
vector<int> host_c(N * N);
// generate random indices between 0 and 1.
generate(host_a.begin(), host_a.end(), []() {return rand() % 2; });
generate(host_b.begin(), host_b.end(), []() {return rand() % 2; });
// device memory allocation
int *dev_a, *dev_b, *dev_c;
cudaMalloc(&dev_a, size);
cudaMalloc(&dev_b, size);
cudaMalloc(&dev_c, size);
//copy data from host to device
cudaMemcpy(dev_a, host_a.data(), size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, host_b.data(), size, cudaMemcpyHostToDevice);
int BLOCKS = N/THREADS;
dim3 threads(THREADS, THREADS);
dim3 blocks(BLOCKS, BLOCKS);
// start tracking the time
cudaEventCreate(&start) ;
cudaEventCreate(&stop) ;
cudaEventRecord(start, 0) ;
// launch kernal
printf("No. of blocks: %d x %d\n", BLOCKS, BLOCKS);
printf("No. of therads: %d x %d\n", THREADS, THREADS);
MatrixMul<<<blocks, threads>>> (dev_a, dev_b, dev_c, N);
// stop tracking the time
cudaEventRecord(stop, 0) ;
cudaEventSynchronize(stop) ;
cudaEventElapsedTime(&time, start, stop) ;
cudaMemcpy(host_c.data(), dev_c, size, cudaMemcpyDeviceToHost);
printf("Compute time on GPU: %3.6f ms \n", time);
// verify result on CPU
verify_result(host_a, host_b, host_c, N);
//free device memory
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <algorithm>
#include <cassert>
#include <cstdlib>
#include <functional>
#include <iostream>
#include <vector>
using std::cout;
using std::generate;
using std::vector;
#define SIZE 64
#define THREADS 32
#define CUDA_CALL(x) do { if((x)!=hipSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
#define CURAND_CALL(x) do { if((x)!=HIPRAND_STATUS_SUCCESS) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
__global__ void MatrixMul(const int *Md, const int *Nd, int *Pd, int Width) {
// Calculate the row index of the Pd element and M
int row = (blockIdx.y * blockDim.y) + threadIdx.y;
// Calculate the column idenx of Pd and N
int col = (blockIdx.x * blockDim.x) + threadIdx.x;
if((row < Width) && (col < Width)) {
// each thread computes one element of the block sub-matrix
for (int k = 0; k < Width; ++k) {
// dot product or corresponding row and column.
Pd[(row * Width) + col] += Md[(row * Width) + k] * Nd[(k * Width) + col];
}
}
}
// Check result on the CPU (single threaded)
void verify_result(vector<int> &a, vector<int> &b, vector<int> &c, int N) {
// Loop over every row...
float time;
hipEvent_t start, stop;
// start tracking the time
hipEventCreate(&start) ;
hipEventCreate(&stop) ;
hipEventRecord(start, 0) ;
for (int i = 0; i < N; i++) {
// Loop every column...
for (int j = 0; j < N; j++) {
// For every element in the row-column pair
int tmp = 0;
for (int k = 0; k < N; k++) {
// Accumulate the partial results
tmp += a[i * N + k] * b[k * N + j];
}
// Check against the CPU result
assert(tmp == c[i * N + j]);
}
}
hipEventRecord(stop, 0) ;
hipEventSynchronize(stop) ;
hipEventElapsedTime(&time, start, stop) ;
printf("Compute time on CPU: %3.6f ms \n", time);
}
int main(void){
// initialize event creation for time tracking
float time;
hipEvent_t start, stop;
// Matrix size of 32 x 32;
int N = SIZE;
printf("Matrix Size: %d x %d\n", N, N);
// size (in bytes) of matrix
size_t size = N * N * sizeof(int);
vector<int> host_a(N * N);
vector<int> host_b(N * N);
vector<int> host_c(N * N);
// generate random indices between 0 and 1.
generate(host_a.begin(), host_a.end(), []() {return rand() % 2; });
generate(host_b.begin(), host_b.end(), []() {return rand() % 2; });
// device memory allocation
int *dev_a, *dev_b, *dev_c;
hipMalloc(&dev_a, size);
hipMalloc(&dev_b, size);
hipMalloc(&dev_c, size);
//copy data from host to device
hipMemcpy(dev_a, host_a.data(), size, hipMemcpyHostToDevice);
hipMemcpy(dev_b, host_b.data(), size, hipMemcpyHostToDevice);
int BLOCKS = N/THREADS;
dim3 threads(THREADS, THREADS);
dim3 blocks(BLOCKS, BLOCKS);
// start tracking the time
hipEventCreate(&start) ;
hipEventCreate(&stop) ;
hipEventRecord(start, 0) ;
// launch kernal
printf("No. of blocks: %d x %d\n", BLOCKS, BLOCKS);
printf("No. of therads: %d x %d\n", THREADS, THREADS);
MatrixMul<<<blocks, threads>>> (dev_a, dev_b, dev_c, N);
// stop tracking the time
hipEventRecord(stop, 0) ;
hipEventSynchronize(stop) ;
hipEventElapsedTime(&time, start, stop) ;
hipMemcpy(host_c.data(), dev_c, size, hipMemcpyDeviceToHost);
printf("Compute time on GPU: %3.6f ms \n", time);
// verify result on CPU
verify_result(host_a, host_b, host_c, N);
//free device memory
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <algorithm>
#include <cassert>
#include <cstdlib>
#include <functional>
#include <iostream>
#include <vector>
using std::cout;
using std::generate;
using std::vector;
#define SIZE 64
#define THREADS 32
#define CUDA_CALL(x) do { if((x)!=hipSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
#define CURAND_CALL(x) do { if((x)!=HIPRAND_STATUS_SUCCESS) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
__global__ void MatrixMul(const int *Md, const int *Nd, int *Pd, int Width) {
// Calculate the row index of the Pd element and M
int row = (blockIdx.y * blockDim.y) + threadIdx.y;
// Calculate the column idenx of Pd and N
int col = (blockIdx.x * blockDim.x) + threadIdx.x;
if((row < Width) && (col < Width)) {
// each thread computes one element of the block sub-matrix
for (int k = 0; k < Width; ++k) {
// dot product or corresponding row and column.
Pd[(row * Width) + col] += Md[(row * Width) + k] * Nd[(k * Width) + col];
}
}
}
// Check result on the CPU (single threaded)
void verify_result(vector<int> &a, vector<int> &b, vector<int> &c, int N) {
// Loop over every row...
float time;
hipEvent_t start, stop;
// start tracking the time
hipEventCreate(&start) ;
hipEventCreate(&stop) ;
hipEventRecord(start, 0) ;
for (int i = 0; i < N; i++) {
// Loop every column...
for (int j = 0; j < N; j++) {
// For every element in the row-column pair
int tmp = 0;
for (int k = 0; k < N; k++) {
// Accumulate the partial results
tmp += a[i * N + k] * b[k * N + j];
}
// Check against the CPU result
assert(tmp == c[i * N + j]);
}
}
hipEventRecord(stop, 0) ;
hipEventSynchronize(stop) ;
hipEventElapsedTime(&time, start, stop) ;
printf("Compute time on CPU: %3.6f ms \n", time);
}
int main(void){
// initialize event creation for time tracking
float time;
hipEvent_t start, stop;
// Matrix size of 32 x 32;
int N = SIZE;
printf("Matrix Size: %d x %d\n", N, N);
// size (in bytes) of matrix
size_t size = N * N * sizeof(int);
vector<int> host_a(N * N);
vector<int> host_b(N * N);
vector<int> host_c(N * N);
// generate random indices between 0 and 1.
generate(host_a.begin(), host_a.end(), []() {return rand() % 2; });
generate(host_b.begin(), host_b.end(), []() {return rand() % 2; });
// device memory allocation
int *dev_a, *dev_b, *dev_c;
hipMalloc(&dev_a, size);
hipMalloc(&dev_b, size);
hipMalloc(&dev_c, size);
//copy data from host to device
hipMemcpy(dev_a, host_a.data(), size, hipMemcpyHostToDevice);
hipMemcpy(dev_b, host_b.data(), size, hipMemcpyHostToDevice);
int BLOCKS = N/THREADS;
dim3 threads(THREADS, THREADS);
dim3 blocks(BLOCKS, BLOCKS);
// start tracking the time
hipEventCreate(&start) ;
hipEventCreate(&stop) ;
hipEventRecord(start, 0) ;
// launch kernal
printf("No. of blocks: %d x %d\n", BLOCKS, BLOCKS);
printf("No. of therads: %d x %d\n", THREADS, THREADS);
MatrixMul<<<blocks, threads>>> (dev_a, dev_b, dev_c, N);
// stop tracking the time
hipEventRecord(stop, 0) ;
hipEventSynchronize(stop) ;
hipEventElapsedTime(&time, start, stop) ;
hipMemcpy(host_c.data(), dev_c, size, hipMemcpyDeviceToHost);
printf("Compute time on GPU: %3.6f ms \n", time);
// verify result on CPU
verify_result(host_a, host_b, host_c, N);
//free device memory
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9MatrixMulPKiS0_Pii
.globl _Z9MatrixMulPKiS0_Pii
.p2align 8
.type _Z9MatrixMulPKiS0_Pii,@function
_Z9MatrixMulPKiS0_Pii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
v_mad_u64_u32 v[0:1], null, s14, s2, v[4:5]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max3_i32 v1, v2, v0, 0
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_3
v_mul_lo_u32 v4, v2, s4
s_load_b64 s[2:3], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v1, v4, v0
v_ashrrev_i32_e32 v5, 31, v4
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_load_b128 s[0:3], s[0:1], 0x0
global_load_b32 v6, v[2:3], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_mov_b32 s0, s4
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s0, 0
v_lshlrev_b64 v[7:8], 2, v[0:1]
v_add_nc_u32_e32 v0, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_load_b32 v1, v[4:5], off
global_load_b32 v9, v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[7:8], null, v9, v1, v[6:7]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v6, v7
global_store_b32 v[2:3], v7, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9MatrixMulPKiS0_Pii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9MatrixMulPKiS0_Pii, .Lfunc_end0-_Z9MatrixMulPKiS0_Pii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9MatrixMulPKiS0_Pii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9MatrixMulPKiS0_Pii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <algorithm>
#include <cassert>
#include <cstdlib>
#include <functional>
#include <iostream>
#include <vector>
using std::cout;
using std::generate;
using std::vector;
#define SIZE 64
#define THREADS 32
#define CUDA_CALL(x) do { if((x)!=hipSuccess) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
#define CURAND_CALL(x) do { if((x)!=HIPRAND_STATUS_SUCCESS) { \
printf("Error at %s:%d\n",__FILE__,__LINE__);\
return EXIT_FAILURE;}} while(0)
__global__ void MatrixMul(const int *Md, const int *Nd, int *Pd, int Width) {
// Calculate the row index of the Pd element and M
int row = (blockIdx.y * blockDim.y) + threadIdx.y;
// Calculate the column idenx of Pd and N
int col = (blockIdx.x * blockDim.x) + threadIdx.x;
if((row < Width) && (col < Width)) {
// each thread computes one element of the block sub-matrix
for (int k = 0; k < Width; ++k) {
// dot product or corresponding row and column.
Pd[(row * Width) + col] += Md[(row * Width) + k] * Nd[(k * Width) + col];
}
}
}
// Check result on the CPU (single threaded)
void verify_result(vector<int> &a, vector<int> &b, vector<int> &c, int N) {
// Loop over every row...
float time;
hipEvent_t start, stop;
// start tracking the time
hipEventCreate(&start) ;
hipEventCreate(&stop) ;
hipEventRecord(start, 0) ;
for (int i = 0; i < N; i++) {
// Loop every column...
for (int j = 0; j < N; j++) {
// For every element in the row-column pair
int tmp = 0;
for (int k = 0; k < N; k++) {
// Accumulate the partial results
tmp += a[i * N + k] * b[k * N + j];
}
// Check against the CPU result
assert(tmp == c[i * N + j]);
}
}
hipEventRecord(stop, 0) ;
hipEventSynchronize(stop) ;
hipEventElapsedTime(&time, start, stop) ;
printf("Compute time on CPU: %3.6f ms \n", time);
}
int main(void){
// initialize event creation for time tracking
float time;
hipEvent_t start, stop;
// Matrix size of 32 x 32;
int N = SIZE;
printf("Matrix Size: %d x %d\n", N, N);
// size (in bytes) of matrix
size_t size = N * N * sizeof(int);
vector<int> host_a(N * N);
vector<int> host_b(N * N);
vector<int> host_c(N * N);
// generate random indices between 0 and 1.
generate(host_a.begin(), host_a.end(), []() {return rand() % 2; });
generate(host_b.begin(), host_b.end(), []() {return rand() % 2; });
// device memory allocation
int *dev_a, *dev_b, *dev_c;
hipMalloc(&dev_a, size);
hipMalloc(&dev_b, size);
hipMalloc(&dev_c, size);
//copy data from host to device
hipMemcpy(dev_a, host_a.data(), size, hipMemcpyHostToDevice);
hipMemcpy(dev_b, host_b.data(), size, hipMemcpyHostToDevice);
int BLOCKS = N/THREADS;
dim3 threads(THREADS, THREADS);
dim3 blocks(BLOCKS, BLOCKS);
// start tracking the time
hipEventCreate(&start) ;
hipEventCreate(&stop) ;
hipEventRecord(start, 0) ;
// launch kernal
printf("No. of blocks: %d x %d\n", BLOCKS, BLOCKS);
printf("No. of therads: %d x %d\n", THREADS, THREADS);
MatrixMul<<<blocks, threads>>> (dev_a, dev_b, dev_c, N);
// stop tracking the time
hipEventRecord(stop, 0) ;
hipEventSynchronize(stop) ;
hipEventElapsedTime(&time, start, stop) ;
hipMemcpy(host_c.data(), dev_c, size, hipMemcpyDeviceToHost);
printf("Compute time on GPU: %3.6f ms \n", time);
// verify result on CPU
verify_result(host_a, host_b, host_c, N);
//free device memory
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
return 0;
} | .text
.file "matrixMultiply.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__MatrixMulPKiS0_Pii # -- Begin function _Z24__device_stub__MatrixMulPKiS0_Pii
.p2align 4, 0x90
.type _Z24__device_stub__MatrixMulPKiS0_Pii,@function
_Z24__device_stub__MatrixMulPKiS0_Pii: # @_Z24__device_stub__MatrixMulPKiS0_Pii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9MatrixMulPKiS0_Pii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__MatrixMulPKiS0_Pii, .Lfunc_end0-_Z24__device_stub__MatrixMulPKiS0_Pii
.cfi_endproc
# -- End function
.globl _Z13verify_resultRSt6vectorIiSaIiEES2_S2_i # -- Begin function _Z13verify_resultRSt6vectorIiSaIiEES2_S2_i
.p2align 4, 0x90
.type _Z13verify_resultRSt6vectorIiSaIiEES2_S2_i,@function
_Z13verify_resultRSt6vectorIiSaIiEES2_S2_i: # @_Z13verify_resultRSt6vectorIiSaIiEES2_S2_i
.cfi_startproc
# %bb.0: # %._crit_edge24
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 16(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq (%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z13verify_resultRSt6vectorIiSaIiEES2_S2_i, .Lfunc_end1-_Z13verify_resultRSt6vectorIiSaIiEES2_S2_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt6vectorIiSaIiEEC2EmRKS0_.exit
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %edi
movl $64, %esi
movl $64, %edx
xorl %eax, %eax
callq printf
.cfi_escape 0x2e, 0x00
movl $16384, %edi # imm = 0x4000
callq _Znwm
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $16384, %edx # imm = 0x4000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $16384, %edi # imm = 0x4000
callq _Znwm
.Ltmp1:
# %bb.1: # %_ZNSt6vectorIiSaIiEEC2EmRKS0_.exit45
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $16384, %edx # imm = 0x4000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.Ltmp3:
.cfi_escape 0x2e, 0x00
movl $16384, %edi # imm = 0x4000
callq _Znwm
.Ltmp4:
# %bb.2: # %_ZNSt6vectorIiSaIiEEC2EmRKS0_.exit46
movq %rax, %r15
.cfi_escape 0x2e, 0x00
xorl %r12d, %r12d
movl $16384, %edx # imm = 0x4000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
callq rand
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
andl $-2, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r12)
addq $4, %r12
cmpq $16384, %r12 # imm = 0x4000
jne .LBB2_3
# %bb.4: # %.lr.ph.i47.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_5: # %.lr.ph.i47
# =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
callq rand
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
andl $-2, %ecx
subl %ecx, %eax
movl %eax, (%r14,%r12)
addq $4, %r12
cmpq $16384, %r12 # imm = 0x4000
jne .LBB2_5
# %bb.6: # %_ZSt8generateIN9__gnu_cxx17__normal_iteratorIPiSt6vectorIiSaIiEEEEZ4mainEUlvE0_EvT_S8_T0_.exit
.Ltmp6:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
.Ltmp7:
# %bb.7: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit
.Ltmp8:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
.Ltmp9:
# %bb.8: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit49
.Ltmp10:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
.Ltmp11:
# %bb.9: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit50
movq 32(%rsp), %rdi
.Ltmp12:
.cfi_escape 0x2e, 0x00
movl $16384, %edx # imm = 0x4000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp13:
# %bb.10:
movq 24(%rsp), %rdi
.Ltmp14:
.cfi_escape 0x2e, 0x00
movl $16384, %edx # imm = 0x4000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp15:
# %bb.11:
.Ltmp17:
.cfi_escape 0x2e, 0x00
leaq 72(%rsp), %rdi
callq hipEventCreate
.Ltmp18:
# %bb.12:
.Ltmp19:
.cfi_escape 0x2e, 0x00
leaq 40(%rsp), %rdi
callq hipEventCreate
.Ltmp20:
# %bb.13:
movq 72(%rsp), %rdi
.Ltmp21:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp22:
# %bb.14:
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %edi
movl $2, %esi
movl $2, %edx
xorl %eax, %eax
callq printf
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %edi
movl $32, %esi
movl $32, %edx
xorl %eax, %eax
callq printf
.Ltmp23:
.cfi_escape 0x2e, 0x00
movabsq $8589934594, %rdi # imm = 0x200000002
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp24:
# %bb.15:
testl %eax, %eax
jne .LBB2_18
# %bb.16:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
movl $64, 52(%rsp)
leaq 144(%rsp), %rax
movq %rax, 80(%rsp)
leaq 136(%rsp), %rax
movq %rax, 88(%rsp)
leaq 128(%rsp), %rax
movq %rax, 96(%rsp)
leaq 52(%rsp), %rax
movq %rax, 104(%rsp)
.Ltmp25:
.cfi_escape 0x2e, 0x00
movq %rsp, %rdi
leaq 56(%rsp), %rsi
leaq 120(%rsp), %rdx
leaq 112(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp26:
# %bb.17: # %.noexc
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
.Ltmp27:
.cfi_escape 0x2e, 0x10
leaq 80(%rsp), %r9
movl $_Z9MatrixMulPKiS0_Pii, %edi
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp28:
.LBB2_18:
movq 40(%rsp), %rdi
.Ltmp29:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp30:
# %bb.19:
movq 40(%rsp), %rdi
.Ltmp31:
.cfi_escape 0x2e, 0x00
callq hipEventSynchronize
.Ltmp32:
# %bb.20:
movq 72(%rsp), %rsi
movq 40(%rsp), %rdx
.Ltmp33:
.cfi_escape 0x2e, 0x00
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
.Ltmp34:
# %bb.21:
movq 16(%rsp), %rsi
.Ltmp35:
.cfi_escape 0x2e, 0x00
movl $16384, %edx # imm = 0x4000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp36:
# %bb.22:
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %edi
movb $1, %al
callq printf
.Ltmp37:
.cfi_escape 0x2e, 0x00
leaq 80(%rsp), %rdi
callq hipEventCreate
.Ltmp38:
# %bb.23: # %.noexc52
.Ltmp39:
.cfi_escape 0x2e, 0x00
movq %rsp, %rdi
callq hipEventCreate
.Ltmp40:
# %bb.24: # %.noexc53
movq 80(%rsp), %rdi
.Ltmp41:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp42:
# %bb.25: # %.noexc54
movq (%rsp), %rdi
.Ltmp43:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp44:
# %bb.26: # %.noexc55
movq (%rsp), %rdi
.Ltmp45:
.cfi_escape 0x2e, 0x00
callq hipEventSynchronize
.Ltmp46:
# %bb.27: # %.noexc56
movq 80(%rsp), %rsi
movq (%rsp), %rdx
.Ltmp47:
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
callq hipEventElapsedTime
.Ltmp48:
# %bb.28: # %_Z13verify_resultRSt6vectorIiSaIiEES2_S2_i.exit
movss 56(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
.Ltmp49:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp50:
# %bb.29:
movq 24(%rsp), %rdi
.Ltmp51:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp52:
# %bb.30:
movq 16(%rsp), %rdi
.Ltmp53:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp54:
# %bb.31: # %_ZNSt6vectorIiSaIiEED2Ev.exit
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_33:
.cfi_def_cfa_offset 192
.Ltmp5:
movq %rax, %r12
jmp .LBB2_37
.LBB2_32:
.Ltmp2:
movq %rax, %r12
jmp .LBB2_38
.LBB2_35:
.Ltmp16:
jmp .LBB2_36
.LBB2_34:
.Ltmp55:
.LBB2_36: # %_ZNSt6vectorIiSaIiEED2Ev.exit63
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZdlPv
.LBB2_37: # %_ZNSt6vectorIiSaIiEED2Ev.exit65
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.LBB2_38: # %_ZNSt6vectorIiSaIiEED2Ev.exit67
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp6-.Ltmp4 # Call between .Ltmp4 and .Ltmp6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp15-.Ltmp6 # Call between .Ltmp6 and .Ltmp15
.uleb128 .Ltmp16-.Lfunc_begin0 # jumps to .Ltmp16
.byte 0 # On action: cleanup
.uleb128 .Ltmp17-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp54-.Ltmp17 # Call between .Ltmp17 and .Ltmp54
.uleb128 .Ltmp55-.Lfunc_begin0 # jumps to .Ltmp55
.byte 0 # On action: cleanup
.uleb128 .Ltmp54-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Lfunc_end2-.Ltmp54 # Call between .Ltmp54 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9MatrixMulPKiS0_Pii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9MatrixMulPKiS0_Pii,@object # @_Z9MatrixMulPKiS0_Pii
.section .rodata,"a",@progbits
.globl _Z9MatrixMulPKiS0_Pii
.p2align 3, 0x0
_Z9MatrixMulPKiS0_Pii:
.quad _Z24__device_stub__MatrixMulPKiS0_Pii
.size _Z9MatrixMulPKiS0_Pii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Compute time on CPU: %3.6f ms \n"
.size .L.str, 33
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Matrix Size: %d x %d\n"
.size .L.str.1, 22
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "No. of blocks: %d x %d\n"
.size .L.str.2, 24
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "No. of therads: %d x %d\n"
.size .L.str.3, 25
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Compute time on GPU: %3.6f ms \n"
.size .L.str.4, 33
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9MatrixMulPKiS0_Pii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__MatrixMulPKiS0_Pii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z9MatrixMulPKiS0_Pii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9MatrixMulPKiS0_Pii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0030*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e680000002600 */
/*0040*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R5, R5, c[0x0][0x0], R2 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R9, R9, c[0x0][0x4], R0 ; /* 0x0000010009097a24 */
/* 0x002fe200078e0200 */
/*0080*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fc80000000f00 */
/*0090*/ ISETP.GE.OR P0, PT, R9, c[0x0][0x178], P0 ; /* 0x00005e0009007a0c */
/* 0x000fc80000706670 */
/*00a0*/ ISETP.LT.OR P0, PT, R0, 0x1, P0 ; /* 0x000000010000780c */
/* 0x000fda0000701670 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R0, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x000fe20007ffe0ff */
/*00d0*/ IMAD R9, R9, c[0x0][0x178], RZ ; /* 0x00005e0009097a24 */
/* 0x000fe200078e02ff */
/*00e0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0100*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0110*/ IADD3 R3, R5, R9, RZ ; /* 0x0000000905037210 */
/* 0x000fe40007ffe0ff */
/*0120*/ LOP3.LUT R4, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300047812 */
/* 0x000fe400078ec0ff */
/*0130*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fc40000000f00 */
/*0140*/ IMAD.WIDE R2, R3, R8, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0208 */
/*0150*/ @!P0 BRA 0xcb0 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R11, -R4, c[0x0][0x178], RZ ; /* 0x00005e00040b7a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000162000c1e1900 */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ MOV R10, RZ ; /* 0x000000ff000a7202 */
/* 0x000fe20000000f00 */
/*01a0*/ IMAD.WIDE R12, R5, R8, c[0x0][0x168] ; /* 0x00005a00050c7625 */
/* 0x000fe200078e0208 */
/*01b0*/ ISETP.GT.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fda0003f04270 */
/*01c0*/ @!P0 BRA 0xae0 ; /* 0x0000091000008947 */
/* 0x001fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R11, 0xc, PT ; /* 0x0000000c0b00780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x7a0 ; /* 0x000005a000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*0220*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x004ea2000c1e1900 */
/*0230*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fca0008000f00 */
/*0240*/ IMAD.WIDE R6, R9, 0x4, R6 ; /* 0x0000000409067825 */
/* 0x000fca00078e0206 */
/*0250*/ LDG.E R16, [R6.64] ; /* 0x0000000406107981 */
/* 0x000ea4000c1e1900 */
/*0260*/ IMAD R19, R14, R16, R15 ; /* 0x000000100e137224 */
/* 0x024fe400078e020f */
/*0270*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0280*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0290*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea8000c1e1900 */
/*02a0*/ LDG.E R17, [R6.64+0x4] ; /* 0x0000040406117981 */
/* 0x000ea4000c1e1900 */
/*02b0*/ IMAD R21, R16, R17, R19 ; /* 0x0000001110157224 */
/* 0x004fc400078e0213 */
/*02c0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*02d0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*02e0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*02f0*/ LDG.E R12, [R6.64+0x8] ; /* 0x00000804060c7981 */
/* 0x000ea4000c1e1900 */
/*0300*/ IMAD R23, R18, R12, R21 ; /* 0x0000000c12177224 */
/* 0x004fc400078e0215 */
/*0310*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0210 */
/*0320*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0330*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000e28000c1e1900 */
/*0340*/ LDG.E R14, [R6.64+0xc] ; /* 0x00000c04060e7981 */
/* 0x000e24000c1e1900 */
/*0350*/ IMAD R19, R18, R14, R23 ; /* 0x0000000e12137224 */
/* 0x001fc400078e0217 */
/*0360*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0370*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0380*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e68000c1e1900 */
/*0390*/ LDG.E R16, [R6.64+0x10] ; /* 0x0000100406107981 */
/* 0x000e64000c1e1900 */
/*03a0*/ IMAD R21, R18, R16, R19 ; /* 0x0000001012157224 */
/* 0x002fc400078e0213 */
/*03b0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*03c0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*03d0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*03e0*/ LDG.E R12, [R6.64+0x14] ; /* 0x00001404060c7981 */
/* 0x000ea4000c1e1900 */
/*03f0*/ IMAD R23, R18, R12, R21 ; /* 0x0000000c12177224 */
/* 0x004fc400078e0215 */
/*0400*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0210 */
/*0410*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0420*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000e28000c1e1900 */
/*0430*/ LDG.E R14, [R6.64+0x18] ; /* 0x00001804060e7981 */
/* 0x000e24000c1e1900 */
/*0440*/ IMAD R19, R18, R14, R23 ; /* 0x0000000e12137224 */
/* 0x001fc400078e0217 */
/*0450*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0460*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0470*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e68000c1e1900 */
/*0480*/ LDG.E R16, [R6.64+0x1c] ; /* 0x00001c0406107981 */
/* 0x000e64000c1e1900 */
/*0490*/ IMAD R21, R18, R16, R19 ; /* 0x0000001012157224 */
/* 0x002fc400078e0213 */
/*04a0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*04b0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*04c0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*04d0*/ LDG.E R12, [R6.64+0x20] ; /* 0x00002004060c7981 */
/* 0x000ea4000c1e1900 */
/*04e0*/ IMAD R23, R18, R12, R21 ; /* 0x0000000c12177224 */
/* 0x004fc400078e0215 */
/*04f0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0210 */
/*0500*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0510*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000e28000c1e1900 */
/*0520*/ LDG.E R14, [R6.64+0x24] ; /* 0x00002404060e7981 */
/* 0x000e24000c1e1900 */
/*0530*/ IMAD R19, R18, R14, R23 ; /* 0x0000000e12137224 */
/* 0x001fc400078e0217 */
/*0540*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0550*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x000fe8000c101904 */
/*0560*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e68000c1e1900 */
/*0570*/ LDG.E R16, [R6.64+0x28] ; /* 0x0000280406107981 */
/* 0x000e64000c1e1900 */
/*0580*/ IMAD R21, R18, R16, R19 ; /* 0x0000001012157224 */
/* 0x002fc400078e0213 */
/*0590*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*05a0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*05b0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*05c0*/ LDG.E R12, [R6.64+0x2c] ; /* 0x00002c04060c7981 */
/* 0x000ea4000c1e1900 */
/*05d0*/ IMAD R23, R18, R12, R21 ; /* 0x0000000c12177224 */
/* 0x004fc400078e0215 */
/*05e0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0210 */
/*05f0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*0600*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000ea8000c1e1900 */
/*0610*/ LDG.E R14, [R6.64+0x30] ; /* 0x00003004060e7981 */
/* 0x000ea4000c1e1900 */
/*0620*/ IMAD R25, R18, R14, R23 ; /* 0x0000000e12197224 */
/* 0x004fc400078e0217 */
/*0630*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0640*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*0650*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e28000c1e1900 */
/*0660*/ LDG.E R16, [R6.64+0x34] ; /* 0x0000340406107981 */
/* 0x000e24000c1e1900 */
/*0670*/ IMAD R21, R18, R16, R25 ; /* 0x0000001012157224 */
/* 0x001fc400078e0219 */
/*0680*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*0690*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0005e8000c101904 */
/*06a0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000e68000c1e1900 */
/*06b0*/ LDG.E R12, [R6.64+0x38] ; /* 0x00003804060c7981 */
/* 0x000e62000c1e1900 */
/*06c0*/ IADD3 R11, R11, -0x10, RZ ; /* 0xfffffff00b0b7810 */
/* 0x000fe20007ffe0ff */
/*06d0*/ IMAD R23, R18, R12, R21 ; /* 0x0000000c12177224 */
/* 0x002fc400078e0215 */
/*06e0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*06f0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0700*/ LDG.E R13, [R6.64+0x3c] ; /* 0x00003c04060d7981 */
/* 0x000ee8000c1e1900 */
/*0710*/ LDG.E R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000ee2000c1e1900 */
/*0720*/ ISETP.GT.AND P1, PT, R11, 0xc, PT ; /* 0x0000000c0b00780c */
/* 0x000fe20003f24270 */
/*0730*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0740*/ IADD3 R10, R10, 0x10, RZ ; /* 0x000000100a0a7810 */
/* 0x000fc60007ffe0ff */
/*0750*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0760*/ IMAD R15, R12, R13, R23 ; /* 0x0000000d0c0f7224 */
/* 0x008fe400078e0217 */
/*0770*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0212 */
/*0780*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0005e4000c101904 */
/*0790*/ @P1 BRA 0x210 ; /* 0xfffffa7000001947 */
/* 0x000fea000383ffff */
/*07a0*/ ISETP.GT.AND P1, PT, R11, 0x4, PT ; /* 0x000000040b00780c */
/* 0x000fda0003f24270 */
/*07b0*/ @!P1 BRA 0xac0 ; /* 0x0000030000009947 */
/* 0x000fea0003800000 */
/*07c0*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*07d0*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ee2000c1e1900 */
/*07e0*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fca0008000f00 */
/*07f0*/ IMAD.WIDE R6, R9, 0x4, R6 ; /* 0x0000000409067825 */
/* 0x000fca00078e0206 */
/*0800*/ LDG.E R16, [R6.64] ; /* 0x0000000406107981 */
/* 0x000ee4000c1e1900 */
/*0810*/ IMAD R19, R14, R16, R15 ; /* 0x000000100e137224 */
/* 0x028fe400078e020f */
/*0820*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x004fc600078e020c */
/*0830*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0840*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea8000c1e1900 */
/*0850*/ LDG.E R17, [R6.64+0x4] ; /* 0x0000040406117981 */
/* 0x000ea4000c1e1900 */
/*0860*/ IMAD R21, R16, R17, R19 ; /* 0x0000001110157224 */
/* 0x004fc400078e0213 */
/*0870*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*0880*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0890*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*08a0*/ LDG.E R12, [R6.64+0x8] ; /* 0x00000804060c7981 */
/* 0x000ea4000c1e1900 */
/*08b0*/ IMAD R23, R18, R12, R21 ; /* 0x0000000c12177224 */
/* 0x004fc400078e0215 */
/*08c0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0210 */
/*08d0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*08e0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000e28000c1e1900 */
/*08f0*/ LDG.E R14, [R6.64+0xc] ; /* 0x00000c04060e7981 */
/* 0x000e24000c1e1900 */
/*0900*/ IMAD R19, R18, R14, R23 ; /* 0x0000000e12137224 */
/* 0x001fc400078e0217 */
/*0910*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0920*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0930*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e68000c1e1900 */
/*0940*/ LDG.E R16, [R6.64+0x10] ; /* 0x0000100406107981 */
/* 0x000e64000c1e1900 */
/*0950*/ IMAD R21, R18, R16, R19 ; /* 0x0000001012157224 */
/* 0x002fc400078e0213 */
/*0960*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*0970*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0980*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*0990*/ LDG.E R12, [R6.64+0x14] ; /* 0x00001404060c7981 */
/* 0x000ea4000c1e1900 */
/*09a0*/ IMAD R23, R18, R12, R21 ; /* 0x0000000c12177224 */
/* 0x004fc400078e0215 */
/*09b0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0210 */
/*09c0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*09d0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R14, [R6.64+0x18] ; /* 0x00001804060e7981 */
/* 0x000ea4000c1e1900 */
/*09f0*/ IMAD R25, R18, R14, R23 ; /* 0x0000000e12197224 */
/* 0x004fc400078e0217 */
/*0a00*/ IMAD.WIDE R18, R0, 0x4, R12 ; /* 0x0000000400127825 */
/* 0x001fc600078e020c */
/*0a10*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0a20*/ LDG.E R15, [R6.64+0x1c] ; /* 0x00001c04060f7981 */
/* 0x000ea8000c1e1900 */
/*0a30*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000ea2000c1e1900 */
/*0a40*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0a50*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0a60*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0212 */
/*0a70*/ IADD3 R10, R10, 0x8, RZ ; /* 0x000000080a0a7810 */
/* 0x000fc40007ffe0ff */
/*0a80*/ IADD3 R11, R11, -0x8, RZ ; /* 0xfffffff80b0b7810 */
/* 0x000fe20007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ IMAD R15, R14, R15, R25 ; /* 0x0000000f0e0f7224 */
/* 0x004fca00078e0219 */
/*0ab0*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0003e8000c101904 */
/*0ac0*/ ISETP.NE.OR P0, PT, R11, RZ, P0 ; /* 0x000000ff0b00720c */
/* 0x000fda0000705670 */
/*0ad0*/ @!P0 BRA 0xcb0 ; /* 0x000001d000008947 */
/* 0x000fea0003800000 */
/*0ae0*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe20008000f00 */
/*0af0*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ee2000c1e1900 */
/*0b00*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fca0008000f00 */
/*0b10*/ IMAD.WIDE R6, R9, 0x4, R6 ; /* 0x0000000409067825 */
/* 0x000fca00078e0206 */
/*0b20*/ LDG.E R16, [R6.64] ; /* 0x0000000406107981 */
/* 0x000ee4000c1e1900 */
/*0b30*/ IMAD R21, R14, R16, R15 ; /* 0x000000100e157224 */
/* 0x02efe400078e020f */
/*0b40*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0b50*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*0b60*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea8000c1e1900 */
/*0b70*/ LDG.E R17, [R6.64+0x4] ; /* 0x0000040406117981 */
/* 0x000ea4000c1e1900 */
/*0b80*/ IMAD R23, R16, R17, R21 ; /* 0x0000001110177224 */
/* 0x004fc400078e0215 */
/*0b90*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*0ba0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0001e8000c101904 */
/*0bb0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*0bc0*/ LDG.E R12, [R6.64+0x8] ; /* 0x00000804060c7981 */
/* 0x000ea2000c1e1900 */
/*0bd0*/ IADD3 R11, R11, -0x4, RZ ; /* 0xfffffffc0b0b7810 */
/* 0x000fe20007ffe0ff */
/*0be0*/ IMAD R25, R18, R12, R23 ; /* 0x0000000c12197224 */
/* 0x004fc400078e0217 */
/*0bf0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*0c00*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0001e8000c101904 */
/*0c10*/ LDG.E R13, [R6.64+0xc] ; /* 0x00000c04060d7981 */
/* 0x000ea8000c1e1900 */
/*0c20*/ LDG.E R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000ea2000c1e1900 */
/*0c30*/ ISETP.NE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f05270 */
/*0c40*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0c50*/ IADD3 R10, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc60007ffe0ff */
/*0c60*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0c70*/ IMAD R15, R12, R13, R25 ; /* 0x0000000d0c0f7224 */
/* 0x004fe400078e0219 */
/*0c80*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0212 */
/*0c90*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0001e4000c101904 */
/*0ca0*/ @P0 BRA 0xae0 ; /* 0xfffffe3000000947 */
/* 0x001fea000383ffff */
/*0cb0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0cc0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0cd0*/ LDG.E R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000162000c1e1900 */
/*0ce0*/ IADD3 R7, R9, R10, RZ ; /* 0x0000000a09077210 */
/* 0x000fe20007ffe0ff */
/*0cf0*/ IMAD R5, R10, c[0x0][0x178], R5 ; /* 0x00005e000a057a24 */
/* 0x000fc800078e0205 */
/*0d00*/ IMAD.WIDE R6, R7, R8, c[0x0][0x160] ; /* 0x0000580007067625 */
/* 0x000fc800078e0208 */
/*0d10*/ IMAD.WIDE R8, R5, R8, c[0x0][0x168] ; /* 0x00005a0005087625 */
/* 0x001fca00078e0208 */
/*0d20*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x0010e8000c1e1900 */
/*0d30*/ LDG.E R5, [R6.64] ; /* 0x0000000406057981 */
/* 0x0008e2000c1e1900 */
/*0d40*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fc80007ffe0ff */
/*0d50*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0d60*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0d70*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x010fc80007f3e0ff */
/*0d80*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0d90*/ IMAD R11, R10, R5, R11 ; /* 0x000000050a0b7224 */
/* 0x028fca00078e020b */
/*0da0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e2000c101904 */
/*0db0*/ @P0 BRA 0xd20 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0dc0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0dd0*/ BRA 0xdd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9MatrixMulPKiS0_Pii
.globl _Z9MatrixMulPKiS0_Pii
.p2align 8
.type _Z9MatrixMulPKiS0_Pii,@function
_Z9MatrixMulPKiS0_Pii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
v_mad_u64_u32 v[0:1], null, s14, s2, v[4:5]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max3_i32 v1, v2, v0, 0
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_3
v_mul_lo_u32 v4, v2, s4
s_load_b64 s[2:3], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v1, v4, v0
v_ashrrev_i32_e32 v5, 31, v4
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_load_b128 s[0:3], s[0:1], 0x0
global_load_b32 v6, v[2:3], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_mov_b32 s0, s4
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s0, 0
v_lshlrev_b64 v[7:8], 2, v[0:1]
v_add_nc_u32_e32 v0, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_load_b32 v1, v[4:5], off
global_load_b32 v9, v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[7:8], null, v9, v1, v[6:7]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v6, v7
global_store_b32 v[2:3], v7, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9MatrixMulPKiS0_Pii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9MatrixMulPKiS0_Pii, .Lfunc_end0-_Z9MatrixMulPKiS0_Pii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9MatrixMulPKiS0_Pii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9MatrixMulPKiS0_Pii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005d73d_00000000-6_matrixMultiply.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4930:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4930:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Compute time on CPU: %3.6f ms \n"
.text
.globl _Z13verify_resultRSt6vectorIiSaIiEES2_S2_i
.type _Z13verify_resultRSt6vectorIiSaIiEES2_S2_i, @function
_Z13verify_resultRSt6vectorIiSaIiEES2_S2_i:
.LFB4920:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movl %ecx, %ebx
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %esi
movl $0, %edi
testl %ebx, %ebx
jg .L4
.L5:
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
leal 1(%rsi), %eax
cmpl %edx, %esi
je .L5
movl %eax, %esi
.L4:
movl %edi, %ecx
.L8:
movl $0, %eax
.L6:
movl %eax, %edx
addl $1, %eax
cmpl %eax, %ebx
jne .L6
leal 1(%rcx), %eax
cmpl %edx, %ecx
je .L7
movl %eax, %ecx
jmp .L8
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4920:
.size _Z13verify_resultRSt6vectorIiSaIiEES2_S2_i, .-_Z13verify_resultRSt6vectorIiSaIiEES2_S2_i
.globl _Z35__device_stub__Z9MatrixMulPKiS0_PiiPKiS0_Pii
.type _Z35__device_stub__Z9MatrixMulPKiS0_PiiPKiS0_Pii, @function
_Z35__device_stub__Z9MatrixMulPKiS0_PiiPKiS0_Pii:
.LFB4952:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9MatrixMulPKiS0_Pii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4952:
.size _Z35__device_stub__Z9MatrixMulPKiS0_PiiPKiS0_Pii, .-_Z35__device_stub__Z9MatrixMulPKiS0_PiiPKiS0_Pii
.globl _Z9MatrixMulPKiS0_Pii
.type _Z9MatrixMulPKiS0_Pii, @function
_Z9MatrixMulPKiS0_Pii:
.LFB4953:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9MatrixMulPKiS0_PiiPKiS0_Pii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4953:
.size _Z9MatrixMulPKiS0_Pii, .-_Z9MatrixMulPKiS0_Pii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z9MatrixMulPKiS0_Pii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4955:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9MatrixMulPKiS0_Pii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4955:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._ZNSt6vectorIiSaIiEEC2EmRKS0_.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "cannot create std::vector larger than max_size()"
.section .text._ZNSt6vectorIiSaIiEEC2EmRKS0_,"axG",@progbits,_ZNSt6vectorIiSaIiEEC5EmRKS0_,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEEC2EmRKS0_
.type _ZNSt6vectorIiSaIiEEC2EmRKS0_, @function
_ZNSt6vectorIiSaIiEEC2EmRKS0_:
.LFB5270:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %rax
shrq $61, %rax
jne .L35
movq %rdi, %rbx
movq %rsi, %rbp
movq $0, (%rdi)
movq $0, 8(%rdi)
movq $0, 16(%rdi)
testq %rsi, %rsi
je .L27
leaq 0(,%rsi,4), %r12
movq %r12, %rdi
call _Znwm@PLT
movq %rax, (%rbx)
movq %rax, 8(%rbx)
leaq (%rax,%r12), %rdx
movq %rdx, 16(%rbx)
movl $0, (%rax)
addq $4, %rax
cmpq $1, %rbp
je .L30
cmpq %rax, %rdx
je .L31
.L29:
movl $0, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L29
jmp .L28
.L35:
leaq .LC2(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L30:
movq %rax, %rdx
jmp .L28
.L31:
movq %rax, %rdx
jmp .L28
.L27:
movq $0, (%rdi)
movq $0, 16(%rdi)
movl $0, %edx
.L28:
movq %rdx, 8(%rbx)
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5270:
.size _ZNSt6vectorIiSaIiEEC2EmRKS0_, .-_ZNSt6vectorIiSaIiEEC2EmRKS0_
.weak _ZNSt6vectorIiSaIiEEC1EmRKS0_
.set _ZNSt6vectorIiSaIiEEC1EmRKS0_,_ZNSt6vectorIiSaIiEEC2EmRKS0_
.section .text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEED2Ev
.type _ZNSt6vectorIiSaIiEED2Ev, @function
_ZNSt6vectorIiSaIiEED2Ev:
.LFB5273:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L39
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L39:
ret
.cfi_endproc
.LFE5273:
.size _ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev
.weak _ZNSt6vectorIiSaIiEED1Ev
.set _ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev
.section .rodata.str1.1
.LC3:
.string "Matrix Size: %d x %d\n"
.LC4:
.string "No. of blocks: %d x %d\n"
.LC5:
.string "No. of therads: %d x %d\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "Compute time on GPU: %3.6f ms \n"
.text
.globl main
.type main, @function
main:
.LFB4921:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4921
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $184, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movl $64, %ecx
movl $64, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
.LEHB0:
call __printf_chk@PLT
leaq 144(%rsp), %rbx
leaq 80(%rsp), %rdi
movq %rbx, %rdx
movl $4096, %esi
call _ZNSt6vectorIiSaIiEEC1EmRKS0_
.LEHE0:
leaq 112(%rsp), %rdi
movq %rbx, %rdx
movl $4096, %esi
.LEHB1:
call _ZNSt6vectorIiSaIiEEC1EmRKS0_
.LEHE1:
leaq 68(%rsp), %rdx
movq %rbx, %rdi
movl $4096, %esi
.LEHB2:
call _ZNSt6vectorIiSaIiEEC1EmRKS0_
.LEHE2:
movq 88(%rsp), %rbp
movq 80(%rsp), %r13
cmpq %rbp, %r13
je .L43
movq %r13, %rbx
.L44:
call rand@PLT
movl %eax, %edx
shrl $31, %edx
addl %edx, %eax
andl $1, %eax
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbx, %rbp
jne .L44
.L43:
movq 120(%rsp), %rbp
movq 112(%rsp), %r12
cmpq %rbp, %r12
je .L45
movq %r12, %rbx
.L46:
call rand@PLT
movl %eax, %edx
shrl $31, %edx
addl %edx, %eax
andl $1, %eax
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbx, %rbp
jne .L46
.L45:
leaq 32(%rsp), %rdi
movl $16384, %esi
.LEHB3:
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $16384, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $16384, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $16384, %edx
movq %r13, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16384, %edx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 56(%rsp)
movl $32, 60(%rsp)
movl $1, 64(%rsp)
movl $2, 68(%rsp)
movl $2, 72(%rsp)
movl $1, 76(%rsp)
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movl $2, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $32, %ecx
movl $32, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 64(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movq 68(%rsp), %rdi
movl 76(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L47
movl $64, %ecx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z35__device_stub__Z9MatrixMulPKiS0_PiiPKiS0_Pii
.L47:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $2, %ecx
movl $16384, %edx
movq 48(%rsp), %rsi
movq 144(%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 144(%rsp), %rdx
leaq 112(%rsp), %rsi
leaq 80(%rsp), %rdi
movl $64, %ecx
call _Z13verify_resultRSt6vectorIiSaIiEES2_S2_i
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
.LEHE3:
leaq 144(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
leaq 112(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
leaq 80(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L60
movl $0, %eax
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 144(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
.L49:
leaq 112(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
.L50:
leaq 80(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 168(%rsp), %rax
subq %fs:40, %rax
je .L51
call __stack_chk_fail@PLT
.L54:
endbr64
movq %rax, %rbx
jmp .L49
.L53:
endbr64
movq %rax, %rbx
jmp .L50
.L51:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L60:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4921:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4921:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4921-.LLSDACSB4921
.LLSDACSB4921:
.uleb128 .LEHB0-.LFB4921
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4921
.uleb128 .LEHE1-.LEHB1
.uleb128 .L53-.LFB4921
.uleb128 0
.uleb128 .LEHB2-.LFB4921
.uleb128 .LEHE2-.LEHB2
.uleb128 .L54-.LFB4921
.uleb128 0
.uleb128 .LEHB3-.LFB4921
.uleb128 .LEHE3-.LEHB3
.uleb128 .L55-.LFB4921
.uleb128 0
.uleb128 .LEHB4-.LFB4921
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE4921:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixMultiply.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__MatrixMulPKiS0_Pii # -- Begin function _Z24__device_stub__MatrixMulPKiS0_Pii
.p2align 4, 0x90
.type _Z24__device_stub__MatrixMulPKiS0_Pii,@function
_Z24__device_stub__MatrixMulPKiS0_Pii: # @_Z24__device_stub__MatrixMulPKiS0_Pii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9MatrixMulPKiS0_Pii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__MatrixMulPKiS0_Pii, .Lfunc_end0-_Z24__device_stub__MatrixMulPKiS0_Pii
.cfi_endproc
# -- End function
.globl _Z13verify_resultRSt6vectorIiSaIiEES2_S2_i # -- Begin function _Z13verify_resultRSt6vectorIiSaIiEES2_S2_i
.p2align 4, 0x90
.type _Z13verify_resultRSt6vectorIiSaIiEES2_S2_i,@function
_Z13verify_resultRSt6vectorIiSaIiEES2_S2_i: # @_Z13verify_resultRSt6vectorIiSaIiEES2_S2_i
.cfi_startproc
# %bb.0: # %._crit_edge24
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 16(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq (%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z13verify_resultRSt6vectorIiSaIiEES2_S2_i, .Lfunc_end1-_Z13verify_resultRSt6vectorIiSaIiEES2_S2_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt6vectorIiSaIiEEC2EmRKS0_.exit
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %edi
movl $64, %esi
movl $64, %edx
xorl %eax, %eax
callq printf
.cfi_escape 0x2e, 0x00
movl $16384, %edi # imm = 0x4000
callq _Znwm
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $16384, %edx # imm = 0x4000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $16384, %edi # imm = 0x4000
callq _Znwm
.Ltmp1:
# %bb.1: # %_ZNSt6vectorIiSaIiEEC2EmRKS0_.exit45
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movl $16384, %edx # imm = 0x4000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.Ltmp3:
.cfi_escape 0x2e, 0x00
movl $16384, %edi # imm = 0x4000
callq _Znwm
.Ltmp4:
# %bb.2: # %_ZNSt6vectorIiSaIiEEC2EmRKS0_.exit46
movq %rax, %r15
.cfi_escape 0x2e, 0x00
xorl %r12d, %r12d
movl $16384, %edx # imm = 0x4000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
callq rand
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
andl $-2, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r12)
addq $4, %r12
cmpq $16384, %r12 # imm = 0x4000
jne .LBB2_3
# %bb.4: # %.lr.ph.i47.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_5: # %.lr.ph.i47
# =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
callq rand
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
andl $-2, %ecx
subl %ecx, %eax
movl %eax, (%r14,%r12)
addq $4, %r12
cmpq $16384, %r12 # imm = 0x4000
jne .LBB2_5
# %bb.6: # %_ZSt8generateIN9__gnu_cxx17__normal_iteratorIPiSt6vectorIiSaIiEEEEZ4mainEUlvE0_EvT_S8_T0_.exit
.Ltmp6:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
.Ltmp7:
# %bb.7: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit
.Ltmp8:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
.Ltmp9:
# %bb.8: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit49
.Ltmp10:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movl $16384, %esi # imm = 0x4000
callq hipMalloc
.Ltmp11:
# %bb.9: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit50
movq 32(%rsp), %rdi
.Ltmp12:
.cfi_escape 0x2e, 0x00
movl $16384, %edx # imm = 0x4000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp13:
# %bb.10:
movq 24(%rsp), %rdi
.Ltmp14:
.cfi_escape 0x2e, 0x00
movl $16384, %edx # imm = 0x4000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp15:
# %bb.11:
.Ltmp17:
.cfi_escape 0x2e, 0x00
leaq 72(%rsp), %rdi
callq hipEventCreate
.Ltmp18:
# %bb.12:
.Ltmp19:
.cfi_escape 0x2e, 0x00
leaq 40(%rsp), %rdi
callq hipEventCreate
.Ltmp20:
# %bb.13:
movq 72(%rsp), %rdi
.Ltmp21:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp22:
# %bb.14:
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %edi
movl $2, %esi
movl $2, %edx
xorl %eax, %eax
callq printf
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %edi
movl $32, %esi
movl $32, %edx
xorl %eax, %eax
callq printf
.Ltmp23:
.cfi_escape 0x2e, 0x00
movabsq $8589934594, %rdi # imm = 0x200000002
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp24:
# %bb.15:
testl %eax, %eax
jne .LBB2_18
# %bb.16:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
movl $64, 52(%rsp)
leaq 144(%rsp), %rax
movq %rax, 80(%rsp)
leaq 136(%rsp), %rax
movq %rax, 88(%rsp)
leaq 128(%rsp), %rax
movq %rax, 96(%rsp)
leaq 52(%rsp), %rax
movq %rax, 104(%rsp)
.Ltmp25:
.cfi_escape 0x2e, 0x00
movq %rsp, %rdi
leaq 56(%rsp), %rsi
leaq 120(%rsp), %rdx
leaq 112(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp26:
# %bb.17: # %.noexc
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
.Ltmp27:
.cfi_escape 0x2e, 0x10
leaq 80(%rsp), %r9
movl $_Z9MatrixMulPKiS0_Pii, %edi
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp28:
.LBB2_18:
movq 40(%rsp), %rdi
.Ltmp29:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp30:
# %bb.19:
movq 40(%rsp), %rdi
.Ltmp31:
.cfi_escape 0x2e, 0x00
callq hipEventSynchronize
.Ltmp32:
# %bb.20:
movq 72(%rsp), %rsi
movq 40(%rsp), %rdx
.Ltmp33:
.cfi_escape 0x2e, 0x00
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
.Ltmp34:
# %bb.21:
movq 16(%rsp), %rsi
.Ltmp35:
.cfi_escape 0x2e, 0x00
movl $16384, %edx # imm = 0x4000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp36:
# %bb.22:
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movl $.L.str.4, %edi
movb $1, %al
callq printf
.Ltmp37:
.cfi_escape 0x2e, 0x00
leaq 80(%rsp), %rdi
callq hipEventCreate
.Ltmp38:
# %bb.23: # %.noexc52
.Ltmp39:
.cfi_escape 0x2e, 0x00
movq %rsp, %rdi
callq hipEventCreate
.Ltmp40:
# %bb.24: # %.noexc53
movq 80(%rsp), %rdi
.Ltmp41:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp42:
# %bb.25: # %.noexc54
movq (%rsp), %rdi
.Ltmp43:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp44:
# %bb.26: # %.noexc55
movq (%rsp), %rdi
.Ltmp45:
.cfi_escape 0x2e, 0x00
callq hipEventSynchronize
.Ltmp46:
# %bb.27: # %.noexc56
movq 80(%rsp), %rsi
movq (%rsp), %rdx
.Ltmp47:
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
callq hipEventElapsedTime
.Ltmp48:
# %bb.28: # %_Z13verify_resultRSt6vectorIiSaIiEES2_S2_i.exit
movss 56(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
movb $1, %al
callq printf
movq 32(%rsp), %rdi
.Ltmp49:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp50:
# %bb.29:
movq 24(%rsp), %rdi
.Ltmp51:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp52:
# %bb.30:
movq 16(%rsp), %rdi
.Ltmp53:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp54:
# %bb.31: # %_ZNSt6vectorIiSaIiEED2Ev.exit
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_33:
.cfi_def_cfa_offset 192
.Ltmp5:
movq %rax, %r12
jmp .LBB2_37
.LBB2_32:
.Ltmp2:
movq %rax, %r12
jmp .LBB2_38
.LBB2_35:
.Ltmp16:
jmp .LBB2_36
.LBB2_34:
.Ltmp55:
.LBB2_36: # %_ZNSt6vectorIiSaIiEED2Ev.exit63
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZdlPv
.LBB2_37: # %_ZNSt6vectorIiSaIiEED2Ev.exit65
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.LBB2_38: # %_ZNSt6vectorIiSaIiEED2Ev.exit67
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp6-.Ltmp4 # Call between .Ltmp4 and .Ltmp6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp15-.Ltmp6 # Call between .Ltmp6 and .Ltmp15
.uleb128 .Ltmp16-.Lfunc_begin0 # jumps to .Ltmp16
.byte 0 # On action: cleanup
.uleb128 .Ltmp17-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp54-.Ltmp17 # Call between .Ltmp17 and .Ltmp54
.uleb128 .Ltmp55-.Lfunc_begin0 # jumps to .Ltmp55
.byte 0 # On action: cleanup
.uleb128 .Ltmp54-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Lfunc_end2-.Ltmp54 # Call between .Ltmp54 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9MatrixMulPKiS0_Pii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9MatrixMulPKiS0_Pii,@object # @_Z9MatrixMulPKiS0_Pii
.section .rodata,"a",@progbits
.globl _Z9MatrixMulPKiS0_Pii
.p2align 3, 0x0
_Z9MatrixMulPKiS0_Pii:
.quad _Z24__device_stub__MatrixMulPKiS0_Pii
.size _Z9MatrixMulPKiS0_Pii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Compute time on CPU: %3.6f ms \n"
.size .L.str, 33
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Matrix Size: %d x %d\n"
.size .L.str.1, 22
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "No. of blocks: %d x %d\n"
.size .L.str.2, 24
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "No. of therads: %d x %d\n"
.size .L.str.3, 25
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Compute time on GPU: %3.6f ms \n"
.size .L.str.4, 33
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9MatrixMulPKiS0_Pii"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__MatrixMulPKiS0_Pii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z9MatrixMulPKiS0_Pii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <time.h>
#include <cuda.h>
#define M 400
#define N 400
#define R 400
#define THREADS_PER_BLOCK 512
__global__ void gpu_matmul(int *a, int *b, int *c, int m, int n, int r)
{
int i = threadIdx.y + blockIdx.y * blockDim.y;
int j = threadIdx.x + blockIdx.x * blockDim.x;
int sum = 0;
if (i < n && j < n)
{
for(int k = 0; k < n; k++)
{
sum += a[i*n+k]*b[k*n+j];
}
}
c[i*n+j] = sum;
}
void cpu_matmul(int *a, int *b, int *c, int m, int n, int r)
{
int sum;
for (int i = 0; i < m; i++)
{
for (int j = 0; j < r; j++)
{
sum = 0;
for (int k = 0; k < n; k++)
{
sum += a[i*m+k]*b[k*n+j];
}
c[i*m+j] = sum;
}
}
}
void random_matrix(int *a, int m, int n)
{
for (int i = 0; i < m; i++)
{
for (int j = 0; j < n; j++)
{
a[i*m+j] = rand() % 100;
}
}
}
int main(void)
{
int *a, *b, *c, *c2;
int *d_a, *d_b, *d_c;
long a_size, b_size, c_size;
long size_int = sizeof(int);
double elapsed;
clock_t initial, final;
cudaError_t error;
a_size = M * N * size_int;
b_size = N * R * size_int;
c_size = M * R * size_int;
//Allocate memory on host for arrays a, b, and c (flattened 2D arrays)
a = (int *)malloc(a_size);
b = (int *)malloc(b_size);
c = (int *)malloc(c_size);
c2 = (int *)malloc(c_size);
//Allocate memory on device for a, b, and c
if ((error = cudaMalloc((void **)&d_a, a_size)) != cudaSuccess)
{
printf("Error allocating d_a: %s in %s on line %d\n", cudaGetErrorString(error), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
if ((error = cudaMalloc((void **)&d_b, b_size)) != cudaSuccess)
{
printf("Error allocating d_b: %s in %s on line %d\n", cudaGetErrorString(error), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
if ((error = cudaMalloc((void **)&d_c, c_size)) != cudaSuccess)
{
printf("Error allocating d_c: %s in %s on line %d\n", cudaGetErrorString(error), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
random_matrix(a, M, N);
random_matrix(b, N, R);
if ((error = cudaMemcpy(d_a, a, a_size, cudaMemcpyHostToDevice)) != cudaSuccess)
{
printf("Error copying a to d_a: %s in %s on line %d\n", cudaGetErrorString(error), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
if ((error = cudaMemcpy(d_b, b, b_size, cudaMemcpyHostToDevice)) != cudaSuccess)
{
printf("Error copying b to d_b: %s in %s on line %d\n", cudaGetErrorString(error), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
cudaDeviceSynchronize();
printf("\nCPU vs. GPU: Multiplying %dx%d by %dx%d Matrix\n", M, N, N, R);
printf("====================================================\n");
initial = clock();
gpu_matmul<<<1,4>>>(d_a, d_b, d_c, M, N, R);
cudaDeviceSynchronize();
final = clock();
elapsed = (double)(final - initial) / CLOCKS_PER_SEC;
printf("GPU:\t\t%e seconds\n", elapsed);
initial = clock();
cpu_matmul(a, b, c, M, N, R);
final = clock();
elapsed = (double)(final - initial) / CLOCKS_PER_SEC;
printf("CPU:\t\t%e seconds\n\n", elapsed);
cudaMemcpy(c2, d_c, c_size, cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
for (int i = 0; i < M; i++)
{
for (int j = 0; j < R; j++)
{
printf("%d\t\t%d\t\t%d\n", c[i*M+j], c2[i*M+j], c[i*M+j] == c2[i*M+j]);
}
}
free(a); free(b); free(c);
cudaFree(d_a); cudaFree(d_b); cudaFree(d_c);
return 0;
} | code for sm_80
Function : _Z10gpu_matmulPiS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0xc00 ; /* 0x00000bc000007945 */
/* 0x000fe20003800000 */
/*0040*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0060*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0070*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0090*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fe20003f06270 */
/*00a0*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fe200078e0202 */
/*00b0*/ MOV R2, c[0x0][0x17c] ; /* 0x00005f0000027a02 */
/* 0x000fc80000000f00 */
/*00c0*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x17c], P0 ; /* 0x00005f0003007a0c */
/* 0x000fc80000706670 */
/*00d0*/ ISETP.LT.OR P0, PT, R2, 0x1, P0 ; /* 0x000000010200780c */
/* 0x000fda0000701670 */
/*00e0*/ @P0 BRA 0xbf0 ; /* 0x00000b0000000947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0100*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0120*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fd20000000f00 */
/*0140*/ @!P0 BRA 0xaf0 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R6, -R5, c[0x0][0x17c], RZ ; /* 0x00005f0005067a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ IMAD R7, R3, c[0x0][0x17c], RZ ; /* 0x00005f0003077a24 */
/* 0x000fe200078e02ff */
/*0190*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*01a0*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fca0000000f00 */
/*01b0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x168] ; /* 0x00005a0000087625 */
/* 0x000fcc00078e0209 */
/*01c0*/ @!P0 BRA 0x960 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x6a0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ MOV R14, UR6 ; /* 0x00000006000e7c02 */
/* 0x000fe20008000f00 */
/*0220*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a2000c1e1900 */
/*0230*/ MOV R15, UR7 ; /* 0x00000007000f7c02 */
/* 0x000fca0008000f00 */
/*0240*/ IMAD.WIDE R14, R7, 0x4, R14 ; /* 0x00000004070e7825 */
/* 0x000fca00078e020e */
/*0250*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fc600078e0208 */
/*0270*/ LDG.E R18, [R14.64+0x4] ; /* 0x000004040e127981 */
/* 0x000ee6000c1e1900 */
/*0280*/ IMAD.WIDE R22, R2.reuse, 0x4, R8 ; /* 0x0000000402167825 */
/* 0x040fe200078e0208 */
/*0290*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x0000e8000c1e1900 */
/*02a0*/ LDG.E R28, [R22.64] ; /* 0x00000004161c7981 */
/* 0x000322000c1e1900 */
/*02b0*/ IMAD.WIDE R26, R2, 0x4, R22 ; /* 0x00000004021a7825 */
/* 0x000fc600078e0216 */
/*02c0*/ LDG.E R29, [R14.64+0x8] ; /* 0x000008040e1d7981 */
/* 0x000f26000c1e1900 */
/*02d0*/ IMAD.WIDE R12, R2.reuse, 0x4, R26 ; /* 0x00000004020c7825 */
/* 0x040fe200078e021a */
/*02e0*/ LDG.E R16, [R26.64] ; /* 0x000000041a107981 */
/* 0x000b28000c1e1900 */
/*02f0*/ LDG.E R17, [R14.64+0xc] ; /* 0x00000c040e117981 */
/* 0x000f28000c1e1900 */
/*0300*/ LDG.E R20, [R14.64+0x10] ; /* 0x000010040e147981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000328000c1e1900 */
/*0320*/ LDG.E R8, [R14.64+0x14] ; /* 0x000014040e087981 */
/* 0x001f28000c1e1900 */
/*0330*/ LDG.E R26, [R14.64+0x1c] ; /* 0x00001c040e1a7981 */
/* 0x020f62000c1e1900 */
/*0340*/ IMAD.WIDE R12, R2, 0x4, R12 ; /* 0x00000004020c7825 */
/* 0x002fca00078e020c */
/*0350*/ LDG.E R9, [R12.64] ; /* 0x000000040c097981 */
/* 0x000562000c1e1900 */
/*0360*/ IMAD.WIDE R22, R2, 0x4, R12 ; /* 0x0000000402167825 */
/* 0x000fc800078e020c */
/*0370*/ IMAD R12, R11, R10, R24 ; /* 0x0000000a0b0c7224 */
/* 0x004fe400078e0218 */
/*0380*/ LDG.E R10, [R14.64+0x18] ; /* 0x000018040e0a7981 */
/* 0x000ea2000c1e1900 */
/*0390*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*03a0*/ LDG.E R11, [R22.64] ; /* 0x00000004160b7981 */
/* 0x0000a8000c1e1900 */
/*03b0*/ LDG.E R27, [R24.64] ; /* 0x00000004181b7981 */
/* 0x0002a2000c1e1900 */
/*03c0*/ IMAD R12, R19, R18, R12 ; /* 0x00000012130c7224 */
/* 0x008fe400078e020c */
/*03d0*/ IMAD.WIDE R18, R2, 0x4, R24 ; /* 0x0000000402127825 */
/* 0x000fe200078e0218 */
/*03e0*/ LDG.E R23, [R14.64+0x20] ; /* 0x000020040e177981 */
/* 0x001ee6000c1e1900 */
/*03f0*/ IMAD R28, R28, R29, R12 ; /* 0x0000001d1c1c7224 */
/* 0x010fc400078e020c */
/*0400*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x000fe200078e0212 */
/*0410*/ LDG.E R25, [R14.64+0x24] ; /* 0x000024040e197981 */
/* 0x002f26000c1e1900 */
/*0420*/ IMAD R28, R16, R17, R28 ; /* 0x00000011101c7224 */
/* 0x000fe200078e021c */
/*0430*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000e2000c1e1900 */
/*0440*/ IMAD.WIDE R16, R2, 0x4, R12 ; /* 0x0000000402107825 */
/* 0x000fc600078e020c */
/*0450*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000322000c1e1900 */
/*0460*/ IMAD R28, R21, R20, R28 ; /* 0x00000014151c7224 */
/* 0x000fc600078e021c */
/*0470*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x0002e2000c1e1900 */
/*0480*/ IMAD.WIDE R20, R2, 0x4, R16 ; /* 0x0000000402147825 */
/* 0x000fc600078e0210 */
/*0490*/ LDG.E R29, [R14.64+0x28] ; /* 0x000028040e1d7981 */
/* 0x000f28000c1e1900 */
/*04a0*/ LDG.E R19, [R14.64+0x2c] ; /* 0x00002c040e137981 */
/* 0x001f28000c1e1900 */
/*04b0*/ LDG.E R24, [R14.64+0x30] ; /* 0x000030040e187981 */
/* 0x000f22000c1e1900 */
/*04c0*/ IMAD R28, R9, R8, R28 ; /* 0x00000008091c7224 */
/* 0x020fe400078e021c */
/*04d0*/ IMAD.WIDE R8, R2, 0x4, R20 ; /* 0x0000000402087825 */
/* 0x000fc400078e0214 */
/*04e0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000168000c1e1900 */
/*04f0*/ LDG.E R21, [R14.64+0x38] ; /* 0x000038040e157981 */
/* 0x001f62000c1e1900 */
/*0500*/ IMAD R28, R11, R10, R28 ; /* 0x0000000a0b1c7224 */
/* 0x004fe400078e021c */
/*0510*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fe400078e0208 */
/*0520*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x0000a4000c1e1900 */
/*0530*/ IMAD R13, R27, R26, R28 ; /* 0x0000001a1b0d7224 */
/* 0x002fc400078e021c */
/*0540*/ IMAD.WIDE R26, R2.reuse, 0x4, R10 ; /* 0x00000004021a7825 */
/* 0x040fe400078e020a */
/*0550*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0002a8000c1e1900 */
/*0560*/ LDG.E R9, [R14.64+0x34] ; /* 0x000034040e097981 */
/* 0x001ea2000c1e1900 */
/*0570*/ IMAD.WIDE R16, R2, 0x4, R26 ; /* 0x0000000402107825 */
/* 0x000fc600078e021a */
/*0580*/ LDG.E R28, [R26.64] ; /* 0x000000041a1c7981 */
/* 0x0000a8000c1e1900 */
/*0590*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x002ea8000c1e1900 */
/*05a0*/ LDG.E R26, [R14.64+0x3c] ; /* 0x00003c040e1a7981 */
/* 0x001ea2000c1e1900 */
/*05b0*/ IMAD R13, R18, R23, R13 ; /* 0x00000017120d7224 */
/* 0x008fc800078e020d */
/*05c0*/ IMAD R12, R12, R25, R13 ; /* 0x000000190c0c7224 */
/* 0x010fe200078e020d */
/*05d0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc60007ffe0ff */
/*05e0*/ IMAD R12, R22, R29, R12 ; /* 0x0000001d160c7224 */
/* 0x000fe200078e020c */
/*05f0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fc60003f24270 */
/*0600*/ IMAD R19, R20, R19, R12 ; /* 0x0000001314137224 */
/* 0x020fe200078e020c */
/*0610*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0620*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0630*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0640*/ IMAD R8, R8, R24, R19 ; /* 0x0000001808087224 */
/* 0x004fc800078e0213 */
/*0650*/ IMAD R8, R10, R9, R8 ; /* 0x000000090a087224 */
/* 0x000fc800078e0208 */
/*0660*/ IMAD R8, R28, R21, R8 ; /* 0x000000151c087224 */
/* 0x000fc800078e0208 */
/*0670*/ IMAD R24, R11, R26, R8 ; /* 0x0000001a0b187224 */
/* 0x000fe400078e0208 */
/*0680*/ IMAD.WIDE R8, R2, 0x4, R16 ; /* 0x0000000402087825 */
/* 0x000fe200078e0210 */
/*0690*/ @P1 BRA 0x210 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06a0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06b0*/ @!P1 BRA 0x940 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06c0*/ IMAD.WIDE R16, R2, 0x4, R8 ; /* 0x0000000402107825 */
/* 0x000fe200078e0208 */
/*06d0*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*06e0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*06f0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fc60008000f00 */
/*0700*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe400078e0210 */
/*0710*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e4000c1e1900 */
/*0720*/ IMAD.WIDE R10, R7, 0x4, R10 ; /* 0x00000004070a7825 */
/* 0x000fe400078e020a */
/*0730*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000964000c1e1900 */
/*0740*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe400078e020c */
/*0750*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee2000c1e1900 */
/*0770*/ IMAD.WIDE R18, R2, 0x4, R14 ; /* 0x0000000402127825 */
/* 0x000fc600078e020e */
/*0780*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f66000c1e1900 */
/*0790*/ IMAD.WIDE R20, R2.reuse, 0x4, R18 ; /* 0x0000000402147825 */
/* 0x040fe200078e0212 */
/*07a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07b0*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R8, R2, 0x4, R20 ; /* 0x0000000402087825 */
/* 0x001fc600078e0214 */
/*07d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*07e0*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*07f0*/ IMAD.WIDE R12, R2, 0x4, R8 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0208 */
/*0800*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f28000c1e1900 */
/*0810*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f28000c1e1900 */
/*0820*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000328000c1e1900 */
/*0830*/ LDG.E R19, [R10.64+0x1c] ; /* 0x00001c040a137981 */
/* 0x001f28000c1e1900 */
/*0840*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f28000c1e1900 */
/*0850*/ LDG.E R9, [R12.64] ; /* 0x000000040c097981 */
/* 0x000f22000c1e1900 */
/*0860*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0870*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0880*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0890*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08a0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08b0*/ IMAD R22, R23, R22, R24 ; /* 0x0000001617167224 */
/* 0x004fc800078e0218 */
/*08c0*/ IMAD R16, R16, R25, R22 ; /* 0x0000001910107224 */
/* 0x008fc800078e0216 */
/*08d0*/ IMAD R16, R26, R27, R16 ; /* 0x0000001b1a107224 */
/* 0x020fc800078e0210 */
/*08e0*/ IMAD R29, R14, R29, R16 ; /* 0x0000001d0e1d7224 */
/* 0x000fc800078e0210 */
/*08f0*/ IMAD R18, R18, R28, R29 ; /* 0x0000001c12127224 */
/* 0x000fc800078e021d */
/*0900*/ IMAD R15, R20, R15, R18 ; /* 0x0000000f140f7224 */
/* 0x010fc800078e0212 */
/*0910*/ IMAD R8, R17, R8, R15 ; /* 0x0000000811087224 */
/* 0x000fc800078e020f */
/*0920*/ IMAD R24, R9, R19, R8 ; /* 0x0000001309187224 */
/* 0x000fe400078e0208 */
/*0930*/ IMAD.WIDE R8, R2, 0x4, R12 ; /* 0x0000000402087825 */
/* 0x000fc800078e020c */
/*0940*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0950*/ @!P0 BRA 0xaf0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0960*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0970*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fe200078e0208 */
/*0980*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fe20008000f00 */
/*0990*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ IMAD.WIDE R12, R7, 0x4, R12 ; /* 0x00000004070c7825 */
/* 0x000fc800078e020c */
/*09b0*/ IMAD.WIDE R14, R2.reuse, 0x4, R10 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020a */
/*09c0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000ea8000c1e1900 */
/*09d0*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ee2000c1e1900 */
/*09e0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fc600078e020e */
/*09f0*/ LDG.E R19, [R12.64+0x4] ; /* 0x000004040c137981 */
/* 0x000ee8000c1e1900 */
/*0a00*/ LDG.E R21, [R14.64] ; /* 0x000000040e157981 */
/* 0x000f28000c1e1900 */
/*0a10*/ LDG.E R20, [R12.64+0x8] ; /* 0x000008040c147981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R22, [R12.64+0xc] ; /* 0x00000c040c167981 */
/* 0x000f68000c1e1900 */
/*0a30*/ LDG.E R23, [R16.64] ; /* 0x0000000410177981 */
/* 0x000f62000c1e1900 */
/*0a40*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a50*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a60*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a70*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a80*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a90*/ IMAD R18, R9, R18, R24 ; /* 0x0000001209127224 */
/* 0x004fc800078e0218 */
/*0aa0*/ IMAD R18, R11, R19, R18 ; /* 0x000000130b127224 */
/* 0x008fe400078e0212 */
/*0ab0*/ IMAD.WIDE R8, R2, 0x4, R16 ; /* 0x0000000402087825 */
/* 0x000fc800078e0210 */
/*0ac0*/ IMAD R18, R21, R20, R18 ; /* 0x0000001415127224 */
/* 0x010fc800078e0212 */
/*0ad0*/ IMAD R24, R23, R22, R18 ; /* 0x0000001617187224 */
/* 0x020fe200078e0212 */
/*0ae0*/ @P0 BRA 0x960 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0af0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b00*/ @!P0 BRA 0xbf0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b10*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b20*/ IMAD R6, R3, c[0x0][0x17c], R4 ; /* 0x00005f0003067a24 */
/* 0x000fe400078e0204 */
/*0b30*/ IMAD R4, R4, c[0x0][0x17c], R0 ; /* 0x00005f0004047a24 */
/* 0x000fce00078e0200 */
/*0b40*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b50*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b60*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b70*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b80*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0b90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0ba0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bb0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bc0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bd0*/ IMAD R24, R11, R4, R24 ; /* 0x000000040b187224 */
/* 0x004fcc00078e0218 */
/*0be0*/ @P0 BRA 0xb60 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0bf0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0c00*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c10*/ IMAD R3, R3, c[0x0][0x17c], R0 ; /* 0x00005f0003037a24 */
/* 0x000fc800078e0200 */
/*0c20*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c30*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*0c40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c50*/ BRA 0xc50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <time.h>
#include <cuda.h>
#define M 400
#define N 400
#define R 400
#define THREADS_PER_BLOCK 512
__global__ void gpu_matmul(int *a, int *b, int *c, int m, int n, int r)
{
int i = threadIdx.y + blockIdx.y * blockDim.y;
int j = threadIdx.x + blockIdx.x * blockDim.x;
int sum = 0;
if (i < n && j < n)
{
for(int k = 0; k < n; k++)
{
sum += a[i*n+k]*b[k*n+j];
}
}
c[i*n+j] = sum;
}
void cpu_matmul(int *a, int *b, int *c, int m, int n, int r)
{
int sum;
for (int i = 0; i < m; i++)
{
for (int j = 0; j < r; j++)
{
sum = 0;
for (int k = 0; k < n; k++)
{
sum += a[i*m+k]*b[k*n+j];
}
c[i*m+j] = sum;
}
}
}
void random_matrix(int *a, int m, int n)
{
for (int i = 0; i < m; i++)
{
for (int j = 0; j < n; j++)
{
a[i*m+j] = rand() % 100;
}
}
}
int main(void)
{
int *a, *b, *c, *c2;
int *d_a, *d_b, *d_c;
long a_size, b_size, c_size;
long size_int = sizeof(int);
double elapsed;
clock_t initial, final;
cudaError_t error;
a_size = M * N * size_int;
b_size = N * R * size_int;
c_size = M * R * size_int;
//Allocate memory on host for arrays a, b, and c (flattened 2D arrays)
a = (int *)malloc(a_size);
b = (int *)malloc(b_size);
c = (int *)malloc(c_size);
c2 = (int *)malloc(c_size);
//Allocate memory on device for a, b, and c
if ((error = cudaMalloc((void **)&d_a, a_size)) != cudaSuccess)
{
printf("Error allocating d_a: %s in %s on line %d\n", cudaGetErrorString(error), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
if ((error = cudaMalloc((void **)&d_b, b_size)) != cudaSuccess)
{
printf("Error allocating d_b: %s in %s on line %d\n", cudaGetErrorString(error), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
if ((error = cudaMalloc((void **)&d_c, c_size)) != cudaSuccess)
{
printf("Error allocating d_c: %s in %s on line %d\n", cudaGetErrorString(error), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
random_matrix(a, M, N);
random_matrix(b, N, R);
if ((error = cudaMemcpy(d_a, a, a_size, cudaMemcpyHostToDevice)) != cudaSuccess)
{
printf("Error copying a to d_a: %s in %s on line %d\n", cudaGetErrorString(error), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
if ((error = cudaMemcpy(d_b, b, b_size, cudaMemcpyHostToDevice)) != cudaSuccess)
{
printf("Error copying b to d_b: %s in %s on line %d\n", cudaGetErrorString(error), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
cudaDeviceSynchronize();
printf("\nCPU vs. GPU: Multiplying %dx%d by %dx%d Matrix\n", M, N, N, R);
printf("====================================================\n");
initial = clock();
gpu_matmul<<<1,4>>>(d_a, d_b, d_c, M, N, R);
cudaDeviceSynchronize();
final = clock();
elapsed = (double)(final - initial) / CLOCKS_PER_SEC;
printf("GPU:\t\t%e seconds\n", elapsed);
initial = clock();
cpu_matmul(a, b, c, M, N, R);
final = clock();
elapsed = (double)(final - initial) / CLOCKS_PER_SEC;
printf("CPU:\t\t%e seconds\n\n", elapsed);
cudaMemcpy(c2, d_c, c_size, cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
for (int i = 0; i < M; i++)
{
for (int j = 0; j < R; j++)
{
printf("%d\t\t%d\t\t%d\n", c[i*M+j], c2[i*M+j], c[i*M+j] == c2[i*M+j]);
}
}
free(a); free(b); free(c);
cudaFree(d_a); cudaFree(d_b); cudaFree(d_c);
return 0;
} | .file "tmpxft_0012c045_00000000-6_matrixMultiplication.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10cpu_matmulPiS_S_iii
.type _Z10cpu_matmulPiS_S_iii, @function
_Z10cpu_matmulPiS_S_iii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rsi, -24(%rsp)
movq %rdx, -16(%rsp)
testl %ecx, %ecx
jle .L3
movq %rdi, %r14
movl %ecx, %eax
movl %r8d, %ebp
movslq %r8d, %rdx
leaq 0(,%rdx,4), %r8
movl $0, %r13d
movl $0, %ecx
movslq %r9d, %r12
movq %rdx, -8(%rsp)
movl %r9d, %edx
jmp .L5
.L6:
movl (%rcx), %esi
imull (%rdi), %esi
addl %esi, %r13d
addq $4, %rcx
addq %r8, %rdi
cmpq %r9, %rcx
jne .L6
.L8:
movl %r13d, (%rbx,%r10,4)
addq $1, %r10
addq $4, %r11
cmpq %r12, %r10
je .L13
.L9:
movq %r11, %rdi
movq %r15, %rcx
movl $0, %r13d
testl %ebp, %ebp
jg .L6
jmp .L8
.L13:
movl -32(%rsp), %ecx
movl -28(%rsp), %r13d
.L7:
addl $1, %ecx
addl %eax, %r13d
cmpl %ecx, %eax
je .L3
.L5:
testl %edx, %edx
jle .L7
movq -24(%rsp), %r11
movslq %r13d, %rdi
leaq 0(,%rdi,4), %rbx
leaq (%r14,%rbx), %r15
movq -8(%rsp), %rsi
addq %rsi, %rdi
leaq (%r14,%rdi,4), %r9
movq -16(%rsp), %rdi
addq %rdi, %rbx
movl $0, %r10d
movl %ecx, -32(%rsp)
movl %r13d, -28(%rsp)
jmp .L9
.L3:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z10cpu_matmulPiS_S_iii, .-_Z10cpu_matmulPiS_S_iii
.globl _Z13random_matrixPiii
.type _Z13random_matrixPiii, @function
_Z13random_matrixPiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %edx, 4(%rsp)
testl %esi, %esi
jle .L16
movq %rdi, %r15
movl %esi, %r14d
movl $0, %r13d
movl $0, %r12d
movl %edx, %eax
cltq
movq %rax, 8(%rsp)
jmp .L18
.L20:
movslq %r13d, %rax
leaq (%r15,%rax,4), %rbx
movq 8(%rsp), %rsi
addq %rsi, %rax
leaq (%r15,%rax,4), %rbp
.L19:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L19
.L21:
addl $1, %r12d
addl %r14d, %r13d
cmpl %r12d, %r14d
je .L16
.L18:
cmpl $0, 4(%rsp)
jg .L20
jmp .L21
.L16:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z13random_matrixPiii, .-_Z13random_matrixPiii
.globl _Z37__device_stub__Z10gpu_matmulPiS_S_iiiPiS_S_iii
.type _Z37__device_stub__Z10gpu_matmulPiS_S_iiiPiS_S_iii, @function
_Z37__device_stub__Z10gpu_matmulPiS_S_iiiPiS_S_iii:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10gpu_matmulPiS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z37__device_stub__Z10gpu_matmulPiS_S_iiiPiS_S_iii, .-_Z37__device_stub__Z10gpu_matmulPiS_S_iiiPiS_S_iii
.globl _Z10gpu_matmulPiS_S_iii
.type _Z10gpu_matmulPiS_S_iii, @function
_Z10gpu_matmulPiS_S_iii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z10gpu_matmulPiS_S_iiiPiS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10gpu_matmulPiS_S_iii, .-_Z10gpu_matmulPiS_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/daniel-s-ingram/cuda_fun/master/matrixMultiplication/matrixMultiplication.cu"
.align 8
.LC1:
.string "Error allocating d_a: %s in %s on line %d\n"
.align 8
.LC2:
.string "Error allocating d_b: %s in %s on line %d\n"
.align 8
.LC3:
.string "Error allocating d_c: %s in %s on line %d\n"
.align 8
.LC4:
.string "Error copying a to d_a: %s in %s on line %d\n"
.align 8
.LC5:
.string "Error copying b to d_b: %s in %s on line %d\n"
.align 8
.LC6:
.string "\nCPU vs. GPU: Multiplying %dx%d by %dx%d Matrix\n"
.align 8
.LC7:
.string "====================================================\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC9:
.string "GPU:\t\t%e seconds\n"
.LC10:
.string "CPU:\t\t%e seconds\n\n"
.LC11:
.string "%d\t\t%d\t\t%d\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $640000, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movl $640000, %edi
call malloc@PLT
movq %rax, (%rsp)
movl $640000, %edi
call malloc@PLT
movq %rax, %r15
movl $640000, %edi
call malloc@PLT
movq %rax, %r12
leaq 24(%rsp), %rdi
movl $640000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L45
leaq 32(%rsp), %rdi
movl $640000, %esi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L46
leaq 40(%rsp), %rdi
movl $640000, %esi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L47
movl $400, %edx
movl $400, %esi
movq 8(%rsp), %rbx
movq %rbx, %rdi
call _Z13random_matrixPiii
movl $400, %edx
movl $400, %esi
movq (%rsp), %rdi
call _Z13random_matrixPiii
movl $1, %ecx
movl $640000, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
testl %eax, %eax
jne .L48
movl $1, %ecx
movl $640000, %edx
movq (%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
testl %eax, %eax
jne .L49
call cudaDeviceSynchronize@PLT
movl $400, %r9d
movl $400, %r8d
movl $400, %ecx
movl $400, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call clock@PLT
movq %rax, %rbx
movl $4, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L38:
call cudaDeviceSynchronize@PLT
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC8(%rip), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call clock@PLT
movq %rax, %rbx
movl $400, %r9d
movl $400, %r8d
movl $400, %ecx
movq %r15, %rdx
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z10cpu_matmulPiS_S_iii
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC8(%rip), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $640000, %edx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
movq %r15, %rbp
leaq 640000(%r15), %r14
leaq .LC11(%rip), %r13
.L39:
movl $0, %ebx
.L40:
movl 0(%rbp,%rbx), %edx
movl (%r12,%rbx), %ecx
cmpl %ecx, %edx
sete %r8b
movzbl %r8b, %r8d
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $1600, %rbx
jne .L40
addq $1600, %rbp
addq $1600, %r12
cmpq %r14, %rbp
jne .L39
movq 8(%rsp), %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L51
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $81, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L46:
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $87, %r8d
leaq .LC0(%rip), %rcx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L47:
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $93, %r8d
leaq .LC0(%rip), %rcx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L48:
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $102, %r8d
leaq .LC0(%rip), %rcx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L49:
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $108, %r8d
leaq .LC0(%rip), %rcx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L50:
movl $400, %r9d
movl $400, %r8d
movl $400, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z37__device_stub__Z10gpu_matmulPiS_S_iiiPiS_S_iii
jmp .L38
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z10gpu_matmulPiS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z10gpu_matmulPiS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC8:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <time.h>
#include <cuda.h>
#define M 400
#define N 400
#define R 400
#define THREADS_PER_BLOCK 512
__global__ void gpu_matmul(int *a, int *b, int *c, int m, int n, int r)
{
int i = threadIdx.y + blockIdx.y * blockDim.y;
int j = threadIdx.x + blockIdx.x * blockDim.x;
int sum = 0;
if (i < n && j < n)
{
for(int k = 0; k < n; k++)
{
sum += a[i*n+k]*b[k*n+j];
}
}
c[i*n+j] = sum;
}
void cpu_matmul(int *a, int *b, int *c, int m, int n, int r)
{
int sum;
for (int i = 0; i < m; i++)
{
for (int j = 0; j < r; j++)
{
sum = 0;
for (int k = 0; k < n; k++)
{
sum += a[i*m+k]*b[k*n+j];
}
c[i*m+j] = sum;
}
}
}
void random_matrix(int *a, int m, int n)
{
for (int i = 0; i < m; i++)
{
for (int j = 0; j < n; j++)
{
a[i*m+j] = rand() % 100;
}
}
}
int main(void)
{
int *a, *b, *c, *c2;
int *d_a, *d_b, *d_c;
long a_size, b_size, c_size;
long size_int = sizeof(int);
double elapsed;
clock_t initial, final;
cudaError_t error;
a_size = M * N * size_int;
b_size = N * R * size_int;
c_size = M * R * size_int;
//Allocate memory on host for arrays a, b, and c (flattened 2D arrays)
a = (int *)malloc(a_size);
b = (int *)malloc(b_size);
c = (int *)malloc(c_size);
c2 = (int *)malloc(c_size);
//Allocate memory on device for a, b, and c
if ((error = cudaMalloc((void **)&d_a, a_size)) != cudaSuccess)
{
printf("Error allocating d_a: %s in %s on line %d\n", cudaGetErrorString(error), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
if ((error = cudaMalloc((void **)&d_b, b_size)) != cudaSuccess)
{
printf("Error allocating d_b: %s in %s on line %d\n", cudaGetErrorString(error), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
if ((error = cudaMalloc((void **)&d_c, c_size)) != cudaSuccess)
{
printf("Error allocating d_c: %s in %s on line %d\n", cudaGetErrorString(error), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
random_matrix(a, M, N);
random_matrix(b, N, R);
if ((error = cudaMemcpy(d_a, a, a_size, cudaMemcpyHostToDevice)) != cudaSuccess)
{
printf("Error copying a to d_a: %s in %s on line %d\n", cudaGetErrorString(error), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
if ((error = cudaMemcpy(d_b, b, b_size, cudaMemcpyHostToDevice)) != cudaSuccess)
{
printf("Error copying b to d_b: %s in %s on line %d\n", cudaGetErrorString(error), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
cudaDeviceSynchronize();
printf("\nCPU vs. GPU: Multiplying %dx%d by %dx%d Matrix\n", M, N, N, R);
printf("====================================================\n");
initial = clock();
gpu_matmul<<<1,4>>>(d_a, d_b, d_c, M, N, R);
cudaDeviceSynchronize();
final = clock();
elapsed = (double)(final - initial) / CLOCKS_PER_SEC;
printf("GPU:\t\t%e seconds\n", elapsed);
initial = clock();
cpu_matmul(a, b, c, M, N, R);
final = clock();
elapsed = (double)(final - initial) / CLOCKS_PER_SEC;
printf("CPU:\t\t%e seconds\n\n", elapsed);
cudaMemcpy(c2, d_c, c_size, cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
for (int i = 0; i < M; i++)
{
for (int j = 0; j < R; j++)
{
printf("%d\t\t%d\t\t%d\n", c[i*M+j], c2[i*M+j], c[i*M+j] == c2[i*M+j]);
}
}
free(a); free(b); free(c);
cudaFree(d_a); cudaFree(d_b); cudaFree(d_c);
return 0;
} | #include <stdio.h>
#include <time.h>
#include <hip/hip_runtime.h>
#define M 400
#define N 400
#define R 400
#define THREADS_PER_BLOCK 512
__global__ void gpu_matmul(int *a, int *b, int *c, int m, int n, int r)
{
int i = threadIdx.y + blockIdx.y * blockDim.y;
int j = threadIdx.x + blockIdx.x * blockDim.x;
int sum = 0;
if (i < n && j < n)
{
for(int k = 0; k < n; k++)
{
sum += a[i*n+k]*b[k*n+j];
}
}
c[i*n+j] = sum;
}
void cpu_matmul(int *a, int *b, int *c, int m, int n, int r)
{
int sum;
for (int i = 0; i < m; i++)
{
for (int j = 0; j < r; j++)
{
sum = 0;
for (int k = 0; k < n; k++)
{
sum += a[i*m+k]*b[k*n+j];
}
c[i*m+j] = sum;
}
}
}
void random_matrix(int *a, int m, int n)
{
for (int i = 0; i < m; i++)
{
for (int j = 0; j < n; j++)
{
a[i*m+j] = rand() % 100;
}
}
}
int main(void)
{
int *a, *b, *c, *c2;
int *d_a, *d_b, *d_c;
long a_size, b_size, c_size;
long size_int = sizeof(int);
double elapsed;
clock_t initial, final;
hipError_t error;
a_size = M * N * size_int;
b_size = N * R * size_int;
c_size = M * R * size_int;
//Allocate memory on host for arrays a, b, and c (flattened 2D arrays)
a = (int *)malloc(a_size);
b = (int *)malloc(b_size);
c = (int *)malloc(c_size);
c2 = (int *)malloc(c_size);
//Allocate memory on device for a, b, and c
if ((error = hipMalloc((void **)&d_a, a_size)) != hipSuccess)
{
printf("Error allocating d_a: %s in %s on line %d\n", hipGetErrorString(error), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
if ((error = hipMalloc((void **)&d_b, b_size)) != hipSuccess)
{
printf("Error allocating d_b: %s in %s on line %d\n", hipGetErrorString(error), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
if ((error = hipMalloc((void **)&d_c, c_size)) != hipSuccess)
{
printf("Error allocating d_c: %s in %s on line %d\n", hipGetErrorString(error), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
random_matrix(a, M, N);
random_matrix(b, N, R);
if ((error = hipMemcpy(d_a, a, a_size, hipMemcpyHostToDevice)) != hipSuccess)
{
printf("Error copying a to d_a: %s in %s on line %d\n", hipGetErrorString(error), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
if ((error = hipMemcpy(d_b, b, b_size, hipMemcpyHostToDevice)) != hipSuccess)
{
printf("Error copying b to d_b: %s in %s on line %d\n", hipGetErrorString(error), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
hipDeviceSynchronize();
printf("\nCPU vs. GPU: Multiplying %dx%d by %dx%d Matrix\n", M, N, N, R);
printf("====================================================\n");
initial = clock();
gpu_matmul<<<1,4>>>(d_a, d_b, d_c, M, N, R);
hipDeviceSynchronize();
final = clock();
elapsed = (double)(final - initial) / CLOCKS_PER_SEC;
printf("GPU:\t\t%e seconds\n", elapsed);
initial = clock();
cpu_matmul(a, b, c, M, N, R);
final = clock();
elapsed = (double)(final - initial) / CLOCKS_PER_SEC;
printf("CPU:\t\t%e seconds\n\n", elapsed);
hipMemcpy(c2, d_c, c_size, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
for (int i = 0; i < M; i++)
{
for (int j = 0; j < R; j++)
{
printf("%d\t\t%d\t\t%d\n", c[i*M+j], c2[i*M+j], c[i*M+j] == c2[i*M+j]);
}
}
free(a); free(b); free(c);
hipFree(d_a); hipFree(d_b); hipFree(d_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <time.h>
#include <hip/hip_runtime.h>
#define M 400
#define N 400
#define R 400
#define THREADS_PER_BLOCK 512
__global__ void gpu_matmul(int *a, int *b, int *c, int m, int n, int r)
{
int i = threadIdx.y + blockIdx.y * blockDim.y;
int j = threadIdx.x + blockIdx.x * blockDim.x;
int sum = 0;
if (i < n && j < n)
{
for(int k = 0; k < n; k++)
{
sum += a[i*n+k]*b[k*n+j];
}
}
c[i*n+j] = sum;
}
void cpu_matmul(int *a, int *b, int *c, int m, int n, int r)
{
int sum;
for (int i = 0; i < m; i++)
{
for (int j = 0; j < r; j++)
{
sum = 0;
for (int k = 0; k < n; k++)
{
sum += a[i*m+k]*b[k*n+j];
}
c[i*m+j] = sum;
}
}
}
void random_matrix(int *a, int m, int n)
{
for (int i = 0; i < m; i++)
{
for (int j = 0; j < n; j++)
{
a[i*m+j] = rand() % 100;
}
}
}
int main(void)
{
int *a, *b, *c, *c2;
int *d_a, *d_b, *d_c;
long a_size, b_size, c_size;
long size_int = sizeof(int);
double elapsed;
clock_t initial, final;
hipError_t error;
a_size = M * N * size_int;
b_size = N * R * size_int;
c_size = M * R * size_int;
//Allocate memory on host for arrays a, b, and c (flattened 2D arrays)
a = (int *)malloc(a_size);
b = (int *)malloc(b_size);
c = (int *)malloc(c_size);
c2 = (int *)malloc(c_size);
//Allocate memory on device for a, b, and c
if ((error = hipMalloc((void **)&d_a, a_size)) != hipSuccess)
{
printf("Error allocating d_a: %s in %s on line %d\n", hipGetErrorString(error), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
if ((error = hipMalloc((void **)&d_b, b_size)) != hipSuccess)
{
printf("Error allocating d_b: %s in %s on line %d\n", hipGetErrorString(error), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
if ((error = hipMalloc((void **)&d_c, c_size)) != hipSuccess)
{
printf("Error allocating d_c: %s in %s on line %d\n", hipGetErrorString(error), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
random_matrix(a, M, N);
random_matrix(b, N, R);
if ((error = hipMemcpy(d_a, a, a_size, hipMemcpyHostToDevice)) != hipSuccess)
{
printf("Error copying a to d_a: %s in %s on line %d\n", hipGetErrorString(error), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
if ((error = hipMemcpy(d_b, b, b_size, hipMemcpyHostToDevice)) != hipSuccess)
{
printf("Error copying b to d_b: %s in %s on line %d\n", hipGetErrorString(error), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
hipDeviceSynchronize();
printf("\nCPU vs. GPU: Multiplying %dx%d by %dx%d Matrix\n", M, N, N, R);
printf("====================================================\n");
initial = clock();
gpu_matmul<<<1,4>>>(d_a, d_b, d_c, M, N, R);
hipDeviceSynchronize();
final = clock();
elapsed = (double)(final - initial) / CLOCKS_PER_SEC;
printf("GPU:\t\t%e seconds\n", elapsed);
initial = clock();
cpu_matmul(a, b, c, M, N, R);
final = clock();
elapsed = (double)(final - initial) / CLOCKS_PER_SEC;
printf("CPU:\t\t%e seconds\n\n", elapsed);
hipMemcpy(c2, d_c, c_size, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
for (int i = 0; i < M; i++)
{
for (int j = 0; j < R; j++)
{
printf("%d\t\t%d\t\t%d\n", c[i*M+j], c2[i*M+j], c[i*M+j] == c2[i*M+j]);
}
}
free(a); free(b); free(c);
hipFree(d_a); hipFree(d_b); hipFree(d_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10gpu_matmulPiS_S_iii
.globl _Z10gpu_matmulPiS_S_iii
.p2align 8
.type _Z10gpu_matmulPiS_S_iii,@function
_Z10gpu_matmulPiS_S_iii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s2, s[0:1], 0x1c
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
v_max3_i32 v2, v0, v1, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v2
v_mov_b32_e32 v2, 0
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_mov_b32 s4, s2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s4, s4, -1
s_cmp_lg_u32 s4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s2, v5
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10gpu_matmulPiS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10gpu_matmulPiS_S_iii, .Lfunc_end0-_Z10gpu_matmulPiS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10gpu_matmulPiS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10gpu_matmulPiS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <time.h>
#include <hip/hip_runtime.h>
#define M 400
#define N 400
#define R 400
#define THREADS_PER_BLOCK 512
__global__ void gpu_matmul(int *a, int *b, int *c, int m, int n, int r)
{
int i = threadIdx.y + blockIdx.y * blockDim.y;
int j = threadIdx.x + blockIdx.x * blockDim.x;
int sum = 0;
if (i < n && j < n)
{
for(int k = 0; k < n; k++)
{
sum += a[i*n+k]*b[k*n+j];
}
}
c[i*n+j] = sum;
}
void cpu_matmul(int *a, int *b, int *c, int m, int n, int r)
{
int sum;
for (int i = 0; i < m; i++)
{
for (int j = 0; j < r; j++)
{
sum = 0;
for (int k = 0; k < n; k++)
{
sum += a[i*m+k]*b[k*n+j];
}
c[i*m+j] = sum;
}
}
}
void random_matrix(int *a, int m, int n)
{
for (int i = 0; i < m; i++)
{
for (int j = 0; j < n; j++)
{
a[i*m+j] = rand() % 100;
}
}
}
int main(void)
{
int *a, *b, *c, *c2;
int *d_a, *d_b, *d_c;
long a_size, b_size, c_size;
long size_int = sizeof(int);
double elapsed;
clock_t initial, final;
hipError_t error;
a_size = M * N * size_int;
b_size = N * R * size_int;
c_size = M * R * size_int;
//Allocate memory on host for arrays a, b, and c (flattened 2D arrays)
a = (int *)malloc(a_size);
b = (int *)malloc(b_size);
c = (int *)malloc(c_size);
c2 = (int *)malloc(c_size);
//Allocate memory on device for a, b, and c
if ((error = hipMalloc((void **)&d_a, a_size)) != hipSuccess)
{
printf("Error allocating d_a: %s in %s on line %d\n", hipGetErrorString(error), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
if ((error = hipMalloc((void **)&d_b, b_size)) != hipSuccess)
{
printf("Error allocating d_b: %s in %s on line %d\n", hipGetErrorString(error), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
if ((error = hipMalloc((void **)&d_c, c_size)) != hipSuccess)
{
printf("Error allocating d_c: %s in %s on line %d\n", hipGetErrorString(error), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
random_matrix(a, M, N);
random_matrix(b, N, R);
if ((error = hipMemcpy(d_a, a, a_size, hipMemcpyHostToDevice)) != hipSuccess)
{
printf("Error copying a to d_a: %s in %s on line %d\n", hipGetErrorString(error), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
if ((error = hipMemcpy(d_b, b, b_size, hipMemcpyHostToDevice)) != hipSuccess)
{
printf("Error copying b to d_b: %s in %s on line %d\n", hipGetErrorString(error), __FILE__, __LINE__);
exit(EXIT_FAILURE);
}
hipDeviceSynchronize();
printf("\nCPU vs. GPU: Multiplying %dx%d by %dx%d Matrix\n", M, N, N, R);
printf("====================================================\n");
initial = clock();
gpu_matmul<<<1,4>>>(d_a, d_b, d_c, M, N, R);
hipDeviceSynchronize();
final = clock();
elapsed = (double)(final - initial) / CLOCKS_PER_SEC;
printf("GPU:\t\t%e seconds\n", elapsed);
initial = clock();
cpu_matmul(a, b, c, M, N, R);
final = clock();
elapsed = (double)(final - initial) / CLOCKS_PER_SEC;
printf("CPU:\t\t%e seconds\n\n", elapsed);
hipMemcpy(c2, d_c, c_size, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
for (int i = 0; i < M; i++)
{
for (int j = 0; j < R; j++)
{
printf("%d\t\t%d\t\t%d\n", c[i*M+j], c2[i*M+j], c[i*M+j] == c2[i*M+j]);
}
}
free(a); free(b); free(c);
hipFree(d_a); hipFree(d_b); hipFree(d_c);
return 0;
} | .text
.file "matrixMultiplication.hip"
.globl _Z25__device_stub__gpu_matmulPiS_S_iii # -- Begin function _Z25__device_stub__gpu_matmulPiS_S_iii
.p2align 4, 0x90
.type _Z25__device_stub__gpu_matmulPiS_S_iii,@function
_Z25__device_stub__gpu_matmulPiS_S_iii: # @_Z25__device_stub__gpu_matmulPiS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10gpu_matmulPiS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z25__device_stub__gpu_matmulPiS_S_iii, .Lfunc_end0-_Z25__device_stub__gpu_matmulPiS_S_iii
.cfi_endproc
# -- End function
.globl _Z10cpu_matmulPiS_S_iii # -- Begin function _Z10cpu_matmulPiS_S_iii
.p2align 4, 0x90
.type _Z10cpu_matmulPiS_S_iii,@function
_Z10cpu_matmulPiS_S_iii: # @_Z10cpu_matmulPiS_S_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, -28(%rsp) # 4-byte Spill
movq %rdx, -8(%rsp) # 8-byte Spill
movq %rsi, -16(%rsp) # 8-byte Spill
movq %rdi, -24(%rsp) # 8-byte Spill
movl %ecx, -32(%rsp) # 4-byte Spill
testl %ecx, %ecx
jle .LBB1_7
# %bb.1: # %.preheader27.lr.ph
movslq %r8d, %rax
movl -32(%rsp), %ecx # 4-byte Reload
movl -28(%rsp), %r11d # 4-byte Reload
movl %eax, %ebx
shlq $2, %rax
xorl %r14d, %r14d
xorl %r15d, %r15d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_6: # %._crit_edge31
# in Loop: Header=BB1_2 Depth=1
incq %r15
addl -32(%rsp), %r14d # 4-byte Folded Reload
cmpq %rcx, %r15
je .LBB1_7
.LBB1_2: # %.preheader27
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
# Child Loop BB1_9 Depth 3
cmpl $0, -28(%rsp) # 4-byte Folded Reload
jle .LBB1_6
# %bb.3: # %.preheader.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %r14d, %edx
movq -24(%rsp), %rsi # 8-byte Reload
leaq (%rsi,%rdx,4), %r12
movq %r15, %rdx
imulq %rcx, %rdx
movq -8(%rsp), %rsi # 8-byte Reload
leaq (%rsi,%rdx,4), %r13
movq -16(%rsp), %rdi # 8-byte Reload
xorl %r10d, %r10d
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_4 Depth=2
xorl %edx, %edx
.LBB1_10: # %._crit_edge
# in Loop: Header=BB1_4 Depth=2
movl %edx, (%r13,%r10,4)
incq %r10
addq $4, %rdi
cmpq %r11, %r10
je .LBB1_6
.LBB1_4: # %.preheader
# Parent Loop BB1_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_9 Depth 3
testl %r8d, %r8d
jle .LBB1_5
# %bb.8: # %.lr.ph.preheader
# in Loop: Header=BB1_4 Depth=2
xorl %esi, %esi
movq %rdi, %rbp
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_9: # %.lr.ph
# Parent Loop BB1_2 Depth=1
# Parent Loop BB1_4 Depth=2
# => This Inner Loop Header: Depth=3
movl (%rbp), %r9d
imull (%r12,%rsi,4), %r9d
addl %r9d, %edx
incq %rsi
addq %rax, %rbp
cmpq %rsi, %rbx
jne .LBB1_9
jmp .LBB1_10
.LBB1_7: # %._crit_edge33
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z10cpu_matmulPiS_S_iii, .Lfunc_end1-_Z10cpu_matmulPiS_S_iii
.cfi_endproc
# -- End function
.globl _Z13random_matrixPiii # -- Begin function _Z13random_matrixPiii
.p2align 4, 0x90
.type _Z13random_matrixPiii,@function
_Z13random_matrixPiii: # @_Z13random_matrixPiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, 4(%rsp) # 4-byte Spill
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB2_6
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebp
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl 4(%rsp), %r12d # 4-byte Reload
xorl %r13d, %r13d
xorl %r14d, %r14d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %r14
addl %ebp, %r13d
cmpq 16(%rsp), %r14 # 8-byte Folded Reload
je .LBB2_6
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
cmpl $0, 4(%rsp) # 4-byte Folded Reload
jle .LBB2_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbx
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r12
jne .LBB2_4
jmp .LBB2_5
.LBB2_6: # %._crit_edge13
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z13random_matrixPiii, .Lfunc_end2-_Z13random_matrixPiii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $640000, %edi # imm = 0x9C400
callq malloc
movq %rax, %rbp
movl $640000, %edi # imm = 0x9C400
callq malloc
movq %rax, %r14
movl $640000, %edi # imm = 0x9C400
callq malloc
movq %rax, %r15
movl $640000, %edi # imm = 0x9C400
callq malloc
movq %rax, %r12
leaq 24(%rsp), %rdi
movl $640000, %esi # imm = 0x9C400
callq hipMalloc
testl %eax, %eax
jne .LBB3_1
# %bb.3:
leaq 16(%rsp), %rdi
movl $640000, %esi # imm = 0x9C400
callq hipMalloc
testl %eax, %eax
jne .LBB3_4
# %bb.5:
leaq 8(%rsp), %rdi
movl $640000, %esi # imm = 0x9C400
callq hipMalloc
testl %eax, %eax
jne .LBB3_31
# %bb.6: # %.preheader.i.preheader
xorl %r13d, %r13d
movq %rbp, 48(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB3_7: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_8 Depth 2
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_8: # Parent Loop BB3_7 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbp,%rbx,4)
incq %rbx
cmpq $400, %rbx # imm = 0x190
jne .LBB3_8
# %bb.9: # %._crit_edge.i
# in Loop: Header=BB3_7 Depth=1
incq %r13
addq $1600, %rbp # imm = 0x640
cmpq $400, %r13 # imm = 0x190
jne .LBB3_7
# %bb.10: # %.preheader.i64.preheader
xorl %r13d, %r13d
movq %r14, %rbp
.p2align 4, 0x90
.LBB3_11: # %.preheader.i64
# =>This Loop Header: Depth=1
# Child Loop BB3_12 Depth 2
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_12: # Parent Loop BB3_11 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbp,%rbx,4)
incq %rbx
cmpq $400, %rbx # imm = 0x190
jne .LBB3_12
# %bb.13: # %._crit_edge.i69
# in Loop: Header=BB3_11 Depth=1
incq %r13
addq $1600, %rbp # imm = 0x640
cmpq $400, %r13 # imm = 0x190
jne .LBB3_11
# %bb.14: # %_Z13random_matrixPiii.exit72
movq 24(%rsp), %rdi
movl $640000, %edx # imm = 0x9C400
movq 48(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_15
# %bb.16:
movq 16(%rsp), %rdi
movl $640000, %edx # imm = 0x9C400
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_17
# %bb.18:
callq hipDeviceSynchronize
movl $.L.str.6, %edi
movl $400, %esi # imm = 0x190
movl $400, %edx # imm = 0x190
movl $400, %ecx # imm = 0x190
movl $400, %r8d # imm = 0x190
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
callq puts@PLT
callq clock
movq %rax, %r13
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 3(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_20
# %bb.19:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $400, 44(%rsp) # imm = 0x190
movl $400, 40(%rsp) # imm = 0x190
movl $400, 36(%rsp) # imm = 0x190
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 44(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
leaq 36(%rsp), %rax
movq %rax, 168(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z10gpu_matmulPiS_S_iii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_20:
callq hipDeviceSynchronize
callq clock
subq %r13, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
xorl %ebp, %ebp
callq clock
movq %rax, %r13
.p2align 4, 0x90
.LBB3_21: # %.preheader27.i
# =>This Loop Header: Depth=1
# Child Loop BB3_22 Depth 2
# Child Loop BB3_23 Depth 3
imulq $1600, %rbp, %rcx # imm = 0x640
addq %r15, %rcx
movq %r14, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_22: # %.preheader.i73
# Parent Loop BB3_21 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_23 Depth 3
xorl %edi, %edi
movq %rdx, %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB3_23: # %.lr.ph.i
# Parent Loop BB3_21 Depth=1
# Parent Loop BB3_22 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r8), %r10d
imull (%rbx,%rdi,4), %r10d
addl %r10d, %r9d
incq %rdi
addq $1600, %r8 # imm = 0x640
cmpq $400, %rdi # imm = 0x190
jne .LBB3_23
# %bb.24: # %._crit_edge.i77
# in Loop: Header=BB3_22 Depth=2
movl %r9d, (%rcx,%rsi,4)
incq %rsi
addq $4, %rdx
cmpq $400, %rsi # imm = 0x190
jne .LBB3_22
# %bb.25: # %._crit_edge31.i
# in Loop: Header=BB3_21 Depth=1
incq %rbp
addq $1600, %rbx # imm = 0x640
cmpq $400, %rbp # imm = 0x190
jne .LBB3_21
# %bb.26: # %_Z10cpu_matmulPiS_S_iii.exit
callq clock
subq %r13, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movl $.L.str.9, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rsi
movl $640000, %edx # imm = 0x9C400
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movq %r15, %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_27: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_28 Depth 2
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_28: # Parent Loop BB3_27 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r13,%rbx,4), %esi
movl (%r12,%rbx,4), %edx
xorl %ecx, %ecx
cmpl %edx, %esi
sete %cl
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $400, %rbx # imm = 0x190
jne .LBB3_28
# %bb.29: # in Loop: Header=BB3_27 Depth=1
incq %rbp
addq $1600, %r12 # imm = 0x640
addq $1600, %r13 # imm = 0x640
cmpq $400, %rbp # imm = 0x190
jne .LBB3_27
# %bb.30:
movq 48(%rsp), %rdi # 8-byte Reload
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_1:
.cfi_def_cfa_offset 240
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $81, %ecx
jmp .LBB3_2
.LBB3_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $87, %ecx
jmp .LBB3_2
.LBB3_31:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $93, %ecx
jmp .LBB3_2
.LBB3_15:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $102, %ecx
jmp .LBB3_2
.LBB3_17:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $108, %ecx
.LBB3_2:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10gpu_matmulPiS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10gpu_matmulPiS_S_iii,@object # @_Z10gpu_matmulPiS_S_iii
.section .rodata,"a",@progbits
.globl _Z10gpu_matmulPiS_S_iii
.p2align 3, 0x0
_Z10gpu_matmulPiS_S_iii:
.quad _Z25__device_stub__gpu_matmulPiS_S_iii
.size _Z10gpu_matmulPiS_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error allocating d_a: %s in %s on line %d\n"
.size .L.str, 43
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/daniel-s-ingram/cuda_fun/master/matrixMultiplication/matrixMultiplication.hip"
.size .L.str.1, 135
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Error allocating d_b: %s in %s on line %d\n"
.size .L.str.2, 43
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error allocating d_c: %s in %s on line %d\n"
.size .L.str.3, 43
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Error copying a to d_a: %s in %s on line %d\n"
.size .L.str.4, 45
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Error copying b to d_b: %s in %s on line %d\n"
.size .L.str.5, 45
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\nCPU vs. GPU: Multiplying %dx%d by %dx%d Matrix\n"
.size .L.str.6, 49
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "GPU:\t\t%e seconds\n"
.size .L.str.8, 18
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "CPU:\t\t%e seconds\n\n"
.size .L.str.9, 19
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "%d\t\t%d\t\t%d\n"
.size .L.str.10, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10gpu_matmulPiS_S_iii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "===================================================="
.size .Lstr, 53
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__gpu_matmulPiS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10gpu_matmulPiS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10gpu_matmulPiS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0xc00 ; /* 0x00000bc000007945 */
/* 0x000fe20003800000 */
/*0040*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0060*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0070*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0090*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fe20003f06270 */
/*00a0*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fe200078e0202 */
/*00b0*/ MOV R2, c[0x0][0x17c] ; /* 0x00005f0000027a02 */
/* 0x000fc80000000f00 */
/*00c0*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x17c], P0 ; /* 0x00005f0003007a0c */
/* 0x000fc80000706670 */
/*00d0*/ ISETP.LT.OR P0, PT, R2, 0x1, P0 ; /* 0x000000010200780c */
/* 0x000fda0000701670 */
/*00e0*/ @P0 BRA 0xbf0 ; /* 0x00000b0000000947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0100*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0120*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fd20000000f00 */
/*0140*/ @!P0 BRA 0xaf0 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R6, -R5, c[0x0][0x17c], RZ ; /* 0x00005f0005067a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ IMAD R7, R3, c[0x0][0x17c], RZ ; /* 0x00005f0003077a24 */
/* 0x000fe200078e02ff */
/*0190*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*01a0*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fca0000000f00 */
/*01b0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x168] ; /* 0x00005a0000087625 */
/* 0x000fcc00078e0209 */
/*01c0*/ @!P0 BRA 0x960 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x6a0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ MOV R14, UR6 ; /* 0x00000006000e7c02 */
/* 0x000fe20008000f00 */
/*0220*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a2000c1e1900 */
/*0230*/ MOV R15, UR7 ; /* 0x00000007000f7c02 */
/* 0x000fca0008000f00 */
/*0240*/ IMAD.WIDE R14, R7, 0x4, R14 ; /* 0x00000004070e7825 */
/* 0x000fca00078e020e */
/*0250*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fc600078e0208 */
/*0270*/ LDG.E R18, [R14.64+0x4] ; /* 0x000004040e127981 */
/* 0x000ee6000c1e1900 */
/*0280*/ IMAD.WIDE R22, R2.reuse, 0x4, R8 ; /* 0x0000000402167825 */
/* 0x040fe200078e0208 */
/*0290*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x0000e8000c1e1900 */
/*02a0*/ LDG.E R28, [R22.64] ; /* 0x00000004161c7981 */
/* 0x000322000c1e1900 */
/*02b0*/ IMAD.WIDE R26, R2, 0x4, R22 ; /* 0x00000004021a7825 */
/* 0x000fc600078e0216 */
/*02c0*/ LDG.E R29, [R14.64+0x8] ; /* 0x000008040e1d7981 */
/* 0x000f26000c1e1900 */
/*02d0*/ IMAD.WIDE R12, R2.reuse, 0x4, R26 ; /* 0x00000004020c7825 */
/* 0x040fe200078e021a */
/*02e0*/ LDG.E R16, [R26.64] ; /* 0x000000041a107981 */
/* 0x000b28000c1e1900 */
/*02f0*/ LDG.E R17, [R14.64+0xc] ; /* 0x00000c040e117981 */
/* 0x000f28000c1e1900 */
/*0300*/ LDG.E R20, [R14.64+0x10] ; /* 0x000010040e147981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000328000c1e1900 */
/*0320*/ LDG.E R8, [R14.64+0x14] ; /* 0x000014040e087981 */
/* 0x001f28000c1e1900 */
/*0330*/ LDG.E R26, [R14.64+0x1c] ; /* 0x00001c040e1a7981 */
/* 0x020f62000c1e1900 */
/*0340*/ IMAD.WIDE R12, R2, 0x4, R12 ; /* 0x00000004020c7825 */
/* 0x002fca00078e020c */
/*0350*/ LDG.E R9, [R12.64] ; /* 0x000000040c097981 */
/* 0x000562000c1e1900 */
/*0360*/ IMAD.WIDE R22, R2, 0x4, R12 ; /* 0x0000000402167825 */
/* 0x000fc800078e020c */
/*0370*/ IMAD R12, R11, R10, R24 ; /* 0x0000000a0b0c7224 */
/* 0x004fe400078e0218 */
/*0380*/ LDG.E R10, [R14.64+0x18] ; /* 0x000018040e0a7981 */
/* 0x000ea2000c1e1900 */
/*0390*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*03a0*/ LDG.E R11, [R22.64] ; /* 0x00000004160b7981 */
/* 0x0000a8000c1e1900 */
/*03b0*/ LDG.E R27, [R24.64] ; /* 0x00000004181b7981 */
/* 0x0002a2000c1e1900 */
/*03c0*/ IMAD R12, R19, R18, R12 ; /* 0x00000012130c7224 */
/* 0x008fe400078e020c */
/*03d0*/ IMAD.WIDE R18, R2, 0x4, R24 ; /* 0x0000000402127825 */
/* 0x000fe200078e0218 */
/*03e0*/ LDG.E R23, [R14.64+0x20] ; /* 0x000020040e177981 */
/* 0x001ee6000c1e1900 */
/*03f0*/ IMAD R28, R28, R29, R12 ; /* 0x0000001d1c1c7224 */
/* 0x010fc400078e020c */
/*0400*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x000fe200078e0212 */
/*0410*/ LDG.E R25, [R14.64+0x24] ; /* 0x000024040e197981 */
/* 0x002f26000c1e1900 */
/*0420*/ IMAD R28, R16, R17, R28 ; /* 0x00000011101c7224 */
/* 0x000fe200078e021c */
/*0430*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000e2000c1e1900 */
/*0440*/ IMAD.WIDE R16, R2, 0x4, R12 ; /* 0x0000000402107825 */
/* 0x000fc600078e020c */
/*0450*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000322000c1e1900 */
/*0460*/ IMAD R28, R21, R20, R28 ; /* 0x00000014151c7224 */
/* 0x000fc600078e021c */
/*0470*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x0002e2000c1e1900 */
/*0480*/ IMAD.WIDE R20, R2, 0x4, R16 ; /* 0x0000000402147825 */
/* 0x000fc600078e0210 */
/*0490*/ LDG.E R29, [R14.64+0x28] ; /* 0x000028040e1d7981 */
/* 0x000f28000c1e1900 */
/*04a0*/ LDG.E R19, [R14.64+0x2c] ; /* 0x00002c040e137981 */
/* 0x001f28000c1e1900 */
/*04b0*/ LDG.E R24, [R14.64+0x30] ; /* 0x000030040e187981 */
/* 0x000f22000c1e1900 */
/*04c0*/ IMAD R28, R9, R8, R28 ; /* 0x00000008091c7224 */
/* 0x020fe400078e021c */
/*04d0*/ IMAD.WIDE R8, R2, 0x4, R20 ; /* 0x0000000402087825 */
/* 0x000fc400078e0214 */
/*04e0*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000168000c1e1900 */
/*04f0*/ LDG.E R21, [R14.64+0x38] ; /* 0x000038040e157981 */
/* 0x001f62000c1e1900 */
/*0500*/ IMAD R28, R11, R10, R28 ; /* 0x0000000a0b1c7224 */
/* 0x004fe400078e021c */
/*0510*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fe400078e0208 */
/*0520*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x0000a4000c1e1900 */
/*0530*/ IMAD R13, R27, R26, R28 ; /* 0x0000001a1b0d7224 */
/* 0x002fc400078e021c */
/*0540*/ IMAD.WIDE R26, R2.reuse, 0x4, R10 ; /* 0x00000004021a7825 */
/* 0x040fe400078e020a */
/*0550*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0002a8000c1e1900 */
/*0560*/ LDG.E R9, [R14.64+0x34] ; /* 0x000034040e097981 */
/* 0x001ea2000c1e1900 */
/*0570*/ IMAD.WIDE R16, R2, 0x4, R26 ; /* 0x0000000402107825 */
/* 0x000fc600078e021a */
/*0580*/ LDG.E R28, [R26.64] ; /* 0x000000041a1c7981 */
/* 0x0000a8000c1e1900 */
/*0590*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x002ea8000c1e1900 */
/*05a0*/ LDG.E R26, [R14.64+0x3c] ; /* 0x00003c040e1a7981 */
/* 0x001ea2000c1e1900 */
/*05b0*/ IMAD R13, R18, R23, R13 ; /* 0x00000017120d7224 */
/* 0x008fc800078e020d */
/*05c0*/ IMAD R12, R12, R25, R13 ; /* 0x000000190c0c7224 */
/* 0x010fe200078e020d */
/*05d0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc60007ffe0ff */
/*05e0*/ IMAD R12, R22, R29, R12 ; /* 0x0000001d160c7224 */
/* 0x000fe200078e020c */
/*05f0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fc60003f24270 */
/*0600*/ IMAD R19, R20, R19, R12 ; /* 0x0000001314137224 */
/* 0x020fe200078e020c */
/*0610*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0620*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0630*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0640*/ IMAD R8, R8, R24, R19 ; /* 0x0000001808087224 */
/* 0x004fc800078e0213 */
/*0650*/ IMAD R8, R10, R9, R8 ; /* 0x000000090a087224 */
/* 0x000fc800078e0208 */
/*0660*/ IMAD R8, R28, R21, R8 ; /* 0x000000151c087224 */
/* 0x000fc800078e0208 */
/*0670*/ IMAD R24, R11, R26, R8 ; /* 0x0000001a0b187224 */
/* 0x000fe400078e0208 */
/*0680*/ IMAD.WIDE R8, R2, 0x4, R16 ; /* 0x0000000402087825 */
/* 0x000fe200078e0210 */
/*0690*/ @P1 BRA 0x210 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06a0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06b0*/ @!P1 BRA 0x940 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06c0*/ IMAD.WIDE R16, R2, 0x4, R8 ; /* 0x0000000402107825 */
/* 0x000fe200078e0208 */
/*06d0*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*06e0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*06f0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fc60008000f00 */
/*0700*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe400078e0210 */
/*0710*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e4000c1e1900 */
/*0720*/ IMAD.WIDE R10, R7, 0x4, R10 ; /* 0x00000004070a7825 */
/* 0x000fe400078e020a */
/*0730*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000964000c1e1900 */
/*0740*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe400078e020c */
/*0750*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee2000c1e1900 */
/*0770*/ IMAD.WIDE R18, R2, 0x4, R14 ; /* 0x0000000402127825 */
/* 0x000fc600078e020e */
/*0780*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f66000c1e1900 */
/*0790*/ IMAD.WIDE R20, R2.reuse, 0x4, R18 ; /* 0x0000000402147825 */
/* 0x040fe200078e0212 */
/*07a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07b0*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R8, R2, 0x4, R20 ; /* 0x0000000402087825 */
/* 0x001fc600078e0214 */
/*07d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*07e0*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*07f0*/ IMAD.WIDE R12, R2, 0x4, R8 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0208 */
/*0800*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f28000c1e1900 */
/*0810*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f28000c1e1900 */
/*0820*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000328000c1e1900 */
/*0830*/ LDG.E R19, [R10.64+0x1c] ; /* 0x00001c040a137981 */
/* 0x001f28000c1e1900 */
/*0840*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f28000c1e1900 */
/*0850*/ LDG.E R9, [R12.64] ; /* 0x000000040c097981 */
/* 0x000f22000c1e1900 */
/*0860*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0870*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0880*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0890*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08a0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08b0*/ IMAD R22, R23, R22, R24 ; /* 0x0000001617167224 */
/* 0x004fc800078e0218 */
/*08c0*/ IMAD R16, R16, R25, R22 ; /* 0x0000001910107224 */
/* 0x008fc800078e0216 */
/*08d0*/ IMAD R16, R26, R27, R16 ; /* 0x0000001b1a107224 */
/* 0x020fc800078e0210 */
/*08e0*/ IMAD R29, R14, R29, R16 ; /* 0x0000001d0e1d7224 */
/* 0x000fc800078e0210 */
/*08f0*/ IMAD R18, R18, R28, R29 ; /* 0x0000001c12127224 */
/* 0x000fc800078e021d */
/*0900*/ IMAD R15, R20, R15, R18 ; /* 0x0000000f140f7224 */
/* 0x010fc800078e0212 */
/*0910*/ IMAD R8, R17, R8, R15 ; /* 0x0000000811087224 */
/* 0x000fc800078e020f */
/*0920*/ IMAD R24, R9, R19, R8 ; /* 0x0000001309187224 */
/* 0x000fe400078e0208 */
/*0930*/ IMAD.WIDE R8, R2, 0x4, R12 ; /* 0x0000000402087825 */
/* 0x000fc800078e020c */
/*0940*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0950*/ @!P0 BRA 0xaf0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0960*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0970*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fe200078e0208 */
/*0980*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fe20008000f00 */
/*0990*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ IMAD.WIDE R12, R7, 0x4, R12 ; /* 0x00000004070c7825 */
/* 0x000fc800078e020c */
/*09b0*/ IMAD.WIDE R14, R2.reuse, 0x4, R10 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020a */
/*09c0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000ea8000c1e1900 */
/*09d0*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ee2000c1e1900 */
/*09e0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fc600078e020e */
/*09f0*/ LDG.E R19, [R12.64+0x4] ; /* 0x000004040c137981 */
/* 0x000ee8000c1e1900 */
/*0a00*/ LDG.E R21, [R14.64] ; /* 0x000000040e157981 */
/* 0x000f28000c1e1900 */
/*0a10*/ LDG.E R20, [R12.64+0x8] ; /* 0x000008040c147981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R22, [R12.64+0xc] ; /* 0x00000c040c167981 */
/* 0x000f68000c1e1900 */
/*0a30*/ LDG.E R23, [R16.64] ; /* 0x0000000410177981 */
/* 0x000f62000c1e1900 */
/*0a40*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a50*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a60*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a70*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a80*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a90*/ IMAD R18, R9, R18, R24 ; /* 0x0000001209127224 */
/* 0x004fc800078e0218 */
/*0aa0*/ IMAD R18, R11, R19, R18 ; /* 0x000000130b127224 */
/* 0x008fe400078e0212 */
/*0ab0*/ IMAD.WIDE R8, R2, 0x4, R16 ; /* 0x0000000402087825 */
/* 0x000fc800078e0210 */
/*0ac0*/ IMAD R18, R21, R20, R18 ; /* 0x0000001415127224 */
/* 0x010fc800078e0212 */
/*0ad0*/ IMAD R24, R23, R22, R18 ; /* 0x0000001617187224 */
/* 0x020fe200078e0212 */
/*0ae0*/ @P0 BRA 0x960 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0af0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b00*/ @!P0 BRA 0xbf0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b10*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b20*/ IMAD R6, R3, c[0x0][0x17c], R4 ; /* 0x00005f0003067a24 */
/* 0x000fe400078e0204 */
/*0b30*/ IMAD R4, R4, c[0x0][0x17c], R0 ; /* 0x00005f0004047a24 */
/* 0x000fce00078e0200 */
/*0b40*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b50*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b60*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b70*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b80*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0b90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0ba0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bb0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bc0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bd0*/ IMAD R24, R11, R4, R24 ; /* 0x000000040b187224 */
/* 0x004fcc00078e0218 */
/*0be0*/ @P0 BRA 0xb60 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0bf0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0c00*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c10*/ IMAD R3, R3, c[0x0][0x17c], R0 ; /* 0x00005f0003037a24 */
/* 0x000fc800078e0200 */
/*0c20*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c30*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*0c40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c50*/ BRA 0xc50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10gpu_matmulPiS_S_iii
.globl _Z10gpu_matmulPiS_S_iii
.p2align 8
.type _Z10gpu_matmulPiS_S_iii,@function
_Z10gpu_matmulPiS_S_iii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s2, s[0:1], 0x1c
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
v_max3_i32 v2, v0, v1, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v2
v_mov_b32_e32 v2, 0
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_mov_b32 s4, s2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s4, s4, -1
s_cmp_lg_u32 s4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s2, v5
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10gpu_matmulPiS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10gpu_matmulPiS_S_iii, .Lfunc_end0-_Z10gpu_matmulPiS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10gpu_matmulPiS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10gpu_matmulPiS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012c045_00000000-6_matrixMultiplication.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10cpu_matmulPiS_S_iii
.type _Z10cpu_matmulPiS_S_iii, @function
_Z10cpu_matmulPiS_S_iii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rsi, -24(%rsp)
movq %rdx, -16(%rsp)
testl %ecx, %ecx
jle .L3
movq %rdi, %r14
movl %ecx, %eax
movl %r8d, %ebp
movslq %r8d, %rdx
leaq 0(,%rdx,4), %r8
movl $0, %r13d
movl $0, %ecx
movslq %r9d, %r12
movq %rdx, -8(%rsp)
movl %r9d, %edx
jmp .L5
.L6:
movl (%rcx), %esi
imull (%rdi), %esi
addl %esi, %r13d
addq $4, %rcx
addq %r8, %rdi
cmpq %r9, %rcx
jne .L6
.L8:
movl %r13d, (%rbx,%r10,4)
addq $1, %r10
addq $4, %r11
cmpq %r12, %r10
je .L13
.L9:
movq %r11, %rdi
movq %r15, %rcx
movl $0, %r13d
testl %ebp, %ebp
jg .L6
jmp .L8
.L13:
movl -32(%rsp), %ecx
movl -28(%rsp), %r13d
.L7:
addl $1, %ecx
addl %eax, %r13d
cmpl %ecx, %eax
je .L3
.L5:
testl %edx, %edx
jle .L7
movq -24(%rsp), %r11
movslq %r13d, %rdi
leaq 0(,%rdi,4), %rbx
leaq (%r14,%rbx), %r15
movq -8(%rsp), %rsi
addq %rsi, %rdi
leaq (%r14,%rdi,4), %r9
movq -16(%rsp), %rdi
addq %rdi, %rbx
movl $0, %r10d
movl %ecx, -32(%rsp)
movl %r13d, -28(%rsp)
jmp .L9
.L3:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z10cpu_matmulPiS_S_iii, .-_Z10cpu_matmulPiS_S_iii
.globl _Z13random_matrixPiii
.type _Z13random_matrixPiii, @function
_Z13random_matrixPiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %edx, 4(%rsp)
testl %esi, %esi
jle .L16
movq %rdi, %r15
movl %esi, %r14d
movl $0, %r13d
movl $0, %r12d
movl %edx, %eax
cltq
movq %rax, 8(%rsp)
jmp .L18
.L20:
movslq %r13d, %rax
leaq (%r15,%rax,4), %rbx
movq 8(%rsp), %rsi
addq %rsi, %rax
leaq (%r15,%rax,4), %rbp
.L19:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L19
.L21:
addl $1, %r12d
addl %r14d, %r13d
cmpl %r12d, %r14d
je .L16
.L18:
cmpl $0, 4(%rsp)
jg .L20
jmp .L21
.L16:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z13random_matrixPiii, .-_Z13random_matrixPiii
.globl _Z37__device_stub__Z10gpu_matmulPiS_S_iiiPiS_S_iii
.type _Z37__device_stub__Z10gpu_matmulPiS_S_iiiPiS_S_iii, @function
_Z37__device_stub__Z10gpu_matmulPiS_S_iiiPiS_S_iii:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10gpu_matmulPiS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L24
.L29:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z37__device_stub__Z10gpu_matmulPiS_S_iiiPiS_S_iii, .-_Z37__device_stub__Z10gpu_matmulPiS_S_iiiPiS_S_iii
.globl _Z10gpu_matmulPiS_S_iii
.type _Z10gpu_matmulPiS_S_iii, @function
_Z10gpu_matmulPiS_S_iii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z10gpu_matmulPiS_S_iiiPiS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10gpu_matmulPiS_S_iii, .-_Z10gpu_matmulPiS_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/daniel-s-ingram/cuda_fun/master/matrixMultiplication/matrixMultiplication.cu"
.align 8
.LC1:
.string "Error allocating d_a: %s in %s on line %d\n"
.align 8
.LC2:
.string "Error allocating d_b: %s in %s on line %d\n"
.align 8
.LC3:
.string "Error allocating d_c: %s in %s on line %d\n"
.align 8
.LC4:
.string "Error copying a to d_a: %s in %s on line %d\n"
.align 8
.LC5:
.string "Error copying b to d_b: %s in %s on line %d\n"
.align 8
.LC6:
.string "\nCPU vs. GPU: Multiplying %dx%d by %dx%d Matrix\n"
.align 8
.LC7:
.string "====================================================\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC9:
.string "GPU:\t\t%e seconds\n"
.LC10:
.string "CPU:\t\t%e seconds\n\n"
.LC11:
.string "%d\t\t%d\t\t%d\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $640000, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movl $640000, %edi
call malloc@PLT
movq %rax, (%rsp)
movl $640000, %edi
call malloc@PLT
movq %rax, %r15
movl $640000, %edi
call malloc@PLT
movq %rax, %r12
leaq 24(%rsp), %rdi
movl $640000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L45
leaq 32(%rsp), %rdi
movl $640000, %esi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L46
leaq 40(%rsp), %rdi
movl $640000, %esi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L47
movl $400, %edx
movl $400, %esi
movq 8(%rsp), %rbx
movq %rbx, %rdi
call _Z13random_matrixPiii
movl $400, %edx
movl $400, %esi
movq (%rsp), %rdi
call _Z13random_matrixPiii
movl $1, %ecx
movl $640000, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
testl %eax, %eax
jne .L48
movl $1, %ecx
movl $640000, %edx
movq (%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
testl %eax, %eax
jne .L49
call cudaDeviceSynchronize@PLT
movl $400, %r9d
movl $400, %r8d
movl $400, %ecx
movl $400, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call clock@PLT
movq %rax, %rbx
movl $4, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L38:
call cudaDeviceSynchronize@PLT
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC8(%rip), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call clock@PLT
movq %rax, %rbx
movl $400, %r9d
movl $400, %r8d
movl $400, %ecx
movq %r15, %rdx
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z10cpu_matmulPiS_S_iii
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC8(%rip), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $640000, %edx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
movq %r15, %rbp
leaq 640000(%r15), %r14
leaq .LC11(%rip), %r13
.L39:
movl $0, %ebx
.L40:
movl 0(%rbp,%rbx), %edx
movl (%r12,%rbx), %ecx
cmpl %ecx, %edx
sete %r8b
movzbl %r8b, %r8d
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $1600, %rbx
jne .L40
addq $1600, %rbp
addq $1600, %r12
cmpq %r14, %rbp
jne .L39
movq 8(%rsp), %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L51
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $81, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L46:
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $87, %r8d
leaq .LC0(%rip), %rcx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L47:
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $93, %r8d
leaq .LC0(%rip), %rcx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L48:
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $102, %r8d
leaq .LC0(%rip), %rcx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L49:
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $108, %r8d
leaq .LC0(%rip), %rcx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L50:
movl $400, %r9d
movl $400, %r8d
movl $400, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z37__device_stub__Z10gpu_matmulPiS_S_iiiPiS_S_iii
jmp .L38
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z10gpu_matmulPiS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z10gpu_matmulPiS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC8:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixMultiplication.hip"
.globl _Z25__device_stub__gpu_matmulPiS_S_iii # -- Begin function _Z25__device_stub__gpu_matmulPiS_S_iii
.p2align 4, 0x90
.type _Z25__device_stub__gpu_matmulPiS_S_iii,@function
_Z25__device_stub__gpu_matmulPiS_S_iii: # @_Z25__device_stub__gpu_matmulPiS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10gpu_matmulPiS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z25__device_stub__gpu_matmulPiS_S_iii, .Lfunc_end0-_Z25__device_stub__gpu_matmulPiS_S_iii
.cfi_endproc
# -- End function
.globl _Z10cpu_matmulPiS_S_iii # -- Begin function _Z10cpu_matmulPiS_S_iii
.p2align 4, 0x90
.type _Z10cpu_matmulPiS_S_iii,@function
_Z10cpu_matmulPiS_S_iii: # @_Z10cpu_matmulPiS_S_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, -28(%rsp) # 4-byte Spill
movq %rdx, -8(%rsp) # 8-byte Spill
movq %rsi, -16(%rsp) # 8-byte Spill
movq %rdi, -24(%rsp) # 8-byte Spill
movl %ecx, -32(%rsp) # 4-byte Spill
testl %ecx, %ecx
jle .LBB1_7
# %bb.1: # %.preheader27.lr.ph
movslq %r8d, %rax
movl -32(%rsp), %ecx # 4-byte Reload
movl -28(%rsp), %r11d # 4-byte Reload
movl %eax, %ebx
shlq $2, %rax
xorl %r14d, %r14d
xorl %r15d, %r15d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_6: # %._crit_edge31
# in Loop: Header=BB1_2 Depth=1
incq %r15
addl -32(%rsp), %r14d # 4-byte Folded Reload
cmpq %rcx, %r15
je .LBB1_7
.LBB1_2: # %.preheader27
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
# Child Loop BB1_9 Depth 3
cmpl $0, -28(%rsp) # 4-byte Folded Reload
jle .LBB1_6
# %bb.3: # %.preheader.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %r14d, %edx
movq -24(%rsp), %rsi # 8-byte Reload
leaq (%rsi,%rdx,4), %r12
movq %r15, %rdx
imulq %rcx, %rdx
movq -8(%rsp), %rsi # 8-byte Reload
leaq (%rsi,%rdx,4), %r13
movq -16(%rsp), %rdi # 8-byte Reload
xorl %r10d, %r10d
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_4 Depth=2
xorl %edx, %edx
.LBB1_10: # %._crit_edge
# in Loop: Header=BB1_4 Depth=2
movl %edx, (%r13,%r10,4)
incq %r10
addq $4, %rdi
cmpq %r11, %r10
je .LBB1_6
.LBB1_4: # %.preheader
# Parent Loop BB1_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_9 Depth 3
testl %r8d, %r8d
jle .LBB1_5
# %bb.8: # %.lr.ph.preheader
# in Loop: Header=BB1_4 Depth=2
xorl %esi, %esi
movq %rdi, %rbp
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_9: # %.lr.ph
# Parent Loop BB1_2 Depth=1
# Parent Loop BB1_4 Depth=2
# => This Inner Loop Header: Depth=3
movl (%rbp), %r9d
imull (%r12,%rsi,4), %r9d
addl %r9d, %edx
incq %rsi
addq %rax, %rbp
cmpq %rsi, %rbx
jne .LBB1_9
jmp .LBB1_10
.LBB1_7: # %._crit_edge33
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z10cpu_matmulPiS_S_iii, .Lfunc_end1-_Z10cpu_matmulPiS_S_iii
.cfi_endproc
# -- End function
.globl _Z13random_matrixPiii # -- Begin function _Z13random_matrixPiii
.p2align 4, 0x90
.type _Z13random_matrixPiii,@function
_Z13random_matrixPiii: # @_Z13random_matrixPiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, 4(%rsp) # 4-byte Spill
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB2_6
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebp
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl 4(%rsp), %r12d # 4-byte Reload
xorl %r13d, %r13d
xorl %r14d, %r14d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %r14
addl %ebp, %r13d
cmpq 16(%rsp), %r14 # 8-byte Folded Reload
je .LBB2_6
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
cmpl $0, 4(%rsp) # 4-byte Folded Reload
jle .LBB2_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbx
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r12
jne .LBB2_4
jmp .LBB2_5
.LBB2_6: # %._crit_edge13
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z13random_matrixPiii, .Lfunc_end2-_Z13random_matrixPiii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $640000, %edi # imm = 0x9C400
callq malloc
movq %rax, %rbp
movl $640000, %edi # imm = 0x9C400
callq malloc
movq %rax, %r14
movl $640000, %edi # imm = 0x9C400
callq malloc
movq %rax, %r15
movl $640000, %edi # imm = 0x9C400
callq malloc
movq %rax, %r12
leaq 24(%rsp), %rdi
movl $640000, %esi # imm = 0x9C400
callq hipMalloc
testl %eax, %eax
jne .LBB3_1
# %bb.3:
leaq 16(%rsp), %rdi
movl $640000, %esi # imm = 0x9C400
callq hipMalloc
testl %eax, %eax
jne .LBB3_4
# %bb.5:
leaq 8(%rsp), %rdi
movl $640000, %esi # imm = 0x9C400
callq hipMalloc
testl %eax, %eax
jne .LBB3_31
# %bb.6: # %.preheader.i.preheader
xorl %r13d, %r13d
movq %rbp, 48(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB3_7: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_8 Depth 2
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_8: # Parent Loop BB3_7 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbp,%rbx,4)
incq %rbx
cmpq $400, %rbx # imm = 0x190
jne .LBB3_8
# %bb.9: # %._crit_edge.i
# in Loop: Header=BB3_7 Depth=1
incq %r13
addq $1600, %rbp # imm = 0x640
cmpq $400, %r13 # imm = 0x190
jne .LBB3_7
# %bb.10: # %.preheader.i64.preheader
xorl %r13d, %r13d
movq %r14, %rbp
.p2align 4, 0x90
.LBB3_11: # %.preheader.i64
# =>This Loop Header: Depth=1
# Child Loop BB3_12 Depth 2
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_12: # Parent Loop BB3_11 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbp,%rbx,4)
incq %rbx
cmpq $400, %rbx # imm = 0x190
jne .LBB3_12
# %bb.13: # %._crit_edge.i69
# in Loop: Header=BB3_11 Depth=1
incq %r13
addq $1600, %rbp # imm = 0x640
cmpq $400, %r13 # imm = 0x190
jne .LBB3_11
# %bb.14: # %_Z13random_matrixPiii.exit72
movq 24(%rsp), %rdi
movl $640000, %edx # imm = 0x9C400
movq 48(%rsp), %rbx # 8-byte Reload
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_15
# %bb.16:
movq 16(%rsp), %rdi
movl $640000, %edx # imm = 0x9C400
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_17
# %bb.18:
callq hipDeviceSynchronize
movl $.L.str.6, %edi
movl $400, %esi # imm = 0x190
movl $400, %edx # imm = 0x190
movl $400, %ecx # imm = 0x190
movl $400, %r8d # imm = 0x190
xorl %eax, %eax
callq printf
movl $.Lstr, %edi
callq puts@PLT
callq clock
movq %rax, %r13
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 3(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_20
# %bb.19:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl $400, 44(%rsp) # imm = 0x190
movl $400, 40(%rsp) # imm = 0x190
movl $400, 36(%rsp) # imm = 0x190
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 44(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
leaq 36(%rsp), %rax
movq %rax, 168(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z10gpu_matmulPiS_S_iii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_20:
callq hipDeviceSynchronize
callq clock
subq %r13, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
xorl %ebp, %ebp
callq clock
movq %rax, %r13
.p2align 4, 0x90
.LBB3_21: # %.preheader27.i
# =>This Loop Header: Depth=1
# Child Loop BB3_22 Depth 2
# Child Loop BB3_23 Depth 3
imulq $1600, %rbp, %rcx # imm = 0x640
addq %r15, %rcx
movq %r14, %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_22: # %.preheader.i73
# Parent Loop BB3_21 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_23 Depth 3
xorl %edi, %edi
movq %rdx, %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB3_23: # %.lr.ph.i
# Parent Loop BB3_21 Depth=1
# Parent Loop BB3_22 Depth=2
# => This Inner Loop Header: Depth=3
movl (%r8), %r10d
imull (%rbx,%rdi,4), %r10d
addl %r10d, %r9d
incq %rdi
addq $1600, %r8 # imm = 0x640
cmpq $400, %rdi # imm = 0x190
jne .LBB3_23
# %bb.24: # %._crit_edge.i77
# in Loop: Header=BB3_22 Depth=2
movl %r9d, (%rcx,%rsi,4)
incq %rsi
addq $4, %rdx
cmpq $400, %rsi # imm = 0x190
jne .LBB3_22
# %bb.25: # %._crit_edge31.i
# in Loop: Header=BB3_21 Depth=1
incq %rbp
addq $1600, %rbx # imm = 0x640
cmpq $400, %rbp # imm = 0x190
jne .LBB3_21
# %bb.26: # %_Z10cpu_matmulPiS_S_iii.exit
callq clock
subq %r13, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI3_0(%rip), %xmm0
movl $.L.str.9, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rsi
movl $640000, %edx # imm = 0x9C400
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movq %r15, %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_27: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_28 Depth 2
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_28: # Parent Loop BB3_27 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r13,%rbx,4), %esi
movl (%r12,%rbx,4), %edx
xorl %ecx, %ecx
cmpl %edx, %esi
sete %cl
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $400, %rbx # imm = 0x190
jne .LBB3_28
# %bb.29: # in Loop: Header=BB3_27 Depth=1
incq %rbp
addq $1600, %r12 # imm = 0x640
addq $1600, %r13 # imm = 0x640
cmpq $400, %rbp # imm = 0x190
jne .LBB3_27
# %bb.30:
movq 48(%rsp), %rdi # 8-byte Reload
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_1:
.cfi_def_cfa_offset 240
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $81, %ecx
jmp .LBB3_2
.LBB3_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $87, %ecx
jmp .LBB3_2
.LBB3_31:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $93, %ecx
jmp .LBB3_2
.LBB3_15:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $102, %ecx
jmp .LBB3_2
.LBB3_17:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movl $.L.str.1, %edx
movq %rax, %rsi
movl $108, %ecx
.LBB3_2:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10gpu_matmulPiS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10gpu_matmulPiS_S_iii,@object # @_Z10gpu_matmulPiS_S_iii
.section .rodata,"a",@progbits
.globl _Z10gpu_matmulPiS_S_iii
.p2align 3, 0x0
_Z10gpu_matmulPiS_S_iii:
.quad _Z25__device_stub__gpu_matmulPiS_S_iii
.size _Z10gpu_matmulPiS_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error allocating d_a: %s in %s on line %d\n"
.size .L.str, 43
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/daniel-s-ingram/cuda_fun/master/matrixMultiplication/matrixMultiplication.hip"
.size .L.str.1, 135
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Error allocating d_b: %s in %s on line %d\n"
.size .L.str.2, 43
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error allocating d_c: %s in %s on line %d\n"
.size .L.str.3, 43
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Error copying a to d_a: %s in %s on line %d\n"
.size .L.str.4, 45
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Error copying b to d_b: %s in %s on line %d\n"
.size .L.str.5, 45
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\nCPU vs. GPU: Multiplying %dx%d by %dx%d Matrix\n"
.size .L.str.6, 49
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "GPU:\t\t%e seconds\n"
.size .L.str.8, 18
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "CPU:\t\t%e seconds\n\n"
.size .L.str.9, 19
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "%d\t\t%d\t\t%d\n"
.size .L.str.10, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10gpu_matmulPiS_S_iii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "===================================================="
.size .Lstr, 53
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__gpu_matmulPiS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10gpu_matmulPiS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
// filename: eeTanh.cu
// a simple CUDA kernel to square the elements of a matrix
extern "C" // ensure function name to be exactly "eeTanh"
{
}
__global__ void cauchyLogErr(int N, int M, float *A, float *Y)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int index = j*N + i;
int L = N*M;
if (i < N && j < M)
{
// A2 in this case is stored in the doubled rows of A, the length of A is
// doublt that of Y
float a = __expf(A[index+L]);
A[index] = __fmul_rn(fabsf(__fsub_rn(A[index], Y[index])), a);
A[index +L] = -__logf(__fmul_rn(0.5, a)); // stick final sum factor in 2nd part of A so when it sums to total the cost will be correct
}
} | code for sm_80
Function : _Z12cauchyLogErriiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x164], PT ; /* 0x0000590003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x160], P0 ; /* 0x0000580000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*00b0*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fe20000000f00 */
/*00c0*/ IMAD R0, R3, c[0x0][0x160], R0 ; /* 0x0000580003007a24 */
/* 0x000fe200078e0200 */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00e0*/ IMAD R2, R5, c[0x0][0x160], R0 ; /* 0x0000580005027a24 */
/* 0x000fc800078e0200 */
/*00f0*/ IMAD.WIDE R2, R2, R9, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0209 */
/*0100*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R9, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0209 */
/*0120*/ IMAD.WIDE R4, R0, R9, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe400078e0209 */
/*0130*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee8000c1e1900 */
/*0140*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ee2000c1e1900 */
/*0150*/ FMUL R8, R8, 1.4426950216293334961 ; /* 0x3fb8aa3b08087820 */
/* 0x004fca0000400000 */
/*0160*/ FSETP.GEU.AND P0, PT, R8, -126, PT ; /* 0xc2fc00000800780b */
/* 0x000fe20003f0e000 */
/*0170*/ FADD R9, -R6, R9 ; /* 0x0000000906097221 */
/* 0x008fd80000000100 */
/*0180*/ @!P0 FMUL R8, R8, 0.5 ; /* 0x3f00000008088820 */
/* 0x000fc80000400000 */
/*0190*/ MUFU.EX2 R0, R8 ; /* 0x0000000800007308 */
/* 0x000e240000000800 */
/*01a0*/ @!P0 FMUL R0, R0, R0 ; /* 0x0000000000008220 */
/* 0x001fc80000400000 */
/*01b0*/ FMUL R10, R0.reuse, 0.5 ; /* 0x3f000000000a7820 */
/* 0x040fe40000400000 */
/*01c0*/ FMUL R9, R0, |R9| ; /* 0x4000000900097220 */
/* 0x000fc60000400000 */
/*01d0*/ FSETP.GEU.AND P0, PT, |R10|.reuse, 1.175494350822287508e-38, PT ; /* 0x008000000a00780b */
/* 0x040fe40003f0e200 */
/*01e0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000ff6000c101904 */
/*01f0*/ @!P0 FMUL R10, R10, 16777216 ; /* 0x4b8000000a0a8820 */
/* 0x000fc80000400000 */
/*0200*/ MUFU.LG2 R11, R10 ; /* 0x0000000a000b7308 */
/* 0x000e240000000c00 */
/*0210*/ @!P0 FADD R11, R11, -24 ; /* 0xc1c000000b0b8421 */
/* 0x001fc80000000000 */
/*0220*/ FMUL R11, R11, -0.69314718246459960938 ; /* 0xbf3172180b0b7820 */
/* 0x000fca0000400000 */
/*0230*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe2000c101904 */
/*0240*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0250*/ BRA 0x250; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
// filename: eeTanh.cu
// a simple CUDA kernel to square the elements of a matrix
extern "C" // ensure function name to be exactly "eeTanh"
{
}
__global__ void cauchyLogErr(int N, int M, float *A, float *Y)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int index = j*N + i;
int L = N*M;
if (i < N && j < M)
{
// A2 in this case is stored in the doubled rows of A, the length of A is
// doublt that of Y
float a = __expf(A[index+L]);
A[index] = __fmul_rn(fabsf(__fsub_rn(A[index], Y[index])), a);
A[index +L] = -__logf(__fmul_rn(0.5, a)); // stick final sum factor in 2nd part of A so when it sums to total the cost will be correct
}
} | .file "tmpxft_0000f396_00000000-6_cauchyLogErr.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z12cauchyLogErriiPfS_iiPfS_
.type _Z36__device_stub__Z12cauchyLogErriiPfS_iiPfS_, @function
_Z36__device_stub__Z12cauchyLogErriiPfS_iiPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12cauchyLogErriiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z12cauchyLogErriiPfS_iiPfS_, .-_Z36__device_stub__Z12cauchyLogErriiPfS_iiPfS_
.globl _Z12cauchyLogErriiPfS_
.type _Z12cauchyLogErriiPfS_, @function
_Z12cauchyLogErriiPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12cauchyLogErriiPfS_iiPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12cauchyLogErriiPfS_, .-_Z12cauchyLogErriiPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12cauchyLogErriiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12cauchyLogErriiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
// filename: eeTanh.cu
// a simple CUDA kernel to square the elements of a matrix
extern "C" // ensure function name to be exactly "eeTanh"
{
}
__global__ void cauchyLogErr(int N, int M, float *A, float *Y)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int index = j*N + i;
int L = N*M;
if (i < N && j < M)
{
// A2 in this case is stored in the doubled rows of A, the length of A is
// doublt that of Y
float a = __expf(A[index+L]);
A[index] = __fmul_rn(fabsf(__fsub_rn(A[index], Y[index])), a);
A[index +L] = -__logf(__fmul_rn(0.5, a)); // stick final sum factor in 2nd part of A so when it sums to total the cost will be correct
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
// filename: eeTanh.cu
// a simple CUDA kernel to square the elements of a matrix
extern "C" // ensure function name to be exactly "eeTanh"
{
}
__global__ void cauchyLogErr(int N, int M, float *A, float *Y)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int index = j*N + i;
int L = N*M;
if (i < N && j < M)
{
// A2 in this case is stored in the doubled rows of A, the length of A is
// doublt that of Y
float a = __expf(A[index+L]);
A[index] = __fmul_rn(fabsf(__fsub_rn(A[index], Y[index])), a);
A[index +L] = -__logf(__fmul_rn(0.5, a)); // stick final sum factor in 2nd part of A so when it sums to total the cost will be correct
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// filename: eeTanh.cu
// a simple CUDA kernel to square the elements of a matrix
extern "C" // ensure function name to be exactly "eeTanh"
{
}
__global__ void cauchyLogErr(int N, int M, float *A, float *Y)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int index = j*N + i;
int L = N*M;
if (i < N && j < M)
{
// A2 in this case is stored in the doubled rows of A, the length of A is
// doublt that of Y
float a = __expf(A[index+L]);
A[index] = __fmul_rn(fabsf(__fsub_rn(A[index], Y[index])), a);
A[index +L] = -__logf(__fmul_rn(0.5, a)); // stick final sum factor in 2nd part of A so when it sums to total the cost will be correct
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12cauchyLogErriiPfS_
.globl _Z12cauchyLogErriiPfS_
.p2align 8
.type _Z12cauchyLogErriiPfS_,@function
_Z12cauchyLogErriiPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_load_b128 s[0:3], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s5, s4, v[2:3]
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
global_load_b32 v6, v[0:1], off
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(2)
v_mul_f32_e32 v6, 0x3fb8aa3b, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_exp_f32_e32 v6, v6
s_waitcnt vmcnt(0)
s_waitcnt_depctr 0xfff
v_dual_sub_f32 v4, v5, v4 :: v_dual_mul_f32 v7, 0.5, v6
v_mul_f32_e64 v4, v6, |v4|
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f32_e32 vcc_lo, 0x800000, v7
v_cndmask_b32_e64 v8, 1.0, 0x4f800000, vcc_lo
v_mul_f32_e32 v7, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_log_f32_e32 v7, v7
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v8, 0x3f317217, v7
v_cmp_gt_f32_e64 s0, 0x7f800000, |v7|
v_fma_f32 v8, v7, 0x3f317217, -v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v8, v7, 0x3377d1cf, v8
v_fmac_f32_e32 v8, 0x3f317217, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v7, v7, v8, s0
v_cndmask_b32_e64 v8, 0, 0x41b17218, vcc_lo
v_sub_f32_e32 v5, v7, v8
s_delay_alu instid0(VALU_DEP_1)
v_xor_b32_e32 v5, 0x80000000, v5
s_clause 0x1
global_store_b32 v[2:3], v4, off
global_store_b32 v[0:1], v5, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12cauchyLogErriiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12cauchyLogErriiPfS_, .Lfunc_end0-_Z12cauchyLogErriiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12cauchyLogErriiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12cauchyLogErriiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// filename: eeTanh.cu
// a simple CUDA kernel to square the elements of a matrix
extern "C" // ensure function name to be exactly "eeTanh"
{
}
__global__ void cauchyLogErr(int N, int M, float *A, float *Y)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int index = j*N + i;
int L = N*M;
if (i < N && j < M)
{
// A2 in this case is stored in the doubled rows of A, the length of A is
// doublt that of Y
float a = __expf(A[index+L]);
A[index] = __fmul_rn(fabsf(__fsub_rn(A[index], Y[index])), a);
A[index +L] = -__logf(__fmul_rn(0.5, a)); // stick final sum factor in 2nd part of A so when it sums to total the cost will be correct
}
} | .text
.file "cauchyLogErr.hip"
.globl _Z27__device_stub__cauchyLogErriiPfS_ # -- Begin function _Z27__device_stub__cauchyLogErriiPfS_
.p2align 4, 0x90
.type _Z27__device_stub__cauchyLogErriiPfS_,@function
_Z27__device_stub__cauchyLogErriiPfS_: # @_Z27__device_stub__cauchyLogErriiPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12cauchyLogErriiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__cauchyLogErriiPfS_, .Lfunc_end0-_Z27__device_stub__cauchyLogErriiPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12cauchyLogErriiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12cauchyLogErriiPfS_,@object # @_Z12cauchyLogErriiPfS_
.section .rodata,"a",@progbits
.globl _Z12cauchyLogErriiPfS_
.p2align 3, 0x0
_Z12cauchyLogErriiPfS_:
.quad _Z27__device_stub__cauchyLogErriiPfS_
.size _Z12cauchyLogErriiPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12cauchyLogErriiPfS_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__cauchyLogErriiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12cauchyLogErriiPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12cauchyLogErriiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x164], PT ; /* 0x0000590003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x160], P0 ; /* 0x0000580000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*00b0*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fe20000000f00 */
/*00c0*/ IMAD R0, R3, c[0x0][0x160], R0 ; /* 0x0000580003007a24 */
/* 0x000fe200078e0200 */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00e0*/ IMAD R2, R5, c[0x0][0x160], R0 ; /* 0x0000580005027a24 */
/* 0x000fc800078e0200 */
/*00f0*/ IMAD.WIDE R2, R2, R9, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0209 */
/*0100*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R9, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0209 */
/*0120*/ IMAD.WIDE R4, R0, R9, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe400078e0209 */
/*0130*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee8000c1e1900 */
/*0140*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ee2000c1e1900 */
/*0150*/ FMUL R8, R8, 1.4426950216293334961 ; /* 0x3fb8aa3b08087820 */
/* 0x004fca0000400000 */
/*0160*/ FSETP.GEU.AND P0, PT, R8, -126, PT ; /* 0xc2fc00000800780b */
/* 0x000fe20003f0e000 */
/*0170*/ FADD R9, -R6, R9 ; /* 0x0000000906097221 */
/* 0x008fd80000000100 */
/*0180*/ @!P0 FMUL R8, R8, 0.5 ; /* 0x3f00000008088820 */
/* 0x000fc80000400000 */
/*0190*/ MUFU.EX2 R0, R8 ; /* 0x0000000800007308 */
/* 0x000e240000000800 */
/*01a0*/ @!P0 FMUL R0, R0, R0 ; /* 0x0000000000008220 */
/* 0x001fc80000400000 */
/*01b0*/ FMUL R10, R0.reuse, 0.5 ; /* 0x3f000000000a7820 */
/* 0x040fe40000400000 */
/*01c0*/ FMUL R9, R0, |R9| ; /* 0x4000000900097220 */
/* 0x000fc60000400000 */
/*01d0*/ FSETP.GEU.AND P0, PT, |R10|.reuse, 1.175494350822287508e-38, PT ; /* 0x008000000a00780b */
/* 0x040fe40003f0e200 */
/*01e0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000ff6000c101904 */
/*01f0*/ @!P0 FMUL R10, R10, 16777216 ; /* 0x4b8000000a0a8820 */
/* 0x000fc80000400000 */
/*0200*/ MUFU.LG2 R11, R10 ; /* 0x0000000a000b7308 */
/* 0x000e240000000c00 */
/*0210*/ @!P0 FADD R11, R11, -24 ; /* 0xc1c000000b0b8421 */
/* 0x001fc80000000000 */
/*0220*/ FMUL R11, R11, -0.69314718246459960938 ; /* 0xbf3172180b0b7820 */
/* 0x000fca0000400000 */
/*0230*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe2000c101904 */
/*0240*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0250*/ BRA 0x250; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12cauchyLogErriiPfS_
.globl _Z12cauchyLogErriiPfS_
.p2align 8
.type _Z12cauchyLogErriiPfS_,@function
_Z12cauchyLogErriiPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_load_b128 s[0:3], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s5, s4, v[2:3]
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
global_load_b32 v6, v[0:1], off
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[2:3], off
s_waitcnt vmcnt(2)
v_mul_f32_e32 v6, 0x3fb8aa3b, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_exp_f32_e32 v6, v6
s_waitcnt vmcnt(0)
s_waitcnt_depctr 0xfff
v_dual_sub_f32 v4, v5, v4 :: v_dual_mul_f32 v7, 0.5, v6
v_mul_f32_e64 v4, v6, |v4|
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f32_e32 vcc_lo, 0x800000, v7
v_cndmask_b32_e64 v8, 1.0, 0x4f800000, vcc_lo
v_mul_f32_e32 v7, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_log_f32_e32 v7, v7
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v8, 0x3f317217, v7
v_cmp_gt_f32_e64 s0, 0x7f800000, |v7|
v_fma_f32 v8, v7, 0x3f317217, -v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v8, v7, 0x3377d1cf, v8
v_fmac_f32_e32 v8, 0x3f317217, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v7, v7, v8, s0
v_cndmask_b32_e64 v8, 0, 0x41b17218, vcc_lo
v_sub_f32_e32 v5, v7, v8
s_delay_alu instid0(VALU_DEP_1)
v_xor_b32_e32 v5, 0x80000000, v5
s_clause 0x1
global_store_b32 v[2:3], v4, off
global_store_b32 v[0:1], v5, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12cauchyLogErriiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12cauchyLogErriiPfS_, .Lfunc_end0-_Z12cauchyLogErriiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12cauchyLogErriiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12cauchyLogErriiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000f396_00000000-6_cauchyLogErr.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z12cauchyLogErriiPfS_iiPfS_
.type _Z36__device_stub__Z12cauchyLogErriiPfS_iiPfS_, @function
_Z36__device_stub__Z12cauchyLogErriiPfS_iiPfS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12cauchyLogErriiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z12cauchyLogErriiPfS_iiPfS_, .-_Z36__device_stub__Z12cauchyLogErriiPfS_iiPfS_
.globl _Z12cauchyLogErriiPfS_
.type _Z12cauchyLogErriiPfS_, @function
_Z12cauchyLogErriiPfS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12cauchyLogErriiPfS_iiPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12cauchyLogErriiPfS_, .-_Z12cauchyLogErriiPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12cauchyLogErriiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12cauchyLogErriiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cauchyLogErr.hip"
.globl _Z27__device_stub__cauchyLogErriiPfS_ # -- Begin function _Z27__device_stub__cauchyLogErriiPfS_
.p2align 4, 0x90
.type _Z27__device_stub__cauchyLogErriiPfS_,@function
_Z27__device_stub__cauchyLogErriiPfS_: # @_Z27__device_stub__cauchyLogErriiPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12cauchyLogErriiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__cauchyLogErriiPfS_, .Lfunc_end0-_Z27__device_stub__cauchyLogErriiPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12cauchyLogErriiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12cauchyLogErriiPfS_,@object # @_Z12cauchyLogErriiPfS_
.section .rodata,"a",@progbits
.globl _Z12cauchyLogErriiPfS_
.p2align 3, 0x0
_Z12cauchyLogErriiPfS_:
.quad _Z27__device_stub__cauchyLogErriiPfS_
.size _Z12cauchyLogErriiPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12cauchyLogErriiPfS_"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__cauchyLogErriiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12cauchyLogErriiPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <cuda_runtime_api.h>
#include<stdio.h>
__global__ void cuda_gray_kernel(unsigned char *b, unsigned char *g, unsigned char *r, unsigned char *gray, size_t size)
{
size_t idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx >= size) {
return;
}
gray[idx] = (unsigned char)(0.114f*b[idx] + 0.587f*g[idx] + 0.299f*r[idx] + 0.5);
}
extern "C" {
void cuda_gray(unsigned char *a, unsigned char *b, unsigned char *c, unsigned char *d, size_t size)
{
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
unsigned char *d_a, *d_b, *d_c, *d_d;
cudaMalloc((void **)&d_a, size * sizeof(char));
cudaMalloc((void **)&d_b, size * sizeof(char));
cudaMalloc((void **)&d_c, size * sizeof(char));
cudaMalloc((void **)&d_d, size * sizeof(char));
cudaMemcpy(d_a, a, size * sizeof(char), cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size * sizeof(char), cudaMemcpyHostToDevice);
cudaMemcpy(d_c, c, size * sizeof(char), cudaMemcpyHostToDevice);
cudaMemcpy(d_d, d, size * sizeof(char), cudaMemcpyHostToDevice);
cudaEventRecord(start);
cuda_gray_kernel <<< ceil(size / 1024.0), 1024 >>> (d_a, d_b, d_c, d_d, size);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("Time on GPU : %f msec\n", milliseconds);
cudaMemcpy(d, d_d, size * sizeof(char), cudaMemcpyDeviceToHost);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
cudaFree(d_d);
}
} | code for sm_80
Function : _Z16cuda_gray_kernelPhS_S_S_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x184], PT, P0 ; /* 0x00006100ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IADD3 R6, P1, R0.reuse, c[0x0][0x168], RZ ; /* 0x00005a0000067a10 */
/* 0x040fe20007f3e0ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IADD3 R4, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000047a10 */
/* 0x000fc60007f1e0ff */
/*00a0*/ IMAD.X R7, RZ, RZ, c[0x0][0x16c], P1 ; /* 0x00005b00ff077624 */
/* 0x000fe200008e06ff */
/*00b0*/ IADD3.X R5, RZ, c[0x0][0x164], RZ, P0, !PT ; /* 0x00005900ff057a10 */
/* 0x000fe400007fe4ff */
/*00c0*/ IADD3 R8, P0, R0.reuse, c[0x0][0x170], RZ ; /* 0x00005c0000087a10 */
/* 0x040fe40007f1e0ff */
/*00d0*/ LDG.E.U8 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea4000c1e1100 */
/*00e0*/ IADD3.X R9, RZ, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d00ff097a10 */
/* 0x000fe400007fe4ff */
/*00f0*/ LDG.E.U8 R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x0000e8000c1e1100 */
/*0100*/ LDG.E.U8 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f22000c1e1100 */
/*0110*/ IADD3 R4, P0, R0, c[0x0][0x178], RZ ; /* 0x00005e0000047a10 */
/* 0x001fca0007f1e0ff */
/*0120*/ IMAD.X R5, RZ, RZ, c[0x0][0x17c], P0 ; /* 0x00005f00ff057624 */
/* 0x000fe200000e06ff */
/*0130*/ I2F.U16 R2, R6 ; /* 0x0000000600027306 */
/* 0x004e300000101000 */
/*0140*/ I2F.U16 R10, R10 ; /* 0x0000000a000a7306 */
/* 0x008e700000101000 */
/*0150*/ I2F.U16 R12, R8 ; /* 0x00000008000c7306 */
/* 0x010ea20000101000 */
/*0160*/ FMUL R3, R2, 0.58700001239776611328 ; /* 0x3f1645a202037820 */
/* 0x001fc80000400000 */
/*0170*/ FFMA R3, R10, 0.11400000005960464478, R3 ; /* 0x3de978d50a037823 */
/* 0x002fc80000000003 */
/*0180*/ FFMA R12, R12, 0.29899999499320983887, R3 ; /* 0x3e9916870c0c7823 */
/* 0x004fc80000000003 */
/*0190*/ F2F.F64.F32 R2, R12 ; /* 0x0000000c00027310 */
/* 0x000e240000201800 */
/*01a0*/ DADD R2, R2, 0.5 ; /* 0x3fe0000002027429 */
/* 0x001e140000000000 */
/*01b0*/ F2I.U32.F64.TRUNC R3, R2 ; /* 0x0000000200037311 */
/* 0x001e24000030d000 */
/*01c0*/ STG.E.U8 [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x001fe2000c101104 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cuda_runtime_api.h>
#include<stdio.h>
__global__ void cuda_gray_kernel(unsigned char *b, unsigned char *g, unsigned char *r, unsigned char *gray, size_t size)
{
size_t idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx >= size) {
return;
}
gray[idx] = (unsigned char)(0.114f*b[idx] + 0.587f*g[idx] + 0.299f*r[idx] + 0.5);
}
extern "C" {
void cuda_gray(unsigned char *a, unsigned char *b, unsigned char *c, unsigned char *d, size_t size)
{
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
unsigned char *d_a, *d_b, *d_c, *d_d;
cudaMalloc((void **)&d_a, size * sizeof(char));
cudaMalloc((void **)&d_b, size * sizeof(char));
cudaMalloc((void **)&d_c, size * sizeof(char));
cudaMalloc((void **)&d_d, size * sizeof(char));
cudaMemcpy(d_a, a, size * sizeof(char), cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size * sizeof(char), cudaMemcpyHostToDevice);
cudaMemcpy(d_c, c, size * sizeof(char), cudaMemcpyHostToDevice);
cudaMemcpy(d_d, d, size * sizeof(char), cudaMemcpyHostToDevice);
cudaEventRecord(start);
cuda_gray_kernel <<< ceil(size / 1024.0), 1024 >>> (d_a, d_b, d_c, d_d, size);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("Time on GPU : %f msec\n", milliseconds);
cudaMemcpy(d, d_d, size * sizeof(char), cudaMemcpyDeviceToHost);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
cudaFree(d_d);
}
} | .file "tmpxft_0010459c_00000000-6_cuda_lib.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z16cuda_gray_kernelPhS_S_S_mPhS_S_S_m
.type _Z43__device_stub__Z16cuda_gray_kernelPhS_S_S_mPhS_S_S_m, @function
_Z43__device_stub__Z16cuda_gray_kernelPhS_S_S_mPhS_S_S_m:
.LFB2082:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16cuda_gray_kernelPhS_S_S_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z43__device_stub__Z16cuda_gray_kernelPhS_S_S_mPhS_S_S_m, .-_Z43__device_stub__Z16cuda_gray_kernelPhS_S_S_mPhS_S_S_m
.globl _Z16cuda_gray_kernelPhS_S_S_m
.type _Z16cuda_gray_kernelPhS_S_S_m, @function
_Z16cuda_gray_kernelPhS_S_S_m:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z16cuda_gray_kernelPhS_S_S_mPhS_S_S_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z16cuda_gray_kernelPhS_S_S_m, .-_Z16cuda_gray_kernelPhS_S_S_m
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "Time on GPU : %f msec\n"
.text
.globl cuda_gray
.type cuda_gray, @function
cuda_gray:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movq %rcx, %rbp
movq %r8, %rbx
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
call cudaEventCreate@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq (%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
testq %rbx, %rbx
js .L12
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
.L13:
mulsd .LC0(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC6(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC1(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L14
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC3(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L14:
cvttsd2siq %xmm3, %rax
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L15:
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movq 8(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 60(%rsp)
leaq 60(%rsp), %rdi
movq 8(%rsp), %rdx
movq (%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 60(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movq %rbx, %rax
shrq %rax
movq %rbx, %rdx
andl $1, %edx
orq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
jmp .L13
.L18:
movq %rbx, %r8
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z43__device_stub__Z16cuda_gray_kernelPhS_S_S_mPhS_S_S_m
jmp .L15
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size cuda_gray, .-cuda_gray
.section .rodata.str1.1
.LC7:
.string "_Z16cuda_gray_kernelPhS_S_S_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z16cuda_gray_kernelPhS_S_S_m(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1062207488
.align 8
.LC1:
.long 0
.long 1127219200
.align 8
.LC3:
.long 0
.long 1072693248
.align 8
.LC6:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cuda_runtime_api.h>
#include<stdio.h>
__global__ void cuda_gray_kernel(unsigned char *b, unsigned char *g, unsigned char *r, unsigned char *gray, size_t size)
{
size_t idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx >= size) {
return;
}
gray[idx] = (unsigned char)(0.114f*b[idx] + 0.587f*g[idx] + 0.299f*r[idx] + 0.5);
}
extern "C" {
void cuda_gray(unsigned char *a, unsigned char *b, unsigned char *c, unsigned char *d, size_t size)
{
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
unsigned char *d_a, *d_b, *d_c, *d_d;
cudaMalloc((void **)&d_a, size * sizeof(char));
cudaMalloc((void **)&d_b, size * sizeof(char));
cudaMalloc((void **)&d_c, size * sizeof(char));
cudaMalloc((void **)&d_d, size * sizeof(char));
cudaMemcpy(d_a, a, size * sizeof(char), cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size * sizeof(char), cudaMemcpyHostToDevice);
cudaMemcpy(d_c, c, size * sizeof(char), cudaMemcpyHostToDevice);
cudaMemcpy(d_d, d, size * sizeof(char), cudaMemcpyHostToDevice);
cudaEventRecord(start);
cuda_gray_kernel <<< ceil(size / 1024.0), 1024 >>> (d_a, d_b, d_c, d_d, size);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
printf("Time on GPU : %f msec\n", milliseconds);
cudaMemcpy(d, d_d, size * sizeof(char), cudaMemcpyDeviceToHost);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
cudaFree(d_d);
}
} | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include<stdio.h>
__global__ void cuda_gray_kernel(unsigned char *b, unsigned char *g, unsigned char *r, unsigned char *gray, size_t size)
{
size_t idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx >= size) {
return;
}
gray[idx] = (unsigned char)(0.114f*b[idx] + 0.587f*g[idx] + 0.299f*r[idx] + 0.5);
}
extern "C" {
void cuda_gray(unsigned char *a, unsigned char *b, unsigned char *c, unsigned char *d, size_t size)
{
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
unsigned char *d_a, *d_b, *d_c, *d_d;
hipMalloc((void **)&d_a, size * sizeof(char));
hipMalloc((void **)&d_b, size * sizeof(char));
hipMalloc((void **)&d_c, size * sizeof(char));
hipMalloc((void **)&d_d, size * sizeof(char));
hipMemcpy(d_a, a, size * sizeof(char), hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size * sizeof(char), hipMemcpyHostToDevice);
hipMemcpy(d_c, c, size * sizeof(char), hipMemcpyHostToDevice);
hipMemcpy(d_d, d, size * sizeof(char), hipMemcpyHostToDevice);
hipEventRecord(start);
cuda_gray_kernel <<< ceil(size / 1024.0), 1024 >>> (d_a, d_b, d_c, d_d, size);
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
printf("Time on GPU : %f msec\n", milliseconds);
hipMemcpy(d, d_d, size * sizeof(char), hipMemcpyDeviceToHost);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
hipFree(d_d);
}
} |
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