system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //##########################################################//
// Name: Kirtan Mali //
// Roll no: 18AG10016 //
// Question 2: Matrix Transpose using Rect Tiles //
//##########################################################//
#include <stdio.h>
#include <stdlib.h>
// Cuda Libraries
#include <cuda.h>
#include <cuda_runtime.h>
// Macro for error checking and debugging
#define CHECK(call) { \
const cudaError_t error = call; \
if (error != cudaSuccess) { \
printf("Error: %s:%d, ", __FILE__, __LINE__); \
printf("code: %d, reason: %s\n", error, cudaGetErrorString(error)); \
exit(1); \
} \
}
typedef long long int lli;
#define MAX_VAL 100
#define TILEX 32
#define TILEY 16
#define BLOCKX 32
#define BLOCKY 16
void printMat(float *matrix, lli n);
void transpose_CPU(float *matrix, float *output, int n);
float *createMat(lli n, int isempty, int seed);
__global__ void transposeCoalesced_RECTTILES(float *matrix, float *output, int n)
{
// shared memory
__shared__ float tile[BLOCKY][BLOCKX];
// global memory index for original matrix
int ix = blockDim.x * blockIdx.x + threadIdx.x;
int iy = blockDim.y * blockIdx.y + threadIdx.y;
// transposed index in shared memory
int irow = (threadIdx.y * blockDim.x + threadIdx.x) % blockDim.y;
int icol = (threadIdx.y * blockDim.x + threadIdx.x) / blockDim.y;
// global memory index for transposed matrix
int ox = blockDim.y * blockIdx.y + irow;
int oy = blockDim.x * blockIdx.x + icol;
if (ix < n && iy < n) {
tile[threadIdx.y][threadIdx.x] = matrix[iy * n + ix];
__syncthreads();
output[oy * n + ox] = tile[irow][icol];
}
}
int main(int argc, char **argv)
{
// Error code to check return values for CUDA calls
cudaError_t err = cudaSuccess;
int isprint = 1;
if (argc > 1)
isprint = 0;
lli t;
scanf("%lld", &t);
while (t--)
{
srand(t);
lli n;
scanf("%lld", &n);
size_t size = sizeof(float) * n * n;
float *h_matrix = createMat(n, 0, t);
float *h_output = createMat(n, 1, t);
float *h_output_check = createMat(n, 1, t);
float *d_matrix = NULL;
float *d_output = NULL;
CHECK(cudaMalloc((void **)&d_matrix, size));
CHECK(cudaMalloc((void **)&d_output, size));
CHECK(cudaMemcpy(d_matrix, h_matrix, size, cudaMemcpyHostToDevice));
dim3 dimGrid((n + BLOCKX - 1) / BLOCKX, (n + BLOCKY - 1) / BLOCKY);
dim3 dimBlock(BLOCKX, BLOCKY);
transposeCoalesced_RECTTILES<<<dimGrid, dimBlock>>>(d_matrix, d_output, n);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch convolution_2D_DEVICE kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
CHECK(cudaMemcpy(h_output, d_output, size, cudaMemcpyDeviceToHost));
// transpose_CPU(h_matrix, h_output_check, n);
if (isprint == 1)
{
printf("\n\n***** Original Matrix *****\n\n");
printMat(h_matrix, n);
printf("\n\n***** Transposed Matrix using GPU *****\n\n");
printMat(h_output, n);
// printf("\n\n***** Transposed Matrix using CPU *****\n\n")
//printMat(h_output_check, n);
}
free(h_matrix);
free(h_output);
free(h_output_check);
cudaFree(d_matrix);
cudaFree(d_output);
}
return 0;
}
// Utility Functions
float *createMat(lli n, int isempty, int seed)
{
srand(seed+1);
size_t size = sizeof(float) * n * n;
float *matrix = (float *)malloc(size);
for (int i=0; i<n*n; i++)
{
if (isempty == 1)
matrix[i] = 0.0f;
else
matrix[i] = (float)rand()/((float)RAND_MAX/MAX_VAL);
}
return matrix;
}
void printMat(float *matrix, lli n)
{
for (lli i=0; i<n*n; i++)
{
printf("% 6.2f ", matrix[i]);
if (i % n == n-1)
printf("\n");
}
}
void transpose_CPU(float *matrix, float *output, int n)
{
for (int i=0; i<n; i++)
{
for (int j=0; j<n; j++)
{
output[i*n+j] = matrix[j*n+i];
}
}
} | code for sm_80
Function : _Z28transposeCoalesced_RECTTILESPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002600 */
/*0020*/ S2R R11, SR_TID.Y ; /* 0x00000000000b7919 */
/* 0x000e280000002200 */
/*0030*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e680000002500 */
/*0040*/ S2R R12, SR_TID.X ; /* 0x00000000000c7919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R4, R2, c[0x0][0x4], R11 ; /* 0x0000010002047a24 */
/* 0x001fca00078e020b */
/*0060*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R9, c[0x0][0x0], R12 ; /* 0x0000000009037a24 */
/* 0x002fca00078e020c */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x170], P0 ; /* 0x00005c0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R5, R4, c[0x0][0x170], R3 ; /* 0x00005c0004057a24 */
/* 0x000fe200078e0203 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R5, R0, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fcc00078e0200 */
/*00e0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x0000a2000c1e1900 */
/*00f0*/ I2F.U32.RP R8, c[0x0][0x4] ; /* 0x0000010000087b06 */
/* 0x000e620000209000 */
/*0100*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x4], PT ; /* 0x00000100ff007a0c */
/* 0x000fce0003f45070 */
/*0110*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x002e640000001000 */
/*0120*/ IADD3 R6, R8, 0xffffffe, RZ ; /* 0x0ffffffe08067810 */
/* 0x002fcc0007ffe0ff */
/*0130*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x0002e4000021f000 */
/*0140*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x002fe200078e00ff */
/*0150*/ IADD3 R3, RZ, -R7, RZ ; /* 0x80000007ff037210 */
/* 0x008fca0007ffe0ff */
/*0160*/ IMAD R3, R3, c[0x0][0x4], RZ ; /* 0x0000010003037a24 */
/* 0x000fc800078e02ff */
/*0170*/ IMAD.HI.U32 R10, R7, R3, R6 ; /* 0x00000003070a7227 */
/* 0x000fc800078e0006 */
/*0180*/ IMAD R3, R11.reuse, c[0x0][0x0], R12 ; /* 0x000000000b037a24 */
/* 0x040fe200078e020c */
/*0190*/ LEA R12, R11, R12, 0x5 ; /* 0x0000000c0b0c7211 */
/* 0x000fc600078e28ff */
/*01a0*/ IMAD.HI.U32 R10, R10, R3, RZ ; /* 0x000000030a0a7227 */
/* 0x000fca00078e00ff */
/*01b0*/ IADD3 R4, -R10, RZ, RZ ; /* 0x000000ff0a047210 */
/* 0x001fca0007ffe1ff */
/*01c0*/ IMAD R4, R4, c[0x0][0x4], R3 ; /* 0x0000010004047a24 */
/* 0x000fca00078e0203 */
/*01d0*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x4], PT ; /* 0x0000010004007a0c */
/* 0x000fda0003f06070 */
/*01e0*/ @P0 IADD3 R4, R4, -c[0x0][0x4], RZ ; /* 0x8000010004040a10 */
/* 0x000fe40007ffe0ff */
/*01f0*/ @P0 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a0810 */
/* 0x000fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x4], PT ; /* 0x0000010004007a0c */
/* 0x000fda0003f26070 */
/*0210*/ @P1 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a1810 */
/* 0x000fe40007ffe0ff */
/*0220*/ @!P2 LOP3.LUT R10, RZ, c[0x0][0x4], RZ, 0x33, !PT ; /* 0x00000100ff0aaa12 */
/* 0x000fca00078e33ff */
/*0230*/ IMAD.MOV R4, RZ, RZ, -R10 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a0a */
/*0240*/ IMAD R3, R4, c[0x0][0x4], R3 ; /* 0x0000010004037a24 */
/* 0x000fca00078e0203 */
/*0250*/ LEA R7, R3, R10, 0x5 ; /* 0x0000000a03077211 */
/* 0x000fe200078e28ff */
/*0260*/ IMAD R10, R9, c[0x0][0x0], R10 ; /* 0x00000000090a7a24 */
/* 0x000fe400078e020a */
/*0270*/ IMAD R3, R2, c[0x0][0x4], R3 ; /* 0x0000010002037a24 */
/* 0x000fc800078e0203 */
/*0280*/ IMAD R3, R10, c[0x0][0x170], R3 ; /* 0x00005c000a037a24 */
/* 0x000fc800078e0203 */
/*0290*/ IMAD.WIDE R2, R3, R0, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fe200078e0200 */
/*02a0*/ STS [R12.X4], R5 ; /* 0x000000050c007388 */
/* 0x004fe80000004800 */
/*02b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02c0*/ LDS R7, [R7.X4] ; /* 0x0000000007077984 */
/* 0x000e280000004800 */
/*02d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe2000c101904 */
/*02e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02f0*/ BRA 0x2f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //##########################################################//
// Name: Kirtan Mali //
// Roll no: 18AG10016 //
// Question 2: Matrix Transpose using Rect Tiles //
//##########################################################//
#include <stdio.h>
#include <stdlib.h>
// Cuda Libraries
#include <cuda.h>
#include <cuda_runtime.h>
// Macro for error checking and debugging
#define CHECK(call) { \
const cudaError_t error = call; \
if (error != cudaSuccess) { \
printf("Error: %s:%d, ", __FILE__, __LINE__); \
printf("code: %d, reason: %s\n", error, cudaGetErrorString(error)); \
exit(1); \
} \
}
typedef long long int lli;
#define MAX_VAL 100
#define TILEX 32
#define TILEY 16
#define BLOCKX 32
#define BLOCKY 16
void printMat(float *matrix, lli n);
void transpose_CPU(float *matrix, float *output, int n);
float *createMat(lli n, int isempty, int seed);
__global__ void transposeCoalesced_RECTTILES(float *matrix, float *output, int n)
{
// shared memory
__shared__ float tile[BLOCKY][BLOCKX];
// global memory index for original matrix
int ix = blockDim.x * blockIdx.x + threadIdx.x;
int iy = blockDim.y * blockIdx.y + threadIdx.y;
// transposed index in shared memory
int irow = (threadIdx.y * blockDim.x + threadIdx.x) % blockDim.y;
int icol = (threadIdx.y * blockDim.x + threadIdx.x) / blockDim.y;
// global memory index for transposed matrix
int ox = blockDim.y * blockIdx.y + irow;
int oy = blockDim.x * blockIdx.x + icol;
if (ix < n && iy < n) {
tile[threadIdx.y][threadIdx.x] = matrix[iy * n + ix];
__syncthreads();
output[oy * n + ox] = tile[irow][icol];
}
}
int main(int argc, char **argv)
{
// Error code to check return values for CUDA calls
cudaError_t err = cudaSuccess;
int isprint = 1;
if (argc > 1)
isprint = 0;
lli t;
scanf("%lld", &t);
while (t--)
{
srand(t);
lli n;
scanf("%lld", &n);
size_t size = sizeof(float) * n * n;
float *h_matrix = createMat(n, 0, t);
float *h_output = createMat(n, 1, t);
float *h_output_check = createMat(n, 1, t);
float *d_matrix = NULL;
float *d_output = NULL;
CHECK(cudaMalloc((void **)&d_matrix, size));
CHECK(cudaMalloc((void **)&d_output, size));
CHECK(cudaMemcpy(d_matrix, h_matrix, size, cudaMemcpyHostToDevice));
dim3 dimGrid((n + BLOCKX - 1) / BLOCKX, (n + BLOCKY - 1) / BLOCKY);
dim3 dimBlock(BLOCKX, BLOCKY);
transposeCoalesced_RECTTILES<<<dimGrid, dimBlock>>>(d_matrix, d_output, n);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch convolution_2D_DEVICE kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
CHECK(cudaMemcpy(h_output, d_output, size, cudaMemcpyDeviceToHost));
// transpose_CPU(h_matrix, h_output_check, n);
if (isprint == 1)
{
printf("\n\n***** Original Matrix *****\n\n");
printMat(h_matrix, n);
printf("\n\n***** Transposed Matrix using GPU *****\n\n");
printMat(h_output, n);
// printf("\n\n***** Transposed Matrix using CPU *****\n\n")
//printMat(h_output_check, n);
}
free(h_matrix);
free(h_output);
free(h_output_check);
cudaFree(d_matrix);
cudaFree(d_output);
}
return 0;
}
// Utility Functions
float *createMat(lli n, int isempty, int seed)
{
srand(seed+1);
size_t size = sizeof(float) * n * n;
float *matrix = (float *)malloc(size);
for (int i=0; i<n*n; i++)
{
if (isempty == 1)
matrix[i] = 0.0f;
else
matrix[i] = (float)rand()/((float)RAND_MAX/MAX_VAL);
}
return matrix;
}
void printMat(float *matrix, lli n)
{
for (lli i=0; i<n*n; i++)
{
printf("% 6.2f ", matrix[i]);
if (i % n == n-1)
printf("\n");
}
}
void transpose_CPU(float *matrix, float *output, int n)
{
for (int i=0; i<n; i++)
{
for (int j=0; j<n; j++)
{
output[i*n+j] = matrix[j*n+i];
}
}
} | .file "tmpxft_00108cb8_00000000-6_transpose_TILE2D.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9createMatxii
.type _Z9createMatxii, @function
_Z9createMatxii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movl %esi, %r13d
leal 1(%rdx), %edi
call srand@PLT
imulq %rbp, %rbp
leaq 0(,%rbp,4), %rdi
call malloc@PLT
movq %rax, %r12
testq %rbp, %rbp
jle .L3
movl $0, %ebx
jmp .L6
.L5:
movss %xmm0, (%r12,%rbx,4)
addq $1, %rbx
cmpq %rbp, %rbx
je .L3
.L6:
pxor %xmm0, %xmm0
cmpl $1, %r13d
je .L5
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
divss .LC1(%rip), %xmm0
jmp .L5
.L3:
movq %r12, %rax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z9createMatxii, .-_Z9createMatxii
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "% 6.2f "
.LC3:
.string "\n"
.text
.globl _Z8printMatPfx
.type _Z8printMatPfx, @function
_Z8printMatPfx:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rsi, %r13
imulq %rsi, %r13
testq %r13, %r13
jle .L10
movq %rdi, %r12
movq %rsi, %rbp
movl $0, %ebx
leaq .LC2(%rip), %r15
leaq -1(%rsi), %r14
jmp .L13
.L12:
addq $1, %rbx
cmpq %r13, %rbx
je .L10
.L13:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movq %r15, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %rax
cqto
idivq %rbp
cmpq %r14, %rdx
jne .L12
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L12
.L10:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z8printMatPfx, .-_Z8printMatPfx
.globl _Z13transpose_CPUPfS_i
.type _Z13transpose_CPUPfS_i, @function
_Z13transpose_CPUPfS_i:
.LFB2060:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L16
movslq %edx, %r10
leaq 0(,%r10,4), %r8
addq %r8, %rsi
negq %r10
salq $2, %r10
movl $0, %r9d
.L18:
leaq (%rsi,%r10), %rax
movq %rdi, %rcx
.L19:
movss (%rcx), %xmm0
movss %xmm0, (%rax)
addq %r8, %rcx
addq $4, %rax
cmpq %rsi, %rax
jne .L19
addl $1, %r9d
addq $4, %rdi
addq %r8, %rsi
cmpl %r9d, %edx
jne .L18
.L16:
ret
.cfi_endproc
.LFE2060:
.size _Z13transpose_CPUPfS_i, .-_Z13transpose_CPUPfS_i
.globl _Z51__device_stub__Z28transposeCoalesced_RECTTILESPfS_iPfS_i
.type _Z51__device_stub__Z28transposeCoalesced_RECTTILESPfS_iPfS_i, @function
_Z51__device_stub__Z28transposeCoalesced_RECTTILESPfS_iPfS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z28transposeCoalesced_RECTTILESPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z51__device_stub__Z28transposeCoalesced_RECTTILESPfS_iPfS_i, .-_Z51__device_stub__Z28transposeCoalesced_RECTTILESPfS_iPfS_i
.globl _Z28transposeCoalesced_RECTTILESPfS_i
.type _Z28transposeCoalesced_RECTTILESPfS_i, @function
_Z28transposeCoalesced_RECTTILESPfS_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z28transposeCoalesced_RECTTILESPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z28transposeCoalesced_RECTTILESPfS_i, .-_Z28transposeCoalesced_RECTTILESPfS_i
.section .rodata.str1.1
.LC4:
.string "%lld"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "/home/ubuntu/Datasets/stackv2/train-structured/KaLiMaLi555/hp3/master/term_assignments/transpose_TILE2D.cu"
.section .rodata.str1.1
.LC6:
.string "Error: %s:%d, "
.LC7:
.string "code: %d, reason: %s\n"
.section .rodata.str1.8
.align 8
.LC8:
.string "Failed to launch convolution_2D_DEVICE kernel (error code %s)!\n"
.align 8
.LC9:
.string "\n\n***** Original Matrix *****\n\n"
.align 8
.LC10:
.string "\n\n***** Transposed Matrix using GPU *****\n\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movl %edi, %r15d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rsi
leaq .LC4(%rip), %rdi
call __isoc23_scanf@PLT
movq 16(%rsp), %rax
leaq -1(%rax), %rdi
movq %rdi, 16(%rsp)
testq %rax, %rax
je .L30
leaq 24(%rsp), %rax
movq %rax, 8(%rsp)
jmp .L38
.L45:
movl $87, %ecx
leaq .LC5(%rip), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r13d, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L46:
movl $89, %ecx
leaq .LC5(%rip), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r13d, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L47:
movl $91, %ecx
leaq .LC5(%rip), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r13d, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L42
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L43
cmpl $1, %r15d
jle .L44
.L37:
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rax
leaq -1(%rax), %rdi
movq %rdi, 16(%rsp)
testq %rax, %rax
je .L30
.L38:
call srand@PLT
movq 8(%rsp), %rsi
leaq .LC4(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movq 24(%rsp), %rdi
movq %rdi, %rbx
imulq %rdi, %rbx
salq $2, %rbx
movl 16(%rsp), %edx
movl $0, %esi
call _Z9createMatxii
movq %rax, %rbp
movl 16(%rsp), %edx
movl $1, %esi
movq 24(%rsp), %rdi
call _Z9createMatxii
movq %rax, %r12
movl 16(%rsp), %edx
movl $1, %esi
movq 24(%rsp), %rdi
call _Z9createMatxii
movq %rax, %r14
movq $0, 32(%rsp)
movq $0, 40(%rsp)
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L45
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L46
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L47
movq 24(%rsp), %rax
leaq 62(%rax), %rdx
movq %rax, %rcx
addq $31, %rcx
cmovns %rcx, %rdx
sarq $5, %rdx
movl %edx, 48(%rsp)
leaq 30(%rax), %rdx
addq $15, %rax
cmovs %rdx, %rax
sarq $4, %rax
movl %eax, 52(%rsp)
movl $32, 60(%rsp)
movl $16, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L34
movl 24(%rsp), %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z51__device_stub__Z28transposeCoalesced_RECTTILESPfS_iPfS_i
jmp .L34
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L43:
movl $106, %ecx
leaq .LC5(%rip), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L44:
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rsi
movq %rbp, %rdi
call _Z8printMatPfx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rsi
movq %r12, %rdi
call _Z8printMatPfx
jmp .L37
.L30:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L48
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC11:
.string "_Z28transposeCoalesced_RECTTILESPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z28transposeCoalesced_RECTTILESPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1269028618
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //##########################################################//
// Name: Kirtan Mali //
// Roll no: 18AG10016 //
// Question 2: Matrix Transpose using Rect Tiles //
//##########################################################//
#include <stdio.h>
#include <stdlib.h>
// Cuda Libraries
#include <cuda.h>
#include <cuda_runtime.h>
// Macro for error checking and debugging
#define CHECK(call) { \
const cudaError_t error = call; \
if (error != cudaSuccess) { \
printf("Error: %s:%d, ", __FILE__, __LINE__); \
printf("code: %d, reason: %s\n", error, cudaGetErrorString(error)); \
exit(1); \
} \
}
typedef long long int lli;
#define MAX_VAL 100
#define TILEX 32
#define TILEY 16
#define BLOCKX 32
#define BLOCKY 16
void printMat(float *matrix, lli n);
void transpose_CPU(float *matrix, float *output, int n);
float *createMat(lli n, int isempty, int seed);
__global__ void transposeCoalesced_RECTTILES(float *matrix, float *output, int n)
{
// shared memory
__shared__ float tile[BLOCKY][BLOCKX];
// global memory index for original matrix
int ix = blockDim.x * blockIdx.x + threadIdx.x;
int iy = blockDim.y * blockIdx.y + threadIdx.y;
// transposed index in shared memory
int irow = (threadIdx.y * blockDim.x + threadIdx.x) % blockDim.y;
int icol = (threadIdx.y * blockDim.x + threadIdx.x) / blockDim.y;
// global memory index for transposed matrix
int ox = blockDim.y * blockIdx.y + irow;
int oy = blockDim.x * blockIdx.x + icol;
if (ix < n && iy < n) {
tile[threadIdx.y][threadIdx.x] = matrix[iy * n + ix];
__syncthreads();
output[oy * n + ox] = tile[irow][icol];
}
}
int main(int argc, char **argv)
{
// Error code to check return values for CUDA calls
cudaError_t err = cudaSuccess;
int isprint = 1;
if (argc > 1)
isprint = 0;
lli t;
scanf("%lld", &t);
while (t--)
{
srand(t);
lli n;
scanf("%lld", &n);
size_t size = sizeof(float) * n * n;
float *h_matrix = createMat(n, 0, t);
float *h_output = createMat(n, 1, t);
float *h_output_check = createMat(n, 1, t);
float *d_matrix = NULL;
float *d_output = NULL;
CHECK(cudaMalloc((void **)&d_matrix, size));
CHECK(cudaMalloc((void **)&d_output, size));
CHECK(cudaMemcpy(d_matrix, h_matrix, size, cudaMemcpyHostToDevice));
dim3 dimGrid((n + BLOCKX - 1) / BLOCKX, (n + BLOCKY - 1) / BLOCKY);
dim3 dimBlock(BLOCKX, BLOCKY);
transposeCoalesced_RECTTILES<<<dimGrid, dimBlock>>>(d_matrix, d_output, n);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch convolution_2D_DEVICE kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
CHECK(cudaMemcpy(h_output, d_output, size, cudaMemcpyDeviceToHost));
// transpose_CPU(h_matrix, h_output_check, n);
if (isprint == 1)
{
printf("\n\n***** Original Matrix *****\n\n");
printMat(h_matrix, n);
printf("\n\n***** Transposed Matrix using GPU *****\n\n");
printMat(h_output, n);
// printf("\n\n***** Transposed Matrix using CPU *****\n\n")
//printMat(h_output_check, n);
}
free(h_matrix);
free(h_output);
free(h_output_check);
cudaFree(d_matrix);
cudaFree(d_output);
}
return 0;
}
// Utility Functions
float *createMat(lli n, int isempty, int seed)
{
srand(seed+1);
size_t size = sizeof(float) * n * n;
float *matrix = (float *)malloc(size);
for (int i=0; i<n*n; i++)
{
if (isempty == 1)
matrix[i] = 0.0f;
else
matrix[i] = (float)rand()/((float)RAND_MAX/MAX_VAL);
}
return matrix;
}
void printMat(float *matrix, lli n)
{
for (lli i=0; i<n*n; i++)
{
printf("% 6.2f ", matrix[i]);
if (i % n == n-1)
printf("\n");
}
}
void transpose_CPU(float *matrix, float *output, int n)
{
for (int i=0; i<n; i++)
{
for (int j=0; j<n; j++)
{
output[i*n+j] = matrix[j*n+i];
}
}
} | //##########################################################//
// Name: Kirtan Mali //
// Roll no: 18AG10016 //
// Question 2: Matrix Transpose using Rect Tiles //
//##########################################################//
#include <stdio.h>
#include <stdlib.h>
// Cuda Libraries
#include <hip/hip_runtime.h>
// Macro for error checking and debugging
#define CHECK(call) { \
const hipError_t error = call; \
if (error != hipSuccess) { \
printf("Error: %s:%d, ", __FILE__, __LINE__); \
printf("code: %d, reason: %s\n", error, hipGetErrorString(error)); \
exit(1); \
} \
}
typedef long long int lli;
#define MAX_VAL 100
#define TILEX 32
#define TILEY 16
#define BLOCKX 32
#define BLOCKY 16
void printMat(float *matrix, lli n);
void transpose_CPU(float *matrix, float *output, int n);
float *createMat(lli n, int isempty, int seed);
__global__ void transposeCoalesced_RECTTILES(float *matrix, float *output, int n)
{
// shared memory
__shared__ float tile[BLOCKY][BLOCKX];
// global memory index for original matrix
int ix = blockDim.x * blockIdx.x + threadIdx.x;
int iy = blockDim.y * blockIdx.y + threadIdx.y;
// transposed index in shared memory
int irow = (threadIdx.y * blockDim.x + threadIdx.x) % blockDim.y;
int icol = (threadIdx.y * blockDim.x + threadIdx.x) / blockDim.y;
// global memory index for transposed matrix
int ox = blockDim.y * blockIdx.y + irow;
int oy = blockDim.x * blockIdx.x + icol;
if (ix < n && iy < n) {
tile[threadIdx.y][threadIdx.x] = matrix[iy * n + ix];
__syncthreads();
output[oy * n + ox] = tile[irow][icol];
}
}
int main(int argc, char **argv)
{
// Error code to check return values for CUDA calls
hipError_t err = hipSuccess;
int isprint = 1;
if (argc > 1)
isprint = 0;
lli t;
scanf("%lld", &t);
while (t--)
{
srand(t);
lli n;
scanf("%lld", &n);
size_t size = sizeof(float) * n * n;
float *h_matrix = createMat(n, 0, t);
float *h_output = createMat(n, 1, t);
float *h_output_check = createMat(n, 1, t);
float *d_matrix = NULL;
float *d_output = NULL;
CHECK(hipMalloc((void **)&d_matrix, size));
CHECK(hipMalloc((void **)&d_output, size));
CHECK(hipMemcpy(d_matrix, h_matrix, size, hipMemcpyHostToDevice));
dim3 dimGrid((n + BLOCKX - 1) / BLOCKX, (n + BLOCKY - 1) / BLOCKY);
dim3 dimBlock(BLOCKX, BLOCKY);
transposeCoalesced_RECTTILES<<<dimGrid, dimBlock>>>(d_matrix, d_output, n);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch convolution_2D_DEVICE kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
CHECK(hipMemcpy(h_output, d_output, size, hipMemcpyDeviceToHost));
// transpose_CPU(h_matrix, h_output_check, n);
if (isprint == 1)
{
printf("\n\n***** Original Matrix *****\n\n");
printMat(h_matrix, n);
printf("\n\n***** Transposed Matrix using GPU *****\n\n");
printMat(h_output, n);
// printf("\n\n***** Transposed Matrix using CPU *****\n\n")
//printMat(h_output_check, n);
}
free(h_matrix);
free(h_output);
free(h_output_check);
hipFree(d_matrix);
hipFree(d_output);
}
return 0;
}
// Utility Functions
float *createMat(lli n, int isempty, int seed)
{
srand(seed+1);
size_t size = sizeof(float) * n * n;
float *matrix = (float *)malloc(size);
for (int i=0; i<n*n; i++)
{
if (isempty == 1)
matrix[i] = 0.0f;
else
matrix[i] = (float)rand()/((float)RAND_MAX/MAX_VAL);
}
return matrix;
}
void printMat(float *matrix, lli n)
{
for (lli i=0; i<n*n; i++)
{
printf("% 6.2f ", matrix[i]);
if (i % n == n-1)
printf("\n");
}
}
void transpose_CPU(float *matrix, float *output, int n)
{
for (int i=0; i<n; i++)
{
for (int j=0; j<n; j++)
{
output[i*n+j] = matrix[j*n+i];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //##########################################################//
// Name: Kirtan Mali //
// Roll no: 18AG10016 //
// Question 2: Matrix Transpose using Rect Tiles //
//##########################################################//
#include <stdio.h>
#include <stdlib.h>
// Cuda Libraries
#include <hip/hip_runtime.h>
// Macro for error checking and debugging
#define CHECK(call) { \
const hipError_t error = call; \
if (error != hipSuccess) { \
printf("Error: %s:%d, ", __FILE__, __LINE__); \
printf("code: %d, reason: %s\n", error, hipGetErrorString(error)); \
exit(1); \
} \
}
typedef long long int lli;
#define MAX_VAL 100
#define TILEX 32
#define TILEY 16
#define BLOCKX 32
#define BLOCKY 16
void printMat(float *matrix, lli n);
void transpose_CPU(float *matrix, float *output, int n);
float *createMat(lli n, int isempty, int seed);
__global__ void transposeCoalesced_RECTTILES(float *matrix, float *output, int n)
{
// shared memory
__shared__ float tile[BLOCKY][BLOCKX];
// global memory index for original matrix
int ix = blockDim.x * blockIdx.x + threadIdx.x;
int iy = blockDim.y * blockIdx.y + threadIdx.y;
// transposed index in shared memory
int irow = (threadIdx.y * blockDim.x + threadIdx.x) % blockDim.y;
int icol = (threadIdx.y * blockDim.x + threadIdx.x) / blockDim.y;
// global memory index for transposed matrix
int ox = blockDim.y * blockIdx.y + irow;
int oy = blockDim.x * blockIdx.x + icol;
if (ix < n && iy < n) {
tile[threadIdx.y][threadIdx.x] = matrix[iy * n + ix];
__syncthreads();
output[oy * n + ox] = tile[irow][icol];
}
}
int main(int argc, char **argv)
{
// Error code to check return values for CUDA calls
hipError_t err = hipSuccess;
int isprint = 1;
if (argc > 1)
isprint = 0;
lli t;
scanf("%lld", &t);
while (t--)
{
srand(t);
lli n;
scanf("%lld", &n);
size_t size = sizeof(float) * n * n;
float *h_matrix = createMat(n, 0, t);
float *h_output = createMat(n, 1, t);
float *h_output_check = createMat(n, 1, t);
float *d_matrix = NULL;
float *d_output = NULL;
CHECK(hipMalloc((void **)&d_matrix, size));
CHECK(hipMalloc((void **)&d_output, size));
CHECK(hipMemcpy(d_matrix, h_matrix, size, hipMemcpyHostToDevice));
dim3 dimGrid((n + BLOCKX - 1) / BLOCKX, (n + BLOCKY - 1) / BLOCKY);
dim3 dimBlock(BLOCKX, BLOCKY);
transposeCoalesced_RECTTILES<<<dimGrid, dimBlock>>>(d_matrix, d_output, n);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch convolution_2D_DEVICE kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
CHECK(hipMemcpy(h_output, d_output, size, hipMemcpyDeviceToHost));
// transpose_CPU(h_matrix, h_output_check, n);
if (isprint == 1)
{
printf("\n\n***** Original Matrix *****\n\n");
printMat(h_matrix, n);
printf("\n\n***** Transposed Matrix using GPU *****\n\n");
printMat(h_output, n);
// printf("\n\n***** Transposed Matrix using CPU *****\n\n")
//printMat(h_output_check, n);
}
free(h_matrix);
free(h_output);
free(h_output_check);
hipFree(d_matrix);
hipFree(d_output);
}
return 0;
}
// Utility Functions
float *createMat(lli n, int isempty, int seed)
{
srand(seed+1);
size_t size = sizeof(float) * n * n;
float *matrix = (float *)malloc(size);
for (int i=0; i<n*n; i++)
{
if (isempty == 1)
matrix[i] = 0.0f;
else
matrix[i] = (float)rand()/((float)RAND_MAX/MAX_VAL);
}
return matrix;
}
void printMat(float *matrix, lli n)
{
for (lli i=0; i<n*n; i++)
{
printf("% 6.2f ", matrix[i]);
if (i % n == n-1)
printf("\n");
}
}
void transpose_CPU(float *matrix, float *output, int n)
{
for (int i=0; i<n; i++)
{
for (int j=0; j<n; j++)
{
output[i*n+j] = matrix[j*n+i];
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z28transposeCoalesced_RECTTILESPfS_i
.globl _Z28transposeCoalesced_RECTTILESPfS_i
.p2align 8
.type _Z28transposeCoalesced_RECTTILESPfS_i,@function
_Z28transposeCoalesced_RECTTILESPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s2, 0xffff
s_lshr_b32 s5, s2, 16
s_mul_i32 s14, s14, s6
s_mul_i32 s15, s15, s5
v_add_nc_u32_e32 v0, s14, v2
v_add_nc_u32_e32 v3, s15, v1
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v4, v0, v3
v_cmpx_gt_i32_e64 s4, v4
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[4:5], null, v3, s4, v[0:1]
v_cvt_f32_u32_e32 v0, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_iflag_f32_e32 v0, v0
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[4:5]
v_mad_u32_u24 v5, v1, s6, v2
v_lshlrev_b32_e32 v2, 2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
s_sub_i32 s0, 0, s5
v_lshl_add_u32 v1, v1, 7, v2
global_load_b32 v3, v[3:4], off
v_mul_lo_u32 v4, s0, v0
v_mul_hi_u32 v4, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v4
v_mul_hi_u32 v0, v5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v4, v0, s5
v_add_nc_u32_e32 v6, 1, v0
v_sub_nc_u32_e32 v4, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_subrev_nc_u32_e32 v7, s5, v4
v_cmp_le_u32_e32 vcc_lo, s5, v4
v_cndmask_b32_e32 v0, v0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v4, v7, vcc_lo
v_add_nc_u32_e32 v6, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s5, v4
v_cndmask_b32_e32 v0, v0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_lo_u32 v4, v0, s5
v_add_nc_u32_e32 v6, s14, v0
v_lshlrev_b32_e32 v0, 2, v0
v_mul_lo_u32 v6, v6, s4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v5, v4
v_lshl_add_u32 v2, v4, 7, v0
s_delay_alu instid0(VALU_DEP_3)
v_add3_u32 v0, v4, s15, v6
s_waitcnt vmcnt(0)
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v2, v2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z28transposeCoalesced_RECTTILESPfS_i
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z28transposeCoalesced_RECTTILESPfS_i, .Lfunc_end0-_Z28transposeCoalesced_RECTTILESPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z28transposeCoalesced_RECTTILESPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z28transposeCoalesced_RECTTILESPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //##########################################################//
// Name: Kirtan Mali //
// Roll no: 18AG10016 //
// Question 2: Matrix Transpose using Rect Tiles //
//##########################################################//
#include <stdio.h>
#include <stdlib.h>
// Cuda Libraries
#include <hip/hip_runtime.h>
// Macro for error checking and debugging
#define CHECK(call) { \
const hipError_t error = call; \
if (error != hipSuccess) { \
printf("Error: %s:%d, ", __FILE__, __LINE__); \
printf("code: %d, reason: %s\n", error, hipGetErrorString(error)); \
exit(1); \
} \
}
typedef long long int lli;
#define MAX_VAL 100
#define TILEX 32
#define TILEY 16
#define BLOCKX 32
#define BLOCKY 16
void printMat(float *matrix, lli n);
void transpose_CPU(float *matrix, float *output, int n);
float *createMat(lli n, int isempty, int seed);
__global__ void transposeCoalesced_RECTTILES(float *matrix, float *output, int n)
{
// shared memory
__shared__ float tile[BLOCKY][BLOCKX];
// global memory index for original matrix
int ix = blockDim.x * blockIdx.x + threadIdx.x;
int iy = blockDim.y * blockIdx.y + threadIdx.y;
// transposed index in shared memory
int irow = (threadIdx.y * blockDim.x + threadIdx.x) % blockDim.y;
int icol = (threadIdx.y * blockDim.x + threadIdx.x) / blockDim.y;
// global memory index for transposed matrix
int ox = blockDim.y * blockIdx.y + irow;
int oy = blockDim.x * blockIdx.x + icol;
if (ix < n && iy < n) {
tile[threadIdx.y][threadIdx.x] = matrix[iy * n + ix];
__syncthreads();
output[oy * n + ox] = tile[irow][icol];
}
}
int main(int argc, char **argv)
{
// Error code to check return values for CUDA calls
hipError_t err = hipSuccess;
int isprint = 1;
if (argc > 1)
isprint = 0;
lli t;
scanf("%lld", &t);
while (t--)
{
srand(t);
lli n;
scanf("%lld", &n);
size_t size = sizeof(float) * n * n;
float *h_matrix = createMat(n, 0, t);
float *h_output = createMat(n, 1, t);
float *h_output_check = createMat(n, 1, t);
float *d_matrix = NULL;
float *d_output = NULL;
CHECK(hipMalloc((void **)&d_matrix, size));
CHECK(hipMalloc((void **)&d_output, size));
CHECK(hipMemcpy(d_matrix, h_matrix, size, hipMemcpyHostToDevice));
dim3 dimGrid((n + BLOCKX - 1) / BLOCKX, (n + BLOCKY - 1) / BLOCKY);
dim3 dimBlock(BLOCKX, BLOCKY);
transposeCoalesced_RECTTILES<<<dimGrid, dimBlock>>>(d_matrix, d_output, n);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch convolution_2D_DEVICE kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
CHECK(hipMemcpy(h_output, d_output, size, hipMemcpyDeviceToHost));
// transpose_CPU(h_matrix, h_output_check, n);
if (isprint == 1)
{
printf("\n\n***** Original Matrix *****\n\n");
printMat(h_matrix, n);
printf("\n\n***** Transposed Matrix using GPU *****\n\n");
printMat(h_output, n);
// printf("\n\n***** Transposed Matrix using CPU *****\n\n")
//printMat(h_output_check, n);
}
free(h_matrix);
free(h_output);
free(h_output_check);
hipFree(d_matrix);
hipFree(d_output);
}
return 0;
}
// Utility Functions
float *createMat(lli n, int isempty, int seed)
{
srand(seed+1);
size_t size = sizeof(float) * n * n;
float *matrix = (float *)malloc(size);
for (int i=0; i<n*n; i++)
{
if (isempty == 1)
matrix[i] = 0.0f;
else
matrix[i] = (float)rand()/((float)RAND_MAX/MAX_VAL);
}
return matrix;
}
void printMat(float *matrix, lli n)
{
for (lli i=0; i<n*n; i++)
{
printf("% 6.2f ", matrix[i]);
if (i % n == n-1)
printf("\n");
}
}
void transpose_CPU(float *matrix, float *output, int n)
{
for (int i=0; i<n; i++)
{
for (int j=0; j<n; j++)
{
output[i*n+j] = matrix[j*n+i];
}
}
} | .text
.file "transpose_TILE2D.hip"
.globl _Z43__device_stub__transposeCoalesced_RECTTILESPfS_i # -- Begin function _Z43__device_stub__transposeCoalesced_RECTTILESPfS_i
.p2align 4, 0x90
.type _Z43__device_stub__transposeCoalesced_RECTTILESPfS_i,@function
_Z43__device_stub__transposeCoalesced_RECTTILESPfS_i: # @_Z43__device_stub__transposeCoalesced_RECTTILESPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z28transposeCoalesced_RECTTILESPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z43__device_stub__transposeCoalesced_RECTTILESPfS_i, .Lfunc_end0-_Z43__device_stub__transposeCoalesced_RECTTILESPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x4ba3d70a # float 21474836
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, 40(%rsp) # 4-byte Spill
leaq 8(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_31: # %_Z8printMatPfx.exit67
# in Loop: Header=BB1_1 Depth=1
movq %rbp, %rdi
callq free
movq %r14, %rdi
callq free
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
.LBB1_1: # =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
# Child Loop BB1_23 Depth 2
# Child Loop BB1_28 Depth 2
movq 8(%rsp), %rdi
subq $1, %rdi
movq %rdi, 8(%rsp)
jb .LBB1_32
# %bb.2: # in Loop: Header=BB1_1 Depth=1
# kill: def $edi killed $edi killed $rdi
callq srand
movl $.L.str, %edi
leaq 16(%rsp), %rsi
xorl %eax, %eax
callq __isoc23_scanf
movq 16(%rsp), %rbx
movq %rbx, %r14
imulq %rbx, %r14
leaq (,%r14,4), %r15
movl 8(%rsp), %edi
incl %edi
callq srand
movq %r15, %rdi
callq malloc
movq %rax, %rbp
testq %rbx, %rbx
je .LBB1_5
# %bb.3: # %.lr.ph.i
# in Loop: Header=BB1_1 Depth=1
cmpq $1, %r14
adcq $0, %r14
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss %xmm1, %xmm0
movss %xmm0, (%rbp,%rbx,4)
incq %rbx
cmpq %rbx, %r14
jne .LBB1_4
.LBB1_5: # %_Z9createMatxii.exit
# in Loop: Header=BB1_1 Depth=1
movq 16(%rsp), %rbx
movl 8(%rsp), %edi
incl %edi
callq srand
movq %rbx, %r12
imulq %rbx, %r12
leaq (,%r12,4), %rdi
callq malloc
movq %rax, %r14
testq %rbx, %rbx
je .LBB1_7
# %bb.6: # %.lr.ph.i44
# in Loop: Header=BB1_1 Depth=1
cmpq $1, %r12
adcq $0, %r12
shlq $2, %r12
movq %r14, %rdi
xorl %esi, %esi
movq %r12, %rdx
callq memset@PLT
.LBB1_7: # %_Z9createMatxii.exit49
# in Loop: Header=BB1_1 Depth=1
movl 8(%rsp), %edi
incl %edi
callq srand
movq $0, 32(%rsp)
movq $0, 24(%rsp)
leaq 32(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_8
# %bb.9: # in Loop: Header=BB1_1 Depth=1
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_10
# %bb.13: # in Loop: Header=BB1_1 Depth=1
movq 32(%rsp), %rdi
movq %rbp, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_14
# %bb.15: # in Loop: Header=BB1_1 Depth=1
movq 16(%rsp), %rax
leaq 31(%rax), %rcx
leaq 62(%rax), %rdx
testq %rcx, %rcx
cmovnsq %rcx, %rdx
shrq $5, %rdx
leaq 15(%rax), %rcx
addq $30, %rax
testq %rcx, %rcx
cmovnsq %rcx, %rax
andq $-16, %rax
shlq $28, %rax
movl %edx, %edi
orq %rax, %rdi
movl $1, %esi
movabsq $68719476768, %rdx # imm = 0x1000000020
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_17
# %bb.16: # in Loop: Header=BB1_1 Depth=1
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movl 16(%rsp), %edx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl %edx, 44(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 44(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z28transposeCoalesced_RECTTILESPfS_i, %edi
leaq 112(%rsp), %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_17: # in Loop: Header=BB1_1 Depth=1
callq hipGetLastError
testl %eax, %eax
jne .LBB1_33
# %bb.18: # in Loop: Header=BB1_1 Depth=1
movq 24(%rsp), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_19
# %bb.20: # in Loop: Header=BB1_1 Depth=1
cmpl $1, 40(%rsp) # 4-byte Folded Reload
jg .LBB1_31
# %bb.21: # in Loop: Header=BB1_1 Depth=1
movl $.Lstr, %edi
callq puts@PLT
movq 16(%rsp), %r13
testq %r13, %r13
je .LBB1_26
# %bb.22: # %.lr.ph.i58
# in Loop: Header=BB1_1 Depth=1
movq %r13, %r12
imulq %r13, %r12
leaq -1(%r13), %rbx
cmpq $1, %r12
adcq $0, %r12
xorl %r15d, %r15d
jmp .LBB1_23
.p2align 4, 0x90
.LBB1_25: # in Loop: Header=BB1_23 Depth=2
incq %r15
cmpq %r15, %r12
je .LBB1_26
.LBB1_23: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbp,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movq %r15, %rax
cqto
idivq %r13
cmpq %rbx, %rdx
jne .LBB1_25
# %bb.24: # in Loop: Header=BB1_23 Depth=2
movl $10, %edi
callq putchar@PLT
jmp .LBB1_25
.p2align 4, 0x90
.LBB1_26: # %_Z8printMatPfx.exit
# in Loop: Header=BB1_1 Depth=1
movl $.Lstr.1, %edi
callq puts@PLT
movq 16(%rsp), %r12
testq %r12, %r12
je .LBB1_31
# %bb.27: # %.lr.ph.i62
# in Loop: Header=BB1_1 Depth=1
movq %r12, %r13
imulq %r12, %r13
leaq -1(%r12), %rbx
cmpq $1, %r13
adcq $0, %r13
xorl %r15d, %r15d
jmp .LBB1_28
.p2align 4, 0x90
.LBB1_30: # in Loop: Header=BB1_28 Depth=2
incq %r15
cmpq %r15, %r13
je .LBB1_31
.LBB1_28: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movq %r15, %rax
cqto
idivq %r12
cmpq %rbx, %rdx
jne .LBB1_30
# %bb.29: # in Loop: Header=BB1_28 Depth=2
movl $10, %edi
callq putchar@PLT
jmp .LBB1_30
.LBB1_32: # %._crit_edge
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_19:
.cfi_def_cfa_offset 192
movl $.L.str.1, %edi
movl $.L.str.2, %esi
movl $106, %edx
jmp .LBB1_11
.LBB1_14:
movl $.L.str.1, %edi
movl $.L.str.2, %esi
movl $91, %edx
jmp .LBB1_11
.LBB1_8:
movl %eax, %r12d
movl $.L.str.1, %edi
movl $.L.str.2, %esi
movl $87, %edx
xorl %eax, %eax
callq printf
movl %r12d, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movl %r12d, %esi
jmp .LBB1_12
.LBB1_33:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB1_10:
movl $.L.str.1, %edi
movl $.L.str.2, %esi
movl $89, %edx
.LBB1_11:
movl %eax, %ebx
xorl %eax, %eax
callq printf
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movl %ebx, %esi
.LBB1_12:
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z9createMatxii
.LCPI2_0:
.long 0x4ba3d70a # float 21474836
.text
.globl _Z9createMatxii
.p2align 4, 0x90
.type _Z9createMatxii,@function
_Z9createMatxii: # @_Z9createMatxii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
# kill: def $edx killed $edx def $rdx
movl %esi, %ebx
movq %rdi, %r15
leal 1(%rdx), %edi
callq srand
movq %r15, %r12
imulq %r15, %r12
leaq (,%r12,4), %rdi
callq malloc
movq %rax, %r14
testq %r15, %r15
je .LBB2_5
# %bb.1: # %.lr.ph
cmpq $1, %r12
adcq $0, %r12
xorl %r15d, %r15d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_4: # in Loop: Header=BB2_2 Depth=1
movss %xmm0, (%r14,%r15,4)
incq %r15
cmpq %r15, %r12
je .LBB2_5
.LBB2_2: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cmpl $1, %ebx
je .LBB2_4
# %bb.3: # in Loop: Header=BB2_2 Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss .LCPI2_0(%rip), %xmm0
jmp .LBB2_4
.LBB2_5: # %._crit_edge
movq %r14, %rax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z9createMatxii, .Lfunc_end2-_Z9createMatxii
.cfi_endproc
# -- End function
.globl _Z8printMatPfx # -- Begin function _Z8printMatPfx
.p2align 4, 0x90
.type _Z8printMatPfx,@function
_Z8printMatPfx: # @_Z8printMatPfx
.cfi_startproc
# %bb.0:
testq %rsi, %rsi
je .LBB3_6
# %bb.1: # %.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
movq %rsi, %r12
imulq %rbx, %r12
leaq -1(%rsi), %r13
cmpq $1, %r12
adcq $0, %r12
xorl %r15d, %r15d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_4: # in Loop: Header=BB3_2 Depth=1
incq %r15
cmpq %r15, %r12
je .LBB3_5
.LBB3_2: # =>This Inner Loop Header: Depth=1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movq %r15, %rax
cqto
idivq %rbx
cmpq %r13, %rdx
jne .LBB3_4
# %bb.3: # in Loop: Header=BB3_2 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB3_4
.LBB3_5:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.LBB3_6: # %._crit_edge
retq
.Lfunc_end3:
.size _Z8printMatPfx, .Lfunc_end3-_Z8printMatPfx
.cfi_endproc
# -- End function
.globl _Z13transpose_CPUPfS_i # -- Begin function _Z13transpose_CPUPfS_i
.p2align 4, 0x90
.type _Z13transpose_CPUPfS_i,@function
_Z13transpose_CPUPfS_i: # @_Z13transpose_CPUPfS_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB4_6
# %bb.1: # %.preheader.lr.ph
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %edx, %eax
leaq (,%rax,4), %rcx
xorl %r8d, %r8d
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_3 Depth 2
movl %r8d, %r10d
leaq (%rsi,%r10,4), %r10
movq %rdi, %r11
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_3: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r11), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%r10,%rbx,4)
incq %rbx
addq %rcx, %r11
cmpq %rbx, %rax
jne .LBB4_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
incq %r9
addl %edx, %r8d
addq $4, %rdi
cmpq %rax, %r9
jne .LBB4_2
# %bb.5:
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.LBB4_6: # %._crit_edge17
retq
.Lfunc_end4:
.size _Z13transpose_CPUPfS_i, .Lfunc_end4-_Z13transpose_CPUPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28transposeCoalesced_RECTTILESPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z28transposeCoalesced_RECTTILESPfS_i,@object # @_Z28transposeCoalesced_RECTTILESPfS_i
.section .rodata,"a",@progbits
.globl _Z28transposeCoalesced_RECTTILESPfS_i
.p2align 3, 0x0
_Z28transposeCoalesced_RECTTILESPfS_i:
.quad _Z43__device_stub__transposeCoalesced_RECTTILESPfS_i
.size _Z28transposeCoalesced_RECTTILESPfS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%lld"
.size .L.str, 5
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error: %s:%d, "
.size .L.str.1, 15
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/KaLiMaLi555/hp3/master/term_assignments/transpose_TILE2D.hip"
.size .L.str.2, 118
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "code: %d, reason: %s\n"
.size .L.str.3, 22
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to launch convolution_2D_DEVICE kernel (error code %s)!\n"
.size .L.str.4, 64
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "% 6.2f "
.size .L.str.7, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z28transposeCoalesced_RECTTILESPfS_i"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n\n***** Original Matrix *****\n"
.size .Lstr, 31
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n\n***** Transposed Matrix using GPU *****\n"
.size .Lstr.1, 43
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z43__device_stub__transposeCoalesced_RECTTILESPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z28transposeCoalesced_RECTTILESPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z28transposeCoalesced_RECTTILESPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002600 */
/*0020*/ S2R R11, SR_TID.Y ; /* 0x00000000000b7919 */
/* 0x000e280000002200 */
/*0030*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e680000002500 */
/*0040*/ S2R R12, SR_TID.X ; /* 0x00000000000c7919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R4, R2, c[0x0][0x4], R11 ; /* 0x0000010002047a24 */
/* 0x001fca00078e020b */
/*0060*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R9, c[0x0][0x0], R12 ; /* 0x0000000009037a24 */
/* 0x002fca00078e020c */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x170], P0 ; /* 0x00005c0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R5, R4, c[0x0][0x170], R3 ; /* 0x00005c0004057a24 */
/* 0x000fe200078e0203 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R5, R0, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fcc00078e0200 */
/*00e0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x0000a2000c1e1900 */
/*00f0*/ I2F.U32.RP R8, c[0x0][0x4] ; /* 0x0000010000087b06 */
/* 0x000e620000209000 */
/*0100*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x4], PT ; /* 0x00000100ff007a0c */
/* 0x000fce0003f45070 */
/*0110*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x002e640000001000 */
/*0120*/ IADD3 R6, R8, 0xffffffe, RZ ; /* 0x0ffffffe08067810 */
/* 0x002fcc0007ffe0ff */
/*0130*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x0002e4000021f000 */
/*0140*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x002fe200078e00ff */
/*0150*/ IADD3 R3, RZ, -R7, RZ ; /* 0x80000007ff037210 */
/* 0x008fca0007ffe0ff */
/*0160*/ IMAD R3, R3, c[0x0][0x4], RZ ; /* 0x0000010003037a24 */
/* 0x000fc800078e02ff */
/*0170*/ IMAD.HI.U32 R10, R7, R3, R6 ; /* 0x00000003070a7227 */
/* 0x000fc800078e0006 */
/*0180*/ IMAD R3, R11.reuse, c[0x0][0x0], R12 ; /* 0x000000000b037a24 */
/* 0x040fe200078e020c */
/*0190*/ LEA R12, R11, R12, 0x5 ; /* 0x0000000c0b0c7211 */
/* 0x000fc600078e28ff */
/*01a0*/ IMAD.HI.U32 R10, R10, R3, RZ ; /* 0x000000030a0a7227 */
/* 0x000fca00078e00ff */
/*01b0*/ IADD3 R4, -R10, RZ, RZ ; /* 0x000000ff0a047210 */
/* 0x001fca0007ffe1ff */
/*01c0*/ IMAD R4, R4, c[0x0][0x4], R3 ; /* 0x0000010004047a24 */
/* 0x000fca00078e0203 */
/*01d0*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x4], PT ; /* 0x0000010004007a0c */
/* 0x000fda0003f06070 */
/*01e0*/ @P0 IADD3 R4, R4, -c[0x0][0x4], RZ ; /* 0x8000010004040a10 */
/* 0x000fe40007ffe0ff */
/*01f0*/ @P0 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a0810 */
/* 0x000fe40007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x4], PT ; /* 0x0000010004007a0c */
/* 0x000fda0003f26070 */
/*0210*/ @P1 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a1810 */
/* 0x000fe40007ffe0ff */
/*0220*/ @!P2 LOP3.LUT R10, RZ, c[0x0][0x4], RZ, 0x33, !PT ; /* 0x00000100ff0aaa12 */
/* 0x000fca00078e33ff */
/*0230*/ IMAD.MOV R4, RZ, RZ, -R10 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a0a */
/*0240*/ IMAD R3, R4, c[0x0][0x4], R3 ; /* 0x0000010004037a24 */
/* 0x000fca00078e0203 */
/*0250*/ LEA R7, R3, R10, 0x5 ; /* 0x0000000a03077211 */
/* 0x000fe200078e28ff */
/*0260*/ IMAD R10, R9, c[0x0][0x0], R10 ; /* 0x00000000090a7a24 */
/* 0x000fe400078e020a */
/*0270*/ IMAD R3, R2, c[0x0][0x4], R3 ; /* 0x0000010002037a24 */
/* 0x000fc800078e0203 */
/*0280*/ IMAD R3, R10, c[0x0][0x170], R3 ; /* 0x00005c000a037a24 */
/* 0x000fc800078e0203 */
/*0290*/ IMAD.WIDE R2, R3, R0, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fe200078e0200 */
/*02a0*/ STS [R12.X4], R5 ; /* 0x000000050c007388 */
/* 0x004fe80000004800 */
/*02b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02c0*/ LDS R7, [R7.X4] ; /* 0x0000000007077984 */
/* 0x000e280000004800 */
/*02d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe2000c101904 */
/*02e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02f0*/ BRA 0x2f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z28transposeCoalesced_RECTTILESPfS_i
.globl _Z28transposeCoalesced_RECTTILESPfS_i
.p2align 8
.type _Z28transposeCoalesced_RECTTILESPfS_i,@function
_Z28transposeCoalesced_RECTTILESPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s2, 0xffff
s_lshr_b32 s5, s2, 16
s_mul_i32 s14, s14, s6
s_mul_i32 s15, s15, s5
v_add_nc_u32_e32 v0, s14, v2
v_add_nc_u32_e32 v3, s15, v1
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v4, v0, v3
v_cmpx_gt_i32_e64 s4, v4
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[4:5], null, v3, s4, v[0:1]
v_cvt_f32_u32_e32 v0, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_iflag_f32_e32 v0, v0
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[4:5]
v_mad_u32_u24 v5, v1, s6, v2
v_lshlrev_b32_e32 v2, 2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
s_sub_i32 s0, 0, s5
v_lshl_add_u32 v1, v1, 7, v2
global_load_b32 v3, v[3:4], off
v_mul_lo_u32 v4, s0, v0
v_mul_hi_u32 v4, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v4
v_mul_hi_u32 v0, v5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v4, v0, s5
v_add_nc_u32_e32 v6, 1, v0
v_sub_nc_u32_e32 v4, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_subrev_nc_u32_e32 v7, s5, v4
v_cmp_le_u32_e32 vcc_lo, s5, v4
v_cndmask_b32_e32 v0, v0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v4, v7, vcc_lo
v_add_nc_u32_e32 v6, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s5, v4
v_cndmask_b32_e32 v0, v0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_lo_u32 v4, v0, s5
v_add_nc_u32_e32 v6, s14, v0
v_lshlrev_b32_e32 v0, 2, v0
v_mul_lo_u32 v6, v6, s4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v5, v4
v_lshl_add_u32 v2, v4, 7, v0
s_delay_alu instid0(VALU_DEP_3)
v_add3_u32 v0, v4, s15, v6
s_waitcnt vmcnt(0)
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v2, v2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z28transposeCoalesced_RECTTILESPfS_i
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z28transposeCoalesced_RECTTILESPfS_i, .Lfunc_end0-_Z28transposeCoalesced_RECTTILESPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z28transposeCoalesced_RECTTILESPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z28transposeCoalesced_RECTTILESPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00108cb8_00000000-6_transpose_TILE2D.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9createMatxii
.type _Z9createMatxii, @function
_Z9createMatxii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movl %esi, %r13d
leal 1(%rdx), %edi
call srand@PLT
imulq %rbp, %rbp
leaq 0(,%rbp,4), %rdi
call malloc@PLT
movq %rax, %r12
testq %rbp, %rbp
jle .L3
movl $0, %ebx
jmp .L6
.L5:
movss %xmm0, (%r12,%rbx,4)
addq $1, %rbx
cmpq %rbp, %rbx
je .L3
.L6:
pxor %xmm0, %xmm0
cmpl $1, %r13d
je .L5
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
divss .LC1(%rip), %xmm0
jmp .L5
.L3:
movq %r12, %rax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z9createMatxii, .-_Z9createMatxii
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "% 6.2f "
.LC3:
.string "\n"
.text
.globl _Z8printMatPfx
.type _Z8printMatPfx, @function
_Z8printMatPfx:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rsi, %r13
imulq %rsi, %r13
testq %r13, %r13
jle .L10
movq %rdi, %r12
movq %rsi, %rbp
movl $0, %ebx
leaq .LC2(%rip), %r15
leaq -1(%rsi), %r14
jmp .L13
.L12:
addq $1, %rbx
cmpq %r13, %rbx
je .L10
.L13:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx,4), %xmm0
movq %r15, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %rax
cqto
idivq %rbp
cmpq %r14, %rdx
jne .L12
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L12
.L10:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z8printMatPfx, .-_Z8printMatPfx
.globl _Z13transpose_CPUPfS_i
.type _Z13transpose_CPUPfS_i, @function
_Z13transpose_CPUPfS_i:
.LFB2060:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L16
movslq %edx, %r10
leaq 0(,%r10,4), %r8
addq %r8, %rsi
negq %r10
salq $2, %r10
movl $0, %r9d
.L18:
leaq (%rsi,%r10), %rax
movq %rdi, %rcx
.L19:
movss (%rcx), %xmm0
movss %xmm0, (%rax)
addq %r8, %rcx
addq $4, %rax
cmpq %rsi, %rax
jne .L19
addl $1, %r9d
addq $4, %rdi
addq %r8, %rsi
cmpl %r9d, %edx
jne .L18
.L16:
ret
.cfi_endproc
.LFE2060:
.size _Z13transpose_CPUPfS_i, .-_Z13transpose_CPUPfS_i
.globl _Z51__device_stub__Z28transposeCoalesced_RECTTILESPfS_iPfS_i
.type _Z51__device_stub__Z28transposeCoalesced_RECTTILESPfS_iPfS_i, @function
_Z51__device_stub__Z28transposeCoalesced_RECTTILESPfS_iPfS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z28transposeCoalesced_RECTTILESPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z51__device_stub__Z28transposeCoalesced_RECTTILESPfS_iPfS_i, .-_Z51__device_stub__Z28transposeCoalesced_RECTTILESPfS_iPfS_i
.globl _Z28transposeCoalesced_RECTTILESPfS_i
.type _Z28transposeCoalesced_RECTTILESPfS_i, @function
_Z28transposeCoalesced_RECTTILESPfS_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z28transposeCoalesced_RECTTILESPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z28transposeCoalesced_RECTTILESPfS_i, .-_Z28transposeCoalesced_RECTTILESPfS_i
.section .rodata.str1.1
.LC4:
.string "%lld"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "/home/ubuntu/Datasets/stackv2/train-structured/KaLiMaLi555/hp3/master/term_assignments/transpose_TILE2D.cu"
.section .rodata.str1.1
.LC6:
.string "Error: %s:%d, "
.LC7:
.string "code: %d, reason: %s\n"
.section .rodata.str1.8
.align 8
.LC8:
.string "Failed to launch convolution_2D_DEVICE kernel (error code %s)!\n"
.align 8
.LC9:
.string "\n\n***** Original Matrix *****\n\n"
.align 8
.LC10:
.string "\n\n***** Transposed Matrix using GPU *****\n\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movl %edi, %r15d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rsi
leaq .LC4(%rip), %rdi
call __isoc23_scanf@PLT
movq 16(%rsp), %rax
leaq -1(%rax), %rdi
movq %rdi, 16(%rsp)
testq %rax, %rax
je .L30
leaq 24(%rsp), %rax
movq %rax, 8(%rsp)
jmp .L38
.L45:
movl $87, %ecx
leaq .LC5(%rip), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r13d, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L46:
movl $89, %ecx
leaq .LC5(%rip), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r13d, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L47:
movl $91, %ecx
leaq .LC5(%rip), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r13d, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r13d, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L42
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L43
cmpl $1, %r15d
jle .L44
.L37:
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rax
leaq -1(%rax), %rdi
movq %rdi, 16(%rsp)
testq %rax, %rax
je .L30
.L38:
call srand@PLT
movq 8(%rsp), %rsi
leaq .LC4(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movq 24(%rsp), %rdi
movq %rdi, %rbx
imulq %rdi, %rbx
salq $2, %rbx
movl 16(%rsp), %edx
movl $0, %esi
call _Z9createMatxii
movq %rax, %rbp
movl 16(%rsp), %edx
movl $1, %esi
movq 24(%rsp), %rdi
call _Z9createMatxii
movq %rax, %r12
movl 16(%rsp), %edx
movl $1, %esi
movq 24(%rsp), %rdi
call _Z9createMatxii
movq %rax, %r14
movq $0, 32(%rsp)
movq $0, 40(%rsp)
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L45
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L46
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r13d
testl %eax, %eax
jne .L47
movq 24(%rsp), %rax
leaq 62(%rax), %rdx
movq %rax, %rcx
addq $31, %rcx
cmovns %rcx, %rdx
sarq $5, %rdx
movl %edx, 48(%rsp)
leaq 30(%rax), %rdx
addq $15, %rax
cmovs %rdx, %rax
sarq $4, %rax
movl %eax, 52(%rsp)
movl $32, 60(%rsp)
movl $16, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L34
movl 24(%rsp), %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z51__device_stub__Z28transposeCoalesced_RECTTILESPfS_iPfS_i
jmp .L34
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L43:
movl $106, %ecx
leaq .LC5(%rip), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L44:
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rsi
movq %rbp, %rdi
call _Z8printMatPfx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rsi
movq %r12, %rdi
call _Z8printMatPfx
jmp .L37
.L30:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L48
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC11:
.string "_Z28transposeCoalesced_RECTTILESPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z28transposeCoalesced_RECTTILESPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1269028618
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "transpose_TILE2D.hip"
.globl _Z43__device_stub__transposeCoalesced_RECTTILESPfS_i # -- Begin function _Z43__device_stub__transposeCoalesced_RECTTILESPfS_i
.p2align 4, 0x90
.type _Z43__device_stub__transposeCoalesced_RECTTILESPfS_i,@function
_Z43__device_stub__transposeCoalesced_RECTTILESPfS_i: # @_Z43__device_stub__transposeCoalesced_RECTTILESPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z28transposeCoalesced_RECTTILESPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z43__device_stub__transposeCoalesced_RECTTILESPfS_i, .Lfunc_end0-_Z43__device_stub__transposeCoalesced_RECTTILESPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x4ba3d70a # float 21474836
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, 40(%rsp) # 4-byte Spill
leaq 8(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_31: # %_Z8printMatPfx.exit67
# in Loop: Header=BB1_1 Depth=1
movq %rbp, %rdi
callq free
movq %r14, %rdi
callq free
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
.LBB1_1: # =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
# Child Loop BB1_23 Depth 2
# Child Loop BB1_28 Depth 2
movq 8(%rsp), %rdi
subq $1, %rdi
movq %rdi, 8(%rsp)
jb .LBB1_32
# %bb.2: # in Loop: Header=BB1_1 Depth=1
# kill: def $edi killed $edi killed $rdi
callq srand
movl $.L.str, %edi
leaq 16(%rsp), %rsi
xorl %eax, %eax
callq __isoc23_scanf
movq 16(%rsp), %rbx
movq %rbx, %r14
imulq %rbx, %r14
leaq (,%r14,4), %r15
movl 8(%rsp), %edi
incl %edi
callq srand
movq %r15, %rdi
callq malloc
movq %rax, %rbp
testq %rbx, %rbx
je .LBB1_5
# %bb.3: # %.lr.ph.i
# in Loop: Header=BB1_1 Depth=1
cmpq $1, %r14
adcq $0, %r14
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss %xmm1, %xmm0
movss %xmm0, (%rbp,%rbx,4)
incq %rbx
cmpq %rbx, %r14
jne .LBB1_4
.LBB1_5: # %_Z9createMatxii.exit
# in Loop: Header=BB1_1 Depth=1
movq 16(%rsp), %rbx
movl 8(%rsp), %edi
incl %edi
callq srand
movq %rbx, %r12
imulq %rbx, %r12
leaq (,%r12,4), %rdi
callq malloc
movq %rax, %r14
testq %rbx, %rbx
je .LBB1_7
# %bb.6: # %.lr.ph.i44
# in Loop: Header=BB1_1 Depth=1
cmpq $1, %r12
adcq $0, %r12
shlq $2, %r12
movq %r14, %rdi
xorl %esi, %esi
movq %r12, %rdx
callq memset@PLT
.LBB1_7: # %_Z9createMatxii.exit49
# in Loop: Header=BB1_1 Depth=1
movl 8(%rsp), %edi
incl %edi
callq srand
movq $0, 32(%rsp)
movq $0, 24(%rsp)
leaq 32(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_8
# %bb.9: # in Loop: Header=BB1_1 Depth=1
leaq 24(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_10
# %bb.13: # in Loop: Header=BB1_1 Depth=1
movq 32(%rsp), %rdi
movq %rbp, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_14
# %bb.15: # in Loop: Header=BB1_1 Depth=1
movq 16(%rsp), %rax
leaq 31(%rax), %rcx
leaq 62(%rax), %rdx
testq %rcx, %rcx
cmovnsq %rcx, %rdx
shrq $5, %rdx
leaq 15(%rax), %rcx
addq $30, %rax
testq %rcx, %rcx
cmovnsq %rcx, %rax
andq $-16, %rax
shlq $28, %rax
movl %edx, %edi
orq %rax, %rdi
movl $1, %esi
movabsq $68719476768, %rdx # imm = 0x1000000020
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_17
# %bb.16: # in Loop: Header=BB1_1 Depth=1
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movl 16(%rsp), %edx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movl %edx, 44(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 44(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
movl $_Z28transposeCoalesced_RECTTILESPfS_i, %edi
leaq 112(%rsp), %r9
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_17: # in Loop: Header=BB1_1 Depth=1
callq hipGetLastError
testl %eax, %eax
jne .LBB1_33
# %bb.18: # in Loop: Header=BB1_1 Depth=1
movq 24(%rsp), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_19
# %bb.20: # in Loop: Header=BB1_1 Depth=1
cmpl $1, 40(%rsp) # 4-byte Folded Reload
jg .LBB1_31
# %bb.21: # in Loop: Header=BB1_1 Depth=1
movl $.Lstr, %edi
callq puts@PLT
movq 16(%rsp), %r13
testq %r13, %r13
je .LBB1_26
# %bb.22: # %.lr.ph.i58
# in Loop: Header=BB1_1 Depth=1
movq %r13, %r12
imulq %r13, %r12
leaq -1(%r13), %rbx
cmpq $1, %r12
adcq $0, %r12
xorl %r15d, %r15d
jmp .LBB1_23
.p2align 4, 0x90
.LBB1_25: # in Loop: Header=BB1_23 Depth=2
incq %r15
cmpq %r15, %r12
je .LBB1_26
.LBB1_23: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbp,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movq %r15, %rax
cqto
idivq %r13
cmpq %rbx, %rdx
jne .LBB1_25
# %bb.24: # in Loop: Header=BB1_23 Depth=2
movl $10, %edi
callq putchar@PLT
jmp .LBB1_25
.p2align 4, 0x90
.LBB1_26: # %_Z8printMatPfx.exit
# in Loop: Header=BB1_1 Depth=1
movl $.Lstr.1, %edi
callq puts@PLT
movq 16(%rsp), %r12
testq %r12, %r12
je .LBB1_31
# %bb.27: # %.lr.ph.i62
# in Loop: Header=BB1_1 Depth=1
movq %r12, %r13
imulq %r12, %r13
leaq -1(%r12), %rbx
cmpq $1, %r13
adcq $0, %r13
xorl %r15d, %r15d
jmp .LBB1_28
.p2align 4, 0x90
.LBB1_30: # in Loop: Header=BB1_28 Depth=2
incq %r15
cmpq %r15, %r13
je .LBB1_31
.LBB1_28: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movq %r15, %rax
cqto
idivq %r12
cmpq %rbx, %rdx
jne .LBB1_30
# %bb.29: # in Loop: Header=BB1_28 Depth=2
movl $10, %edi
callq putchar@PLT
jmp .LBB1_30
.LBB1_32: # %._crit_edge
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_19:
.cfi_def_cfa_offset 192
movl $.L.str.1, %edi
movl $.L.str.2, %esi
movl $106, %edx
jmp .LBB1_11
.LBB1_14:
movl $.L.str.1, %edi
movl $.L.str.2, %esi
movl $91, %edx
jmp .LBB1_11
.LBB1_8:
movl %eax, %r12d
movl $.L.str.1, %edi
movl $.L.str.2, %esi
movl $87, %edx
xorl %eax, %eax
callq printf
movl %r12d, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movl %r12d, %esi
jmp .LBB1_12
.LBB1_33:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB1_10:
movl $.L.str.1, %edi
movl $.L.str.2, %esi
movl $89, %edx
.LBB1_11:
movl %eax, %ebx
xorl %eax, %eax
callq printf
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movl %ebx, %esi
.LBB1_12:
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z9createMatxii
.LCPI2_0:
.long 0x4ba3d70a # float 21474836
.text
.globl _Z9createMatxii
.p2align 4, 0x90
.type _Z9createMatxii,@function
_Z9createMatxii: # @_Z9createMatxii
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
# kill: def $edx killed $edx def $rdx
movl %esi, %ebx
movq %rdi, %r15
leal 1(%rdx), %edi
callq srand
movq %r15, %r12
imulq %r15, %r12
leaq (,%r12,4), %rdi
callq malloc
movq %rax, %r14
testq %r15, %r15
je .LBB2_5
# %bb.1: # %.lr.ph
cmpq $1, %r12
adcq $0, %r12
xorl %r15d, %r15d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_4: # in Loop: Header=BB2_2 Depth=1
movss %xmm0, (%r14,%r15,4)
incq %r15
cmpq %r15, %r12
je .LBB2_5
.LBB2_2: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cmpl $1, %ebx
je .LBB2_4
# %bb.3: # in Loop: Header=BB2_2 Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss .LCPI2_0(%rip), %xmm0
jmp .LBB2_4
.LBB2_5: # %._crit_edge
movq %r14, %rax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z9createMatxii, .Lfunc_end2-_Z9createMatxii
.cfi_endproc
# -- End function
.globl _Z8printMatPfx # -- Begin function _Z8printMatPfx
.p2align 4, 0x90
.type _Z8printMatPfx,@function
_Z8printMatPfx: # @_Z8printMatPfx
.cfi_startproc
# %bb.0:
testq %rsi, %rsi
je .LBB3_6
# %bb.1: # %.lr.ph
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
movq %rsi, %r12
imulq %rbx, %r12
leaq -1(%rsi), %r13
cmpq $1, %r12
adcq $0, %r12
xorl %r15d, %r15d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_4: # in Loop: Header=BB3_2 Depth=1
incq %r15
cmpq %r15, %r12
je .LBB3_5
.LBB3_2: # =>This Inner Loop Header: Depth=1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movq %r15, %rax
cqto
idivq %rbx
cmpq %r13, %rdx
jne .LBB3_4
# %bb.3: # in Loop: Header=BB3_2 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB3_4
.LBB3_5:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.LBB3_6: # %._crit_edge
retq
.Lfunc_end3:
.size _Z8printMatPfx, .Lfunc_end3-_Z8printMatPfx
.cfi_endproc
# -- End function
.globl _Z13transpose_CPUPfS_i # -- Begin function _Z13transpose_CPUPfS_i
.p2align 4, 0x90
.type _Z13transpose_CPUPfS_i,@function
_Z13transpose_CPUPfS_i: # @_Z13transpose_CPUPfS_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB4_6
# %bb.1: # %.preheader.lr.ph
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %edx, %eax
leaq (,%rax,4), %rcx
xorl %r8d, %r8d
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_3 Depth 2
movl %r8d, %r10d
leaq (%rsi,%r10,4), %r10
movq %rdi, %r11
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB4_3: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r11), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%r10,%rbx,4)
incq %rbx
addq %rcx, %r11
cmpq %rbx, %rax
jne .LBB4_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
incq %r9
addl %edx, %r8d
addq $4, %rdi
cmpq %rax, %r9
jne .LBB4_2
# %bb.5:
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.LBB4_6: # %._crit_edge17
retq
.Lfunc_end4:
.size _Z13transpose_CPUPfS_i, .Lfunc_end4-_Z13transpose_CPUPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z28transposeCoalesced_RECTTILESPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z28transposeCoalesced_RECTTILESPfS_i,@object # @_Z28transposeCoalesced_RECTTILESPfS_i
.section .rodata,"a",@progbits
.globl _Z28transposeCoalesced_RECTTILESPfS_i
.p2align 3, 0x0
_Z28transposeCoalesced_RECTTILESPfS_i:
.quad _Z43__device_stub__transposeCoalesced_RECTTILESPfS_i
.size _Z28transposeCoalesced_RECTTILESPfS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%lld"
.size .L.str, 5
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error: %s:%d, "
.size .L.str.1, 15
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/KaLiMaLi555/hp3/master/term_assignments/transpose_TILE2D.hip"
.size .L.str.2, 118
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "code: %d, reason: %s\n"
.size .L.str.3, 22
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to launch convolution_2D_DEVICE kernel (error code %s)!\n"
.size .L.str.4, 64
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "% 6.2f "
.size .L.str.7, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z28transposeCoalesced_RECTTILESPfS_i"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n\n***** Original Matrix *****\n"
.size .Lstr, 31
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n\n***** Transposed Matrix using GPU *****\n"
.size .Lstr.1, 43
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z43__device_stub__transposeCoalesced_RECTTILESPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z28transposeCoalesced_RECTTILESPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* Null model based on cell link strength
* ranged between 0 and 1
*
* CUDA version
*
* compile with nvcc nco.cu -o nco -lcuda
*/
#include <stdlib.h>
#include <stdio.h>
#include <cuda.h>
#include <math.h>
#include <time.h>
#include <curand_kernel.h>
__global__ void nullmodel(float *M, int *out, curandState *states)
{
unsigned int tid = threadIdx.x + blockIdx.x * blockDim.x;
curand_init(threadIdx.x, 0, 0, &states[tid]);
float tar = (float)curand_uniform(&states[tid]);
out[tid] = (tar < M[tid])? 1 : 0;
}
int main(int argc, char **argv)
{
srand ( time(NULL) );
clock_t start, stop;
// PRNG
curandState *devStates;
// Network shape
int nrow = 100;
int ncol = 100;
double connec = 0.6;
int net_size = nrow * ncol;
// Memory allocation on host
const size_t nbytes_ref= net_size * sizeof(float);
const size_t nbytes_out= net_size * sizeof(int);
float *h_ref = (float*)malloc(nbytes_ref);
int *h_out = (int*)malloc(nbytes_out);
// create a random network -------
for(int row = 0; row < nrow; ++row)
{
for(int col = 0; col < ncol; ++col)
{
if((double)(rand() / (float)RAND_MAX) < connec)
{
h_ref[col + row*nrow] = (float)(rand() / (float)RAND_MAX);
}
}
}
// rand() / (float)RAND_MAX;
// Memory allocation on device
float *d_ref;
int *d_out;
cudaMalloc((void**)&d_ref, nbytes_ref);
cudaMalloc((void**)&d_out, nbytes_out);
// Memory transfer from host to device
cudaMemcpy(d_ref, h_ref, nbytes_ref, cudaMemcpyHostToDevice);
cudaMemcpy(d_out, h_out, nbytes_out, cudaMemcpyHostToDevice);
cudaMalloc( (void **)&devStates, net_size * sizeof(curandState) );
// Record initial time and start doing the null model
start = clock();
for(int repl = 0; repl < 1000; ++repl)
{
nullmodel<<<ncol,nrow>>>(d_ref, d_out, devStates);
// Memory transfer from the device to the host
cudaMemcpy(h_out, d_out, nbytes_ref, cudaMemcpyDeviceToHost);
}
stop = clock();
printf("1000 null network generated in %f s.\n", (stop-start)/(float)CLOCKS_PER_SEC);
// Free memory space
free(h_ref);
free(h_out);
cudaFree(d_ref);
cudaFree(d_out);
return EXIT_SUCCESS;
} | code for sm_80
Function : _Z9nullmodelPfPiP17curandStateXORWOW
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fe200078e00ff */
/*0030*/ HFMA2.MMA R12, -RZ, RZ, -38016, 0.02740478515625 ; /* 0xf8a42704ff0c7435 */
/* 0x000fe200000001ff */
/*0040*/ IMAD.MOV.U32 R13, RZ, RZ, -0x23270784 ; /* 0xdcd8f87cff0d7424 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0070*/ LOP3.LUT R0, R8, 0xaad26b49, RZ, 0x3c, !PT ; /* 0xaad26b4908007812 */
/* 0x001fe200078e3cff */
/*0080*/ IMAD R8, R5, c[0x0][0x0], R8 ; /* 0x0000000005087a24 */
/* 0x002fc800078e0208 */
/*0090*/ IMAD R0, R0, 0x4182bed5, RZ ; /* 0x4182bed500007824 */
/* 0x000fe400078e02ff */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x30 ; /* 0x00000030ff057424 */
/* 0x000fc600078e00ff */
/*00b0*/ IADD3 R2, R0.reuse, 0x75bcd15, RZ ; /* 0x075bcd1500027810 */
/* 0x040fe40007ffe0ff */
/*00c0*/ LOP3.LUT R11, R0.reuse, 0x159a55e5, RZ, 0x3c, !PT ; /* 0x159a55e5000b7812 */
/* 0x040fe400078e3cff */
/*00d0*/ SHF.R.U32.HI R3, RZ, 0x2, R2 ; /* 0x00000002ff037819 */
/* 0x000fe40000011602 */
/*00e0*/ IADD3 R10, R0.reuse, -0x26039c23, RZ ; /* 0xd9fc63dd000a7810 */
/* 0x040fe40007ffe0ff */
/*00f0*/ LOP3.LUT R3, R3, R2, RZ, 0x3c, !PT ; /* 0x0000000203037212 */
/* 0x000fe400078e3cff */
/*0100*/ IADD3 R2, R0, 0x583f19, RZ ; /* 0x00583f1900027810 */
/* 0x000fc60007ffe0ff */
/*0110*/ IMAD.SHL.U32 R4, R3, 0x2, RZ ; /* 0x0000000203047824 */
/* 0x000fca00078e00ff */
/*0120*/ LOP3.LUT R6, R2, R4, R3, 0x96, !PT ; /* 0x0000000402067212 */
/* 0x000fe200078e9603 */
/*0130*/ IMAD.WIDE.U32 R4, R8, R5, c[0x0][0x170] ; /* 0x00005c0008047625 */
/* 0x000fe200078e0005 */
/*0140*/ SHF.L.U32 R3, R2, 0x4, RZ ; /* 0x0000000402037819 */
/* 0x000fc800000006ff */
/*0150*/ LOP3.LUT R3, R6, R3, RZ, 0x3c, !PT ; /* 0x0000000306037212 */
/* 0x000fe200078e3cff */
/*0160*/ IMAD.WIDE.U32 R6, R8, R15, c[0x0][0x160] ; /* 0x0000580008067625 */
/* 0x000fe200078e000f */
/*0170*/ STG.E.64 [R4.64+0x8], R12 ; /* 0x0000080c04007986 */
/* 0x000fe8000c101b04 */
/*0180*/ STG.E.64 [R4.64], R10 ; /* 0x0000000a04007986 */
/* 0x0001e8000c101b04 */
/*0190*/ STG.E.64 [R4.64+0x18], RZ ; /* 0x000018ff04007986 */
/* 0x000fe8000c101b04 */
/*01a0*/ STG.E [R4.64+0x20], RZ ; /* 0x000020ff04007986 */
/* 0x000fe8000c101904 */
/*01b0*/ STG.E.64 [R4.64+0x28], RZ ; /* 0x000028ff04007986 */
/* 0x000fe8000c101b04 */
/*01c0*/ STG.E.64 [R4.64+0x10], R2 ; /* 0x0000100204007986 */
/* 0x000fe8000c101b04 */
/*01d0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*01e0*/ IMAD.IADD R0, R3, 0x1, R10 ; /* 0x0000000103007824 */
/* 0x000fe200078e020a */
/*01f0*/ MOV R9, 0x2f800000 ; /* 0x2f80000000097802 */
/* 0x000fca0000000f00 */
/*0200*/ I2F.U32 R0, R0 ; /* 0x0000000000007306 */
/* 0x000e640000201000 */
/*0210*/ FFMA R9, R0, R9, 1.1641532182693481445e-10 ; /* 0x2f00000000097423 */
/* 0x002fca0000000009 */
/*0220*/ FSETP.GEU.AND P0, PT, R9, R6, PT ; /* 0x000000060900720b */
/* 0x004fe20003f0e000 */
/*0230*/ IMAD.WIDE.U32 R8, R8, R15, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fc600078e000f */
/*0240*/ SEL R11, RZ, 0x1, P0 ; /* 0x00000001ff0b7807 */
/* 0x001fca0000000000 */
/*0250*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x000fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Null model based on cell link strength
* ranged between 0 and 1
*
* CUDA version
*
* compile with nvcc nco.cu -o nco -lcuda
*/
#include <stdlib.h>
#include <stdio.h>
#include <cuda.h>
#include <math.h>
#include <time.h>
#include <curand_kernel.h>
__global__ void nullmodel(float *M, int *out, curandState *states)
{
unsigned int tid = threadIdx.x + blockIdx.x * blockDim.x;
curand_init(threadIdx.x, 0, 0, &states[tid]);
float tar = (float)curand_uniform(&states[tid]);
out[tid] = (tar < M[tid])? 1 : 0;
}
int main(int argc, char **argv)
{
srand ( time(NULL) );
clock_t start, stop;
// PRNG
curandState *devStates;
// Network shape
int nrow = 100;
int ncol = 100;
double connec = 0.6;
int net_size = nrow * ncol;
// Memory allocation on host
const size_t nbytes_ref= net_size * sizeof(float);
const size_t nbytes_out= net_size * sizeof(int);
float *h_ref = (float*)malloc(nbytes_ref);
int *h_out = (int*)malloc(nbytes_out);
// create a random network -------
for(int row = 0; row < nrow; ++row)
{
for(int col = 0; col < ncol; ++col)
{
if((double)(rand() / (float)RAND_MAX) < connec)
{
h_ref[col + row*nrow] = (float)(rand() / (float)RAND_MAX);
}
}
}
// rand() / (float)RAND_MAX;
// Memory allocation on device
float *d_ref;
int *d_out;
cudaMalloc((void**)&d_ref, nbytes_ref);
cudaMalloc((void**)&d_out, nbytes_out);
// Memory transfer from host to device
cudaMemcpy(d_ref, h_ref, nbytes_ref, cudaMemcpyHostToDevice);
cudaMemcpy(d_out, h_out, nbytes_out, cudaMemcpyHostToDevice);
cudaMalloc( (void **)&devStates, net_size * sizeof(curandState) );
// Record initial time and start doing the null model
start = clock();
for(int repl = 0; repl < 1000; ++repl)
{
nullmodel<<<ncol,nrow>>>(d_ref, d_out, devStates);
// Memory transfer from the device to the host
cudaMemcpy(h_out, d_out, nbytes_ref, cudaMemcpyDeviceToHost);
}
stop = clock();
printf("1000 null network generated in %f s.\n", (stop-start)/(float)CLOCKS_PER_SEC);
// Free memory space
free(h_ref);
free(h_out);
cudaFree(d_ref);
cudaFree(d_out);
return EXIT_SUCCESS;
} | .file "tmpxft_0016bba0_00000000-6_nco.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2274:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2274:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z9nullmodelPfPiP17curandStateXORWOWPfPiP17curandStateXORWOW
.type _Z50__device_stub__Z9nullmodelPfPiP17curandStateXORWOWPfPiP17curandStateXORWOW, @function
_Z50__device_stub__Z9nullmodelPfPiP17curandStateXORWOWPfPiP17curandStateXORWOW:
.LFB2296:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9nullmodelPfPiP17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2296:
.size _Z50__device_stub__Z9nullmodelPfPiP17curandStateXORWOWPfPiP17curandStateXORWOW, .-_Z50__device_stub__Z9nullmodelPfPiP17curandStateXORWOWPfPiP17curandStateXORWOW
.globl _Z9nullmodelPfPiP17curandStateXORWOW
.type _Z9nullmodelPfPiP17curandStateXORWOW, @function
_Z9nullmodelPfPiP17curandStateXORWOW:
.LFB2297:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z9nullmodelPfPiP17curandStateXORWOWPfPiP17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2297:
.size _Z9nullmodelPfPiP17curandStateXORWOW, .-_Z9nullmodelPfPiP17curandStateXORWOW
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "1000 null network generated in %f s.\n"
.text
.globl main
.type main, @function
main:
.LFB2271:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $40000, %edi
call malloc@PLT
movq %rax, %r12
movl $40000, %edi
call malloc@PLT
movq %rax, %r13
movl $100, %ebp
jmp .L12
.L13:
addl $1, %ebx
cmpl %ebp, %ebx
je .L24
.L15:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movsd .LC1(%rip), %xmm1
comisd %xmm0, %xmm1
jbe .L13
call rand@PLT
movl %eax, %edx
movslq %ebx, %rax
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, (%r12,%rax,4)
jmp .L13
.L24:
addl $100, %ebp
cmpl $10100, %ebp
je .L16
.L12:
leal -100(%rbp), %ebx
jmp .L15
.L16:
leaq 16(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40000, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40000, %edx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rdi
movl $480000, %esi
call cudaMalloc@PLT
call clock@PLT
movq %rax, %rbp
movl $1000, %ebx
jmp .L18
.L17:
movl $2, %ecx
movl $40000, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
subl $1, %ebx
je .L25
.L18:
movl $100, 44(%rsp)
movl $1, 48(%rsp)
movl $100, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L17
movq 8(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z50__device_stub__Z9nullmodelPfPiP17curandStateXORWOWPfPiP17curandStateXORWOW
jmp .L17
.L25:
call clock@PLT
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC4:
.string "_Z9nullmodelPfPiP17curandStateXORWOW"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "precalc_xorwow_matrix"
.LC6:
.string "precalc_xorwow_offset_matrix"
.LC7:
.string "mrg32k3aM1"
.LC8:
.string "mrg32k3aM2"
.LC9:
.string "mrg32k3aM1SubSeq"
.LC10:
.string "mrg32k3aM2SubSeq"
.LC11:
.string "mrg32k3aM1Seq"
.LC12:
.string "mrg32k3aM2Seq"
.LC13:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2299:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z9nullmodelPfPiP17curandStateXORWOW(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2299:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 858993459
.long 1071854387
.section .rodata.cst4
.align 4
.LC2:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Null model based on cell link strength
* ranged between 0 and 1
*
* CUDA version
*
* compile with nvcc nco.cu -o nco -lcuda
*/
#include <stdlib.h>
#include <stdio.h>
#include <cuda.h>
#include <math.h>
#include <time.h>
#include <curand_kernel.h>
__global__ void nullmodel(float *M, int *out, curandState *states)
{
unsigned int tid = threadIdx.x + blockIdx.x * blockDim.x;
curand_init(threadIdx.x, 0, 0, &states[tid]);
float tar = (float)curand_uniform(&states[tid]);
out[tid] = (tar < M[tid])? 1 : 0;
}
int main(int argc, char **argv)
{
srand ( time(NULL) );
clock_t start, stop;
// PRNG
curandState *devStates;
// Network shape
int nrow = 100;
int ncol = 100;
double connec = 0.6;
int net_size = nrow * ncol;
// Memory allocation on host
const size_t nbytes_ref= net_size * sizeof(float);
const size_t nbytes_out= net_size * sizeof(int);
float *h_ref = (float*)malloc(nbytes_ref);
int *h_out = (int*)malloc(nbytes_out);
// create a random network -------
for(int row = 0; row < nrow; ++row)
{
for(int col = 0; col < ncol; ++col)
{
if((double)(rand() / (float)RAND_MAX) < connec)
{
h_ref[col + row*nrow] = (float)(rand() / (float)RAND_MAX);
}
}
}
// rand() / (float)RAND_MAX;
// Memory allocation on device
float *d_ref;
int *d_out;
cudaMalloc((void**)&d_ref, nbytes_ref);
cudaMalloc((void**)&d_out, nbytes_out);
// Memory transfer from host to device
cudaMemcpy(d_ref, h_ref, nbytes_ref, cudaMemcpyHostToDevice);
cudaMemcpy(d_out, h_out, nbytes_out, cudaMemcpyHostToDevice);
cudaMalloc( (void **)&devStates, net_size * sizeof(curandState) );
// Record initial time and start doing the null model
start = clock();
for(int repl = 0; repl < 1000; ++repl)
{
nullmodel<<<ncol,nrow>>>(d_ref, d_out, devStates);
// Memory transfer from the device to the host
cudaMemcpy(h_out, d_out, nbytes_ref, cudaMemcpyDeviceToHost);
}
stop = clock();
printf("1000 null network generated in %f s.\n", (stop-start)/(float)CLOCKS_PER_SEC);
// Free memory space
free(h_ref);
free(h_out);
cudaFree(d_ref);
cudaFree(d_out);
return EXIT_SUCCESS;
} | /*
* Null model based on cell link strength
* ranged between 0 and 1
*
* CUDA version
*
* compile with nvcc nco.cu -o nco -lcuda
*/
#include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <math.h>
#include <time.h>
#include <hiprand/hiprand_kernel.h>
__global__ void nullmodel(float *M, int *out, hiprandState *states)
{
unsigned int tid = threadIdx.x + blockIdx.x * blockDim.x;
hiprand_init(threadIdx.x, 0, 0, &states[tid]);
float tar = (float)hiprand_uniform(&states[tid]);
out[tid] = (tar < M[tid])? 1 : 0;
}
int main(int argc, char **argv)
{
srand ( time(NULL) );
clock_t start, stop;
// PRNG
hiprandState *devStates;
// Network shape
int nrow = 100;
int ncol = 100;
double connec = 0.6;
int net_size = nrow * ncol;
// Memory allocation on host
const size_t nbytes_ref= net_size * sizeof(float);
const size_t nbytes_out= net_size * sizeof(int);
float *h_ref = (float*)malloc(nbytes_ref);
int *h_out = (int*)malloc(nbytes_out);
// create a random network -------
for(int row = 0; row < nrow; ++row)
{
for(int col = 0; col < ncol; ++col)
{
if((double)(rand() / (float)RAND_MAX) < connec)
{
h_ref[col + row*nrow] = (float)(rand() / (float)RAND_MAX);
}
}
}
// rand() / (float)RAND_MAX;
// Memory allocation on device
float *d_ref;
int *d_out;
hipMalloc((void**)&d_ref, nbytes_ref);
hipMalloc((void**)&d_out, nbytes_out);
// Memory transfer from host to device
hipMemcpy(d_ref, h_ref, nbytes_ref, hipMemcpyHostToDevice);
hipMemcpy(d_out, h_out, nbytes_out, hipMemcpyHostToDevice);
hipMalloc( (void **)&devStates, net_size * sizeof(hiprandState) );
// Record initial time and start doing the null model
start = clock();
for(int repl = 0; repl < 1000; ++repl)
{
nullmodel<<<ncol,nrow>>>(d_ref, d_out, devStates);
// Memory transfer from the device to the host
hipMemcpy(h_out, d_out, nbytes_ref, hipMemcpyDeviceToHost);
}
stop = clock();
printf("1000 null network generated in %f s.\n", (stop-start)/(float)CLOCKS_PER_SEC);
// Free memory space
free(h_ref);
free(h_out);
hipFree(d_ref);
hipFree(d_out);
return EXIT_SUCCESS;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* Null model based on cell link strength
* ranged between 0 and 1
*
* CUDA version
*
* compile with nvcc nco.cu -o nco -lcuda
*/
#include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <math.h>
#include <time.h>
#include <hiprand/hiprand_kernel.h>
__global__ void nullmodel(float *M, int *out, hiprandState *states)
{
unsigned int tid = threadIdx.x + blockIdx.x * blockDim.x;
hiprand_init(threadIdx.x, 0, 0, &states[tid]);
float tar = (float)hiprand_uniform(&states[tid]);
out[tid] = (tar < M[tid])? 1 : 0;
}
int main(int argc, char **argv)
{
srand ( time(NULL) );
clock_t start, stop;
// PRNG
hiprandState *devStates;
// Network shape
int nrow = 100;
int ncol = 100;
double connec = 0.6;
int net_size = nrow * ncol;
// Memory allocation on host
const size_t nbytes_ref= net_size * sizeof(float);
const size_t nbytes_out= net_size * sizeof(int);
float *h_ref = (float*)malloc(nbytes_ref);
int *h_out = (int*)malloc(nbytes_out);
// create a random network -------
for(int row = 0; row < nrow; ++row)
{
for(int col = 0; col < ncol; ++col)
{
if((double)(rand() / (float)RAND_MAX) < connec)
{
h_ref[col + row*nrow] = (float)(rand() / (float)RAND_MAX);
}
}
}
// rand() / (float)RAND_MAX;
// Memory allocation on device
float *d_ref;
int *d_out;
hipMalloc((void**)&d_ref, nbytes_ref);
hipMalloc((void**)&d_out, nbytes_out);
// Memory transfer from host to device
hipMemcpy(d_ref, h_ref, nbytes_ref, hipMemcpyHostToDevice);
hipMemcpy(d_out, h_out, nbytes_out, hipMemcpyHostToDevice);
hipMalloc( (void **)&devStates, net_size * sizeof(hiprandState) );
// Record initial time and start doing the null model
start = clock();
for(int repl = 0; repl < 1000; ++repl)
{
nullmodel<<<ncol,nrow>>>(d_ref, d_out, devStates);
// Memory transfer from the device to the host
hipMemcpy(h_out, d_out, nbytes_ref, hipMemcpyDeviceToHost);
}
stop = clock();
printf("1000 null network generated in %f s.\n", (stop-start)/(float)CLOCKS_PER_SEC);
// Free memory space
free(h_ref);
free(h_out);
hipFree(d_ref);
hipFree(d_out);
return EXIT_SUCCESS;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9nullmodelPfPiP12hiprandState
.globl _Z9nullmodelPfPiP12hiprandState
.p2align 8
.type _Z9nullmodelPfPiP12hiprandState,@function
_Z9nullmodelPfPiP12hiprandState:
s_clause 0x2
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
v_xor_b32_e32 v2, 0x2c7f967f, v0
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 0x8f14727c
v_mov_b32_e32 v3, 0xa96f9d04
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v9, v2, 0x493c4aa1
v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v5, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v10, 0x583f19, v9
v_xor_b32_e32 v8, 0x159a55e5, v9
v_add_nc_u32_e32 v17, 0x75bcd15, v9
v_add_nc_u32_e32 v18, 0x8ac25218, v9
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[6:7], null, s15, s6, v[0:1]
v_dual_mov_b32 v7, 0 :: v_dual_add_nc_u32 v0, 0x8ac7d9dd, v9
v_mov_b32_e32 v9, v10
v_lshlrev_b64 v[11:12], 2, v[6:7]
v_mad_u64_u32 v[13:14], null, v6, 48, s[4:5]
v_mov_b32_e32 v7, v8
s_clause 0x5
global_store_b32 v[13:14], v18, off
global_store_b32 v[13:14], v17, off offset:24
global_store_b64 v[13:14], v[7:8], off offset:24
global_store_b96 v[13:14], v[3:5], off offset:28
global_store_b64 v[13:14], v[9:10], off offset:36
global_store_b96 v[13:14], v[0:2], off
v_add_co_u32 v15, vcc_lo, s0, v11
v_add_co_ci_u32_e32 v16, vcc_lo, s1, v12, vcc_lo
v_lshrrev_b32_e32 v2, 2, v17
v_lshlrev_b32_e32 v3, 4, v10
global_load_b32 v1, v[15:16], off
v_xor_b32_e32 v2, v2, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v4, 1, v2
v_xor_b32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor3_b32 v2, v3, v10, v2
v_add_nc_u32_e32 v0, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v0, v0
v_fmaak_f32 v0, 0x2f800000, v0, 0x2f800000
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_f32_e32 vcc_lo, v0, v1
v_cndmask_b32_e64 v3, 0, 1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v11
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v12, vcc_lo
global_store_b32 v[13:14], v2, off offset:40
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9nullmodelPfPiP12hiprandState
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 19
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9nullmodelPfPiP12hiprandState, .Lfunc_end0-_Z9nullmodelPfPiP12hiprandState
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9nullmodelPfPiP12hiprandState
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9nullmodelPfPiP12hiprandState.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 19
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* Null model based on cell link strength
* ranged between 0 and 1
*
* CUDA version
*
* compile with nvcc nco.cu -o nco -lcuda
*/
#include <stdlib.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <math.h>
#include <time.h>
#include <hiprand/hiprand_kernel.h>
__global__ void nullmodel(float *M, int *out, hiprandState *states)
{
unsigned int tid = threadIdx.x + blockIdx.x * blockDim.x;
hiprand_init(threadIdx.x, 0, 0, &states[tid]);
float tar = (float)hiprand_uniform(&states[tid]);
out[tid] = (tar < M[tid])? 1 : 0;
}
int main(int argc, char **argv)
{
srand ( time(NULL) );
clock_t start, stop;
// PRNG
hiprandState *devStates;
// Network shape
int nrow = 100;
int ncol = 100;
double connec = 0.6;
int net_size = nrow * ncol;
// Memory allocation on host
const size_t nbytes_ref= net_size * sizeof(float);
const size_t nbytes_out= net_size * sizeof(int);
float *h_ref = (float*)malloc(nbytes_ref);
int *h_out = (int*)malloc(nbytes_out);
// create a random network -------
for(int row = 0; row < nrow; ++row)
{
for(int col = 0; col < ncol; ++col)
{
if((double)(rand() / (float)RAND_MAX) < connec)
{
h_ref[col + row*nrow] = (float)(rand() / (float)RAND_MAX);
}
}
}
// rand() / (float)RAND_MAX;
// Memory allocation on device
float *d_ref;
int *d_out;
hipMalloc((void**)&d_ref, nbytes_ref);
hipMalloc((void**)&d_out, nbytes_out);
// Memory transfer from host to device
hipMemcpy(d_ref, h_ref, nbytes_ref, hipMemcpyHostToDevice);
hipMemcpy(d_out, h_out, nbytes_out, hipMemcpyHostToDevice);
hipMalloc( (void **)&devStates, net_size * sizeof(hiprandState) );
// Record initial time and start doing the null model
start = clock();
for(int repl = 0; repl < 1000; ++repl)
{
nullmodel<<<ncol,nrow>>>(d_ref, d_out, devStates);
// Memory transfer from the device to the host
hipMemcpy(h_out, d_out, nbytes_ref, hipMemcpyDeviceToHost);
}
stop = clock();
printf("1000 null network generated in %f s.\n", (stop-start)/(float)CLOCKS_PER_SEC);
// Free memory space
free(h_ref);
free(h_out);
hipFree(d_ref);
hipFree(d_out);
return EXIT_SUCCESS;
} | .text
.file "nco.hip"
.globl _Z24__device_stub__nullmodelPfPiP12hiprandState # -- Begin function _Z24__device_stub__nullmodelPfPiP12hiprandState
.p2align 4, 0x90
.type _Z24__device_stub__nullmodelPfPiP12hiprandState,@function
_Z24__device_stub__nullmodelPfPiP12hiprandState: # @_Z24__device_stub__nullmodelPfPiP12hiprandState
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9nullmodelPfPiP12hiprandState, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__nullmodelPfPiP12hiprandState, .Lfunc_end0-_Z24__device_stub__nullmodelPfPiP12hiprandState
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI1_2:
.long 0x49742400 # float 1.0E+6
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x3fe3333333333333 # double 0.59999999999999998
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %r13
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %r14
movq %r13, %r15
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_1 Depth=1
incq %rbx
addq $400, %r15 # imm = 0x190
cmpq $100, %rbx
je .LBB1_6
.LBB1_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %r12d, %r12d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_4: # in Loop: Header=BB1_2 Depth=2
incq %r12
cmpq $100, %r12
je .LBB1_5
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
ucomisd %xmm0, %xmm1
jbe .LBB1_4
# %bb.3: # in Loop: Header=BB1_2 Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, (%r15,%r12,4)
jmp .LBB1_4
.LBB1_6:
movabsq $4294967396, %r15 # imm = 0x100000064
leaq 8(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
movq %rsp, %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
movq 8(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movq %r13, 24(%rsp) # 8-byte Spill
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 32(%rsp), %rdi
movl $480000, %esi # imm = 0x75300
callq hipMalloc
movl $1000, %ebp # imm = 0x3E8
callq clock
movq %rax, 16(%rsp) # 8-byte Spill
leaq 48(%rsp), %rbx
leaq 40(%rsp), %r12
leaq 112(%rsp), %r13
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_9: # in Loop: Header=BB1_7 Depth=1
movq (%rsp), %rsi
movl $40000, %edx # imm = 0x9C40
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
decl %ebp
je .LBB1_10
.LBB1_7: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_9
# %bb.8: # in Loop: Header=BB1_7 Depth=1
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
movq %rbx, %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z9nullmodelPfPiP12hiprandState, %edi
movq %r13, %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_9
.LBB1_10:
callq clock
subq 16(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
divss .LCPI1_2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rdi # 8-byte Reload
callq free
movq %r14, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9nullmodelPfPiP12hiprandState, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9nullmodelPfPiP12hiprandState,@object # @_Z9nullmodelPfPiP12hiprandState
.section .rodata,"a",@progbits
.globl _Z9nullmodelPfPiP12hiprandState
.p2align 3, 0x0
_Z9nullmodelPfPiP12hiprandState:
.quad _Z24__device_stub__nullmodelPfPiP12hiprandState
.size _Z9nullmodelPfPiP12hiprandState, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "1000 null network generated in %f s.\n"
.size .L.str, 38
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9nullmodelPfPiP12hiprandState"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__nullmodelPfPiP12hiprandState
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9nullmodelPfPiP12hiprandState
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9nullmodelPfPiP17curandStateXORWOW
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fe200078e00ff */
/*0030*/ HFMA2.MMA R12, -RZ, RZ, -38016, 0.02740478515625 ; /* 0xf8a42704ff0c7435 */
/* 0x000fe200000001ff */
/*0040*/ IMAD.MOV.U32 R13, RZ, RZ, -0x23270784 ; /* 0xdcd8f87cff0d7424 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0070*/ LOP3.LUT R0, R8, 0xaad26b49, RZ, 0x3c, !PT ; /* 0xaad26b4908007812 */
/* 0x001fe200078e3cff */
/*0080*/ IMAD R8, R5, c[0x0][0x0], R8 ; /* 0x0000000005087a24 */
/* 0x002fc800078e0208 */
/*0090*/ IMAD R0, R0, 0x4182bed5, RZ ; /* 0x4182bed500007824 */
/* 0x000fe400078e02ff */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x30 ; /* 0x00000030ff057424 */
/* 0x000fc600078e00ff */
/*00b0*/ IADD3 R2, R0.reuse, 0x75bcd15, RZ ; /* 0x075bcd1500027810 */
/* 0x040fe40007ffe0ff */
/*00c0*/ LOP3.LUT R11, R0.reuse, 0x159a55e5, RZ, 0x3c, !PT ; /* 0x159a55e5000b7812 */
/* 0x040fe400078e3cff */
/*00d0*/ SHF.R.U32.HI R3, RZ, 0x2, R2 ; /* 0x00000002ff037819 */
/* 0x000fe40000011602 */
/*00e0*/ IADD3 R10, R0.reuse, -0x26039c23, RZ ; /* 0xd9fc63dd000a7810 */
/* 0x040fe40007ffe0ff */
/*00f0*/ LOP3.LUT R3, R3, R2, RZ, 0x3c, !PT ; /* 0x0000000203037212 */
/* 0x000fe400078e3cff */
/*0100*/ IADD3 R2, R0, 0x583f19, RZ ; /* 0x00583f1900027810 */
/* 0x000fc60007ffe0ff */
/*0110*/ IMAD.SHL.U32 R4, R3, 0x2, RZ ; /* 0x0000000203047824 */
/* 0x000fca00078e00ff */
/*0120*/ LOP3.LUT R6, R2, R4, R3, 0x96, !PT ; /* 0x0000000402067212 */
/* 0x000fe200078e9603 */
/*0130*/ IMAD.WIDE.U32 R4, R8, R5, c[0x0][0x170] ; /* 0x00005c0008047625 */
/* 0x000fe200078e0005 */
/*0140*/ SHF.L.U32 R3, R2, 0x4, RZ ; /* 0x0000000402037819 */
/* 0x000fc800000006ff */
/*0150*/ LOP3.LUT R3, R6, R3, RZ, 0x3c, !PT ; /* 0x0000000306037212 */
/* 0x000fe200078e3cff */
/*0160*/ IMAD.WIDE.U32 R6, R8, R15, c[0x0][0x160] ; /* 0x0000580008067625 */
/* 0x000fe200078e000f */
/*0170*/ STG.E.64 [R4.64+0x8], R12 ; /* 0x0000080c04007986 */
/* 0x000fe8000c101b04 */
/*0180*/ STG.E.64 [R4.64], R10 ; /* 0x0000000a04007986 */
/* 0x0001e8000c101b04 */
/*0190*/ STG.E.64 [R4.64+0x18], RZ ; /* 0x000018ff04007986 */
/* 0x000fe8000c101b04 */
/*01a0*/ STG.E [R4.64+0x20], RZ ; /* 0x000020ff04007986 */
/* 0x000fe8000c101904 */
/*01b0*/ STG.E.64 [R4.64+0x28], RZ ; /* 0x000028ff04007986 */
/* 0x000fe8000c101b04 */
/*01c0*/ STG.E.64 [R4.64+0x10], R2 ; /* 0x0000100204007986 */
/* 0x000fe8000c101b04 */
/*01d0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*01e0*/ IMAD.IADD R0, R3, 0x1, R10 ; /* 0x0000000103007824 */
/* 0x000fe200078e020a */
/*01f0*/ MOV R9, 0x2f800000 ; /* 0x2f80000000097802 */
/* 0x000fca0000000f00 */
/*0200*/ I2F.U32 R0, R0 ; /* 0x0000000000007306 */
/* 0x000e640000201000 */
/*0210*/ FFMA R9, R0, R9, 1.1641532182693481445e-10 ; /* 0x2f00000000097423 */
/* 0x002fca0000000009 */
/*0220*/ FSETP.GEU.AND P0, PT, R9, R6, PT ; /* 0x000000060900720b */
/* 0x004fe20003f0e000 */
/*0230*/ IMAD.WIDE.U32 R8, R8, R15, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fc600078e000f */
/*0240*/ SEL R11, RZ, 0x1, P0 ; /* 0x00000001ff0b7807 */
/* 0x001fca0000000000 */
/*0250*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x000fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9nullmodelPfPiP12hiprandState
.globl _Z9nullmodelPfPiP12hiprandState
.p2align 8
.type _Z9nullmodelPfPiP12hiprandState,@function
_Z9nullmodelPfPiP12hiprandState:
s_clause 0x2
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
v_xor_b32_e32 v2, 0x2c7f967f, v0
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 0x8f14727c
v_mov_b32_e32 v3, 0xa96f9d04
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v9, v2, 0x493c4aa1
v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v5, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v10, 0x583f19, v9
v_xor_b32_e32 v8, 0x159a55e5, v9
v_add_nc_u32_e32 v17, 0x75bcd15, v9
v_add_nc_u32_e32 v18, 0x8ac25218, v9
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[6:7], null, s15, s6, v[0:1]
v_dual_mov_b32 v7, 0 :: v_dual_add_nc_u32 v0, 0x8ac7d9dd, v9
v_mov_b32_e32 v9, v10
v_lshlrev_b64 v[11:12], 2, v[6:7]
v_mad_u64_u32 v[13:14], null, v6, 48, s[4:5]
v_mov_b32_e32 v7, v8
s_clause 0x5
global_store_b32 v[13:14], v18, off
global_store_b32 v[13:14], v17, off offset:24
global_store_b64 v[13:14], v[7:8], off offset:24
global_store_b96 v[13:14], v[3:5], off offset:28
global_store_b64 v[13:14], v[9:10], off offset:36
global_store_b96 v[13:14], v[0:2], off
v_add_co_u32 v15, vcc_lo, s0, v11
v_add_co_ci_u32_e32 v16, vcc_lo, s1, v12, vcc_lo
v_lshrrev_b32_e32 v2, 2, v17
v_lshlrev_b32_e32 v3, 4, v10
global_load_b32 v1, v[15:16], off
v_xor_b32_e32 v2, v2, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v4, 1, v2
v_xor_b32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor3_b32 v2, v3, v10, v2
v_add_nc_u32_e32 v0, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v0, v0
v_fmaak_f32 v0, 0x2f800000, v0, 0x2f800000
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_f32_e32 vcc_lo, v0, v1
v_cndmask_b32_e64 v3, 0, 1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v11
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v12, vcc_lo
global_store_b32 v[13:14], v2, off offset:40
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9nullmodelPfPiP12hiprandState
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 19
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9nullmodelPfPiP12hiprandState, .Lfunc_end0-_Z9nullmodelPfPiP12hiprandState
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9nullmodelPfPiP12hiprandState
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9nullmodelPfPiP12hiprandState.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 19
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016bba0_00000000-6_nco.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2274:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2274:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z9nullmodelPfPiP17curandStateXORWOWPfPiP17curandStateXORWOW
.type _Z50__device_stub__Z9nullmodelPfPiP17curandStateXORWOWPfPiP17curandStateXORWOW, @function
_Z50__device_stub__Z9nullmodelPfPiP17curandStateXORWOWPfPiP17curandStateXORWOW:
.LFB2296:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9nullmodelPfPiP17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2296:
.size _Z50__device_stub__Z9nullmodelPfPiP17curandStateXORWOWPfPiP17curandStateXORWOW, .-_Z50__device_stub__Z9nullmodelPfPiP17curandStateXORWOWPfPiP17curandStateXORWOW
.globl _Z9nullmodelPfPiP17curandStateXORWOW
.type _Z9nullmodelPfPiP17curandStateXORWOW, @function
_Z9nullmodelPfPiP17curandStateXORWOW:
.LFB2297:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z9nullmodelPfPiP17curandStateXORWOWPfPiP17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2297:
.size _Z9nullmodelPfPiP17curandStateXORWOW, .-_Z9nullmodelPfPiP17curandStateXORWOW
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "1000 null network generated in %f s.\n"
.text
.globl main
.type main, @function
main:
.LFB2271:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $40000, %edi
call malloc@PLT
movq %rax, %r12
movl $40000, %edi
call malloc@PLT
movq %rax, %r13
movl $100, %ebp
jmp .L12
.L13:
addl $1, %ebx
cmpl %ebp, %ebx
je .L24
.L15:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movsd .LC1(%rip), %xmm1
comisd %xmm0, %xmm1
jbe .L13
call rand@PLT
movl %eax, %edx
movslq %ebx, %rax
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, (%r12,%rax,4)
jmp .L13
.L24:
addl $100, %ebp
cmpl $10100, %ebp
je .L16
.L12:
leal -100(%rbp), %ebx
jmp .L15
.L16:
leaq 16(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40000, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40000, %edx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rdi
movl $480000, %esi
call cudaMalloc@PLT
call clock@PLT
movq %rax, %rbp
movl $1000, %ebx
jmp .L18
.L17:
movl $2, %ecx
movl $40000, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
subl $1, %ebx
je .L25
.L18:
movl $100, 44(%rsp)
movl $1, 48(%rsp)
movl $100, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L17
movq 8(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z50__device_stub__Z9nullmodelPfPiP17curandStateXORWOWPfPiP17curandStateXORWOW
jmp .L17
.L25:
call clock@PLT
subq %rbp, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC4:
.string "_Z9nullmodelPfPiP17curandStateXORWOW"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "precalc_xorwow_matrix"
.LC6:
.string "precalc_xorwow_offset_matrix"
.LC7:
.string "mrg32k3aM1"
.LC8:
.string "mrg32k3aM2"
.LC9:
.string "mrg32k3aM1SubSeq"
.LC10:
.string "mrg32k3aM2SubSeq"
.LC11:
.string "mrg32k3aM1Seq"
.LC12:
.string "mrg32k3aM2Seq"
.LC13:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2299:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z9nullmodelPfPiP17curandStateXORWOW(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2299:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 858993459
.long 1071854387
.section .rodata.cst4
.align 4
.LC2:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "nco.hip"
.globl _Z24__device_stub__nullmodelPfPiP12hiprandState # -- Begin function _Z24__device_stub__nullmodelPfPiP12hiprandState
.p2align 4, 0x90
.type _Z24__device_stub__nullmodelPfPiP12hiprandState,@function
_Z24__device_stub__nullmodelPfPiP12hiprandState: # @_Z24__device_stub__nullmodelPfPiP12hiprandState
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9nullmodelPfPiP12hiprandState, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__nullmodelPfPiP12hiprandState, .Lfunc_end0-_Z24__device_stub__nullmodelPfPiP12hiprandState
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI1_2:
.long 0x49742400 # float 1.0E+6
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x3fe3333333333333 # double 0.59999999999999998
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %ebx, %ebx
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %r13
movl $40000, %edi # imm = 0x9C40
callq malloc
movq %rax, %r14
movq %r13, %r15
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_1 Depth=1
incq %rbx
addq $400, %r15 # imm = 0x190
cmpq $100, %rbx
je .LBB1_6
.LBB1_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %r12d, %r12d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_4: # in Loop: Header=BB1_2 Depth=2
incq %r12
cmpq $100, %r12
je .LBB1_5
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
ucomisd %xmm0, %xmm1
jbe .LBB1_4
# %bb.3: # in Loop: Header=BB1_2 Depth=2
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, (%r15,%r12,4)
jmp .LBB1_4
.LBB1_6:
movabsq $4294967396, %r15 # imm = 0x100000064
leaq 8(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
movq %rsp, %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
movq 8(%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movq %r13, 24(%rsp) # 8-byte Spill
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $40000, %edx # imm = 0x9C40
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 32(%rsp), %rdi
movl $480000, %esi # imm = 0x75300
callq hipMalloc
movl $1000, %ebp # imm = 0x3E8
callq clock
movq %rax, 16(%rsp) # 8-byte Spill
leaq 48(%rsp), %rbx
leaq 40(%rsp), %r12
leaq 112(%rsp), %r13
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_9: # in Loop: Header=BB1_7 Depth=1
movq (%rsp), %rsi
movl $40000, %edx # imm = 0x9C40
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
decl %ebp
je .LBB1_10
.LBB1_7: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_9
# %bb.8: # in Loop: Header=BB1_7 Depth=1
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
movq %rbx, %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z9nullmodelPfPiP12hiprandState, %edi
movq %r13, %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_9
.LBB1_10:
callq clock
subq 16(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
divss .LCPI1_2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rdi # 8-byte Reload
callq free
movq %r14, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9nullmodelPfPiP12hiprandState, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9nullmodelPfPiP12hiprandState,@object # @_Z9nullmodelPfPiP12hiprandState
.section .rodata,"a",@progbits
.globl _Z9nullmodelPfPiP12hiprandState
.p2align 3, 0x0
_Z9nullmodelPfPiP12hiprandState:
.quad _Z24__device_stub__nullmodelPfPiP12hiprandState
.size _Z9nullmodelPfPiP12hiprandState, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "1000 null network generated in %f s.\n"
.size .L.str, 38
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9nullmodelPfPiP12hiprandState"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__nullmodelPfPiP12hiprandState
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9nullmodelPfPiP12hiprandState
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <algorithm>
#define BLOCK_SIZE 256
__global__ void dot(int numElements, const float3* a, const float3* b, float* c)
{
int i = threadIdx.x + blockIdx.x*blockDim.x;
if (i < numElements)
{
c[i] = a[i].x*b[i].x + a[i].y*b[i].y + a[i].z*b[i].z;
}
}
int main()
{
int numElements = 10000;
float3* h_a = (float3*)calloc(numElements, sizeof(float3));
float3* h_b = (float3*)calloc(numElements, sizeof(float3));
float* h_c = (float*)calloc(numElements, sizeof(float));
srand(1214134);
for (int i = 0; i < numElements; i++)
{
h_a[i].x = float(rand())/float(RAND_MAX + 1.0);
h_a[i].y = float(rand())/float(RAND_MAX + 1.0);
h_a[i].z = float(rand())/float(RAND_MAX + 1.0);
h_b[i].x = float(rand())/float(RAND_MAX + 1.0);
h_b[i].y = float(rand())/float(RAND_MAX + 1.0);
h_b[i].z = float(rand())/float(RAND_MAX + 1.0);
}
float3* d_a;
float3* d_b;
float* d_c;
cudaMalloc((void**)&d_a, numElements*sizeof(float3));
cudaMalloc((void**)&d_b, numElements*sizeof(float3));
cudaMalloc((void**)&d_c, numElements*sizeof(float));
cudaMemcpy(d_a, h_a, numElements*sizeof(float3), cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, numElements*sizeof(float3), cudaMemcpyHostToDevice);
dot<<<numElements/BLOCK_SIZE + 1, BLOCK_SIZE>>>(numElements, d_a, d_b, d_c);
cudaMemcpy(h_c, d_c, numElements*sizeof(float), cudaMemcpyDeviceToHost);
for (int i = 0; i < std::min(10, numElements); i++)
{
printf("%f*%f + %f*%f + %f*%f = %f\n", h_a[i].x, h_b[i].x, h_a[i].y, h_b[i].y, h_a[i].z, h_b[i].z, h_c[i]);
}
printf("...\n");
free(h_a);
free(h_b);
free(h_c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | code for sm_80
Function : _Z3dotiPK6float3S1_Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 7.152557373046875e-07 ; /* 0x0000000cff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R6, R5, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R6, R5, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fe200078e0205 */
/*00a0*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040402097981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R8, [R4.64+0x4] ; /* 0x0000040404087981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ee8000c1e1900 */
/*00d0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ee8000c1e1900 */
/*00e0*/ LDG.E R10, [R2.64+0x8] ; /* 0x00000804020a7981 */
/* 0x000f28000c1e1900 */
/*00f0*/ LDG.E R11, [R4.64+0x8] ; /* 0x00000804040b7981 */
/* 0x000f22000c1e1900 */
/*0100*/ FMUL R8, R8, R9 ; /* 0x0000000908087220 */
/* 0x004fe20000400000 */
/*0110*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fc600000001ff */
/*0120*/ FFMA R0, R0, R7, R8 ; /* 0x0000000700007223 */
/* 0x008fce0000000008 */
/*0130*/ IMAD.WIDE R6, R6, R9, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fc800078e0209 */
/*0140*/ FFMA R11, R11, R10, R0 ; /* 0x0000000a0b0b7223 */
/* 0x010fca0000000000 */
/*0150*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <algorithm>
#define BLOCK_SIZE 256
__global__ void dot(int numElements, const float3* a, const float3* b, float* c)
{
int i = threadIdx.x + blockIdx.x*blockDim.x;
if (i < numElements)
{
c[i] = a[i].x*b[i].x + a[i].y*b[i].y + a[i].z*b[i].z;
}
}
int main()
{
int numElements = 10000;
float3* h_a = (float3*)calloc(numElements, sizeof(float3));
float3* h_b = (float3*)calloc(numElements, sizeof(float3));
float* h_c = (float*)calloc(numElements, sizeof(float));
srand(1214134);
for (int i = 0; i < numElements; i++)
{
h_a[i].x = float(rand())/float(RAND_MAX + 1.0);
h_a[i].y = float(rand())/float(RAND_MAX + 1.0);
h_a[i].z = float(rand())/float(RAND_MAX + 1.0);
h_b[i].x = float(rand())/float(RAND_MAX + 1.0);
h_b[i].y = float(rand())/float(RAND_MAX + 1.0);
h_b[i].z = float(rand())/float(RAND_MAX + 1.0);
}
float3* d_a;
float3* d_b;
float* d_c;
cudaMalloc((void**)&d_a, numElements*sizeof(float3));
cudaMalloc((void**)&d_b, numElements*sizeof(float3));
cudaMalloc((void**)&d_c, numElements*sizeof(float));
cudaMemcpy(d_a, h_a, numElements*sizeof(float3), cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, numElements*sizeof(float3), cudaMemcpyHostToDevice);
dot<<<numElements/BLOCK_SIZE + 1, BLOCK_SIZE>>>(numElements, d_a, d_b, d_c);
cudaMemcpy(h_c, d_c, numElements*sizeof(float), cudaMemcpyDeviceToHost);
for (int i = 0; i < std::min(10, numElements); i++)
{
printf("%f*%f + %f*%f + %f*%f = %f\n", h_a[i].x, h_b[i].x, h_a[i].y, h_b[i].y, h_a[i].z, h_b[i].z, h_c[i]);
}
printf("...\n");
free(h_a);
free(h_b);
free(h_c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | .file "tmpxft_0005847d_00000000-6_vector_dot_product_gpu_ref.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2341:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2341:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z3dotiPK6float3S1_PfiPK6float3S1_Pf
.type _Z35__device_stub__Z3dotiPK6float3S1_PfiPK6float3S1_Pf, @function
_Z35__device_stub__Z3dotiPK6float3S1_PfiPK6float3S1_Pf:
.LFB2363:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3dotiPK6float3S1_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2363:
.size _Z35__device_stub__Z3dotiPK6float3S1_PfiPK6float3S1_Pf, .-_Z35__device_stub__Z3dotiPK6float3S1_PfiPK6float3S1_Pf
.globl _Z3dotiPK6float3S1_Pf
.type _Z3dotiPK6float3S1_Pf, @function
_Z3dotiPK6float3S1_Pf:
.LFB2364:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z3dotiPK6float3S1_PfiPK6float3S1_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2364:
.size _Z3dotiPK6float3S1_Pf, .-_Z3dotiPK6float3S1_Pf
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%f*%f + %f*%f + %f*%f = %f\n"
.LC2:
.string "...\n"
.text
.globl main
.type main, @function
main:
.LFB2337:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $12, %esi
movl $10000, %edi
call calloc@PLT
movq %rax, %r15
movl $12, %esi
movl $10000, %edi
call calloc@PLT
movq %rax, %rbp
movq %rax, (%rsp)
movl $4, %esi
movl $10000, %edi
call calloc@PLT
movq %rax, 8(%rsp)
movl $1214134, %edi
call srand@PLT
movq %r15, %r14
movq %rbp, %r13
leaq 120000(%r15), %r12
movq %r15, %rbx
.L12:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, (%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 4(%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 8(%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 0(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 4(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 8(%rbp)
addq $12, %rbx
addq $12, %rbp
cmpq %r12, %rbx
jne .L12
leaq 24(%rsp), %rdi
movl $120000, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $120000, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $120000, %edx
movq %r15, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $120000, %edx
movq (%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $40, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $40000, %edx
movq 40(%rsp), %rsi
movq 8(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 40(%rbx), %r12
leaq .LC1(%rip), %rbp
.L14:
pxor %xmm0, %xmm0
cvtss2sd (%r14), %xmm0
pxor %xmm6, %xmm6
cvtss2sd (%rbx), %xmm6
pxor %xmm5, %xmm5
cvtss2sd 8(%r13), %xmm5
pxor %xmm4, %xmm4
cvtss2sd 8(%r14), %xmm4
pxor %xmm3, %xmm3
cvtss2sd 4(%r13), %xmm3
pxor %xmm2, %xmm2
cvtss2sd 4(%r14), %xmm2
pxor %xmm1, %xmm1
cvtss2sd 0(%r13), %xmm1
movq %rbp, %rsi
movl $2, %edi
movl $7, %eax
call __printf_chk@PLT
addq $4, %rbx
addq $12, %r13
addq $12, %r14
cmpq %r12, %rbx
jne .L14
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r15, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movl $10000, %edi
call _Z35__device_stub__Z3dotiPK6float3S1_PfiPK6float3S1_Pf
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2337:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z3dotiPK6float3S1_Pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2366:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z3dotiPK6float3S1_Pf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2366:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <algorithm>
#define BLOCK_SIZE 256
__global__ void dot(int numElements, const float3* a, const float3* b, float* c)
{
int i = threadIdx.x + blockIdx.x*blockDim.x;
if (i < numElements)
{
c[i] = a[i].x*b[i].x + a[i].y*b[i].y + a[i].z*b[i].z;
}
}
int main()
{
int numElements = 10000;
float3* h_a = (float3*)calloc(numElements, sizeof(float3));
float3* h_b = (float3*)calloc(numElements, sizeof(float3));
float* h_c = (float*)calloc(numElements, sizeof(float));
srand(1214134);
for (int i = 0; i < numElements; i++)
{
h_a[i].x = float(rand())/float(RAND_MAX + 1.0);
h_a[i].y = float(rand())/float(RAND_MAX + 1.0);
h_a[i].z = float(rand())/float(RAND_MAX + 1.0);
h_b[i].x = float(rand())/float(RAND_MAX + 1.0);
h_b[i].y = float(rand())/float(RAND_MAX + 1.0);
h_b[i].z = float(rand())/float(RAND_MAX + 1.0);
}
float3* d_a;
float3* d_b;
float* d_c;
cudaMalloc((void**)&d_a, numElements*sizeof(float3));
cudaMalloc((void**)&d_b, numElements*sizeof(float3));
cudaMalloc((void**)&d_c, numElements*sizeof(float));
cudaMemcpy(d_a, h_a, numElements*sizeof(float3), cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, numElements*sizeof(float3), cudaMemcpyHostToDevice);
dot<<<numElements/BLOCK_SIZE + 1, BLOCK_SIZE>>>(numElements, d_a, d_b, d_c);
cudaMemcpy(h_c, d_c, numElements*sizeof(float), cudaMemcpyDeviceToHost);
for (int i = 0; i < std::min(10, numElements); i++)
{
printf("%f*%f + %f*%f + %f*%f = %f\n", h_a[i].x, h_b[i].x, h_a[i].y, h_b[i].y, h_a[i].z, h_b[i].z, h_c[i]);
}
printf("...\n");
free(h_a);
free(h_b);
free(h_c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <algorithm>
#define BLOCK_SIZE 256
__global__ void dot(int numElements, const float3* a, const float3* b, float* c)
{
int i = threadIdx.x + blockIdx.x*blockDim.x;
if (i < numElements)
{
c[i] = a[i].x*b[i].x + a[i].y*b[i].y + a[i].z*b[i].z;
}
}
int main()
{
int numElements = 10000;
float3* h_a = (float3*)calloc(numElements, sizeof(float3));
float3* h_b = (float3*)calloc(numElements, sizeof(float3));
float* h_c = (float*)calloc(numElements, sizeof(float));
srand(1214134);
for (int i = 0; i < numElements; i++)
{
h_a[i].x = float(rand())/float(RAND_MAX + 1.0);
h_a[i].y = float(rand())/float(RAND_MAX + 1.0);
h_a[i].z = float(rand())/float(RAND_MAX + 1.0);
h_b[i].x = float(rand())/float(RAND_MAX + 1.0);
h_b[i].y = float(rand())/float(RAND_MAX + 1.0);
h_b[i].z = float(rand())/float(RAND_MAX + 1.0);
}
float3* d_a;
float3* d_b;
float* d_c;
hipMalloc((void**)&d_a, numElements*sizeof(float3));
hipMalloc((void**)&d_b, numElements*sizeof(float3));
hipMalloc((void**)&d_c, numElements*sizeof(float));
hipMemcpy(d_a, h_a, numElements*sizeof(float3), hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, numElements*sizeof(float3), hipMemcpyHostToDevice);
dot<<<numElements/BLOCK_SIZE + 1, BLOCK_SIZE>>>(numElements, d_a, d_b, d_c);
hipMemcpy(h_c, d_c, numElements*sizeof(float), hipMemcpyDeviceToHost);
for (int i = 0; i < std::min(10, numElements); i++)
{
printf("%f*%f + %f*%f + %f*%f = %f\n", h_a[i].x, h_b[i].x, h_a[i].y, h_b[i].y, h_a[i].z, h_b[i].z, h_c[i]);
}
printf("...\n");
free(h_a);
free(h_b);
free(h_c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <algorithm>
#define BLOCK_SIZE 256
__global__ void dot(int numElements, const float3* a, const float3* b, float* c)
{
int i = threadIdx.x + blockIdx.x*blockDim.x;
if (i < numElements)
{
c[i] = a[i].x*b[i].x + a[i].y*b[i].y + a[i].z*b[i].z;
}
}
int main()
{
int numElements = 10000;
float3* h_a = (float3*)calloc(numElements, sizeof(float3));
float3* h_b = (float3*)calloc(numElements, sizeof(float3));
float* h_c = (float*)calloc(numElements, sizeof(float));
srand(1214134);
for (int i = 0; i < numElements; i++)
{
h_a[i].x = float(rand())/float(RAND_MAX + 1.0);
h_a[i].y = float(rand())/float(RAND_MAX + 1.0);
h_a[i].z = float(rand())/float(RAND_MAX + 1.0);
h_b[i].x = float(rand())/float(RAND_MAX + 1.0);
h_b[i].y = float(rand())/float(RAND_MAX + 1.0);
h_b[i].z = float(rand())/float(RAND_MAX + 1.0);
}
float3* d_a;
float3* d_b;
float* d_c;
hipMalloc((void**)&d_a, numElements*sizeof(float3));
hipMalloc((void**)&d_b, numElements*sizeof(float3));
hipMalloc((void**)&d_c, numElements*sizeof(float));
hipMemcpy(d_a, h_a, numElements*sizeof(float3), hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, numElements*sizeof(float3), hipMemcpyHostToDevice);
dot<<<numElements/BLOCK_SIZE + 1, BLOCK_SIZE>>>(numElements, d_a, d_b, d_c);
hipMemcpy(h_c, d_c, numElements*sizeof(float), hipMemcpyDeviceToHost);
for (int i = 0; i < std::min(10, numElements); i++)
{
printf("%f*%f + %f*%f + %f*%f = %f\n", h_a[i].x, h_b[i].x, h_a[i].y, h_b[i].y, h_a[i].z, h_b[i].z, h_c[i]);
}
printf("...\n");
free(h_a);
free(h_b);
free(h_c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf
.globl _Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf
.p2align 8
.type _Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf,@function
_Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[2:3], null, v1, 12, s[4:5]
v_mad_i64_i32 v[6:7], null, v1, 12, s[6:7]
global_load_b96 v[3:5], v[2:3], off
global_load_b96 v[6:8], v[6:7], off
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v4, v4, v7
v_fmac_f32_e32 v4, v3, v6
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v8
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf, .Lfunc_end0-_Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <algorithm>
#define BLOCK_SIZE 256
__global__ void dot(int numElements, const float3* a, const float3* b, float* c)
{
int i = threadIdx.x + blockIdx.x*blockDim.x;
if (i < numElements)
{
c[i] = a[i].x*b[i].x + a[i].y*b[i].y + a[i].z*b[i].z;
}
}
int main()
{
int numElements = 10000;
float3* h_a = (float3*)calloc(numElements, sizeof(float3));
float3* h_b = (float3*)calloc(numElements, sizeof(float3));
float* h_c = (float*)calloc(numElements, sizeof(float));
srand(1214134);
for (int i = 0; i < numElements; i++)
{
h_a[i].x = float(rand())/float(RAND_MAX + 1.0);
h_a[i].y = float(rand())/float(RAND_MAX + 1.0);
h_a[i].z = float(rand())/float(RAND_MAX + 1.0);
h_b[i].x = float(rand())/float(RAND_MAX + 1.0);
h_b[i].y = float(rand())/float(RAND_MAX + 1.0);
h_b[i].z = float(rand())/float(RAND_MAX + 1.0);
}
float3* d_a;
float3* d_b;
float* d_c;
hipMalloc((void**)&d_a, numElements*sizeof(float3));
hipMalloc((void**)&d_b, numElements*sizeof(float3));
hipMalloc((void**)&d_c, numElements*sizeof(float));
hipMemcpy(d_a, h_a, numElements*sizeof(float3), hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, numElements*sizeof(float3), hipMemcpyHostToDevice);
dot<<<numElements/BLOCK_SIZE + 1, BLOCK_SIZE>>>(numElements, d_a, d_b, d_c);
hipMemcpy(h_c, d_c, numElements*sizeof(float), hipMemcpyDeviceToHost);
for (int i = 0; i < std::min(10, numElements); i++)
{
printf("%f*%f + %f*%f + %f*%f = %f\n", h_a[i].x, h_b[i].x, h_a[i].y, h_b[i].y, h_a[i].z, h_b[i].z, h_c[i]);
}
printf("...\n");
free(h_a);
free(h_b);
free(h_c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.file "vector_dot_product_gpu_ref.hip"
.globl _Z18__device_stub__dotiPK15HIP_vector_typeIfLj3EES2_Pf # -- Begin function _Z18__device_stub__dotiPK15HIP_vector_typeIfLj3EES2_Pf
.p2align 4, 0x90
.type _Z18__device_stub__dotiPK15HIP_vector_typeIfLj3EES2_Pf,@function
_Z18__device_stub__dotiPK15HIP_vector_typeIfLj3EES2_Pf: # @_Z18__device_stub__dotiPK15HIP_vector_typeIfLj3EES2_Pf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__dotiPK15HIP_vector_typeIfLj3EES2_Pf, .Lfunc_end0-_Z18__device_stub__dotiPK15HIP_vector_typeIfLj3EES2_Pf
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $10000, %edi # imm = 0x2710
movl $12, %esi
callq calloc
movq %rax, %rbx
movl $10000, %edi # imm = 0x2710
movl $12, %esi
callq calloc
movq %rax, %r14
movl $10000, %edi # imm = 0x2710
movl $4, %esi
callq calloc
movq %rax, %r15
movl $1214134, %edi # imm = 0x1286B6
callq srand
movl $8, %r12d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, -8(%rbx,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, -4(%rbx,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, (%rbx,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, -8(%r14,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, -4(%r14,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, (%r14,%r12)
addq $12, %r12
cmpq $120008, %r12 # imm = 0x1D4C8
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $120000, %esi # imm = 0x1D4C0
callq hipMalloc
leaq 16(%rsp), %rdi
movl $120000, %esi # imm = 0x1D4C0
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
movq 24(%rsp), %rdi
movl $120000, %edx # imm = 0x1D4C0
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $120000, %edx # imm = 0x1D4C0
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967336, %rdi # imm = 0x100000028
leaq 216(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl $10000, 36(%rsp) # imm = 0x2710
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 104(%rsp), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $40000, %edx # imm = 0x9C40
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $2, %r12d
movq %r15, %r13
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss -8(%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss -4(%rbx,%r12,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss -8(%r14,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss -4(%r14,%r12,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
cvtss2sd %xmm2, %xmm2
cvtss2sd %xmm3, %xmm3
movss (%rbx,%r12,4), %xmm4 # xmm4 = mem[0],zero,zero,zero
cvtss2sd %xmm4, %xmm4
movss (%r14,%r12,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
cvtss2sd %xmm5, %xmm5
movss (%r13), %xmm6 # xmm6 = mem[0],zero,zero,zero
cvtss2sd %xmm6, %xmm6
movl $.L.str, %edi
movb $7, %al
callq printf
addq $4, %r13
addq $3, %r12
cmpq $32, %r12
jne .LBB1_5
# %bb.6:
movl $.Lstr, %edi
callq puts@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf,@object # @_Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf
.section .rodata,"a",@progbits
.globl _Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf
.p2align 3, 0x0
_Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf:
.quad _Z18__device_stub__dotiPK15HIP_vector_typeIfLj3EES2_Pf
.size _Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f*%f + %f*%f + %f*%f = %f\n"
.size .L.str, 28
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "..."
.size .Lstr, 4
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__dotiPK15HIP_vector_typeIfLj3EES2_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3dotiPK6float3S1_Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 7.152557373046875e-07 ; /* 0x0000000cff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R6, R5, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R6, R5, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fe200078e0205 */
/*00a0*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040402097981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R8, [R4.64+0x4] ; /* 0x0000040404087981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ee8000c1e1900 */
/*00d0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ee8000c1e1900 */
/*00e0*/ LDG.E R10, [R2.64+0x8] ; /* 0x00000804020a7981 */
/* 0x000f28000c1e1900 */
/*00f0*/ LDG.E R11, [R4.64+0x8] ; /* 0x00000804040b7981 */
/* 0x000f22000c1e1900 */
/*0100*/ FMUL R8, R8, R9 ; /* 0x0000000908087220 */
/* 0x004fe20000400000 */
/*0110*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fc600000001ff */
/*0120*/ FFMA R0, R0, R7, R8 ; /* 0x0000000700007223 */
/* 0x008fce0000000008 */
/*0130*/ IMAD.WIDE R6, R6, R9, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fc800078e0209 */
/*0140*/ FFMA R11, R11, R10, R0 ; /* 0x0000000a0b0b7223 */
/* 0x010fca0000000000 */
/*0150*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf
.globl _Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf
.p2align 8
.type _Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf,@function
_Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[2:3], null, v1, 12, s[4:5]
v_mad_i64_i32 v[6:7], null, v1, 12, s[6:7]
global_load_b96 v[3:5], v[2:3], off
global_load_b96 v[6:8], v[6:7], off
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v4, v4, v7
v_fmac_f32_e32 v4, v3, v6
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v8
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf, .Lfunc_end0-_Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005847d_00000000-6_vector_dot_product_gpu_ref.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2341:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2341:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z3dotiPK6float3S1_PfiPK6float3S1_Pf
.type _Z35__device_stub__Z3dotiPK6float3S1_PfiPK6float3S1_Pf, @function
_Z35__device_stub__Z3dotiPK6float3S1_PfiPK6float3S1_Pf:
.LFB2363:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3dotiPK6float3S1_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2363:
.size _Z35__device_stub__Z3dotiPK6float3S1_PfiPK6float3S1_Pf, .-_Z35__device_stub__Z3dotiPK6float3S1_PfiPK6float3S1_Pf
.globl _Z3dotiPK6float3S1_Pf
.type _Z3dotiPK6float3S1_Pf, @function
_Z3dotiPK6float3S1_Pf:
.LFB2364:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z3dotiPK6float3S1_PfiPK6float3S1_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2364:
.size _Z3dotiPK6float3S1_Pf, .-_Z3dotiPK6float3S1_Pf
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%f*%f + %f*%f + %f*%f = %f\n"
.LC2:
.string "...\n"
.text
.globl main
.type main, @function
main:
.LFB2337:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $12, %esi
movl $10000, %edi
call calloc@PLT
movq %rax, %r15
movl $12, %esi
movl $10000, %edi
call calloc@PLT
movq %rax, %rbp
movq %rax, (%rsp)
movl $4, %esi
movl $10000, %edi
call calloc@PLT
movq %rax, 8(%rsp)
movl $1214134, %edi
call srand@PLT
movq %r15, %r14
movq %rbp, %r13
leaq 120000(%r15), %r12
movq %r15, %rbx
.L12:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, (%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 4(%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 8(%rbx)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 0(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 4(%rbp)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC0(%rip), %xmm0
movss %xmm0, 8(%rbp)
addq $12, %rbx
addq $12, %rbp
cmpq %r12, %rbx
jne .L12
leaq 24(%rsp), %rdi
movl $120000, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $120000, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $120000, %edx
movq %r15, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $120000, %edx
movq (%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $40, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $40000, %edx
movq 40(%rsp), %rsi
movq 8(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 40(%rbx), %r12
leaq .LC1(%rip), %rbp
.L14:
pxor %xmm0, %xmm0
cvtss2sd (%r14), %xmm0
pxor %xmm6, %xmm6
cvtss2sd (%rbx), %xmm6
pxor %xmm5, %xmm5
cvtss2sd 8(%r13), %xmm5
pxor %xmm4, %xmm4
cvtss2sd 8(%r14), %xmm4
pxor %xmm3, %xmm3
cvtss2sd 4(%r13), %xmm3
pxor %xmm2, %xmm2
cvtss2sd 4(%r14), %xmm2
pxor %xmm1, %xmm1
cvtss2sd 0(%r13), %xmm1
movq %rbp, %rsi
movl $2, %edi
movl $7, %eax
call __printf_chk@PLT
addq $4, %rbx
addq $12, %r13
addq $12, %r14
cmpq %r12, %rbx
jne .L14
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r15, %rdi
call free@PLT
movq (%rsp), %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movl $10000, %edi
call _Z35__device_stub__Z3dotiPK6float3S1_PfiPK6float3S1_Pf
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2337:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z3dotiPK6float3S1_Pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2366:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z3dotiPK6float3S1_Pf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2366:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 805306368
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vector_dot_product_gpu_ref.hip"
.globl _Z18__device_stub__dotiPK15HIP_vector_typeIfLj3EES2_Pf # -- Begin function _Z18__device_stub__dotiPK15HIP_vector_typeIfLj3EES2_Pf
.p2align 4, 0x90
.type _Z18__device_stub__dotiPK15HIP_vector_typeIfLj3EES2_Pf,@function
_Z18__device_stub__dotiPK15HIP_vector_typeIfLj3EES2_Pf: # @_Z18__device_stub__dotiPK15HIP_vector_typeIfLj3EES2_Pf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__dotiPK15HIP_vector_typeIfLj3EES2_Pf, .Lfunc_end0-_Z18__device_stub__dotiPK15HIP_vector_typeIfLj3EES2_Pf
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $10000, %edi # imm = 0x2710
movl $12, %esi
callq calloc
movq %rax, %rbx
movl $10000, %edi # imm = 0x2710
movl $12, %esi
callq calloc
movq %rax, %r14
movl $10000, %edi # imm = 0x2710
movl $4, %esi
callq calloc
movq %rax, %r15
movl $1214134, %edi # imm = 0x1286B6
callq srand
movl $8, %r12d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, -8(%rbx,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, -4(%rbx,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, (%rbx,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, -8(%r14,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, -4(%r14,%r12)
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, (%r14,%r12)
addq $12, %r12
cmpq $120008, %r12 # imm = 0x1D4C8
jne .LBB1_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $120000, %esi # imm = 0x1D4C0
callq hipMalloc
leaq 16(%rsp), %rdi
movl $120000, %esi # imm = 0x1D4C0
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
movq 24(%rsp), %rdi
movl $120000, %edx # imm = 0x1D4C0
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $120000, %edx # imm = 0x1D4C0
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967336, %rdi # imm = 0x100000028
leaq 216(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl $10000, 36(%rsp) # imm = 0x2710
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 104(%rsp), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $40000, %edx # imm = 0x9C40
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $2, %r12d
movq %r15, %r13
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss -8(%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss -4(%rbx,%r12,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss -8(%r14,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss -4(%r14,%r12,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
cvtss2sd %xmm2, %xmm2
cvtss2sd %xmm3, %xmm3
movss (%rbx,%r12,4), %xmm4 # xmm4 = mem[0],zero,zero,zero
cvtss2sd %xmm4, %xmm4
movss (%r14,%r12,4), %xmm5 # xmm5 = mem[0],zero,zero,zero
cvtss2sd %xmm5, %xmm5
movss (%r13), %xmm6 # xmm6 = mem[0],zero,zero,zero
cvtss2sd %xmm6, %xmm6
movl $.L.str, %edi
movb $7, %al
callq printf
addq $4, %r13
addq $3, %r12
cmpq $32, %r12
jne .LBB1_5
# %bb.6:
movl $.Lstr, %edi
callq puts@PLT
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf,@object # @_Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf
.section .rodata,"a",@progbits
.globl _Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf
.p2align 3, 0x0
_Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf:
.quad _Z18__device_stub__dotiPK15HIP_vector_typeIfLj3EES2_Pf
.size _Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f*%f + %f*%f + %f*%f = %f\n"
.size .L.str, 28
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "..."
.size .Lstr, 4
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__dotiPK15HIP_vector_typeIfLj3EES2_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3dotiPK15HIP_vector_typeIfLj3EES2_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
typedef short WORD;
typedef int DWORD;
typedef int LONG;
static unsigned char s_box[256] = {
// 0 1 2 3 4 5 6 7 8 9 a b c d e f
0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76, // 0
0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0, // 1
0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc, 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15, // 2
0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75, // 3
0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84, // 4
0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf, // 5
0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8, // 6
0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5, 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2, // 7
0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73, // 8
0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb, // 9
0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79, // a
0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9, 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08, // b
0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a, // c
0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e, // d
0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf, // e
0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16};// f
static unsigned char inv_s_box[256] = {
// 0 1 2 3 4 5 6 7 8 9 a b c d e f
0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38, 0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb, // 0
0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87, 0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb, // 1
0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d, 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e, // 2
0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2, 0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25, // 3
0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16, 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92, // 4
0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda, 0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84, // 5
0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a, 0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06, // 6
0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02, 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b, // 7
0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea, 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73, // 8
0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85, 0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e, // 9
0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89, 0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b, // a
0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20, 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4, // b
0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31, 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f, // c
0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d, 0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef, // d
0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0, 0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61, // e
0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26, 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d};// f
int Nb = 4;
void shift_rows(unsigned char *state) {
unsigned char i, k, s, tmp;
for (i = 1; i < 4; i++) {
s = 0;
while (s < i) {
tmp = state[Nb*i+0];
for (k = 1; k < Nb; k++) {
state[Nb*i+k-1] = state[Nb*i+k];
}
state[Nb*i+Nb-1] = tmp;
s++;
}
}
}
void inv_shift_rows(unsigned char *state) {
unsigned char i, k, s, tmp;
for (i = 1; i < 4; i++) {
s = 0;
while (s < i) {
tmp = state[Nb*i+Nb-1];
for (k = Nb-1; k > 0; k--) {
state[Nb*i+k] = state[Nb*i+k-1];
}
state[Nb*i+0] = tmp;
s++;
}
}
}
unsigned char gmult(unsigned char a, unsigned char b) {
unsigned char p = 0, i = 0, hbs = 0;
for (i = 0; i < 8; i++) {
if (b & 1) {
p ^= a;
}
hbs = a & 0x80;
a <<= 1;
if (hbs) a ^= 0x1b; // 0000 0001 0001 1011
b >>= 1;
}
return (unsigned char)p;
}
void coef_mult(unsigned char *a, unsigned char *b, unsigned char *d) {
d[0] = gmult(a[0],b[0])^gmult(a[3],b[1])^gmult(a[2],b[2])^gmult(a[1],b[3]);
d[1] = gmult(a[1],b[0])^gmult(a[0],b[1])^gmult(a[3],b[2])^gmult(a[2],b[3]);
d[2] = gmult(a[2],b[0])^gmult(a[1],b[1])^gmult(a[0],b[2])^gmult(a[3],b[3]);
d[3] = gmult(a[3],b[0])^gmult(a[2],b[1])^gmult(a[1],b[2])^gmult(a[0],b[3]);
}
void mix_columns(unsigned char *state) {
unsigned char a[] = {0x02, 0x01, 0x01, 0x03}; // a(x) = {02} + {01}x + {01}x2 + {03}x3
unsigned char i, j, col[4], res[4];
for (j = 0; j < Nb; j++) {
for (i = 0; i < 4; i++) {
col[i] = state[Nb*i+j];
}
coef_mult(a, col, res);
for (i = 0; i < 4; i++) {
state[Nb*i+j] = res[i];
}
}
}
void inv_mix_columns(unsigned char *state) {
unsigned char a[] = {0x0e, 0x09, 0x0d, 0x0b}; // a(x) = {0e} + {09}x + {0d}x2 + {0b}x3
unsigned char i, j, col[4], res[4];
for (j = 0; j < Nb; j++) {
for (i = 0; i < 4; i++) {
col[i] = state[Nb*i+j];
}
coef_mult(a, col, res);
for (i = 0; i < 4; i++) {
state[Nb*i+j] = res[i];
}
}
}
//Round Keys
unsigned char key[16] = {
0x00, 0x01, 0x02, 0x03,
0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0a, 0x0b,
0x0c, 0x0d, 0x0e, 0x0f};
void key_xor(unsigned char *state){
for(int i=0;i < 16;i++)
{
state[i] = state[i]^key[i];
}
}
#pragma pack(push, 1)
typedef struct tagBITMAPFILEHEADER
{
WORD bfType; //specifies the file type
DWORD bfSize; //specifies the size in bytes of the bitmap file
WORD bfReserved1; //reserved; must be 0
WORD bfReserved2; //reserved; must be 0
DWORD bOffBits; //species the offset in bytes from the bitmapfileheader to the bitmap bits
}BITMAPFILEHEADER;
#pragma pack(pop)
#pragma pack(push, 1)
typedef struct tagBITMAPINFOHEADER
{
DWORD biSize; //specifies the number of bytes required by the struct
LONG biWidth; //specifies width in pixels
LONG biHeight; //species height in pixels
WORD biPlanes; //specifies the number of color planes, must be 1
WORD biBitCount; //specifies the number of bit per pixel
DWORD biCompression;//spcifies the type of compression
DWORD biSizeImage; //size of image in bytes
LONG biXPelsPerMeter; //number of pixels per meter in x axis
LONG biYPelsPerMeter; //number of pixels per meter in y axis
DWORD biClrUsed; //number of colors used by th ebitmap
DWORD biClrImportant; //number of colors that are important
}BITMAPINFOHEADER;
#pragma pack(pop)
unsigned char *LoadBitmapFile(char *filename, BITMAPINFOHEADER *bitmapInfoHeader, BITMAPFILEHEADER *bitmapFileHeader)
{
FILE *filePtr; //our file pointer
unsigned char *bitmapImage; //store image data
int imageIdx=0; //image index counter
unsigned char tempRGB; //our swap variable
//open filename in read binary mode
filePtr = fopen(filename,"rb");
if (filePtr == NULL)
return NULL;
//read the bitmap file header
fread(bitmapFileHeader, sizeof(BITMAPFILEHEADER),1,filePtr);
//verify that this is a bmp file by check bitmap id
if (bitmapFileHeader->bfType !=0x4D42)
{
fclose(filePtr);
return NULL;
}
//read the bitmap info header
fread(bitmapInfoHeader, sizeof(BITMAPINFOHEADER),1,filePtr); // small edit. forgot to add the closing bracket at sizeof
//move file point to the begging of bitmap data
fseek(filePtr, bitmapFileHeader->bOffBits, SEEK_SET);
//allocate enough memory for the bitmap image data
bitmapImage = (unsigned char*)malloc(bitmapInfoHeader->biSizeImage);
//verify memory allocation
if (!bitmapImage)
{
free(bitmapImage);
fclose(filePtr);
return NULL;
}
//read in the bitmap image data
fread(bitmapImage,1,bitmapInfoHeader->biSizeImage,filePtr);
//make sure bitmap image data was read
if (bitmapImage == NULL)
{
fclose(filePtr);
return NULL;
}
cudaEvent_t start;
cudaEventCreate(&start);
cudaEvent_t end;
cudaEventCreate(&end);
float swapTime;
cudaEventRecord(start, 0);
//swap the r and b values to get RGB (bitmap is BGR)
for (imageIdx = 0; imageIdx < bitmapInfoHeader->biSizeImage;imageIdx+=3)
{
tempRGB = bitmapImage[imageIdx];
bitmapImage[imageIdx] = bitmapImage[imageIdx + 2];
bitmapImage[imageIdx + 2] = tempRGB;
}
cudaEventRecord(end, 0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&swapTime, start, end);
printf("Load Swap Time: %fms\n",swapTime);
cudaEventDestroy(start);
cudaEventDestroy(end);
//close file and return bitmap iamge data
fclose(filePtr);
return bitmapImage;
}
void ReloadBitmapFile(char *filename, unsigned char *bitmapImage, BITMAPFILEHEADER *bitmapFileHeader, BITMAPINFOHEADER *bitmapInfoHeader)
{
FILE *filePtr; //our file pointer
int imageIdx=0; //image index counter
unsigned char tempRGB; //our swap variable
//open filename in write binary mode
filePtr = fopen(filename,"wb");
if (filePtr == NULL)
{
printf("\nERROR: Cannot open file %s", filename);
exit(1);
}
//write the bitmap file header
fwrite(bitmapFileHeader, sizeof(BITMAPFILEHEADER),1,filePtr);
//write the bitmap info header
fwrite(bitmapInfoHeader, sizeof(BITMAPINFOHEADER),1,filePtr); // small edit. forgot to add the closing bracket at sizeof
//swap the r and b values to get RGB (bitmap is BGR)
for (imageIdx = 0; imageIdx < bitmapInfoHeader->biSizeImage;imageIdx+=3)
{
tempRGB = bitmapImage[imageIdx];
bitmapImage[imageIdx] = bitmapImage[imageIdx + 2];
bitmapImage[imageIdx + 2] = tempRGB;
}
//write in the bitmap image data
fwrite(bitmapImage,bitmapInfoHeader->biSizeImage,1,filePtr);
//close file
fclose(filePtr);
}
void encrypt(unsigned char *bitmapImage, int size, int key)
{
int i;
//byte substitution
for(i=0;i < size;i++)
{
bitmapImage[i] = s_box[bitmapImage[i]];
}
//shift rows
unsigned char * p = bitmapImage;
for(i=0;i < size;i+=16)
{
shift_rows(p + i);
}
//mix columns
p = bitmapImage;
for(i=0;i < size;i+=16)
{
mix_columns(p + i);
}
//Add key
p = bitmapImage;
for(i=0;i < size;i+=16)
{
key_xor(p + i);
}
}
void decrypt(unsigned char *bitmapImage, int size, int key)
{
int i;
unsigned char * p = bitmapImage;
//Add key
for(i=0;i < size;i+=16)
{
key_xor(p + i);
}
//mix columns
p = bitmapImage;
for(i=0;i < size;i+=16)
{
inv_mix_columns(p + i);
}
//shift rows
p = bitmapImage;
for(i=0;i < size;i+=16)
{
inv_shift_rows(p + i);
}
//byte substitution
for(i=0;i < size;i++)
{
bitmapImage[i] = inv_s_box[bitmapImage[i]];
}
}
int main()
{
BITMAPINFOHEADER bitmapInfoHeader;
BITMAPFILEHEADER bitmapFileHeader;
unsigned char *bitmapData;
bitmapData = LoadBitmapFile("lena.bmp",&bitmapInfoHeader, &bitmapFileHeader);
printf("%d\n",bitmapInfoHeader.biSizeImage);
int key = 251;
cudaEvent_t start;
cudaEventCreate(&start);
cudaEvent_t end;
cudaEventCreate(&end);
float encryptionTime, decryptionTime;
//Encryption
cudaEventRecord(start, 0);
encrypt(bitmapData, bitmapInfoHeader.biSizeImage, key);
cudaEventRecord(end, 0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&encryptionTime, start, end);
printf("Encryption Time: %fms\n",encryptionTime);
ReloadBitmapFile("encrypted.bmp", bitmapData, &bitmapFileHeader, &bitmapInfoHeader);
//load encrypted image to array
bitmapData = LoadBitmapFile("encrypted.bmp",&bitmapInfoHeader, &bitmapFileHeader);
//Decryption
cudaEventRecord(start, 0);
decrypt(bitmapData, bitmapInfoHeader.biSizeImage, key);
cudaEventRecord(end, 0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&decryptionTime, start, end);
printf("Decryption Time: %fms\n",decryptionTime);
ReloadBitmapFile("Decrypted.bmp", bitmapData, &bitmapFileHeader, &bitmapInfoHeader);
cudaEventDestroy(start);
cudaEventDestroy(end);
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
typedef short WORD;
typedef int DWORD;
typedef int LONG;
static unsigned char s_box[256] = {
// 0 1 2 3 4 5 6 7 8 9 a b c d e f
0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76, // 0
0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0, // 1
0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc, 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15, // 2
0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75, // 3
0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84, // 4
0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf, // 5
0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8, // 6
0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5, 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2, // 7
0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73, // 8
0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb, // 9
0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79, // a
0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9, 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08, // b
0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a, // c
0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e, // d
0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf, // e
0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16};// f
static unsigned char inv_s_box[256] = {
// 0 1 2 3 4 5 6 7 8 9 a b c d e f
0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38, 0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb, // 0
0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87, 0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb, // 1
0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d, 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e, // 2
0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2, 0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25, // 3
0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16, 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92, // 4
0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda, 0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84, // 5
0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a, 0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06, // 6
0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02, 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b, // 7
0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea, 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73, // 8
0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85, 0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e, // 9
0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89, 0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b, // a
0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20, 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4, // b
0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31, 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f, // c
0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d, 0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef, // d
0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0, 0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61, // e
0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26, 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d};// f
int Nb = 4;
void shift_rows(unsigned char *state) {
unsigned char i, k, s, tmp;
for (i = 1; i < 4; i++) {
s = 0;
while (s < i) {
tmp = state[Nb*i+0];
for (k = 1; k < Nb; k++) {
state[Nb*i+k-1] = state[Nb*i+k];
}
state[Nb*i+Nb-1] = tmp;
s++;
}
}
}
void inv_shift_rows(unsigned char *state) {
unsigned char i, k, s, tmp;
for (i = 1; i < 4; i++) {
s = 0;
while (s < i) {
tmp = state[Nb*i+Nb-1];
for (k = Nb-1; k > 0; k--) {
state[Nb*i+k] = state[Nb*i+k-1];
}
state[Nb*i+0] = tmp;
s++;
}
}
}
unsigned char gmult(unsigned char a, unsigned char b) {
unsigned char p = 0, i = 0, hbs = 0;
for (i = 0; i < 8; i++) {
if (b & 1) {
p ^= a;
}
hbs = a & 0x80;
a <<= 1;
if (hbs) a ^= 0x1b; // 0000 0001 0001 1011
b >>= 1;
}
return (unsigned char)p;
}
void coef_mult(unsigned char *a, unsigned char *b, unsigned char *d) {
d[0] = gmult(a[0],b[0])^gmult(a[3],b[1])^gmult(a[2],b[2])^gmult(a[1],b[3]);
d[1] = gmult(a[1],b[0])^gmult(a[0],b[1])^gmult(a[3],b[2])^gmult(a[2],b[3]);
d[2] = gmult(a[2],b[0])^gmult(a[1],b[1])^gmult(a[0],b[2])^gmult(a[3],b[3]);
d[3] = gmult(a[3],b[0])^gmult(a[2],b[1])^gmult(a[1],b[2])^gmult(a[0],b[3]);
}
void mix_columns(unsigned char *state) {
unsigned char a[] = {0x02, 0x01, 0x01, 0x03}; // a(x) = {02} + {01}x + {01}x2 + {03}x3
unsigned char i, j, col[4], res[4];
for (j = 0; j < Nb; j++) {
for (i = 0; i < 4; i++) {
col[i] = state[Nb*i+j];
}
coef_mult(a, col, res);
for (i = 0; i < 4; i++) {
state[Nb*i+j] = res[i];
}
}
}
void inv_mix_columns(unsigned char *state) {
unsigned char a[] = {0x0e, 0x09, 0x0d, 0x0b}; // a(x) = {0e} + {09}x + {0d}x2 + {0b}x3
unsigned char i, j, col[4], res[4];
for (j = 0; j < Nb; j++) {
for (i = 0; i < 4; i++) {
col[i] = state[Nb*i+j];
}
coef_mult(a, col, res);
for (i = 0; i < 4; i++) {
state[Nb*i+j] = res[i];
}
}
}
//Round Keys
unsigned char key[16] = {
0x00, 0x01, 0x02, 0x03,
0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0a, 0x0b,
0x0c, 0x0d, 0x0e, 0x0f};
void key_xor(unsigned char *state){
for(int i=0;i < 16;i++)
{
state[i] = state[i]^key[i];
}
}
#pragma pack(push, 1)
typedef struct tagBITMAPFILEHEADER
{
WORD bfType; //specifies the file type
DWORD bfSize; //specifies the size in bytes of the bitmap file
WORD bfReserved1; //reserved; must be 0
WORD bfReserved2; //reserved; must be 0
DWORD bOffBits; //species the offset in bytes from the bitmapfileheader to the bitmap bits
}BITMAPFILEHEADER;
#pragma pack(pop)
#pragma pack(push, 1)
typedef struct tagBITMAPINFOHEADER
{
DWORD biSize; //specifies the number of bytes required by the struct
LONG biWidth; //specifies width in pixels
LONG biHeight; //species height in pixels
WORD biPlanes; //specifies the number of color planes, must be 1
WORD biBitCount; //specifies the number of bit per pixel
DWORD biCompression;//spcifies the type of compression
DWORD biSizeImage; //size of image in bytes
LONG biXPelsPerMeter; //number of pixels per meter in x axis
LONG biYPelsPerMeter; //number of pixels per meter in y axis
DWORD biClrUsed; //number of colors used by th ebitmap
DWORD biClrImportant; //number of colors that are important
}BITMAPINFOHEADER;
#pragma pack(pop)
unsigned char *LoadBitmapFile(char *filename, BITMAPINFOHEADER *bitmapInfoHeader, BITMAPFILEHEADER *bitmapFileHeader)
{
FILE *filePtr; //our file pointer
unsigned char *bitmapImage; //store image data
int imageIdx=0; //image index counter
unsigned char tempRGB; //our swap variable
//open filename in read binary mode
filePtr = fopen(filename,"rb");
if (filePtr == NULL)
return NULL;
//read the bitmap file header
fread(bitmapFileHeader, sizeof(BITMAPFILEHEADER),1,filePtr);
//verify that this is a bmp file by check bitmap id
if (bitmapFileHeader->bfType !=0x4D42)
{
fclose(filePtr);
return NULL;
}
//read the bitmap info header
fread(bitmapInfoHeader, sizeof(BITMAPINFOHEADER),1,filePtr); // small edit. forgot to add the closing bracket at sizeof
//move file point to the begging of bitmap data
fseek(filePtr, bitmapFileHeader->bOffBits, SEEK_SET);
//allocate enough memory for the bitmap image data
bitmapImage = (unsigned char*)malloc(bitmapInfoHeader->biSizeImage);
//verify memory allocation
if (!bitmapImage)
{
free(bitmapImage);
fclose(filePtr);
return NULL;
}
//read in the bitmap image data
fread(bitmapImage,1,bitmapInfoHeader->biSizeImage,filePtr);
//make sure bitmap image data was read
if (bitmapImage == NULL)
{
fclose(filePtr);
return NULL;
}
cudaEvent_t start;
cudaEventCreate(&start);
cudaEvent_t end;
cudaEventCreate(&end);
float swapTime;
cudaEventRecord(start, 0);
//swap the r and b values to get RGB (bitmap is BGR)
for (imageIdx = 0; imageIdx < bitmapInfoHeader->biSizeImage;imageIdx+=3)
{
tempRGB = bitmapImage[imageIdx];
bitmapImage[imageIdx] = bitmapImage[imageIdx + 2];
bitmapImage[imageIdx + 2] = tempRGB;
}
cudaEventRecord(end, 0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&swapTime, start, end);
printf("Load Swap Time: %fms\n",swapTime);
cudaEventDestroy(start);
cudaEventDestroy(end);
//close file and return bitmap iamge data
fclose(filePtr);
return bitmapImage;
}
void ReloadBitmapFile(char *filename, unsigned char *bitmapImage, BITMAPFILEHEADER *bitmapFileHeader, BITMAPINFOHEADER *bitmapInfoHeader)
{
FILE *filePtr; //our file pointer
int imageIdx=0; //image index counter
unsigned char tempRGB; //our swap variable
//open filename in write binary mode
filePtr = fopen(filename,"wb");
if (filePtr == NULL)
{
printf("\nERROR: Cannot open file %s", filename);
exit(1);
}
//write the bitmap file header
fwrite(bitmapFileHeader, sizeof(BITMAPFILEHEADER),1,filePtr);
//write the bitmap info header
fwrite(bitmapInfoHeader, sizeof(BITMAPINFOHEADER),1,filePtr); // small edit. forgot to add the closing bracket at sizeof
//swap the r and b values to get RGB (bitmap is BGR)
for (imageIdx = 0; imageIdx < bitmapInfoHeader->biSizeImage;imageIdx+=3)
{
tempRGB = bitmapImage[imageIdx];
bitmapImage[imageIdx] = bitmapImage[imageIdx + 2];
bitmapImage[imageIdx + 2] = tempRGB;
}
//write in the bitmap image data
fwrite(bitmapImage,bitmapInfoHeader->biSizeImage,1,filePtr);
//close file
fclose(filePtr);
}
void encrypt(unsigned char *bitmapImage, int size, int key)
{
int i;
//byte substitution
for(i=0;i < size;i++)
{
bitmapImage[i] = s_box[bitmapImage[i]];
}
//shift rows
unsigned char * p = bitmapImage;
for(i=0;i < size;i+=16)
{
shift_rows(p + i);
}
//mix columns
p = bitmapImage;
for(i=0;i < size;i+=16)
{
mix_columns(p + i);
}
//Add key
p = bitmapImage;
for(i=0;i < size;i+=16)
{
key_xor(p + i);
}
}
void decrypt(unsigned char *bitmapImage, int size, int key)
{
int i;
unsigned char * p = bitmapImage;
//Add key
for(i=0;i < size;i+=16)
{
key_xor(p + i);
}
//mix columns
p = bitmapImage;
for(i=0;i < size;i+=16)
{
inv_mix_columns(p + i);
}
//shift rows
p = bitmapImage;
for(i=0;i < size;i+=16)
{
inv_shift_rows(p + i);
}
//byte substitution
for(i=0;i < size;i++)
{
bitmapImage[i] = inv_s_box[bitmapImage[i]];
}
}
int main()
{
BITMAPINFOHEADER bitmapInfoHeader;
BITMAPFILEHEADER bitmapFileHeader;
unsigned char *bitmapData;
bitmapData = LoadBitmapFile("lena.bmp",&bitmapInfoHeader, &bitmapFileHeader);
printf("%d\n",bitmapInfoHeader.biSizeImage);
int key = 251;
cudaEvent_t start;
cudaEventCreate(&start);
cudaEvent_t end;
cudaEventCreate(&end);
float encryptionTime, decryptionTime;
//Encryption
cudaEventRecord(start, 0);
encrypt(bitmapData, bitmapInfoHeader.biSizeImage, key);
cudaEventRecord(end, 0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&encryptionTime, start, end);
printf("Encryption Time: %fms\n",encryptionTime);
ReloadBitmapFile("encrypted.bmp", bitmapData, &bitmapFileHeader, &bitmapInfoHeader);
//load encrypted image to array
bitmapData = LoadBitmapFile("encrypted.bmp",&bitmapInfoHeader, &bitmapFileHeader);
//Decryption
cudaEventRecord(start, 0);
decrypt(bitmapData, bitmapInfoHeader.biSizeImage, key);
cudaEventRecord(end, 0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&decryptionTime, start, end);
printf("Decryption Time: %fms\n",decryptionTime);
ReloadBitmapFile("Decrypted.bmp", bitmapData, &bitmapFileHeader, &bitmapInfoHeader);
cudaEventDestroy(start);
cudaEventDestroy(end);
return 0;
} | .file "tmpxft_000a27ec_00000000-6_serial.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2071:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2071:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10shift_rowsPh
.type _Z10shift_rowsPh, @function
_Z10shift_rowsPh:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movq %rdi, %rcx
movl $1, %r8d
movl $1, %ebx
.L4:
movl %r8d, %r11d
movl $0, %edi
movl %r8d, %esi
leal 1(%r8), %r10d
testb %r8b, %r8b
je .L16
.L7:
movl Nb(%rip), %eax
movl %r8d, %edx
imull %eax, %edx
movslq %edx, %rdx
movzbl (%rcx,%rdx), %r9d
cmpl $1, %eax
jle .L5
movl $1, %ebp
movl %ebx, %edx
.L6:
imull %esi, %eax
addl %edx, %eax
cltq
movzbl (%rcx,%rax), %edx
movb %dl, -1(%rcx,%rax)
addl $1, %ebp
movzbl %bpl, %edx
movl Nb(%rip), %eax
cmpl %eax, %edx
jl .L6
.L5:
imull %r10d, %eax
cltq
movb %r9b, -1(%rcx,%rax)
addl $1, %edi
cmpb %dil, %r11b
jne .L7
addl $1, %r8d
cmpl $4, %r8d
jne .L4
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl %r10d, %r8d
jmp .L4
.cfi_endproc
.LFE2057:
.size _Z10shift_rowsPh, .-_Z10shift_rowsPh
.globl _Z14inv_shift_rowsPh
.type _Z14inv_shift_rowsPh, @function
_Z14inv_shift_rowsPh:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rcx
movl $1, %r9d
.L18:
movl %r9d, %ebx
movl $0, %r8d
movl %r9d, %edi
leal 1(%r9), %r11d
testb %r9b, %r9b
je .L30
.L21:
movl Nb(%rip), %edx
movl %r11d, %eax
imull %edx, %eax
cltq
movzbl -1(%rcx,%rax), %r10d
subb $1, %dl
je .L19
movzbl %dl, %edx
.L20:
movl %edi, %eax
imull Nb(%rip), %eax
addl %edx, %eax
cltq
movzbl -1(%rcx,%rax), %esi
movb %sil, (%rcx,%rax)
subl $1, %edx
testb %dl, %dl
jne .L20
.L19:
movl %edi, %eax
imull Nb(%rip), %eax
cltq
movb %r10b, (%rcx,%rax)
addl $1, %r8d
cmpb %bl, %r8b
jne .L21
addl $1, %r9d
cmpl $4, %r9d
jne .L18
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movl %r11d, %r9d
jmp .L18
.cfi_endproc
.LFE2058:
.size _Z14inv_shift_rowsPh, .-_Z14inv_shift_rowsPh
.globl _Z5gmulthh
.type _Z5gmulthh, @function
_Z5gmulthh:
.LFB2059:
.cfi_startproc
endbr64
movl $8, %edx
movl $0, %ecx
.L33:
movl %esi, %eax
andl $1, %eax
negl %eax
andl %edi, %eax
xorl %eax, %ecx
leal (%rdi,%rdi), %eax
movl %eax, %r8d
xorl $27, %r8d
testb %dil, %dil
cmovs %r8d, %eax
movl %eax, %edi
shrb %sil
subb $1, %dl
jne .L33
movl %ecx, %eax
ret
.cfi_endproc
.LFE2059:
.size _Z5gmulthh, .-_Z5gmulthh
.globl _Z9coef_multPhS_S_
.type _Z9coef_multPhS_S_, @function
_Z9coef_multPhS_S_:
.LFB2060:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r13
movzbl (%rsi), %esi
movzbl (%rdi), %edi
call _Z5gmulthh
movl %eax, %r12d
movzbl 1(%rbp), %esi
movzbl 3(%rbx), %edi
call _Z5gmulthh
xorl %eax, %r12d
movzbl 2(%rbp), %esi
movzbl 2(%rbx), %edi
call _Z5gmulthh
xorl %eax, %r12d
movzbl 3(%rbp), %esi
movzbl 1(%rbx), %edi
call _Z5gmulthh
xorl %eax, %r12d
movb %r12b, 0(%r13)
movzbl 0(%rbp), %esi
movzbl 1(%rbx), %edi
call _Z5gmulthh
movl %eax, %r12d
movzbl 1(%rbp), %esi
movzbl (%rbx), %edi
call _Z5gmulthh
xorl %eax, %r12d
movzbl 2(%rbp), %esi
movzbl 3(%rbx), %edi
call _Z5gmulthh
xorl %eax, %r12d
movzbl 3(%rbp), %esi
movzbl 2(%rbx), %edi
call _Z5gmulthh
xorl %eax, %r12d
movb %r12b, 1(%r13)
movzbl 0(%rbp), %esi
movzbl 2(%rbx), %edi
call _Z5gmulthh
movl %eax, %r12d
movzbl 1(%rbp), %esi
movzbl 1(%rbx), %edi
call _Z5gmulthh
xorl %eax, %r12d
movzbl 2(%rbp), %esi
movzbl (%rbx), %edi
call _Z5gmulthh
xorl %eax, %r12d
movzbl 3(%rbp), %esi
movzbl 3(%rbx), %edi
call _Z5gmulthh
xorl %eax, %r12d
movb %r12b, 2(%r13)
movzbl 0(%rbp), %esi
movzbl 3(%rbx), %edi
call _Z5gmulthh
movl %eax, %r12d
movzbl 1(%rbp), %esi
movzbl 2(%rbx), %edi
call _Z5gmulthh
xorl %eax, %r12d
movzbl 2(%rbp), %esi
movzbl 1(%rbx), %edi
call _Z5gmulthh
xorl %eax, %r12d
movzbl 3(%rbp), %esi
movzbl (%rbx), %edi
call _Z5gmulthh
xorl %eax, %r12d
movb %r12b, 3(%r13)
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z9coef_multPhS_S_, .-_Z9coef_multPhS_S_
.globl _Z11mix_columnsPh
.type _Z11mix_columnsPh, @function
_Z11mix_columnsPh:
.LFB2061:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r12
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $50397442, 12(%rsp)
movl Nb(%rip), %ecx
movl $0, %r13d
movl $0, %ebp
leaq 20(%rsp), %rbx
testl %ecx, %ecx
jg .L39
.L38:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L49
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
addl $1, %r13d
movzbl %r13b, %ebp
movl Nb(%rip), %ecx
cmpl %ecx, %ebp
jge .L38
.L39:
movslq %ecx, %rcx
movslq %ebp, %rdx
addq %r12, %rdx
leaq 16(%rsp), %rax
.L41:
movzbl (%rdx), %esi
movb %sil, (%rax)
addq %rcx, %rdx
addq $1, %rax
cmpq %rbx, %rax
jne .L41
leaq 16(%rsp), %rsi
leaq 12(%rsp), %rdi
movq %rbx, %rdx
call _Z9coef_multPhS_S_
movl $0, %edx
.L42:
movl %edx, %eax
imull Nb(%rip), %eax
addl %ebp, %eax
cltq
movzbl (%rdx,%rbx), %ecx
movb %cl, (%r12,%rax)
addq $1, %rdx
cmpq $4, %rdx
jne .L42
jmp .L50
.L49:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z11mix_columnsPh, .-_Z11mix_columnsPh
.globl _Z15inv_mix_columnsPh
.type _Z15inv_mix_columnsPh, @function
_Z15inv_mix_columnsPh:
.LFB2062:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r12
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $185403662, 12(%rsp)
movl Nb(%rip), %ecx
movl $0, %r13d
movl $0, %ebp
leaq 20(%rsp), %rbx
testl %ecx, %ecx
jg .L52
.L51:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L62
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L63:
.cfi_restore_state
addl $1, %r13d
movzbl %r13b, %ebp
movl Nb(%rip), %ecx
cmpl %ecx, %ebp
jge .L51
.L52:
movslq %ecx, %rcx
movslq %ebp, %rdx
addq %r12, %rdx
leaq 16(%rsp), %rax
.L54:
movzbl (%rdx), %esi
movb %sil, (%rax)
addq %rcx, %rdx
addq $1, %rax
cmpq %rbx, %rax
jne .L54
leaq 16(%rsp), %rsi
leaq 12(%rsp), %rdi
movq %rbx, %rdx
call _Z9coef_multPhS_S_
movl $0, %edx
.L55:
movl %edx, %eax
imull Nb(%rip), %eax
addl %ebp, %eax
cltq
movzbl (%rdx,%rbx), %ecx
movb %cl, (%r12,%rax)
addq $1, %rdx
cmpq $4, %rdx
jne .L55
jmp .L63
.L62:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size _Z15inv_mix_columnsPh, .-_Z15inv_mix_columnsPh
.globl _Z7key_xorPh
.type _Z7key_xorPh, @function
_Z7key_xorPh:
.LFB2063:
.cfi_startproc
endbr64
movl $0, %eax
leaq key(%rip), %rcx
.L65:
movzbl (%rcx,%rax), %edx
xorb %dl, (%rdi,%rax)
addq $1, %rax
cmpq $16, %rax
jne .L65
ret
.cfi_endproc
.LFE2063:
.size _Z7key_xorPh, .-_Z7key_xorPh
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "rb"
.LC1:
.string "Load Swap Time: %fms\n"
.text
.globl _Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER
.type _Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER, @function
_Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER:
.LFB2064:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %r12
movq %rdx, %rbx
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
call fopen@PLT
movq %rax, %rbp
testq %rax, %rax
je .L74
movq %rax, %r8
movl $1, %ecx
movl $14, %edx
movq $-1, %rsi
movq %rbx, %rdi
call __fread_chk@PLT
cmpw $19778, (%rbx)
jne .L77
movq %rbp, %r8
movl $1, %ecx
movl $40, %edx
movq $-1, %rsi
movq %r12, %rdi
call __fread_chk@PLT
movslq 10(%rbx), %rsi
movl $0, %edx
movq %rbp, %rdi
call fseek@PLT
movslq 20(%r12), %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, %rbx
testq %rax, %rax
je .L78
movq %rbp, %r8
movq %r13, %rcx
movl $1, %edx
movq %r13, %rsi
movq %rax, %rdi
call __fread_chk@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl 20(%r12), %esi
testl %esi, %esi
jle .L71
movl $0, %eax
.L72:
movzbl (%rbx,%rax), %edx
movzbl 2(%rbx,%rax), %ecx
movb %cl, (%rbx,%rax)
movb %dl, 2(%rbx,%rax)
addq $3, %rax
cmpl %eax, %esi
jg .L72
.L71:
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaEventDestroy@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq %rbp, %rdi
call fclose@PLT
.L67:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L79
movq %rbx, %rax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L77:
.cfi_restore_state
movq %rbp, %rdi
call fclose@PLT
movl $0, %ebx
jmp .L67
.L78:
movq %rbp, %rdi
call fclose@PLT
jmp .L67
.L74:
movq %rax, %rbx
jmp .L67
.L79:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2064:
.size _Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER, .-_Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER
.section .rodata.str1.1
.LC2:
.string "wb"
.LC3:
.string "\nERROR: Cannot open file %s"
.text
.globl _Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER
.type _Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER, @function
_Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER:
.LFB2065:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r13
movq %rsi, %rbx
movq %rdx, %r14
movq %rcx, %r12
leaq .LC2(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L86
movq %rax, %rbp
movq %rax, %rcx
movl $1, %edx
movl $14, %esi
movq %r14, %rdi
call fwrite@PLT
movq %rbp, %rcx
movl $1, %edx
movl $40, %esi
movq %r12, %rdi
call fwrite@PLT
movl 20(%r12), %esi
testl %esi, %esi
jle .L82
movl $0, %eax
.L83:
movzbl (%rbx,%rax), %edx
movzbl 2(%rbx,%rax), %ecx
movb %cl, (%rbx,%rax)
movb %dl, 2(%rbx,%rax)
movl 20(%r12), %esi
addq $3, %rax
cmpl %eax, %esi
jg .L83
.L82:
movslq %esi, %rsi
movq %rbp, %rcx
movl $1, %edx
movq %rbx, %rdi
call fwrite@PLT
movq %rbp, %rdi
call fclose@PLT
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L86:
.cfi_restore_state
movq %r13, %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2065:
.size _Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER, .-_Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER
.globl _Z7encryptPhii
.type _Z7encryptPhii, @function
_Z7encryptPhii:
.LFB2066:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L98
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movq %rdi, %rbp
movslq %esi, %rcx
addq %rdi, %rcx
movq %rdi, %rax
leaq _ZL5s_box(%rip), %rdi
.L89:
movzbl (%rax), %edx
movzbl (%rdi,%rdx), %edx
movb %dl, (%rax)
addq $1, %rax
cmpq %rcx, %rax
jne .L89
subl $1, %esi
shrl $4, %esi
movl %esi, %esi
salq $4, %rsi
leaq 16(%rbx,%rsi), %r13
movq %rbx, %r12
.L90:
movq %r12, %rdi
call _Z10shift_rowsPh
addq $16, %r12
cmpq %r13, %r12
jne .L90
.L91:
movq %rbx, %rdi
call _Z11mix_columnsPh
addq $16, %rbx
cmpq %r13, %rbx
jne .L91
.L92:
movq %rbp, %rdi
call _Z7key_xorPh
addq $16, %rbp
cmpq %r13, %rbp
jne .L92
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L98:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE2066:
.size _Z7encryptPhii, .-_Z7encryptPhii
.globl _Z7decryptPhii
.type _Z7decryptPhii, @function
_Z7decryptPhii:
.LFB2067:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L112
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r13
movl %esi, %r14d
movq %rdi, %rbx
leal -1(%rsi), %eax
shrl $4, %eax
movl %eax, %eax
salq $4, %rax
leaq 16(%rdi,%rax), %r12
movq %rdi, %rbp
.L103:
movq %rbp, %rdi
call _Z7key_xorPh
addq $16, %rbp
cmpq %r12, %rbp
jne .L103
movq %r13, %rbp
.L104:
movq %rbp, %rdi
call _Z15inv_mix_columnsPh
addq $16, %rbp
cmpq %r12, %rbp
jne .L104
movq %r13, %rbp
.L105:
movq %rbp, %rdi
call _Z14inv_shift_rowsPh
addq $16, %rbp
cmpq %r12, %rbp
jne .L105
movslq %r14d, %r14
addq %r14, %r13
leaq _ZL9inv_s_box(%rip), %rdx
.L106:
movzbl (%rbx), %eax
movzbl (%rdx,%rax), %eax
movb %al, (%rbx)
addq $1, %rbx
cmpq %rbx, %r13
jne .L106
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L112:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
ret
.cfi_endproc
.LFE2067:
.size _Z7decryptPhii, .-_Z7decryptPhii
.section .rodata.str1.1
.LC4:
.string "lena.bmp"
.LC5:
.string "%d\n"
.LC6:
.string "Encryption Time: %fms\n"
.LC7:
.string "encrypted.bmp"
.LC8:
.string "Decryption Time: %fms\n"
.LC9:
.string "Decrypted.bmp"
.text
.globl main
.type main, @function
main:
.LFB2068:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $96, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 34(%rsp), %rbp
leaq 48(%rsp), %r12
movq %rbp, %rdx
movq %r12, %rsi
leaq .LC4(%rip), %rdi
call _Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER
movq %rax, %rbx
movl 68(%rsp), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $251, %edx
movl 68(%rsp), %esi
movq %rbx, %rdi
call _Z7encryptPhii
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 8(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r12, %rcx
movq %rbp, %rdx
movq %rbx, %rsi
leaq .LC7(%rip), %rbx
movq %rbx, %rdi
call _Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER
movq %rbp, %rdx
movq %r12, %rsi
movq %rbx, %rdi
call _Z14LoadBitmapFilePcP19tagBITMAPINFOHEADERP19tagBITMAPFILEHEADER
movq %rax, %rbx
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $251, %edx
movl 68(%rsp), %esi
movq %rbx, %rdi
call _Z7decryptPhii
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r12, %rcx
movq %rbp, %rdx
movq %rbx, %rsi
leaq .LC9(%rip), %rdi
call _Z16ReloadBitmapFilePcPhP19tagBITMAPFILEHEADERP19tagBITMAPINFOHEADER
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L118
movl $0, %eax
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L118:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2068:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2094:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2094:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl key
.data
.align 16
.type key, @object
.size key, 16
key:
.string ""
.ascii "\001\002\003\004\005\006\007\b\t\n\013\f\r\016\017"
.globl Nb
.align 4
.type Nb, @object
.size Nb, 4
Nb:
.long 4
.section .rodata
.align 32
.type _ZL9inv_s_box, @object
.size _ZL9inv_s_box, 256
_ZL9inv_s_box:
.string "R\tj\32506\2458\277@\243\236\201\363\327\373|\3439\202\233/\377\2074\216CD\304\336\351\313T{\2242\246\302#=\356L\225\013B\372\303N\b.\241f(\331$\262v[\242Im\213\321%r\370\366d\206h\230\026\324\244\\\314]e\266\222lpHP\375\355\271\332^\025FW\247\215\235\204\220\330\253"
.ascii "\214\274\323\n\367\344X\005\270\263E\006\320,\036\217\312?\017"
.ascii "\002\301\257\275\003\001\023\212k:\221\021AOg\334\352\227\362"
.ascii "\317\316\360\264\346s\226\254t\"\347\2555\205\342\3717\350\034"
.ascii "u\337nG\361\032q\035)\305\211o\267b\016\252\030\276\033\374V"
.ascii ">K\306\322y \232\333\300\376x\315Z\364\037\335\2503\210\007\307"
.ascii "1\261\022\020Y'\200\354_`Q\177\251\031\265J\r-\345z\237\223\311"
.ascii "\234\357\240\340;M\256*\365\260\310\353\273<\203S\231a\027+\004"
.ascii "~\272w\326&\341i\024cU!\f}"
.align 32
.type _ZL5s_box, @object
.size _ZL5s_box, 256
_ZL5s_box:
.string "c|w{\362ko\3050\001g+\376\327\253v\312\202\311}\372YG\360\255\324\242\257\234\244r\300\267\375\223&6?\367\3144\245\345\361q\3301\025\004\307#\303\030\226\005\232\007\022\200\342\353'\262u\t\203,\032\033nZ\240R;\326\263)\343/\204S\321"
.ascii "\355 \374\261[j\313\2769JLX\317\320\357\252\373CM3\205E\371\002"
.ascii "\177P<\237\250Q\243@\217\222\2358\365\274\266\332!\020\377\363"
.ascii "\322\315\f\023\354_\227D\027\304\247~=d]\031s`\201O\334\"*\220"
.ascii "\210F\356\270\024\336^\013\333\3402:\nI\006$\\\302\323\254b\221"
.ascii "\225\344y\347\3107m\215\325N\251lV\364\352ez\256\b\272x%.\034"
.ascii "\246\264\306\350\335t\037K\275\213\212p>\265fH\003\366\016a5"
.ascii "W\271\206\301\035\236\341\370\230\021i\331\216\224\233\036\207"
.ascii "\351\316U(\337\214\241\211\r\277\346BhA\231-\017\260T\273\026"
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
typedef short WORD;
typedef int DWORD;
typedef int LONG;
static unsigned char s_box[256] = {
// 0 1 2 3 4 5 6 7 8 9 a b c d e f
0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76, // 0
0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0, // 1
0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc, 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15, // 2
0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75, // 3
0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84, // 4
0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf, // 5
0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8, // 6
0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5, 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2, // 7
0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73, // 8
0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb, // 9
0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79, // a
0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9, 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08, // b
0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a, // c
0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e, // d
0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf, // e
0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16};// f
static unsigned char inv_s_box[256] = {
// 0 1 2 3 4 5 6 7 8 9 a b c d e f
0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38, 0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb, // 0
0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87, 0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb, // 1
0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d, 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e, // 2
0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2, 0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25, // 3
0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16, 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92, // 4
0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda, 0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84, // 5
0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a, 0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06, // 6
0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02, 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b, // 7
0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea, 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73, // 8
0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85, 0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e, // 9
0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89, 0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b, // a
0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20, 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4, // b
0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31, 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f, // c
0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d, 0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef, // d
0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0, 0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61, // e
0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26, 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d};// f
int Nb = 4;
void shift_rows(unsigned char *state) {
unsigned char i, k, s, tmp;
for (i = 1; i < 4; i++) {
s = 0;
while (s < i) {
tmp = state[Nb*i+0];
for (k = 1; k < Nb; k++) {
state[Nb*i+k-1] = state[Nb*i+k];
}
state[Nb*i+Nb-1] = tmp;
s++;
}
}
}
void inv_shift_rows(unsigned char *state) {
unsigned char i, k, s, tmp;
for (i = 1; i < 4; i++) {
s = 0;
while (s < i) {
tmp = state[Nb*i+Nb-1];
for (k = Nb-1; k > 0; k--) {
state[Nb*i+k] = state[Nb*i+k-1];
}
state[Nb*i+0] = tmp;
s++;
}
}
}
unsigned char gmult(unsigned char a, unsigned char b) {
unsigned char p = 0, i = 0, hbs = 0;
for (i = 0; i < 8; i++) {
if (b & 1) {
p ^= a;
}
hbs = a & 0x80;
a <<= 1;
if (hbs) a ^= 0x1b; // 0000 0001 0001 1011
b >>= 1;
}
return (unsigned char)p;
}
void coef_mult(unsigned char *a, unsigned char *b, unsigned char *d) {
d[0] = gmult(a[0],b[0])^gmult(a[3],b[1])^gmult(a[2],b[2])^gmult(a[1],b[3]);
d[1] = gmult(a[1],b[0])^gmult(a[0],b[1])^gmult(a[3],b[2])^gmult(a[2],b[3]);
d[2] = gmult(a[2],b[0])^gmult(a[1],b[1])^gmult(a[0],b[2])^gmult(a[3],b[3]);
d[3] = gmult(a[3],b[0])^gmult(a[2],b[1])^gmult(a[1],b[2])^gmult(a[0],b[3]);
}
void mix_columns(unsigned char *state) {
unsigned char a[] = {0x02, 0x01, 0x01, 0x03}; // a(x) = {02} + {01}x + {01}x2 + {03}x3
unsigned char i, j, col[4], res[4];
for (j = 0; j < Nb; j++) {
for (i = 0; i < 4; i++) {
col[i] = state[Nb*i+j];
}
coef_mult(a, col, res);
for (i = 0; i < 4; i++) {
state[Nb*i+j] = res[i];
}
}
}
void inv_mix_columns(unsigned char *state) {
unsigned char a[] = {0x0e, 0x09, 0x0d, 0x0b}; // a(x) = {0e} + {09}x + {0d}x2 + {0b}x3
unsigned char i, j, col[4], res[4];
for (j = 0; j < Nb; j++) {
for (i = 0; i < 4; i++) {
col[i] = state[Nb*i+j];
}
coef_mult(a, col, res);
for (i = 0; i < 4; i++) {
state[Nb*i+j] = res[i];
}
}
}
//Round Keys
unsigned char key[16] = {
0x00, 0x01, 0x02, 0x03,
0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0a, 0x0b,
0x0c, 0x0d, 0x0e, 0x0f};
void key_xor(unsigned char *state){
for(int i=0;i < 16;i++)
{
state[i] = state[i]^key[i];
}
}
#pragma pack(push, 1)
typedef struct tagBITMAPFILEHEADER
{
WORD bfType; //specifies the file type
DWORD bfSize; //specifies the size in bytes of the bitmap file
WORD bfReserved1; //reserved; must be 0
WORD bfReserved2; //reserved; must be 0
DWORD bOffBits; //species the offset in bytes from the bitmapfileheader to the bitmap bits
}BITMAPFILEHEADER;
#pragma pack(pop)
#pragma pack(push, 1)
typedef struct tagBITMAPINFOHEADER
{
DWORD biSize; //specifies the number of bytes required by the struct
LONG biWidth; //specifies width in pixels
LONG biHeight; //species height in pixels
WORD biPlanes; //specifies the number of color planes, must be 1
WORD biBitCount; //specifies the number of bit per pixel
DWORD biCompression;//spcifies the type of compression
DWORD biSizeImage; //size of image in bytes
LONG biXPelsPerMeter; //number of pixels per meter in x axis
LONG biYPelsPerMeter; //number of pixels per meter in y axis
DWORD biClrUsed; //number of colors used by th ebitmap
DWORD biClrImportant; //number of colors that are important
}BITMAPINFOHEADER;
#pragma pack(pop)
unsigned char *LoadBitmapFile(char *filename, BITMAPINFOHEADER *bitmapInfoHeader, BITMAPFILEHEADER *bitmapFileHeader)
{
FILE *filePtr; //our file pointer
unsigned char *bitmapImage; //store image data
int imageIdx=0; //image index counter
unsigned char tempRGB; //our swap variable
//open filename in read binary mode
filePtr = fopen(filename,"rb");
if (filePtr == NULL)
return NULL;
//read the bitmap file header
fread(bitmapFileHeader, sizeof(BITMAPFILEHEADER),1,filePtr);
//verify that this is a bmp file by check bitmap id
if (bitmapFileHeader->bfType !=0x4D42)
{
fclose(filePtr);
return NULL;
}
//read the bitmap info header
fread(bitmapInfoHeader, sizeof(BITMAPINFOHEADER),1,filePtr); // small edit. forgot to add the closing bracket at sizeof
//move file point to the begging of bitmap data
fseek(filePtr, bitmapFileHeader->bOffBits, SEEK_SET);
//allocate enough memory for the bitmap image data
bitmapImage = (unsigned char*)malloc(bitmapInfoHeader->biSizeImage);
//verify memory allocation
if (!bitmapImage)
{
free(bitmapImage);
fclose(filePtr);
return NULL;
}
//read in the bitmap image data
fread(bitmapImage,1,bitmapInfoHeader->biSizeImage,filePtr);
//make sure bitmap image data was read
if (bitmapImage == NULL)
{
fclose(filePtr);
return NULL;
}
cudaEvent_t start;
cudaEventCreate(&start);
cudaEvent_t end;
cudaEventCreate(&end);
float swapTime;
cudaEventRecord(start, 0);
//swap the r and b values to get RGB (bitmap is BGR)
for (imageIdx = 0; imageIdx < bitmapInfoHeader->biSizeImage;imageIdx+=3)
{
tempRGB = bitmapImage[imageIdx];
bitmapImage[imageIdx] = bitmapImage[imageIdx + 2];
bitmapImage[imageIdx + 2] = tempRGB;
}
cudaEventRecord(end, 0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&swapTime, start, end);
printf("Load Swap Time: %fms\n",swapTime);
cudaEventDestroy(start);
cudaEventDestroy(end);
//close file and return bitmap iamge data
fclose(filePtr);
return bitmapImage;
}
void ReloadBitmapFile(char *filename, unsigned char *bitmapImage, BITMAPFILEHEADER *bitmapFileHeader, BITMAPINFOHEADER *bitmapInfoHeader)
{
FILE *filePtr; //our file pointer
int imageIdx=0; //image index counter
unsigned char tempRGB; //our swap variable
//open filename in write binary mode
filePtr = fopen(filename,"wb");
if (filePtr == NULL)
{
printf("\nERROR: Cannot open file %s", filename);
exit(1);
}
//write the bitmap file header
fwrite(bitmapFileHeader, sizeof(BITMAPFILEHEADER),1,filePtr);
//write the bitmap info header
fwrite(bitmapInfoHeader, sizeof(BITMAPINFOHEADER),1,filePtr); // small edit. forgot to add the closing bracket at sizeof
//swap the r and b values to get RGB (bitmap is BGR)
for (imageIdx = 0; imageIdx < bitmapInfoHeader->biSizeImage;imageIdx+=3)
{
tempRGB = bitmapImage[imageIdx];
bitmapImage[imageIdx] = bitmapImage[imageIdx + 2];
bitmapImage[imageIdx + 2] = tempRGB;
}
//write in the bitmap image data
fwrite(bitmapImage,bitmapInfoHeader->biSizeImage,1,filePtr);
//close file
fclose(filePtr);
}
void encrypt(unsigned char *bitmapImage, int size, int key)
{
int i;
//byte substitution
for(i=0;i < size;i++)
{
bitmapImage[i] = s_box[bitmapImage[i]];
}
//shift rows
unsigned char * p = bitmapImage;
for(i=0;i < size;i+=16)
{
shift_rows(p + i);
}
//mix columns
p = bitmapImage;
for(i=0;i < size;i+=16)
{
mix_columns(p + i);
}
//Add key
p = bitmapImage;
for(i=0;i < size;i+=16)
{
key_xor(p + i);
}
}
void decrypt(unsigned char *bitmapImage, int size, int key)
{
int i;
unsigned char * p = bitmapImage;
//Add key
for(i=0;i < size;i+=16)
{
key_xor(p + i);
}
//mix columns
p = bitmapImage;
for(i=0;i < size;i+=16)
{
inv_mix_columns(p + i);
}
//shift rows
p = bitmapImage;
for(i=0;i < size;i+=16)
{
inv_shift_rows(p + i);
}
//byte substitution
for(i=0;i < size;i++)
{
bitmapImage[i] = inv_s_box[bitmapImage[i]];
}
}
int main()
{
BITMAPINFOHEADER bitmapInfoHeader;
BITMAPFILEHEADER bitmapFileHeader;
unsigned char *bitmapData;
bitmapData = LoadBitmapFile("lena.bmp",&bitmapInfoHeader, &bitmapFileHeader);
printf("%d\n",bitmapInfoHeader.biSizeImage);
int key = 251;
cudaEvent_t start;
cudaEventCreate(&start);
cudaEvent_t end;
cudaEventCreate(&end);
float encryptionTime, decryptionTime;
//Encryption
cudaEventRecord(start, 0);
encrypt(bitmapData, bitmapInfoHeader.biSizeImage, key);
cudaEventRecord(end, 0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&encryptionTime, start, end);
printf("Encryption Time: %fms\n",encryptionTime);
ReloadBitmapFile("encrypted.bmp", bitmapData, &bitmapFileHeader, &bitmapInfoHeader);
//load encrypted image to array
bitmapData = LoadBitmapFile("encrypted.bmp",&bitmapInfoHeader, &bitmapFileHeader);
//Decryption
cudaEventRecord(start, 0);
decrypt(bitmapData, bitmapInfoHeader.biSizeImage, key);
cudaEventRecord(end, 0);
cudaEventSynchronize(end);
cudaEventElapsedTime(&decryptionTime, start, end);
printf("Decryption Time: %fms\n",decryptionTime);
ReloadBitmapFile("Decrypted.bmp", bitmapData, &bitmapFileHeader, &bitmapInfoHeader);
cudaEventDestroy(start);
cudaEventDestroy(end);
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
typedef short WORD;
typedef int DWORD;
typedef int LONG;
static unsigned char s_box[256] = {
// 0 1 2 3 4 5 6 7 8 9 a b c d e f
0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76, // 0
0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0, // 1
0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc, 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15, // 2
0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75, // 3
0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84, // 4
0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf, // 5
0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8, // 6
0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5, 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2, // 7
0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73, // 8
0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb, // 9
0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79, // a
0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9, 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08, // b
0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a, // c
0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e, // d
0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf, // e
0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16};// f
static unsigned char inv_s_box[256] = {
// 0 1 2 3 4 5 6 7 8 9 a b c d e f
0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38, 0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb, // 0
0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87, 0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb, // 1
0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d, 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e, // 2
0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2, 0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25, // 3
0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16, 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92, // 4
0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda, 0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84, // 5
0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a, 0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06, // 6
0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02, 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b, // 7
0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea, 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73, // 8
0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85, 0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e, // 9
0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89, 0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b, // a
0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20, 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4, // b
0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31, 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f, // c
0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d, 0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef, // d
0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0, 0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61, // e
0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26, 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d};// f
int Nb = 4;
void shift_rows(unsigned char *state) {
unsigned char i, k, s, tmp;
for (i = 1; i < 4; i++) {
s = 0;
while (s < i) {
tmp = state[Nb*i+0];
for (k = 1; k < Nb; k++) {
state[Nb*i+k-1] = state[Nb*i+k];
}
state[Nb*i+Nb-1] = tmp;
s++;
}
}
}
void inv_shift_rows(unsigned char *state) {
unsigned char i, k, s, tmp;
for (i = 1; i < 4; i++) {
s = 0;
while (s < i) {
tmp = state[Nb*i+Nb-1];
for (k = Nb-1; k > 0; k--) {
state[Nb*i+k] = state[Nb*i+k-1];
}
state[Nb*i+0] = tmp;
s++;
}
}
}
unsigned char gmult(unsigned char a, unsigned char b) {
unsigned char p = 0, i = 0, hbs = 0;
for (i = 0; i < 8; i++) {
if (b & 1) {
p ^= a;
}
hbs = a & 0x80;
a <<= 1;
if (hbs) a ^= 0x1b; // 0000 0001 0001 1011
b >>= 1;
}
return (unsigned char)p;
}
void coef_mult(unsigned char *a, unsigned char *b, unsigned char *d) {
d[0] = gmult(a[0],b[0])^gmult(a[3],b[1])^gmult(a[2],b[2])^gmult(a[1],b[3]);
d[1] = gmult(a[1],b[0])^gmult(a[0],b[1])^gmult(a[3],b[2])^gmult(a[2],b[3]);
d[2] = gmult(a[2],b[0])^gmult(a[1],b[1])^gmult(a[0],b[2])^gmult(a[3],b[3]);
d[3] = gmult(a[3],b[0])^gmult(a[2],b[1])^gmult(a[1],b[2])^gmult(a[0],b[3]);
}
void mix_columns(unsigned char *state) {
unsigned char a[] = {0x02, 0x01, 0x01, 0x03}; // a(x) = {02} + {01}x + {01}x2 + {03}x3
unsigned char i, j, col[4], res[4];
for (j = 0; j < Nb; j++) {
for (i = 0; i < 4; i++) {
col[i] = state[Nb*i+j];
}
coef_mult(a, col, res);
for (i = 0; i < 4; i++) {
state[Nb*i+j] = res[i];
}
}
}
void inv_mix_columns(unsigned char *state) {
unsigned char a[] = {0x0e, 0x09, 0x0d, 0x0b}; // a(x) = {0e} + {09}x + {0d}x2 + {0b}x3
unsigned char i, j, col[4], res[4];
for (j = 0; j < Nb; j++) {
for (i = 0; i < 4; i++) {
col[i] = state[Nb*i+j];
}
coef_mult(a, col, res);
for (i = 0; i < 4; i++) {
state[Nb*i+j] = res[i];
}
}
}
//Round Keys
unsigned char key[16] = {
0x00, 0x01, 0x02, 0x03,
0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0a, 0x0b,
0x0c, 0x0d, 0x0e, 0x0f};
void key_xor(unsigned char *state){
for(int i=0;i < 16;i++)
{
state[i] = state[i]^key[i];
}
}
#pragma pack(push, 1)
typedef struct tagBITMAPFILEHEADER
{
WORD bfType; //specifies the file type
DWORD bfSize; //specifies the size in bytes of the bitmap file
WORD bfReserved1; //reserved; must be 0
WORD bfReserved2; //reserved; must be 0
DWORD bOffBits; //species the offset in bytes from the bitmapfileheader to the bitmap bits
}BITMAPFILEHEADER;
#pragma pack(pop)
#pragma pack(push, 1)
typedef struct tagBITMAPINFOHEADER
{
DWORD biSize; //specifies the number of bytes required by the struct
LONG biWidth; //specifies width in pixels
LONG biHeight; //species height in pixels
WORD biPlanes; //specifies the number of color planes, must be 1
WORD biBitCount; //specifies the number of bit per pixel
DWORD biCompression;//spcifies the type of compression
DWORD biSizeImage; //size of image in bytes
LONG biXPelsPerMeter; //number of pixels per meter in x axis
LONG biYPelsPerMeter; //number of pixels per meter in y axis
DWORD biClrUsed; //number of colors used by th ebitmap
DWORD biClrImportant; //number of colors that are important
}BITMAPINFOHEADER;
#pragma pack(pop)
unsigned char *LoadBitmapFile(char *filename, BITMAPINFOHEADER *bitmapInfoHeader, BITMAPFILEHEADER *bitmapFileHeader)
{
FILE *filePtr; //our file pointer
unsigned char *bitmapImage; //store image data
int imageIdx=0; //image index counter
unsigned char tempRGB; //our swap variable
//open filename in read binary mode
filePtr = fopen(filename,"rb");
if (filePtr == NULL)
return NULL;
//read the bitmap file header
fread(bitmapFileHeader, sizeof(BITMAPFILEHEADER),1,filePtr);
//verify that this is a bmp file by check bitmap id
if (bitmapFileHeader->bfType !=0x4D42)
{
fclose(filePtr);
return NULL;
}
//read the bitmap info header
fread(bitmapInfoHeader, sizeof(BITMAPINFOHEADER),1,filePtr); // small edit. forgot to add the closing bracket at sizeof
//move file point to the begging of bitmap data
fseek(filePtr, bitmapFileHeader->bOffBits, SEEK_SET);
//allocate enough memory for the bitmap image data
bitmapImage = (unsigned char*)malloc(bitmapInfoHeader->biSizeImage);
//verify memory allocation
if (!bitmapImage)
{
free(bitmapImage);
fclose(filePtr);
return NULL;
}
//read in the bitmap image data
fread(bitmapImage,1,bitmapInfoHeader->biSizeImage,filePtr);
//make sure bitmap image data was read
if (bitmapImage == NULL)
{
fclose(filePtr);
return NULL;
}
hipEvent_t start;
hipEventCreate(&start);
hipEvent_t end;
hipEventCreate(&end);
float swapTime;
hipEventRecord(start, 0);
//swap the r and b values to get RGB (bitmap is BGR)
for (imageIdx = 0; imageIdx < bitmapInfoHeader->biSizeImage;imageIdx+=3)
{
tempRGB = bitmapImage[imageIdx];
bitmapImage[imageIdx] = bitmapImage[imageIdx + 2];
bitmapImage[imageIdx + 2] = tempRGB;
}
hipEventRecord(end, 0);
hipEventSynchronize(end);
hipEventElapsedTime(&swapTime, start, end);
printf("Load Swap Time: %fms\n",swapTime);
hipEventDestroy(start);
hipEventDestroy(end);
//close file and return bitmap iamge data
fclose(filePtr);
return bitmapImage;
}
void ReloadBitmapFile(char *filename, unsigned char *bitmapImage, BITMAPFILEHEADER *bitmapFileHeader, BITMAPINFOHEADER *bitmapInfoHeader)
{
FILE *filePtr; //our file pointer
int imageIdx=0; //image index counter
unsigned char tempRGB; //our swap variable
//open filename in write binary mode
filePtr = fopen(filename,"wb");
if (filePtr == NULL)
{
printf("\nERROR: Cannot open file %s", filename);
exit(1);
}
//write the bitmap file header
fwrite(bitmapFileHeader, sizeof(BITMAPFILEHEADER),1,filePtr);
//write the bitmap info header
fwrite(bitmapInfoHeader, sizeof(BITMAPINFOHEADER),1,filePtr); // small edit. forgot to add the closing bracket at sizeof
//swap the r and b values to get RGB (bitmap is BGR)
for (imageIdx = 0; imageIdx < bitmapInfoHeader->biSizeImage;imageIdx+=3)
{
tempRGB = bitmapImage[imageIdx];
bitmapImage[imageIdx] = bitmapImage[imageIdx + 2];
bitmapImage[imageIdx + 2] = tempRGB;
}
//write in the bitmap image data
fwrite(bitmapImage,bitmapInfoHeader->biSizeImage,1,filePtr);
//close file
fclose(filePtr);
}
void encrypt(unsigned char *bitmapImage, int size, int key)
{
int i;
//byte substitution
for(i=0;i < size;i++)
{
bitmapImage[i] = s_box[bitmapImage[i]];
}
//shift rows
unsigned char * p = bitmapImage;
for(i=0;i < size;i+=16)
{
shift_rows(p + i);
}
//mix columns
p = bitmapImage;
for(i=0;i < size;i+=16)
{
mix_columns(p + i);
}
//Add key
p = bitmapImage;
for(i=0;i < size;i+=16)
{
key_xor(p + i);
}
}
void decrypt(unsigned char *bitmapImage, int size, int key)
{
int i;
unsigned char * p = bitmapImage;
//Add key
for(i=0;i < size;i+=16)
{
key_xor(p + i);
}
//mix columns
p = bitmapImage;
for(i=0;i < size;i+=16)
{
inv_mix_columns(p + i);
}
//shift rows
p = bitmapImage;
for(i=0;i < size;i+=16)
{
inv_shift_rows(p + i);
}
//byte substitution
for(i=0;i < size;i++)
{
bitmapImage[i] = inv_s_box[bitmapImage[i]];
}
}
int main()
{
BITMAPINFOHEADER bitmapInfoHeader;
BITMAPFILEHEADER bitmapFileHeader;
unsigned char *bitmapData;
bitmapData = LoadBitmapFile("lena.bmp",&bitmapInfoHeader, &bitmapFileHeader);
printf("%d\n",bitmapInfoHeader.biSizeImage);
int key = 251;
hipEvent_t start;
hipEventCreate(&start);
hipEvent_t end;
hipEventCreate(&end);
float encryptionTime, decryptionTime;
//Encryption
hipEventRecord(start, 0);
encrypt(bitmapData, bitmapInfoHeader.biSizeImage, key);
hipEventRecord(end, 0);
hipEventSynchronize(end);
hipEventElapsedTime(&encryptionTime, start, end);
printf("Encryption Time: %fms\n",encryptionTime);
ReloadBitmapFile("encrypted.bmp", bitmapData, &bitmapFileHeader, &bitmapInfoHeader);
//load encrypted image to array
bitmapData = LoadBitmapFile("encrypted.bmp",&bitmapInfoHeader, &bitmapFileHeader);
//Decryption
hipEventRecord(start, 0);
decrypt(bitmapData, bitmapInfoHeader.biSizeImage, key);
hipEventRecord(end, 0);
hipEventSynchronize(end);
hipEventElapsedTime(&decryptionTime, start, end);
printf("Decryption Time: %fms\n",decryptionTime);
ReloadBitmapFile("Decrypted.bmp", bitmapData, &bitmapFileHeader, &bitmapInfoHeader);
hipEventDestroy(start);
hipEventDestroy(end);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
typedef short WORD;
typedef int DWORD;
typedef int LONG;
static unsigned char s_box[256] = {
// 0 1 2 3 4 5 6 7 8 9 a b c d e f
0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76, // 0
0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0, // 1
0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc, 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15, // 2
0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75, // 3
0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84, // 4
0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf, // 5
0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8, // 6
0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5, 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2, // 7
0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73, // 8
0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb, // 9
0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79, // a
0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9, 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08, // b
0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a, // c
0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e, // d
0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf, // e
0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16};// f
static unsigned char inv_s_box[256] = {
// 0 1 2 3 4 5 6 7 8 9 a b c d e f
0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38, 0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb, // 0
0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87, 0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb, // 1
0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d, 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e, // 2
0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2, 0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25, // 3
0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16, 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92, // 4
0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda, 0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84, // 5
0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a, 0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06, // 6
0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02, 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b, // 7
0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea, 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73, // 8
0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85, 0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e, // 9
0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89, 0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b, // a
0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20, 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4, // b
0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31, 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f, // c
0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d, 0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef, // d
0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0, 0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61, // e
0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26, 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d};// f
int Nb = 4;
void shift_rows(unsigned char *state) {
unsigned char i, k, s, tmp;
for (i = 1; i < 4; i++) {
s = 0;
while (s < i) {
tmp = state[Nb*i+0];
for (k = 1; k < Nb; k++) {
state[Nb*i+k-1] = state[Nb*i+k];
}
state[Nb*i+Nb-1] = tmp;
s++;
}
}
}
void inv_shift_rows(unsigned char *state) {
unsigned char i, k, s, tmp;
for (i = 1; i < 4; i++) {
s = 0;
while (s < i) {
tmp = state[Nb*i+Nb-1];
for (k = Nb-1; k > 0; k--) {
state[Nb*i+k] = state[Nb*i+k-1];
}
state[Nb*i+0] = tmp;
s++;
}
}
}
unsigned char gmult(unsigned char a, unsigned char b) {
unsigned char p = 0, i = 0, hbs = 0;
for (i = 0; i < 8; i++) {
if (b & 1) {
p ^= a;
}
hbs = a & 0x80;
a <<= 1;
if (hbs) a ^= 0x1b; // 0000 0001 0001 1011
b >>= 1;
}
return (unsigned char)p;
}
void coef_mult(unsigned char *a, unsigned char *b, unsigned char *d) {
d[0] = gmult(a[0],b[0])^gmult(a[3],b[1])^gmult(a[2],b[2])^gmult(a[1],b[3]);
d[1] = gmult(a[1],b[0])^gmult(a[0],b[1])^gmult(a[3],b[2])^gmult(a[2],b[3]);
d[2] = gmult(a[2],b[0])^gmult(a[1],b[1])^gmult(a[0],b[2])^gmult(a[3],b[3]);
d[3] = gmult(a[3],b[0])^gmult(a[2],b[1])^gmult(a[1],b[2])^gmult(a[0],b[3]);
}
void mix_columns(unsigned char *state) {
unsigned char a[] = {0x02, 0x01, 0x01, 0x03}; // a(x) = {02} + {01}x + {01}x2 + {03}x3
unsigned char i, j, col[4], res[4];
for (j = 0; j < Nb; j++) {
for (i = 0; i < 4; i++) {
col[i] = state[Nb*i+j];
}
coef_mult(a, col, res);
for (i = 0; i < 4; i++) {
state[Nb*i+j] = res[i];
}
}
}
void inv_mix_columns(unsigned char *state) {
unsigned char a[] = {0x0e, 0x09, 0x0d, 0x0b}; // a(x) = {0e} + {09}x + {0d}x2 + {0b}x3
unsigned char i, j, col[4], res[4];
for (j = 0; j < Nb; j++) {
for (i = 0; i < 4; i++) {
col[i] = state[Nb*i+j];
}
coef_mult(a, col, res);
for (i = 0; i < 4; i++) {
state[Nb*i+j] = res[i];
}
}
}
//Round Keys
unsigned char key[16] = {
0x00, 0x01, 0x02, 0x03,
0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0a, 0x0b,
0x0c, 0x0d, 0x0e, 0x0f};
void key_xor(unsigned char *state){
for(int i=0;i < 16;i++)
{
state[i] = state[i]^key[i];
}
}
#pragma pack(push, 1)
typedef struct tagBITMAPFILEHEADER
{
WORD bfType; //specifies the file type
DWORD bfSize; //specifies the size in bytes of the bitmap file
WORD bfReserved1; //reserved; must be 0
WORD bfReserved2; //reserved; must be 0
DWORD bOffBits; //species the offset in bytes from the bitmapfileheader to the bitmap bits
}BITMAPFILEHEADER;
#pragma pack(pop)
#pragma pack(push, 1)
typedef struct tagBITMAPINFOHEADER
{
DWORD biSize; //specifies the number of bytes required by the struct
LONG biWidth; //specifies width in pixels
LONG biHeight; //species height in pixels
WORD biPlanes; //specifies the number of color planes, must be 1
WORD biBitCount; //specifies the number of bit per pixel
DWORD biCompression;//spcifies the type of compression
DWORD biSizeImage; //size of image in bytes
LONG biXPelsPerMeter; //number of pixels per meter in x axis
LONG biYPelsPerMeter; //number of pixels per meter in y axis
DWORD biClrUsed; //number of colors used by th ebitmap
DWORD biClrImportant; //number of colors that are important
}BITMAPINFOHEADER;
#pragma pack(pop)
unsigned char *LoadBitmapFile(char *filename, BITMAPINFOHEADER *bitmapInfoHeader, BITMAPFILEHEADER *bitmapFileHeader)
{
FILE *filePtr; //our file pointer
unsigned char *bitmapImage; //store image data
int imageIdx=0; //image index counter
unsigned char tempRGB; //our swap variable
//open filename in read binary mode
filePtr = fopen(filename,"rb");
if (filePtr == NULL)
return NULL;
//read the bitmap file header
fread(bitmapFileHeader, sizeof(BITMAPFILEHEADER),1,filePtr);
//verify that this is a bmp file by check bitmap id
if (bitmapFileHeader->bfType !=0x4D42)
{
fclose(filePtr);
return NULL;
}
//read the bitmap info header
fread(bitmapInfoHeader, sizeof(BITMAPINFOHEADER),1,filePtr); // small edit. forgot to add the closing bracket at sizeof
//move file point to the begging of bitmap data
fseek(filePtr, bitmapFileHeader->bOffBits, SEEK_SET);
//allocate enough memory for the bitmap image data
bitmapImage = (unsigned char*)malloc(bitmapInfoHeader->biSizeImage);
//verify memory allocation
if (!bitmapImage)
{
free(bitmapImage);
fclose(filePtr);
return NULL;
}
//read in the bitmap image data
fread(bitmapImage,1,bitmapInfoHeader->biSizeImage,filePtr);
//make sure bitmap image data was read
if (bitmapImage == NULL)
{
fclose(filePtr);
return NULL;
}
hipEvent_t start;
hipEventCreate(&start);
hipEvent_t end;
hipEventCreate(&end);
float swapTime;
hipEventRecord(start, 0);
//swap the r and b values to get RGB (bitmap is BGR)
for (imageIdx = 0; imageIdx < bitmapInfoHeader->biSizeImage;imageIdx+=3)
{
tempRGB = bitmapImage[imageIdx];
bitmapImage[imageIdx] = bitmapImage[imageIdx + 2];
bitmapImage[imageIdx + 2] = tempRGB;
}
hipEventRecord(end, 0);
hipEventSynchronize(end);
hipEventElapsedTime(&swapTime, start, end);
printf("Load Swap Time: %fms\n",swapTime);
hipEventDestroy(start);
hipEventDestroy(end);
//close file and return bitmap iamge data
fclose(filePtr);
return bitmapImage;
}
void ReloadBitmapFile(char *filename, unsigned char *bitmapImage, BITMAPFILEHEADER *bitmapFileHeader, BITMAPINFOHEADER *bitmapInfoHeader)
{
FILE *filePtr; //our file pointer
int imageIdx=0; //image index counter
unsigned char tempRGB; //our swap variable
//open filename in write binary mode
filePtr = fopen(filename,"wb");
if (filePtr == NULL)
{
printf("\nERROR: Cannot open file %s", filename);
exit(1);
}
//write the bitmap file header
fwrite(bitmapFileHeader, sizeof(BITMAPFILEHEADER),1,filePtr);
//write the bitmap info header
fwrite(bitmapInfoHeader, sizeof(BITMAPINFOHEADER),1,filePtr); // small edit. forgot to add the closing bracket at sizeof
//swap the r and b values to get RGB (bitmap is BGR)
for (imageIdx = 0; imageIdx < bitmapInfoHeader->biSizeImage;imageIdx+=3)
{
tempRGB = bitmapImage[imageIdx];
bitmapImage[imageIdx] = bitmapImage[imageIdx + 2];
bitmapImage[imageIdx + 2] = tempRGB;
}
//write in the bitmap image data
fwrite(bitmapImage,bitmapInfoHeader->biSizeImage,1,filePtr);
//close file
fclose(filePtr);
}
void encrypt(unsigned char *bitmapImage, int size, int key)
{
int i;
//byte substitution
for(i=0;i < size;i++)
{
bitmapImage[i] = s_box[bitmapImage[i]];
}
//shift rows
unsigned char * p = bitmapImage;
for(i=0;i < size;i+=16)
{
shift_rows(p + i);
}
//mix columns
p = bitmapImage;
for(i=0;i < size;i+=16)
{
mix_columns(p + i);
}
//Add key
p = bitmapImage;
for(i=0;i < size;i+=16)
{
key_xor(p + i);
}
}
void decrypt(unsigned char *bitmapImage, int size, int key)
{
int i;
unsigned char * p = bitmapImage;
//Add key
for(i=0;i < size;i+=16)
{
key_xor(p + i);
}
//mix columns
p = bitmapImage;
for(i=0;i < size;i+=16)
{
inv_mix_columns(p + i);
}
//shift rows
p = bitmapImage;
for(i=0;i < size;i+=16)
{
inv_shift_rows(p + i);
}
//byte substitution
for(i=0;i < size;i++)
{
bitmapImage[i] = inv_s_box[bitmapImage[i]];
}
}
int main()
{
BITMAPINFOHEADER bitmapInfoHeader;
BITMAPFILEHEADER bitmapFileHeader;
unsigned char *bitmapData;
bitmapData = LoadBitmapFile("lena.bmp",&bitmapInfoHeader, &bitmapFileHeader);
printf("%d\n",bitmapInfoHeader.biSizeImage);
int key = 251;
hipEvent_t start;
hipEventCreate(&start);
hipEvent_t end;
hipEventCreate(&end);
float encryptionTime, decryptionTime;
//Encryption
hipEventRecord(start, 0);
encrypt(bitmapData, bitmapInfoHeader.biSizeImage, key);
hipEventRecord(end, 0);
hipEventSynchronize(end);
hipEventElapsedTime(&encryptionTime, start, end);
printf("Encryption Time: %fms\n",encryptionTime);
ReloadBitmapFile("encrypted.bmp", bitmapData, &bitmapFileHeader, &bitmapInfoHeader);
//load encrypted image to array
bitmapData = LoadBitmapFile("encrypted.bmp",&bitmapInfoHeader, &bitmapFileHeader);
//Decryption
hipEventRecord(start, 0);
decrypt(bitmapData, bitmapInfoHeader.biSizeImage, key);
hipEventRecord(end, 0);
hipEventSynchronize(end);
hipEventElapsedTime(&decryptionTime, start, end);
printf("Decryption Time: %fms\n",decryptionTime);
ReloadBitmapFile("Decrypted.bmp", bitmapData, &bitmapFileHeader, &bitmapInfoHeader);
hipEventDestroy(start);
hipEventDestroy(end);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* AsmTest.cu
*
* Created on: May 18, 2014
* Author: reid
*/
__forceinline__ __device__ float2 add(float2 a, float2 b)
{
float2 c;
c.x = a.x + b.x;
c.y = a.y + b.y;
return c;
}
__device__ float2 sub(float2 a, float2 b)
{
float2 c;
c.x = a.x - b.x;
c.y = a.y - b.y;
return c;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* AsmTest.cu
*
* Created on: May 18, 2014
* Author: reid
*/
__forceinline__ __device__ float2 add(float2 a, float2 b)
{
float2 c;
c.x = a.x + b.x;
c.y = a.y + b.y;
return c;
}
__device__ float2 sub(float2 a, float2 b)
{
float2 c;
c.x = a.x - b.x;
c.y = a.y - b.y;
return c;
} | .file "tmpxft_001b8868_00000000-6_AsmTest.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3sub6float2S_
.type _Z3sub6float2S_, @function
_Z3sub6float2S_:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z3sub6float2S_, .-_Z3sub6float2S_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* AsmTest.cu
*
* Created on: May 18, 2014
* Author: reid
*/
__forceinline__ __device__ float2 add(float2 a, float2 b)
{
float2 c;
c.x = a.x + b.x;
c.y = a.y + b.y;
return c;
}
__device__ float2 sub(float2 a, float2 b)
{
float2 c;
c.x = a.x - b.x;
c.y = a.y - b.y;
return c;
} | #include <hip/hip_runtime.h>
/*
* AsmTest.cu
*
* Created on: May 18, 2014
* Author: reid
*/
__forceinline__ __device__ float2 add(float2 a, float2 b)
{
float2 c;
c.x = a.x + b.x;
c.y = a.y + b.y;
return c;
}
__device__ float2 sub(float2 a, float2 b)
{
float2 c;
c.x = a.x - b.x;
c.y = a.y - b.y;
return c;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*
* AsmTest.cu
*
* Created on: May 18, 2014
* Author: reid
*/
__forceinline__ __device__ float2 add(float2 a, float2 b)
{
float2 c;
c.x = a.x + b.x;
c.y = a.y + b.y;
return c;
}
__device__ float2 sub(float2 a, float2 b)
{
float2 c;
c.x = a.x - b.x;
c.y = a.y - b.y;
return c;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*
* AsmTest.cu
*
* Created on: May 18, 2014
* Author: reid
*/
__forceinline__ __device__ float2 add(float2 a, float2 b)
{
float2 c;
c.x = a.x + b.x;
c.y = a.y + b.y;
return c;
}
__device__ float2 sub(float2 a, float2 b)
{
float2 c;
c.x = a.x - b.x;
c.y = a.y - b.y;
return c;
} | .text
.file "AsmTest.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b8868_00000000-6_AsmTest.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3sub6float2S_
.type _Z3sub6float2S_, @function
_Z3sub6float2S_:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z3sub6float2S_, .-_Z3sub6float2S_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "AsmTest.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#define STR_NUM 1024
#define RUN_COUNT 1
__global__ void func(char *buf)
{
int idx = gridDim.x*blockIdx.x;
buf[idx ] = 'A';
buf[idx+1] = 'B';
buf[idx+2] = 'C';
buf[idx+3] = 'D';
buf[idx+4] = 'E';
buf[idx+5] = 'F';
buf[idx+6] = 'G';
buf[idx+7] = 'H';
buf[idx+8] = 'I';
buf[idx+9] = 'J';
}
int main()
{
int i;
size_t buf_size = STR_NUM*10*sizeof(char);
char *h_buf, *d_buf;
cudaSetDevice(0);
for(i=0; i<RUN_COUNT; i++)
{
h_buf = (char*)malloc(buf_size);
cudaMalloc( (void**)&d_buf, buf_size );
func<<<STR_NUM, 10>>>(d_buf);
cudaMemcpy( h_buf, d_buf, buf_size, cudaMemcpyDeviceToHost );
free(h_buf);
cudaFree( d_buf );
}
return 0;
} | code for sm_80
Function : _Z4funcPc
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR5, c[0x0][0xc] ; /* 0x0000030000057ab9 */
/* 0x000fe20000000800 */
/*0030*/ HFMA2.MMA R4, -RZ, RZ, 0, 3.93390655517578125e-06 ; /* 0x00000042ff047435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0050*/ HFMA2.MMA R10, -RZ, RZ, 0, 4.291534423828125e-06 ; /* 0x00000048ff0a7435 */
/* 0x000fe200000001ff */
/*0060*/ IMAD.MOV.U32 R0, RZ, RZ, 0x41 ; /* 0x00000041ff007424 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R12, 0x4a ; /* 0x0000004a000c7802 */
/* 0x000fe20000000f00 */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, 0x43 ; /* 0x00000043ff057424 */
/* 0x000fe200078e00ff */
/*0090*/ HFMA2.MMA R6, -RZ, RZ, 0, 4.0531158447265625e-06 ; /* 0x00000044ff067435 */
/* 0x000fe200000001ff */
/*00a0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x47 ; /* 0x00000047ff097424 */
/* 0x000fe200078e00ff */
/*00b0*/ MOV R8, 0x46 ; /* 0x0000004600087802 */
/* 0x000fe20000000f00 */
/*00c0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x49 ; /* 0x00000049ff0b7424 */
/* 0x000fc400078e00ff */
/*00d0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x45 ; /* 0x00000045ff077424 */
/* 0x000fe200078e00ff */
/*00e0*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x001fc8000f8e023f */
/*00f0*/ UIADD3 UR5, UP0, UR4, UR6, URZ ; /* 0x0000000604057290 */
/* 0x000fc8000ff1e03f */
/*0100*/ ULEA.HI.X.SX32 UR4, UR4, UR7, 0x1, UP0 ; /* 0x0000000704047291 */
/* 0x000fe400080f0e3f */
/*0110*/ IMAD.U32 R2, RZ, RZ, UR5 ; /* 0x00000005ff027e24 */
/* 0x000fc8000f8e00ff */
/*0120*/ MOV R3, UR4 ; /* 0x0000000400037c02 */
/* 0x000fe20008000f00 */
/*0130*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0140*/ STG.E.U8 [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x0001e8000c101104 */
/*0150*/ STG.E.U8 [R2.64+0x1], R4 ; /* 0x0000010402007986 */
/* 0x0003e8000c101104 */
/*0160*/ STG.E.U8 [R2.64+0x2], R5 ; /* 0x0000020502007986 */
/* 0x0005e2000c101104 */
/*0170*/ PRMT R0, R9, 0x7610, R0 ; /* 0x0000761009007816 */
/* 0x001fc60000000000 */
/*0180*/ STG.E.U8 [R2.64+0x3], R6 ; /* 0x0000030602007986 */
/* 0x000fe2000c101104 */
/*0190*/ PRMT R9, R11, 0x7610, R9 ; /* 0x000076100b097816 */
/* 0x000fe40000000009 */
/*01a0*/ PRMT R4, R10, 0x7610, R4 ; /* 0x000076100a047816 */
/* 0x002fe20000000004 */
/*01b0*/ STG.E.U8 [R2.64+0x4], R7 ; /* 0x0000040702007986 */
/* 0x000fe2000c101104 */
/*01c0*/ PRMT R5, R12, 0x7610, R5 ; /* 0x000076100c057816 */
/* 0x004fc60000000005 */
/*01d0*/ STG.E.U8 [R2.64+0x5], R8 ; /* 0x0000050802007986 */
/* 0x000fe8000c101104 */
/*01e0*/ STG.E.U8 [R2.64+0x6], R0 ; /* 0x0000060002007986 */
/* 0x000fe8000c101104 */
/*01f0*/ STG.E.U8 [R2.64+0x7], R4 ; /* 0x0000070402007986 */
/* 0x000fe8000c101104 */
/*0200*/ STG.E.U8 [R2.64+0x8], R9 ; /* 0x0000080902007986 */
/* 0x000fe8000c101104 */
/*0210*/ STG.E.U8 [R2.64+0x9], R5 ; /* 0x0000090502007986 */
/* 0x000fe2000c101104 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define STR_NUM 1024
#define RUN_COUNT 1
__global__ void func(char *buf)
{
int idx = gridDim.x*blockIdx.x;
buf[idx ] = 'A';
buf[idx+1] = 'B';
buf[idx+2] = 'C';
buf[idx+3] = 'D';
buf[idx+4] = 'E';
buf[idx+5] = 'F';
buf[idx+6] = 'G';
buf[idx+7] = 'H';
buf[idx+8] = 'I';
buf[idx+9] = 'J';
}
int main()
{
int i;
size_t buf_size = STR_NUM*10*sizeof(char);
char *h_buf, *d_buf;
cudaSetDevice(0);
for(i=0; i<RUN_COUNT; i++)
{
h_buf = (char*)malloc(buf_size);
cudaMalloc( (void**)&d_buf, buf_size );
func<<<STR_NUM, 10>>>(d_buf);
cudaMemcpy( h_buf, d_buf, buf_size, cudaMemcpyDeviceToHost );
free(h_buf);
cudaFree( d_buf );
}
return 0;
} | .file "tmpxft_00091e05_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z4funcPcPc
.type _Z23__device_stub__Z4funcPcPc, @function
_Z23__device_stub__Z4funcPcPc:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4funcPc(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z23__device_stub__Z4funcPcPc, .-_Z23__device_stub__Z4funcPcPc
.globl _Z4funcPc
.type _Z4funcPc, @function
_Z4funcPc:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z4funcPcPc
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4funcPc, .-_Z4funcPc
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
movl $10240, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $10240, %esi
call cudaMalloc@PLT
movl $10, 28(%rsp)
movl $1, 32(%rsp)
movl $1024, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movl $10240, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z23__device_stub__Z4funcPcPc
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4funcPc"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4funcPc(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define STR_NUM 1024
#define RUN_COUNT 1
__global__ void func(char *buf)
{
int idx = gridDim.x*blockIdx.x;
buf[idx ] = 'A';
buf[idx+1] = 'B';
buf[idx+2] = 'C';
buf[idx+3] = 'D';
buf[idx+4] = 'E';
buf[idx+5] = 'F';
buf[idx+6] = 'G';
buf[idx+7] = 'H';
buf[idx+8] = 'I';
buf[idx+9] = 'J';
}
int main()
{
int i;
size_t buf_size = STR_NUM*10*sizeof(char);
char *h_buf, *d_buf;
cudaSetDevice(0);
for(i=0; i<RUN_COUNT; i++)
{
h_buf = (char*)malloc(buf_size);
cudaMalloc( (void**)&d_buf, buf_size );
func<<<STR_NUM, 10>>>(d_buf);
cudaMemcpy( h_buf, d_buf, buf_size, cudaMemcpyDeviceToHost );
free(h_buf);
cudaFree( d_buf );
}
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define STR_NUM 1024
#define RUN_COUNT 1
__global__ void func(char *buf)
{
int idx = gridDim.x*blockIdx.x;
buf[idx ] = 'A';
buf[idx+1] = 'B';
buf[idx+2] = 'C';
buf[idx+3] = 'D';
buf[idx+4] = 'E';
buf[idx+5] = 'F';
buf[idx+6] = 'G';
buf[idx+7] = 'H';
buf[idx+8] = 'I';
buf[idx+9] = 'J';
}
int main()
{
int i;
size_t buf_size = STR_NUM*10*sizeof(char);
char *h_buf, *d_buf;
hipSetDevice(0);
for(i=0; i<RUN_COUNT; i++)
{
h_buf = (char*)malloc(buf_size);
hipMalloc( (void**)&d_buf, buf_size );
func<<<STR_NUM, 10>>>(d_buf);
hipMemcpy( h_buf, d_buf, buf_size, hipMemcpyDeviceToHost );
free(h_buf);
hipFree( d_buf );
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define STR_NUM 1024
#define RUN_COUNT 1
__global__ void func(char *buf)
{
int idx = gridDim.x*blockIdx.x;
buf[idx ] = 'A';
buf[idx+1] = 'B';
buf[idx+2] = 'C';
buf[idx+3] = 'D';
buf[idx+4] = 'E';
buf[idx+5] = 'F';
buf[idx+6] = 'G';
buf[idx+7] = 'H';
buf[idx+8] = 'I';
buf[idx+9] = 'J';
}
int main()
{
int i;
size_t buf_size = STR_NUM*10*sizeof(char);
char *h_buf, *d_buf;
hipSetDevice(0);
for(i=0; i<RUN_COUNT; i++)
{
h_buf = (char*)malloc(buf_size);
hipMalloc( (void**)&d_buf, buf_size );
func<<<STR_NUM, 10>>>(d_buf);
hipMemcpy( h_buf, d_buf, buf_size, hipMemcpyDeviceToHost );
free(h_buf);
hipFree( d_buf );
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4funcPc
.globl _Z4funcPc
.p2align 8
.type _Z4funcPc,@function
_Z4funcPc:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, 0x48474645
v_mov_b32_e32 v0, 0x44434241
v_mov_b32_e32 v3, 0x4a49
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s3, s2, 31
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_clause 0x1
global_store_b64 v2, v[0:1], s[0:1]
global_store_b16 v2, v3, s[0:1] offset:8
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4funcPc
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4funcPc, .Lfunc_end0-_Z4funcPc
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4funcPc
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z4funcPc.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define STR_NUM 1024
#define RUN_COUNT 1
__global__ void func(char *buf)
{
int idx = gridDim.x*blockIdx.x;
buf[idx ] = 'A';
buf[idx+1] = 'B';
buf[idx+2] = 'C';
buf[idx+3] = 'D';
buf[idx+4] = 'E';
buf[idx+5] = 'F';
buf[idx+6] = 'G';
buf[idx+7] = 'H';
buf[idx+8] = 'I';
buf[idx+9] = 'J';
}
int main()
{
int i;
size_t buf_size = STR_NUM*10*sizeof(char);
char *h_buf, *d_buf;
hipSetDevice(0);
for(i=0; i<RUN_COUNT; i++)
{
h_buf = (char*)malloc(buf_size);
hipMalloc( (void**)&d_buf, buf_size );
func<<<STR_NUM, 10>>>(d_buf);
hipMemcpy( h_buf, d_buf, buf_size, hipMemcpyDeviceToHost );
free(h_buf);
hipFree( d_buf );
}
return 0;
} | .text
.file "main.hip"
.globl _Z19__device_stub__funcPc # -- Begin function _Z19__device_stub__funcPc
.p2align 4, 0x90
.type _Z19__device_stub__funcPc,@function
_Z19__device_stub__funcPc: # @_Z19__device_stub__funcPc
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z4funcPc, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z19__device_stub__funcPc, .Lfunc_end0-_Z19__device_stub__funcPc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %.critedge
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
xorl %edi, %edi
callq hipSetDevice
movl $10240, %edi # imm = 0x2800
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $10240, %esi # imm = 0x2800
callq hipMalloc
movabsq $4294967306, %rdx # imm = 0x10000000A
leaq 1014(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z4funcPc, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movl $10240, %edx # imm = 0x2800
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4funcPc, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4funcPc,@object # @_Z4funcPc
.section .rodata,"a",@progbits
.globl _Z4funcPc
.p2align 3, 0x0
_Z4funcPc:
.quad _Z19__device_stub__funcPc
.size _Z4funcPc, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4funcPc"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__funcPc
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4funcPc
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4funcPc
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR5, c[0x0][0xc] ; /* 0x0000030000057ab9 */
/* 0x000fe20000000800 */
/*0030*/ HFMA2.MMA R4, -RZ, RZ, 0, 3.93390655517578125e-06 ; /* 0x00000042ff047435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0050*/ HFMA2.MMA R10, -RZ, RZ, 0, 4.291534423828125e-06 ; /* 0x00000048ff0a7435 */
/* 0x000fe200000001ff */
/*0060*/ IMAD.MOV.U32 R0, RZ, RZ, 0x41 ; /* 0x00000041ff007424 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R12, 0x4a ; /* 0x0000004a000c7802 */
/* 0x000fe20000000f00 */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, 0x43 ; /* 0x00000043ff057424 */
/* 0x000fe200078e00ff */
/*0090*/ HFMA2.MMA R6, -RZ, RZ, 0, 4.0531158447265625e-06 ; /* 0x00000044ff067435 */
/* 0x000fe200000001ff */
/*00a0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x47 ; /* 0x00000047ff097424 */
/* 0x000fe200078e00ff */
/*00b0*/ MOV R8, 0x46 ; /* 0x0000004600087802 */
/* 0x000fe20000000f00 */
/*00c0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x49 ; /* 0x00000049ff0b7424 */
/* 0x000fc400078e00ff */
/*00d0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x45 ; /* 0x00000045ff077424 */
/* 0x000fe200078e00ff */
/*00e0*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x001fc8000f8e023f */
/*00f0*/ UIADD3 UR5, UP0, UR4, UR6, URZ ; /* 0x0000000604057290 */
/* 0x000fc8000ff1e03f */
/*0100*/ ULEA.HI.X.SX32 UR4, UR4, UR7, 0x1, UP0 ; /* 0x0000000704047291 */
/* 0x000fe400080f0e3f */
/*0110*/ IMAD.U32 R2, RZ, RZ, UR5 ; /* 0x00000005ff027e24 */
/* 0x000fc8000f8e00ff */
/*0120*/ MOV R3, UR4 ; /* 0x0000000400037c02 */
/* 0x000fe20008000f00 */
/*0130*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0140*/ STG.E.U8 [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x0001e8000c101104 */
/*0150*/ STG.E.U8 [R2.64+0x1], R4 ; /* 0x0000010402007986 */
/* 0x0003e8000c101104 */
/*0160*/ STG.E.U8 [R2.64+0x2], R5 ; /* 0x0000020502007986 */
/* 0x0005e2000c101104 */
/*0170*/ PRMT R0, R9, 0x7610, R0 ; /* 0x0000761009007816 */
/* 0x001fc60000000000 */
/*0180*/ STG.E.U8 [R2.64+0x3], R6 ; /* 0x0000030602007986 */
/* 0x000fe2000c101104 */
/*0190*/ PRMT R9, R11, 0x7610, R9 ; /* 0x000076100b097816 */
/* 0x000fe40000000009 */
/*01a0*/ PRMT R4, R10, 0x7610, R4 ; /* 0x000076100a047816 */
/* 0x002fe20000000004 */
/*01b0*/ STG.E.U8 [R2.64+0x4], R7 ; /* 0x0000040702007986 */
/* 0x000fe2000c101104 */
/*01c0*/ PRMT R5, R12, 0x7610, R5 ; /* 0x000076100c057816 */
/* 0x004fc60000000005 */
/*01d0*/ STG.E.U8 [R2.64+0x5], R8 ; /* 0x0000050802007986 */
/* 0x000fe8000c101104 */
/*01e0*/ STG.E.U8 [R2.64+0x6], R0 ; /* 0x0000060002007986 */
/* 0x000fe8000c101104 */
/*01f0*/ STG.E.U8 [R2.64+0x7], R4 ; /* 0x0000070402007986 */
/* 0x000fe8000c101104 */
/*0200*/ STG.E.U8 [R2.64+0x8], R9 ; /* 0x0000080902007986 */
/* 0x000fe8000c101104 */
/*0210*/ STG.E.U8 [R2.64+0x9], R5 ; /* 0x0000090502007986 */
/* 0x000fe2000c101104 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4funcPc
.globl _Z4funcPc
.p2align 8
.type _Z4funcPc,@function
_Z4funcPc:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, 0x48474645
v_mov_b32_e32 v0, 0x44434241
v_mov_b32_e32 v3, 0x4a49
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s3, s2, 31
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_clause 0x1
global_store_b64 v2, v[0:1], s[0:1]
global_store_b16 v2, v3, s[0:1] offset:8
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4funcPc
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4funcPc, .Lfunc_end0-_Z4funcPc
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4funcPc
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z4funcPc.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00091e05_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z4funcPcPc
.type _Z23__device_stub__Z4funcPcPc, @function
_Z23__device_stub__Z4funcPcPc:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4funcPc(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z23__device_stub__Z4funcPcPc, .-_Z23__device_stub__Z4funcPcPc
.globl _Z4funcPc
.type _Z4funcPc, @function
_Z4funcPc:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z4funcPcPc
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4funcPc, .-_Z4funcPc
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
movl $10240, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $10240, %esi
call cudaMalloc@PLT
movl $10, 28(%rsp)
movl $1, 32(%rsp)
movl $1024, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movl $10240, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z23__device_stub__Z4funcPcPc
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4funcPc"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4funcPc(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z19__device_stub__funcPc # -- Begin function _Z19__device_stub__funcPc
.p2align 4, 0x90
.type _Z19__device_stub__funcPc,@function
_Z19__device_stub__funcPc: # @_Z19__device_stub__funcPc
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z4funcPc, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z19__device_stub__funcPc, .Lfunc_end0-_Z19__device_stub__funcPc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %.critedge
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
xorl %edi, %edi
callq hipSetDevice
movl $10240, %edi # imm = 0x2800
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $10240, %esi # imm = 0x2800
callq hipMalloc
movabsq $4294967306, %rdx # imm = 0x10000000A
leaq 1014(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z4funcPc, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movl $10240, %edx # imm = 0x2800
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4funcPc, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4funcPc,@object # @_Z4funcPc
.section .rodata,"a",@progbits
.globl _Z4funcPc
.p2align 3, 0x0
_Z4funcPc:
.quad _Z19__device_stub__funcPc
.size _Z4funcPc, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4funcPc"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__funcPc
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4funcPc
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define BLOCK_WIDTH 32
//#define BLOCK_HEIGHT 32
#define BLOCK_HEIGHT 16
#define TILE_WIDTH 96
//#define TILE_HEIGHT 96
#define TILE_HEIGHT 48
#define SMALL_TILE_WIDTH 64
//#define SMALL_TILE_HEIGHT 64
#define SMALL_TILE_HEIGHT 32
__global__ void superResolutionKernel(float* o_arr1d, float* i_arr1d, int rows, int cols) {
__shared__ float tile[TILE_HEIGHT][TILE_WIDTH];
__shared__ float buf[SMALL_TILE_HEIGHT][TILE_WIDTH]; // buffer for down/up sampling
__shared__ float small_tile[SMALL_TILE_HEIGHT][SMALL_TILE_WIDTH];
int tx = threadIdx.x;
int ty = threadIdx.y;
for(int offset_y = 0; offset_y < TILE_HEIGHT; offset_y += BLOCK_HEIGHT) {
for(int offset_x = 0; offset_x < TILE_WIDTH; offset_x += BLOCK_WIDTH) {
int xidx = blockIdx.x * TILE_WIDTH + offset_x + tx;
int yidx = blockIdx.y * TILE_HEIGHT + offset_y + ty;
tile[offset_y + ty][offset_x + tx] = i_arr1d[yidx * cols + xidx];
}
}
__syncthreads();
// col downsample: (TILE_HEIGHT, TILE_WIDTH) -> (SMALL_TILE_HEIGHT, TILE_WIDTH)
for(int offset_x = 0; offset_x < TILE_WIDTH; offset_x += BLOCK_WIDTH) {
buf[2*ty][offset_x + tx] = -0.022 * tile[3*ty][offset_x + tx] + 0.974 * tile[3*ty+1][offset_x + tx] + 0.227 * tile[3*ty+2][offset_x + tx];
buf[2*ty+1][offset_x + tx] = 0.227 * tile[3*ty][offset_x + tx] + 0.974 * tile[3*ty+1][offset_x + tx] + -0.022 * tile[3*ty+2][offset_x + tx];
}
__syncthreads();
// row downsample: (SMALL_TILE_HEIGHT, TILE_WIDTH) -> (SMALL_TILE_HEIGHT, SMALL_TILE_WIDTH)
for(int offset_y = 0; offset_y < SMALL_TILE_HEIGHT; offset_y += BLOCK_HEIGHT) {
small_tile[offset_y + ty][2*tx] = -0.022 * buf[offset_y + ty][3*tx] + 0.974 * buf[offset_y + ty][3*tx+1] + 0.227 * buf[offset_y + ty][3*tx+2];
small_tile[offset_y + ty][2*tx+1] = 0.227 * buf[offset_y + ty][3*tx] + 0.974 * buf[offset_y + ty][3*tx+1] + -0.022 * buf[offset_y + ty][3*tx+2];
}
__syncthreads();
// row upsample: (SMALL_TILE_HEIGHT, SMALL_TILE_WIDTH) -> (SMALL_TILE_HEIGHT, TILE_WIDTH)
for(int offset_y = 0; offset_y < SMALL_TILE_HEIGHT; offset_y += BLOCK_HEIGHT) {
// 3*tx
if(tx == 0)
buf[offset_y + ty][0] = 0.927 * small_tile[offset_y + ty][0] + -0.047 * small_tile[offset_y + ty][1];
else
buf[offset_y + ty][3*tx] = 0.119 * small_tile[offset_y + ty][2*tx-1] + 0.927 * small_tile[offset_y + ty][2*tx]
+ -0.047 * small_tile[offset_y + ty][2*tx+1];
// 3*tx+2
if(tx == BLOCK_WIDTH-1)
buf[offset_y + ty][TILE_WIDTH-1] = -0.047 * small_tile[offset_y + ty][SMALL_TILE_WIDTH-2] + 0.927 * small_tile[offset_y + ty][SMALL_TILE_WIDTH-1];
else
buf[offset_y + ty][3*tx+2] = -0.047 * small_tile[offset_y + ty][2*tx] + 0.927 * small_tile[offset_y + ty][2*tx+1]
+ 0.119 * small_tile[offset_y + ty][2*tx+2];
// 3*tx+1
if(tx == 0)
buf[offset_y + ty][1] = 0.6 * small_tile[offset_y + ty][0] + 0.6 * small_tile[offset_y + ty][1] + -0.1 * small_tile[offset_y + ty][2];
else if(tx == BLOCK_WIDTH-1)
buf[offset_y + ty][TILE_WIDTH-2] = -0.1 * small_tile[offset_y + ty][SMALL_TILE_WIDTH-3] + 0.6 * small_tile[offset_y + ty][SMALL_TILE_WIDTH-2]
+ 0.6 * small_tile[offset_y + ty][SMALL_TILE_WIDTH-1];
else
buf[offset_y + ty][3*tx+1] = -0.1 * small_tile[offset_y + ty][2*tx-1] + 0.6 * small_tile[offset_y + ty][2*tx]
+ 0.6 * small_tile[offset_y + ty][2*tx+1] + -0.1 * small_tile[offset_y + ty][2*tx+2];
}
__syncthreads();
// col upsample: (SMALL_TILE_HEIGHT, TILE_WIDTH) -> (TILE_HEIGHT, TILE_WIDTH)
for(int offset_x = 0; offset_x < TILE_WIDTH; offset_x += BLOCK_WIDTH) {
int xidx = blockIdx.x * TILE_WIDTH + offset_x + tx;
// 3*ty
if(ty == 0) {
int yidx = blockIdx.y * TILE_HEIGHT;
o_arr1d[yidx * cols + xidx] = 0.927 * buf[0][offset_x + tx] + -0.047 * buf[1][offset_x + tx];
}
else {
int yidx = blockIdx.y * TILE_HEIGHT + 3*ty;
o_arr1d[yidx * cols + xidx] = 0.119 * buf[2*tx-1][offset_x + tx] + 0.927 * buf[2*tx][offset_x + tx]
+ -0.047 * buf[2*tx+1][offset_x + tx];
}
// 3*ty+2
if(ty == BLOCK_HEIGHT-1) {
int yidx = blockIdx.y * TILE_HEIGHT + TILE_HEIGHT-1;
o_arr1d[yidx * cols + xidx] = -0.047 * buf[SMALL_TILE_HEIGHT-2][offset_x + tx] + 0.927 * buf[SMALL_TILE_HEIGHT-1][offset_x + tx];
}
else {
int yidx = blockIdx.y * TILE_HEIGHT + 3*ty+2;
o_arr1d[yidx * cols + xidx] = -0.047 * buf[2*ty][offset_x + tx] + 0.927 * buf[2*ty+1][offset_x + tx]
+ 0.119 * small_tile[2*ty+2][offset_x + tx];
}
// 3*ty+1
if(ty == 0) {
int yidx = blockIdx.y * TILE_HEIGHT + 1;
o_arr1d[yidx * cols + xidx] = 0.6 * buf[0][offset_x + tx] + 0.6 * buf[1][offset_x + tx] + -0.1 * buf[2][offset_x + tx];
}
else if(ty == BLOCK_HEIGHT-1) {
int yidx = blockIdx.y * TILE_HEIGHT + TILE_HEIGHT-2;
o_arr1d[yidx * cols + xidx] = -0.1 * buf[SMALL_TILE_HEIGHT-3][offset_x + tx] + 0.6 * buf[SMALL_TILE_HEIGHT-2][offset_x + tx]
+ 0.6 * buf[SMALL_TILE_HEIGHT-1][offset_x + tx];
}
else {
int yidx = blockIdx.y * TILE_HEIGHT + 3*ty+1;
o_arr1d[yidx * cols + xidx] = -0.1 * buf[2*ty-1][offset_x + tx] + 0.6 * buf[2*ty][offset_x + tx]
+ 0.6 * buf[2*ty+1][offset_x + tx] + -0.1 * buf[2*ty+2][offset_x + tx];
}
}
} | .file "tmpxft_00070e1f_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z21superResolutionKernelPfS_iiPfS_ii
.type _Z45__device_stub__Z21superResolutionKernelPfS_iiPfS_ii, @function
_Z45__device_stub__Z21superResolutionKernelPfS_iiPfS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21superResolutionKernelPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z21superResolutionKernelPfS_iiPfS_ii, .-_Z45__device_stub__Z21superResolutionKernelPfS_iiPfS_ii
.globl _Z21superResolutionKernelPfS_ii
.type _Z21superResolutionKernelPfS_ii, @function
_Z21superResolutionKernelPfS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z21superResolutionKernelPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z21superResolutionKernelPfS_ii, .-_Z21superResolutionKernelPfS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z21superResolutionKernelPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21superResolutionKernelPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define BLOCK_WIDTH 32
//#define BLOCK_HEIGHT 32
#define BLOCK_HEIGHT 16
#define TILE_WIDTH 96
//#define TILE_HEIGHT 96
#define TILE_HEIGHT 48
#define SMALL_TILE_WIDTH 64
//#define SMALL_TILE_HEIGHT 64
#define SMALL_TILE_HEIGHT 32
__global__ void superResolutionKernel(float* o_arr1d, float* i_arr1d, int rows, int cols) {
__shared__ float tile[TILE_HEIGHT][TILE_WIDTH];
__shared__ float buf[SMALL_TILE_HEIGHT][TILE_WIDTH]; // buffer for down/up sampling
__shared__ float small_tile[SMALL_TILE_HEIGHT][SMALL_TILE_WIDTH];
int tx = threadIdx.x;
int ty = threadIdx.y;
for(int offset_y = 0; offset_y < TILE_HEIGHT; offset_y += BLOCK_HEIGHT) {
for(int offset_x = 0; offset_x < TILE_WIDTH; offset_x += BLOCK_WIDTH) {
int xidx = blockIdx.x * TILE_WIDTH + offset_x + tx;
int yidx = blockIdx.y * TILE_HEIGHT + offset_y + ty;
tile[offset_y + ty][offset_x + tx] = i_arr1d[yidx * cols + xidx];
}
}
__syncthreads();
// col downsample: (TILE_HEIGHT, TILE_WIDTH) -> (SMALL_TILE_HEIGHT, TILE_WIDTH)
for(int offset_x = 0; offset_x < TILE_WIDTH; offset_x += BLOCK_WIDTH) {
buf[2*ty][offset_x + tx] = -0.022 * tile[3*ty][offset_x + tx] + 0.974 * tile[3*ty+1][offset_x + tx] + 0.227 * tile[3*ty+2][offset_x + tx];
buf[2*ty+1][offset_x + tx] = 0.227 * tile[3*ty][offset_x + tx] + 0.974 * tile[3*ty+1][offset_x + tx] + -0.022 * tile[3*ty+2][offset_x + tx];
}
__syncthreads();
// row downsample: (SMALL_TILE_HEIGHT, TILE_WIDTH) -> (SMALL_TILE_HEIGHT, SMALL_TILE_WIDTH)
for(int offset_y = 0; offset_y < SMALL_TILE_HEIGHT; offset_y += BLOCK_HEIGHT) {
small_tile[offset_y + ty][2*tx] = -0.022 * buf[offset_y + ty][3*tx] + 0.974 * buf[offset_y + ty][3*tx+1] + 0.227 * buf[offset_y + ty][3*tx+2];
small_tile[offset_y + ty][2*tx+1] = 0.227 * buf[offset_y + ty][3*tx] + 0.974 * buf[offset_y + ty][3*tx+1] + -0.022 * buf[offset_y + ty][3*tx+2];
}
__syncthreads();
// row upsample: (SMALL_TILE_HEIGHT, SMALL_TILE_WIDTH) -> (SMALL_TILE_HEIGHT, TILE_WIDTH)
for(int offset_y = 0; offset_y < SMALL_TILE_HEIGHT; offset_y += BLOCK_HEIGHT) {
// 3*tx
if(tx == 0)
buf[offset_y + ty][0] = 0.927 * small_tile[offset_y + ty][0] + -0.047 * small_tile[offset_y + ty][1];
else
buf[offset_y + ty][3*tx] = 0.119 * small_tile[offset_y + ty][2*tx-1] + 0.927 * small_tile[offset_y + ty][2*tx]
+ -0.047 * small_tile[offset_y + ty][2*tx+1];
// 3*tx+2
if(tx == BLOCK_WIDTH-1)
buf[offset_y + ty][TILE_WIDTH-1] = -0.047 * small_tile[offset_y + ty][SMALL_TILE_WIDTH-2] + 0.927 * small_tile[offset_y + ty][SMALL_TILE_WIDTH-1];
else
buf[offset_y + ty][3*tx+2] = -0.047 * small_tile[offset_y + ty][2*tx] + 0.927 * small_tile[offset_y + ty][2*tx+1]
+ 0.119 * small_tile[offset_y + ty][2*tx+2];
// 3*tx+1
if(tx == 0)
buf[offset_y + ty][1] = 0.6 * small_tile[offset_y + ty][0] + 0.6 * small_tile[offset_y + ty][1] + -0.1 * small_tile[offset_y + ty][2];
else if(tx == BLOCK_WIDTH-1)
buf[offset_y + ty][TILE_WIDTH-2] = -0.1 * small_tile[offset_y + ty][SMALL_TILE_WIDTH-3] + 0.6 * small_tile[offset_y + ty][SMALL_TILE_WIDTH-2]
+ 0.6 * small_tile[offset_y + ty][SMALL_TILE_WIDTH-1];
else
buf[offset_y + ty][3*tx+1] = -0.1 * small_tile[offset_y + ty][2*tx-1] + 0.6 * small_tile[offset_y + ty][2*tx]
+ 0.6 * small_tile[offset_y + ty][2*tx+1] + -0.1 * small_tile[offset_y + ty][2*tx+2];
}
__syncthreads();
// col upsample: (SMALL_TILE_HEIGHT, TILE_WIDTH) -> (TILE_HEIGHT, TILE_WIDTH)
for(int offset_x = 0; offset_x < TILE_WIDTH; offset_x += BLOCK_WIDTH) {
int xidx = blockIdx.x * TILE_WIDTH + offset_x + tx;
// 3*ty
if(ty == 0) {
int yidx = blockIdx.y * TILE_HEIGHT;
o_arr1d[yidx * cols + xidx] = 0.927 * buf[0][offset_x + tx] + -0.047 * buf[1][offset_x + tx];
}
else {
int yidx = blockIdx.y * TILE_HEIGHT + 3*ty;
o_arr1d[yidx * cols + xidx] = 0.119 * buf[2*tx-1][offset_x + tx] + 0.927 * buf[2*tx][offset_x + tx]
+ -0.047 * buf[2*tx+1][offset_x + tx];
}
// 3*ty+2
if(ty == BLOCK_HEIGHT-1) {
int yidx = blockIdx.y * TILE_HEIGHT + TILE_HEIGHT-1;
o_arr1d[yidx * cols + xidx] = -0.047 * buf[SMALL_TILE_HEIGHT-2][offset_x + tx] + 0.927 * buf[SMALL_TILE_HEIGHT-1][offset_x + tx];
}
else {
int yidx = blockIdx.y * TILE_HEIGHT + 3*ty+2;
o_arr1d[yidx * cols + xidx] = -0.047 * buf[2*ty][offset_x + tx] + 0.927 * buf[2*ty+1][offset_x + tx]
+ 0.119 * small_tile[2*ty+2][offset_x + tx];
}
// 3*ty+1
if(ty == 0) {
int yidx = blockIdx.y * TILE_HEIGHT + 1;
o_arr1d[yidx * cols + xidx] = 0.6 * buf[0][offset_x + tx] + 0.6 * buf[1][offset_x + tx] + -0.1 * buf[2][offset_x + tx];
}
else if(ty == BLOCK_HEIGHT-1) {
int yidx = blockIdx.y * TILE_HEIGHT + TILE_HEIGHT-2;
o_arr1d[yidx * cols + xidx] = -0.1 * buf[SMALL_TILE_HEIGHT-3][offset_x + tx] + 0.6 * buf[SMALL_TILE_HEIGHT-2][offset_x + tx]
+ 0.6 * buf[SMALL_TILE_HEIGHT-1][offset_x + tx];
}
else {
int yidx = blockIdx.y * TILE_HEIGHT + 3*ty+1;
o_arr1d[yidx * cols + xidx] = -0.1 * buf[2*ty-1][offset_x + tx] + 0.6 * buf[2*ty][offset_x + tx]
+ 0.6 * buf[2*ty+1][offset_x + tx] + -0.1 * buf[2*ty+2][offset_x + tx];
}
}
} | #include <hip/hip_runtime.h>
#define BLOCK_WIDTH 32
//#define BLOCK_HEIGHT 32
#define BLOCK_HEIGHT 16
#define TILE_WIDTH 96
//#define TILE_HEIGHT 96
#define TILE_HEIGHT 48
#define SMALL_TILE_WIDTH 64
//#define SMALL_TILE_HEIGHT 64
#define SMALL_TILE_HEIGHT 32
__global__ void superResolutionKernel(float* o_arr1d, float* i_arr1d, int rows, int cols) {
__shared__ float tile[TILE_HEIGHT][TILE_WIDTH];
__shared__ float buf[SMALL_TILE_HEIGHT][TILE_WIDTH]; // buffer for down/up sampling
__shared__ float small_tile[SMALL_TILE_HEIGHT][SMALL_TILE_WIDTH];
int tx = threadIdx.x;
int ty = threadIdx.y;
for(int offset_y = 0; offset_y < TILE_HEIGHT; offset_y += BLOCK_HEIGHT) {
for(int offset_x = 0; offset_x < TILE_WIDTH; offset_x += BLOCK_WIDTH) {
int xidx = blockIdx.x * TILE_WIDTH + offset_x + tx;
int yidx = blockIdx.y * TILE_HEIGHT + offset_y + ty;
tile[offset_y + ty][offset_x + tx] = i_arr1d[yidx * cols + xidx];
}
}
__syncthreads();
// col downsample: (TILE_HEIGHT, TILE_WIDTH) -> (SMALL_TILE_HEIGHT, TILE_WIDTH)
for(int offset_x = 0; offset_x < TILE_WIDTH; offset_x += BLOCK_WIDTH) {
buf[2*ty][offset_x + tx] = -0.022 * tile[3*ty][offset_x + tx] + 0.974 * tile[3*ty+1][offset_x + tx] + 0.227 * tile[3*ty+2][offset_x + tx];
buf[2*ty+1][offset_x + tx] = 0.227 * tile[3*ty][offset_x + tx] + 0.974 * tile[3*ty+1][offset_x + tx] + -0.022 * tile[3*ty+2][offset_x + tx];
}
__syncthreads();
// row downsample: (SMALL_TILE_HEIGHT, TILE_WIDTH) -> (SMALL_TILE_HEIGHT, SMALL_TILE_WIDTH)
for(int offset_y = 0; offset_y < SMALL_TILE_HEIGHT; offset_y += BLOCK_HEIGHT) {
small_tile[offset_y + ty][2*tx] = -0.022 * buf[offset_y + ty][3*tx] + 0.974 * buf[offset_y + ty][3*tx+1] + 0.227 * buf[offset_y + ty][3*tx+2];
small_tile[offset_y + ty][2*tx+1] = 0.227 * buf[offset_y + ty][3*tx] + 0.974 * buf[offset_y + ty][3*tx+1] + -0.022 * buf[offset_y + ty][3*tx+2];
}
__syncthreads();
// row upsample: (SMALL_TILE_HEIGHT, SMALL_TILE_WIDTH) -> (SMALL_TILE_HEIGHT, TILE_WIDTH)
for(int offset_y = 0; offset_y < SMALL_TILE_HEIGHT; offset_y += BLOCK_HEIGHT) {
// 3*tx
if(tx == 0)
buf[offset_y + ty][0] = 0.927 * small_tile[offset_y + ty][0] + -0.047 * small_tile[offset_y + ty][1];
else
buf[offset_y + ty][3*tx] = 0.119 * small_tile[offset_y + ty][2*tx-1] + 0.927 * small_tile[offset_y + ty][2*tx]
+ -0.047 * small_tile[offset_y + ty][2*tx+1];
// 3*tx+2
if(tx == BLOCK_WIDTH-1)
buf[offset_y + ty][TILE_WIDTH-1] = -0.047 * small_tile[offset_y + ty][SMALL_TILE_WIDTH-2] + 0.927 * small_tile[offset_y + ty][SMALL_TILE_WIDTH-1];
else
buf[offset_y + ty][3*tx+2] = -0.047 * small_tile[offset_y + ty][2*tx] + 0.927 * small_tile[offset_y + ty][2*tx+1]
+ 0.119 * small_tile[offset_y + ty][2*tx+2];
// 3*tx+1
if(tx == 0)
buf[offset_y + ty][1] = 0.6 * small_tile[offset_y + ty][0] + 0.6 * small_tile[offset_y + ty][1] + -0.1 * small_tile[offset_y + ty][2];
else if(tx == BLOCK_WIDTH-1)
buf[offset_y + ty][TILE_WIDTH-2] = -0.1 * small_tile[offset_y + ty][SMALL_TILE_WIDTH-3] + 0.6 * small_tile[offset_y + ty][SMALL_TILE_WIDTH-2]
+ 0.6 * small_tile[offset_y + ty][SMALL_TILE_WIDTH-1];
else
buf[offset_y + ty][3*tx+1] = -0.1 * small_tile[offset_y + ty][2*tx-1] + 0.6 * small_tile[offset_y + ty][2*tx]
+ 0.6 * small_tile[offset_y + ty][2*tx+1] + -0.1 * small_tile[offset_y + ty][2*tx+2];
}
__syncthreads();
// col upsample: (SMALL_TILE_HEIGHT, TILE_WIDTH) -> (TILE_HEIGHT, TILE_WIDTH)
for(int offset_x = 0; offset_x < TILE_WIDTH; offset_x += BLOCK_WIDTH) {
int xidx = blockIdx.x * TILE_WIDTH + offset_x + tx;
// 3*ty
if(ty == 0) {
int yidx = blockIdx.y * TILE_HEIGHT;
o_arr1d[yidx * cols + xidx] = 0.927 * buf[0][offset_x + tx] + -0.047 * buf[1][offset_x + tx];
}
else {
int yidx = blockIdx.y * TILE_HEIGHT + 3*ty;
o_arr1d[yidx * cols + xidx] = 0.119 * buf[2*tx-1][offset_x + tx] + 0.927 * buf[2*tx][offset_x + tx]
+ -0.047 * buf[2*tx+1][offset_x + tx];
}
// 3*ty+2
if(ty == BLOCK_HEIGHT-1) {
int yidx = blockIdx.y * TILE_HEIGHT + TILE_HEIGHT-1;
o_arr1d[yidx * cols + xidx] = -0.047 * buf[SMALL_TILE_HEIGHT-2][offset_x + tx] + 0.927 * buf[SMALL_TILE_HEIGHT-1][offset_x + tx];
}
else {
int yidx = blockIdx.y * TILE_HEIGHT + 3*ty+2;
o_arr1d[yidx * cols + xidx] = -0.047 * buf[2*ty][offset_x + tx] + 0.927 * buf[2*ty+1][offset_x + tx]
+ 0.119 * small_tile[2*ty+2][offset_x + tx];
}
// 3*ty+1
if(ty == 0) {
int yidx = blockIdx.y * TILE_HEIGHT + 1;
o_arr1d[yidx * cols + xidx] = 0.6 * buf[0][offset_x + tx] + 0.6 * buf[1][offset_x + tx] + -0.1 * buf[2][offset_x + tx];
}
else if(ty == BLOCK_HEIGHT-1) {
int yidx = blockIdx.y * TILE_HEIGHT + TILE_HEIGHT-2;
o_arr1d[yidx * cols + xidx] = -0.1 * buf[SMALL_TILE_HEIGHT-3][offset_x + tx] + 0.6 * buf[SMALL_TILE_HEIGHT-2][offset_x + tx]
+ 0.6 * buf[SMALL_TILE_HEIGHT-1][offset_x + tx];
}
else {
int yidx = blockIdx.y * TILE_HEIGHT + 3*ty+1;
o_arr1d[yidx * cols + xidx] = -0.1 * buf[2*ty-1][offset_x + tx] + 0.6 * buf[2*ty][offset_x + tx]
+ 0.6 * buf[2*ty+1][offset_x + tx] + -0.1 * buf[2*ty+2][offset_x + tx];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define BLOCK_WIDTH 32
//#define BLOCK_HEIGHT 32
#define BLOCK_HEIGHT 16
#define TILE_WIDTH 96
//#define TILE_HEIGHT 96
#define TILE_HEIGHT 48
#define SMALL_TILE_WIDTH 64
//#define SMALL_TILE_HEIGHT 64
#define SMALL_TILE_HEIGHT 32
__global__ void superResolutionKernel(float* o_arr1d, float* i_arr1d, int rows, int cols) {
__shared__ float tile[TILE_HEIGHT][TILE_WIDTH];
__shared__ float buf[SMALL_TILE_HEIGHT][TILE_WIDTH]; // buffer for down/up sampling
__shared__ float small_tile[SMALL_TILE_HEIGHT][SMALL_TILE_WIDTH];
int tx = threadIdx.x;
int ty = threadIdx.y;
for(int offset_y = 0; offset_y < TILE_HEIGHT; offset_y += BLOCK_HEIGHT) {
for(int offset_x = 0; offset_x < TILE_WIDTH; offset_x += BLOCK_WIDTH) {
int xidx = blockIdx.x * TILE_WIDTH + offset_x + tx;
int yidx = blockIdx.y * TILE_HEIGHT + offset_y + ty;
tile[offset_y + ty][offset_x + tx] = i_arr1d[yidx * cols + xidx];
}
}
__syncthreads();
// col downsample: (TILE_HEIGHT, TILE_WIDTH) -> (SMALL_TILE_HEIGHT, TILE_WIDTH)
for(int offset_x = 0; offset_x < TILE_WIDTH; offset_x += BLOCK_WIDTH) {
buf[2*ty][offset_x + tx] = -0.022 * tile[3*ty][offset_x + tx] + 0.974 * tile[3*ty+1][offset_x + tx] + 0.227 * tile[3*ty+2][offset_x + tx];
buf[2*ty+1][offset_x + tx] = 0.227 * tile[3*ty][offset_x + tx] + 0.974 * tile[3*ty+1][offset_x + tx] + -0.022 * tile[3*ty+2][offset_x + tx];
}
__syncthreads();
// row downsample: (SMALL_TILE_HEIGHT, TILE_WIDTH) -> (SMALL_TILE_HEIGHT, SMALL_TILE_WIDTH)
for(int offset_y = 0; offset_y < SMALL_TILE_HEIGHT; offset_y += BLOCK_HEIGHT) {
small_tile[offset_y + ty][2*tx] = -0.022 * buf[offset_y + ty][3*tx] + 0.974 * buf[offset_y + ty][3*tx+1] + 0.227 * buf[offset_y + ty][3*tx+2];
small_tile[offset_y + ty][2*tx+1] = 0.227 * buf[offset_y + ty][3*tx] + 0.974 * buf[offset_y + ty][3*tx+1] + -0.022 * buf[offset_y + ty][3*tx+2];
}
__syncthreads();
// row upsample: (SMALL_TILE_HEIGHT, SMALL_TILE_WIDTH) -> (SMALL_TILE_HEIGHT, TILE_WIDTH)
for(int offset_y = 0; offset_y < SMALL_TILE_HEIGHT; offset_y += BLOCK_HEIGHT) {
// 3*tx
if(tx == 0)
buf[offset_y + ty][0] = 0.927 * small_tile[offset_y + ty][0] + -0.047 * small_tile[offset_y + ty][1];
else
buf[offset_y + ty][3*tx] = 0.119 * small_tile[offset_y + ty][2*tx-1] + 0.927 * small_tile[offset_y + ty][2*tx]
+ -0.047 * small_tile[offset_y + ty][2*tx+1];
// 3*tx+2
if(tx == BLOCK_WIDTH-1)
buf[offset_y + ty][TILE_WIDTH-1] = -0.047 * small_tile[offset_y + ty][SMALL_TILE_WIDTH-2] + 0.927 * small_tile[offset_y + ty][SMALL_TILE_WIDTH-1];
else
buf[offset_y + ty][3*tx+2] = -0.047 * small_tile[offset_y + ty][2*tx] + 0.927 * small_tile[offset_y + ty][2*tx+1]
+ 0.119 * small_tile[offset_y + ty][2*tx+2];
// 3*tx+1
if(tx == 0)
buf[offset_y + ty][1] = 0.6 * small_tile[offset_y + ty][0] + 0.6 * small_tile[offset_y + ty][1] + -0.1 * small_tile[offset_y + ty][2];
else if(tx == BLOCK_WIDTH-1)
buf[offset_y + ty][TILE_WIDTH-2] = -0.1 * small_tile[offset_y + ty][SMALL_TILE_WIDTH-3] + 0.6 * small_tile[offset_y + ty][SMALL_TILE_WIDTH-2]
+ 0.6 * small_tile[offset_y + ty][SMALL_TILE_WIDTH-1];
else
buf[offset_y + ty][3*tx+1] = -0.1 * small_tile[offset_y + ty][2*tx-1] + 0.6 * small_tile[offset_y + ty][2*tx]
+ 0.6 * small_tile[offset_y + ty][2*tx+1] + -0.1 * small_tile[offset_y + ty][2*tx+2];
}
__syncthreads();
// col upsample: (SMALL_TILE_HEIGHT, TILE_WIDTH) -> (TILE_HEIGHT, TILE_WIDTH)
for(int offset_x = 0; offset_x < TILE_WIDTH; offset_x += BLOCK_WIDTH) {
int xidx = blockIdx.x * TILE_WIDTH + offset_x + tx;
// 3*ty
if(ty == 0) {
int yidx = blockIdx.y * TILE_HEIGHT;
o_arr1d[yidx * cols + xidx] = 0.927 * buf[0][offset_x + tx] + -0.047 * buf[1][offset_x + tx];
}
else {
int yidx = blockIdx.y * TILE_HEIGHT + 3*ty;
o_arr1d[yidx * cols + xidx] = 0.119 * buf[2*tx-1][offset_x + tx] + 0.927 * buf[2*tx][offset_x + tx]
+ -0.047 * buf[2*tx+1][offset_x + tx];
}
// 3*ty+2
if(ty == BLOCK_HEIGHT-1) {
int yidx = blockIdx.y * TILE_HEIGHT + TILE_HEIGHT-1;
o_arr1d[yidx * cols + xidx] = -0.047 * buf[SMALL_TILE_HEIGHT-2][offset_x + tx] + 0.927 * buf[SMALL_TILE_HEIGHT-1][offset_x + tx];
}
else {
int yidx = blockIdx.y * TILE_HEIGHT + 3*ty+2;
o_arr1d[yidx * cols + xidx] = -0.047 * buf[2*ty][offset_x + tx] + 0.927 * buf[2*ty+1][offset_x + tx]
+ 0.119 * small_tile[2*ty+2][offset_x + tx];
}
// 3*ty+1
if(ty == 0) {
int yidx = blockIdx.y * TILE_HEIGHT + 1;
o_arr1d[yidx * cols + xidx] = 0.6 * buf[0][offset_x + tx] + 0.6 * buf[1][offset_x + tx] + -0.1 * buf[2][offset_x + tx];
}
else if(ty == BLOCK_HEIGHT-1) {
int yidx = blockIdx.y * TILE_HEIGHT + TILE_HEIGHT-2;
o_arr1d[yidx * cols + xidx] = -0.1 * buf[SMALL_TILE_HEIGHT-3][offset_x + tx] + 0.6 * buf[SMALL_TILE_HEIGHT-2][offset_x + tx]
+ 0.6 * buf[SMALL_TILE_HEIGHT-1][offset_x + tx];
}
else {
int yidx = blockIdx.y * TILE_HEIGHT + 3*ty+1;
o_arr1d[yidx * cols + xidx] = -0.1 * buf[2*ty-1][offset_x + tx] + 0.6 * buf[2*ty][offset_x + tx]
+ 0.6 * buf[2*ty+1][offset_x + tx] + -0.1 * buf[2*ty+2][offset_x + tx];
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21superResolutionKernelPfS_ii
.globl _Z21superResolutionKernelPfS_ii
.p2align 8
.type _Z21superResolutionKernelPfS_ii,@function
_Z21superResolutionKernelPfS_ii:
s_clause 0x1
s_load_b32 s16, s[0:1], 0x14
s_load_b64 s[2:3], s[0:1], 0x8
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_mul_i32 s4, s14, 0x60
s_mov_b32 s5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, 48, v[1:2]
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v3, s16, v2
v_lshlrev_b32_e32 v2, 2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u32_u24 v2, v1, 0x180, v2
v_add3_u32 v3, v0, v3, s4
s_lshl_b32 s4, s16, 4
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_2)
v_mov_b32_e32 v4, v2
s_movk_i32 s6, 0xffe0
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s6, 32
v_add_nc_u32_e32 v5, s6, v3
s_cmp_gt_u32 s6, 63
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
ds_store_b32 v4, v5
v_add_nc_u32_e32 v4, 0x80, v4
s_cbranch_scc0 .LBB0_2
v_add_nc_u32_e32 v2, 0x1800, v2
v_add_nc_u32_e32 v3, s4, v3
s_add_i32 s6, s5, 16
s_cmp_gt_u32 s5, 31
s_mov_b32 s5, s6
s_cbranch_scc0 .LBB0_1
v_mul_u32_u24_e32 v2, 0x300, v1
v_lshlrev_b32_e32 v3, 2, v0
v_mul_u32_u24_e32 v4, 3, v1
s_movk_i32 s8, 0xffe0
s_mov_b32 s3, 0x3fef2b02
s_mov_b32 s2, 0xc49ba5e
v_add3_u32 v2, v2, v3, 0x4800
v_mad_u32_u24 v3, v4, 0x180, v3
s_mov_b32 s5, 0xbf96872b
s_mov_b32 s4, 0x20c49ba
s_mov_b32 s7, 0x3fcd0e56
s_mov_b32 s6, 0x4189375
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.p2align 6
.LBB0_5:
ds_load_2addr_b32 v[4:5], v3 offset1:96
s_add_i32 s8, s8, 32
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_cmp_gt_u32 s8, 63
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[5:6], v5
v_cvt_f64_f32_e32 v[7:8], v4
v_mul_f64 v[4:5], v[5:6], s[2:3]
ds_load_b32 v6, v3 offset:768
v_add_nc_u32_e32 v3, 0x80, v3
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[9:10], v6
v_fma_f64 v[11:12], v[7:8], s[4:5], v[4:5]
v_fma_f64 v[4:5], v[7:8], s[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[6:7], v[9:10], s[6:7], v[11:12]
v_fma_f64 v[4:5], v[9:10], s[4:5], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_f64_e32 v6, v[6:7]
v_cvt_f32_f64_e32 v4, v[4:5]
ds_store_2addr_b32 v2, v6, v4 offset1:96
v_add_nc_u32_e32 v2, 0x80, v2
s_cbranch_scc0 .LBB0_5
v_mul_u32_u24_e32 v2, 3, v0
v_lshlrev_b32_e32 v3, 8, v1
v_lshlrev_b32_e32 v4, 3, v0
v_mul_u32_u24_e32 v5, 0x180, v1
s_mov_b32 s8, 0
v_lshlrev_b32_e32 v6, 2, v2
s_mov_b32 s3, 0x3fef2b02
v_add3_u32 v2, v3, v4, 0x7800
s_mov_b32 s2, 0xc49ba5e
s_mov_b32 s5, 0xbf96872b
v_add3_u32 v3, v5, v6, 0x4800
s_mov_b32 s4, 0x20c49ba
s_mov_b32 s7, 0x3fcd0e56
s_mov_b32 s6, 0x4189375
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.p2align 6
.LBB0_7:
ds_load_2addr_b32 v[4:5], v3 offset1:1
ds_load_b32 v9, v3 offset:8
v_add_nc_u32_e32 v3, 0x1800, v3
s_waitcnt lgkmcnt(1)
v_cvt_f64_f32_e32 v[5:6], v5
v_cvt_f64_f32_e32 v[7:8], v4
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[9:10], v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[4:5], v[5:6], s[2:3]
v_fma_f64 v[11:12], v[7:8], s[4:5], v[4:5]
v_fma_f64 v[4:5], v[7:8], s[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[6:7], v[9:10], s[6:7], v[11:12]
v_fma_f64 v[4:5], v[9:10], s[4:5], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_f64_e32 v6, v[6:7]
v_cvt_f32_f64_e32 v4, v[4:5]
v_add_nc_u32_e32 v5, s8, v2
s_addk_i32 s8, 0x1000
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_lg_i32 s8, 0x1000
ds_store_2addr_b32 v5, v6, v4 offset1:1
s_cbranch_scc0 .LBB0_7
v_mul_u32_u24_e32 v2, 3, v0
v_lshlrev_b32_e32 v3, 8, v1
v_lshlrev_b32_e32 v7, 3, v0
s_movk_i32 s3, 0x180
v_cmp_ne_u32_e32 vcc_lo, 0, v0
v_lshlrev_b32_e32 v2, 2, v2
v_cmp_ne_u32_e64 s2, 31, v0
v_mad_u32_u24 v4, v0, 3, 2
v_mad_u32_u24 v5, v1, s3, 0x4800
v_add_nc_u32_e32 v6, 0x7800, v3
v_mad_u32_u24 v2, v1, 0x180, v2
v_add3_u32 v7, v3, v7, 0x77fc
s_mov_b32 s3, 16
s_mov_b32 s5, 0x3feda9fb
s_mov_b32 s4, 0xe76c8b44
v_add_nc_u32_e32 v8, 0x4804, v2
v_add_nc_u32_e32 v9, 0x4800, v2
s_mov_b32 s7, 0x3fbe76c8
s_mov_b32 s6, 0xb4395810
s_mov_b32 s9, 0xbfa81062
s_mov_b32 s8, 0x4dd2f1aa
s_mov_b32 s11, 0xbfb99999
s_mov_b32 s10, 0x9999999a
s_mov_b32 s13, 0x3fe33333
s_mov_b32 s12, 0x33333333
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB0_10
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s17
v_add_nc_u32_e32 v6, 0x1000, v6
v_add_nc_u32_e32 v5, 0x1800, v5
v_add_nc_u32_e32 v8, 0x1800, v8
v_add_nc_u32_e32 v7, 0x1000, v7
v_add_nc_u32_e32 v9, 0x1800, v9
s_add_i32 s3, s3, -16
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s3, 0
s_cbranch_scc1 .LBB0_26
.LBB0_10:
s_and_saveexec_b32 s17, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s17, exec_lo, s17
s_cbranch_execz .LBB0_12
ds_load_2addr_b32 v[2:3], v7 offset1:1
ds_load_b32 v12, v7 offset:8
s_waitcnt lgkmcnt(1)
v_cvt_f64_f32_e32 v[10:11], v3
v_cvt_f64_f32_e32 v[2:3], v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[10:11], v[10:11], s[4:5]
v_fma_f64 v[2:3], v[2:3], s[6:7], v[10:11]
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[10:11], v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[10:11], s[8:9], v[2:3]
v_cvt_f32_f64_e32 v2, v[2:3]
ds_store_b32 v9, v2
.LBB0_12:
s_and_not1_saveexec_b32 s17, s17
s_cbranch_execz .LBB0_14
ds_load_2addr_b32 v[2:3], v6 offset1:1
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[10:11], v3
v_cvt_f64_f32_e32 v[2:3], v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[10:11], v[10:11], s[8:9]
v_fma_f64 v[2:3], v[2:3], s[4:5], v[10:11]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v2, v[2:3]
ds_store_b32 v5, v2
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s17
s_and_saveexec_b32 s17, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s17, exec_lo, s17
s_cbranch_execz .LBB0_16
ds_load_2addr_b32 v[2:3], v7 offset0:1 offset1:2
ds_load_b32 v12, v7 offset:12
s_waitcnt lgkmcnt(1)
v_cvt_f64_f32_e32 v[10:11], v2
v_cvt_f64_f32_e32 v[2:3], v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[10:11], v[10:11], s[8:9]
v_fma_f64 v[2:3], v[2:3], s[4:5], v[10:11]
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[10:11], v12
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[2:3], v[10:11], s[6:7], v[2:3]
.LBB0_16:
s_or_saveexec_b32 s17, s17
v_mov_b32_e32 v10, v4
s_xor_b32 exec_lo, exec_lo, s17
s_cbranch_execz .LBB0_18
ds_load_2addr_b32 v[2:3], v6 offset0:62 offset1:63
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[10:11], v2
v_cvt_f64_f32_e32 v[2:3], v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[10:11], v[10:11], s[8:9]
v_fma_f64 v[2:3], v[2:3], s[4:5], v[10:11]
v_mov_b32_e32 v10, 0x5f
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_f64_e32 v2, v[2:3]
v_lshl_add_u32 v3, v10, 2, v5
ds_store_b32 v3, v2
s_and_saveexec_b32 s17, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s17, exec_lo, s17
s_cbranch_execz .LBB0_24
s_and_saveexec_b32 s18, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s18, exec_lo, s18
s_cbranch_execz .LBB0_21
ds_load_2addr_b32 v[2:3], v7 offset1:1
ds_load_2addr_b32 v[10:11], v7 offset0:2 offset1:3
s_waitcnt lgkmcnt(1)
v_cvt_f64_f32_e32 v[12:13], v2
v_cvt_f64_f32_e32 v[2:3], v3
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[14:15], v10
v_cvt_f64_f32_e32 v[10:11], v11
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[12:13], v[12:13], s[10:11]
v_fma_f64 v[2:3], v[2:3], s[12:13], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[14:15], s[12:13], v[2:3]
v_fma_f64 v[2:3], v[10:11], s[10:11], v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v2, v[2:3]
ds_store_b32 v8, v2
.LBB0_21:
s_and_not1_saveexec_b32 s18, s18
s_cbranch_execz .LBB0_23
ds_load_2addr_b32 v[2:3], v6 offset0:61 offset1:62
ds_load_b32 v12, v6 offset:252
s_waitcnt lgkmcnt(1)
v_cvt_f64_f32_e32 v[10:11], v2
v_cvt_f64_f32_e32 v[2:3], v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[10:11], v[10:11], s[10:11]
v_fma_f64 v[2:3], v[2:3], s[12:13], v[10:11]
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[10:11], v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[10:11], s[12:13], v[2:3]
v_cvt_f32_f64_e32 v2, v[2:3]
ds_store_b32 v5, v2 offset:376
.LBB0_23:
s_or_b32 exec_lo, exec_lo, s18
.LBB0_24:
s_and_not1_saveexec_b32 s17, s17
s_cbranch_execz .LBB0_9
ds_load_2addr_b32 v[2:3], v6 offset1:1
ds_load_b32 v12, v6 offset:8
s_waitcnt lgkmcnt(1)
v_cvt_f64_f32_e32 v[10:11], v3
v_cvt_f64_f32_e32 v[2:3], v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[10:11], v[10:11], s[12:13]
v_fma_f64 v[2:3], v[2:3], s[12:13], v[10:11]
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[10:11], v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[10:11], s[10:11], v[2:3]
v_cvt_f32_f64_e32 v2, v[2:3]
ds_store_b32 v5, v2 offset:4
s_branch .LBB0_9
.LBB0_26:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v6, 2, v0
s_mul_i32 s15, s15, 48
v_cmp_ne_u32_e32 vcc_lo, 0, v1
v_mad_u32_u24 v4, v1, 3, s15
v_cmp_ne_u32_e64 s0, 15, v1
v_mad_u32_u24 v8, v1, 0x300, v6
v_lshl_add_u32 v9, v1, 9, v6
v_mad_u64_u32 v[1:2], null, s14, 0x60, v[0:1]
v_add_nc_u32_e32 v5, 2, v4
v_add_nc_u32_e32 v7, 1, v4
v_mul_u32_u24_e32 v10, 0x304, v0
s_mov_b32 s17, 0
s_add_i32 s18, s15, 47
s_add_i32 s19, s15, 46
s_or_b32 s20, s15, 1
s_mov_b32 s14, 0
s_mov_b32 s5, 0x3feda9fb
s_mov_b32 s4, 0xe76c8b44
s_mov_b32 s7, 0x3fbe76c8
s_mov_b32 s6, 0xb4395810
s_mov_b32 s9, 0xbfa81062
s_mov_b32 s8, 0x4dd2f1aa
s_mov_b32 s11, 0xbfb99999
s_mov_b32 s10, 0x9999999a
s_mov_b32 s13, 0x3fe33333
s_mov_b32 s12, 0x33333333
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB0_28
.LBB0_27:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_f64_e32 v11, v[2:3]
v_mul_lo_u32 v2, v12, s16
s_addk_i32 s17, 0x80
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v2, v1, s14, v2
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, s1, s2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s1, s3, v3, s1
s_add_i32 s1, s14, 32
s_cmp_gt_u32 s14, 63
s_mov_b32 s14, s1
global_store_b32 v[2:3], v11, off
s_cbranch_scc1 .LBB0_44
.LBB0_28:
s_and_saveexec_b32 s1, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB0_30
v_add_nc_u32_e32 v13, s17, v10
s_movk_i32 s21, 0x4600
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v2, s21, v13
ds_load_2addr_b32 v[2:3], v2 offset0:32 offset1:128
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[11:12], v3
v_cvt_f64_f32_e32 v[2:3], v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[11:12], v[11:12], s[4:5]
v_fma_f64 v[2:3], v[2:3], s[6:7], v[11:12]
v_add_nc_u32_e32 v12, 0x4980, v13
.LBB0_30:
s_or_saveexec_b32 s1, s1
v_add_nc_u32_e32 v11, s17, v6
v_mov_b32_e32 v13, v4
s_xor_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_32
ds_load_b32 v2, v11 offset:18432
v_dual_mov_b32 v13, s15 :: v_dual_add_nc_u32 v12, s14, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshl_add_u32 v12, v12, 2, 0x4980
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[2:3], v2
v_mul_f64 v[2:3], v[2:3], s[4:5]
.LBB0_32:
s_or_b32 exec_lo, exec_lo, s1
ds_load_b32 v12, v12
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[14:15], v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[14:15], s[8:9], v[2:3]
v_cvt_f32_f64_e32 v12, v[2:3]
v_mul_lo_u32 v2, v13, s16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v2, v1, s14, v2
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, s1, s2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v3, s1, s3, v3, s1
global_store_b32 v[2:3], v12, off
s_and_saveexec_b32 s1, s0
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB0_34
v_add_nc_u32_e32 v2, s17, v8
s_movk_i32 s21, 0x4800
v_add_nc_u32_e32 v14, s17, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v2, s21, v2
ds_load_b32 v14, v14 offset:31232
ds_load_2addr_b32 v[2:3], v2 offset1:96
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[12:13], v2
v_cvt_f64_f32_e32 v[2:3], v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[12:13], v[12:13], s[8:9]
v_fma_f64 v[2:3], v[2:3], s[4:5], v[12:13]
v_cvt_f64_f32_e32 v[12:13], v14
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[2:3], v[12:13], s[6:7], v[2:3]
.LBB0_34:
s_or_saveexec_b32 s1, s1
v_mov_b32_e32 v12, v5
s_xor_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB0_36
s_movk_i32 s21, 0x7400
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, s21, v11
ds_load_2addr_b32 v[2:3], v2 offset0:64 offset1:160
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[12:13], v2
v_cvt_f64_f32_e32 v[2:3], v3
v_mul_f64 v[12:13], v[12:13], s[8:9]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[2:3], v[2:3], s[4:5], v[12:13]
v_mov_b32_e32 v12, s18
.LBB0_36:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_f64_e32 v13, v[2:3]
v_mul_lo_u32 v2, v12, s16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v2, v1, s14, v2
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, s1, s2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v3, s1, s3, v3, s1
global_store_b32 v[2:3], v13, off
s_and_saveexec_b32 s1, vcc_lo
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB0_42
s_and_saveexec_b32 s21, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s21, exec_lo, s21
s_cbranch_execz .LBB0_39
v_add_nc_u32_e32 v13, s17, v8
s_movk_i32 s22, 0x4600
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v2, s22, v13
s_movk_i32 s22, 0x4800
s_delay_alu instid0(SALU_CYCLE_1)
v_add_nc_u32_e32 v13, s22, v13
ds_load_2addr_b32 v[2:3], v2 offset0:32 offset1:128
ds_load_2addr_b32 v[13:14], v13 offset0:96 offset1:192
s_waitcnt lgkmcnt(1)
v_cvt_f64_f32_e32 v[11:12], v2
v_cvt_f64_f32_e32 v[2:3], v3
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[15:16], v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[11:12], v[11:12], s[10:11]
v_fma_f64 v[2:3], v[2:3], s[12:13], v[11:12]
v_cvt_f64_f32_e32 v[11:12], v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[15:16], s[12:13], v[2:3]
v_fma_f64 v[2:3], v[11:12], s[10:11], v[2:3]
.LBB0_39:
s_or_saveexec_b32 s21, s21
v_mov_b32_e32 v12, v7
s_xor_b32 exec_lo, exec_lo, s21
s_cbranch_execz .LBB0_41
s_movk_i32 s22, 0x7200
s_delay_alu instid0(SALU_CYCLE_1)
v_add_nc_u32_e32 v2, s22, v11
ds_load_b32 v11, v11 offset:30336
ds_load_2addr_b32 v[2:3], v2 offset0:96 offset1:192
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[12:13], v2
v_cvt_f64_f32_e32 v[2:3], v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[12:13], v[12:13], s[10:11]
v_fma_f64 v[2:3], v[2:3], s[12:13], v[12:13]
v_cvt_f64_f32_e32 v[11:12], v11
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[2:3], v[11:12], s[12:13], v[2:3]
v_mov_b32_e32 v12, s19
.LBB0_41:
s_or_b32 exec_lo, exec_lo, s21
.LBB0_42:
s_and_not1_saveexec_b32 s1, s1
s_cbranch_execz .LBB0_27
s_movk_i32 s21, 0x4800
s_delay_alu instid0(SALU_CYCLE_1)
v_add_nc_u32_e32 v2, s21, v11
ds_load_b32 v11, v11 offset:19200
ds_load_2addr_b32 v[2:3], v2 offset1:96
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[12:13], v3
v_cvt_f64_f32_e32 v[2:3], v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[12:13], v[12:13], s[12:13]
v_fma_f64 v[2:3], v[2:3], s[12:13], v[12:13]
v_cvt_f64_f32_e32 v[11:12], v11
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[2:3], v[11:12], s[10:11], v[2:3]
v_mov_b32_e32 v12, s20
s_branch .LBB0_27
.LBB0_44:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21superResolutionKernelPfS_ii
.amdhsa_group_segment_fixed_size 38912
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 23
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21superResolutionKernelPfS_ii, .Lfunc_end0-_Z21superResolutionKernelPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 38912
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21superResolutionKernelPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 25
.sgpr_spill_count: 0
.symbol: _Z21superResolutionKernelPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define BLOCK_WIDTH 32
//#define BLOCK_HEIGHT 32
#define BLOCK_HEIGHT 16
#define TILE_WIDTH 96
//#define TILE_HEIGHT 96
#define TILE_HEIGHT 48
#define SMALL_TILE_WIDTH 64
//#define SMALL_TILE_HEIGHT 64
#define SMALL_TILE_HEIGHT 32
__global__ void superResolutionKernel(float* o_arr1d, float* i_arr1d, int rows, int cols) {
__shared__ float tile[TILE_HEIGHT][TILE_WIDTH];
__shared__ float buf[SMALL_TILE_HEIGHT][TILE_WIDTH]; // buffer for down/up sampling
__shared__ float small_tile[SMALL_TILE_HEIGHT][SMALL_TILE_WIDTH];
int tx = threadIdx.x;
int ty = threadIdx.y;
for(int offset_y = 0; offset_y < TILE_HEIGHT; offset_y += BLOCK_HEIGHT) {
for(int offset_x = 0; offset_x < TILE_WIDTH; offset_x += BLOCK_WIDTH) {
int xidx = blockIdx.x * TILE_WIDTH + offset_x + tx;
int yidx = blockIdx.y * TILE_HEIGHT + offset_y + ty;
tile[offset_y + ty][offset_x + tx] = i_arr1d[yidx * cols + xidx];
}
}
__syncthreads();
// col downsample: (TILE_HEIGHT, TILE_WIDTH) -> (SMALL_TILE_HEIGHT, TILE_WIDTH)
for(int offset_x = 0; offset_x < TILE_WIDTH; offset_x += BLOCK_WIDTH) {
buf[2*ty][offset_x + tx] = -0.022 * tile[3*ty][offset_x + tx] + 0.974 * tile[3*ty+1][offset_x + tx] + 0.227 * tile[3*ty+2][offset_x + tx];
buf[2*ty+1][offset_x + tx] = 0.227 * tile[3*ty][offset_x + tx] + 0.974 * tile[3*ty+1][offset_x + tx] + -0.022 * tile[3*ty+2][offset_x + tx];
}
__syncthreads();
// row downsample: (SMALL_TILE_HEIGHT, TILE_WIDTH) -> (SMALL_TILE_HEIGHT, SMALL_TILE_WIDTH)
for(int offset_y = 0; offset_y < SMALL_TILE_HEIGHT; offset_y += BLOCK_HEIGHT) {
small_tile[offset_y + ty][2*tx] = -0.022 * buf[offset_y + ty][3*tx] + 0.974 * buf[offset_y + ty][3*tx+1] + 0.227 * buf[offset_y + ty][3*tx+2];
small_tile[offset_y + ty][2*tx+1] = 0.227 * buf[offset_y + ty][3*tx] + 0.974 * buf[offset_y + ty][3*tx+1] + -0.022 * buf[offset_y + ty][3*tx+2];
}
__syncthreads();
// row upsample: (SMALL_TILE_HEIGHT, SMALL_TILE_WIDTH) -> (SMALL_TILE_HEIGHT, TILE_WIDTH)
for(int offset_y = 0; offset_y < SMALL_TILE_HEIGHT; offset_y += BLOCK_HEIGHT) {
// 3*tx
if(tx == 0)
buf[offset_y + ty][0] = 0.927 * small_tile[offset_y + ty][0] + -0.047 * small_tile[offset_y + ty][1];
else
buf[offset_y + ty][3*tx] = 0.119 * small_tile[offset_y + ty][2*tx-1] + 0.927 * small_tile[offset_y + ty][2*tx]
+ -0.047 * small_tile[offset_y + ty][2*tx+1];
// 3*tx+2
if(tx == BLOCK_WIDTH-1)
buf[offset_y + ty][TILE_WIDTH-1] = -0.047 * small_tile[offset_y + ty][SMALL_TILE_WIDTH-2] + 0.927 * small_tile[offset_y + ty][SMALL_TILE_WIDTH-1];
else
buf[offset_y + ty][3*tx+2] = -0.047 * small_tile[offset_y + ty][2*tx] + 0.927 * small_tile[offset_y + ty][2*tx+1]
+ 0.119 * small_tile[offset_y + ty][2*tx+2];
// 3*tx+1
if(tx == 0)
buf[offset_y + ty][1] = 0.6 * small_tile[offset_y + ty][0] + 0.6 * small_tile[offset_y + ty][1] + -0.1 * small_tile[offset_y + ty][2];
else if(tx == BLOCK_WIDTH-1)
buf[offset_y + ty][TILE_WIDTH-2] = -0.1 * small_tile[offset_y + ty][SMALL_TILE_WIDTH-3] + 0.6 * small_tile[offset_y + ty][SMALL_TILE_WIDTH-2]
+ 0.6 * small_tile[offset_y + ty][SMALL_TILE_WIDTH-1];
else
buf[offset_y + ty][3*tx+1] = -0.1 * small_tile[offset_y + ty][2*tx-1] + 0.6 * small_tile[offset_y + ty][2*tx]
+ 0.6 * small_tile[offset_y + ty][2*tx+1] + -0.1 * small_tile[offset_y + ty][2*tx+2];
}
__syncthreads();
// col upsample: (SMALL_TILE_HEIGHT, TILE_WIDTH) -> (TILE_HEIGHT, TILE_WIDTH)
for(int offset_x = 0; offset_x < TILE_WIDTH; offset_x += BLOCK_WIDTH) {
int xidx = blockIdx.x * TILE_WIDTH + offset_x + tx;
// 3*ty
if(ty == 0) {
int yidx = blockIdx.y * TILE_HEIGHT;
o_arr1d[yidx * cols + xidx] = 0.927 * buf[0][offset_x + tx] + -0.047 * buf[1][offset_x + tx];
}
else {
int yidx = blockIdx.y * TILE_HEIGHT + 3*ty;
o_arr1d[yidx * cols + xidx] = 0.119 * buf[2*tx-1][offset_x + tx] + 0.927 * buf[2*tx][offset_x + tx]
+ -0.047 * buf[2*tx+1][offset_x + tx];
}
// 3*ty+2
if(ty == BLOCK_HEIGHT-1) {
int yidx = blockIdx.y * TILE_HEIGHT + TILE_HEIGHT-1;
o_arr1d[yidx * cols + xidx] = -0.047 * buf[SMALL_TILE_HEIGHT-2][offset_x + tx] + 0.927 * buf[SMALL_TILE_HEIGHT-1][offset_x + tx];
}
else {
int yidx = blockIdx.y * TILE_HEIGHT + 3*ty+2;
o_arr1d[yidx * cols + xidx] = -0.047 * buf[2*ty][offset_x + tx] + 0.927 * buf[2*ty+1][offset_x + tx]
+ 0.119 * small_tile[2*ty+2][offset_x + tx];
}
// 3*ty+1
if(ty == 0) {
int yidx = blockIdx.y * TILE_HEIGHT + 1;
o_arr1d[yidx * cols + xidx] = 0.6 * buf[0][offset_x + tx] + 0.6 * buf[1][offset_x + tx] + -0.1 * buf[2][offset_x + tx];
}
else if(ty == BLOCK_HEIGHT-1) {
int yidx = blockIdx.y * TILE_HEIGHT + TILE_HEIGHT-2;
o_arr1d[yidx * cols + xidx] = -0.1 * buf[SMALL_TILE_HEIGHT-3][offset_x + tx] + 0.6 * buf[SMALL_TILE_HEIGHT-2][offset_x + tx]
+ 0.6 * buf[SMALL_TILE_HEIGHT-1][offset_x + tx];
}
else {
int yidx = blockIdx.y * TILE_HEIGHT + 3*ty+1;
o_arr1d[yidx * cols + xidx] = -0.1 * buf[2*ty-1][offset_x + tx] + 0.6 * buf[2*ty][offset_x + tx]
+ 0.6 * buf[2*ty+1][offset_x + tx] + -0.1 * buf[2*ty+2][offset_x + tx];
}
}
} | .text
.file "kernel.hip"
.globl _Z36__device_stub__superResolutionKernelPfS_ii # -- Begin function _Z36__device_stub__superResolutionKernelPfS_ii
.p2align 4, 0x90
.type _Z36__device_stub__superResolutionKernelPfS_ii,@function
_Z36__device_stub__superResolutionKernelPfS_ii: # @_Z36__device_stub__superResolutionKernelPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21superResolutionKernelPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z36__device_stub__superResolutionKernelPfS_ii, .Lfunc_end0-_Z36__device_stub__superResolutionKernelPfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21superResolutionKernelPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21superResolutionKernelPfS_ii,@object # @_Z21superResolutionKernelPfS_ii
.section .rodata,"a",@progbits
.globl _Z21superResolutionKernelPfS_ii
.p2align 3, 0x0
_Z21superResolutionKernelPfS_ii:
.quad _Z36__device_stub__superResolutionKernelPfS_ii
.size _Z21superResolutionKernelPfS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21superResolutionKernelPfS_ii"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__superResolutionKernelPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21superResolutionKernelPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00070e1f_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z21superResolutionKernelPfS_iiPfS_ii
.type _Z45__device_stub__Z21superResolutionKernelPfS_iiPfS_ii, @function
_Z45__device_stub__Z21superResolutionKernelPfS_iiPfS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21superResolutionKernelPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z21superResolutionKernelPfS_iiPfS_ii, .-_Z45__device_stub__Z21superResolutionKernelPfS_iiPfS_ii
.globl _Z21superResolutionKernelPfS_ii
.type _Z21superResolutionKernelPfS_ii, @function
_Z21superResolutionKernelPfS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z21superResolutionKernelPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z21superResolutionKernelPfS_ii, .-_Z21superResolutionKernelPfS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z21superResolutionKernelPfS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21superResolutionKernelPfS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z36__device_stub__superResolutionKernelPfS_ii # -- Begin function _Z36__device_stub__superResolutionKernelPfS_ii
.p2align 4, 0x90
.type _Z36__device_stub__superResolutionKernelPfS_ii,@function
_Z36__device_stub__superResolutionKernelPfS_ii: # @_Z36__device_stub__superResolutionKernelPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21superResolutionKernelPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z36__device_stub__superResolutionKernelPfS_ii, .Lfunc_end0-_Z36__device_stub__superResolutionKernelPfS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21superResolutionKernelPfS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21superResolutionKernelPfS_ii,@object # @_Z21superResolutionKernelPfS_ii
.section .rodata,"a",@progbits
.globl _Z21superResolutionKernelPfS_ii
.p2align 3, 0x0
_Z21superResolutionKernelPfS_ii:
.quad _Z36__device_stub__superResolutionKernelPfS_ii
.size _Z21superResolutionKernelPfS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21superResolutionKernelPfS_ii"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__superResolutionKernelPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21superResolutionKernelPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
using namespace std;
int main() {
cudaEvent_t start, stop, done_offload;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventCreate(&done_offload);
void *p, *q;
long size = 1024l * 1024 * 200;
cudaMalloc(&p, size);
cudaMallocHost(&q, size);
cout << "without split by event\n";
int N = 100;
cudaEventRecord(start);
for (int i = 0; i < N; i++) {
cudaMemcpyAsync(q, p, size, cudaMemcpyDeviceToHost, NULL);
}
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milli;
cudaEventElapsedTime(&milli, start, stop);
cout << "Time(ms): " << milli << endl;
cout << "with split by event\n";
cudaEventRecord(start);
for (int i = 0; i < N; i++) {
cudaMemcpyAsync(q, p, size, cudaMemcpyDeviceToHost, NULL);
cudaEventRecord(done_offload, NULL);
cudaEventSynchronize(done_offload);
}
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&milli, start, stop);
cout << "Time(ms): " << milli << endl;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
using namespace std;
int main() {
cudaEvent_t start, stop, done_offload;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventCreate(&done_offload);
void *p, *q;
long size = 1024l * 1024 * 200;
cudaMalloc(&p, size);
cudaMallocHost(&q, size);
cout << "without split by event\n";
int N = 100;
cudaEventRecord(start);
for (int i = 0; i < N; i++) {
cudaMemcpyAsync(q, p, size, cudaMemcpyDeviceToHost, NULL);
}
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milli;
cudaEventElapsedTime(&milli, start, stop);
cout << "Time(ms): " << milli << endl;
cout << "with split by event\n";
cudaEventRecord(start);
for (int i = 0; i < N; i++) {
cudaMemcpyAsync(q, p, size, cudaMemcpyDeviceToHost, NULL);
cudaEventRecord(done_offload, NULL);
cudaEventSynchronize(done_offload);
}
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&milli, start, stop);
cout << "Time(ms): " << milli << endl;
} | .file "tmpxft_0003b9de_00000000-6_copy_split.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "without split by event\n"
.LC1:
.string "Time(ms): "
.LC2:
.string "with split by event\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
movl $209715200, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $209715200, %esi
call cudaMallocHost@PLT
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $100, %ebx
.L4:
movl $0, %r8d
movl $2, %ecx
movl $209715200, %edx
movq 40(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpyAsync@PLT
subl $1, %ebx
jne .L4
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC2(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $100, %ebx
.L5:
movl $0, %r8d
movl $2, %ecx
movl $209715200, %edx
movq 40(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpyAsync@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
subl $1, %ebx
jne .L5
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L10
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
using namespace std;
int main() {
cudaEvent_t start, stop, done_offload;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventCreate(&done_offload);
void *p, *q;
long size = 1024l * 1024 * 200;
cudaMalloc(&p, size);
cudaMallocHost(&q, size);
cout << "without split by event\n";
int N = 100;
cudaEventRecord(start);
for (int i = 0; i < N; i++) {
cudaMemcpyAsync(q, p, size, cudaMemcpyDeviceToHost, NULL);
}
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milli;
cudaEventElapsedTime(&milli, start, stop);
cout << "Time(ms): " << milli << endl;
cout << "with split by event\n";
cudaEventRecord(start);
for (int i = 0; i < N; i++) {
cudaMemcpyAsync(q, p, size, cudaMemcpyDeviceToHost, NULL);
cudaEventRecord(done_offload, NULL);
cudaEventSynchronize(done_offload);
}
cudaEventRecord(stop);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&milli, start, stop);
cout << "Time(ms): " << milli << endl;
} | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
int main() {
hipEvent_t start, stop, done_offload;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventCreate(&done_offload);
void *p, *q;
long size = 1024l * 1024 * 200;
hipMalloc(&p, size);
hipHostMalloc(&q, size, hipHostMallocDefault);
cout << "without split by event\n";
int N = 100;
hipEventRecord(start);
for (int i = 0; i < N; i++) {
hipMemcpyAsync(q, p, size, hipMemcpyDeviceToHost, NULL);
}
hipEventRecord(stop);
hipEventSynchronize(stop);
float milli;
hipEventElapsedTime(&milli, start, stop);
cout << "Time(ms): " << milli << endl;
cout << "with split by event\n";
hipEventRecord(start);
for (int i = 0; i < N; i++) {
hipMemcpyAsync(q, p, size, hipMemcpyDeviceToHost, NULL);
hipEventRecord(done_offload, NULL);
hipEventSynchronize(done_offload);
}
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&milli, start, stop);
cout << "Time(ms): " << milli << endl;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
int main() {
hipEvent_t start, stop, done_offload;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventCreate(&done_offload);
void *p, *q;
long size = 1024l * 1024 * 200;
hipMalloc(&p, size);
hipHostMalloc(&q, size, hipHostMallocDefault);
cout << "without split by event\n";
int N = 100;
hipEventRecord(start);
for (int i = 0; i < N; i++) {
hipMemcpyAsync(q, p, size, hipMemcpyDeviceToHost, NULL);
}
hipEventRecord(stop);
hipEventSynchronize(stop);
float milli;
hipEventElapsedTime(&milli, start, stop);
cout << "Time(ms): " << milli << endl;
cout << "with split by event\n";
hipEventRecord(start);
for (int i = 0; i < N; i++) {
hipMemcpyAsync(q, p, size, hipMemcpyDeviceToHost, NULL);
hipEventRecord(done_offload, NULL);
hipEventSynchronize(done_offload);
}
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&milli, start, stop);
cout << "Time(ms): " << milli << endl;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
int main() {
hipEvent_t start, stop, done_offload;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventCreate(&done_offload);
void *p, *q;
long size = 1024l * 1024 * 200;
hipMalloc(&p, size);
hipHostMalloc(&q, size, hipHostMallocDefault);
cout << "without split by event\n";
int N = 100;
hipEventRecord(start);
for (int i = 0; i < N; i++) {
hipMemcpyAsync(q, p, size, hipMemcpyDeviceToHost, NULL);
}
hipEventRecord(stop);
hipEventSynchronize(stop);
float milli;
hipEventElapsedTime(&milli, start, stop);
cout << "Time(ms): " << milli << endl;
cout << "with split by event\n";
hipEventRecord(start);
for (int i = 0; i < N; i++) {
hipMemcpyAsync(q, p, size, hipMemcpyDeviceToHost, NULL);
hipEventRecord(done_offload, NULL);
hipEventSynchronize(done_offload);
}
hipEventRecord(stop);
hipEventSynchronize(stop);
hipEventElapsedTime(&milli, start, stop);
cout << "Time(ms): " << milli << endl;
} | .text
.file "copy_split.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $56, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 40(%rsp), %rdi
movl $209715200, %esi # imm = 0xC800000
callq hipMalloc
leaq 32(%rsp), %rdi
movl $209715200, %esi # imm = 0xC800000
xorl %edx, %edx
callq hipHostMalloc
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $100, %ebx
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movq 32(%rsp), %rdi
movq 40(%rsp), %rsi
movl $209715200, %edx # imm = 0xC800000
movl $2, %ecx
xorl %r8d, %r8d
callq hipMemcpyAsync
decl %ebx
jne .LBB0_1
# %bb.2:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_13
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_5
# %bb.4:
movzbl 67(%rbx), %ecx
jmp .LBB0_6
.LBB0_5:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $100, %ebx
.p2align 4, 0x90
.LBB0_7: # =>This Inner Loop Header: Depth=1
movq 32(%rsp), %rdi
movq 40(%rsp), %rsi
movl $209715200, %edx # imm = 0xC800000
movl $2, %ecx
xorl %r8d, %r8d
callq hipMemcpyAsync
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 48(%rsp), %rdi
callq hipEventSynchronize
decl %ebx
jne .LBB0_7
# %bb.8:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_13
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i13
cmpb $0, 56(%rbx)
je .LBB0_11
# %bb.10:
movzbl 67(%rbx), %ecx
jmp .LBB0_12
.LBB0_11:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit16
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_13:
.cfi_def_cfa_offset 80
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "without split by event\n"
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Time(ms): "
.size .L.str.1, 11
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "with split by event\n"
.size .L.str.2, 21
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003b9de_00000000-6_copy_split.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "without split by event\n"
.LC1:
.string "Time(ms): "
.LC2:
.string "with split by event\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
movl $209715200, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $209715200, %esi
call cudaMallocHost@PLT
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $100, %ebx
.L4:
movl $0, %r8d
movl $2, %ecx
movl $209715200, %edx
movq 40(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpyAsync@PLT
subl $1, %ebx
jne .L4
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC2(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $100, %ebx
.L5:
movl $0, %r8d
movl $2, %ecx
movl $209715200, %edx
movq 40(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpyAsync@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
subl $1, %ebx
jne .L5
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L10
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "copy_split.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $56, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 40(%rsp), %rdi
movl $209715200, %esi # imm = 0xC800000
callq hipMalloc
leaq 32(%rsp), %rdi
movl $209715200, %esi # imm = 0xC800000
xorl %edx, %edx
callq hipHostMalloc
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $100, %ebx
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movq 32(%rsp), %rdi
movq 40(%rsp), %rsi
movl $209715200, %edx # imm = 0xC800000
movl $2, %ecx
xorl %r8d, %r8d
callq hipMemcpyAsync
decl %ebx
jne .LBB0_1
# %bb.2:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_13
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_5
# %bb.4:
movzbl 67(%rbx), %ecx
jmp .LBB0_6
.LBB0_5:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $100, %ebx
.p2align 4, 0x90
.LBB0_7: # =>This Inner Loop Header: Depth=1
movq 32(%rsp), %rdi
movq 40(%rsp), %rsi
movl $209715200, %edx # imm = 0xC800000
movl $2, %ecx
xorl %r8d, %r8d
callq hipMemcpyAsync
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 48(%rsp), %rdi
callq hipEventSynchronize
decl %ebx
jne .LBB0_7
# %bb.8:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 12(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_13
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i13
cmpb $0, 56(%rbx)
je .LBB0_11
# %bb.10:
movzbl 67(%rbx), %ecx
jmp .LBB0_12
.LBB0_11:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit16
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_13:
.cfi_def_cfa_offset 80
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "without split by event\n"
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Time(ms): "
.size .L.str.1, 11
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "with split by event\n"
.size .L.str.2, 21
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <time.h>
__global__ void gpu_loop()
{
printf("GPU::This is iteration number %d\n", threadIdx.x);
}
__host__ void cpu_loop(int n)
{
for(int i = 0; i < n; i++)
printf("CPU::This is iteration number %d\n", i);
}
int main()
{
int n, b;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
printf("n, b?\n");
scanf("%d %d", &n, &b);
cudaEventRecord(start,0);
gpu_loop<<<b, n>>>();
//commented out the functions which helps to calculate time
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
float et;
cudaEventElapsedTime(&et, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
clock_t begin = clock();
cpu_loop(n);
clock_t end = clock();
double time_spent = (double)1000 * (end - begin) / CLOCKS_PER_SEC;
printf("GPU time: %f\n", et);
printf("CPU time: %f", time_spent);
} | code for sm_80
Function : _Z8gpu_loopv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0060*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe40007f1e0ff */
/*0070*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a60000000a00 */
/*0080*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*0090*/ STL [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013e80000100800 */
/*00a0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x002fc60000000000 */
/*00b0*/ MOV R11, 0x120 ; /* 0x00000120000b7802 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R20, 0xa0 ; /* 0x000000a000147802 */
/* 0x000fc40000000f00 */
/*00d0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*00f0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0100*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0110*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x004fea0003c00000 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <time.h>
__global__ void gpu_loop()
{
printf("GPU::This is iteration number %d\n", threadIdx.x);
}
__host__ void cpu_loop(int n)
{
for(int i = 0; i < n; i++)
printf("CPU::This is iteration number %d\n", i);
}
int main()
{
int n, b;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
printf("n, b?\n");
scanf("%d %d", &n, &b);
cudaEventRecord(start,0);
gpu_loop<<<b, n>>>();
//commented out the functions which helps to calculate time
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
float et;
cudaEventElapsedTime(&et, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
clock_t begin = clock();
cpu_loop(n);
clock_t end = clock();
double time_spent = (double)1000 * (end - begin) / CLOCKS_PER_SEC;
printf("GPU time: %f\n", et);
printf("CPU time: %f", time_spent);
} | .file "tmpxft_000b68ef_00000000-6_sample_shlee.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "CPU::This is iteration number %d\n"
.text
.globl _Z8cpu_loopi
.type _Z8cpu_loopi, @function
_Z8cpu_loopi:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L8
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %edi, %ebp
movl $0, %ebx
leaq .LC0(%rip), %r12
.L5:
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, %ebp
jne .L5
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE2057:
.size _Z8cpu_loopi, .-_Z8cpu_loopi
.globl _Z26__device_stub__Z8gpu_loopvv
.type _Z26__device_stub__Z8gpu_loopvv, @function
_Z26__device_stub__Z8gpu_loopvv:
.LFB2083:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8gpu_loopv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z26__device_stub__Z8gpu_loopvv, .-_Z26__device_stub__Z8gpu_loopvv
.globl _Z8gpu_loopv
.type _Z8gpu_loopv, @function
_Z8gpu_loopv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8gpu_loopvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z8gpu_loopv, .-_Z8gpu_loopv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "n, b?\n"
.LC2:
.string "%d %d"
.LC5:
.string "GPU time: %f\n"
.LC6:
.string "CPU time: %f"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $80, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 28(%rsp), %rdx
leaq 24(%rsp), %rsi
leaq .LC2(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl 24(%rsp), %eax
movl %eax, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl 28(%rsp), %eax
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 60(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
call clock@PLT
movq %rax, %rbx
movl 24(%rsp), %edi
call _Z8cpu_loopi
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC3(%rip), %xmm0
divsd .LC4(%rip), %xmm0
movsd %xmm0, 8(%rsp)
pxor %xmm0, %xmm0
cvtss2sd 60(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
call _Z26__device_stub__Z8gpu_loopvv
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z8gpu_loopv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z8gpu_loopv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1083129856
.align 8
.LC4:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <time.h>
__global__ void gpu_loop()
{
printf("GPU::This is iteration number %d\n", threadIdx.x);
}
__host__ void cpu_loop(int n)
{
for(int i = 0; i < n; i++)
printf("CPU::This is iteration number %d\n", i);
}
int main()
{
int n, b;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
printf("n, b?\n");
scanf("%d %d", &n, &b);
cudaEventRecord(start,0);
gpu_loop<<<b, n>>>();
//commented out the functions which helps to calculate time
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
float et;
cudaEventElapsedTime(&et, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
clock_t begin = clock();
cpu_loop(n);
clock_t end = clock();
double time_spent = (double)1000 * (end - begin) / CLOCKS_PER_SEC;
printf("GPU time: %f\n", et);
printf("CPU time: %f", time_spent);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
__global__ void gpu_loop()
{
printf("GPU::This is iteration number %d\n", threadIdx.x);
}
__host__ void cpu_loop(int n)
{
for(int i = 0; i < n; i++)
printf("CPU::This is iteration number %d\n", i);
}
int main()
{
int n, b;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
printf("n, b?\n");
scanf("%d %d", &n, &b);
hipEventRecord(start,0);
gpu_loop<<<b, n>>>();
//commented out the functions which helps to calculate time
hipEventRecord(stop,0);
hipEventSynchronize(stop);
float et;
hipEventElapsedTime(&et, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
clock_t begin = clock();
cpu_loop(n);
clock_t end = clock();
double time_spent = (double)1000 * (end - begin) / CLOCKS_PER_SEC;
printf("GPU time: %f\n", et);
printf("CPU time: %f", time_spent);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
__global__ void gpu_loop()
{
printf("GPU::This is iteration number %d\n", threadIdx.x);
}
__host__ void cpu_loop(int n)
{
for(int i = 0; i < n; i++)
printf("CPU::This is iteration number %d\n", i);
}
int main()
{
int n, b;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
printf("n, b?\n");
scanf("%d %d", &n, &b);
hipEventRecord(start,0);
gpu_loop<<<b, n>>>();
//commented out the functions which helps to calculate time
hipEventRecord(stop,0);
hipEventSynchronize(stop);
float et;
hipEventElapsedTime(&et, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
clock_t begin = clock();
cpu_loop(n);
clock_t end = clock();
double time_spent = (double)1000 * (end - begin) / CLOCKS_PER_SEC;
printf("GPU time: %f\n", et);
printf("CPU time: %f", time_spent);
} | .text
.file "sample_shlee.hip"
.globl _Z23__device_stub__gpu_loopv # -- Begin function _Z23__device_stub__gpu_loopv
.p2align 4, 0x90
.type _Z23__device_stub__gpu_loopv,@function
_Z23__device_stub__gpu_loopv: # @_Z23__device_stub__gpu_loopv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8gpu_loopv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__gpu_loopv, .Lfunc_end0-_Z23__device_stub__gpu_loopv
.cfi_endproc
# -- End function
.globl _Z8cpu_loopi # -- Begin function _Z8cpu_loopi
.p2align 4, 0x90
.type _Z8cpu_loopi,@function
_Z8cpu_loopi: # @_Z8cpu_loopi
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl %edi, %ebx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
incl %ebp
cmpl %ebp, %ebx
jne .LBB1_2
# %bb.3:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %rbp
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z8cpu_loopi, .Lfunc_end1-_Z8cpu_loopi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x408f400000000000 # double 1000
.LCPI2_1:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movl $.Lstr, %edi
callq puts@PLT
leaq 12(%rsp), %rsi
leaq 36(%rsp), %rdx
movl $.L.str.2, %edi
xorl %eax, %eax
callq __isoc23_scanf
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl 36(%rsp), %edi
movl 12(%rsp), %edx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
leaq 40(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8gpu_loopv, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 40(%rsp), %rdi
callq hipEventElapsedTime
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
callq clock
movq %rax, %rbx
movl 12(%rsp), %r14d
testl %r14d, %r14d
jle .LBB2_5
# %bb.3: # %.lr.ph.i.preheader
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_4: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $.L.str, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
incl %ebp
cmpl %ebp, %r14d
jne .LBB2_4
.LBB2_5: # %_Z8cpu_loopi.exit
callq clock
subq %rbx, %rax
cvtsi2sd %rax, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
divsd .LCPI2_1(%rip), %xmm0
movsd %xmm0, 56(%rsp) # 8-byte Spill
movss 40(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movl $.L.str.4, %edi
movsd 56(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8gpu_loopv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8gpu_loopv,@object # @_Z8gpu_loopv
.section .rodata,"a",@progbits
.globl _Z8gpu_loopv
.p2align 3, 0x0
_Z8gpu_loopv:
.quad _Z23__device_stub__gpu_loopv
.size _Z8gpu_loopv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CPU::This is iteration number %d\n"
.size .L.str, 34
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d %d"
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GPU time: %f\n"
.size .L.str.3, 14
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "CPU time: %f"
.size .L.str.4, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8gpu_loopv"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "n, b?"
.size .Lstr, 6
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__gpu_loopv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8gpu_loopv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b68ef_00000000-6_sample_shlee.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "CPU::This is iteration number %d\n"
.text
.globl _Z8cpu_loopi
.type _Z8cpu_loopi, @function
_Z8cpu_loopi:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L8
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %edi, %ebp
movl $0, %ebx
leaq .LC0(%rip), %r12
.L5:
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, %ebp
jne .L5
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE2057:
.size _Z8cpu_loopi, .-_Z8cpu_loopi
.globl _Z26__device_stub__Z8gpu_loopvv
.type _Z26__device_stub__Z8gpu_loopvv, @function
_Z26__device_stub__Z8gpu_loopvv:
.LFB2083:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z8gpu_loopv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z26__device_stub__Z8gpu_loopvv, .-_Z26__device_stub__Z8gpu_loopvv
.globl _Z8gpu_loopv
.type _Z8gpu_loopv, @function
_Z8gpu_loopv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z8gpu_loopvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z8gpu_loopv, .-_Z8gpu_loopv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "n, b?\n"
.LC2:
.string "%d %d"
.LC5:
.string "GPU time: %f\n"
.LC6:
.string "CPU time: %f"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $80, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 28(%rsp), %rdx
leaq 24(%rsp), %rsi
leaq .LC2(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl 24(%rsp), %eax
movl %eax, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl 28(%rsp), %eax
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 60(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
call clock@PLT
movq %rax, %rbx
movl 24(%rsp), %edi
call _Z8cpu_loopi
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC3(%rip), %xmm0
divsd .LC4(%rip), %xmm0
movsd %xmm0, 8(%rsp)
pxor %xmm0, %xmm0
cvtss2sd 60(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
call _Z26__device_stub__Z8gpu_loopvv
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z8gpu_loopv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z8gpu_loopv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1083129856
.align 8
.LC4:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sample_shlee.hip"
.globl _Z23__device_stub__gpu_loopv # -- Begin function _Z23__device_stub__gpu_loopv
.p2align 4, 0x90
.type _Z23__device_stub__gpu_loopv,@function
_Z23__device_stub__gpu_loopv: # @_Z23__device_stub__gpu_loopv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z8gpu_loopv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z23__device_stub__gpu_loopv, .Lfunc_end0-_Z23__device_stub__gpu_loopv
.cfi_endproc
# -- End function
.globl _Z8cpu_loopi # -- Begin function _Z8cpu_loopi
.p2align 4, 0x90
.type _Z8cpu_loopi,@function
_Z8cpu_loopi: # @_Z8cpu_loopi
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl %edi, %ebx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
incl %ebp
cmpl %ebp, %ebx
jne .LBB1_2
# %bb.3:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %rbp
.LBB1_4: # %._crit_edge
retq
.Lfunc_end1:
.size _Z8cpu_loopi, .Lfunc_end1-_Z8cpu_loopi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x408f400000000000 # double 1000
.LCPI2_1:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movl $.Lstr, %edi
callq puts@PLT
leaq 12(%rsp), %rsi
leaq 36(%rsp), %rdx
movl $.L.str.2, %edi
xorl %eax, %eax
callq __isoc23_scanf
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl 36(%rsp), %edi
movl 12(%rsp), %edx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
leaq 40(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8gpu_loopv, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 40(%rsp), %rdi
callq hipEventElapsedTime
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipEventDestroy
callq clock
movq %rax, %rbx
movl 12(%rsp), %r14d
testl %r14d, %r14d
jle .LBB2_5
# %bb.3: # %.lr.ph.i.preheader
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_4: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $.L.str, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
incl %ebp
cmpl %ebp, %r14d
jne .LBB2_4
.LBB2_5: # %_Z8cpu_loopi.exit
callq clock
subq %rbx, %rax
cvtsi2sd %rax, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
divsd .LCPI2_1(%rip), %xmm0
movsd %xmm0, 56(%rsp) # 8-byte Spill
movss 40(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movl $.L.str.4, %edi
movsd 56(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8gpu_loopv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8gpu_loopv,@object # @_Z8gpu_loopv
.section .rodata,"a",@progbits
.globl _Z8gpu_loopv
.p2align 3, 0x0
_Z8gpu_loopv:
.quad _Z23__device_stub__gpu_loopv
.size _Z8gpu_loopv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CPU::This is iteration number %d\n"
.size .L.str, 34
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d %d"
.size .L.str.2, 6
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GPU time: %f\n"
.size .L.str.3, 14
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "CPU time: %f"
.size .L.str.4, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8gpu_loopv"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "n, b?"
.size .Lstr, 6
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__gpu_loopv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8gpu_loopv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*************************************************
** Accelereyes Training Day 1 **
** Vector Addition **
** **
** This program will add two vectors and store **
** the result in a third vector using the GPU **
*************************************************/
#include <iostream>
#include <vector>
#include "cuda.h"
__global__ void add(int* a, int* b, int* c) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
c[id] = a[id] + b[id];
}
int main(void) {
using namespace std;
long N = 1000;
size_t size = N * sizeof(int);
// initialize device pointers and allocate memory on the GPU
int *d_a, *d_b, *d_c;
cudaMalloc(&d_a, size);
cudaMalloc(&d_b, size);
cudaMalloc(&d_c, size);
// initalize data on host
vector<int> h_a(N, 1);
vector<int> h_b(N, 2);
vector<int> h_c(N);
// move host data to the GPU
cudaMemcpy(d_a, &h_a.front(), size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, &h_b.front(), size, cudaMemcpyHostToDevice);
// launch kernel
int blocks = 10;
add <<< blocks, N/blocks >>> (d_a, d_b, d_c);
// get the results from the GPU
cudaMemcpy(&h_c.front(), d_c, size, cudaMemcpyDeviceToHost);
for(int i = 0; i < N; ++i) {
cout << h_c[i] << ", ";
}
return 0;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*************************************************
** Accelereyes Training Day 1 **
** Vector Addition **
** **
** This program will add two vectors and store **
** the result in a third vector using the GPU **
*************************************************/
#include <iostream>
#include <vector>
#include "cuda.h"
__global__ void add(int* a, int* b, int* c) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
c[id] = a[id] + b[id];
}
int main(void) {
using namespace std;
long N = 1000;
size_t size = N * sizeof(int);
// initialize device pointers and allocate memory on the GPU
int *d_a, *d_b, *d_c;
cudaMalloc(&d_a, size);
cudaMalloc(&d_b, size);
cudaMalloc(&d_c, size);
// initalize data on host
vector<int> h_a(N, 1);
vector<int> h_b(N, 2);
vector<int> h_c(N);
// move host data to the GPU
cudaMemcpy(d_a, &h_a.front(), size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, &h_b.front(), size, cudaMemcpyHostToDevice);
// launch kernel
int blocks = 10;
add <<< blocks, N/blocks >>> (d_a, d_b, d_c);
// get the results from the GPU
cudaMemcpy(&h_c.front(), d_c, size, cudaMemcpyDeviceToHost);
for(int i = 0; i < N; ++i) {
cout << h_c[i] << ", ";
}
return 0;
} | .file "tmpxft_0005de6d_00000000-6_vector_addition.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4035:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4035:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB4057:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4057:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB4058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4058:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEED2Ev
.type _ZNSt6vectorIiSaIiEED2Ev, @function
_ZNSt6vectorIiSaIiEED2Ev:
.LFB4371:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L16
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L16:
ret
.cfi_endproc
.LFE4371:
.size _ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev
.weak _ZNSt6vectorIiSaIiEED1Ev
.set _ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev
.section .rodata.str1.1
.LC1:
.string ", "
.text
.globl main
.type main, @function
main:
.LFB4032:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4032
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $152, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $4000, %esi
.LEHB0:
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
movl $4000, %edi
call _Znwm@PLT
.LEHE0:
movq %rax, %rbx
movq %rax, 48(%rsp)
leaq 4000(%rax), %rdx
movq %rdx, 64(%rsp)
.L20:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L20
movq %rdx, 56(%rsp)
movq $0, 88(%rsp)
movq $0, 96(%rsp)
movl $4000, %edi
.LEHB1:
call _Znwm@PLT
.LEHE1:
movq %rax, %r12
movq %rax, 80(%rsp)
leaq 4000(%rax), %rdx
movq %rdx, 96(%rsp)
.L21:
movl $2, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L21
movq %rdx, 88(%rsp)
movq $0, 120(%rsp)
movq $0, 128(%rsp)
movl $4000, %edi
.LEHB2:
call _Znwm@PLT
.LEHE2:
movq %rax, %rbp
movq %rax, 112(%rsp)
leaq 4000(%rax), %rdx
movq %rdx, 128(%rsp)
movl $0, (%rax)
leaq 4(%rax), %rax
.L22:
movl $0, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L22
movq %rdx, 120(%rsp)
movl $1, %ecx
movl $4000, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
.LEHB3:
call cudaMemcpy@PLT
movl $1, %ecx
movl $4000, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $100, 36(%rsp)
movl $1, 40(%rsp)
movl $10, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L23
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
.L23:
movl $2, %ecx
movl $4000, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq %rbp, %rbx
addq $4000, %rbp
leaq _ZSt4cout(%rip), %r12
leaq .LC1(%rip), %r13
jmp .L24
.L40:
movq %rax, %rdi
movl $2, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbp, %rbx
je .L39
.L24:
movl (%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
.LEHE3:
jmp .L40
.L39:
leaq 112(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
leaq 80(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
leaq 48(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 112(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
.L26:
leaq 80(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
.L27:
leaq 48(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L28
call __stack_chk_fail@PLT
.L31:
endbr64
movq %rax, %rbx
jmp .L26
.L30:
endbr64
movq %rax, %rbx
jmp .L27
.L28:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4032:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4032:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4032-.LLSDACSB4032
.LLSDACSB4032:
.uleb128 .LEHB0-.LFB4032
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4032
.uleb128 .LEHE1-.LEHB1
.uleb128 .L30-.LFB4032
.uleb128 0
.uleb128 .LEHB2-.LFB4032
.uleb128 .LEHE2-.LEHB2
.uleb128 .L31-.LFB4032
.uleb128 0
.uleb128 .LEHB3-.LFB4032
.uleb128 .LEHE3-.LEHB3
.uleb128 .L32-.LFB4032
.uleb128 0
.uleb128 .LEHB4-.LFB4032
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE4032:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*************************************************
** Accelereyes Training Day 1 **
** Vector Addition **
** **
** This program will add two vectors and store **
** the result in a third vector using the GPU **
*************************************************/
#include <iostream>
#include <vector>
#include "cuda.h"
__global__ void add(int* a, int* b, int* c) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
c[id] = a[id] + b[id];
}
int main(void) {
using namespace std;
long N = 1000;
size_t size = N * sizeof(int);
// initialize device pointers and allocate memory on the GPU
int *d_a, *d_b, *d_c;
cudaMalloc(&d_a, size);
cudaMalloc(&d_b, size);
cudaMalloc(&d_c, size);
// initalize data on host
vector<int> h_a(N, 1);
vector<int> h_b(N, 2);
vector<int> h_c(N);
// move host data to the GPU
cudaMemcpy(d_a, &h_a.front(), size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, &h_b.front(), size, cudaMemcpyHostToDevice);
// launch kernel
int blocks = 10;
add <<< blocks, N/blocks >>> (d_a, d_b, d_c);
// get the results from the GPU
cudaMemcpy(&h_c.front(), d_c, size, cudaMemcpyDeviceToHost);
for(int i = 0; i < N; ++i) {
cout << h_c[i] << ", ";
}
return 0;
} | /*************************************************
** Accelereyes Training Day 1 **
** Vector Addition **
** **
** This program will add two vectors and store **
** the result in a third vector using the GPU **
*************************************************/
#include <iostream>
#include <vector>
#include "hip/hip_runtime.h"
__global__ void add(int* a, int* b, int* c) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
c[id] = a[id] + b[id];
}
int main(void) {
using namespace std;
long N = 1000;
size_t size = N * sizeof(int);
// initialize device pointers and allocate memory on the GPU
int *d_a, *d_b, *d_c;
hipMalloc(&d_a, size);
hipMalloc(&d_b, size);
hipMalloc(&d_c, size);
// initalize data on host
vector<int> h_a(N, 1);
vector<int> h_b(N, 2);
vector<int> h_c(N);
// move host data to the GPU
hipMemcpy(d_a, &h_a.front(), size, hipMemcpyHostToDevice);
hipMemcpy(d_b, &h_b.front(), size, hipMemcpyHostToDevice);
// launch kernel
int blocks = 10;
add <<< blocks, N/blocks >>> (d_a, d_b, d_c);
// get the results from the GPU
hipMemcpy(&h_c.front(), d_c, size, hipMemcpyDeviceToHost);
for(int i = 0; i < N; ++i) {
cout << h_c[i] << ", ";
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*************************************************
** Accelereyes Training Day 1 **
** Vector Addition **
** **
** This program will add two vectors and store **
** the result in a third vector using the GPU **
*************************************************/
#include <iostream>
#include <vector>
#include "hip/hip_runtime.h"
__global__ void add(int* a, int* b, int* c) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
c[id] = a[id] + b[id];
}
int main(void) {
using namespace std;
long N = 1000;
size_t size = N * sizeof(int);
// initialize device pointers and allocate memory on the GPU
int *d_a, *d_b, *d_c;
hipMalloc(&d_a, size);
hipMalloc(&d_b, size);
hipMalloc(&d_c, size);
// initalize data on host
vector<int> h_a(N, 1);
vector<int> h_b(N, 2);
vector<int> h_c(N);
// move host data to the GPU
hipMemcpy(d_a, &h_a.front(), size, hipMemcpyHostToDevice);
hipMemcpy(d_b, &h_b.front(), size, hipMemcpyHostToDevice);
// launch kernel
int blocks = 10;
add <<< blocks, N/blocks >>> (d_a, d_b, d_c);
// get the results from the GPU
hipMemcpy(&h_c.front(), d_c, size, hipMemcpyDeviceToHost);
for(int i = 0; i < N; ++i) {
cout << h_c[i] << ", ";
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*************************************************
** Accelereyes Training Day 1 **
** Vector Addition **
** **
** This program will add two vectors and store **
** the result in a third vector using the GPU **
*************************************************/
#include <iostream>
#include <vector>
#include "hip/hip_runtime.h"
__global__ void add(int* a, int* b, int* c) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
c[id] = a[id] + b[id];
}
int main(void) {
using namespace std;
long N = 1000;
size_t size = N * sizeof(int);
// initialize device pointers and allocate memory on the GPU
int *d_a, *d_b, *d_c;
hipMalloc(&d_a, size);
hipMalloc(&d_b, size);
hipMalloc(&d_c, size);
// initalize data on host
vector<int> h_a(N, 1);
vector<int> h_b(N, 2);
vector<int> h_c(N);
// move host data to the GPU
hipMemcpy(d_a, &h_a.front(), size, hipMemcpyHostToDevice);
hipMemcpy(d_b, &h_b.front(), size, hipMemcpyHostToDevice);
// launch kernel
int blocks = 10;
add <<< blocks, N/blocks >>> (d_a, d_b, d_c);
// get the results from the GPU
hipMemcpy(&h_c.front(), d_c, size, hipMemcpyDeviceToHost);
for(int i = 0; i < N; ++i) {
cout << h_c[i] << ", ";
}
return 0;
} | .text
.file "vector_addition.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %.noexc
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
.cfi_escape 0x2e, 0x00
movq %rsp, %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
.cfi_escape 0x2e, 0x00
movl $4000, %edi # imm = 0xFA0
callq _Znwm
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # %.lr.ph.i.i.i.i.i.i.i.i.i
# =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%rax)
addq $4, %rax
cmpq $4000, %rax # imm = 0xFA0
jne .LBB1_1
# %bb.2: # %_ZNSt6vectorIiSaIiEEC2EmRKiRKS0_.exit
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $4000, %edi # imm = 0xFA0
callq _Znwm
.Ltmp1:
# %bb.3: # %.lr.ph.i.i.i.i.i.i.i.i.i33.preheader
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_4: # %.lr.ph.i.i.i.i.i.i.i.i.i33
# =>This Inner Loop Header: Depth=1
movl $2, (%r14,%rax)
addq $4, %rax
cmpq $4000, %rax # imm = 0xFA0
jne .LBB1_4
# %bb.5: # %_ZNSt6vectorIiSaIiEEC2EmRKiRKS0_.exit37
.Ltmp3:
.cfi_escape 0x2e, 0x00
movl $4000, %edi # imm = 0xFA0
callq _Znwm
.Ltmp4:
# %bb.6: # %_ZNSt6vectorIiSaIiEEC2EmRKS0_.exit
movq %rax, %r15
.cfi_escape 0x2e, 0x00
movl $4000, %edx # imm = 0xFA0
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movq 16(%rsp), %rdi
.Ltmp6:
.cfi_escape 0x2e, 0x00
movl $4000, %edx # imm = 0xFA0
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp7:
# %bb.7:
movq 8(%rsp), %rdi
.Ltmp8:
.cfi_escape 0x2e, 0x00
movl $4000, %edx # imm = 0xFA0
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp9:
# %bb.8:
.Ltmp11:
.cfi_escape 0x2e, 0x00
movabsq $4294967306, %rdi # imm = 0x10000000A
movabsq $4294967396, %rdx # imm = 0x100000064
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp12:
# %bb.9:
testl %eax, %eax
jne .LBB1_12
# %bb.10:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
.Ltmp13:
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp14:
# %bb.11: # %.noexc39
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
.Ltmp15:
.cfi_escape 0x2e, 0x10
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp16:
.LBB1_12:
movq (%rsp), %rsi
.Ltmp17:
.cfi_escape 0x2e, 0x00
movl $4000, %edx # imm = 0xFA0
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp18:
# %bb.13: # %.preheader.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_14: # %.preheader
# =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %esi
.Ltmp20:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSolsEi
.Ltmp21:
# %bb.15: # in Loop: Header=BB1_14 Depth=1
.Ltmp22:
.cfi_escape 0x2e, 0x00
movl $.L.str, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp23:
# %bb.16: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
# in Loop: Header=BB1_14 Depth=1
incq %r12
cmpq $1000, %r12 # imm = 0x3E8
jne .LBB1_14
# %bb.17: # %_ZNSt6vectorIiSaIiEED2Ev.exit
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_19:
.cfi_def_cfa_offset 160
.Ltmp5:
movq %rax, %r12
jmp .LBB1_24
.LBB1_18:
.Ltmp2:
movq %rax, %r12
jmp .LBB1_25
.LBB1_20:
.Ltmp10:
jmp .LBB1_23
.LBB1_21:
.Ltmp19:
jmp .LBB1_23
.LBB1_22:
.Ltmp24:
.LBB1_23: # %_ZNSt6vectorIiSaIiEED2Ev.exit47
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZdlPv
.LBB1_24: # %_ZNSt6vectorIiSaIiEED2Ev.exit49
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.LBB1_25: # %_ZNSt6vectorIiSaIiEED2Ev.exit51
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp6-.Ltmp4 # Call between .Ltmp4 and .Ltmp6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp9-.Ltmp6 # Call between .Ltmp6 and .Ltmp9
.uleb128 .Ltmp10-.Lfunc_begin0 # jumps to .Ltmp10
.byte 0 # On action: cleanup
.uleb128 .Ltmp11-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp18-.Ltmp11 # Call between .Ltmp11 and .Ltmp18
.uleb128 .Ltmp19-.Lfunc_begin0 # jumps to .Ltmp19
.byte 0 # On action: cleanup
.uleb128 .Ltmp20-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp23-.Ltmp20 # Call between .Ltmp20 and .Ltmp23
.uleb128 .Ltmp24-.Lfunc_begin0 # jumps to .Ltmp24
.byte 0 # On action: cleanup
.uleb128 .Ltmp23-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Lfunc_end1-.Ltmp23 # Call between .Ltmp23 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz ", "
.size .L.str, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z3addPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005de6d_00000000-6_vector_addition.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4035:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4035:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB4057:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4057:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB4058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4058:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEED2Ev
.type _ZNSt6vectorIiSaIiEED2Ev, @function
_ZNSt6vectorIiSaIiEED2Ev:
.LFB4371:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L16
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L16:
ret
.cfi_endproc
.LFE4371:
.size _ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev
.weak _ZNSt6vectorIiSaIiEED1Ev
.set _ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev
.section .rodata.str1.1
.LC1:
.string ", "
.text
.globl main
.type main, @function
main:
.LFB4032:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4032
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $152, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $4000, %esi
.LEHB0:
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
movl $4000, %edi
call _Znwm@PLT
.LEHE0:
movq %rax, %rbx
movq %rax, 48(%rsp)
leaq 4000(%rax), %rdx
movq %rdx, 64(%rsp)
.L20:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L20
movq %rdx, 56(%rsp)
movq $0, 88(%rsp)
movq $0, 96(%rsp)
movl $4000, %edi
.LEHB1:
call _Znwm@PLT
.LEHE1:
movq %rax, %r12
movq %rax, 80(%rsp)
leaq 4000(%rax), %rdx
movq %rdx, 96(%rsp)
.L21:
movl $2, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L21
movq %rdx, 88(%rsp)
movq $0, 120(%rsp)
movq $0, 128(%rsp)
movl $4000, %edi
.LEHB2:
call _Znwm@PLT
.LEHE2:
movq %rax, %rbp
movq %rax, 112(%rsp)
leaq 4000(%rax), %rdx
movq %rdx, 128(%rsp)
movl $0, (%rax)
leaq 4(%rax), %rax
.L22:
movl $0, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L22
movq %rdx, 120(%rsp)
movl $1, %ecx
movl $4000, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
.LEHB3:
call cudaMemcpy@PLT
movl $1, %ecx
movl $4000, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $100, 36(%rsp)
movl $1, 40(%rsp)
movl $10, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L23
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
.L23:
movl $2, %ecx
movl $4000, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq %rbp, %rbx
addq $4000, %rbp
leaq _ZSt4cout(%rip), %r12
leaq .LC1(%rip), %r13
jmp .L24
.L40:
movq %rax, %rdi
movl $2, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbp, %rbx
je .L39
.L24:
movl (%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
.LEHE3:
jmp .L40
.L39:
leaq 112(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
leaq 80(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
leaq 48(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 112(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
.L26:
leaq 80(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
.L27:
leaq 48(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 136(%rsp), %rax
subq %fs:40, %rax
je .L28
call __stack_chk_fail@PLT
.L31:
endbr64
movq %rax, %rbx
jmp .L26
.L30:
endbr64
movq %rax, %rbx
jmp .L27
.L28:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4032:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4032:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4032-.LLSDACSB4032
.LLSDACSB4032:
.uleb128 .LEHB0-.LFB4032
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4032
.uleb128 .LEHE1-.LEHB1
.uleb128 .L30-.LFB4032
.uleb128 0
.uleb128 .LEHB2-.LFB4032
.uleb128 .LEHE2-.LEHB2
.uleb128 .L31-.LFB4032
.uleb128 0
.uleb128 .LEHB3-.LFB4032
.uleb128 .LEHE3-.LEHB3
.uleb128 .L32-.LFB4032
.uleb128 0
.uleb128 .LEHB4-.LFB4032
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE4032:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vector_addition.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %.noexc
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
.cfi_escape 0x2e, 0x00
movq %rsp, %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
.cfi_escape 0x2e, 0x00
movl $4000, %edi # imm = 0xFA0
callq _Znwm
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # %.lr.ph.i.i.i.i.i.i.i.i.i
# =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%rax)
addq $4, %rax
cmpq $4000, %rax # imm = 0xFA0
jne .LBB1_1
# %bb.2: # %_ZNSt6vectorIiSaIiEEC2EmRKiRKS0_.exit
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $4000, %edi # imm = 0xFA0
callq _Znwm
.Ltmp1:
# %bb.3: # %.lr.ph.i.i.i.i.i.i.i.i.i33.preheader
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_4: # %.lr.ph.i.i.i.i.i.i.i.i.i33
# =>This Inner Loop Header: Depth=1
movl $2, (%r14,%rax)
addq $4, %rax
cmpq $4000, %rax # imm = 0xFA0
jne .LBB1_4
# %bb.5: # %_ZNSt6vectorIiSaIiEEC2EmRKiRKS0_.exit37
.Ltmp3:
.cfi_escape 0x2e, 0x00
movl $4000, %edi # imm = 0xFA0
callq _Znwm
.Ltmp4:
# %bb.6: # %_ZNSt6vectorIiSaIiEEC2EmRKS0_.exit
movq %rax, %r15
.cfi_escape 0x2e, 0x00
movl $4000, %edx # imm = 0xFA0
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movq 16(%rsp), %rdi
.Ltmp6:
.cfi_escape 0x2e, 0x00
movl $4000, %edx # imm = 0xFA0
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp7:
# %bb.7:
movq 8(%rsp), %rdi
.Ltmp8:
.cfi_escape 0x2e, 0x00
movl $4000, %edx # imm = 0xFA0
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp9:
# %bb.8:
.Ltmp11:
.cfi_escape 0x2e, 0x00
movabsq $4294967306, %rdi # imm = 0x10000000A
movabsq $4294967396, %rdx # imm = 0x100000064
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp12:
# %bb.9:
testl %eax, %eax
jne .LBB1_12
# %bb.10:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
.Ltmp13:
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp14:
# %bb.11: # %.noexc39
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
.Ltmp15:
.cfi_escape 0x2e, 0x10
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp16:
.LBB1_12:
movq (%rsp), %rsi
.Ltmp17:
.cfi_escape 0x2e, 0x00
movl $4000, %edx # imm = 0xFA0
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp18:
# %bb.13: # %.preheader.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_14: # %.preheader
# =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %esi
.Ltmp20:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSolsEi
.Ltmp21:
# %bb.15: # in Loop: Header=BB1_14 Depth=1
.Ltmp22:
.cfi_escape 0x2e, 0x00
movl $.L.str, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp23:
# %bb.16: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
# in Loop: Header=BB1_14 Depth=1
incq %r12
cmpq $1000, %r12 # imm = 0x3E8
jne .LBB1_14
# %bb.17: # %_ZNSt6vectorIiSaIiEED2Ev.exit
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_19:
.cfi_def_cfa_offset 160
.Ltmp5:
movq %rax, %r12
jmp .LBB1_24
.LBB1_18:
.Ltmp2:
movq %rax, %r12
jmp .LBB1_25
.LBB1_20:
.Ltmp10:
jmp .LBB1_23
.LBB1_21:
.Ltmp19:
jmp .LBB1_23
.LBB1_22:
.Ltmp24:
.LBB1_23: # %_ZNSt6vectorIiSaIiEED2Ev.exit47
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZdlPv
.LBB1_24: # %_ZNSt6vectorIiSaIiEED2Ev.exit49
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.LBB1_25: # %_ZNSt6vectorIiSaIiEED2Ev.exit51
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp6-.Ltmp4 # Call between .Ltmp4 and .Ltmp6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp9-.Ltmp6 # Call between .Ltmp6 and .Ltmp9
.uleb128 .Ltmp10-.Lfunc_begin0 # jumps to .Ltmp10
.byte 0 # On action: cleanup
.uleb128 .Ltmp11-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp18-.Ltmp11 # Call between .Ltmp11 and .Ltmp18
.uleb128 .Ltmp19-.Lfunc_begin0 # jumps to .Ltmp19
.byte 0 # On action: cleanup
.uleb128 .Ltmp20-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp23-.Ltmp20 # Call between .Ltmp20 and .Ltmp23
.uleb128 .Ltmp24-.Lfunc_begin0 # jumps to .Ltmp24
.byte 0 # On action: cleanup
.uleb128 .Ltmp23-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Lfunc_end1-.Ltmp23 # Call between .Ltmp23 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz ", "
.size .L.str, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z3addPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C"
{
__global__ void A_emult_Bg0_32(const int n, const float *a, const float *b, float *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{
if (b[i]>0.0)
{c[i] += a[i];}
else
{c[i] += 0.0;}
}
}
} | code for sm_80
Function : A_emult_Bg0_32
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R5, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ SHF.R.S32.HI R7, RZ, 0x1f, R0 ; /* 0x0000001fff077819 */
/* 0x000fe20000011400 */
/*00b0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x178] ; /* 0x00005e0000047625 */
/* 0x000fe200078e0205 */
/*00c0*/ FSETP.GT.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x004fda0003f04000 */
/*00d0*/ @P0 BRA 0x120 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*00e0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*00f0*/ FADD R3, RZ, R0 ; /* 0x00000000ff037221 */
/* 0x004fca0000000000 */
/*0100*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ LEA R2, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fc800078010ff */
/*0130*/ LEA.HI.X R3, R0, c[0x0][0x16c], R7, 0x2, P0 ; /* 0x00005b0000037a11 */
/* 0x000fe400000f1407 */
/*0140*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea8000c1e1900 */
/*0150*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*0160*/ FADD R7, R2, R7 ; /* 0x0000000702077221 */
/* 0x004fca0000000000 */
/*0170*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
{
__global__ void A_emult_Bg0_32(const int n, const float *a, const float *b, float *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{
if (b[i]>0.0)
{c[i] += a[i];}
else
{c[i] += 0.0;}
}
}
} | .file "tmpxft_0006e3ea_00000000-6_A_emult_Bg0_32.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z14A_emult_Bg0_32iPKfS0_PfiPKfS0_Pf
.type _Z41__device_stub__Z14A_emult_Bg0_32iPKfS0_PfiPKfS0_Pf, @function
_Z41__device_stub__Z14A_emult_Bg0_32iPKfS0_PfiPKfS0_Pf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq A_emult_Bg0_32(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z14A_emult_Bg0_32iPKfS0_PfiPKfS0_Pf, .-_Z41__device_stub__Z14A_emult_Bg0_32iPKfS0_PfiPKfS0_Pf
.globl A_emult_Bg0_32
.type A_emult_Bg0_32, @function
A_emult_Bg0_32:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z14A_emult_Bg0_32iPKfS0_PfiPKfS0_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size A_emult_Bg0_32, .-A_emult_Bg0_32
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "A_emult_Bg0_32"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq A_emult_Bg0_32(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
{
__global__ void A_emult_Bg0_32(const int n, const float *a, const float *b, float *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{
if (b[i]>0.0)
{c[i] += a[i];}
else
{c[i] += 0.0;}
}
}
} | #include <hip/hip_runtime.h>
extern "C"
{
__global__ void A_emult_Bg0_32(const int n, const float *a, const float *b, float *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{
if (b[i]>0.0)
{c[i] += a[i];}
else
{c[i] += 0.0;}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C"
{
__global__ void A_emult_Bg0_32(const int n, const float *a, const float *b, float *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{
if (b[i]>0.0)
{c[i] += a[i];}
else
{c[i] += 0.0;}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected A_emult_Bg0_32
.globl A_emult_Bg0_32
.p2align 8
.type A_emult_Bg0_32,@function
A_emult_Bg0_32:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_6
s_load_b128 s[4:7], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s3, 0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v6, vcc_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_nlt_f32_e32 0, v0
s_xor_b32 s2, exec_lo, s2
v_add_co_u32 v3, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v6, vcc_lo
s_or_saveexec_b32 s2, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v6, v4
v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v5, v3
s_xor_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_5
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
global_load_b32 v0, v[5:6], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v2, vcc_lo
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s2
global_load_b32 v1, v[3:4], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v1, v0
global_store_b32 v[5:6], v0, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel A_emult_Bg0_32
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size A_emult_Bg0_32, .Lfunc_end0-A_emult_Bg0_32
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: A_emult_Bg0_32
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: A_emult_Bg0_32.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C"
{
__global__ void A_emult_Bg0_32(const int n, const float *a, const float *b, float *c)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
if (i<n)
{
if (b[i]>0.0)
{c[i] += a[i];}
else
{c[i] += 0.0;}
}
}
} | .text
.file "A_emult_Bg0_32.hip"
.globl __device_stub__A_emult_Bg0_32 # -- Begin function __device_stub__A_emult_Bg0_32
.p2align 4, 0x90
.type __device_stub__A_emult_Bg0_32,@function
__device_stub__A_emult_Bg0_32: # @__device_stub__A_emult_Bg0_32
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $A_emult_Bg0_32, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__A_emult_Bg0_32, .Lfunc_end0-__device_stub__A_emult_Bg0_32
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $A_emult_Bg0_32, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type A_emult_Bg0_32,@object # @A_emult_Bg0_32
.section .rodata,"a",@progbits
.globl A_emult_Bg0_32
.p2align 3, 0x0
A_emult_Bg0_32:
.quad __device_stub__A_emult_Bg0_32
.size A_emult_Bg0_32, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "A_emult_Bg0_32"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__A_emult_Bg0_32
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym A_emult_Bg0_32
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : A_emult_Bg0_32
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R5, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ SHF.R.S32.HI R7, RZ, 0x1f, R0 ; /* 0x0000001fff077819 */
/* 0x000fe20000011400 */
/*00b0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x178] ; /* 0x00005e0000047625 */
/* 0x000fe200078e0205 */
/*00c0*/ FSETP.GT.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x004fda0003f04000 */
/*00d0*/ @P0 BRA 0x120 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*00e0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*00f0*/ FADD R3, RZ, R0 ; /* 0x00000000ff037221 */
/* 0x004fca0000000000 */
/*0100*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ LEA R2, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fc800078010ff */
/*0130*/ LEA.HI.X R3, R0, c[0x0][0x16c], R7, 0x2, P0 ; /* 0x00005b0000037a11 */
/* 0x000fe400000f1407 */
/*0140*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea8000c1e1900 */
/*0150*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*0160*/ FADD R7, R2, R7 ; /* 0x0000000702077221 */
/* 0x004fca0000000000 */
/*0170*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected A_emult_Bg0_32
.globl A_emult_Bg0_32
.p2align 8
.type A_emult_Bg0_32,@function
A_emult_Bg0_32:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_6
s_load_b128 s[4:7], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s3, 0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v6, vcc_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_nlt_f32_e32 0, v0
s_xor_b32 s2, exec_lo, s2
v_add_co_u32 v3, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v6, vcc_lo
s_or_saveexec_b32 s2, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v6, v4
v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v5, v3
s_xor_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_5
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
global_load_b32 v0, v[5:6], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v2, vcc_lo
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s2
global_load_b32 v1, v[3:4], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v1, v0
global_store_b32 v[5:6], v0, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel A_emult_Bg0_32
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size A_emult_Bg0_32, .Lfunc_end0-A_emult_Bg0_32
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: A_emult_Bg0_32
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: A_emult_Bg0_32.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006e3ea_00000000-6_A_emult_Bg0_32.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z14A_emult_Bg0_32iPKfS0_PfiPKfS0_Pf
.type _Z41__device_stub__Z14A_emult_Bg0_32iPKfS0_PfiPKfS0_Pf, @function
_Z41__device_stub__Z14A_emult_Bg0_32iPKfS0_PfiPKfS0_Pf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq A_emult_Bg0_32(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z14A_emult_Bg0_32iPKfS0_PfiPKfS0_Pf, .-_Z41__device_stub__Z14A_emult_Bg0_32iPKfS0_PfiPKfS0_Pf
.globl A_emult_Bg0_32
.type A_emult_Bg0_32, @function
A_emult_Bg0_32:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z14A_emult_Bg0_32iPKfS0_PfiPKfS0_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size A_emult_Bg0_32, .-A_emult_Bg0_32
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "A_emult_Bg0_32"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq A_emult_Bg0_32(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "A_emult_Bg0_32.hip"
.globl __device_stub__A_emult_Bg0_32 # -- Begin function __device_stub__A_emult_Bg0_32
.p2align 4, 0x90
.type __device_stub__A_emult_Bg0_32,@function
__device_stub__A_emult_Bg0_32: # @__device_stub__A_emult_Bg0_32
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $A_emult_Bg0_32, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__A_emult_Bg0_32, .Lfunc_end0-__device_stub__A_emult_Bg0_32
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $A_emult_Bg0_32, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type A_emult_Bg0_32,@object # @A_emult_Bg0_32
.section .rodata,"a",@progbits
.globl A_emult_Bg0_32
.p2align 3, 0x0
A_emult_Bg0_32:
.quad __device_stub__A_emult_Bg0_32
.size A_emult_Bg0_32, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "A_emult_Bg0_32"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__A_emult_Bg0_32
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym A_emult_Bg0_32
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <math.h>
// Tells the CUDA C++ compiler that this is a function (kernel) that runs on the GPU and can be called from CPU code
// These __global__ functions are known as kernels, and code that runs on the GPU is often called device code, while code that runs on the CPU is host code.
__global__ void add(int n, float *x, float *y) {
for (int i = 0; i < n; ++i) {
y[i] = x[i] + y[i];
}
}
int main() {
int N = 1 << 20; // 1M
float *x, *y;
// Allocate Unified Memory – accessible from CPU or GPU
cudaMallocManaged(&x, N * sizeof(float));
cudaMallocManaged(&y, N * sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; ++i) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Run kernel on 1M elements on the GPU
add<<<1, 1>>>(N, x, y);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
float max_error = 0.0f;
for (int i = 0; i < N; ++i) {
max_error = fmax(max_error, fabs(y[i] - 3.0f));
}
std::cout << "max error: " << max_error << std::endl;
// free memory
cudaFree(x);
cudaFree(y);
return 0;
} | code for sm_80
Function : _Z3addiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0050*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0060*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0070*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe20000000a00 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0090*/ @!P0 BRA 0xaa0 ; /* 0x00000a0000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R6, -R0, c[0x0][0x160], RZ ; /* 0x0000580000067a10 */
/* 0x000fe20007ffe1ff */
/*00b0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00c0*/ MOV R4, c[0x0][0x170] ; /* 0x00005c0000047a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fe200078e00ff */
/*00e0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f04270 */
/*00f0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe200078e00ff */
/*0100*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fd60000000f00 */
/*0110*/ @!P0 BRA 0x8f0 ; /* 0x000007d000008947 */
/* 0x000fea0003800000 */
/*0120*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0130*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0140*/ @!P1 BRA 0x610 ; /* 0x000004c000009947 */
/* 0x000fea0003800000 */
/*0150*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0160*/ LDG.E R7, [R4.64] ; /* 0x0000000a04077981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R8, [R2.64] ; /* 0x0000000a02087981 */
/* 0x000ea4000c1e1900 */
/*0180*/ FADD R7, R7, R8 ; /* 0x0000000807077221 */
/* 0x004fe40000000000 */
/*0190*/ LDG.E R8, [R4.64+0x4] ; /* 0x0000040a04087981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e8000c10190a */
/*01b0*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040a02097981 */
/* 0x000ea8000c1e1900 */
/*01c0*/ LDG.E R7, [R4.64+0x10] ; /* 0x0000100a04077981 */
/* 0x001ee2000c1e1900 */
/*01d0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fc60000000000 */
/*01e0*/ LDG.E R8, [R4.64+0x8] ; /* 0x0000080a04087981 */
/* 0x000ea8000c1e1900 */
/*01f0*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x0001e8000c10190a */
/*0200*/ LDG.E R11, [R2.64+0x8] ; /* 0x0000080a020b7981 */
/* 0x000ea4000c1e1900 */
/*0210*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x004fc40000000000 */
/*0220*/ LDG.E R8, [R4.64+0xc] ; /* 0x00000c0a04087981 */
/* 0x000ea8000c1e1900 */
/*0230*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x000fe8000c10190a */
/*0240*/ LDG.E R13, [R2.64+0xc] ; /* 0x00000c0a020d7981 */
/* 0x000ea4000c1e1900 */
/*0250*/ FADD R13, R8, R13 ; /* 0x0000000d080d7221 */
/* 0x004fca0000000000 */
/*0260*/ STG.E [R4.64+0xc], R13 ; /* 0x00000c0d04007986 */
/* 0x000fe8000c10190a */
/*0270*/ LDG.E R8, [R2.64+0x10] ; /* 0x0000100a02087981 */
/* 0x000ee4000c1e1900 */
/*0280*/ FADD R7, R7, R8 ; /* 0x0000000807077221 */
/* 0x008fe40000000000 */
/*0290*/ LDG.E R8, [R4.64+0x14] ; /* 0x0000140a04087981 */
/* 0x000ea8000c1e1900 */
/*02a0*/ STG.E [R4.64+0x10], R7 ; /* 0x0000100704007986 */
/* 0x0003e8000c10190a */
/*02b0*/ LDG.E R9, [R2.64+0x14] ; /* 0x0000140a02097981 */
/* 0x001ea8000c1e1900 */
/*02c0*/ LDG.E R7, [R4.64+0x20] ; /* 0x0000200a04077981 */
/* 0x002ee2000c1e1900 */
/*02d0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fc60000000000 */
/*02e0*/ LDG.E R8, [R4.64+0x18] ; /* 0x0000180a04087981 */
/* 0x000ea8000c1e1900 */
/*02f0*/ STG.E [R4.64+0x14], R9 ; /* 0x0000140904007986 */
/* 0x0001e8000c10190a */
/*0300*/ LDG.E R11, [R2.64+0x18] ; /* 0x0000180a020b7981 */
/* 0x000ea4000c1e1900 */
/*0310*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x004fc40000000000 */
/*0320*/ LDG.E R8, [R4.64+0x1c] ; /* 0x00001c0a04087981 */
/* 0x000ea8000c1e1900 */
/*0330*/ STG.E [R4.64+0x18], R11 ; /* 0x0000180b04007986 */
/* 0x000fe8000c10190a */
/*0340*/ LDG.E R13, [R2.64+0x1c] ; /* 0x00001c0a020d7981 */
/* 0x000ea4000c1e1900 */
/*0350*/ FADD R13, R8, R13 ; /* 0x0000000d080d7221 */
/* 0x004fca0000000000 */
/*0360*/ STG.E [R4.64+0x1c], R13 ; /* 0x00001c0d04007986 */
/* 0x000fe8000c10190a */
/*0370*/ LDG.E R8, [R2.64+0x20] ; /* 0x0000200a02087981 */
/* 0x000ee4000c1e1900 */
/*0380*/ FADD R7, R7, R8 ; /* 0x0000000807077221 */
/* 0x008fe40000000000 */
/*0390*/ LDG.E R8, [R4.64+0x24] ; /* 0x0000240a04087981 */
/* 0x000ea8000c1e1900 */
/*03a0*/ STG.E [R4.64+0x20], R7 ; /* 0x0000200704007986 */
/* 0x0003e8000c10190a */
/*03b0*/ LDG.E R9, [R2.64+0x24] ; /* 0x0000240a02097981 */
/* 0x001ea8000c1e1900 */
/*03c0*/ LDG.E R7, [R4.64+0x30] ; /* 0x0000300a04077981 */
/* 0x002ee2000c1e1900 */
/*03d0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fc60000000000 */
/*03e0*/ LDG.E R8, [R4.64+0x28] ; /* 0x0000280a04087981 */
/* 0x000ea8000c1e1900 */
/*03f0*/ STG.E [R4.64+0x24], R9 ; /* 0x0000240904007986 */
/* 0x0001e8000c10190a */
/*0400*/ LDG.E R11, [R2.64+0x28] ; /* 0x0000280a020b7981 */
/* 0x000ea4000c1e1900 */
/*0410*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x004fc40000000000 */
/*0420*/ LDG.E R8, [R4.64+0x2c] ; /* 0x00002c0a04087981 */
/* 0x000ea8000c1e1900 */
/*0430*/ STG.E [R4.64+0x28], R11 ; /* 0x0000280b04007986 */
/* 0x0003e8000c10190a */
/*0440*/ LDG.E R13, [R2.64+0x2c] ; /* 0x00002c0a020d7981 */
/* 0x000ea4000c1e1900 */
/*0450*/ FADD R13, R8, R13 ; /* 0x0000000d080d7221 */
/* 0x004fca0000000000 */
/*0460*/ STG.E [R4.64+0x2c], R13 ; /* 0x00002c0d04007986 */
/* 0x0005e8000c10190a */
/*0470*/ LDG.E R8, [R2.64+0x30] ; /* 0x0000300a02087981 */
/* 0x000ee4000c1e1900 */
/*0480*/ FADD R7, R7, R8 ; /* 0x0000000807077221 */
/* 0x008fe40000000000 */
/*0490*/ LDG.E R8, [R4.64+0x34] ; /* 0x0000340a04087981 */
/* 0x000ee8000c1e1900 */
/*04a0*/ STG.E [R4.64+0x30], R7 ; /* 0x0000300704007986 */
/* 0x0009e8000c10190a */
/*04b0*/ LDG.E R9, [R2.64+0x34] ; /* 0x0000340a02097981 */
/* 0x001ee4000c1e1900 */
/*04c0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x008fc40000000000 */
/*04d0*/ LDG.E R8, [R4.64+0x38] ; /* 0x0000380a04087981 */
/* 0x000ee8000c1e1900 */
/*04e0*/ STG.E [R4.64+0x34], R9 ; /* 0x0000340904007986 */
/* 0x000fe8000c10190a */
/*04f0*/ LDG.E R11, [R2.64+0x38] ; /* 0x0000380a020b7981 */
/* 0x002ee2000c1e1900 */
/*0500*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fe20007ffe0ff */
/*0510*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x008fc40000000000 */
/*0520*/ LDG.E R8, [R4.64+0x3c] ; /* 0x00003c0a04087981 */
/* 0x000ee8000c1e1900 */
/*0530*/ STG.E [R4.64+0x38], R11 ; /* 0x0000380b04007986 */
/* 0x000fe8000c10190a */
/*0540*/ LDG.E R13, [R2.64+0x3c] ; /* 0x00003c0a020d7981 */
/* 0x0040e2000c1e1900 */
/*0550*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0560*/ IADD3 R7, P3, R4, 0x40, RZ ; /* 0x0000004004077810 */
/* 0x010fe20007f7e0ff */
/*0570*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*0580*/ IADD3 R10, P2, R2, 0x40, RZ ; /* 0x00000040020a7810 */
/* 0x000fc80007f5e0ff */
/*0590*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */
/* 0x001fe400017fe4ff */
/*05a0*/ MOV R2, R10 ; /* 0x0000000a00027202 */
/* 0x000fe20000000f00 */
/*05b0*/ FADD R13, R8, R13 ; /* 0x0000000d080d7221 */
/* 0x008fe40000000000 */
/*05c0*/ IMAD.X R8, RZ, RZ, R5, P3 ; /* 0x000000ffff087224 */
/* 0x000fc600018e0605 */
/*05d0*/ STG.E [R4.64+0x3c], R13 ; /* 0x00003c0d04007986 */
/* 0x0001e4000c10190a */
/*05e0*/ IMAD.MOV.U32 R4, RZ, RZ, R7 ; /* 0x000000ffff047224 */
/* 0x001fe200078e0007 */
/*05f0*/ MOV R5, R8 ; /* 0x0000000800057202 */
/* 0x000fe20000000f00 */
/*0600*/ @P1 BRA 0x160 ; /* 0xfffffb5000001947 */
/* 0x000fea000383ffff */
/*0610*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0620*/ @!P1 BRA 0x8d0 ; /* 0x000002a000009947 */
/* 0x000fea0003800000 */
/*0630*/ LDG.E R7, [R4.64] ; /* 0x0000000a04077981 */
/* 0x000ea8000c1e1900 */
/*0640*/ LDG.E R8, [R2.64] ; /* 0x0000000a02087981 */
/* 0x000ea4000c1e1900 */
/*0650*/ FADD R7, R7, R8 ; /* 0x0000000807077221 */
/* 0x004fe40000000000 */
/*0660*/ LDG.E R8, [R4.64+0x4] ; /* 0x0000040a04087981 */
/* 0x000ea8000c1e1900 */
/*0670*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e8000c10190a */
/*0680*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040a02097981 */
/* 0x000ea8000c1e1900 */
/*0690*/ LDG.E R7, [R4.64+0x10] ; /* 0x0000100a04077981 */
/* 0x001ee2000c1e1900 */
/*06a0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fc60000000000 */
/*06b0*/ LDG.E R8, [R4.64+0x8] ; /* 0x0000080a04087981 */
/* 0x000ea8000c1e1900 */
/*06c0*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x0001e8000c10190a */
/*06d0*/ LDG.E R11, [R2.64+0x8] ; /* 0x0000080a020b7981 */
/* 0x000ea4000c1e1900 */
/*06e0*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x004fc40000000000 */
/*06f0*/ LDG.E R8, [R4.64+0xc] ; /* 0x00000c0a04087981 */
/* 0x000ea8000c1e1900 */
/*0700*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x0003e8000c10190a */
/*0710*/ LDG.E R13, [R2.64+0xc] ; /* 0x00000c0a020d7981 */
/* 0x000ea4000c1e1900 */
/*0720*/ FADD R13, R8, R13 ; /* 0x0000000d080d7221 */
/* 0x004fca0000000000 */
/*0730*/ STG.E [R4.64+0xc], R13 ; /* 0x00000c0d04007986 */
/* 0x0005e8000c10190a */
/*0740*/ LDG.E R8, [R2.64+0x10] ; /* 0x0000100a02087981 */
/* 0x000ee4000c1e1900 */
/*0750*/ FADD R7, R7, R8 ; /* 0x0000000807077221 */
/* 0x008fe40000000000 */
/*0760*/ LDG.E R8, [R4.64+0x14] ; /* 0x0000140a04087981 */
/* 0x000ee8000c1e1900 */
/*0770*/ STG.E [R4.64+0x10], R7 ; /* 0x0000100704007986 */
/* 0x0009e8000c10190a */
/*0780*/ LDG.E R9, [R2.64+0x14] ; /* 0x0000140a02097981 */
/* 0x001ee4000c1e1900 */
/*0790*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x008fc40000000000 */
/*07a0*/ LDG.E R8, [R4.64+0x18] ; /* 0x0000180a04087981 */
/* 0x000ee8000c1e1900 */
/*07b0*/ STG.E [R4.64+0x14], R9 ; /* 0x0000140904007986 */
/* 0x000fe8000c10190a */
/*07c0*/ LDG.E R11, [R2.64+0x18] ; /* 0x0000180a020b7981 */
/* 0x002ee4000c1e1900 */
/*07d0*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x008fc40000000000 */
/*07e0*/ LDG.E R8, [R4.64+0x1c] ; /* 0x00001c0a04087981 */
/* 0x000ee8000c1e1900 */
/*07f0*/ STG.E [R4.64+0x18], R11 ; /* 0x0000180b04007986 */
/* 0x000fe8000c10190a */
/*0800*/ LDG.E R13, [R2.64+0x1c] ; /* 0x00001c0a020d7981 */
/* 0x0040e2000c1e1900 */
/*0810*/ IADD3 R7, P2, R4, 0x20, RZ ; /* 0x0000002004077810 */
/* 0x010fe40007f5e0ff */
/*0820*/ IADD3 R10, P1, R2, 0x20, RZ ; /* 0x00000020020a7810 */
/* 0x000fc40007f3e0ff */
/*0830*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0840*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0850*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x001fe400008e0603 */
/*0860*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x000fe200078e000a */
/*0870*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0880*/ FADD R13, R8, R13 ; /* 0x0000000d080d7221 */
/* 0x008fe20000000000 */
/*0890*/ IADD3.X R8, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff087210 */
/* 0x000fc800017fe4ff */
/*08a0*/ STG.E [R4.64+0x1c], R13 ; /* 0x00001c0d04007986 */
/* 0x0001e4000c10190a */
/*08b0*/ MOV R4, R7 ; /* 0x0000000700047202 */
/* 0x001fe20000000f00 */
/*08c0*/ IMAD.MOV.U32 R5, RZ, RZ, R8 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0008 */
/*08d0*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*08e0*/ @!P0 BRA 0xaa0 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*08f0*/ LDG.E R7, [R4.64] ; /* 0x0000000a04077981 */
/* 0x000ea8000c1e1900 */
/*0900*/ LDG.E R8, [R2.64] ; /* 0x0000000a02087981 */
/* 0x000ea4000c1e1900 */
/*0910*/ FADD R7, R7, R8 ; /* 0x0000000807077221 */
/* 0x004fe40000000000 */
/*0920*/ LDG.E R8, [R4.64+0x4] ; /* 0x0000040a04087981 */
/* 0x000ea8000c1e1900 */
/*0930*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e8000c10190a */
/*0940*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040a02097981 */
/* 0x000ea4000c1e1900 */
/*0950*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fc40000000000 */
/*0960*/ LDG.E R8, [R4.64+0x8] ; /* 0x0000080a04087981 */
/* 0x000ea8000c1e1900 */
/*0970*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x000fe8000c10190a */
/*0980*/ LDG.E R11, [R2.64+0x8] ; /* 0x0000080a020b7981 */
/* 0x000ea2000c1e1900 */
/*0990*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fe20007ffe0ff */
/*09a0*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x004fc40000000000 */
/*09b0*/ LDG.E R8, [R4.64+0xc] ; /* 0x00000c0a04087981 */
/* 0x000ea8000c1e1900 */
/*09c0*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x000fe8000c10190a */
/*09d0*/ LDG.E R13, [R2.64+0xc] ; /* 0x00000c0a020d7981 */
/* 0x0002a2000c1e1900 */
/*09e0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*09f0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0a00*/ IADD3 R7, P2, R4, 0x10, RZ ; /* 0x0000001004077810 */
/* 0x001fc40007f5e0ff */
/*0a10*/ IADD3 R10, P1, R2, 0x10, RZ ; /* 0x00000010020a7810 */
/* 0x000fc80007f3e0ff */
/*0a20*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x002fe40000ffe4ff */
/*0a30*/ MOV R2, R10 ; /* 0x0000000a00027202 */
/* 0x000fe20000000f00 */
/*0a40*/ FADD R13, R8, R13 ; /* 0x0000000d080d7221 */
/* 0x004fe40000000000 */
/*0a50*/ IMAD.X R8, RZ, RZ, R5, P2 ; /* 0x000000ffff087224 */
/* 0x000fc600010e0605 */
/*0a60*/ STG.E [R4.64+0xc], R13 ; /* 0x00000c0d04007986 */
/* 0x0001e4000c10190a */
/*0a70*/ IMAD.MOV.U32 R4, RZ, RZ, R7 ; /* 0x000000ffff047224 */
/* 0x001fe200078e0007 */
/*0a80*/ MOV R5, R8 ; /* 0x0000000800057202 */
/* 0x000fe20000000f00 */
/*0a90*/ @P0 BRA 0x8f0 ; /* 0xfffffe5000000947 */
/* 0x000fea000383ffff */
/*0aa0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0ab0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0ac0*/ UMOV UR5, 0x4 ; /* 0x0000000400057882 */
/* 0x000fe40000000000 */
/*0ad0*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe40000000a00 */
/*0ae0*/ UIMAD.WIDE UR6, UR4, UR5, UR6 ; /* 0x00000005040672a5 */
/* 0x000fe4000f8e0206 */
/*0af0*/ ULDC.64 UR8, c[0x0][0x168] ; /* 0x00005a0000087ab9 */
/* 0x000fe40000000a00 */
/*0b00*/ UIMAD.WIDE UR4, UR4, UR5, UR8 ; /* 0x00000005040472a5 */
/* 0x000fe4000f8e0208 */
/*0b10*/ IMAD.U32 R2, RZ, RZ, UR6 ; /* 0x00000006ff027e24 */
/* 0x000fe2000f8e00ff */
/*0b20*/ MOV R5, UR7 ; /* 0x0000000700057c02 */
/* 0x000fe20008000f00 */
/*0b30*/ IMAD.U32 R4, RZ, RZ, UR6 ; /* 0x00000006ff047e24 */
/* 0x000fe2000f8e00ff */
/*0b40*/ MOV R3, UR7 ; /* 0x0000000700037c02 */
/* 0x000fe20008000f00 */
/*0b50*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0002 */
/*0b60*/ MOV R9, R5 ; /* 0x0000000500097202 */
/* 0x000fc40000000f00 */
/*0b70*/ MOV R5, UR5 ; /* 0x0000000500057c02 */
/* 0x000fe20008000f00 */
/*0b80*/ IMAD.U32 R4, RZ, RZ, UR4 ; /* 0x00000004ff047e24 */
/* 0x000fe2000f8e00ff */
/*0b90*/ MOV R3, R9 ; /* 0x0000000900037202 */
/* 0x001fe20000000f00 */
/*0ba0*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fc600078e0006 */
/*0bb0*/ LDG.E R5, [R4.64] ; /* 0x0000000a04057981 */
/* 0x000ea8000c1e1900 */
/*0bc0*/ LDG.E R6, [R2.64] ; /* 0x0000000a02067981 */
/* 0x000ea2000c1e1900 */
/*0bd0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc80007ffe0ff */
/*0be0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0bf0*/ UIADD3 UR4, UP0, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fc8000ff1e03f */
/*0c00*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*0c10*/ FADD R7, R6, R5 ; /* 0x0000000506077221 */
/* 0x004fe20000000000 */
/*0c20*/ IADD3 R6, P1, R2, 0x4, RZ ; /* 0x0000000402067810 */
/* 0x000fc80007f3e0ff */
/*0c30*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e2000c10190a */
/*0c40*/ IADD3.X R9, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff097210 */
/* 0x000fe20000ffe4ff */
/*0c50*/ @P0 BRA 0xb70 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*0c60*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c70*/ BRA 0xc70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <math.h>
// Tells the CUDA C++ compiler that this is a function (kernel) that runs on the GPU and can be called from CPU code
// These __global__ functions are known as kernels, and code that runs on the GPU is often called device code, while code that runs on the CPU is host code.
__global__ void add(int n, float *x, float *y) {
for (int i = 0; i < n; ++i) {
y[i] = x[i] + y[i];
}
}
int main() {
int N = 1 << 20; // 1M
float *x, *y;
// Allocate Unified Memory – accessible from CPU or GPU
cudaMallocManaged(&x, N * sizeof(float));
cudaMallocManaged(&y, N * sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; ++i) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Run kernel on 1M elements on the GPU
add<<<1, 1>>>(N, x, y);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
float max_error = 0.0f;
for (int i = 0; i < N; ++i) {
max_error = fmax(max_error, fabs(y[i] - 3.0f));
}
std::cout << "max error: " << max_error << std::endl;
// free memory
cudaFree(x);
cudaFree(y);
return 0;
} | .file "tmpxft_0012f271_00000000-6_add.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z3addiPfS_iPfS_
.type _Z25__device_stub__Z3addiPfS_iPfS_, @function
_Z25__device_stub__Z3addiPfS_iPfS_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z25__device_stub__Z3addiPfS_iPfS_, .-_Z25__device_stub__Z3addiPfS_iPfS_
.globl _Z3addiPfS_
.type _Z3addiPfS_, @function
_Z3addiPfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3addiPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3addiPfS_, .-_Z3addiPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "max error: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
movl $0, %eax
movss .LC1(%rip), %xmm1
movss .LC2(%rip), %xmm0
.L12:
movq 16(%rsp), %rdx
movss %xmm1, (%rdx,%rax)
movq 24(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L12
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call cudaDeviceSynchronize@PLT
movq 24(%rsp), %rbx
leaq 4194304(%rbx), %rbp
movl $0x00000000, 12(%rsp)
.L14:
movss (%rbx), %xmm0
subss .LC3(%rip), %xmm0
andps .LC4(%rip), %xmm0
movss 12(%rsp), %xmm1
call fmaxf@PLT
movss %xmm0, 12(%rsp)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L14
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movl $1048576, %edi
call _Z25__device_stub__Z3addiPfS_iPfS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z3addiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1073741824
.align 4
.LC3:
.long 1077936128
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <math.h>
// Tells the CUDA C++ compiler that this is a function (kernel) that runs on the GPU and can be called from CPU code
// These __global__ functions are known as kernels, and code that runs on the GPU is often called device code, while code that runs on the CPU is host code.
__global__ void add(int n, float *x, float *y) {
for (int i = 0; i < n; ++i) {
y[i] = x[i] + y[i];
}
}
int main() {
int N = 1 << 20; // 1M
float *x, *y;
// Allocate Unified Memory – accessible from CPU or GPU
cudaMallocManaged(&x, N * sizeof(float));
cudaMallocManaged(&y, N * sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; ++i) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Run kernel on 1M elements on the GPU
add<<<1, 1>>>(N, x, y);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
float max_error = 0.0f;
for (int i = 0; i < N; ++i) {
max_error = fmax(max_error, fabs(y[i] - 3.0f));
}
std::cout << "max error: " << max_error << std::endl;
// free memory
cudaFree(x);
cudaFree(y);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
// Tells the CUDA C++ compiler that this is a function (kernel) that runs on the GPU and can be called from CPU code
// These __global__ functions are known as kernels, and code that runs on the GPU is often called device code, while code that runs on the CPU is host code.
__global__ void add(int n, float *x, float *y) {
for (int i = 0; i < n; ++i) {
y[i] = x[i] + y[i];
}
}
int main() {
int N = 1 << 20; // 1M
float *x, *y;
// Allocate Unified Memory – accessible from CPU or GPU
hipMallocManaged(&x, N * sizeof(float));
hipMallocManaged(&y, N * sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; ++i) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Run kernel on 1M elements on the GPU
add<<<1, 1>>>(N, x, y);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
float max_error = 0.0f;
for (int i = 0; i < N; ++i) {
max_error = fmax(max_error, fabs(y[i] - 3.0f));
}
std::cout << "max error: " << max_error << std::endl;
// free memory
hipFree(x);
hipFree(y);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
// Tells the CUDA C++ compiler that this is a function (kernel) that runs on the GPU and can be called from CPU code
// These __global__ functions are known as kernels, and code that runs on the GPU is often called device code, while code that runs on the CPU is host code.
__global__ void add(int n, float *x, float *y) {
for (int i = 0; i < n; ++i) {
y[i] = x[i] + y[i];
}
}
int main() {
int N = 1 << 20; // 1M
float *x, *y;
// Allocate Unified Memory – accessible from CPU or GPU
hipMallocManaged(&x, N * sizeof(float));
hipMallocManaged(&y, N * sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; ++i) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Run kernel on 1M elements on the GPU
add<<<1, 1>>>(N, x, y);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
float max_error = 0.0f;
for (int i = 0; i < N; ++i) {
max_error = fmax(max_error, fabs(y[i] - 3.0f));
}
std::cout << "max error: " << max_error << std::endl;
// free memory
hipFree(x);
hipFree(y);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiPfS_
.globl _Z3addiPfS_
.p2align 8
.type _Z3addiPfS_,@function
_Z3addiPfS_:
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[0:3], s[0:1], 0x8
v_mov_b32_e32 v0, 0
.LBB0_2:
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[0:1]
global_load_b32 v2, v0, s[2:3]
s_add_i32 s4, s4, -1
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[2:3]
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s4, 0
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 5
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiPfS_, .Lfunc_end0-_Z3addiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 5
.sgpr_spill_count: 0
.symbol: _Z3addiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
// Tells the CUDA C++ compiler that this is a function (kernel) that runs on the GPU and can be called from CPU code
// These __global__ functions are known as kernels, and code that runs on the GPU is often called device code, while code that runs on the CPU is host code.
__global__ void add(int n, float *x, float *y) {
for (int i = 0; i < n; ++i) {
y[i] = x[i] + y[i];
}
}
int main() {
int N = 1 << 20; // 1M
float *x, *y;
// Allocate Unified Memory – accessible from CPU or GPU
hipMallocManaged(&x, N * sizeof(float));
hipMallocManaged(&y, N * sizeof(float));
// initialize x and y arrays on the host
for (int i = 0; i < N; ++i) {
x[i] = 1.0f;
y[i] = 2.0f;
}
// Run kernel on 1M elements on the GPU
add<<<1, 1>>>(N, x, y);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
float max_error = 0.0f;
for (int i = 0; i < N; ++i) {
max_error = fmax(max_error, fabs(y[i] - 3.0f));
}
std::cout << "max error: " << max_error << std::endl;
// free memory
hipFree(x);
hipFree(y);
return 0;
} | .text
.file "add.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addiPfS_ # -- Begin function _Z18__device_stub__addiPfS_
.p2align 4, 0x90
.type _Z18__device_stub__addiPfS_,@function
_Z18__device_stub__addiPfS_: # @_Z18__device_stub__addiPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addiPfS_, .Lfunc_end0-_Z18__device_stub__addiPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0xc0400000 # float -3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $152, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rax
xorl %ecx, %ecx
movq 8(%rsp), %rdx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rax,%rcx,4) # imm = 0x3F800000
movl $1073741824, (%rdx,%rcx,4) # imm = 0x40000000
incq %rcx
cmpq $1048576, %rcx # imm = 0x100000
jne .LBB1_1
# %bb.2:
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl $1048576, 28(%rsp) # imm = 0x100000
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addiPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
xorps %xmm2, %xmm2
xorl %eax, %eax
movq 8(%rsp), %rcx
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI1_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm2, %xmm5
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%rcx,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andps %xmm3, %xmm4
maxss %xmm2, %xmm3
andnps %xmm3, %xmm5
orps %xmm4, %xmm5
incq %rax
movaps %xmm5, %xmm2
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
movaps %xmm5, 128(%rsp) # 16-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movaps 128(%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_9
# %bb.8:
movzbl 67(%rbx), %ecx
jmp .LBB1_10
.LBB1_9:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_11:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiPfS_,@object # @_Z3addiPfS_
.section .rodata,"a",@progbits
.globl _Z3addiPfS_
.p2align 3, 0x0
_Z3addiPfS_:
.quad _Z18__device_stub__addiPfS_
.size _Z3addiPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "max error: "
.size .L.str, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addiPfS_"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiPfS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff007624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*0050*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0060*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0070*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe20000000a00 */
/*0080*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0090*/ @!P0 BRA 0xaa0 ; /* 0x00000a0000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R6, -R0, c[0x0][0x160], RZ ; /* 0x0000580000067a10 */
/* 0x000fe20007ffe1ff */
/*00b0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00c0*/ MOV R4, c[0x0][0x170] ; /* 0x00005c0000047a02 */
/* 0x000fe20000000f00 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fe200078e00ff */
/*00e0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f04270 */
/*00f0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe200078e00ff */
/*0100*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fd60000000f00 */
/*0110*/ @!P0 BRA 0x8f0 ; /* 0x000007d000008947 */
/* 0x000fea0003800000 */
/*0120*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0130*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0140*/ @!P1 BRA 0x610 ; /* 0x000004c000009947 */
/* 0x000fea0003800000 */
/*0150*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0160*/ LDG.E R7, [R4.64] ; /* 0x0000000a04077981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R8, [R2.64] ; /* 0x0000000a02087981 */
/* 0x000ea4000c1e1900 */
/*0180*/ FADD R7, R7, R8 ; /* 0x0000000807077221 */
/* 0x004fe40000000000 */
/*0190*/ LDG.E R8, [R4.64+0x4] ; /* 0x0000040a04087981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e8000c10190a */
/*01b0*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040a02097981 */
/* 0x000ea8000c1e1900 */
/*01c0*/ LDG.E R7, [R4.64+0x10] ; /* 0x0000100a04077981 */
/* 0x001ee2000c1e1900 */
/*01d0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fc60000000000 */
/*01e0*/ LDG.E R8, [R4.64+0x8] ; /* 0x0000080a04087981 */
/* 0x000ea8000c1e1900 */
/*01f0*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x0001e8000c10190a */
/*0200*/ LDG.E R11, [R2.64+0x8] ; /* 0x0000080a020b7981 */
/* 0x000ea4000c1e1900 */
/*0210*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x004fc40000000000 */
/*0220*/ LDG.E R8, [R4.64+0xc] ; /* 0x00000c0a04087981 */
/* 0x000ea8000c1e1900 */
/*0230*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x000fe8000c10190a */
/*0240*/ LDG.E R13, [R2.64+0xc] ; /* 0x00000c0a020d7981 */
/* 0x000ea4000c1e1900 */
/*0250*/ FADD R13, R8, R13 ; /* 0x0000000d080d7221 */
/* 0x004fca0000000000 */
/*0260*/ STG.E [R4.64+0xc], R13 ; /* 0x00000c0d04007986 */
/* 0x000fe8000c10190a */
/*0270*/ LDG.E R8, [R2.64+0x10] ; /* 0x0000100a02087981 */
/* 0x000ee4000c1e1900 */
/*0280*/ FADD R7, R7, R8 ; /* 0x0000000807077221 */
/* 0x008fe40000000000 */
/*0290*/ LDG.E R8, [R4.64+0x14] ; /* 0x0000140a04087981 */
/* 0x000ea8000c1e1900 */
/*02a0*/ STG.E [R4.64+0x10], R7 ; /* 0x0000100704007986 */
/* 0x0003e8000c10190a */
/*02b0*/ LDG.E R9, [R2.64+0x14] ; /* 0x0000140a02097981 */
/* 0x001ea8000c1e1900 */
/*02c0*/ LDG.E R7, [R4.64+0x20] ; /* 0x0000200a04077981 */
/* 0x002ee2000c1e1900 */
/*02d0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fc60000000000 */
/*02e0*/ LDG.E R8, [R4.64+0x18] ; /* 0x0000180a04087981 */
/* 0x000ea8000c1e1900 */
/*02f0*/ STG.E [R4.64+0x14], R9 ; /* 0x0000140904007986 */
/* 0x0001e8000c10190a */
/*0300*/ LDG.E R11, [R2.64+0x18] ; /* 0x0000180a020b7981 */
/* 0x000ea4000c1e1900 */
/*0310*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x004fc40000000000 */
/*0320*/ LDG.E R8, [R4.64+0x1c] ; /* 0x00001c0a04087981 */
/* 0x000ea8000c1e1900 */
/*0330*/ STG.E [R4.64+0x18], R11 ; /* 0x0000180b04007986 */
/* 0x000fe8000c10190a */
/*0340*/ LDG.E R13, [R2.64+0x1c] ; /* 0x00001c0a020d7981 */
/* 0x000ea4000c1e1900 */
/*0350*/ FADD R13, R8, R13 ; /* 0x0000000d080d7221 */
/* 0x004fca0000000000 */
/*0360*/ STG.E [R4.64+0x1c], R13 ; /* 0x00001c0d04007986 */
/* 0x000fe8000c10190a */
/*0370*/ LDG.E R8, [R2.64+0x20] ; /* 0x0000200a02087981 */
/* 0x000ee4000c1e1900 */
/*0380*/ FADD R7, R7, R8 ; /* 0x0000000807077221 */
/* 0x008fe40000000000 */
/*0390*/ LDG.E R8, [R4.64+0x24] ; /* 0x0000240a04087981 */
/* 0x000ea8000c1e1900 */
/*03a0*/ STG.E [R4.64+0x20], R7 ; /* 0x0000200704007986 */
/* 0x0003e8000c10190a */
/*03b0*/ LDG.E R9, [R2.64+0x24] ; /* 0x0000240a02097981 */
/* 0x001ea8000c1e1900 */
/*03c0*/ LDG.E R7, [R4.64+0x30] ; /* 0x0000300a04077981 */
/* 0x002ee2000c1e1900 */
/*03d0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fc60000000000 */
/*03e0*/ LDG.E R8, [R4.64+0x28] ; /* 0x0000280a04087981 */
/* 0x000ea8000c1e1900 */
/*03f0*/ STG.E [R4.64+0x24], R9 ; /* 0x0000240904007986 */
/* 0x0001e8000c10190a */
/*0400*/ LDG.E R11, [R2.64+0x28] ; /* 0x0000280a020b7981 */
/* 0x000ea4000c1e1900 */
/*0410*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x004fc40000000000 */
/*0420*/ LDG.E R8, [R4.64+0x2c] ; /* 0x00002c0a04087981 */
/* 0x000ea8000c1e1900 */
/*0430*/ STG.E [R4.64+0x28], R11 ; /* 0x0000280b04007986 */
/* 0x0003e8000c10190a */
/*0440*/ LDG.E R13, [R2.64+0x2c] ; /* 0x00002c0a020d7981 */
/* 0x000ea4000c1e1900 */
/*0450*/ FADD R13, R8, R13 ; /* 0x0000000d080d7221 */
/* 0x004fca0000000000 */
/*0460*/ STG.E [R4.64+0x2c], R13 ; /* 0x00002c0d04007986 */
/* 0x0005e8000c10190a */
/*0470*/ LDG.E R8, [R2.64+0x30] ; /* 0x0000300a02087981 */
/* 0x000ee4000c1e1900 */
/*0480*/ FADD R7, R7, R8 ; /* 0x0000000807077221 */
/* 0x008fe40000000000 */
/*0490*/ LDG.E R8, [R4.64+0x34] ; /* 0x0000340a04087981 */
/* 0x000ee8000c1e1900 */
/*04a0*/ STG.E [R4.64+0x30], R7 ; /* 0x0000300704007986 */
/* 0x0009e8000c10190a */
/*04b0*/ LDG.E R9, [R2.64+0x34] ; /* 0x0000340a02097981 */
/* 0x001ee4000c1e1900 */
/*04c0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x008fc40000000000 */
/*04d0*/ LDG.E R8, [R4.64+0x38] ; /* 0x0000380a04087981 */
/* 0x000ee8000c1e1900 */
/*04e0*/ STG.E [R4.64+0x34], R9 ; /* 0x0000340904007986 */
/* 0x000fe8000c10190a */
/*04f0*/ LDG.E R11, [R2.64+0x38] ; /* 0x0000380a020b7981 */
/* 0x002ee2000c1e1900 */
/*0500*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fe20007ffe0ff */
/*0510*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x008fc40000000000 */
/*0520*/ LDG.E R8, [R4.64+0x3c] ; /* 0x00003c0a04087981 */
/* 0x000ee8000c1e1900 */
/*0530*/ STG.E [R4.64+0x38], R11 ; /* 0x0000380b04007986 */
/* 0x000fe8000c10190a */
/*0540*/ LDG.E R13, [R2.64+0x3c] ; /* 0x00003c0a020d7981 */
/* 0x0040e2000c1e1900 */
/*0550*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0560*/ IADD3 R7, P3, R4, 0x40, RZ ; /* 0x0000004004077810 */
/* 0x010fe20007f7e0ff */
/*0570*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*0580*/ IADD3 R10, P2, R2, 0x40, RZ ; /* 0x00000040020a7810 */
/* 0x000fc80007f5e0ff */
/*0590*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */
/* 0x001fe400017fe4ff */
/*05a0*/ MOV R2, R10 ; /* 0x0000000a00027202 */
/* 0x000fe20000000f00 */
/*05b0*/ FADD R13, R8, R13 ; /* 0x0000000d080d7221 */
/* 0x008fe40000000000 */
/*05c0*/ IMAD.X R8, RZ, RZ, R5, P3 ; /* 0x000000ffff087224 */
/* 0x000fc600018e0605 */
/*05d0*/ STG.E [R4.64+0x3c], R13 ; /* 0x00003c0d04007986 */
/* 0x0001e4000c10190a */
/*05e0*/ IMAD.MOV.U32 R4, RZ, RZ, R7 ; /* 0x000000ffff047224 */
/* 0x001fe200078e0007 */
/*05f0*/ MOV R5, R8 ; /* 0x0000000800057202 */
/* 0x000fe20000000f00 */
/*0600*/ @P1 BRA 0x160 ; /* 0xfffffb5000001947 */
/* 0x000fea000383ffff */
/*0610*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0620*/ @!P1 BRA 0x8d0 ; /* 0x000002a000009947 */
/* 0x000fea0003800000 */
/*0630*/ LDG.E R7, [R4.64] ; /* 0x0000000a04077981 */
/* 0x000ea8000c1e1900 */
/*0640*/ LDG.E R8, [R2.64] ; /* 0x0000000a02087981 */
/* 0x000ea4000c1e1900 */
/*0650*/ FADD R7, R7, R8 ; /* 0x0000000807077221 */
/* 0x004fe40000000000 */
/*0660*/ LDG.E R8, [R4.64+0x4] ; /* 0x0000040a04087981 */
/* 0x000ea8000c1e1900 */
/*0670*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e8000c10190a */
/*0680*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040a02097981 */
/* 0x000ea8000c1e1900 */
/*0690*/ LDG.E R7, [R4.64+0x10] ; /* 0x0000100a04077981 */
/* 0x001ee2000c1e1900 */
/*06a0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fc60000000000 */
/*06b0*/ LDG.E R8, [R4.64+0x8] ; /* 0x0000080a04087981 */
/* 0x000ea8000c1e1900 */
/*06c0*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x0001e8000c10190a */
/*06d0*/ LDG.E R11, [R2.64+0x8] ; /* 0x0000080a020b7981 */
/* 0x000ea4000c1e1900 */
/*06e0*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x004fc40000000000 */
/*06f0*/ LDG.E R8, [R4.64+0xc] ; /* 0x00000c0a04087981 */
/* 0x000ea8000c1e1900 */
/*0700*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x0003e8000c10190a */
/*0710*/ LDG.E R13, [R2.64+0xc] ; /* 0x00000c0a020d7981 */
/* 0x000ea4000c1e1900 */
/*0720*/ FADD R13, R8, R13 ; /* 0x0000000d080d7221 */
/* 0x004fca0000000000 */
/*0730*/ STG.E [R4.64+0xc], R13 ; /* 0x00000c0d04007986 */
/* 0x0005e8000c10190a */
/*0740*/ LDG.E R8, [R2.64+0x10] ; /* 0x0000100a02087981 */
/* 0x000ee4000c1e1900 */
/*0750*/ FADD R7, R7, R8 ; /* 0x0000000807077221 */
/* 0x008fe40000000000 */
/*0760*/ LDG.E R8, [R4.64+0x14] ; /* 0x0000140a04087981 */
/* 0x000ee8000c1e1900 */
/*0770*/ STG.E [R4.64+0x10], R7 ; /* 0x0000100704007986 */
/* 0x0009e8000c10190a */
/*0780*/ LDG.E R9, [R2.64+0x14] ; /* 0x0000140a02097981 */
/* 0x001ee4000c1e1900 */
/*0790*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x008fc40000000000 */
/*07a0*/ LDG.E R8, [R4.64+0x18] ; /* 0x0000180a04087981 */
/* 0x000ee8000c1e1900 */
/*07b0*/ STG.E [R4.64+0x14], R9 ; /* 0x0000140904007986 */
/* 0x000fe8000c10190a */
/*07c0*/ LDG.E R11, [R2.64+0x18] ; /* 0x0000180a020b7981 */
/* 0x002ee4000c1e1900 */
/*07d0*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x008fc40000000000 */
/*07e0*/ LDG.E R8, [R4.64+0x1c] ; /* 0x00001c0a04087981 */
/* 0x000ee8000c1e1900 */
/*07f0*/ STG.E [R4.64+0x18], R11 ; /* 0x0000180b04007986 */
/* 0x000fe8000c10190a */
/*0800*/ LDG.E R13, [R2.64+0x1c] ; /* 0x00001c0a020d7981 */
/* 0x0040e2000c1e1900 */
/*0810*/ IADD3 R7, P2, R4, 0x20, RZ ; /* 0x0000002004077810 */
/* 0x010fe40007f5e0ff */
/*0820*/ IADD3 R10, P1, R2, 0x20, RZ ; /* 0x00000020020a7810 */
/* 0x000fc40007f3e0ff */
/*0830*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0840*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0850*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x001fe400008e0603 */
/*0860*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x000fe200078e000a */
/*0870*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0880*/ FADD R13, R8, R13 ; /* 0x0000000d080d7221 */
/* 0x008fe20000000000 */
/*0890*/ IADD3.X R8, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff087210 */
/* 0x000fc800017fe4ff */
/*08a0*/ STG.E [R4.64+0x1c], R13 ; /* 0x00001c0d04007986 */
/* 0x0001e4000c10190a */
/*08b0*/ MOV R4, R7 ; /* 0x0000000700047202 */
/* 0x001fe20000000f00 */
/*08c0*/ IMAD.MOV.U32 R5, RZ, RZ, R8 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0008 */
/*08d0*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*08e0*/ @!P0 BRA 0xaa0 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*08f0*/ LDG.E R7, [R4.64] ; /* 0x0000000a04077981 */
/* 0x000ea8000c1e1900 */
/*0900*/ LDG.E R8, [R2.64] ; /* 0x0000000a02087981 */
/* 0x000ea4000c1e1900 */
/*0910*/ FADD R7, R7, R8 ; /* 0x0000000807077221 */
/* 0x004fe40000000000 */
/*0920*/ LDG.E R8, [R4.64+0x4] ; /* 0x0000040a04087981 */
/* 0x000ea8000c1e1900 */
/*0930*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e8000c10190a */
/*0940*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040a02097981 */
/* 0x000ea4000c1e1900 */
/*0950*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fc40000000000 */
/*0960*/ LDG.E R8, [R4.64+0x8] ; /* 0x0000080a04087981 */
/* 0x000ea8000c1e1900 */
/*0970*/ STG.E [R4.64+0x4], R9 ; /* 0x0000040904007986 */
/* 0x000fe8000c10190a */
/*0980*/ LDG.E R11, [R2.64+0x8] ; /* 0x0000080a020b7981 */
/* 0x000ea2000c1e1900 */
/*0990*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fe20007ffe0ff */
/*09a0*/ FADD R11, R8, R11 ; /* 0x0000000b080b7221 */
/* 0x004fc40000000000 */
/*09b0*/ LDG.E R8, [R4.64+0xc] ; /* 0x00000c0a04087981 */
/* 0x000ea8000c1e1900 */
/*09c0*/ STG.E [R4.64+0x8], R11 ; /* 0x0000080b04007986 */
/* 0x000fe8000c10190a */
/*09d0*/ LDG.E R13, [R2.64+0xc] ; /* 0x00000c0a020d7981 */
/* 0x0002a2000c1e1900 */
/*09e0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*09f0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000fffe03f */
/*0a00*/ IADD3 R7, P2, R4, 0x10, RZ ; /* 0x0000001004077810 */
/* 0x001fc40007f5e0ff */
/*0a10*/ IADD3 R10, P1, R2, 0x10, RZ ; /* 0x00000010020a7810 */
/* 0x000fc80007f3e0ff */
/*0a20*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x002fe40000ffe4ff */
/*0a30*/ MOV R2, R10 ; /* 0x0000000a00027202 */
/* 0x000fe20000000f00 */
/*0a40*/ FADD R13, R8, R13 ; /* 0x0000000d080d7221 */
/* 0x004fe40000000000 */
/*0a50*/ IMAD.X R8, RZ, RZ, R5, P2 ; /* 0x000000ffff087224 */
/* 0x000fc600010e0605 */
/*0a60*/ STG.E [R4.64+0xc], R13 ; /* 0x00000c0d04007986 */
/* 0x0001e4000c10190a */
/*0a70*/ IMAD.MOV.U32 R4, RZ, RZ, R7 ; /* 0x000000ffff047224 */
/* 0x001fe200078e0007 */
/*0a80*/ MOV R5, R8 ; /* 0x0000000800057202 */
/* 0x000fe20000000f00 */
/*0a90*/ @P0 BRA 0x8f0 ; /* 0xfffffe5000000947 */
/* 0x000fea000383ffff */
/*0aa0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0ab0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0ac0*/ UMOV UR5, 0x4 ; /* 0x0000000400057882 */
/* 0x000fe40000000000 */
/*0ad0*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe40000000a00 */
/*0ae0*/ UIMAD.WIDE UR6, UR4, UR5, UR6 ; /* 0x00000005040672a5 */
/* 0x000fe4000f8e0206 */
/*0af0*/ ULDC.64 UR8, c[0x0][0x168] ; /* 0x00005a0000087ab9 */
/* 0x000fe40000000a00 */
/*0b00*/ UIMAD.WIDE UR4, UR4, UR5, UR8 ; /* 0x00000005040472a5 */
/* 0x000fe4000f8e0208 */
/*0b10*/ IMAD.U32 R2, RZ, RZ, UR6 ; /* 0x00000006ff027e24 */
/* 0x000fe2000f8e00ff */
/*0b20*/ MOV R5, UR7 ; /* 0x0000000700057c02 */
/* 0x000fe20008000f00 */
/*0b30*/ IMAD.U32 R4, RZ, RZ, UR6 ; /* 0x00000006ff047e24 */
/* 0x000fe2000f8e00ff */
/*0b40*/ MOV R3, UR7 ; /* 0x0000000700037c02 */
/* 0x000fe20008000f00 */
/*0b50*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0002 */
/*0b60*/ MOV R9, R5 ; /* 0x0000000500097202 */
/* 0x000fc40000000f00 */
/*0b70*/ MOV R5, UR5 ; /* 0x0000000500057c02 */
/* 0x000fe20008000f00 */
/*0b80*/ IMAD.U32 R4, RZ, RZ, UR4 ; /* 0x00000004ff047e24 */
/* 0x000fe2000f8e00ff */
/*0b90*/ MOV R3, R9 ; /* 0x0000000900037202 */
/* 0x001fe20000000f00 */
/*0ba0*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fc600078e0006 */
/*0bb0*/ LDG.E R5, [R4.64] ; /* 0x0000000a04057981 */
/* 0x000ea8000c1e1900 */
/*0bc0*/ LDG.E R6, [R2.64] ; /* 0x0000000a02067981 */
/* 0x000ea2000c1e1900 */
/*0bd0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc80007ffe0ff */
/*0be0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0bf0*/ UIADD3 UR4, UP0, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fc8000ff1e03f */
/*0c00*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*0c10*/ FADD R7, R6, R5 ; /* 0x0000000506077221 */
/* 0x004fe20000000000 */
/*0c20*/ IADD3 R6, P1, R2, 0x4, RZ ; /* 0x0000000402067810 */
/* 0x000fc80007f3e0ff */
/*0c30*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e2000c10190a */
/*0c40*/ IADD3.X R9, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff097210 */
/* 0x000fe20000ffe4ff */
/*0c50*/ @P0 BRA 0xb70 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*0c60*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c70*/ BRA 0xc70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiPfS_
.globl _Z3addiPfS_
.p2align 8
.type _Z3addiPfS_,@function
_Z3addiPfS_:
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[0:3], s[0:1], 0x8
v_mov_b32_e32 v0, 0
.LBB0_2:
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[0:1]
global_load_b32 v2, v0, s[2:3]
s_add_i32 s4, s4, -1
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[2:3]
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s4, 0
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 5
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiPfS_, .Lfunc_end0-_Z3addiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 5
.sgpr_spill_count: 0
.symbol: _Z3addiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012f271_00000000-6_add.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z3addiPfS_iPfS_
.type _Z25__device_stub__Z3addiPfS_iPfS_, @function
_Z25__device_stub__Z3addiPfS_iPfS_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z25__device_stub__Z3addiPfS_iPfS_, .-_Z25__device_stub__Z3addiPfS_iPfS_
.globl _Z3addiPfS_
.type _Z3addiPfS_, @function
_Z3addiPfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3addiPfS_iPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3addiPfS_, .-_Z3addiPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "max error: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $72, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $4194304, %esi
call cudaMallocManaged@PLT
movl $0, %eax
movss .LC1(%rip), %xmm1
movss .LC2(%rip), %xmm0
.L12:
movq 16(%rsp), %rdx
movss %xmm1, (%rdx,%rax)
movq 24(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L12
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call cudaDeviceSynchronize@PLT
movq 24(%rsp), %rbx
leaq 4194304(%rbx), %rbp
movl $0x00000000, 12(%rsp)
.L14:
movss (%rbx), %xmm0
subss .LC3(%rip), %xmm0
andps .LC4(%rip), %xmm0
movss 12(%rsp), %xmm1
call fmaxf@PLT
movss %xmm0, 12(%rsp)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L14
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movl $1048576, %edi
call _Z25__device_stub__Z3addiPfS_iPfS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z3addiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1073741824
.align 4
.LC3:
.long 1077936128
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__addiPfS_ # -- Begin function _Z18__device_stub__addiPfS_
.p2align 4, 0x90
.type _Z18__device_stub__addiPfS_,@function
_Z18__device_stub__addiPfS_: # @_Z18__device_stub__addiPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addiPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addiPfS_, .Lfunc_end0-_Z18__device_stub__addiPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0xc0400000 # float -3
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $152, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rax
xorl %ecx, %ecx
movq 8(%rsp), %rdx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rax,%rcx,4) # imm = 0x3F800000
movl $1073741824, (%rdx,%rcx,4) # imm = 0x40000000
incq %rcx
cmpq $1048576, %rcx # imm = 0x100000
jne .LBB1_1
# %bb.2:
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl $1048576, 28(%rsp) # imm = 0x100000
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addiPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
xorps %xmm2, %xmm2
xorl %eax, %eax
movq 8(%rsp), %rcx
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI1_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movaps %xmm2, %xmm5
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%rcx,%rax,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm5, %xmm5
movaps %xmm5, %xmm4
andps %xmm3, %xmm4
maxss %xmm2, %xmm3
andnps %xmm3, %xmm5
orps %xmm4, %xmm5
incq %rax
movaps %xmm5, %xmm2
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_5
# %bb.6:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
movaps %xmm5, 128(%rsp) # 16-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movaps 128(%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_9
# %bb.8:
movzbl 67(%rbx), %ecx
jmp .LBB1_10
.LBB1_9:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_11:
.cfi_def_cfa_offset 176
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiPfS_,@object # @_Z3addiPfS_
.section .rodata,"a",@progbits
.globl _Z3addiPfS_
.p2align 3, 0x0
_Z3addiPfS_:
.quad _Z18__device_stub__addiPfS_
.size _Z3addiPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "max error: "
.size .L.str, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addiPfS_"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiPfS_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <algorithm>
#include <cmath>
#include <cstdio>
#include <cstdlib>
#include <iomanip>
#include <iostream>
#include <vector>
#define C 4
#define THREADS 1024 // 2^10
#define MAX 85
#define MAX_S MAX* MAX
#define PERM_MAX (MAX * (MAX - 1) * (MAX - 2) * (MAX - 3)) / 24
#define pb push_back
#define mp make_pair
#define gpuErrChk(ans) \
{ \
gpuAssert((ans), __FILE__, __LINE__); \
}
inline void gpuAssert(cudaError_t code, char* file, int line, bool abort = true)
{
if (code != cudaSuccess) {
fprintf(stderr, "GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort)
getchar();
}
}
using namespace std;
typedef long long int64;
typedef pair<int, int> ii;
/*
sz ---> Adjacency matrix dimension (1D)
perm ---> Number of permutations of an instance
graph ---> Adjacency matrix itself
seeds ---> Set of seeds
faces ---> Set of triangular faces for the output
*/
struct Node {
int sz, perm;
int graph[MAX_S], seeds[C * PERM_MAX], F_ANS[6 * MAX];
};
/*
faces ---> Number of triangular faces
count ---> Number of remaining vertices
tmpMax ---> Max value obtained for a seed
F ---> Set of triangular faces
F ---> Set of remaining vertices
*/
struct Params {
int *faces, *count, *tmpMax;
int *F, *V;
};
/*
SIZE ---> Number of vertices
BLOCKS ---> Number of blocks
PERM ---> Number of permutations
R ---> Output graph for a possible solution
F ---> Set of triangular faces of an instance
qtd ---> Number of possible 4-cliques
*/
clock_t start, stop;
int SIZE, BLOCKS, PERM, qtd = 0;
int R[MAX_S], F[8 * MAX], bib[MAX];
Node* N;
__device__ void initializeDevice(Params* devP, int sz, int t)
{
devP->faces[t] = 0;
devP->tmpMax[t] = -1;
devP->count[t] = sz - 4;
}
/*
Generates a list containing the vertices which are not on the planar graph
*/
__device__ void generateList(Node* devN, Params* devP, int t)
{
int sz = devN->sz;
int va = devN->seeds[t], vb = devN->seeds[t + devN->perm], vc = devN->seeds[t + 2 * devN->perm], vd = devN->seeds[t + 3 * devN->perm];
for (int i = 0; i < sz; i++) {
if (i == va || i == vb || i == vc || i == vd)
devP->V[t + i * devN->perm] = -1;
else
devP->V[t + i * devN->perm] = i;
}
}
/*
Returns the weight of the planar graph so far
*/
__device__ void generateTriangularFaceList(Node* devN, Params* devP, int graph[], int t)
{
int sz = devN->sz;
int va = devN->seeds[t];
int vb = devN->seeds[t + devN->perm];
int vc = devN->seeds[t + 2 * devN->perm];
int vd = devN->seeds[t + 3 * devN->perm];
//generate first triangle of the output graph
devP->F[t + (devP->faces[t] * 3) * devN->perm] = va;
devP->F[t + (devP->faces[t] * 3 + 1) * devN->perm] = vb;
devP->F[t + ((devP->faces[t]++) * 3 + 2) * devN->perm] = vc;
int resp = graph[va * sz + vb] + graph[va * sz + vc] + graph[vb * sz + vc];
//generate the next 3 possible faces
devP->F[t + (devP->faces[t] * 3) * devN->perm] = va;
devP->F[t + (devP->faces[t] * 3 + 1) * devN->perm] = vb;
devP->F[t + ((devP->faces[t]++) * 3 + 2) * devN->perm] = vd;
devP->F[t + (devP->faces[t] * 3) * devN->perm] = va;
devP->F[t + (devP->faces[t] * 3 + 1) * devN->perm] = vc;
devP->F[t + ((devP->faces[t]++) * 3 + 2) * devN->perm] = vd;
devP->F[t + (devP->faces[t] * 3) * devN->perm] = vb;
devP->F[t + (devP->faces[t] * 3 + 1) * devN->perm] = vc;
devP->F[t + ((devP->faces[t]++) * 3 + 2) * devN->perm] = vd;
resp += graph[va * sz + vd] + graph[vb * sz + vd] + graph[vc * sz + vd];
devP->tmpMax[t] = resp;
}
/*
Insert a new vertex, 3 new triangular faces and removes face 'f' from the set
*/
__device__ int operationT2(Node* devN, Params* devP, int graph[], int new_vertex, int f, int t)
{
int sz = devN->sz, perm = devN->perm;
//remove the chosen face and insert a new one
int va = devP->F[t + (f * 3) * perm];
int vb = devP->F[t + (f * 3 + 1) * perm];
int vc = devP->F[t + (f * 3 + 2) * perm];
devP->F[t + (f * 3) * perm] = new_vertex;
devP->F[t + (f * 3 + 1) * perm] = va;
devP->F[t + (f * 3 + 2) * perm] = vb;
//and insert the other two possible faces
devP->F[t + (devP->faces[t] * 3) * perm] = new_vertex;
devP->F[t + (devP->faces[t] * 3 + 1) * perm] = va;
devP->F[t + ((devP->faces[t]++) * 3 + 2) * perm] = vc;
devP->F[t + (devP->faces[t] * 3) * perm] = new_vertex;
devP->F[t + (devP->faces[t] * 3 + 1) * perm] = vb;
devP->F[t + ((devP->faces[t]++) * 3 + 2) * perm] = vc;
int resp = graph[va * sz + new_vertex] + graph[vb * sz + new_vertex] + graph[vc * sz + new_vertex];
return resp;
}
/*
Return the vertex with the maximum gain inserting within a face 'f'
*/
__device__ int maxGain(Node* devN, Params* devP, int graph[], int* f, int t)
{
int sz = devN->sz, perm = devN->perm;
int gain = -1, vertex = -1;
//iterate through the remaining vertices
for (int new_vertex = 0; new_vertex < sz; new_vertex++) {
if (devP->V[t + new_vertex * perm] == -1)
continue;
//and test which has the maximum gain with its insetion
//within all possible faces
int faces = devP->faces[t];
for (int i = 0; i < faces; i++) {
int va = devP->F[t + (i * 3) * perm], vb = devP->F[t + (i * 3 + 1) * perm], vc = devP->F[t + (i * 3 + 2) * perm];
int tmpGain = graph[va * sz + new_vertex] + graph[vb * sz + new_vertex] + graph[vc * sz + new_vertex];
if (tmpGain > gain) {
gain = tmpGain;
*f = i;
vertex = new_vertex;
}
}
}
return vertex;
}
__device__ void tmfg(Node* devN, Params* devP, int graph[], int t)
{
while (devP->count[t]) {
int f = -1;
int vertex = maxGain(devN, devP, graph, &f, t);
devP->V[t + vertex * devN->perm] = -1;
devP->tmpMax[t] += operationT2(devN, devP, graph, vertex, f, t);
devP->count[t]--;
}
}
__global__ void tmfgParallel(Node* devN, Params devP, int* respMax, int* idx)
{
int x = blockDim.x * blockIdx.x + threadIdx.x;
int sz = devN->sz, perm = devN->perm;
extern __shared__ int graph[];
for (int i = threadIdx.x; i < sz * sz; i += blockDim.x) {
graph[i] = devN->graph[i];
graph[i] = devN->graph[i];
}
__syncthreads();
if (x < perm) {
initializeDevice(&devP, sz, x);
generateList(devN, &devP, x);
generateTriangularFaceList(devN, &devP, graph, x);
tmfg(devN, &devP, graph, x);
__syncthreads();
atomicMax(respMax, devP.tmpMax[x]);
if (devP.tmpMax[x] == *respMax)
*idx = x;
__syncthreads();
}
}
int tmfgPrepare()
{
int resp = 0, idx = 0, *tmpResp, *tmpIdx;
gpuErrChk(cudaMalloc((void**)&tmpResp, sizeof(int)));
gpuErrChk(cudaMalloc((void**)&tmpIdx, sizeof(int)));
gpuErrChk(cudaMemcpy(tmpResp, &resp, sizeof(int), cudaMemcpyHostToDevice));
gpuErrChk(cudaMemcpy(tmpIdx, &idx, sizeof(int), cudaMemcpyHostToDevice));
Node* devN;
Params devP;
cout << "Amount of memory: " << (3 * PERM + PERM * SIZE + 6 * SIZE * PERM * sizeof(int)) / 1000000 << "MB" << endl;
gpuErrChk(cudaMalloc((void**)&devN, sizeof(Node)));
gpuErrChk(cudaMemcpy(devN, N, sizeof(Node), cudaMemcpyHostToDevice));
cout << "1 done." << endl;
gpuErrChk(cudaMalloc((void**)&devP.faces, PERM * sizeof(int)));
gpuErrChk(cudaMalloc((void**)&devP.count, PERM * sizeof(int)));
gpuErrChk(cudaMalloc((void**)&devP.tmpMax, PERM * sizeof(int)));
gpuErrChk(cudaMalloc((void**)&devP.F, PERM * 6 * SIZE * sizeof(int)));
gpuErrChk(cudaMalloc((void**)&devP.V, PERM * SIZE * sizeof(int)));
cout << "2 done." << endl;
dim3 blocks(BLOCKS, 1);
dim3 threads(THREADS, 1);
cout << "Launching kernel..." << endl;
tmfgParallel<<<blocks, threads, SIZE * SIZE * sizeof(int)>>>(devN, devP, tmpResp, tmpIdx);
gpuErrChk(cudaDeviceSynchronize());
cout << "Kernel finished." << endl;
//copy back the maximum weight and the index of the graph
//which gave this result
gpuErrChk(cudaMemcpy(&resp, tmpResp, sizeof(int), cudaMemcpyDeviceToHost));
cout << "1 done." << endl;
gpuErrChk(cudaMemcpy(&idx, tmpIdx, sizeof(int), cudaMemcpyDeviceToHost));
cout << "2 done." << endl;
//gpuErrChk(cudaMemcpy(&F, devP.F[idx + ], (6*MAX)*sizeof(int), cudaMemcpyDeviceToHost));
cout << "3 done." << endl;
gpuErrChk(cudaFree(devN));
gpuErrChk(cudaFree(devP.faces));
gpuErrChk(cudaFree(devP.count));
gpuErrChk(cudaFree(devP.tmpMax));
gpuErrChk(cudaFree(devP.F));
gpuErrChk(cudaFree(devP.V));
cout << "Completed." << endl;
return resp;
}
void printElapsedTime(clock_t start, clock_t stop)
{
double elapsed = ((double)(stop - start)) / CLOCKS_PER_SEC;
cout << fixed << setprecision(3) << "Elapsed time: " << elapsed << "s\n";
}
/*
C ---> Size of the combination
index ---> Current index in data[]
data[] ---> Temporary array to store a current combination
i ---> Index of current element in vertices[]
*/
void combineUntil(int index, vector<int>& data, int i)
{
// Current cobination is ready, print it
if (index == C) {
for (int j = 0; j < C; j++) {
N->seeds[qtd + j * PERM] = data[j];
}
qtd++;
return;
}
// When there are no more elements to put in data[]
if (i >= SIZE)
return;
//current is inserted; put next at a next location
data[index] = i;
combineUntil(index + 1, data, i + 1);
//current is deleted; replace it with next
combineUntil(index, data, i + 1);
}
/*
Print all combinations of size 'C' using a temporary array 'data'
*/
void combine()
{
vector<int> data(C);
combineUntil(0, data, 0);
}
void initialize()
{
for (int i = 0; i < SIZE; i++) {
for (int j = i + 1; j < SIZE; j++) {
R[i * SIZE + j] = R[j * SIZE + i] = -1;
}
}
}
void readInput()
{
int x;
cin >> SIZE;
PERM = bib[SIZE - 1];
BLOCKS = PERM / THREADS + 1;
N = (Node*)malloc(sizeof(Node));
N->sz = SIZE;
N->perm = PERM;
for (int i = 0; i < SIZE; i++) {
for (int j = i + 1; j < SIZE; j++) {
cin >> x;
N->graph[i * SIZE + j] = x;
N->graph[j * SIZE + i] = x;
}
}
}
/*
Define the number of permutations and blocks
*/
void sizeDefinitions()
{
for (int i = 6; i <= MAX; i++) {
int resp = 1;
for (int j = i - 3; j <= i; j++)
resp *= j;
resp /= 24;
bib[i - 1] = resp;
}
}
int main(int argv, char** argc)
{
ios::sync_with_stdio(false);
sizeDefinitions();
//read the input, which is given by a size of a graph and its weighted edges.
//the graph given is dense.
readInput();
initialize();
//generate multiple 4-clique seeds, given the number of vertices
combine();
cudaSetDevice(3);
start = clock();
int respMax = tmfgPrepare();
stop = clock();
//reconstruct the graph given the regions of the graph
// for ( int i = 0; i < 2*SIZE; i++ ){
// int va = F[i*3], vb = F[i*3 + 1], vc = F[i*3 + 2];
// if ( va == vb && vb == vc ) continue;
// R[va*SIZE + vb] = R[vb*SIZE + va] = N->graph[va*SIZE + vb];
// R[va*SIZE + vc] = R[vc*SIZE + va] = N->graph[va*SIZE + vc];
// R[vb*SIZE + vc] = R[vc*SIZE + vb] = N->graph[vb*SIZE + vc];
// }
// cout << "Printing generated graph: " << endl;
// for ( int i = 0; i < SIZE; i++ ){
// for ( int j = i+1; j < SIZE; j++ ){
// cout << R[i*SIZE + j] << " ";
// }
// cout << endl;
// }
printElapsedTime(start, stop);
cout << "Maximum weight found: " << respMax << endl;
free(N);
gpuErrChk(cudaDeviceReset());
return 0;
} | .file "tmpxft_000f8076_00000000-6_3-tmfg-agsh.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4583:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4583:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16initializeDeviceP6Paramsii
.type _Z16initializeDeviceP6Paramsii, @function
_Z16initializeDeviceP6Paramsii:
.LFB4567:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4567:
.size _Z16initializeDeviceP6Paramsii, .-_Z16initializeDeviceP6Paramsii
.globl _Z12generateListP4NodeP6Paramsi
.type _Z12generateListP4NodeP6Paramsi, @function
_Z12generateListP4NodeP6Paramsi:
.LFB4568:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4568:
.size _Z12generateListP4NodeP6Paramsi, .-_Z12generateListP4NodeP6Paramsi
.globl _Z26generateTriangularFaceListP4NodeP6ParamsPii
.type _Z26generateTriangularFaceListP4NodeP6ParamsPii, @function
_Z26generateTriangularFaceListP4NodeP6ParamsPii:
.LFB4569:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4569:
.size _Z26generateTriangularFaceListP4NodeP6ParamsPii, .-_Z26generateTriangularFaceListP4NodeP6ParamsPii
.globl _Z11operationT2P4NodeP6ParamsPiiii
.type _Z11operationT2P4NodeP6ParamsPiiii, @function
_Z11operationT2P4NodeP6ParamsPiiii:
.LFB4570:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4570:
.size _Z11operationT2P4NodeP6ParamsPiiii, .-_Z11operationT2P4NodeP6ParamsPiiii
.globl _Z7maxGainP4NodeP6ParamsPiS3_i
.type _Z7maxGainP4NodeP6ParamsPiS3_i, @function
_Z7maxGainP4NodeP6ParamsPiS3_i:
.LFB4571:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4571:
.size _Z7maxGainP4NodeP6ParamsPiS3_i, .-_Z7maxGainP4NodeP6ParamsPiS3_i
.globl _Z4tmfgP4NodeP6ParamsPii
.type _Z4tmfgP4NodeP6ParamsPii, @function
_Z4tmfgP4NodeP6ParamsPii:
.LFB4572:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4572:
.size _Z4tmfgP4NodeP6ParamsPii, .-_Z4tmfgP4NodeP6ParamsPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Elapsed time: "
.LC2:
.string "s\n"
.text
.globl _Z16printElapsedTimell
.type _Z16printElapsedTimell, @function
_Z16printElapsedTimell:
.LFB4574:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
subq %rdi, %rsi
pxor %xmm0, %xmm0
cvtsi2sdq %rsi, %xmm0
divsd .LC0(%rip), %xmm0
movsd %xmm0, 8(%rsp)
leaq _ZSt4cout(%rip), %rbx
movq _ZSt4cout(%rip), %rdx
movq %rbx, %rcx
addq -24(%rdx), %rcx
movl 24(%rcx), %eax
andl $-261, %eax
orl $4, %eax
movl %eax, 24(%rcx)
movq -24(%rdx), %rax
movq $3, 8(%rbx,%rax)
movl $14, %edx
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movsd 8(%rsp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $2, %edx
leaq .LC2(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4574:
.size _Z16printElapsedTimell, .-_Z16printElapsedTimell
.globl _Z12combineUntiliRSt6vectorIiSaIiEEi
.type _Z12combineUntiliRSt6vectorIiSaIiEEi, @function
_Z12combineUntiliRSt6vectorIiSaIiEEi:
.LFB4575:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %r12
cmpl $4, %edi
je .L23
movl %edi, %ebp
cmpl %edx, SIZE(%rip)
jg .L24
.L17:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl qtd(%rip), %edi
movslq PERM(%rip), %rsi
salq $2, %rsi
movslq %edi, %rdx
movq N(%rip), %rax
leaq (%rax,%rdx,4), %rdx
movl $0, %eax
.L19:
movq (%r12), %rcx
movl (%rcx,%rax), %ecx
movl %ecx, 28908(%rdx)
addq $4, %rax
addq %rsi, %rdx
cmpq $16, %rax
jne .L19
addl $1, %edi
movl %edi, qtd(%rip)
jmp .L17
.L24:
movslq %edi, %rcx
movq (%rsi), %rax
movl %edx, (%rax,%rcx,4)
leal 1(%rdx), %ebx
leal 1(%rdi), %edi
movl %ebx, %edx
call _Z12combineUntiliRSt6vectorIiSaIiEEi
movl %ebx, %edx
movq %r12, %rsi
movl %ebp, %edi
call _Z12combineUntiliRSt6vectorIiSaIiEEi
jmp .L17
.cfi_endproc
.LFE4575:
.size _Z12combineUntiliRSt6vectorIiSaIiEEi, .-_Z12combineUntiliRSt6vectorIiSaIiEEi
.globl _Z7combinev
.type _Z7combinev, @function
_Z7combinev:
.LFB4576:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movl $16, %edi
call _Znwm@PLT
movq %rax, (%rsp)
leaq 16(%rax), %rdx
movq %rdx, 16(%rsp)
movl $0, (%rax)
movl $0, 4(%rax)
movl $0, 8(%rax)
movl $0, 12(%rax)
movq %rdx, 8(%rsp)
movq %rsp, %rsi
movl $0, %edx
movl $0, %edi
call _Z12combineUntiliRSt6vectorIiSaIiEEi
movq (%rsp), %rdi
testq %rdi, %rdi
je .L25
movq 16(%rsp), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L25:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L29
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4576:
.size _Z7combinev, .-_Z7combinev
.globl _Z10initializev
.type _Z10initializev, @function
_Z10initializev:
.LFB4577:
.cfi_startproc
endbr64
movl SIZE(%rip), %r11d
testl %r11d, %r11d
jle .L40
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
leal 1(%r11), %ebx
movslq %r11d, %rsi
salq $2, %rsi
movl $1, %r8d
movl $0, %edi
leal -1(%r11), %r10d
leaq R(%rip), %r9
leaq 4(%r9), %rbp
.L35:
addl $1, %edi
cmpl %r11d, %edi
jge .L32
leal (%r10,%r8), %eax
cltq
leaq (%r9,%rax,4), %rdx
movslq %r8d, %r12
leaq (%r9,%r12,4), %rax
movl %r10d, %ecx
subl %edi, %ecx
addq %r12, %rcx
leaq 0(%rbp,%rcx,4), %rcx
.L33:
movl $-1, (%rdx)
movl $-1, (%rax)
addq %rsi, %rdx
addq $4, %rax
cmpq %rcx, %rax
jne .L33
addl %ebx, %r8d
jmp .L35
.L32:
jne .L43
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
addl %ebx, %r8d
jmp .L35
.L40:
.cfi_def_cfa_offset 8
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE4577:
.size _Z10initializev, .-_Z10initializev
.globl _Z9readInputv
.type _Z9readInputv, @function
_Z9readInputv:
.LFB4578:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq SIZE(%rip), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movl SIZE(%rip), %ebp
leal -1(%rbp), %eax
cltq
leaq bib(%rip), %rdx
movl (%rdx,%rax,4), %ebx
movl %ebx, PERM(%rip)
leal 1023(%rbx), %eax
testl %ebx, %ebx
cmovns %ebx, %eax
sarl $10, %eax
addl $1, %eax
movl %eax, BLOCKS(%rip)
movl $32427508, %edi
call malloc@PLT
movq %rax, N(%rip)
movl %ebp, (%rax)
movl %ebx, 4(%rax)
testl %ebp, %ebp
jle .L44
movl $0, %r13d
leaq _ZSt3cin(%rip), %r12
.L47:
movl %r13d, %ebp
addl $1, %r13d
cmpl SIZE(%rip), %r13d
jge .L44
movl %r13d, %ebx
.L46:
leaq 4(%rsp), %rsi
movq %r12, %rdi
call _ZNSirsERi@PLT
movq N(%rip), %rcx
movl SIZE(%rip), %edx
movl 4(%rsp), %esi
movl %edx, %eax
imull %ebp, %eax
addl %ebx, %eax
cltq
movl %esi, 8(%rcx,%rax,4)
movl %edx, %eax
imull %ebx, %eax
addl %ebp, %eax
cltq
movl %esi, 8(%rcx,%rax,4)
addl $1, %ebx
cmpl %ebx, %edx
jg .L46
cmpl %r13d, %edx
jg .L47
.L44:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L52
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4578:
.size _Z9readInputv, .-_Z9readInputv
.globl _Z15sizeDefinitionsv
.type _Z15sizeDefinitionsv, @function
_Z15sizeDefinitionsv:
.LFB4579:
.cfi_startproc
endbr64
movl $6, %edx
leaq -4+bib(%rip), %rsi
.L54:
leal -3(%rdx), %ecx
leal -2(%rdx), %eax
imull %eax, %ecx
leal -1(%rdx), %eax
imull %ecx, %eax
imull %edx, %eax
movslq %eax, %rcx
imulq $715827883, %rcx, %rcx
sarq $34, %rcx
sarl $31, %eax
subl %eax, %ecx
movl %ecx, (%rsi,%rdx,4)
addq $1, %rdx
cmpq $86, %rdx
jne .L54
ret
.cfi_endproc
.LFE4579:
.size _Z15sizeDefinitionsv, .-_Z15sizeDefinitionsv
.globl _Z48__device_stub__Z12tmfgParallelP4Node6ParamsPiS2_P4NodeR6ParamsPiS3_
.type _Z48__device_stub__Z12tmfgParallelP4Node6ParamsPiS2_P4NodeR6ParamsPiS3_, @function
_Z48__device_stub__Z12tmfgParallelP4Node6ParamsPiS2_P4NodeR6ParamsPiS3_:
.LFB4605:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsi, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L60
.L56:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L61
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12tmfgParallelP4Node6ParamsPiS2_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L56
.L61:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4605:
.size _Z48__device_stub__Z12tmfgParallelP4Node6ParamsPiS2_P4NodeR6ParamsPiS3_, .-_Z48__device_stub__Z12tmfgParallelP4Node6ParamsPiS2_P4NodeR6ParamsPiS3_
.globl _Z12tmfgParallelP4Node6ParamsPiS2_
.type _Z12tmfgParallelP4Node6ParamsPiS2_, @function
_Z12tmfgParallelP4Node6ParamsPiS2_:
.LFB4606:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rdx, %rcx
movq %rsi, %rdx
leaq 16(%rsp), %rsi
call _Z48__device_stub__Z12tmfgParallelP4Node6ParamsPiS2_P4NodeR6ParamsPiS3_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4606:
.size _Z12tmfgParallelP4Node6ParamsPiS2_, .-_Z12tmfgParallelP4Node6ParamsPiS2_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "/home/ubuntu/Datasets/stackv2/train-structured/viniscoelho/dimpling/master/dimpling/face/previous-versions/3-tmfg-agsh.cu"
.section .rodata.str1.1
.LC4:
.string "GPUassert: %s %s %d\n"
.LC5:
.string "Amount of memory: "
.LC6:
.string "MB"
.LC7:
.string "1 done."
.LC8:
.string "2 done."
.LC9:
.string "Launching kernel..."
.LC10:
.string "Kernel finished."
.LC11:
.string "3 done."
.LC12:
.string "Completed."
.text
.globl _Z11tmfgPreparev
.type _Z11tmfgPreparev, @function
_Z11tmfgPreparev:
.LFB4573:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $168, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movl $0, 8(%rsp)
movl $0, 12(%rsp)
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L124
.L65:
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L125
.L66:
leaq 8(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L126
.L67:
leaq 12(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L127
.L68:
movl $18, %edx
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl PERM(%rip), %eax
movl %eax, %edx
imull SIZE(%rip), %edx
leal (%rax,%rax,2), %eax
addl %edx, %eax
cltq
leal (%rdx,%rdx,2), %edx
addl %edx, %edx
movslq %edx, %rdx
leaq (%rax,%rdx,4), %rdx
movabsq $4835703278458516699, %rcx
movq %rdx, %rax
mulq %rcx
shrq $18, %rdx
movq %rdx, %rsi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbx
movl $2, %edx
leaq .LC6(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L128
cmpb $0, 56(%rbp)
je .L71
movzbl 67(%rbp), %esi
.L72:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq 32(%rsp), %rdi
movl $32427508, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L129
.L73:
movl $1, %ecx
movl $32427508, %edx
movq N(%rip), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L130
.L74:
movl $7, %edx
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L131
cmpb $0, 56(%rbx)
je .L77
movzbl 67(%rbx), %esi
.L78:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movslq PERM(%rip), %rsi
salq $2, %rsi
leaq 64(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L132
.L79:
movslq PERM(%rip), %rsi
salq $2, %rsi
leaq 72(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L133
.L80:
movslq PERM(%rip), %rsi
salq $2, %rsi
leaq 80(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L134
.L81:
movl PERM(%rip), %eax
imull SIZE(%rip), %eax
leal (%rax,%rax,2), %esi
addl %esi, %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 88(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L135
.L82:
movl PERM(%rip), %esi
imull SIZE(%rip), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 96(%rsp), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L136
.L83:
movl $7, %edx
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L137
cmpb $0, 56(%rbx)
je .L86
movzbl 67(%rbx), %esi
.L87:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl BLOCKS(%rip), %eax
movl %eax, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1024, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $19, %edx
leaq .LC9(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L138
cmpb $0, 56(%rbx)
je .L90
movzbl 67(%rbx), %esi
.L91:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl SIZE(%rip), %eax
imull %eax, %eax
cltq
movl 60(%rsp), %ecx
movl $0, %r9d
leaq 0(,%rax,4), %r8
movq 52(%rsp), %rdx
movq 40(%rsp), %rdi
movl 48(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L139
.L92:
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L140
.L93:
movl $16, %edx
leaq .LC10(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L141
cmpb $0, 56(%rbx)
je .L96
movzbl 67(%rbx), %esi
.L97:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq 8(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L142
.L98:
movl $7, %edx
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L143
cmpb $0, 56(%rbx)
je .L101
movzbl 67(%rbx), %esi
.L102:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq 12(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L144
.L103:
movl $7, %edx
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L145
cmpb $0, 56(%rbx)
je .L106
movzbl 67(%rbx), %esi
.L107:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $7, %edx
leaq .LC11(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L146
cmpb $0, 56(%rbx)
je .L110
movzbl 67(%rbx), %esi
.L111:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L147
.L112:
movq 64(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L148
.L113:
movq 72(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L149
.L114:
movq 80(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L150
.L115:
movq 88(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L151
.L116:
movq 96(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L152
.L117:
movl $10, %edx
leaq .LC12(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L153
cmpb $0, 56(%rbx)
je .L120
movzbl 67(%rbx), %esi
.L121:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl 8(%rsp), %eax
movq 152(%rsp), %rdx
subq %fs:40, %rdx
jne .L154
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L124:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $224, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq stdin(%rip), %rdi
call getc@PLT
jmp .L65
.L125:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $225, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq stdin(%rip), %rdi
call getc@PLT
jmp .L66
.L126:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $226, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq stdin(%rip), %rdi
call getc@PLT
jmp .L67
.L127:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $227, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq stdin(%rip), %rdi
call getc@PLT
jmp .L68
.L128:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L155
call _ZSt16__throw_bad_castv@PLT
.L155:
call __stack_chk_fail@PLT
.L71:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L72
.L129:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $234, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq stdin(%rip), %rdi
call getc@PLT
jmp .L73
.L130:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $235, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq stdin(%rip), %rdi
call getc@PLT
jmp .L74
.L131:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L156
call _ZSt16__throw_bad_castv@PLT
.L156:
call __stack_chk_fail@PLT
.L77:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L78
.L132:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $238, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq stdin(%rip), %rdi
call getc@PLT
jmp .L79
.L133:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $239, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq stdin(%rip), %rdi
call getc@PLT
jmp .L80
.L134:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $240, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq stdin(%rip), %rdi
call getc@PLT
jmp .L81
.L135:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $241, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq stdin(%rip), %rdi
call getc@PLT
jmp .L82
.L136:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $242, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq stdin(%rip), %rdi
call getc@PLT
jmp .L83
.L137:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L157
call _ZSt16__throw_bad_castv@PLT
.L157:
call __stack_chk_fail@PLT
.L86:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L87
.L138:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L158
call _ZSt16__throw_bad_castv@PLT
.L158:
call __stack_chk_fail@PLT
.L90:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L91
.L139:
movdqa 64(%rsp), %xmm0
movaps %xmm0, 112(%rsp)
movdqa 80(%rsp), %xmm1
movaps %xmm1, 128(%rsp)
movq 96(%rsp), %rax
movq %rax, 144(%rsp)
leaq 112(%rsp), %rsi
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 32(%rsp), %rdi
call _Z48__device_stub__Z12tmfgParallelP4Node6ParamsPiS2_P4NodeR6ParamsPiS3_
jmp .L92
.L140:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $250, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq stdin(%rip), %rdi
call getc@PLT
jmp .L93
.L141:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L159
call _ZSt16__throw_bad_castv@PLT
.L159:
call __stack_chk_fail@PLT
.L96:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L97
.L142:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $255, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq stdin(%rip), %rdi
call getc@PLT
jmp .L98
.L143:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L160
call _ZSt16__throw_bad_castv@PLT
.L160:
call __stack_chk_fail@PLT
.L101:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L102
.L144:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $257, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq stdin(%rip), %rdi
call getc@PLT
jmp .L103
.L145:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L161
call _ZSt16__throw_bad_castv@PLT
.L161:
call __stack_chk_fail@PLT
.L106:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L107
.L146:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L162
call _ZSt16__throw_bad_castv@PLT
.L162:
call __stack_chk_fail@PLT
.L110:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L111
.L147:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $262, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq stdin(%rip), %rdi
call getc@PLT
jmp .L112
.L148:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $263, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq stdin(%rip), %rdi
call getc@PLT
jmp .L113
.L149:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $264, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq stdin(%rip), %rdi
call getc@PLT
jmp .L114
.L150:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $265, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq stdin(%rip), %rdi
call getc@PLT
jmp .L115
.L151:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $266, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq stdin(%rip), %rdi
call getc@PLT
jmp .L116
.L152:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $267, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq stdin(%rip), %rdi
call getc@PLT
jmp .L117
.L153:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L163
call _ZSt16__throw_bad_castv@PLT
.L163:
call __stack_chk_fail@PLT
.L120:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L121
.L154:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4573:
.size _Z11tmfgPreparev, .-_Z11tmfgPreparev
.section .rodata.str1.1
.LC13:
.string "Maximum weight found: "
.text
.globl main
.type main, @function
main:
.LFB4580:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl $0, %edi
call _ZNSt8ios_base15sync_with_stdioEb@PLT
call _Z15sizeDefinitionsv
call _Z9readInputv
call _Z10initializev
call _Z7combinev
movl $3, %edi
call cudaSetDevice@PLT
call clock@PLT
movq %rax, start(%rip)
call _Z11tmfgPreparev
movl %eax, %ebx
call clock@PLT
movq %rax, %rsi
movq %rax, stop(%rip)
movq start(%rip), %rdi
call _Z16printElapsedTimell
leaq .LC13(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq N(%rip), %rdi
call free@PLT
call cudaDeviceReset@PLT
testl %eax, %eax
jne .L167
.L165:
movl $0, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L167:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $395, %r9d
leaq .LC3(%rip), %r8
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movq stdin(%rip), %rdi
call getc@PLT
jmp .L165
.cfi_endproc
.LFE4580:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC14:
.string "_Z12tmfgParallelP4Node6ParamsPiS2_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4608:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z12tmfgParallelP4Node6ParamsPiS2_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4608:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl N
.bss
.align 8
.type N, @object
.size N, 8
N:
.zero 8
.globl bib
.align 32
.type bib, @object
.size bib, 340
bib:
.zero 340
.globl F
.align 32
.type F, @object
.size F, 2720
F:
.zero 2720
.globl R
.align 32
.type R, @object
.size R, 28900
R:
.zero 28900
.globl qtd
.align 4
.type qtd, @object
.size qtd, 4
qtd:
.zero 4
.globl PERM
.align 4
.type PERM, @object
.size PERM, 4
PERM:
.zero 4
.globl BLOCKS
.align 4
.type BLOCKS, @object
.size BLOCKS, 4
BLOCKS:
.zero 4
.globl SIZE
.align 4
.type SIZE, @object
.size SIZE, 4
SIZE:
.zero 4
.globl stop
.align 8
.type stop, @object
.size stop, 8
stop:
.zero 8
.globl start
.align 8
.type start, @object
.size start, 8
start:
.zero 8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <algorithm>
#include <cmath>
#include <cstdio>
#include <cstdlib>
#include <iomanip>
#include <iostream>
#include <vector>
#define C 4
#define THREADS 1024 // 2^10
#define MAX 85
#define MAX_S MAX* MAX
#define PERM_MAX (MAX * (MAX - 1) * (MAX - 2) * (MAX - 3)) / 24
#define pb push_back
#define mp make_pair
#define gpuErrChk(ans) \
{ \
gpuAssert((ans), __FILE__, __LINE__); \
}
inline void gpuAssert(cudaError_t code, char* file, int line, bool abort = true)
{
if (code != cudaSuccess) {
fprintf(stderr, "GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort)
getchar();
}
}
using namespace std;
typedef long long int64;
typedef pair<int, int> ii;
/*
sz ---> Adjacency matrix dimension (1D)
perm ---> Number of permutations of an instance
graph ---> Adjacency matrix itself
seeds ---> Set of seeds
faces ---> Set of triangular faces for the output
*/
struct Node {
int sz, perm;
int graph[MAX_S], seeds[C * PERM_MAX], F_ANS[6 * MAX];
};
/*
faces ---> Number of triangular faces
count ---> Number of remaining vertices
tmpMax ---> Max value obtained for a seed
F ---> Set of triangular faces
F ---> Set of remaining vertices
*/
struct Params {
int *faces, *count, *tmpMax;
int *F, *V;
};
/*
SIZE ---> Number of vertices
BLOCKS ---> Number of blocks
PERM ---> Number of permutations
R ---> Output graph for a possible solution
F ---> Set of triangular faces of an instance
qtd ---> Number of possible 4-cliques
*/
clock_t start, stop;
int SIZE, BLOCKS, PERM, qtd = 0;
int R[MAX_S], F[8 * MAX], bib[MAX];
Node* N;
__device__ void initializeDevice(Params* devP, int sz, int t)
{
devP->faces[t] = 0;
devP->tmpMax[t] = -1;
devP->count[t] = sz - 4;
}
/*
Generates a list containing the vertices which are not on the planar graph
*/
__device__ void generateList(Node* devN, Params* devP, int t)
{
int sz = devN->sz;
int va = devN->seeds[t], vb = devN->seeds[t + devN->perm], vc = devN->seeds[t + 2 * devN->perm], vd = devN->seeds[t + 3 * devN->perm];
for (int i = 0; i < sz; i++) {
if (i == va || i == vb || i == vc || i == vd)
devP->V[t + i * devN->perm] = -1;
else
devP->V[t + i * devN->perm] = i;
}
}
/*
Returns the weight of the planar graph so far
*/
__device__ void generateTriangularFaceList(Node* devN, Params* devP, int graph[], int t)
{
int sz = devN->sz;
int va = devN->seeds[t];
int vb = devN->seeds[t + devN->perm];
int vc = devN->seeds[t + 2 * devN->perm];
int vd = devN->seeds[t + 3 * devN->perm];
//generate first triangle of the output graph
devP->F[t + (devP->faces[t] * 3) * devN->perm] = va;
devP->F[t + (devP->faces[t] * 3 + 1) * devN->perm] = vb;
devP->F[t + ((devP->faces[t]++) * 3 + 2) * devN->perm] = vc;
int resp = graph[va * sz + vb] + graph[va * sz + vc] + graph[vb * sz + vc];
//generate the next 3 possible faces
devP->F[t + (devP->faces[t] * 3) * devN->perm] = va;
devP->F[t + (devP->faces[t] * 3 + 1) * devN->perm] = vb;
devP->F[t + ((devP->faces[t]++) * 3 + 2) * devN->perm] = vd;
devP->F[t + (devP->faces[t] * 3) * devN->perm] = va;
devP->F[t + (devP->faces[t] * 3 + 1) * devN->perm] = vc;
devP->F[t + ((devP->faces[t]++) * 3 + 2) * devN->perm] = vd;
devP->F[t + (devP->faces[t] * 3) * devN->perm] = vb;
devP->F[t + (devP->faces[t] * 3 + 1) * devN->perm] = vc;
devP->F[t + ((devP->faces[t]++) * 3 + 2) * devN->perm] = vd;
resp += graph[va * sz + vd] + graph[vb * sz + vd] + graph[vc * sz + vd];
devP->tmpMax[t] = resp;
}
/*
Insert a new vertex, 3 new triangular faces and removes face 'f' from the set
*/
__device__ int operationT2(Node* devN, Params* devP, int graph[], int new_vertex, int f, int t)
{
int sz = devN->sz, perm = devN->perm;
//remove the chosen face and insert a new one
int va = devP->F[t + (f * 3) * perm];
int vb = devP->F[t + (f * 3 + 1) * perm];
int vc = devP->F[t + (f * 3 + 2) * perm];
devP->F[t + (f * 3) * perm] = new_vertex;
devP->F[t + (f * 3 + 1) * perm] = va;
devP->F[t + (f * 3 + 2) * perm] = vb;
//and insert the other two possible faces
devP->F[t + (devP->faces[t] * 3) * perm] = new_vertex;
devP->F[t + (devP->faces[t] * 3 + 1) * perm] = va;
devP->F[t + ((devP->faces[t]++) * 3 + 2) * perm] = vc;
devP->F[t + (devP->faces[t] * 3) * perm] = new_vertex;
devP->F[t + (devP->faces[t] * 3 + 1) * perm] = vb;
devP->F[t + ((devP->faces[t]++) * 3 + 2) * perm] = vc;
int resp = graph[va * sz + new_vertex] + graph[vb * sz + new_vertex] + graph[vc * sz + new_vertex];
return resp;
}
/*
Return the vertex with the maximum gain inserting within a face 'f'
*/
__device__ int maxGain(Node* devN, Params* devP, int graph[], int* f, int t)
{
int sz = devN->sz, perm = devN->perm;
int gain = -1, vertex = -1;
//iterate through the remaining vertices
for (int new_vertex = 0; new_vertex < sz; new_vertex++) {
if (devP->V[t + new_vertex * perm] == -1)
continue;
//and test which has the maximum gain with its insetion
//within all possible faces
int faces = devP->faces[t];
for (int i = 0; i < faces; i++) {
int va = devP->F[t + (i * 3) * perm], vb = devP->F[t + (i * 3 + 1) * perm], vc = devP->F[t + (i * 3 + 2) * perm];
int tmpGain = graph[va * sz + new_vertex] + graph[vb * sz + new_vertex] + graph[vc * sz + new_vertex];
if (tmpGain > gain) {
gain = tmpGain;
*f = i;
vertex = new_vertex;
}
}
}
return vertex;
}
__device__ void tmfg(Node* devN, Params* devP, int graph[], int t)
{
while (devP->count[t]) {
int f = -1;
int vertex = maxGain(devN, devP, graph, &f, t);
devP->V[t + vertex * devN->perm] = -1;
devP->tmpMax[t] += operationT2(devN, devP, graph, vertex, f, t);
devP->count[t]--;
}
}
__global__ void tmfgParallel(Node* devN, Params devP, int* respMax, int* idx)
{
int x = blockDim.x * blockIdx.x + threadIdx.x;
int sz = devN->sz, perm = devN->perm;
extern __shared__ int graph[];
for (int i = threadIdx.x; i < sz * sz; i += blockDim.x) {
graph[i] = devN->graph[i];
graph[i] = devN->graph[i];
}
__syncthreads();
if (x < perm) {
initializeDevice(&devP, sz, x);
generateList(devN, &devP, x);
generateTriangularFaceList(devN, &devP, graph, x);
tmfg(devN, &devP, graph, x);
__syncthreads();
atomicMax(respMax, devP.tmpMax[x]);
if (devP.tmpMax[x] == *respMax)
*idx = x;
__syncthreads();
}
}
int tmfgPrepare()
{
int resp = 0, idx = 0, *tmpResp, *tmpIdx;
gpuErrChk(cudaMalloc((void**)&tmpResp, sizeof(int)));
gpuErrChk(cudaMalloc((void**)&tmpIdx, sizeof(int)));
gpuErrChk(cudaMemcpy(tmpResp, &resp, sizeof(int), cudaMemcpyHostToDevice));
gpuErrChk(cudaMemcpy(tmpIdx, &idx, sizeof(int), cudaMemcpyHostToDevice));
Node* devN;
Params devP;
cout << "Amount of memory: " << (3 * PERM + PERM * SIZE + 6 * SIZE * PERM * sizeof(int)) / 1000000 << "MB" << endl;
gpuErrChk(cudaMalloc((void**)&devN, sizeof(Node)));
gpuErrChk(cudaMemcpy(devN, N, sizeof(Node), cudaMemcpyHostToDevice));
cout << "1 done." << endl;
gpuErrChk(cudaMalloc((void**)&devP.faces, PERM * sizeof(int)));
gpuErrChk(cudaMalloc((void**)&devP.count, PERM * sizeof(int)));
gpuErrChk(cudaMalloc((void**)&devP.tmpMax, PERM * sizeof(int)));
gpuErrChk(cudaMalloc((void**)&devP.F, PERM * 6 * SIZE * sizeof(int)));
gpuErrChk(cudaMalloc((void**)&devP.V, PERM * SIZE * sizeof(int)));
cout << "2 done." << endl;
dim3 blocks(BLOCKS, 1);
dim3 threads(THREADS, 1);
cout << "Launching kernel..." << endl;
tmfgParallel<<<blocks, threads, SIZE * SIZE * sizeof(int)>>>(devN, devP, tmpResp, tmpIdx);
gpuErrChk(cudaDeviceSynchronize());
cout << "Kernel finished." << endl;
//copy back the maximum weight and the index of the graph
//which gave this result
gpuErrChk(cudaMemcpy(&resp, tmpResp, sizeof(int), cudaMemcpyDeviceToHost));
cout << "1 done." << endl;
gpuErrChk(cudaMemcpy(&idx, tmpIdx, sizeof(int), cudaMemcpyDeviceToHost));
cout << "2 done." << endl;
//gpuErrChk(cudaMemcpy(&F, devP.F[idx + ], (6*MAX)*sizeof(int), cudaMemcpyDeviceToHost));
cout << "3 done." << endl;
gpuErrChk(cudaFree(devN));
gpuErrChk(cudaFree(devP.faces));
gpuErrChk(cudaFree(devP.count));
gpuErrChk(cudaFree(devP.tmpMax));
gpuErrChk(cudaFree(devP.F));
gpuErrChk(cudaFree(devP.V));
cout << "Completed." << endl;
return resp;
}
void printElapsedTime(clock_t start, clock_t stop)
{
double elapsed = ((double)(stop - start)) / CLOCKS_PER_SEC;
cout << fixed << setprecision(3) << "Elapsed time: " << elapsed << "s\n";
}
/*
C ---> Size of the combination
index ---> Current index in data[]
data[] ---> Temporary array to store a current combination
i ---> Index of current element in vertices[]
*/
void combineUntil(int index, vector<int>& data, int i)
{
// Current cobination is ready, print it
if (index == C) {
for (int j = 0; j < C; j++) {
N->seeds[qtd + j * PERM] = data[j];
}
qtd++;
return;
}
// When there are no more elements to put in data[]
if (i >= SIZE)
return;
//current is inserted; put next at a next location
data[index] = i;
combineUntil(index + 1, data, i + 1);
//current is deleted; replace it with next
combineUntil(index, data, i + 1);
}
/*
Print all combinations of size 'C' using a temporary array 'data'
*/
void combine()
{
vector<int> data(C);
combineUntil(0, data, 0);
}
void initialize()
{
for (int i = 0; i < SIZE; i++) {
for (int j = i + 1; j < SIZE; j++) {
R[i * SIZE + j] = R[j * SIZE + i] = -1;
}
}
}
void readInput()
{
int x;
cin >> SIZE;
PERM = bib[SIZE - 1];
BLOCKS = PERM / THREADS + 1;
N = (Node*)malloc(sizeof(Node));
N->sz = SIZE;
N->perm = PERM;
for (int i = 0; i < SIZE; i++) {
for (int j = i + 1; j < SIZE; j++) {
cin >> x;
N->graph[i * SIZE + j] = x;
N->graph[j * SIZE + i] = x;
}
}
}
/*
Define the number of permutations and blocks
*/
void sizeDefinitions()
{
for (int i = 6; i <= MAX; i++) {
int resp = 1;
for (int j = i - 3; j <= i; j++)
resp *= j;
resp /= 24;
bib[i - 1] = resp;
}
}
int main(int argv, char** argc)
{
ios::sync_with_stdio(false);
sizeDefinitions();
//read the input, which is given by a size of a graph and its weighted edges.
//the graph given is dense.
readInput();
initialize();
//generate multiple 4-clique seeds, given the number of vertices
combine();
cudaSetDevice(3);
start = clock();
int respMax = tmfgPrepare();
stop = clock();
//reconstruct the graph given the regions of the graph
// for ( int i = 0; i < 2*SIZE; i++ ){
// int va = F[i*3], vb = F[i*3 + 1], vc = F[i*3 + 2];
// if ( va == vb && vb == vc ) continue;
// R[va*SIZE + vb] = R[vb*SIZE + va] = N->graph[va*SIZE + vb];
// R[va*SIZE + vc] = R[vc*SIZE + va] = N->graph[va*SIZE + vc];
// R[vb*SIZE + vc] = R[vc*SIZE + vb] = N->graph[vb*SIZE + vc];
// }
// cout << "Printing generated graph: " << endl;
// for ( int i = 0; i < SIZE; i++ ){
// for ( int j = i+1; j < SIZE; j++ ){
// cout << R[i*SIZE + j] << " ";
// }
// cout << endl;
// }
printElapsedTime(start, stop);
cout << "Maximum weight found: " << respMax << endl;
free(N);
gpuErrChk(cudaDeviceReset());
return 0;
} | #include <hip/hip_runtime.h>
#include <algorithm>
#include <cmath>
#include <cstdio>
#include <cstdlib>
#include <iomanip>
#include <iostream>
#include <vector>
#define C 4
#define THREADS 1024 // 2^10
#define MAX 85
#define MAX_S MAX* MAX
#define PERM_MAX (MAX * (MAX - 1) * (MAX - 2) * (MAX - 3)) / 24
#define pb push_back
#define mp make_pair
#define gpuErrChk(ans) \
{ \
gpuAssert((ans), __FILE__, __LINE__); \
}
inline void gpuAssert(hipError_t code, char* file, int line, bool abort = true)
{
if (code != hipSuccess) {
fprintf(stderr, "GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort)
getchar();
}
}
using namespace std;
typedef long long int64;
typedef pair<int, int> ii;
/*
sz ---> Adjacency matrix dimension (1D)
perm ---> Number of permutations of an instance
graph ---> Adjacency matrix itself
seeds ---> Set of seeds
faces ---> Set of triangular faces for the output
*/
struct Node {
int sz, perm;
int graph[MAX_S], seeds[C * PERM_MAX], F_ANS[6 * MAX];
};
/*
faces ---> Number of triangular faces
count ---> Number of remaining vertices
tmpMax ---> Max value obtained for a seed
F ---> Set of triangular faces
F ---> Set of remaining vertices
*/
struct Params {
int *faces, *count, *tmpMax;
int *F, *V;
};
/*
SIZE ---> Number of vertices
BLOCKS ---> Number of blocks
PERM ---> Number of permutations
R ---> Output graph for a possible solution
F ---> Set of triangular faces of an instance
qtd ---> Number of possible 4-cliques
*/
clock_t start, stop;
int SIZE, BLOCKS, PERM, qtd = 0;
int R[MAX_S], F[8 * MAX], bib[MAX];
Node* N;
__device__ void initializeDevice(Params* devP, int sz, int t)
{
devP->faces[t] = 0;
devP->tmpMax[t] = -1;
devP->count[t] = sz - 4;
}
/*
Generates a list containing the vertices which are not on the planar graph
*/
__device__ void generateList(Node* devN, Params* devP, int t)
{
int sz = devN->sz;
int va = devN->seeds[t], vb = devN->seeds[t + devN->perm], vc = devN->seeds[t + 2 * devN->perm], vd = devN->seeds[t + 3 * devN->perm];
for (int i = 0; i < sz; i++) {
if (i == va || i == vb || i == vc || i == vd)
devP->V[t + i * devN->perm] = -1;
else
devP->V[t + i * devN->perm] = i;
}
}
/*
Returns the weight of the planar graph so far
*/
__device__ void generateTriangularFaceList(Node* devN, Params* devP, int graph[], int t)
{
int sz = devN->sz;
int va = devN->seeds[t];
int vb = devN->seeds[t + devN->perm];
int vc = devN->seeds[t + 2 * devN->perm];
int vd = devN->seeds[t + 3 * devN->perm];
//generate first triangle of the output graph
devP->F[t + (devP->faces[t] * 3) * devN->perm] = va;
devP->F[t + (devP->faces[t] * 3 + 1) * devN->perm] = vb;
devP->F[t + ((devP->faces[t]++) * 3 + 2) * devN->perm] = vc;
int resp = graph[va * sz + vb] + graph[va * sz + vc] + graph[vb * sz + vc];
//generate the next 3 possible faces
devP->F[t + (devP->faces[t] * 3) * devN->perm] = va;
devP->F[t + (devP->faces[t] * 3 + 1) * devN->perm] = vb;
devP->F[t + ((devP->faces[t]++) * 3 + 2) * devN->perm] = vd;
devP->F[t + (devP->faces[t] * 3) * devN->perm] = va;
devP->F[t + (devP->faces[t] * 3 + 1) * devN->perm] = vc;
devP->F[t + ((devP->faces[t]++) * 3 + 2) * devN->perm] = vd;
devP->F[t + (devP->faces[t] * 3) * devN->perm] = vb;
devP->F[t + (devP->faces[t] * 3 + 1) * devN->perm] = vc;
devP->F[t + ((devP->faces[t]++) * 3 + 2) * devN->perm] = vd;
resp += graph[va * sz + vd] + graph[vb * sz + vd] + graph[vc * sz + vd];
devP->tmpMax[t] = resp;
}
/*
Insert a new vertex, 3 new triangular faces and removes face 'f' from the set
*/
__device__ int operationT2(Node* devN, Params* devP, int graph[], int new_vertex, int f, int t)
{
int sz = devN->sz, perm = devN->perm;
//remove the chosen face and insert a new one
int va = devP->F[t + (f * 3) * perm];
int vb = devP->F[t + (f * 3 + 1) * perm];
int vc = devP->F[t + (f * 3 + 2) * perm];
devP->F[t + (f * 3) * perm] = new_vertex;
devP->F[t + (f * 3 + 1) * perm] = va;
devP->F[t + (f * 3 + 2) * perm] = vb;
//and insert the other two possible faces
devP->F[t + (devP->faces[t] * 3) * perm] = new_vertex;
devP->F[t + (devP->faces[t] * 3 + 1) * perm] = va;
devP->F[t + ((devP->faces[t]++) * 3 + 2) * perm] = vc;
devP->F[t + (devP->faces[t] * 3) * perm] = new_vertex;
devP->F[t + (devP->faces[t] * 3 + 1) * perm] = vb;
devP->F[t + ((devP->faces[t]++) * 3 + 2) * perm] = vc;
int resp = graph[va * sz + new_vertex] + graph[vb * sz + new_vertex] + graph[vc * sz + new_vertex];
return resp;
}
/*
Return the vertex with the maximum gain inserting within a face 'f'
*/
__device__ int maxGain(Node* devN, Params* devP, int graph[], int* f, int t)
{
int sz = devN->sz, perm = devN->perm;
int gain = -1, vertex = -1;
//iterate through the remaining vertices
for (int new_vertex = 0; new_vertex < sz; new_vertex++) {
if (devP->V[t + new_vertex * perm] == -1)
continue;
//and test which has the maximum gain with its insetion
//within all possible faces
int faces = devP->faces[t];
for (int i = 0; i < faces; i++) {
int va = devP->F[t + (i * 3) * perm], vb = devP->F[t + (i * 3 + 1) * perm], vc = devP->F[t + (i * 3 + 2) * perm];
int tmpGain = graph[va * sz + new_vertex] + graph[vb * sz + new_vertex] + graph[vc * sz + new_vertex];
if (tmpGain > gain) {
gain = tmpGain;
*f = i;
vertex = new_vertex;
}
}
}
return vertex;
}
__device__ void tmfg(Node* devN, Params* devP, int graph[], int t)
{
while (devP->count[t]) {
int f = -1;
int vertex = maxGain(devN, devP, graph, &f, t);
devP->V[t + vertex * devN->perm] = -1;
devP->tmpMax[t] += operationT2(devN, devP, graph, vertex, f, t);
devP->count[t]--;
}
}
__global__ void tmfgParallel(Node* devN, Params devP, int* respMax, int* idx)
{
int x = blockDim.x * blockIdx.x + threadIdx.x;
int sz = devN->sz, perm = devN->perm;
extern __shared__ int graph[];
for (int i = threadIdx.x; i < sz * sz; i += blockDim.x) {
graph[i] = devN->graph[i];
graph[i] = devN->graph[i];
}
__syncthreads();
if (x < perm) {
initializeDevice(&devP, sz, x);
generateList(devN, &devP, x);
generateTriangularFaceList(devN, &devP, graph, x);
tmfg(devN, &devP, graph, x);
__syncthreads();
atomicMax(respMax, devP.tmpMax[x]);
if (devP.tmpMax[x] == *respMax)
*idx = x;
__syncthreads();
}
}
int tmfgPrepare()
{
int resp = 0, idx = 0, *tmpResp, *tmpIdx;
gpuErrChk(hipMalloc((void**)&tmpResp, sizeof(int)));
gpuErrChk(hipMalloc((void**)&tmpIdx, sizeof(int)));
gpuErrChk(hipMemcpy(tmpResp, &resp, sizeof(int), hipMemcpyHostToDevice));
gpuErrChk(hipMemcpy(tmpIdx, &idx, sizeof(int), hipMemcpyHostToDevice));
Node* devN;
Params devP;
cout << "Amount of memory: " << (3 * PERM + PERM * SIZE + 6 * SIZE * PERM * sizeof(int)) / 1000000 << "MB" << endl;
gpuErrChk(hipMalloc((void**)&devN, sizeof(Node)));
gpuErrChk(hipMemcpy(devN, N, sizeof(Node), hipMemcpyHostToDevice));
cout << "1 done." << endl;
gpuErrChk(hipMalloc((void**)&devP.faces, PERM * sizeof(int)));
gpuErrChk(hipMalloc((void**)&devP.count, PERM * sizeof(int)));
gpuErrChk(hipMalloc((void**)&devP.tmpMax, PERM * sizeof(int)));
gpuErrChk(hipMalloc((void**)&devP.F, PERM * 6 * SIZE * sizeof(int)));
gpuErrChk(hipMalloc((void**)&devP.V, PERM * SIZE * sizeof(int)));
cout << "2 done." << endl;
dim3 blocks(BLOCKS, 1);
dim3 threads(THREADS, 1);
cout << "Launching kernel..." << endl;
tmfgParallel<<<blocks, threads, SIZE * SIZE * sizeof(int)>>>(devN, devP, tmpResp, tmpIdx);
gpuErrChk(hipDeviceSynchronize());
cout << "Kernel finished." << endl;
//copy back the maximum weight and the index of the graph
//which gave this result
gpuErrChk(hipMemcpy(&resp, tmpResp, sizeof(int), hipMemcpyDeviceToHost));
cout << "1 done." << endl;
gpuErrChk(hipMemcpy(&idx, tmpIdx, sizeof(int), hipMemcpyDeviceToHost));
cout << "2 done." << endl;
//gpuErrChk(cudaMemcpy(&F, devP.F[idx + ], (6*MAX)*sizeof(int), cudaMemcpyDeviceToHost));
cout << "3 done." << endl;
gpuErrChk(hipFree(devN));
gpuErrChk(hipFree(devP.faces));
gpuErrChk(hipFree(devP.count));
gpuErrChk(hipFree(devP.tmpMax));
gpuErrChk(hipFree(devP.F));
gpuErrChk(hipFree(devP.V));
cout << "Completed." << endl;
return resp;
}
void printElapsedTime(clock_t start, clock_t stop)
{
double elapsed = ((double)(stop - start)) / CLOCKS_PER_SEC;
cout << fixed << setprecision(3) << "Elapsed time: " << elapsed << "s\n";
}
/*
C ---> Size of the combination
index ---> Current index in data[]
data[] ---> Temporary array to store a current combination
i ---> Index of current element in vertices[]
*/
void combineUntil(int index, vector<int>& data, int i)
{
// Current cobination is ready, print it
if (index == C) {
for (int j = 0; j < C; j++) {
N->seeds[qtd + j * PERM] = data[j];
}
qtd++;
return;
}
// When there are no more elements to put in data[]
if (i >= SIZE)
return;
//current is inserted; put next at a next location
data[index] = i;
combineUntil(index + 1, data, i + 1);
//current is deleted; replace it with next
combineUntil(index, data, i + 1);
}
/*
Print all combinations of size 'C' using a temporary array 'data'
*/
void combine()
{
vector<int> data(C);
combineUntil(0, data, 0);
}
void initialize()
{
for (int i = 0; i < SIZE; i++) {
for (int j = i + 1; j < SIZE; j++) {
R[i * SIZE + j] = R[j * SIZE + i] = -1;
}
}
}
void readInput()
{
int x;
cin >> SIZE;
PERM = bib[SIZE - 1];
BLOCKS = PERM / THREADS + 1;
N = (Node*)malloc(sizeof(Node));
N->sz = SIZE;
N->perm = PERM;
for (int i = 0; i < SIZE; i++) {
for (int j = i + 1; j < SIZE; j++) {
cin >> x;
N->graph[i * SIZE + j] = x;
N->graph[j * SIZE + i] = x;
}
}
}
/*
Define the number of permutations and blocks
*/
void sizeDefinitions()
{
for (int i = 6; i <= MAX; i++) {
int resp = 1;
for (int j = i - 3; j <= i; j++)
resp *= j;
resp /= 24;
bib[i - 1] = resp;
}
}
int main(int argv, char** argc)
{
ios::sync_with_stdio(false);
sizeDefinitions();
//read the input, which is given by a size of a graph and its weighted edges.
//the graph given is dense.
readInput();
initialize();
//generate multiple 4-clique seeds, given the number of vertices
combine();
hipSetDevice(3);
start = clock();
int respMax = tmfgPrepare();
stop = clock();
//reconstruct the graph given the regions of the graph
// for ( int i = 0; i < 2*SIZE; i++ ){
// int va = F[i*3], vb = F[i*3 + 1], vc = F[i*3 + 2];
// if ( va == vb && vb == vc ) continue;
// R[va*SIZE + vb] = R[vb*SIZE + va] = N->graph[va*SIZE + vb];
// R[va*SIZE + vc] = R[vc*SIZE + va] = N->graph[va*SIZE + vc];
// R[vb*SIZE + vc] = R[vc*SIZE + vb] = N->graph[vb*SIZE + vc];
// }
// cout << "Printing generated graph: " << endl;
// for ( int i = 0; i < SIZE; i++ ){
// for ( int j = i+1; j < SIZE; j++ ){
// cout << R[i*SIZE + j] << " ";
// }
// cout << endl;
// }
printElapsedTime(start, stop);
cout << "Maximum weight found: " << respMax << endl;
free(N);
gpuErrChk(hipDeviceReset());
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <algorithm>
#include <cmath>
#include <cstdio>
#include <cstdlib>
#include <iomanip>
#include <iostream>
#include <vector>
#define C 4
#define THREADS 1024 // 2^10
#define MAX 85
#define MAX_S MAX* MAX
#define PERM_MAX (MAX * (MAX - 1) * (MAX - 2) * (MAX - 3)) / 24
#define pb push_back
#define mp make_pair
#define gpuErrChk(ans) \
{ \
gpuAssert((ans), __FILE__, __LINE__); \
}
inline void gpuAssert(hipError_t code, char* file, int line, bool abort = true)
{
if (code != hipSuccess) {
fprintf(stderr, "GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort)
getchar();
}
}
using namespace std;
typedef long long int64;
typedef pair<int, int> ii;
/*
sz ---> Adjacency matrix dimension (1D)
perm ---> Number of permutations of an instance
graph ---> Adjacency matrix itself
seeds ---> Set of seeds
faces ---> Set of triangular faces for the output
*/
struct Node {
int sz, perm;
int graph[MAX_S], seeds[C * PERM_MAX], F_ANS[6 * MAX];
};
/*
faces ---> Number of triangular faces
count ---> Number of remaining vertices
tmpMax ---> Max value obtained for a seed
F ---> Set of triangular faces
F ---> Set of remaining vertices
*/
struct Params {
int *faces, *count, *tmpMax;
int *F, *V;
};
/*
SIZE ---> Number of vertices
BLOCKS ---> Number of blocks
PERM ---> Number of permutations
R ---> Output graph for a possible solution
F ---> Set of triangular faces of an instance
qtd ---> Number of possible 4-cliques
*/
clock_t start, stop;
int SIZE, BLOCKS, PERM, qtd = 0;
int R[MAX_S], F[8 * MAX], bib[MAX];
Node* N;
__device__ void initializeDevice(Params* devP, int sz, int t)
{
devP->faces[t] = 0;
devP->tmpMax[t] = -1;
devP->count[t] = sz - 4;
}
/*
Generates a list containing the vertices which are not on the planar graph
*/
__device__ void generateList(Node* devN, Params* devP, int t)
{
int sz = devN->sz;
int va = devN->seeds[t], vb = devN->seeds[t + devN->perm], vc = devN->seeds[t + 2 * devN->perm], vd = devN->seeds[t + 3 * devN->perm];
for (int i = 0; i < sz; i++) {
if (i == va || i == vb || i == vc || i == vd)
devP->V[t + i * devN->perm] = -1;
else
devP->V[t + i * devN->perm] = i;
}
}
/*
Returns the weight of the planar graph so far
*/
__device__ void generateTriangularFaceList(Node* devN, Params* devP, int graph[], int t)
{
int sz = devN->sz;
int va = devN->seeds[t];
int vb = devN->seeds[t + devN->perm];
int vc = devN->seeds[t + 2 * devN->perm];
int vd = devN->seeds[t + 3 * devN->perm];
//generate first triangle of the output graph
devP->F[t + (devP->faces[t] * 3) * devN->perm] = va;
devP->F[t + (devP->faces[t] * 3 + 1) * devN->perm] = vb;
devP->F[t + ((devP->faces[t]++) * 3 + 2) * devN->perm] = vc;
int resp = graph[va * sz + vb] + graph[va * sz + vc] + graph[vb * sz + vc];
//generate the next 3 possible faces
devP->F[t + (devP->faces[t] * 3) * devN->perm] = va;
devP->F[t + (devP->faces[t] * 3 + 1) * devN->perm] = vb;
devP->F[t + ((devP->faces[t]++) * 3 + 2) * devN->perm] = vd;
devP->F[t + (devP->faces[t] * 3) * devN->perm] = va;
devP->F[t + (devP->faces[t] * 3 + 1) * devN->perm] = vc;
devP->F[t + ((devP->faces[t]++) * 3 + 2) * devN->perm] = vd;
devP->F[t + (devP->faces[t] * 3) * devN->perm] = vb;
devP->F[t + (devP->faces[t] * 3 + 1) * devN->perm] = vc;
devP->F[t + ((devP->faces[t]++) * 3 + 2) * devN->perm] = vd;
resp += graph[va * sz + vd] + graph[vb * sz + vd] + graph[vc * sz + vd];
devP->tmpMax[t] = resp;
}
/*
Insert a new vertex, 3 new triangular faces and removes face 'f' from the set
*/
__device__ int operationT2(Node* devN, Params* devP, int graph[], int new_vertex, int f, int t)
{
int sz = devN->sz, perm = devN->perm;
//remove the chosen face and insert a new one
int va = devP->F[t + (f * 3) * perm];
int vb = devP->F[t + (f * 3 + 1) * perm];
int vc = devP->F[t + (f * 3 + 2) * perm];
devP->F[t + (f * 3) * perm] = new_vertex;
devP->F[t + (f * 3 + 1) * perm] = va;
devP->F[t + (f * 3 + 2) * perm] = vb;
//and insert the other two possible faces
devP->F[t + (devP->faces[t] * 3) * perm] = new_vertex;
devP->F[t + (devP->faces[t] * 3 + 1) * perm] = va;
devP->F[t + ((devP->faces[t]++) * 3 + 2) * perm] = vc;
devP->F[t + (devP->faces[t] * 3) * perm] = new_vertex;
devP->F[t + (devP->faces[t] * 3 + 1) * perm] = vb;
devP->F[t + ((devP->faces[t]++) * 3 + 2) * perm] = vc;
int resp = graph[va * sz + new_vertex] + graph[vb * sz + new_vertex] + graph[vc * sz + new_vertex];
return resp;
}
/*
Return the vertex with the maximum gain inserting within a face 'f'
*/
__device__ int maxGain(Node* devN, Params* devP, int graph[], int* f, int t)
{
int sz = devN->sz, perm = devN->perm;
int gain = -1, vertex = -1;
//iterate through the remaining vertices
for (int new_vertex = 0; new_vertex < sz; new_vertex++) {
if (devP->V[t + new_vertex * perm] == -1)
continue;
//and test which has the maximum gain with its insetion
//within all possible faces
int faces = devP->faces[t];
for (int i = 0; i < faces; i++) {
int va = devP->F[t + (i * 3) * perm], vb = devP->F[t + (i * 3 + 1) * perm], vc = devP->F[t + (i * 3 + 2) * perm];
int tmpGain = graph[va * sz + new_vertex] + graph[vb * sz + new_vertex] + graph[vc * sz + new_vertex];
if (tmpGain > gain) {
gain = tmpGain;
*f = i;
vertex = new_vertex;
}
}
}
return vertex;
}
__device__ void tmfg(Node* devN, Params* devP, int graph[], int t)
{
while (devP->count[t]) {
int f = -1;
int vertex = maxGain(devN, devP, graph, &f, t);
devP->V[t + vertex * devN->perm] = -1;
devP->tmpMax[t] += operationT2(devN, devP, graph, vertex, f, t);
devP->count[t]--;
}
}
__global__ void tmfgParallel(Node* devN, Params devP, int* respMax, int* idx)
{
int x = blockDim.x * blockIdx.x + threadIdx.x;
int sz = devN->sz, perm = devN->perm;
extern __shared__ int graph[];
for (int i = threadIdx.x; i < sz * sz; i += blockDim.x) {
graph[i] = devN->graph[i];
graph[i] = devN->graph[i];
}
__syncthreads();
if (x < perm) {
initializeDevice(&devP, sz, x);
generateList(devN, &devP, x);
generateTriangularFaceList(devN, &devP, graph, x);
tmfg(devN, &devP, graph, x);
__syncthreads();
atomicMax(respMax, devP.tmpMax[x]);
if (devP.tmpMax[x] == *respMax)
*idx = x;
__syncthreads();
}
}
int tmfgPrepare()
{
int resp = 0, idx = 0, *tmpResp, *tmpIdx;
gpuErrChk(hipMalloc((void**)&tmpResp, sizeof(int)));
gpuErrChk(hipMalloc((void**)&tmpIdx, sizeof(int)));
gpuErrChk(hipMemcpy(tmpResp, &resp, sizeof(int), hipMemcpyHostToDevice));
gpuErrChk(hipMemcpy(tmpIdx, &idx, sizeof(int), hipMemcpyHostToDevice));
Node* devN;
Params devP;
cout << "Amount of memory: " << (3 * PERM + PERM * SIZE + 6 * SIZE * PERM * sizeof(int)) / 1000000 << "MB" << endl;
gpuErrChk(hipMalloc((void**)&devN, sizeof(Node)));
gpuErrChk(hipMemcpy(devN, N, sizeof(Node), hipMemcpyHostToDevice));
cout << "1 done." << endl;
gpuErrChk(hipMalloc((void**)&devP.faces, PERM * sizeof(int)));
gpuErrChk(hipMalloc((void**)&devP.count, PERM * sizeof(int)));
gpuErrChk(hipMalloc((void**)&devP.tmpMax, PERM * sizeof(int)));
gpuErrChk(hipMalloc((void**)&devP.F, PERM * 6 * SIZE * sizeof(int)));
gpuErrChk(hipMalloc((void**)&devP.V, PERM * SIZE * sizeof(int)));
cout << "2 done." << endl;
dim3 blocks(BLOCKS, 1);
dim3 threads(THREADS, 1);
cout << "Launching kernel..." << endl;
tmfgParallel<<<blocks, threads, SIZE * SIZE * sizeof(int)>>>(devN, devP, tmpResp, tmpIdx);
gpuErrChk(hipDeviceSynchronize());
cout << "Kernel finished." << endl;
//copy back the maximum weight and the index of the graph
//which gave this result
gpuErrChk(hipMemcpy(&resp, tmpResp, sizeof(int), hipMemcpyDeviceToHost));
cout << "1 done." << endl;
gpuErrChk(hipMemcpy(&idx, tmpIdx, sizeof(int), hipMemcpyDeviceToHost));
cout << "2 done." << endl;
//gpuErrChk(cudaMemcpy(&F, devP.F[idx + ], (6*MAX)*sizeof(int), cudaMemcpyDeviceToHost));
cout << "3 done." << endl;
gpuErrChk(hipFree(devN));
gpuErrChk(hipFree(devP.faces));
gpuErrChk(hipFree(devP.count));
gpuErrChk(hipFree(devP.tmpMax));
gpuErrChk(hipFree(devP.F));
gpuErrChk(hipFree(devP.V));
cout << "Completed." << endl;
return resp;
}
void printElapsedTime(clock_t start, clock_t stop)
{
double elapsed = ((double)(stop - start)) / CLOCKS_PER_SEC;
cout << fixed << setprecision(3) << "Elapsed time: " << elapsed << "s\n";
}
/*
C ---> Size of the combination
index ---> Current index in data[]
data[] ---> Temporary array to store a current combination
i ---> Index of current element in vertices[]
*/
void combineUntil(int index, vector<int>& data, int i)
{
// Current cobination is ready, print it
if (index == C) {
for (int j = 0; j < C; j++) {
N->seeds[qtd + j * PERM] = data[j];
}
qtd++;
return;
}
// When there are no more elements to put in data[]
if (i >= SIZE)
return;
//current is inserted; put next at a next location
data[index] = i;
combineUntil(index + 1, data, i + 1);
//current is deleted; replace it with next
combineUntil(index, data, i + 1);
}
/*
Print all combinations of size 'C' using a temporary array 'data'
*/
void combine()
{
vector<int> data(C);
combineUntil(0, data, 0);
}
void initialize()
{
for (int i = 0; i < SIZE; i++) {
for (int j = i + 1; j < SIZE; j++) {
R[i * SIZE + j] = R[j * SIZE + i] = -1;
}
}
}
void readInput()
{
int x;
cin >> SIZE;
PERM = bib[SIZE - 1];
BLOCKS = PERM / THREADS + 1;
N = (Node*)malloc(sizeof(Node));
N->sz = SIZE;
N->perm = PERM;
for (int i = 0; i < SIZE; i++) {
for (int j = i + 1; j < SIZE; j++) {
cin >> x;
N->graph[i * SIZE + j] = x;
N->graph[j * SIZE + i] = x;
}
}
}
/*
Define the number of permutations and blocks
*/
void sizeDefinitions()
{
for (int i = 6; i <= MAX; i++) {
int resp = 1;
for (int j = i - 3; j <= i; j++)
resp *= j;
resp /= 24;
bib[i - 1] = resp;
}
}
int main(int argv, char** argc)
{
ios::sync_with_stdio(false);
sizeDefinitions();
//read the input, which is given by a size of a graph and its weighted edges.
//the graph given is dense.
readInput();
initialize();
//generate multiple 4-clique seeds, given the number of vertices
combine();
hipSetDevice(3);
start = clock();
int respMax = tmfgPrepare();
stop = clock();
//reconstruct the graph given the regions of the graph
// for ( int i = 0; i < 2*SIZE; i++ ){
// int va = F[i*3], vb = F[i*3 + 1], vc = F[i*3 + 2];
// if ( va == vb && vb == vc ) continue;
// R[va*SIZE + vb] = R[vb*SIZE + va] = N->graph[va*SIZE + vb];
// R[va*SIZE + vc] = R[vc*SIZE + va] = N->graph[va*SIZE + vc];
// R[vb*SIZE + vc] = R[vc*SIZE + vb] = N->graph[vb*SIZE + vc];
// }
// cout << "Printing generated graph: " << endl;
// for ( int i = 0; i < SIZE; i++ ){
// for ( int j = i+1; j < SIZE; j++ ){
// cout << R[i*SIZE + j] << " ";
// }
// cout << endl;
// }
printElapsedTime(start, stop);
cout << "Maximum weight found: " << respMax << endl;
free(N);
gpuErrChk(hipDeviceReset());
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12tmfgParallelP4Node6ParamsPiS2_
.globl _Z12tmfgParallelP4Node6ParamsPiS2_
.p2align 8
.type _Z12tmfgParallelP4Node6ParamsPiS2_,@function
_Z12tmfgParallelP4Node6ParamsPiS2_:
s_load_b256 s[16:23], s[0:1], 0x0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_load_b64 s[2:3], s[16:17], 0x0
s_clause 0x1
s_load_b32 s4, s[0:1], 0x4c
s_load_b128 s[8:11], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_mul_i32 s5, s2, s2
s_and_b32 s4, s4, 0xffff
v_cmpx_gt_u32_e64 s5, v0
s_cbranch_execz .LBB0_3
v_lshl_add_u32 v3, v0, 2, 0
v_mov_b32_e32 v1, v0
s_mov_b32 s7, 0
s_lshl_b32 s12, s4, 2
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, s4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s16, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s17, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cmp_le_i32_e32 vcc_lo, s5, v1
global_load_b32 v2, v[4:5], off offset:8
s_or_b32 s7, vcc_lo, s7
s_waitcnt vmcnt(0)
ds_store_b32 v3, v2
v_add_nc_u32_e32 v3, s12, v3
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s6
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_26
v_ashrrev_i32_e32 v2, 31, v1
s_add_i32 s2, s2, -4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v11, s2
v_mov_b32_e32 v10, -1
v_lshlrev_b64 v[8:9], 2, v[1:2]
s_add_u32 s2, s16, 0x70ec
s_addc_u32 s3, s17, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s18, v8
v_add_co_ci_u32_e32 v5, vcc_lo, s19, v9, vcc_lo
v_add_co_u32 v2, vcc_lo, s22, v8
v_add_co_ci_u32_e32 v3, vcc_lo, s23, v9, vcc_lo
v_add_co_u32 v6, vcc_lo, s20, v8
v_add_co_ci_u32_e32 v7, vcc_lo, s21, v9, vcc_lo
global_store_b32 v[4:5], v0, off
global_store_b32 v[2:3], v10, off
global_store_b32 v[6:7], v11, off
global_load_b32 v10, v0, s[16:17]
v_add_co_u32 v8, s2, s2, v8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, s2, s3, v9, s2
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, 1, v10
s_cbranch_vccnz .LBB0_7
global_load_b32 v12, v0, s[16:17] offset:4
s_add_u32 s2, s16, 0x70ec
s_addc_u32 s3, s17, 0
s_mov_b32 s5, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v11, v12, v1
v_mad_u64_u32 v[13:14], null, v12, 3, v[1:2]
v_lshl_add_u32 v15, v12, 1, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v12, 31, v11
v_ashrrev_i32_e32 v16, 31, v15
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[15:16], 2, v[15:16]
v_lshlrev_b64 v[13:14], 2, v[13:14]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v17, vcc_lo, s2, v11
v_add_co_ci_u32_e32 v18, vcc_lo, s3, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v15, vcc_lo, s2, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s3, v16, vcc_lo
v_add_co_u32 v19, vcc_lo, s2, v13
v_add_co_ci_u32_e32 v20, vcc_lo, s3, v14, vcc_lo
s_clause 0x3
global_load_b32 v11, v[8:9], off
global_load_b32 v12, v[17:18], off
global_load_b32 v13, v[15:16], off
global_load_b32 v14, v[19:20], off
.p2align 6
.LBB0_6:
global_load_b32 v17, v0, s[16:17] offset:4
s_waitcnt vmcnt(4)
v_cmp_eq_u32_e32 vcc_lo, s5, v11
s_waitcnt vmcnt(3)
v_cmp_eq_u32_e64 s2, s5, v12
s_waitcnt vmcnt(2)
v_cmp_eq_u32_e64 s3, s5, v13
s_waitcnt vmcnt(1)
v_cmp_eq_u32_e64 s4, s5, v14
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_or_b32 s2, s2, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_or_b32 s2, s2, s4
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[15:16], null, v17, s5, v[1:2]
v_cndmask_b32_e64 v17, s5, -1, s2
s_add_i32 s5, s5, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_ne_u32_e32 vcc_lo, s5, v10
v_ashrrev_i32_e32 v16, 31, v15
s_and_b32 vcc_lo, exec_lo, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[15:16], 2, v[15:16]
v_add_co_u32 v15, s2, s10, v15
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v16, s2, s11, v16, s2
global_store_b32 v[15:16], v17, off
s_cbranch_vccnz .LBB0_6
.LBB0_7:
global_load_b64 v[10:11], v0, s[16:17]
global_load_b32 v14, v[4:5], off
global_load_b32 v17, v[8:9], off
s_add_u32 s2, s16, 0x70ec
s_addc_u32 s3, s17, 0
s_mov_b32 s4, 0
s_waitcnt vmcnt(2)
v_mul_lo_u32 v18, v11, 3
v_add_nc_u32_e32 v8, v11, v1
v_lshl_add_u32 v11, v11, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v9, 31, v8
v_ashrrev_i32_e32 v12, 31, v11
v_add_nc_u32_e32 v13, v18, v1
s_waitcnt vmcnt(1)
v_mad_u64_u32 v[15:16], null, v14, v18, v[1:2]
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_ashrrev_i32_e32 v14, 31, v13
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v16, 31, v15
v_add_co_u32 v8, vcc_lo, s2, v8
s_delay_alu instid0(VALU_DEP_3)
v_lshlrev_b64 v[13:14], 2, v[13:14]
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
v_add_co_u32 v11, vcc_lo, s2, v11
v_lshlrev_b64 v[15:16], 2, v[15:16]
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
v_add_co_u32 v13, vcc_lo, s2, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s3, v14, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v15, vcc_lo, s8, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s9, v16, vcc_lo
s_clause 0x2
global_load_b32 v18, v[8:9], off
global_load_b32 v19, v[11:12], off
global_load_b32 v13, v[13:14], off
s_mov_b32 s3, exec_lo
s_waitcnt vmcnt(3)
global_store_b32 v[15:16], v17, off
global_load_b32 v8, v[4:5], off
global_load_b32 v9, v0, s[16:17] offset:4
s_waitcnt vmcnt(2)
v_lshlrev_b32_e32 v15, 2, v13
s_waitcnt vmcnt(0)
v_mul_lo_u32 v8, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v8, v8, 1, v8
v_add3_u32 v8, v8, v9, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
global_store_b32 v[8:9], v18, off
global_load_b32 v11, v[4:5], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v8, 1, v11
global_store_b32 v[4:5], v8, off
global_load_b32 v14, v0, s[16:17] offset:4
v_mad_u64_u32 v[8:9], null, v11, 3, 2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[11:12], null, v8, v14, v[1:2]
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[11:12]
v_add_co_u32 v8, vcc_lo, s8, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
global_store_b32 v[8:9], v19, off
global_load_b32 v8, v[4:5], off
global_load_b32 v9, v0, s[16:17] offset:4
s_waitcnt vmcnt(0)
v_mul_lo_u32 v11, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[8:9], null, v11, 3, v[1:2]
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_add_co_u32 v8, vcc_lo, s8, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
global_store_b32 v[8:9], v17, off
global_load_b32 v8, v[4:5], off
global_load_b32 v9, v0, s[16:17] offset:4
s_waitcnt vmcnt(0)
v_mul_lo_u32 v8, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v8, v8, 1, v8
v_add3_u32 v8, v8, v9, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
global_store_b32 v[8:9], v18, off
global_load_b32 v11, v[4:5], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v8, 1, v11
global_store_b32 v[4:5], v8, off
global_load_b32 v14, v0, s[16:17] offset:4
v_mad_u64_u32 v[8:9], null, v11, 3, 2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[11:12], null, v8, v14, v[1:2]
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[11:12]
v_add_co_u32 v8, vcc_lo, s8, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
global_store_b32 v[8:9], v13, off
global_load_b32 v8, v[4:5], off
global_load_b32 v9, v0, s[16:17] offset:4
s_waitcnt vmcnt(0)
v_mul_lo_u32 v11, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[8:9], null, v11, 3, v[1:2]
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_add_co_u32 v8, vcc_lo, s8, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
global_store_b32 v[8:9], v17, off
global_load_b32 v8, v[4:5], off
global_load_b32 v9, v0, s[16:17] offset:4
s_waitcnt vmcnt(0)
v_mul_lo_u32 v8, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v8, v8, 1, v8
v_add3_u32 v8, v8, v9, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
global_store_b32 v[8:9], v19, off
global_load_b32 v11, v[4:5], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v8, 1, v11
global_store_b32 v[4:5], v8, off
global_load_b32 v14, v0, s[16:17] offset:4
v_mad_u64_u32 v[8:9], null, v11, 3, 2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[11:12], null, v8, v14, v[1:2]
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[8:9], 2, v[11:12]
v_lshlrev_b32_e32 v12, 2, v19
v_add_co_u32 v8, vcc_lo, s8, v8
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
global_store_b32 v[8:9], v13, off
global_load_b32 v8, v[4:5], off
global_load_b32 v9, v0, s[16:17] offset:4
s_waitcnt vmcnt(0)
v_mul_lo_u32 v11, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[8:9], null, v11, 3, v[1:2]
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_add_co_u32 v8, vcc_lo, s8, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
global_store_b32 v[8:9], v18, off
global_load_b32 v8, v[4:5], off
global_load_b32 v9, v0, s[16:17] offset:4
s_waitcnt vmcnt(0)
v_mul_lo_u32 v8, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v8, v8, 1, v8
v_add3_u32 v8, v8, v9, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
global_store_b32 v[8:9], v19, off
global_load_b32 v11, v[4:5], off
v_mul_lo_u32 v9, v18, v10
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v14, v9, 2, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v8, 1, v11
global_store_b32 v[4:5], v8, off
global_load_b32 v0, v0, s[16:17] offset:4
v_mul_lo_u32 v8, v17, v10
v_mul_lo_u32 v10, v19, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v8, v8, 2, 0
v_lshlrev_b32_e32 v10, 2, v10
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v16, v18, 2, v8
v_add_nc_u32_e32 v17, v8, v12
v_add_nc_u32_e32 v12, v14, v12
v_add_nc_u32_e32 v18, v8, v15
v_mad_u64_u32 v[8:9], null, v11, 3, 2
ds_load_b32 v11, v16
ds_load_b32 v16, v17
v_add_nc_u32_e32 v14, v14, v15
ds_load_b32 v12, v12
ds_load_b32 v17, v18
v_add3_u32 v15, 0, v10, v15
s_waitcnt lgkmcnt(2)
v_add_nc_u32_e32 v11, v16, v11
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[9:10], null, v8, v0, v[1:2]
ds_load_b32 v0, v14
ds_load_b32 v14, v15
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[8:9], 2, v[9:10]
s_waitcnt lgkmcnt(2)
v_add3_u32 v10, v11, v12, v17
v_add_co_u32 v8, vcc_lo, s8, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
s_waitcnt lgkmcnt(0)
v_add3_u32 v0, v10, v0, v14
global_store_b32 v[8:9], v13, off
global_store_b32 v[2:3], v0, off
global_load_b32 v0, v[6:7], off
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e32 0, v0
s_cbranch_execz .LBB0_19
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v12, -1
s_branch .LBB0_10
.LBB0_9:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[10:11], null, v13, v9, v[1:2]
v_lshl_add_u32 v16, v14, 1, v14
v_add_nc_u32_e32 v20, 2, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[8:9], 2, v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s10, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v9, vcc_lo
global_store_b32 v[8:9], v12, off
global_load_b64 v[8:9], v0, s[16:17]
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[10:11], null, v9, v16, v[1:2]
v_mad_u64_u32 v[16:17], null, v9, v20, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v14, v10, v9
v_ashrrev_i32_e32 v11, 31, v10
v_ashrrev_i32_e32 v17, 31, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v15, 31, v14
v_lshlrev_b64 v[10:11], 2, v[10:11]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[16:17], 2, v[16:17]
v_lshlrev_b64 v[14:15], 2, v[14:15]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v10, vcc_lo, s8, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v14, vcc_lo, s8, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s9, v15, vcc_lo
v_add_co_u32 v16, vcc_lo, s8, v16
s_clause 0x1
global_load_b32 v18, v[10:11], off
global_load_b32 v19, v[14:15], off
v_add_co_ci_u32_e32 v17, vcc_lo, s9, v17, vcc_lo
global_load_b32 v20, v[16:17], off
global_store_b32 v[10:11], v13, off
s_waitcnt vmcnt(2)
global_store_b32 v[14:15], v18, off
s_waitcnt vmcnt(1)
global_store_b32 v[16:17], v19, off
global_load_b32 v14, v[4:5], off
v_mul_lo_u32 v16, v9, 3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[10:11], null, v14, v16, v[1:2]
v_ashrrev_i32_e32 v11, 31, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], 2, v[10:11]
v_add_co_u32 v10, vcc_lo, s8, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
global_store_b32 v[10:11], v13, off
global_load_b32 v10, v[4:5], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v10, v16, v10
v_add3_u32 v10, v10, v9, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[10:11], 2, v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, s8, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
global_store_b32 v[10:11], v18, off
global_load_b32 v17, v[4:5], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[10:11], null, v17, 3, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[14:15], null, v10, v9, v[1:2]
v_ashrrev_i32_e32 v15, 31, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[10:11], 2, v[14:15]
v_add_nc_u32_e32 v14, 1, v17
v_add_co_u32 v10, vcc_lo, s8, v10
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
global_store_b32 v[4:5], v14, off
global_store_b32 v[10:11], v20, off
global_load_b32 v14, v[4:5], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[10:11], null, v14, v16, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[10:11], 2, v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, s8, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
global_store_b32 v[10:11], v13, off
global_load_b32 v10, v[4:5], off
v_lshlrev_b32_e32 v13, 2, v13
s_waitcnt vmcnt(0)
v_mul_lo_u32 v10, v16, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v10, v10, v9, v1
v_ashrrev_i32_e32 v11, 31, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], 2, v[10:11]
v_add_co_u32 v10, vcc_lo, s8, v10
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
global_store_b32 v[10:11], v19, off
global_load_b32 v16, v[4:5], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[10:11], null, v16, 3, 2
v_add_nc_u32_e32 v11, 1, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[14:15], null, v10, v9, v[1:2]
v_ashrrev_i32_e32 v15, 31, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 2, v[14:15]
v_add_co_u32 v9, vcc_lo, s8, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v10, vcc_lo
global_store_b32 v[4:5], v11, off
global_store_b32 v[9:10], v20, off
global_load_b32 v9, v[2:3], off
v_mul_lo_u32 v10, v18, v8
v_mul_lo_u32 v11, v19, v8
v_mul_lo_u32 v8, v20, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v10, 2, v10
v_lshlrev_b32_e32 v11, 2, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v8, 2, v8
v_add3_u32 v10, 0, v10, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add3_u32 v11, 0, v11, v13
v_add3_u32 v8, 0, v8, v13
ds_load_b32 v10, v10
ds_load_b32 v11, v11
ds_load_b32 v8, v8
s_waitcnt lgkmcnt(1)
v_add_nc_u32_e32 v10, v11, v10
s_waitcnt vmcnt(0) lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add3_u32 v8, v10, v8, v9
global_store_b32 v[2:3], v8, off
global_load_b32 v8, v[6:7], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v8, -1, v8
v_cmp_eq_u32_e32 vcc_lo, 0, v8
global_store_b32 v[6:7], v8, off
s_or_b32 s4, vcc_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB0_19
.LBB0_10:
global_load_b64 v[8:9], v0, s[16:17]
v_dual_mov_b32 v13, -1 :: v_dual_mov_b32 v14, -1
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, 1, v8
s_cbranch_vccnz .LBB0_9
v_mul_lo_u32 v16, v9, 3
v_dual_mov_b32 v14, -1 :: v_dual_lshlrev_b32 v15, 1, v9
v_mov_b32_e32 v17, -1
v_mov_b32_e32 v13, -1
s_mov_b32 s5, 0
s_branch .LBB0_14
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s7
.LBB0_13:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s6
s_add_i32 s5, s5, 1
v_cmp_ne_u32_e32 vcc_lo, s5, v8
s_cbranch_vccz .LBB0_9
.LBB0_14:
v_mad_u64_u32 v[10:11], null, s5, v9, v[1:2]
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[10:11], 2, v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, s10, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s11, v11, vcc_lo
global_load_b32 v10, v[10:11], off
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e32 -1, v10
s_cbranch_execz .LBB0_13
global_load_b32 v18, v[4:5], off
s_mov_b32 s7, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e32 0, v18
s_cbranch_execz .LBB0_12
v_mov_b32_e32 v10, v1
s_lshl_b32 s2, s5, 2
s_mov_b32 s12, 0
s_add_i32 s13, s2, 0
s_mov_b32 s14, 0
.LBB0_17:
v_add_nc_u32_e32 v19, v9, v10
v_ashrrev_i32_e32 v11, 31, v10
v_add_nc_u32_e32 v21, v15, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v20, 31, v19
v_lshlrev_b64 v[23:24], 2, v[10:11]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v22, 31, v21
v_add_nc_u32_e32 v10, v10, v16
v_lshlrev_b64 v[19:20], 2, v[19:20]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[21:22], 2, v[21:22]
v_add_co_u32 v23, vcc_lo, s8, v23
v_add_co_ci_u32_e32 v24, vcc_lo, s9, v24, vcc_lo
v_add_co_u32 v19, vcc_lo, s8, v19
v_add_co_ci_u32_e32 v20, vcc_lo, s9, v20, vcc_lo
v_add_co_u32 v21, vcc_lo, s8, v21
v_add_co_ci_u32_e32 v22, vcc_lo, s9, v22, vcc_lo
s_clause 0x2
global_load_b32 v11, v[23:24], off
global_load_b32 v19, v[19:20], off
global_load_b32 v20, v[21:22], off
s_waitcnt vmcnt(2)
v_mul_lo_u32 v11, v11, v8
s_waitcnt vmcnt(1)
v_mul_lo_u32 v19, v19, v8
s_waitcnt vmcnt(0)
v_mul_lo_u32 v20, v20, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshl_add_u32 v11, v11, 2, s13
v_lshl_add_u32 v19, v19, 2, s13
s_delay_alu instid0(VALU_DEP_3)
v_lshl_add_u32 v20, v20, 2, s13
ds_load_b32 v11, v11
ds_load_b32 v19, v19
ds_load_b32 v20, v20
s_waitcnt lgkmcnt(0)
v_add3_u32 v11, v19, v11, v20
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, v11, v17
v_max_i32_e32 v17, v11, v17
v_cndmask_b32_e64 v14, v14, s14, vcc_lo
s_add_i32 s14, s14, 1
v_cndmask_b32_e64 v13, v13, s5, vcc_lo
v_cmp_eq_u32_e64 s2, s14, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s12, s2, s12
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execnz .LBB0_17
s_or_b32 exec_lo, exec_lo, s12
s_branch .LBB0_12
.LBB0_19:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_load_b32 v0, v[2:3], off
s_mov_b32 s2, exec_lo
s_brev_b32 s4, 1
.LBB0_20:
s_ctz_i32_b32 s3, s2
s_waitcnt vmcnt(0)
v_readlane_b32 s5, v0, s3
s_lshl_b32 s3, 1, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_not1_b32 s2, s2, s3
s_max_i32 s4, s4, s5
s_cmp_lg_u32 s2, 0
s_cbranch_scc1 .LBB0_20
s_load_b64 s[2:3], s[0:1], 0x30
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s5, exec_lo, s5
s_cbranch_execz .LBB0_23
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v4, s4
s_waitcnt lgkmcnt(0)
global_atomic_max_i32 v0, v4, s[2:3]
.LBB0_23:
s_or_b32 exec_lo, exec_lo, s5
v_mov_b32_e32 v0, 0
global_load_b32 v2, v[2:3], off
s_waitcnt lgkmcnt(0)
global_load_b32 v3, v0, s[2:3]
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v2, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_25
s_load_b64 s[0:1], s[0:1], 0x38
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB0_25:
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB0_26:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12tmfgParallelP4Node6ParamsPiS2_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 25
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12tmfgParallelP4Node6ParamsPiS2_, .Lfunc_end0-_Z12tmfgParallelP4Node6ParamsPiS2_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 40
.value_kind: by_value
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
- .offset: 184
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12tmfgParallelP4Node6ParamsPiS2_
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z12tmfgParallelP4Node6ParamsPiS2_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 25
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <algorithm>
#include <cmath>
#include <cstdio>
#include <cstdlib>
#include <iomanip>
#include <iostream>
#include <vector>
#define C 4
#define THREADS 1024 // 2^10
#define MAX 85
#define MAX_S MAX* MAX
#define PERM_MAX (MAX * (MAX - 1) * (MAX - 2) * (MAX - 3)) / 24
#define pb push_back
#define mp make_pair
#define gpuErrChk(ans) \
{ \
gpuAssert((ans), __FILE__, __LINE__); \
}
inline void gpuAssert(hipError_t code, char* file, int line, bool abort = true)
{
if (code != hipSuccess) {
fprintf(stderr, "GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort)
getchar();
}
}
using namespace std;
typedef long long int64;
typedef pair<int, int> ii;
/*
sz ---> Adjacency matrix dimension (1D)
perm ---> Number of permutations of an instance
graph ---> Adjacency matrix itself
seeds ---> Set of seeds
faces ---> Set of triangular faces for the output
*/
struct Node {
int sz, perm;
int graph[MAX_S], seeds[C * PERM_MAX], F_ANS[6 * MAX];
};
/*
faces ---> Number of triangular faces
count ---> Number of remaining vertices
tmpMax ---> Max value obtained for a seed
F ---> Set of triangular faces
F ---> Set of remaining vertices
*/
struct Params {
int *faces, *count, *tmpMax;
int *F, *V;
};
/*
SIZE ---> Number of vertices
BLOCKS ---> Number of blocks
PERM ---> Number of permutations
R ---> Output graph for a possible solution
F ---> Set of triangular faces of an instance
qtd ---> Number of possible 4-cliques
*/
clock_t start, stop;
int SIZE, BLOCKS, PERM, qtd = 0;
int R[MAX_S], F[8 * MAX], bib[MAX];
Node* N;
__device__ void initializeDevice(Params* devP, int sz, int t)
{
devP->faces[t] = 0;
devP->tmpMax[t] = -1;
devP->count[t] = sz - 4;
}
/*
Generates a list containing the vertices which are not on the planar graph
*/
__device__ void generateList(Node* devN, Params* devP, int t)
{
int sz = devN->sz;
int va = devN->seeds[t], vb = devN->seeds[t + devN->perm], vc = devN->seeds[t + 2 * devN->perm], vd = devN->seeds[t + 3 * devN->perm];
for (int i = 0; i < sz; i++) {
if (i == va || i == vb || i == vc || i == vd)
devP->V[t + i * devN->perm] = -1;
else
devP->V[t + i * devN->perm] = i;
}
}
/*
Returns the weight of the planar graph so far
*/
__device__ void generateTriangularFaceList(Node* devN, Params* devP, int graph[], int t)
{
int sz = devN->sz;
int va = devN->seeds[t];
int vb = devN->seeds[t + devN->perm];
int vc = devN->seeds[t + 2 * devN->perm];
int vd = devN->seeds[t + 3 * devN->perm];
//generate first triangle of the output graph
devP->F[t + (devP->faces[t] * 3) * devN->perm] = va;
devP->F[t + (devP->faces[t] * 3 + 1) * devN->perm] = vb;
devP->F[t + ((devP->faces[t]++) * 3 + 2) * devN->perm] = vc;
int resp = graph[va * sz + vb] + graph[va * sz + vc] + graph[vb * sz + vc];
//generate the next 3 possible faces
devP->F[t + (devP->faces[t] * 3) * devN->perm] = va;
devP->F[t + (devP->faces[t] * 3 + 1) * devN->perm] = vb;
devP->F[t + ((devP->faces[t]++) * 3 + 2) * devN->perm] = vd;
devP->F[t + (devP->faces[t] * 3) * devN->perm] = va;
devP->F[t + (devP->faces[t] * 3 + 1) * devN->perm] = vc;
devP->F[t + ((devP->faces[t]++) * 3 + 2) * devN->perm] = vd;
devP->F[t + (devP->faces[t] * 3) * devN->perm] = vb;
devP->F[t + (devP->faces[t] * 3 + 1) * devN->perm] = vc;
devP->F[t + ((devP->faces[t]++) * 3 + 2) * devN->perm] = vd;
resp += graph[va * sz + vd] + graph[vb * sz + vd] + graph[vc * sz + vd];
devP->tmpMax[t] = resp;
}
/*
Insert a new vertex, 3 new triangular faces and removes face 'f' from the set
*/
__device__ int operationT2(Node* devN, Params* devP, int graph[], int new_vertex, int f, int t)
{
int sz = devN->sz, perm = devN->perm;
//remove the chosen face and insert a new one
int va = devP->F[t + (f * 3) * perm];
int vb = devP->F[t + (f * 3 + 1) * perm];
int vc = devP->F[t + (f * 3 + 2) * perm];
devP->F[t + (f * 3) * perm] = new_vertex;
devP->F[t + (f * 3 + 1) * perm] = va;
devP->F[t + (f * 3 + 2) * perm] = vb;
//and insert the other two possible faces
devP->F[t + (devP->faces[t] * 3) * perm] = new_vertex;
devP->F[t + (devP->faces[t] * 3 + 1) * perm] = va;
devP->F[t + ((devP->faces[t]++) * 3 + 2) * perm] = vc;
devP->F[t + (devP->faces[t] * 3) * perm] = new_vertex;
devP->F[t + (devP->faces[t] * 3 + 1) * perm] = vb;
devP->F[t + ((devP->faces[t]++) * 3 + 2) * perm] = vc;
int resp = graph[va * sz + new_vertex] + graph[vb * sz + new_vertex] + graph[vc * sz + new_vertex];
return resp;
}
/*
Return the vertex with the maximum gain inserting within a face 'f'
*/
__device__ int maxGain(Node* devN, Params* devP, int graph[], int* f, int t)
{
int sz = devN->sz, perm = devN->perm;
int gain = -1, vertex = -1;
//iterate through the remaining vertices
for (int new_vertex = 0; new_vertex < sz; new_vertex++) {
if (devP->V[t + new_vertex * perm] == -1)
continue;
//and test which has the maximum gain with its insetion
//within all possible faces
int faces = devP->faces[t];
for (int i = 0; i < faces; i++) {
int va = devP->F[t + (i * 3) * perm], vb = devP->F[t + (i * 3 + 1) * perm], vc = devP->F[t + (i * 3 + 2) * perm];
int tmpGain = graph[va * sz + new_vertex] + graph[vb * sz + new_vertex] + graph[vc * sz + new_vertex];
if (tmpGain > gain) {
gain = tmpGain;
*f = i;
vertex = new_vertex;
}
}
}
return vertex;
}
__device__ void tmfg(Node* devN, Params* devP, int graph[], int t)
{
while (devP->count[t]) {
int f = -1;
int vertex = maxGain(devN, devP, graph, &f, t);
devP->V[t + vertex * devN->perm] = -1;
devP->tmpMax[t] += operationT2(devN, devP, graph, vertex, f, t);
devP->count[t]--;
}
}
__global__ void tmfgParallel(Node* devN, Params devP, int* respMax, int* idx)
{
int x = blockDim.x * blockIdx.x + threadIdx.x;
int sz = devN->sz, perm = devN->perm;
extern __shared__ int graph[];
for (int i = threadIdx.x; i < sz * sz; i += blockDim.x) {
graph[i] = devN->graph[i];
graph[i] = devN->graph[i];
}
__syncthreads();
if (x < perm) {
initializeDevice(&devP, sz, x);
generateList(devN, &devP, x);
generateTriangularFaceList(devN, &devP, graph, x);
tmfg(devN, &devP, graph, x);
__syncthreads();
atomicMax(respMax, devP.tmpMax[x]);
if (devP.tmpMax[x] == *respMax)
*idx = x;
__syncthreads();
}
}
int tmfgPrepare()
{
int resp = 0, idx = 0, *tmpResp, *tmpIdx;
gpuErrChk(hipMalloc((void**)&tmpResp, sizeof(int)));
gpuErrChk(hipMalloc((void**)&tmpIdx, sizeof(int)));
gpuErrChk(hipMemcpy(tmpResp, &resp, sizeof(int), hipMemcpyHostToDevice));
gpuErrChk(hipMemcpy(tmpIdx, &idx, sizeof(int), hipMemcpyHostToDevice));
Node* devN;
Params devP;
cout << "Amount of memory: " << (3 * PERM + PERM * SIZE + 6 * SIZE * PERM * sizeof(int)) / 1000000 << "MB" << endl;
gpuErrChk(hipMalloc((void**)&devN, sizeof(Node)));
gpuErrChk(hipMemcpy(devN, N, sizeof(Node), hipMemcpyHostToDevice));
cout << "1 done." << endl;
gpuErrChk(hipMalloc((void**)&devP.faces, PERM * sizeof(int)));
gpuErrChk(hipMalloc((void**)&devP.count, PERM * sizeof(int)));
gpuErrChk(hipMalloc((void**)&devP.tmpMax, PERM * sizeof(int)));
gpuErrChk(hipMalloc((void**)&devP.F, PERM * 6 * SIZE * sizeof(int)));
gpuErrChk(hipMalloc((void**)&devP.V, PERM * SIZE * sizeof(int)));
cout << "2 done." << endl;
dim3 blocks(BLOCKS, 1);
dim3 threads(THREADS, 1);
cout << "Launching kernel..." << endl;
tmfgParallel<<<blocks, threads, SIZE * SIZE * sizeof(int)>>>(devN, devP, tmpResp, tmpIdx);
gpuErrChk(hipDeviceSynchronize());
cout << "Kernel finished." << endl;
//copy back the maximum weight and the index of the graph
//which gave this result
gpuErrChk(hipMemcpy(&resp, tmpResp, sizeof(int), hipMemcpyDeviceToHost));
cout << "1 done." << endl;
gpuErrChk(hipMemcpy(&idx, tmpIdx, sizeof(int), hipMemcpyDeviceToHost));
cout << "2 done." << endl;
//gpuErrChk(cudaMemcpy(&F, devP.F[idx + ], (6*MAX)*sizeof(int), cudaMemcpyDeviceToHost));
cout << "3 done." << endl;
gpuErrChk(hipFree(devN));
gpuErrChk(hipFree(devP.faces));
gpuErrChk(hipFree(devP.count));
gpuErrChk(hipFree(devP.tmpMax));
gpuErrChk(hipFree(devP.F));
gpuErrChk(hipFree(devP.V));
cout << "Completed." << endl;
return resp;
}
void printElapsedTime(clock_t start, clock_t stop)
{
double elapsed = ((double)(stop - start)) / CLOCKS_PER_SEC;
cout << fixed << setprecision(3) << "Elapsed time: " << elapsed << "s\n";
}
/*
C ---> Size of the combination
index ---> Current index in data[]
data[] ---> Temporary array to store a current combination
i ---> Index of current element in vertices[]
*/
void combineUntil(int index, vector<int>& data, int i)
{
// Current cobination is ready, print it
if (index == C) {
for (int j = 0; j < C; j++) {
N->seeds[qtd + j * PERM] = data[j];
}
qtd++;
return;
}
// When there are no more elements to put in data[]
if (i >= SIZE)
return;
//current is inserted; put next at a next location
data[index] = i;
combineUntil(index + 1, data, i + 1);
//current is deleted; replace it with next
combineUntil(index, data, i + 1);
}
/*
Print all combinations of size 'C' using a temporary array 'data'
*/
void combine()
{
vector<int> data(C);
combineUntil(0, data, 0);
}
void initialize()
{
for (int i = 0; i < SIZE; i++) {
for (int j = i + 1; j < SIZE; j++) {
R[i * SIZE + j] = R[j * SIZE + i] = -1;
}
}
}
void readInput()
{
int x;
cin >> SIZE;
PERM = bib[SIZE - 1];
BLOCKS = PERM / THREADS + 1;
N = (Node*)malloc(sizeof(Node));
N->sz = SIZE;
N->perm = PERM;
for (int i = 0; i < SIZE; i++) {
for (int j = i + 1; j < SIZE; j++) {
cin >> x;
N->graph[i * SIZE + j] = x;
N->graph[j * SIZE + i] = x;
}
}
}
/*
Define the number of permutations and blocks
*/
void sizeDefinitions()
{
for (int i = 6; i <= MAX; i++) {
int resp = 1;
for (int j = i - 3; j <= i; j++)
resp *= j;
resp /= 24;
bib[i - 1] = resp;
}
}
int main(int argv, char** argc)
{
ios::sync_with_stdio(false);
sizeDefinitions();
//read the input, which is given by a size of a graph and its weighted edges.
//the graph given is dense.
readInput();
initialize();
//generate multiple 4-clique seeds, given the number of vertices
combine();
hipSetDevice(3);
start = clock();
int respMax = tmfgPrepare();
stop = clock();
//reconstruct the graph given the regions of the graph
// for ( int i = 0; i < 2*SIZE; i++ ){
// int va = F[i*3], vb = F[i*3 + 1], vc = F[i*3 + 2];
// if ( va == vb && vb == vc ) continue;
// R[va*SIZE + vb] = R[vb*SIZE + va] = N->graph[va*SIZE + vb];
// R[va*SIZE + vc] = R[vc*SIZE + va] = N->graph[va*SIZE + vc];
// R[vb*SIZE + vc] = R[vc*SIZE + vb] = N->graph[vb*SIZE + vc];
// }
// cout << "Printing generated graph: " << endl;
// for ( int i = 0; i < SIZE; i++ ){
// for ( int j = i+1; j < SIZE; j++ ){
// cout << R[i*SIZE + j] << " ";
// }
// cout << endl;
// }
printElapsedTime(start, stop);
cout << "Maximum weight found: " << respMax << endl;
free(N);
gpuErrChk(hipDeviceReset());
return 0;
} | .text
.file "3-tmfg-agsh.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__tmfgParallelP4Node6ParamsPiS2_ # -- Begin function _Z27__device_stub__tmfgParallelP4Node6ParamsPiS2_
.p2align 4, 0x90
.type _Z27__device_stub__tmfgParallelP4Node6ParamsPiS2_,@function
_Z27__device_stub__tmfgParallelP4Node6ParamsPiS2_: # @_Z27__device_stub__tmfgParallelP4Node6ParamsPiS2_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 128(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12tmfgParallelP4Node6ParamsPiS2_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__tmfgParallelP4Node6ParamsPiS2_, .Lfunc_end0-_Z27__device_stub__tmfgParallelP4Node6ParamsPiS2_
.cfi_endproc
# -- End function
.globl _Z11tmfgPreparev # -- Begin function _Z11tmfgPreparev
.p2align 4, 0x90
.type _Z11tmfgPreparev,@function
_Z11tmfgPreparev: # @_Z11tmfgPreparev
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $224, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $0, (%rsp)
movl $0, 4(%rsp)
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
.LBB1_2: # %_Z9gpuAssert10hipError_tPcib.exit
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_3
.LBB1_4: # %_Z9gpuAssert10hipError_tPcib.exit8
movq 24(%rsp), %rdi
movq %rsp, %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_5
.LBB1_6: # %_Z9gpuAssert10hipError_tPcib.exit10
movq 16(%rsp), %rdi
leaq 4(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_7
.LBB1_8: # %_Z9gpuAssert10hipError_tPcib.exit12
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl PERM(%rip), %eax
movl SIZE(%rip), %ecx
leal 3(%rcx), %edx
imull %eax, %edx
movslq %edx, %rdx
imull %ecx, %eax
addl %eax, %eax
leal (%rax,%rax,2), %eax
cltq
leaq (%rdx,%rax,4), %rax
movabsq $4835703278458516699, %rcx # imm = 0x431BDE82D7B634DB
mulq %rcx
shrq $18, %rdx
movl $_ZSt4cout, %edi
movq %rdx, %rsi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %rbx
movl $.L.str.2, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB1_79
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_11
# %bb.10:
movzbl 67(%r14), %eax
jmp .LBB1_12
.LBB1_11:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 8(%rsp), %rdi
movl $32427508, %esi # imm = 0x1EECDF4
callq hipMalloc
testl %eax, %eax
jne .LBB1_13
.LBB1_14: # %_Z9gpuAssert10hipError_tPcib.exit14
movq 8(%rsp), %rdi
movq N(%rip), %rsi
movl $32427508, %edx # imm = 0x1EECDF4
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_15
.LBB1_16: # %_Z9gpuAssert10hipError_tPcib.exit16
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_79
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i46
cmpb $0, 56(%rbx)
je .LBB1_19
# %bb.18:
movzbl 67(%rbx), %eax
jmp .LBB1_20
.LBB1_19:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit49
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movslq PERM(%rip), %rsi
shlq $2, %rsi
leaq 32(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
jne .LBB1_21
.LBB1_22: # %_Z9gpuAssert10hipError_tPcib.exit18
leaq 40(%rsp), %rdi
movslq PERM(%rip), %rsi
shlq $2, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_23
.LBB1_24: # %_Z9gpuAssert10hipError_tPcib.exit20
leaq 48(%rsp), %rdi
movslq PERM(%rip), %rsi
shlq $2, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_25
.LBB1_26: # %_Z9gpuAssert10hipError_tPcib.exit22
leaq 56(%rsp), %rdi
movslq PERM(%rip), %rax
movslq SIZE(%rip), %rcx
imulq %rax, %rcx
shlq $3, %rcx
leaq (%rcx,%rcx,2), %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_27
.LBB1_28: # %_Z9gpuAssert10hipError_tPcib.exit24
leaq 64(%rsp), %rdi
movslq PERM(%rip), %rax
movslq SIZE(%rip), %rsi
imulq %rax, %rsi
shlq $2, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_29
.LBB1_30: # %_Z9gpuAssert10hipError_tPcib.exit26
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_79
# %bb.31: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i51
cmpb $0, 56(%rbx)
je .LBB1_33
# %bb.32:
movzbl 67(%rbx), %eax
jmp .LBB1_34
.LBB1_33:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_34: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit54
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl BLOCKS(%rip), %ebx
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB1_79
# %bb.35: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i56
movabsq $4294967296, %r14 # imm = 0x100000000
orq %r14, %rbx
cmpb $0, 56(%r15)
je .LBB1_37
# %bb.36:
movzbl 67(%r15), %eax
jmp .LBB1_38
.LBB1_37:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_38: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit59
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl SIZE(%rip), %r8d
imull %r8d, %r8d
shlq $2, %r8
addq $1024, %r14 # imm = 0x400
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_40
# %bb.39:
movq 8(%rsp), %rax
movq 64(%rsp), %rcx
movq %rcx, 208(%rsp)
movups 32(%rsp), %xmm0
movups 48(%rsp), %xmm1
movaps %xmm1, 192(%rsp)
movaps %xmm0, 176(%rsp)
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 176(%rsp), %rax
movq %rax, 152(%rsp)
leaq 128(%rsp), %rax
movq %rax, 160(%rsp)
leaq 120(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z12tmfgParallelP4Node6ParamsPiS2_, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_40:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_41
.LBB1_42: # %_Z9gpuAssert10hipError_tPcib.exit28
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_79
# %bb.43: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i61
cmpb $0, 56(%rbx)
je .LBB1_45
# %bb.44:
movzbl 67(%rbx), %eax
jmp .LBB1_46
.LBB1_45:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_46: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit64
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 24(%rsp), %rsi
movq %rsp, %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_47
.LBB1_48: # %_Z9gpuAssert10hipError_tPcib.exit30
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_79
# %bb.49: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i66
cmpb $0, 56(%rbx)
je .LBB1_51
# %bb.50:
movzbl 67(%rbx), %eax
jmp .LBB1_52
.LBB1_51:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_52: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit69
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rsi
leaq 4(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_53
.LBB1_54: # %_Z9gpuAssert10hipError_tPcib.exit32
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_79
# %bb.55: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i71
cmpb $0, 56(%rbx)
je .LBB1_57
# %bb.56:
movzbl 67(%rbx), %eax
jmp .LBB1_58
.LBB1_57:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_58: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit74
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_79
# %bb.59: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i76
cmpb $0, 56(%rbx)
je .LBB1_61
# %bb.60:
movzbl 67(%rbx), %eax
jmp .LBB1_62
.LBB1_61:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_62: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit79
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_63
.LBB1_64: # %_Z9gpuAssert10hipError_tPcib.exit34
movq 32(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_65
.LBB1_66: # %_Z9gpuAssert10hipError_tPcib.exit36
movq 40(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_67
.LBB1_68: # %_Z9gpuAssert10hipError_tPcib.exit38
movq 48(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_69
.LBB1_70: # %_Z9gpuAssert10hipError_tPcib.exit40
movq 56(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_71
.LBB1_72: # %_Z9gpuAssert10hipError_tPcib.exit42
movq 64(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_73
.LBB1_74: # %_Z9gpuAssert10hipError_tPcib.exit44
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_79
# %bb.75: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i81
cmpb $0, 56(%rbx)
je .LBB1_77
# %bb.76:
movzbl 67(%rbx), %eax
jmp .LBB1_78
.LBB1_77:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_78: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit84
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl (%rsp), %eax
addq $224, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 256
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $226, %r8d
xorl %eax, %eax
callq fprintf
movq stdin(%rip), %rdi
callq getc
jmp .LBB1_2
.LBB1_3:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $227, %r8d
xorl %eax, %eax
callq fprintf
movq stdin(%rip), %rdi
callq getc
jmp .LBB1_4
.LBB1_5:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $228, %r8d
xorl %eax, %eax
callq fprintf
movq stdin(%rip), %rdi
callq getc
jmp .LBB1_6
.LBB1_7:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $229, %r8d
xorl %eax, %eax
callq fprintf
movq stdin(%rip), %rdi
callq getc
jmp .LBB1_8
.LBB1_13:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $236, %r8d
xorl %eax, %eax
callq fprintf
movq stdin(%rip), %rdi
callq getc
jmp .LBB1_14
.LBB1_15:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $237, %r8d
xorl %eax, %eax
callq fprintf
movq stdin(%rip), %rdi
callq getc
jmp .LBB1_16
.LBB1_21:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $240, %r8d
xorl %eax, %eax
callq fprintf
movq stdin(%rip), %rdi
callq getc
jmp .LBB1_22
.LBB1_23:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $241, %r8d
xorl %eax, %eax
callq fprintf
movq stdin(%rip), %rdi
callq getc
jmp .LBB1_24
.LBB1_25:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $242, %r8d
xorl %eax, %eax
callq fprintf
movq stdin(%rip), %rdi
callq getc
jmp .LBB1_26
.LBB1_27:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $243, %r8d
xorl %eax, %eax
callq fprintf
movq stdin(%rip), %rdi
callq getc
jmp .LBB1_28
.LBB1_29:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $244, %r8d
xorl %eax, %eax
callq fprintf
movq stdin(%rip), %rdi
callq getc
jmp .LBB1_30
.LBB1_41:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $252, %r8d
xorl %eax, %eax
callq fprintf
movq stdin(%rip), %rdi
callq getc
jmp .LBB1_42
.LBB1_47:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $257, %r8d # imm = 0x101
xorl %eax, %eax
callq fprintf
movq stdin(%rip), %rdi
callq getc
jmp .LBB1_48
.LBB1_53:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $259, %r8d # imm = 0x103
xorl %eax, %eax
callq fprintf
movq stdin(%rip), %rdi
callq getc
jmp .LBB1_54
.LBB1_63:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $264, %r8d # imm = 0x108
xorl %eax, %eax
callq fprintf
movq stdin(%rip), %rdi
callq getc
jmp .LBB1_64
.LBB1_65:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $265, %r8d # imm = 0x109
xorl %eax, %eax
callq fprintf
movq stdin(%rip), %rdi
callq getc
jmp .LBB1_66
.LBB1_67:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $266, %r8d # imm = 0x10A
xorl %eax, %eax
callq fprintf
movq stdin(%rip), %rdi
callq getc
jmp .LBB1_68
.LBB1_69:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $267, %r8d # imm = 0x10B
xorl %eax, %eax
callq fprintf
movq stdin(%rip), %rdi
callq getc
jmp .LBB1_70
.LBB1_71:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $268, %r8d # imm = 0x10C
xorl %eax, %eax
callq fprintf
movq stdin(%rip), %rdi
callq getc
jmp .LBB1_72
.LBB1_73:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $269, %r8d # imm = 0x10D
xorl %eax, %eax
callq fprintf
movq stdin(%rip), %rdi
callq getc
jmp .LBB1_74
.LBB1_79:
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z11tmfgPreparev, .Lfunc_end1-_Z11tmfgPreparev
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z16printElapsedTimell
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z16printElapsedTimell
.p2align 4, 0x90
.type _Z16printElapsedTimell,@function
_Z16printElapsedTimell: # @_Z16printElapsedTimell
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
subq %rdi, %rsi
cvtsi2sd %rsi, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rcx
movl $-261, %edx # imm = 0xFEFB
andl _ZSt4cout+24(%rcx), %edx
orl $4, %edx
movl %edx, _ZSt4cout+24(%rcx)
movq -24(%rax), %rax
movq $3, _ZSt4cout+8(%rax)
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.10, %esi
movl $2, %edx
movq %rax, %rdi
popq %rax
.cfi_def_cfa_offset 8
jmp _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l # TAILCALL
.Lfunc_end2:
.size _Z16printElapsedTimell, .Lfunc_end2-_Z16printElapsedTimell
.cfi_endproc
# -- End function
.globl _Z12combineUntiliRSt6vectorIiSaIiEEi # -- Begin function _Z12combineUntiliRSt6vectorIiSaIiEEi
.p2align 4, 0x90
.type _Z12combineUntiliRSt6vectorIiSaIiEEi,@function
_Z12combineUntiliRSt6vectorIiSaIiEEi: # @_Z12combineUntiliRSt6vectorIiSaIiEEi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movq %rsi, %rbx
movl %edi, %r14d
movslq %edi, %r12
leal 1(%r14), %r15d
cmpl $4, %r14d
je .LBB3_2
.p2align 4, 0x90
.LBB3_6: # =>This Inner Loop Header: Depth=1
cmpl %ebp, SIZE(%rip)
jle .LBB3_5
# %bb.7: # in Loop: Header=BB3_6 Depth=1
movq (%rbx), %rax
movl %ebp, (%rax,%r12,4)
incl %ebp
movl %r15d, %edi
movq %rbx, %rsi
movl %ebp, %edx
callq _Z12combineUntiliRSt6vectorIiSaIiEEi
cmpl $4, %r14d
jne .LBB3_6
.LBB3_2: # %.preheader
movq (%rbx), %rax
movq N(%rip), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_3: # =>This Inner Loop Header: Depth=1
movl (%rax,%rdx,4), %esi
movslq qtd(%rip), %rdi
movslq PERM(%rip), %r8
movslq %edx, %r9
imulq %r8, %r9
addq %rdi, %r9
movl %esi, 28908(%rcx,%r9,4)
incq %rdx
cmpq $4, %rdx
jne .LBB3_3
# %bb.4:
incl qtd(%rip)
.LBB3_5:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z12combineUntiliRSt6vectorIiSaIiEEi, .Lfunc_end3-_Z12combineUntiliRSt6vectorIiSaIiEEi
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z7combinev
.LCPI4_0:
.zero 16
.text
.globl _Z7combinev
.p2align 4, 0x90
.type _Z7combinev,@function
_Z7combinev: # @_Z7combinev
.cfi_startproc
# %bb.0: # %_ZNSt6vectorIiSaIiEEC2EmRKS0_.exit
subq $24, %rsp
.cfi_def_cfa_offset 32
xorps %xmm0, %xmm0
movaps %xmm0, (%rsp)
movq $0, 16(%rsp)
movl $16, %edi
callq _Znwm
movq %rax, (%rsp)
movq %rax, 8(%rsp)
leaq 16(%rax), %rcx
movq %rcx, 16(%rsp)
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movq %rcx, 8(%rsp)
movq %rsp, %rsi
xorl %edi, %edi
xorl %edx, %edx
callq _Z12combineUntiliRSt6vectorIiSaIiEEi
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
callq _ZdlPv
.LBB4_2: # %_ZNSt6vectorIiSaIiEED2Ev.exit
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z7combinev, .Lfunc_end4-_Z7combinev
.cfi_endproc
# -- End function
.globl _Z10initializev # -- Begin function _Z10initializev
.p2align 4, 0x90
.type _Z10initializev,@function
_Z10initializev: # @_Z10initializev
.cfi_startproc
# %bb.0:
movl SIZE(%rip), %eax
testl %eax, %eax
jle .LBB5_7
# %bb.1: # %.lr.ph13.preheader
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq (,%rax,4), %rcx
leaq R(,%rax,4), %rdx
leaq 4(,%rax,4), %rsi
leaq -1(%rax), %rdi
movl $R+4, %r8d
xorl %r9d, %r9d
xorl %r10d, %r10d
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_5: # %.loopexit
# in Loop: Header=BB5_2 Depth=1
addq $4, %r8
addl %eax, %r9d
addq %rsi, %rdx
decq %rdi
cmpq %rax, %r10
je .LBB5_6
.LBB5_2: # %.lr.ph13
# =>This Loop Header: Depth=1
# Child Loop BB5_4 Depth 2
incq %r10
cmpq %rax, %r10
jae .LBB5_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB5_2 Depth=1
movl %r9d, %r11d
leaq (%r8,%r11,4), %r11
movq %rdx, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB5_4: # Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $-1, (%rbx)
movl $-1, (%r11,%r14,4)
incq %r14
addq %rcx, %rbx
cmpq %r14, %rdi
jne .LBB5_4
jmp .LBB5_5
.LBB5_6:
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.LBB5_7: # %._crit_edge
retq
.Lfunc_end5:
.size _Z10initializev, .Lfunc_end5-_Z10initializev
.cfi_endproc
# -- End function
.globl _Z9readInputv # -- Begin function _Z9readInputv
.p2align 4, 0x90
.type _Z9readInputv,@function
_Z9readInputv: # @_Z9readInputv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $_ZSt3cin, %edi
movl $SIZE, %esi
callq _ZNSirsERi
movslq SIZE(%rip), %rbx
movl bib-4(,%rbx,4), %r14d
leal 1023(%r14), %eax
testl %r14d, %r14d
cmovnsl %r14d, %eax
movl %r14d, PERM(%rip)
sarl $10, %eax
incl %eax
movl %eax, BLOCKS(%rip)
movl $32427508, %edi # imm = 0x1EECDF4
callq malloc
movq %rax, N(%rip)
movl %ebx, (%rax)
movl %r14d, 4(%rax)
cmpl $0, SIZE(%rip)
jle .LBB6_6
# %bb.1: # %.lr.ph12.preheader
xorl %ebp, %ebp
movl $1, %r14d
leaq 4(%rsp), %rbx
jmp .LBB6_3
.p2align 4, 0x90
.LBB6_2: # %.loopexit
# in Loop: Header=BB6_3 Depth=1
incq %r14
cmpl SIZE(%rip), %ebp
jge .LBB6_6
.LBB6_3: # %.lr.ph12
# =>This Loop Header: Depth=1
# Child Loop BB6_5 Depth 2
movl %ebp, %r15d
leal 1(%r15), %ebp
cmpl SIZE(%rip), %ebp
jge .LBB6_2
# %bb.4: # %.lr.ph.preheader
# in Loop: Header=BB6_3 Depth=1
movslq %r15d, %r12
movq %r14, %r13
.p2align 4, 0x90
.LBB6_5: # %.lr.ph
# Parent Loop BB6_3 Depth=1
# => This Inner Loop Header: Depth=2
movl $_ZSt3cin, %edi
movq %rbx, %rsi
callq _ZNSirsERi
movl 4(%rsp), %eax
movq N(%rip), %rcx
movslq SIZE(%rip), %rdx
imulq %r12, %rdx
addq %r13, %rdx
movl %eax, 8(%rcx,%rdx,4)
movl 4(%rsp), %eax
movl SIZE(%rip), %edx
imull %r13d, %edx
addl %r15d, %edx
movslq %edx, %rdx
movl %eax, 8(%rcx,%rdx,4)
incq %r13
cmpl SIZE(%rip), %r13d
jl .LBB6_5
jmp .LBB6_2
.LBB6_6: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z9readInputv, .Lfunc_end6-_Z9readInputv
.cfi_endproc
# -- End function
.globl _Z15sizeDefinitionsv # -- Begin function _Z15sizeDefinitionsv
.p2align 4, 0x90
.type _Z15sizeDefinitionsv,@function
_Z15sizeDefinitionsv: # @_Z15sizeDefinitionsv
.cfi_startproc
# %bb.0:
movl $6, %eax
movl $3, %ecx
.p2align 4, 0x90
.LBB7_1: # =>This Loop Header: Depth=1
# Child Loop BB7_2 Depth 2
movl $1, %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB7_2: # Parent Loop BB7_1 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rcx,%rsi), %edi
imull %edi, %edx
incl %esi
cmpl $4, %esi
jne .LBB7_2
# %bb.3: # in Loop: Header=BB7_1 Depth=1
movslq %edx, %rdx
imulq $715827883, %rdx, %rdx # imm = 0x2AAAAAAB
movq %rdx, %rsi
shrq $63, %rsi
sarq $34, %rdx
addl %esi, %edx
movl %edx, bib-4(,%rax,4)
incq %rax
incl %ecx
cmpq $86, %rax
jne .LBB7_1
# %bb.4:
retq
.Lfunc_end7:
.size _Z15sizeDefinitionsv, .Lfunc_end7-_Z15sizeDefinitionsv
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI8_0:
.quad 0x412e848000000000 # double 1.0E+6
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI8_1:
.zero 16
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $40, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
xorl %edi, %edi
callq _ZNSt8ios_base15sync_with_stdioEb
movl $6, %eax
movl $3, %ecx
.p2align 4, 0x90
.LBB8_1: # =>This Loop Header: Depth=1
# Child Loop BB8_2 Depth 2
movl $1, %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB8_2: # Parent Loop BB8_1 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rcx,%rsi), %edi
imull %edi, %edx
incl %esi
cmpl $4, %esi
jne .LBB8_2
# %bb.3: # in Loop: Header=BB8_1 Depth=1
movslq %edx, %rdx
imulq $715827883, %rdx, %rdx # imm = 0x2AAAAAAB
movq %rdx, %rsi
shrq $63, %rsi
sarq $34, %rdx
addl %esi, %edx
movl %edx, bib-4(,%rax,4)
incq %rax
incl %ecx
cmpq $86, %rax
jne .LBB8_1
# %bb.4: # %_Z15sizeDefinitionsv.exit
callq _Z9readInputv
movl SIZE(%rip), %eax
testl %eax, %eax
jle .LBB8_10
# %bb.5: # %.lr.ph13.preheader.i
leaq -1(%rax), %rcx
leaq (,%rax,4), %rdx
leaq R(,%rax,4), %rsi
leaq 4(,%rax,4), %rdi
movl $R+4, %r8d
xorl %r9d, %r9d
xorl %r10d, %r10d
jmp .LBB8_7
.p2align 4, 0x90
.LBB8_6: # %.loopexit.i
# in Loop: Header=BB8_7 Depth=1
decq %rcx
addq $4, %r8
addl %eax, %r9d
addq %rdi, %rsi
cmpq %rax, %r10
je .LBB8_10
.LBB8_7: # %.lr.ph13.i
# =>This Loop Header: Depth=1
# Child Loop BB8_9 Depth 2
incq %r10
cmpq %rax, %r10
jae .LBB8_6
# %bb.8: # %.lr.ph.i
# in Loop: Header=BB8_7 Depth=1
movl %r9d, %r11d
leaq (%r8,%r11,4), %r11
movq %rsi, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB8_9: # Parent Loop BB8_7 Depth=1
# => This Inner Loop Header: Depth=2
movl $-1, (%rbx)
movl $-1, (%r11,%r14,4)
incq %r14
addq %rdx, %rbx
cmpq %r14, %rcx
jne .LBB8_9
jmp .LBB8_6
.LBB8_10: # %_Z10initializev.exit
xorps %xmm0, %xmm0
movaps %xmm0, (%rsp)
movq $0, 16(%rsp)
movl $16, %edi
callq _Znwm
movq %rax, (%rsp)
movq %rax, 8(%rsp)
leaq 16(%rax), %rcx
movq %rcx, 16(%rsp)
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movq %rcx, 8(%rsp)
movq %rsp, %rsi
xorl %edi, %edi
xorl %edx, %edx
callq _Z12combineUntiliRSt6vectorIiSaIiEEi
movq (%rsp), %rdi
testq %rdi, %rdi
je .LBB8_12
# %bb.11:
callq _ZdlPv
.LBB8_12: # %_Z7combinev.exit
movl $3, %edi
callq hipSetDevice
callq clock
movq %rax, start(%rip)
callq _Z11tmfgPreparev
movl %eax, %ebx
callq clock
movq %rax, stop(%rip)
subq start(%rip), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI8_0(%rip), %xmm0
movsd %xmm0, 32(%rsp) # 8-byte Spill
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rcx
movl $-261, %edx # imm = 0xFEFB
andl _ZSt4cout+24(%rcx), %edx
orl $4, %edx
movl %edx, _ZSt4cout+24(%rcx)
movq -24(%rax), %rax
movq $3, _ZSt4cout+8(%rax)
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.10, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.11, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB8_19
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB8_15
# %bb.14:
movzbl 67(%rbx), %ecx
jmp .LBB8_16
.LBB8_15:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB8_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq N(%rip), %rdi
callq free
callq hipDeviceReset
testl %eax, %eax
jne .LBB8_17
.LBB8_18: # %_Z9gpuAssert10hipError_tPcib.exit
xorl %eax, %eax
addq $40, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB8_17:
.cfi_def_cfa_offset 64
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
movl $.L.str, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $397, %r8d # imm = 0x18D
xorl %eax, %eax
callq fprintf
movq stdin(%rip), %rdi
callq getc
jmp .LBB8_18
.LBB8_19:
callq _ZSt16__throw_bad_castv
.Lfunc_end8:
.size main, .Lfunc_end8-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB9_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB9_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12tmfgParallelP4Node6ParamsPiS2_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end9:
.size __hip_module_ctor, .Lfunc_end9-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB10_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB10_2:
retq
.Lfunc_end10:
.size __hip_module_dtor, .Lfunc_end10-__hip_module_dtor
.cfi_endproc
# -- End function
.type start,@object # @start
.bss
.globl start
.p2align 3, 0x0
start:
.quad 0 # 0x0
.size start, 8
.type stop,@object # @stop
.globl stop
.p2align 3, 0x0
stop:
.quad 0 # 0x0
.size stop, 8
.type SIZE,@object # @SIZE
.globl SIZE
.p2align 2, 0x0
SIZE:
.long 0 # 0x0
.size SIZE, 4
.type BLOCKS,@object # @BLOCKS
.globl BLOCKS
.p2align 2, 0x0
BLOCKS:
.long 0 # 0x0
.size BLOCKS, 4
.type PERM,@object # @PERM
.globl PERM
.p2align 2, 0x0
PERM:
.long 0 # 0x0
.size PERM, 4
.type qtd,@object # @qtd
.globl qtd
.p2align 2, 0x0
qtd:
.long 0 # 0x0
.size qtd, 4
.type R,@object # @R
.globl R
.p2align 4, 0x0
R:
.zero 28900
.size R, 28900
.type F,@object # @F
.globl F
.p2align 4, 0x0
F:
.zero 2720
.size F, 2720
.type bib,@object # @bib
.globl bib
.p2align 4, 0x0
bib:
.zero 340
.size bib, 340
.type N,@object # @N
.globl N
.p2align 3, 0x0
N:
.quad 0
.size N, 8
.type _Z12tmfgParallelP4Node6ParamsPiS2_,@object # @_Z12tmfgParallelP4Node6ParamsPiS2_
.section .rodata,"a",@progbits
.globl _Z12tmfgParallelP4Node6ParamsPiS2_
.p2align 3, 0x0
_Z12tmfgParallelP4Node6ParamsPiS2_:
.quad _Z27__device_stub__tmfgParallelP4Node6ParamsPiS2_
.size _Z12tmfgParallelP4Node6ParamsPiS2_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/viniscoelho/dimpling/master/dimpling/face/previous-versions/3-tmfg-agsh.hip"
.size .L.str, 133
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Amount of memory: "
.size .L.str.1, 19
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "MB"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "1 done."
.size .L.str.3, 8
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "2 done."
.size .L.str.4, 8
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Launching kernel..."
.size .L.str.5, 20
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Kernel finished."
.size .L.str.6, 17
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "3 done."
.size .L.str.7, 8
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Completed."
.size .L.str.8, 11
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Elapsed time: "
.size .L.str.9, 15
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "s\n"
.size .L.str.10, 3
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Maximum weight found: "
.size .L.str.11, 23
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.12, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12tmfgParallelP4Node6ParamsPiS2_"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__tmfgParallelP4Node6ParamsPiS2_
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym SIZE
.addrsig_sym _Z12tmfgParallelP4Node6ParamsPiS2_
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void inputKernel2(float *x, int n, int N)
{
int ix = blockIdx.x * blockDim.x + threadIdx.x,i;
int iy = blockIdx.y * blockDim.y + threadIdx.y;
int idx = iy * NUM_OF_X_THREADS + ix;
if (idx < N)
{
if (idx < n)
{
x[idx*N] = ((float)idx * 2) - ((float)idx * (float)idx);
}
else
{
x[idx] = 0;
}
for(i=1;i<N;i++)
{
x[idx*N + i] = 0;
}
}
} | code for sm_80
Function : _Z12inputKernel2Pfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc400078e0203 */
/*0060*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fc800078e0205 */
/*0070*/ IMAD R0, R3, 0xa, R0 ; /* 0x0000000a03007824 */
/* 0x000fca00078e0200 */
/*0080*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe20003f06270 */
/*00b0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff0b7624 */
/* 0x000fe200078e00ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00d0*/ ISETP.GE.AND P1, PT, R11, 0x2, PT ; /* 0x000000020b00780c */
/* 0x000fce0003f26270 */
/*00e0*/ @!P0 I2F R2, R0 ; /* 0x0000000000028306 */
/* 0x000e220000201400 */
/*00f0*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff090424 */
/* 0x000fe400078e00ff */
/*0100*/ @!P0 IMAD R6, R0.reuse, c[0x0][0x16c], RZ ; /* 0x00005b0000068a24 */
/* 0x040fe400078e02ff */
/*0110*/ @P0 IMAD.WIDE R4, R0, R9, c[0x0][0x160] ; /* 0x0000580000040625 */
/* 0x000fc800078e0209 */
/*0120*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff098424 */
/* 0x000fe200078e00ff */
/*0130*/ @P0 STG.E [R4.64], RZ ; /* 0x000000ff04000986 */
/* 0x0003e2000c101904 */
/*0140*/ @!P0 FADD R3, R2, R2 ; /* 0x0000000202038221 */
/* 0x001fc80000000000 */
/*0150*/ @!P0 FFMA R7, -R2, R2, R3 ; /* 0x0000000202078223 */
/* 0x000fe40000000103 */
/*0160*/ @!P0 IMAD.WIDE R2, R6, R9, c[0x0][0x160] ; /* 0x0000580006028625 */
/* 0x000fca00078e0209 */
/*0170*/ @!P0 STG.E [R2.64], R7 ; /* 0x0000000702008986 */
/* 0x0003e2000c101904 */
/*0180*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0190*/ IADD3 R2, R11, -0x2, RZ ; /* 0xfffffffe0b027810 */
/* 0x002fe20007ffe0ff */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fc600078e00ff */
/*01b0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*01c0*/ IADD3 R2, R11, -0x1, RZ ; /* 0xffffffff0b027810 */
/* 0x000fc80007ffe0ff */
/*01d0*/ LOP3.LUT R4, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302047812 */
/* 0x000fce00078ec0ff */
/*01e0*/ @!P0 BRA 0x620 ; /* 0x0000043000008947 */
/* 0x000fea0003800000 */
/*01f0*/ IADD3 R6, -R4, c[0x0][0x16c], RZ ; /* 0x00005b0004067a10 */
/* 0x000fe20007ffe1ff */
/*0200*/ IMAD R2, R0, R11, 0x1 ; /* 0x0000000100027424 */
/* 0x000fe400078e020b */
/*0210*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fe200078e00ff */
/*0220*/ ISETP.GT.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe20003f04270 */
/*0230*/ IMAD.WIDE R2, R2, R9, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fd800078e0209 */
/*0240*/ @!P0 BRA 0x560 ; /* 0x0000031000008947 */
/* 0x000fea0003800000 */
/*0250*/ IADD3 R7, R6, -0x1, RZ ; /* 0xffffffff06077810 */
/* 0x000fe40007ffe0ff */
/*0260*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0270*/ ISETP.GT.AND P1, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x000fda0003f24270 */
/*0280*/ @!P1 BRA 0x420 ; /* 0x0000019000009947 */
/* 0x000fea0003800000 */
/*0290*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*02a0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fe20007ffe0ff */
/*02b0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*02c0*/ IADD3 R7, P2, R2, 0x40, RZ ; /* 0x0000004002077810 */
/* 0x000fe40007f5e0ff */
/*02d0*/ ISETP.GT.AND P1, PT, R6, 0xd, PT ; /* 0x0000000d0600780c */
/* 0x000fe20003f24270 */
/*02e0*/ STG.E [R2.64+0x4], RZ ; /* 0x000004ff02007986 */
/* 0x000fe2000c101904 */
/*02f0*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x000fe20007ffe0ff */
/*0300*/ IMAD.X R8, RZ, RZ, R3, P2 ; /* 0x000000ffff087224 */
/* 0x000fe400010e0603 */
/*0310*/ STG.E [R2.64+0x8], RZ ; /* 0x000008ff02007986 */
/* 0x000fe8000c101904 */
/*0320*/ STG.E [R2.64+0xc], RZ ; /* 0x00000cff02007986 */
/* 0x000fe8000c101904 */
/*0330*/ STG.E [R2.64+0x10], RZ ; /* 0x000010ff02007986 */
/* 0x000fe8000c101904 */
/*0340*/ STG.E [R2.64+0x14], RZ ; /* 0x000014ff02007986 */
/* 0x000fe8000c101904 */
/*0350*/ STG.E [R2.64+0x18], RZ ; /* 0x000018ff02007986 */
/* 0x000fe8000c101904 */
/*0360*/ STG.E [R2.64+0x1c], RZ ; /* 0x00001cff02007986 */
/* 0x000fe8000c101904 */
/*0370*/ STG.E [R2.64+0x20], RZ ; /* 0x000020ff02007986 */
/* 0x000fe8000c101904 */
/*0380*/ STG.E [R2.64+0x24], RZ ; /* 0x000024ff02007986 */
/* 0x000fe8000c101904 */
/*0390*/ STG.E [R2.64+0x28], RZ ; /* 0x000028ff02007986 */
/* 0x000fe8000c101904 */
/*03a0*/ STG.E [R2.64+0x2c], RZ ; /* 0x00002cff02007986 */
/* 0x000fe8000c101904 */
/*03b0*/ STG.E [R2.64+0x30], RZ ; /* 0x000030ff02007986 */
/* 0x000fe8000c101904 */
/*03c0*/ STG.E [R2.64+0x34], RZ ; /* 0x000034ff02007986 */
/* 0x000fe8000c101904 */
/*03d0*/ STG.E [R2.64+0x38], RZ ; /* 0x000038ff02007986 */
/* 0x000fe8000c101904 */
/*03e0*/ STG.E [R2.64+0x3c], RZ ; /* 0x00003cff02007986 */
/* 0x0001e4000c101904 */
/*03f0*/ IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0007 */
/*0400*/ IMAD.MOV.U32 R3, RZ, RZ, R8 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0008 */
/*0410*/ @P1 BRA 0x2a0 ; /* 0xfffffe8000001947 */
/* 0x000fea000383ffff */
/*0420*/ IADD3 R7, R6, -0x1, RZ ; /* 0xffffffff06077810 */
/* 0x000fc80007ffe0ff */
/*0430*/ ISETP.GT.AND P1, PT, R7, 0x4, PT ; /* 0x000000040700780c */
/* 0x000fda0003f24270 */
/*0440*/ @!P1 BRA 0x540 ; /* 0x000000f000009947 */
/* 0x000fea0003800000 */
/*0450*/ IADD3 R7, P1, R2, 0x20, RZ ; /* 0x0000002002077810 */
/* 0x000fe20007f3e0ff */
/*0460*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*0470*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0480*/ IADD3 R5, R5, 0x8, RZ ; /* 0x0000000805057810 */
/* 0x000fe20007ffe0ff */
/*0490*/ IMAD.X R8, RZ, RZ, R3, P1 ; /* 0x000000ffff087224 */
/* 0x000fe200008e0603 */
/*04a0*/ STG.E [R2.64+0x4], RZ ; /* 0x000004ff02007986 */
/* 0x000fe2000c101904 */
/*04b0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fc60007ffe0ff */
/*04c0*/ STG.E [R2.64+0x8], RZ ; /* 0x000008ff02007986 */
/* 0x000fe8000c101904 */
/*04d0*/ STG.E [R2.64+0xc], RZ ; /* 0x00000cff02007986 */
/* 0x000fe8000c101904 */
/*04e0*/ STG.E [R2.64+0x10], RZ ; /* 0x000010ff02007986 */
/* 0x000fe8000c101904 */
/*04f0*/ STG.E [R2.64+0x14], RZ ; /* 0x000014ff02007986 */
/* 0x000fe8000c101904 */
/*0500*/ STG.E [R2.64+0x18], RZ ; /* 0x000018ff02007986 */
/* 0x000fe8000c101904 */
/*0510*/ STG.E [R2.64+0x1c], RZ ; /* 0x00001cff02007986 */
/* 0x0001e4000c101904 */
/*0520*/ IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0007 */
/*0530*/ IMAD.MOV.U32 R3, RZ, RZ, R8 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0008 */
/*0540*/ ISETP.NE.OR P0, PT, R6, 0x1, P0 ; /* 0x000000010600780c */
/* 0x000fda0000705670 */
/*0550*/ @!P0 BRA 0x620 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0560*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fe20007ffe0ff */
/*0570*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*0580*/ IADD3 R7, P1, R2, 0x10, RZ ; /* 0x0000001002077810 */
/* 0x000fe40007f3e0ff */
/*0590*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe20003f05270 */
/*05a0*/ STG.E [R2.64+0x4], RZ ; /* 0x000004ff02007986 */
/* 0x000fe2000c101904 */
/*05b0*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe20007ffe0ff */
/*05c0*/ IMAD.X R8, RZ, RZ, R3, P1 ; /* 0x000000ffff087224 */
/* 0x000fe400008e0603 */
/*05d0*/ STG.E [R2.64+0x8], RZ ; /* 0x000008ff02007986 */
/* 0x000fe8000c101904 */
/*05e0*/ STG.E [R2.64+0xc], RZ ; /* 0x00000cff02007986 */
/* 0x0001e4000c101904 */
/*05f0*/ IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0007 */
/*0600*/ IMAD.MOV.U32 R3, RZ, RZ, R8 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0008 */
/*0610*/ @P0 BRA 0x560 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*0620*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0630*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0640*/ IMAD R2, R0, c[0x0][0x16c], R5 ; /* 0x00005b0000027a24 */
/* 0x000fc800078e0205 */
/*0650*/ IMAD.WIDE R2, R2, R9, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0209 */
/*0660*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*0670*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e6000c101904 */
/*0680*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*0690*/ IADD3 R2, P1, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fca0007f3e0ff */
/*06a0*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fcc00008e0603 */
/*06b0*/ @P0 BRA 0x660 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*06c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06d0*/ BRA 0x6d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void inputKernel2(float *x, int n, int N)
{
int ix = blockIdx.x * blockDim.x + threadIdx.x,i;
int iy = blockIdx.y * blockDim.y + threadIdx.y;
int idx = iy * NUM_OF_X_THREADS + ix;
if (idx < N)
{
if (idx < n)
{
x[idx*N] = ((float)idx * 2) - ((float)idx * (float)idx);
}
else
{
x[idx] = 0;
}
for(i=1;i<N;i++)
{
x[idx*N + i] = 0;
}
}
} | .file "tmpxft_00176019_00000000-6_inputKernel2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z12inputKernel2PfiiPfii
.type _Z34__device_stub__Z12inputKernel2PfiiPfii, @function
_Z34__device_stub__Z12inputKernel2PfiiPfii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12inputKernel2Pfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z12inputKernel2PfiiPfii, .-_Z34__device_stub__Z12inputKernel2PfiiPfii
.globl _Z12inputKernel2Pfii
.type _Z12inputKernel2Pfii, @function
_Z12inputKernel2Pfii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12inputKernel2PfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12inputKernel2Pfii, .-_Z12inputKernel2Pfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12inputKernel2Pfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12inputKernel2Pfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void inputKernel2(float *x, int n, int N)
{
int ix = blockIdx.x * blockDim.x + threadIdx.x,i;
int iy = blockIdx.y * blockDim.y + threadIdx.y;
int idx = iy * NUM_OF_X_THREADS + ix;
if (idx < N)
{
if (idx < n)
{
x[idx*N] = ((float)idx * 2) - ((float)idx * (float)idx);
}
else
{
x[idx] = 0;
}
for(i=1;i<N;i++)
{
x[idx*N + i] = 0;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void inputKernel2(float *x, int n, int N)
{
int ix = blockIdx.x * blockDim.x + threadIdx.x,i;
int iy = blockIdx.y * blockDim.y + threadIdx.y;
int idx = iy * NUM_OF_X_THREADS + ix;
if (idx < N)
{
if (idx < n)
{
x[idx*N] = ((float)idx * 2) - ((float)idx * (float)idx);
}
else
{
x[idx] = 0;
}
for(i=1;i<N;i++)
{
x[idx*N + i] = 0;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void inputKernel2(float *x, int n, int N)
{
int ix = blockIdx.x * blockDim.x + threadIdx.x,i;
int iy = blockIdx.y * blockDim.y + threadIdx.y;
int idx = iy * NUM_OF_X_THREADS + ix;
if (idx < N)
{
if (idx < n)
{
x[idx*N] = ((float)idx * 2) - ((float)idx * (float)idx);
}
else
{
x[idx] = 0;
}
for(i=1;i<N;i++)
{
x[idx*N + i] = 0;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12inputKernel2Pfii
.globl _Z12inputKernel2Pfii
.p2align 8
.type _Z12inputKernel2Pfii,@function
_Z12inputKernel2Pfii:
s_load_b32 s3, s[0:1], 0x1c
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s3, 16
s_and_b32 s3, s3, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_load_b32 s2, s[0:1], 0xc
s_mul_i32 s14, s14, s3
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v2, 10
v_add3_u32 v2, s14, v0, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_load_b32 s3, s[0:1], 0x8
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s3, v2
s_and_saveexec_b32 s3, vcc_lo
v_cvt_f32_i32_e32 v1, v2
v_mul_lo_u32 v0, v2, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, v1, v1
v_fma_f32 v3, v1, 2.0, -v3
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
s_cmp_lt_i32 s2, 2
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_cbranch_scc1 .LBB0_6
v_mad_u64_u32 v[0:1], null, v2, s2, 1
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_add_i32 s0, s2, -1
.LBB0_5:
global_store_b32 v[0:1], v2, off
v_add_co_u32 v0, vcc_lo, v0, 4
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s0, 0
s_cbranch_scc1 .LBB0_5
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12inputKernel2Pfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12inputKernel2Pfii, .Lfunc_end0-_Z12inputKernel2Pfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12inputKernel2Pfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12inputKernel2Pfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void inputKernel2(float *x, int n, int N)
{
int ix = blockIdx.x * blockDim.x + threadIdx.x,i;
int iy = blockIdx.y * blockDim.y + threadIdx.y;
int idx = iy * NUM_OF_X_THREADS + ix;
if (idx < N)
{
if (idx < n)
{
x[idx*N] = ((float)idx * 2) - ((float)idx * (float)idx);
}
else
{
x[idx] = 0;
}
for(i=1;i<N;i++)
{
x[idx*N + i] = 0;
}
}
} | .text
.file "inputKernel2.hip"
.globl _Z27__device_stub__inputKernel2Pfii # -- Begin function _Z27__device_stub__inputKernel2Pfii
.p2align 4, 0x90
.type _Z27__device_stub__inputKernel2Pfii,@function
_Z27__device_stub__inputKernel2Pfii: # @_Z27__device_stub__inputKernel2Pfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12inputKernel2Pfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__inputKernel2Pfii, .Lfunc_end0-_Z27__device_stub__inputKernel2Pfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12inputKernel2Pfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12inputKernel2Pfii,@object # @_Z12inputKernel2Pfii
.section .rodata,"a",@progbits
.globl _Z12inputKernel2Pfii
.p2align 3, 0x0
_Z12inputKernel2Pfii:
.quad _Z27__device_stub__inputKernel2Pfii
.size _Z12inputKernel2Pfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12inputKernel2Pfii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__inputKernel2Pfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12inputKernel2Pfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12inputKernel2Pfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc400078e0203 */
/*0060*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fc800078e0205 */
/*0070*/ IMAD R0, R3, 0xa, R0 ; /* 0x0000000a03007824 */
/* 0x000fca00078e0200 */
/*0080*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe20003f06270 */
/*00b0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff0b7624 */
/* 0x000fe200078e00ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*00d0*/ ISETP.GE.AND P1, PT, R11, 0x2, PT ; /* 0x000000020b00780c */
/* 0x000fce0003f26270 */
/*00e0*/ @!P0 I2F R2, R0 ; /* 0x0000000000028306 */
/* 0x000e220000201400 */
/*00f0*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff090424 */
/* 0x000fe400078e00ff */
/*0100*/ @!P0 IMAD R6, R0.reuse, c[0x0][0x16c], RZ ; /* 0x00005b0000068a24 */
/* 0x040fe400078e02ff */
/*0110*/ @P0 IMAD.WIDE R4, R0, R9, c[0x0][0x160] ; /* 0x0000580000040625 */
/* 0x000fc800078e0209 */
/*0120*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff098424 */
/* 0x000fe200078e00ff */
/*0130*/ @P0 STG.E [R4.64], RZ ; /* 0x000000ff04000986 */
/* 0x0003e2000c101904 */
/*0140*/ @!P0 FADD R3, R2, R2 ; /* 0x0000000202038221 */
/* 0x001fc80000000000 */
/*0150*/ @!P0 FFMA R7, -R2, R2, R3 ; /* 0x0000000202078223 */
/* 0x000fe40000000103 */
/*0160*/ @!P0 IMAD.WIDE R2, R6, R9, c[0x0][0x160] ; /* 0x0000580006028625 */
/* 0x000fca00078e0209 */
/*0170*/ @!P0 STG.E [R2.64], R7 ; /* 0x0000000702008986 */
/* 0x0003e2000c101904 */
/*0180*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0190*/ IADD3 R2, R11, -0x2, RZ ; /* 0xfffffffe0b027810 */
/* 0x002fe20007ffe0ff */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fc600078e00ff */
/*01b0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*01c0*/ IADD3 R2, R11, -0x1, RZ ; /* 0xffffffff0b027810 */
/* 0x000fc80007ffe0ff */
/*01d0*/ LOP3.LUT R4, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302047812 */
/* 0x000fce00078ec0ff */
/*01e0*/ @!P0 BRA 0x620 ; /* 0x0000043000008947 */
/* 0x000fea0003800000 */
/*01f0*/ IADD3 R6, -R4, c[0x0][0x16c], RZ ; /* 0x00005b0004067a10 */
/* 0x000fe20007ffe1ff */
/*0200*/ IMAD R2, R0, R11, 0x1 ; /* 0x0000000100027424 */
/* 0x000fe400078e020b */
/*0210*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fe200078e00ff */
/*0220*/ ISETP.GT.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe20003f04270 */
/*0230*/ IMAD.WIDE R2, R2, R9, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fd800078e0209 */
/*0240*/ @!P0 BRA 0x560 ; /* 0x0000031000008947 */
/* 0x000fea0003800000 */
/*0250*/ IADD3 R7, R6, -0x1, RZ ; /* 0xffffffff06077810 */
/* 0x000fe40007ffe0ff */
/*0260*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0270*/ ISETP.GT.AND P1, PT, R7, 0xc, PT ; /* 0x0000000c0700780c */
/* 0x000fda0003f24270 */
/*0280*/ @!P1 BRA 0x420 ; /* 0x0000019000009947 */
/* 0x000fea0003800000 */
/*0290*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*02a0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fe20007ffe0ff */
/*02b0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*02c0*/ IADD3 R7, P2, R2, 0x40, RZ ; /* 0x0000004002077810 */
/* 0x000fe40007f5e0ff */
/*02d0*/ ISETP.GT.AND P1, PT, R6, 0xd, PT ; /* 0x0000000d0600780c */
/* 0x000fe20003f24270 */
/*02e0*/ STG.E [R2.64+0x4], RZ ; /* 0x000004ff02007986 */
/* 0x000fe2000c101904 */
/*02f0*/ IADD3 R5, R5, 0x10, RZ ; /* 0x0000001005057810 */
/* 0x000fe20007ffe0ff */
/*0300*/ IMAD.X R8, RZ, RZ, R3, P2 ; /* 0x000000ffff087224 */
/* 0x000fe400010e0603 */
/*0310*/ STG.E [R2.64+0x8], RZ ; /* 0x000008ff02007986 */
/* 0x000fe8000c101904 */
/*0320*/ STG.E [R2.64+0xc], RZ ; /* 0x00000cff02007986 */
/* 0x000fe8000c101904 */
/*0330*/ STG.E [R2.64+0x10], RZ ; /* 0x000010ff02007986 */
/* 0x000fe8000c101904 */
/*0340*/ STG.E [R2.64+0x14], RZ ; /* 0x000014ff02007986 */
/* 0x000fe8000c101904 */
/*0350*/ STG.E [R2.64+0x18], RZ ; /* 0x000018ff02007986 */
/* 0x000fe8000c101904 */
/*0360*/ STG.E [R2.64+0x1c], RZ ; /* 0x00001cff02007986 */
/* 0x000fe8000c101904 */
/*0370*/ STG.E [R2.64+0x20], RZ ; /* 0x000020ff02007986 */
/* 0x000fe8000c101904 */
/*0380*/ STG.E [R2.64+0x24], RZ ; /* 0x000024ff02007986 */
/* 0x000fe8000c101904 */
/*0390*/ STG.E [R2.64+0x28], RZ ; /* 0x000028ff02007986 */
/* 0x000fe8000c101904 */
/*03a0*/ STG.E [R2.64+0x2c], RZ ; /* 0x00002cff02007986 */
/* 0x000fe8000c101904 */
/*03b0*/ STG.E [R2.64+0x30], RZ ; /* 0x000030ff02007986 */
/* 0x000fe8000c101904 */
/*03c0*/ STG.E [R2.64+0x34], RZ ; /* 0x000034ff02007986 */
/* 0x000fe8000c101904 */
/*03d0*/ STG.E [R2.64+0x38], RZ ; /* 0x000038ff02007986 */
/* 0x000fe8000c101904 */
/*03e0*/ STG.E [R2.64+0x3c], RZ ; /* 0x00003cff02007986 */
/* 0x0001e4000c101904 */
/*03f0*/ IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0007 */
/*0400*/ IMAD.MOV.U32 R3, RZ, RZ, R8 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0008 */
/*0410*/ @P1 BRA 0x2a0 ; /* 0xfffffe8000001947 */
/* 0x000fea000383ffff */
/*0420*/ IADD3 R7, R6, -0x1, RZ ; /* 0xffffffff06077810 */
/* 0x000fc80007ffe0ff */
/*0430*/ ISETP.GT.AND P1, PT, R7, 0x4, PT ; /* 0x000000040700780c */
/* 0x000fda0003f24270 */
/*0440*/ @!P1 BRA 0x540 ; /* 0x000000f000009947 */
/* 0x000fea0003800000 */
/*0450*/ IADD3 R7, P1, R2, 0x20, RZ ; /* 0x0000002002077810 */
/* 0x000fe20007f3e0ff */
/*0460*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*0470*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0480*/ IADD3 R5, R5, 0x8, RZ ; /* 0x0000000805057810 */
/* 0x000fe20007ffe0ff */
/*0490*/ IMAD.X R8, RZ, RZ, R3, P1 ; /* 0x000000ffff087224 */
/* 0x000fe200008e0603 */
/*04a0*/ STG.E [R2.64+0x4], RZ ; /* 0x000004ff02007986 */
/* 0x000fe2000c101904 */
/*04b0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fc60007ffe0ff */
/*04c0*/ STG.E [R2.64+0x8], RZ ; /* 0x000008ff02007986 */
/* 0x000fe8000c101904 */
/*04d0*/ STG.E [R2.64+0xc], RZ ; /* 0x00000cff02007986 */
/* 0x000fe8000c101904 */
/*04e0*/ STG.E [R2.64+0x10], RZ ; /* 0x000010ff02007986 */
/* 0x000fe8000c101904 */
/*04f0*/ STG.E [R2.64+0x14], RZ ; /* 0x000014ff02007986 */
/* 0x000fe8000c101904 */
/*0500*/ STG.E [R2.64+0x18], RZ ; /* 0x000018ff02007986 */
/* 0x000fe8000c101904 */
/*0510*/ STG.E [R2.64+0x1c], RZ ; /* 0x00001cff02007986 */
/* 0x0001e4000c101904 */
/*0520*/ IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0007 */
/*0530*/ IMAD.MOV.U32 R3, RZ, RZ, R8 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0008 */
/*0540*/ ISETP.NE.OR P0, PT, R6, 0x1, P0 ; /* 0x000000010600780c */
/* 0x000fda0000705670 */
/*0550*/ @!P0 BRA 0x620 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0560*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fe20007ffe0ff */
/*0570*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*0580*/ IADD3 R7, P1, R2, 0x10, RZ ; /* 0x0000001002077810 */
/* 0x000fe40007f3e0ff */
/*0590*/ ISETP.NE.AND P0, PT, R6, 0x1, PT ; /* 0x000000010600780c */
/* 0x000fe20003f05270 */
/*05a0*/ STG.E [R2.64+0x4], RZ ; /* 0x000004ff02007986 */
/* 0x000fe2000c101904 */
/*05b0*/ IADD3 R5, R5, 0x4, RZ ; /* 0x0000000405057810 */
/* 0x000fe20007ffe0ff */
/*05c0*/ IMAD.X R8, RZ, RZ, R3, P1 ; /* 0x000000ffff087224 */
/* 0x000fe400008e0603 */
/*05d0*/ STG.E [R2.64+0x8], RZ ; /* 0x000008ff02007986 */
/* 0x000fe8000c101904 */
/*05e0*/ STG.E [R2.64+0xc], RZ ; /* 0x00000cff02007986 */
/* 0x0001e4000c101904 */
/*05f0*/ IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff027224 */
/* 0x001fc400078e0007 */
/*0600*/ IMAD.MOV.U32 R3, RZ, RZ, R8 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0008 */
/*0610*/ @P0 BRA 0x560 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*0620*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0630*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0640*/ IMAD R2, R0, c[0x0][0x16c], R5 ; /* 0x00005b0000027a24 */
/* 0x000fc800078e0205 */
/*0650*/ IMAD.WIDE R2, R2, R9, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0209 */
/*0660*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*0670*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e6000c101904 */
/*0680*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*0690*/ IADD3 R2, P1, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fca0007f3e0ff */
/*06a0*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fcc00008e0603 */
/*06b0*/ @P0 BRA 0x660 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*06c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06d0*/ BRA 0x6d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12inputKernel2Pfii
.globl _Z12inputKernel2Pfii
.p2align 8
.type _Z12inputKernel2Pfii,@function
_Z12inputKernel2Pfii:
s_load_b32 s3, s[0:1], 0x1c
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s3, 16
s_and_b32 s3, s3, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s2, v[1:2]
s_load_b32 s2, s[0:1], 0xc
s_mul_i32 s14, s14, s3
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v2, 10
v_add3_u32 v2, s14, v0, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_load_b32 s3, s[0:1], 0x8
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s3, v2
s_and_saveexec_b32 s3, vcc_lo
v_cvt_f32_i32_e32 v1, v2
v_mul_lo_u32 v0, v2, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, v1, v1
v_fma_f32 v3, v1, 2.0, -v3
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
s_cmp_lt_i32 s2, 2
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_cbranch_scc1 .LBB0_6
v_mad_u64_u32 v[0:1], null, v2, s2, 1
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_add_i32 s0, s2, -1
.LBB0_5:
global_store_b32 v[0:1], v2, off
v_add_co_u32 v0, vcc_lo, v0, 4
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s0, 0
s_cbranch_scc1 .LBB0_5
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12inputKernel2Pfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12inputKernel2Pfii, .Lfunc_end0-_Z12inputKernel2Pfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12inputKernel2Pfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12inputKernel2Pfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00176019_00000000-6_inputKernel2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z12inputKernel2PfiiPfii
.type _Z34__device_stub__Z12inputKernel2PfiiPfii, @function
_Z34__device_stub__Z12inputKernel2PfiiPfii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12inputKernel2Pfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z12inputKernel2PfiiPfii, .-_Z34__device_stub__Z12inputKernel2PfiiPfii
.globl _Z12inputKernel2Pfii
.type _Z12inputKernel2Pfii, @function
_Z12inputKernel2Pfii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12inputKernel2PfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12inputKernel2Pfii, .-_Z12inputKernel2Pfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12inputKernel2Pfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12inputKernel2Pfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "inputKernel2.hip"
.globl _Z27__device_stub__inputKernel2Pfii # -- Begin function _Z27__device_stub__inputKernel2Pfii
.p2align 4, 0x90
.type _Z27__device_stub__inputKernel2Pfii,@function
_Z27__device_stub__inputKernel2Pfii: # @_Z27__device_stub__inputKernel2Pfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12inputKernel2Pfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__inputKernel2Pfii, .Lfunc_end0-_Z27__device_stub__inputKernel2Pfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12inputKernel2Pfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12inputKernel2Pfii,@object # @_Z12inputKernel2Pfii
.section .rodata,"a",@progbits
.globl _Z12inputKernel2Pfii
.p2align 3, 0x0
_Z12inputKernel2Pfii:
.quad _Z27__device_stub__inputKernel2Pfii
.size _Z12inputKernel2Pfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12inputKernel2Pfii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__inputKernel2Pfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12inputKernel2Pfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* purpose: just a demo to show how matrix addition can be done on
* the GPU with just a single thread block, ie for rather
* small sized underlying matrix dimensions
* n.b. here we want to consider threadblock dimensions
* different from the actual shape of the arrays
* compilation: nvcc ./single_thread_block_matrix_addition_v2.cu
* usage: ./a.out
*/
#include <stdio.h>
#define N 31
/*
* GPU kernel
*/
__global__ void MatAdd(float **A, float **B, float **C)
{
int i, j, block;
block = blockIdx.x;
i = threadIdx.x;
j = threadIdx.y;
if ( (i < N) && (j < N)) {
C[i][j] = A[i][j] + B[i][j];
}
printf("process (%d,%d) from block %d finished\n", i,j,block);
}
/*
* host main
*/
int main()
{
int i, j;
dim3 threadsPerBlock, numBlocks;
float **A, **B, **C;
/*
* using CUDA unified memory, first allocate
* the memory in convenient 2D format, then
* initialize with some dummy content
*/
cudaMallocManaged(&A, N * sizeof(float *));
cudaMallocManaged(&B, N * sizeof(float *));
cudaMallocManaged(&C, N * sizeof(float *));
for (i = 0; i < N; i++) {
cudaMallocManaged(&A[i], N * sizeof(float));
cudaMallocManaged(&B[i], N * sizeof(float));
cudaMallocManaged(&C[i], N * sizeof(float));
for (j = 0; j < N; j++) {
A[i][j] = (float) ((i * N) + j);
B[i][j] = (N * N) - A[i][j];
C[i][j] = (float) 0;
}
}
/* set up GPU kernel execution configuration */
threadsPerBlock.x = N + 1;
threadsPerBlock.y = N + 1;
numBlocks.x = 1;
/* launch the GPU kernel */
MatAdd<<<numBlocks, threadsPerBlock>>>(A, B, C);
cudaDeviceSynchronize();
/* print result */
for (i = 0; i < N; i++) {
for (j = 0; j < N; j++) {
printf("%d %d %f\n", i, j, C[i][j]);
}
}
/* make clean */
for (i = 0; i < N; i++) {
cudaFree(C[i]);
cudaFree(B[i]);
cudaFree(A[i]);
}
cudaFree(C);
cudaFree(B);
cudaFree(A);
return(0);
} | code for sm_80
Function : _Z6MatAddPPfS0_S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc600078e00ff */
/*0010*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fe40007ffe0ff */
/*0040*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e620000002100 */
/*0050*/ ISETP.GT.AND P0, PT, R9, 0x1e, PT ; /* 0x0000001e0900780c */
/* 0x001fc80003f04270 */
/*0060*/ ISETP.GT.OR P0, PT, R8, 0x1e, P0 ; /* 0x0000001e0800780c */
/* 0x002fda0000704670 */
/*0070*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, 0x8 ; /* 0x00000008ff0b8424 */
/* 0x000fc800078e00ff */
/*0080*/ @!P0 IMAD.WIDE R6, R8, R11, c[0x0][0x160] ; /* 0x0000580008068625 */
/* 0x000fc800078e020b */
/*0090*/ @!P0 IMAD.WIDE R18, R8.reuse, R11.reuse, c[0x0][0x168] ; /* 0x00005a0008128625 */
/* 0x0c0fe400078e020b */
/*00a0*/ @!P0 LDG.E.64 R6, [R6.64] ; /* 0x0000000406068981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ @!P0 LDG.E.64 R4, [R18.64] ; /* 0x0000000412048981 */
/* 0x000ee2000c1e1b00 */
/*00c0*/ @!P0 IMAD.WIDE R10, R8, R11, c[0x0][0x170] ; /* 0x00005c00080a8625 */
/* 0x000fcc00078e020b */
/*00d0*/ @!P0 LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a8981 */
/* 0x000f22000c1e1b00 */
/*00e0*/ @!P0 IMAD.WIDE R16, R9, 0x4, R6 ; /* 0x0000000409108825 */
/* 0x004fc800078e0206 */
/*00f0*/ @!P0 IMAD.WIDE R4, R9.reuse, 0x4, R4 ; /* 0x0000000409048825 */
/* 0x048fe400078e0204 */
/*0100*/ @!P0 LD.E R17, [R16.64] ; /* 0x0000000410118980 */
/* 0x000ea8000c101900 */
/*0110*/ @!P0 LD.E R0, [R4.64] ; /* 0x0000000404008980 */
/* 0x0000a8000c101900 */
/*0120*/ S2R R14, SR_CTAID.X ; /* 0x00000000000e7919 */
/* 0x000e620000002500 */
/*0130*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*0140*/ @!P0 IMAD.WIDE R12, R9, 0x4, R10 ; /* 0x00000004090c8825 */
/* 0x010fca00078e020a */
/*0150*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000ee20000000a00 */
/*0160*/ MOV R4, c[0x4][0x8] ; /* 0x0100020000047a02 */
/* 0x001fe20000000f00 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0180*/ @!P0 FADD R0, R0, R17 ; /* 0x0000001100008221 */
/* 0x004fca0000000000 */
/*0190*/ @!P0 ST.E [R12.64], R0 ; /* 0x000000000c008985 */
/* 0x0001e8000c101904 */
/*01a0*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0001e80000100a00 */
/*01b0*/ STL [R1+0x8], R14 ; /* 0x0000080e01007387 */
/* 0x0021e20000100800 */
/*01c0*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fc80007f1e0ff */
/*01d0*/ IADD3.X R7, RZ, c[0x0][0x24], RZ, P0, !PT ; /* 0x00000900ff077a10 */
/* 0x000fe400007fe4ff */
/*01e0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x009fce0000000000 */
/*01f0*/ MOV R11, 0x260 ; /* 0x00000260000b7802 */
/* 0x000fe40000000f00 */
/*0200*/ MOV R20, 0x1e0 ; /* 0x000001e000147802 */
/* 0x000fe40000000f00 */
/*0210*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0220*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0230*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0240*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0250*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* purpose: just a demo to show how matrix addition can be done on
* the GPU with just a single thread block, ie for rather
* small sized underlying matrix dimensions
* n.b. here we want to consider threadblock dimensions
* different from the actual shape of the arrays
* compilation: nvcc ./single_thread_block_matrix_addition_v2.cu
* usage: ./a.out
*/
#include <stdio.h>
#define N 31
/*
* GPU kernel
*/
__global__ void MatAdd(float **A, float **B, float **C)
{
int i, j, block;
block = blockIdx.x;
i = threadIdx.x;
j = threadIdx.y;
if ( (i < N) && (j < N)) {
C[i][j] = A[i][j] + B[i][j];
}
printf("process (%d,%d) from block %d finished\n", i,j,block);
}
/*
* host main
*/
int main()
{
int i, j;
dim3 threadsPerBlock, numBlocks;
float **A, **B, **C;
/*
* using CUDA unified memory, first allocate
* the memory in convenient 2D format, then
* initialize with some dummy content
*/
cudaMallocManaged(&A, N * sizeof(float *));
cudaMallocManaged(&B, N * sizeof(float *));
cudaMallocManaged(&C, N * sizeof(float *));
for (i = 0; i < N; i++) {
cudaMallocManaged(&A[i], N * sizeof(float));
cudaMallocManaged(&B[i], N * sizeof(float));
cudaMallocManaged(&C[i], N * sizeof(float));
for (j = 0; j < N; j++) {
A[i][j] = (float) ((i * N) + j);
B[i][j] = (N * N) - A[i][j];
C[i][j] = (float) 0;
}
}
/* set up GPU kernel execution configuration */
threadsPerBlock.x = N + 1;
threadsPerBlock.y = N + 1;
numBlocks.x = 1;
/* launch the GPU kernel */
MatAdd<<<numBlocks, threadsPerBlock>>>(A, B, C);
cudaDeviceSynchronize();
/* print result */
for (i = 0; i < N; i++) {
for (j = 0; j < N; j++) {
printf("%d %d %f\n", i, j, C[i][j]);
}
}
/* make clean */
for (i = 0; i < N; i++) {
cudaFree(C[i]);
cudaFree(B[i]);
cudaFree(A[i]);
}
cudaFree(C);
cudaFree(B);
cudaFree(A);
return(0);
} | .file "tmpxft_00074e83_00000000-6_single_thread_block_matrix_addition.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z6MatAddPPfS0_S0_PPfS0_S0_
.type _Z32__device_stub__Z6MatAddPPfS0_S0_PPfS0_S0_, @function
_Z32__device_stub__Z6MatAddPPfS0_S0_PPfS0_S0_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6MatAddPPfS0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z6MatAddPPfS0_S0_PPfS0_S0_, .-_Z32__device_stub__Z6MatAddPPfS0_S0_PPfS0_S0_
.globl _Z6MatAddPPfS0_S0_
.type _Z6MatAddPPfS0_S0_, @function
_Z6MatAddPPfS0_S0_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6MatAddPPfS0_S0_PPfS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6MatAddPPfS0_S0_, .-_Z6MatAddPPfS0_S0_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%d %d %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 8(%rsp), %rdi
movl $1, %edx
movl $248, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $248, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $248, %esi
call cudaMallocManaged@PLT
movl $0, %ebp
movl $0, %ebx
.L13:
movq %rbx, %rdi
addq 8(%rsp), %rdi
movl $1, %edx
movl $124, %esi
call cudaMallocManaged@PLT
movq %rbx, %rdi
addq 16(%rsp), %rdi
movl $1, %edx
movl $124, %esi
call cudaMallocManaged@PLT
movq %rbx, %rdi
addq 24(%rsp), %rdi
movl $1, %edx
movl $124, %esi
call cudaMallocManaged@PLT
movl %ebp, %edx
movl $0, %eax
.L12:
movq 8(%rsp), %rcx
movq (%rcx,%rbx), %rcx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, (%rcx,%rax)
movq 16(%rsp), %rcx
movq (%rcx,%rbx), %rcx
movq 8(%rsp), %rsi
movq (%rsi,%rbx), %rsi
movss .LC0(%rip), %xmm0
subss (%rsi,%rax), %xmm0
movss %xmm0, (%rcx,%rax)
movq 24(%rsp), %rcx
movq (%rcx,%rbx), %rcx
movl $0x00000000, (%rcx,%rax)
addq $4, %rax
addl $1, %edx
cmpq $124, %rax
jne .L12
addq $8, %rbx
addl $31, %ebp
cmpl $961, %ebp
jne .L13
movl $32, 32(%rsp)
movl $32, 36(%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L14:
call cudaDeviceSynchronize@PLT
movl $0, %r14d
leaq .LC2(%rip), %r13
.L15:
movl %r14d, %r12d
leaq 0(,%r14,8), %rbp
movl $0, %ebx
.L16:
movq 24(%rsp), %rax
movq (%rax,%rbp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx,4), %xmm0
movl %ebx, %ecx
movl %r12d, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $31, %rbx
jne .L16
addq $1, %r14
cmpq $31, %r14
jne .L15
movl $0, %ebx
.L17:
movq 24(%rsp), %rax
movq (%rax,%rbx), %rdi
call cudaFree@PLT
movq 16(%rsp), %rax
movq (%rax,%rbx), %rdi
call cudaFree@PLT
movq 8(%rsp), %rax
movq (%rax,%rbx), %rdi
call cudaFree@PLT
addq $8, %rbx
cmpq $248, %rbx
jne .L17
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z6MatAddPPfS0_S0_PPfS0_S0_
jmp .L14
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z6MatAddPPfS0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z6MatAddPPfS0_S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1148207104
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* purpose: just a demo to show how matrix addition can be done on
* the GPU with just a single thread block, ie for rather
* small sized underlying matrix dimensions
* n.b. here we want to consider threadblock dimensions
* different from the actual shape of the arrays
* compilation: nvcc ./single_thread_block_matrix_addition_v2.cu
* usage: ./a.out
*/
#include <stdio.h>
#define N 31
/*
* GPU kernel
*/
__global__ void MatAdd(float **A, float **B, float **C)
{
int i, j, block;
block = blockIdx.x;
i = threadIdx.x;
j = threadIdx.y;
if ( (i < N) && (j < N)) {
C[i][j] = A[i][j] + B[i][j];
}
printf("process (%d,%d) from block %d finished\n", i,j,block);
}
/*
* host main
*/
int main()
{
int i, j;
dim3 threadsPerBlock, numBlocks;
float **A, **B, **C;
/*
* using CUDA unified memory, first allocate
* the memory in convenient 2D format, then
* initialize with some dummy content
*/
cudaMallocManaged(&A, N * sizeof(float *));
cudaMallocManaged(&B, N * sizeof(float *));
cudaMallocManaged(&C, N * sizeof(float *));
for (i = 0; i < N; i++) {
cudaMallocManaged(&A[i], N * sizeof(float));
cudaMallocManaged(&B[i], N * sizeof(float));
cudaMallocManaged(&C[i], N * sizeof(float));
for (j = 0; j < N; j++) {
A[i][j] = (float) ((i * N) + j);
B[i][j] = (N * N) - A[i][j];
C[i][j] = (float) 0;
}
}
/* set up GPU kernel execution configuration */
threadsPerBlock.x = N + 1;
threadsPerBlock.y = N + 1;
numBlocks.x = 1;
/* launch the GPU kernel */
MatAdd<<<numBlocks, threadsPerBlock>>>(A, B, C);
cudaDeviceSynchronize();
/* print result */
for (i = 0; i < N; i++) {
for (j = 0; j < N; j++) {
printf("%d %d %f\n", i, j, C[i][j]);
}
}
/* make clean */
for (i = 0; i < N; i++) {
cudaFree(C[i]);
cudaFree(B[i]);
cudaFree(A[i]);
}
cudaFree(C);
cudaFree(B);
cudaFree(A);
return(0);
} | /*
* purpose: just a demo to show how matrix addition can be done on
* the GPU with just a single thread block, ie for rather
* small sized underlying matrix dimensions
* n.b. here we want to consider threadblock dimensions
* different from the actual shape of the arrays
* compilation: nvcc ./single_thread_block_matrix_addition_v2.cu
* usage: ./a.out
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#define N 31
/*
* GPU kernel
*/
__global__ void MatAdd(float **A, float **B, float **C)
{
int i, j, block;
block = blockIdx.x;
i = threadIdx.x;
j = threadIdx.y;
if ( (i < N) && (j < N)) {
C[i][j] = A[i][j] + B[i][j];
}
printf("process (%d,%d) from block %d finished\n", i,j,block);
}
/*
* host main
*/
int main()
{
int i, j;
dim3 threadsPerBlock, numBlocks;
float **A, **B, **C;
/*
* using CUDA unified memory, first allocate
* the memory in convenient 2D format, then
* initialize with some dummy content
*/
hipMallocManaged(&A, N * sizeof(float *));
hipMallocManaged(&B, N * sizeof(float *));
hipMallocManaged(&C, N * sizeof(float *));
for (i = 0; i < N; i++) {
hipMallocManaged(&A[i], N * sizeof(float));
hipMallocManaged(&B[i], N * sizeof(float));
hipMallocManaged(&C[i], N * sizeof(float));
for (j = 0; j < N; j++) {
A[i][j] = (float) ((i * N) + j);
B[i][j] = (N * N) - A[i][j];
C[i][j] = (float) 0;
}
}
/* set up GPU kernel execution configuration */
threadsPerBlock.x = N + 1;
threadsPerBlock.y = N + 1;
numBlocks.x = 1;
/* launch the GPU kernel */
MatAdd<<<numBlocks, threadsPerBlock>>>(A, B, C);
hipDeviceSynchronize();
/* print result */
for (i = 0; i < N; i++) {
for (j = 0; j < N; j++) {
printf("%d %d %f\n", i, j, C[i][j]);
}
}
/* make clean */
for (i = 0; i < N; i++) {
hipFree(C[i]);
hipFree(B[i]);
hipFree(A[i]);
}
hipFree(C);
hipFree(B);
hipFree(A);
return(0);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* purpose: just a demo to show how matrix addition can be done on
* the GPU with just a single thread block, ie for rather
* small sized underlying matrix dimensions
* n.b. here we want to consider threadblock dimensions
* different from the actual shape of the arrays
* compilation: nvcc ./single_thread_block_matrix_addition_v2.cu
* usage: ./a.out
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#define N 31
/*
* GPU kernel
*/
__global__ void MatAdd(float **A, float **B, float **C)
{
int i, j, block;
block = blockIdx.x;
i = threadIdx.x;
j = threadIdx.y;
if ( (i < N) && (j < N)) {
C[i][j] = A[i][j] + B[i][j];
}
printf("process (%d,%d) from block %d finished\n", i,j,block);
}
/*
* host main
*/
int main()
{
int i, j;
dim3 threadsPerBlock, numBlocks;
float **A, **B, **C;
/*
* using CUDA unified memory, first allocate
* the memory in convenient 2D format, then
* initialize with some dummy content
*/
hipMallocManaged(&A, N * sizeof(float *));
hipMallocManaged(&B, N * sizeof(float *));
hipMallocManaged(&C, N * sizeof(float *));
for (i = 0; i < N; i++) {
hipMallocManaged(&A[i], N * sizeof(float));
hipMallocManaged(&B[i], N * sizeof(float));
hipMallocManaged(&C[i], N * sizeof(float));
for (j = 0; j < N; j++) {
A[i][j] = (float) ((i * N) + j);
B[i][j] = (N * N) - A[i][j];
C[i][j] = (float) 0;
}
}
/* set up GPU kernel execution configuration */
threadsPerBlock.x = N + 1;
threadsPerBlock.y = N + 1;
numBlocks.x = 1;
/* launch the GPU kernel */
MatAdd<<<numBlocks, threadsPerBlock>>>(A, B, C);
hipDeviceSynchronize();
/* print result */
for (i = 0; i < N; i++) {
for (j = 0; j < N; j++) {
printf("%d %d %f\n", i, j, C[i][j]);
}
}
/* make clean */
for (i = 0; i < N; i++) {
hipFree(C[i]);
hipFree(B[i]);
hipFree(A[i]);
}
hipFree(C);
hipFree(B);
hipFree(A);
return(0);
} | .text
.file "single_thread_block_matrix_addition.hip"
.globl _Z21__device_stub__MatAddPPfS0_S0_ # -- Begin function _Z21__device_stub__MatAddPPfS0_S0_
.p2align 4, 0x90
.type _Z21__device_stub__MatAddPPfS0_S0_,@function
_Z21__device_stub__MatAddPPfS0_S0_: # @_Z21__device_stub__MatAddPPfS0_S0_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6MatAddPPfS0_S0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__MatAddPPfS0_S0_, .Lfunc_end0-_Z21__device_stub__MatAddPPfS0_S0_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x44704000 # float 961
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 16(%rsp), %rdi
movl $248, %esi
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $248, %esi
movl $1, %edx
callq hipMallocManaged
movq %rsp, %rdi
movl $248, %esi
movl $1, %edx
callq hipMallocManaged
xorl %r14d, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_1: # =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
leaq (,%r15,8), %rbx
movq 16(%rsp), %rdi
addq %rbx, %rdi
movl $124, %esi
movl $1, %edx
callq hipMallocManaged
movq 8(%rsp), %rdi
addq %rbx, %rdi
movl $124, %esi
movl $1, %edx
callq hipMallocManaged
addq (%rsp), %rbx
movl $124, %esi
movq %rbx, %rdi
movl $1, %edx
callq hipMallocManaged
movss .LCPI1_0(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movq 16(%rsp), %rax
movq (%rax,%r15,8), %rax
movq 8(%rsp), %rcx
movq (%rcx,%r15,8), %rcx
movq (%rsp), %rdx
movq (%rdx,%r15,8), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
leal (%r14,%rsi), %edi
xorps %xmm0, %xmm0
cvtsi2ss %edi, %xmm0
movss %xmm0, (%rax,%rsi,4)
movaps %xmm2, %xmm1
subss %xmm0, %xmm1
movss %xmm1, (%rcx,%rsi,4)
movl $0, (%rdx,%rsi,4)
incq %rsi
cmpq $31, %rsi
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %r15
addq $31, %r14
cmpq $31, %r15
jne .LBB1_1
# %bb.4:
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6MatAddPPfS0_S0_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
callq hipDeviceSynchronize
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_7: # %.preheader48
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movq (%rsp), %rax
movq (%rax,%rbx,8), %rax
movss (%rax,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movl %ebx, %esi
movl %r14d, %edx
movb $1, %al
callq printf
incq %r14
cmpq $31, %r14
jne .LBB1_8
# %bb.9: # in Loop: Header=BB1_7 Depth=1
incq %rbx
cmpq $31, %rbx
jne .LBB1_7
# %bb.10: # %.preheader.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_11: # %.preheader
# =>This Inner Loop Header: Depth=1
movq (%rsp), %rax
movq (%rax,%rbx,8), %rdi
callq hipFree
movq 8(%rsp), %rax
movq (%rax,%rbx,8), %rdi
callq hipFree
movq 16(%rsp), %rax
movq (%rax,%rbx,8), %rdi
callq hipFree
incq %rbx
cmpq $31, %rbx
jne .LBB1_11
# %bb.12:
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6MatAddPPfS0_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6MatAddPPfS0_S0_,@object # @_Z6MatAddPPfS0_S0_
.section .rodata,"a",@progbits
.globl _Z6MatAddPPfS0_S0_
.p2align 3, 0x0
_Z6MatAddPPfS0_S0_:
.quad _Z21__device_stub__MatAddPPfS0_S0_
.size _Z6MatAddPPfS0_S0_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d %d %f\n"
.size .L.str, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6MatAddPPfS0_S0_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__MatAddPPfS0_S0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6MatAddPPfS0_S0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00074e83_00000000-6_single_thread_block_matrix_addition.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z6MatAddPPfS0_S0_PPfS0_S0_
.type _Z32__device_stub__Z6MatAddPPfS0_S0_PPfS0_S0_, @function
_Z32__device_stub__Z6MatAddPPfS0_S0_PPfS0_S0_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6MatAddPPfS0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z6MatAddPPfS0_S0_PPfS0_S0_, .-_Z32__device_stub__Z6MatAddPPfS0_S0_PPfS0_S0_
.globl _Z6MatAddPPfS0_S0_
.type _Z6MatAddPPfS0_S0_, @function
_Z6MatAddPPfS0_S0_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6MatAddPPfS0_S0_PPfS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6MatAddPPfS0_S0_, .-_Z6MatAddPPfS0_S0_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%d %d %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 8(%rsp), %rdi
movl $1, %edx
movl $248, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $248, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $248, %esi
call cudaMallocManaged@PLT
movl $0, %ebp
movl $0, %ebx
.L13:
movq %rbx, %rdi
addq 8(%rsp), %rdi
movl $1, %edx
movl $124, %esi
call cudaMallocManaged@PLT
movq %rbx, %rdi
addq 16(%rsp), %rdi
movl $1, %edx
movl $124, %esi
call cudaMallocManaged@PLT
movq %rbx, %rdi
addq 24(%rsp), %rdi
movl $1, %edx
movl $124, %esi
call cudaMallocManaged@PLT
movl %ebp, %edx
movl $0, %eax
.L12:
movq 8(%rsp), %rcx
movq (%rcx,%rbx), %rcx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, (%rcx,%rax)
movq 16(%rsp), %rcx
movq (%rcx,%rbx), %rcx
movq 8(%rsp), %rsi
movq (%rsi,%rbx), %rsi
movss .LC0(%rip), %xmm0
subss (%rsi,%rax), %xmm0
movss %xmm0, (%rcx,%rax)
movq 24(%rsp), %rcx
movq (%rcx,%rbx), %rcx
movl $0x00000000, (%rcx,%rax)
addq $4, %rax
addl $1, %edx
cmpq $124, %rax
jne .L12
addq $8, %rbx
addl $31, %ebp
cmpl $961, %ebp
jne .L13
movl $32, 32(%rsp)
movl $32, 36(%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L14:
call cudaDeviceSynchronize@PLT
movl $0, %r14d
leaq .LC2(%rip), %r13
.L15:
movl %r14d, %r12d
leaq 0(,%r14,8), %rbp
movl $0, %ebx
.L16:
movq 24(%rsp), %rax
movq (%rax,%rbp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx,4), %xmm0
movl %ebx, %ecx
movl %r12d, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $31, %rbx
jne .L16
addq $1, %r14
cmpq $31, %r14
jne .L15
movl $0, %ebx
.L17:
movq 24(%rsp), %rax
movq (%rax,%rbx), %rdi
call cudaFree@PLT
movq 16(%rsp), %rax
movq (%rax,%rbx), %rdi
call cudaFree@PLT
movq 8(%rsp), %rax
movq (%rax,%rbx), %rdi
call cudaFree@PLT
addq $8, %rbx
cmpq $248, %rbx
jne .L17
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z6MatAddPPfS0_S0_PPfS0_S0_
jmp .L14
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z6MatAddPPfS0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z6MatAddPPfS0_S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1148207104
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "single_thread_block_matrix_addition.hip"
.globl _Z21__device_stub__MatAddPPfS0_S0_ # -- Begin function _Z21__device_stub__MatAddPPfS0_S0_
.p2align 4, 0x90
.type _Z21__device_stub__MatAddPPfS0_S0_,@function
_Z21__device_stub__MatAddPPfS0_S0_: # @_Z21__device_stub__MatAddPPfS0_S0_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6MatAddPPfS0_S0_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__MatAddPPfS0_S0_, .Lfunc_end0-_Z21__device_stub__MatAddPPfS0_S0_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x44704000 # float 961
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 16(%rsp), %rdi
movl $248, %esi
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $248, %esi
movl $1, %edx
callq hipMallocManaged
movq %rsp, %rdi
movl $248, %esi
movl $1, %edx
callq hipMallocManaged
xorl %r14d, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_1: # =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
leaq (,%r15,8), %rbx
movq 16(%rsp), %rdi
addq %rbx, %rdi
movl $124, %esi
movl $1, %edx
callq hipMallocManaged
movq 8(%rsp), %rdi
addq %rbx, %rdi
movl $124, %esi
movl $1, %edx
callq hipMallocManaged
addq (%rsp), %rbx
movl $124, %esi
movq %rbx, %rdi
movl $1, %edx
callq hipMallocManaged
movss .LCPI1_0(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movq 16(%rsp), %rax
movq (%rax,%r15,8), %rax
movq 8(%rsp), %rcx
movq (%rcx,%r15,8), %rcx
movq (%rsp), %rdx
movq (%rdx,%r15,8), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
leal (%r14,%rsi), %edi
xorps %xmm0, %xmm0
cvtsi2ss %edi, %xmm0
movss %xmm0, (%rax,%rsi,4)
movaps %xmm2, %xmm1
subss %xmm0, %xmm1
movss %xmm1, (%rcx,%rsi,4)
movl $0, (%rdx,%rsi,4)
incq %rsi
cmpq $31, %rsi
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %r15
addq $31, %r14
cmpq $31, %r15
jne .LBB1_1
# %bb.4:
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6MatAddPPfS0_S0_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
callq hipDeviceSynchronize
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_7: # %.preheader48
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movq (%rsp), %rax
movq (%rax,%rbx,8), %rax
movss (%rax,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movl %ebx, %esi
movl %r14d, %edx
movb $1, %al
callq printf
incq %r14
cmpq $31, %r14
jne .LBB1_8
# %bb.9: # in Loop: Header=BB1_7 Depth=1
incq %rbx
cmpq $31, %rbx
jne .LBB1_7
# %bb.10: # %.preheader.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_11: # %.preheader
# =>This Inner Loop Header: Depth=1
movq (%rsp), %rax
movq (%rax,%rbx,8), %rdi
callq hipFree
movq 8(%rsp), %rax
movq (%rax,%rbx,8), %rdi
callq hipFree
movq 16(%rsp), %rax
movq (%rax,%rbx,8), %rdi
callq hipFree
incq %rbx
cmpq $31, %rbx
jne .LBB1_11
# %bb.12:
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6MatAddPPfS0_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6MatAddPPfS0_S0_,@object # @_Z6MatAddPPfS0_S0_
.section .rodata,"a",@progbits
.globl _Z6MatAddPPfS0_S0_
.p2align 3, 0x0
_Z6MatAddPPfS0_S0_:
.quad _Z21__device_stub__MatAddPPfS0_S0_
.size _Z6MatAddPPfS0_S0_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d %d %f\n"
.size .L.str, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6MatAddPPfS0_S0_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__MatAddPPfS0_S0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6MatAddPPfS0_S0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<iostream>
using namespace std;
int main(int argc, char* argv[]){
cudaDeviceProp property;
cudaGetDeviceProperties(&property, 0);
cout << property.name << endl;
cout << property.major << endl;
cout << property.minor << endl;
cout << property.totalGlobalMem << endl;
cout << property.clockRate << endl;
cout << "sharedMem" << endl;
cout << property.sharedMemPerBlock << endl;
cout << property.regsPerBlock << endl;
cout << "warpSize" << endl;
cout << property.warpSize << endl;
cout << "Maximum thread" << endl;
cout << property.maxThreadsPerMultiProcessor << endl;
cout << "number of MP" << endl;
cout << property.multiProcessorCount<< endl;
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<iostream>
using namespace std;
int main(int argc, char* argv[]){
cudaDeviceProp property;
cudaGetDeviceProperties(&property, 0);
cout << property.name << endl;
cout << property.major << endl;
cout << property.minor << endl;
cout << property.totalGlobalMem << endl;
cout << property.clockRate << endl;
cout << "sharedMem" << endl;
cout << property.sharedMemPerBlock << endl;
cout << property.regsPerBlock << endl;
cout << "warpSize" << endl;
cout << property.warpSize << endl;
cout << "Maximum thread" << endl;
cout << property.maxThreadsPerMultiProcessor << endl;
cout << "number of MP" << endl;
cout << property.multiProcessorCount<< endl;
return 0;
} | .file "tmpxft_001b9d78_00000000-6_deviceProp.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "sharedMem"
.LC1:
.string "warpSize"
.LC2:
.string "Maximum thread"
.LC3:
.string "number of MP"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1040, %rsp
.cfi_def_cfa_offset 1056
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
movq %rsp, %rbx
movl $0, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbx, %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl 360(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl 364(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 288(%rsp), %rsi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl 348(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC0(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 296(%rsp), %rsi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl 304(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC1(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl 308(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC2(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl 624(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl 388(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L6
movl $0, %eax
addq $1040, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<iostream>
using namespace std;
int main(int argc, char* argv[]){
cudaDeviceProp property;
cudaGetDeviceProperties(&property, 0);
cout << property.name << endl;
cout << property.major << endl;
cout << property.minor << endl;
cout << property.totalGlobalMem << endl;
cout << property.clockRate << endl;
cout << "sharedMem" << endl;
cout << property.sharedMemPerBlock << endl;
cout << property.regsPerBlock << endl;
cout << "warpSize" << endl;
cout << property.warpSize << endl;
cout << "Maximum thread" << endl;
cout << property.maxThreadsPerMultiProcessor << endl;
cout << "number of MP" << endl;
cout << property.multiProcessorCount<< endl;
return 0;
} | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<iostream>
using namespace std;
int main(int argc, char* argv[]){
hipDeviceProp_t property;
hipGetDeviceProperties(&property, 0);
cout << property.name << endl;
cout << property.major << endl;
cout << property.minor << endl;
cout << property.totalGlobalMem << endl;
cout << property.clockRate << endl;
cout << "sharedMem" << endl;
cout << property.sharedMemPerBlock << endl;
cout << property.regsPerBlock << endl;
cout << "warpSize" << endl;
cout << property.warpSize << endl;
cout << "Maximum thread" << endl;
cout << property.maxThreadsPerMultiProcessor << endl;
cout << "number of MP" << endl;
cout << property.multiProcessorCount<< endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<iostream>
using namespace std;
int main(int argc, char* argv[]){
hipDeviceProp_t property;
hipGetDeviceProperties(&property, 0);
cout << property.name << endl;
cout << property.major << endl;
cout << property.minor << endl;
cout << property.totalGlobalMem << endl;
cout << property.clockRate << endl;
cout << "sharedMem" << endl;
cout << property.sharedMemPerBlock << endl;
cout << property.regsPerBlock << endl;
cout << "warpSize" << endl;
cout << property.warpSize << endl;
cout << "Maximum thread" << endl;
cout << property.maxThreadsPerMultiProcessor << endl;
cout << "number of MP" << endl;
cout << property.multiProcessorCount<< endl;
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<iostream>
using namespace std;
int main(int argc, char* argv[]){
hipDeviceProp_t property;
hipGetDeviceProperties(&property, 0);
cout << property.name << endl;
cout << property.major << endl;
cout << property.minor << endl;
cout << property.totalGlobalMem << endl;
cout << property.clockRate << endl;
cout << "sharedMem" << endl;
cout << property.sharedMemPerBlock << endl;
cout << property.regsPerBlock << endl;
cout << "warpSize" << endl;
cout << property.warpSize << endl;
cout << "Maximum thread" << endl;
cout << property.maxThreadsPerMultiProcessor << endl;
cout << "number of MP" << endl;
cout << property.multiProcessorCount<< endl;
return 0;
} | .text
.file "deviceProp.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 8(%rsp), %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movq %rbx, %rdi
callq strlen
movl $_ZSt4cout, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_57
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB0_4
.LBB0_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl 368(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_57
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i2
cmpb $0, 56(%rbx)
je .LBB0_7
# %bb.6:
movzbl 67(%rbx), %ecx
jmp .LBB0_8
.LBB0_7:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit5
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl 372(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_57
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i7
cmpb $0, 56(%rbx)
je .LBB0_11
# %bb.10:
movzbl 67(%rbx), %ecx
jmp .LBB0_12
.LBB0_11:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit10
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 296(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_57
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i12
cmpb $0, 56(%rbx)
je .LBB0_15
# %bb.14:
movzbl 67(%rbx), %ecx
jmp .LBB0_16
.LBB0_15:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit15
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl 356(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_57
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i17
cmpb $0, 56(%rbx)
je .LBB0_19
# %bb.18:
movzbl 67(%rbx), %ecx
jmp .LBB0_20
.LBB0_19:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit20
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_57
# %bb.21: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i22
cmpb $0, 56(%rbx)
je .LBB0_23
# %bb.22:
movzbl 67(%rbx), %eax
jmp .LBB0_24
.LBB0_23:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_24: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit25
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 304(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_57
# %bb.25: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i27
cmpb $0, 56(%rbx)
je .LBB0_27
# %bb.26:
movzbl 67(%rbx), %ecx
jmp .LBB0_28
.LBB0_27:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_28: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit30
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl 312(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_57
# %bb.29: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i32
cmpb $0, 56(%rbx)
je .LBB0_31
# %bb.30:
movzbl 67(%rbx), %ecx
jmp .LBB0_32
.LBB0_31:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_32: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit35
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_57
# %bb.33: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i37
cmpb $0, 56(%rbx)
je .LBB0_35
# %bb.34:
movzbl 67(%rbx), %eax
jmp .LBB0_36
.LBB0_35:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_36: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit40
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl 316(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_57
# %bb.37: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i42
cmpb $0, 56(%rbx)
je .LBB0_39
# %bb.38:
movzbl 67(%rbx), %ecx
jmp .LBB0_40
.LBB0_39:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_40: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit45
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_57
# %bb.41: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i47
cmpb $0, 56(%rbx)
je .LBB0_43
# %bb.42:
movzbl 67(%rbx), %eax
jmp .LBB0_44
.LBB0_43:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_44: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit50
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl 632(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_57
# %bb.45: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i52
cmpb $0, 56(%rbx)
je .LBB0_47
# %bb.46:
movzbl 67(%rbx), %ecx
jmp .LBB0_48
.LBB0_47:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_48: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit55
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_57
# %bb.49: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i57
cmpb $0, 56(%rbx)
je .LBB0_51
# %bb.50:
movzbl 67(%rbx), %eax
jmp .LBB0_52
.LBB0_51:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_52: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit60
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl 396(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_57
# %bb.53: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i62
cmpb $0, 56(%rbx)
je .LBB0_55
# %bb.54:
movzbl 67(%rbx), %ecx
jmp .LBB0_56
.LBB0_55:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_56: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit65
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_57:
.cfi_def_cfa_offset 1504
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "sharedMem"
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "warpSize"
.size .L.str.1, 9
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Maximum thread"
.size .L.str.2, 15
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "number of MP"
.size .L.str.3, 13
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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