system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*! @file gpu_info.cpp
*! @brief print gpu info
*/
#include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
void print_device_props_short()
{
const size_t kb = 1024;
const size_t mb = kb * kb;
int devCount;
cudaGetDeviceCount(&devCount);
printf("Found the following GPUs:\n");
for(int i = 0; i < devCount; ++i)
{
cudaDeviceProp props;
cudaGetDeviceProperties(&props, i);
printf(" | %d: %s\n", i, props.name);
printf(" | arch version / compute capability: %d.%d\n", props.major, props.minor);
printf(" | Global memory: %d MB\n", props.totalGlobalMem / mb);
}
}
void print_device_props_complete()
{
const int kb = 1024;
const int mb = kb * kb;
int devCount;
cudaGetDeviceCount(&devCount);
printf("Found the following GPUs:\n");
for(int i = 0; i < devCount; ++i)
{
cudaDeviceProp props;
cudaGetDeviceProperties(&props, i);
printf(" | %d: %s\n", i, props.name);
printf(" | arch version / compute capability: %d.%d\n", props.major, props.minor);
printf(" | global memory: %d MB\n", props.totalGlobalMem / mb);
printf(" | shared memory: %d KB\n", props.sharedMemPerBlock / kb);
printf(" | constant memory: %d KB\n", props.totalConstMem / kb);
printf(" | 32b-registers per block: %d\n", props.regsPerBlock);
printf(" | warp size: %d\n", props.warpSize );
printf(" | max pitch: %d KB\n", props.memPitch / kb );
printf(" | threads per block: %d\n", props.maxThreadsPerBlock );
printf(" | max block dimensions: %d, %d, %d\n", props.maxThreadsDim[0], props.maxThreadsDim[1], props.maxThreadsDim[2] );
printf(" | max grid dimensions: %d, %d, %d\n", props.maxGridSize[0], props.maxGridSize[1], props.maxGridSize[2] );
printf(" | clock rate: %d Hz\n", props.clockRate);
}
}
extern "C" void gpu_print_info_short() {
print_device_props_short();
}
extern "C" void gpu_print_info_long() {
print_device_props_complete();
} | .file "tmpxft_0005b6be_00000000-6_gpu_info.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Found the following GPUs:\n"
.LC1:
.string " | %d: %s\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string " | arch version / compute capability: %d.%d\n"
.section .rodata.str1.1
.LC3:
.string " | Global memory: %d MB\n"
.text
.globl _Z24print_device_props_shortv
.type _Z24print_device_props_shortv, @function
_Z24print_device_props_shortv:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $1056, %rsp
.cfi_def_cfa_offset 1104
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L3
movl $0, %ebx
leaq 16(%rsp), %rbp
leaq .LC1(%rip), %r14
leaq .LC2(%rip), %r13
leaq .LC3(%rip), %r12
.L5:
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbp, %rcx
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %ecx
movl 376(%rsp), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rdx
shrq $20, %rdx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jg .L5
.L3:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z24print_device_props_shortv, .-_Z24print_device_props_shortv
.section .rodata.str1.1
.LC4:
.string " | global memory: %d MB\n"
.LC5:
.string " | shared memory: %d KB\n"
.LC6:
.string " | constant memory: %d KB\n"
.section .rodata.str1.8
.align 8
.LC7:
.string " | 32b-registers per block: %d\n"
.section .rodata.str1.1
.LC8:
.string " | warp size: %d\n"
.LC9:
.string " | max pitch: %d KB\n"
.LC10:
.string " | threads per block: %d\n"
.section .rodata.str1.8
.align 8
.LC11:
.string " | max block dimensions: %d, %d, %d\n"
.align 8
.LC12:
.string " | max grid dimensions: %d, %d, %d\n"
.section .rodata.str1.1
.LC13:
.string " | clock rate: %d Hz\n"
.text
.globl _Z27print_device_props_completev
.type _Z27print_device_props_completev, @function
_Z27print_device_props_completev:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L10
movl $0, %ebx
leaq .LC1(%rip), %r14
leaq .LC2(%rip), %r13
leaq .LC4(%rip), %r12
leaq .LC5(%rip), %rbp
.L12:
leaq 16(%rsp), %r15
movl %ebx, %esi
movq %r15, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %r15, %rcx
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %ecx
movl 376(%rsp), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rdx
shrq $20, %rdx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 312(%rsp), %rdx
shrq $10, %rdx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 368(%rsp), %rdx
shrq $10, %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 320(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 324(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 328(%rsp), %rdx
shrq $10, %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 364(%rsp), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jg .L12
.L10:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z27print_device_props_completev, .-_Z27print_device_props_completev
.globl gpu_print_info_short
.type gpu_print_info_short, @function
gpu_print_info_short:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24print_device_props_shortv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size gpu_print_info_short, .-gpu_print_info_short
.globl gpu_print_info_long
.type gpu_print_info_long, @function
gpu_print_info_long:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27print_device_props_completev
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size gpu_print_info_long, .-gpu_print_info_long
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*! @file gpu_info.cpp
*! @brief print gpu info
*/
#include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
void print_device_props_short()
{
const size_t kb = 1024;
const size_t mb = kb * kb;
int devCount;
cudaGetDeviceCount(&devCount);
printf("Found the following GPUs:\n");
for(int i = 0; i < devCount; ++i)
{
cudaDeviceProp props;
cudaGetDeviceProperties(&props, i);
printf(" | %d: %s\n", i, props.name);
printf(" | arch version / compute capability: %d.%d\n", props.major, props.minor);
printf(" | Global memory: %d MB\n", props.totalGlobalMem / mb);
}
}
void print_device_props_complete()
{
const int kb = 1024;
const int mb = kb * kb;
int devCount;
cudaGetDeviceCount(&devCount);
printf("Found the following GPUs:\n");
for(int i = 0; i < devCount; ++i)
{
cudaDeviceProp props;
cudaGetDeviceProperties(&props, i);
printf(" | %d: %s\n", i, props.name);
printf(" | arch version / compute capability: %d.%d\n", props.major, props.minor);
printf(" | global memory: %d MB\n", props.totalGlobalMem / mb);
printf(" | shared memory: %d KB\n", props.sharedMemPerBlock / kb);
printf(" | constant memory: %d KB\n", props.totalConstMem / kb);
printf(" | 32b-registers per block: %d\n", props.regsPerBlock);
printf(" | warp size: %d\n", props.warpSize );
printf(" | max pitch: %d KB\n", props.memPitch / kb );
printf(" | threads per block: %d\n", props.maxThreadsPerBlock );
printf(" | max block dimensions: %d, %d, %d\n", props.maxThreadsDim[0], props.maxThreadsDim[1], props.maxThreadsDim[2] );
printf(" | max grid dimensions: %d, %d, %d\n", props.maxGridSize[0], props.maxGridSize[1], props.maxGridSize[2] );
printf(" | clock rate: %d Hz\n", props.clockRate);
}
}
extern "C" void gpu_print_info_short() {
print_device_props_short();
}
extern "C" void gpu_print_info_long() {
print_device_props_complete();
} | /*! @file gpu_info.cpp
*! @brief print gpu info
*/
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
void print_device_props_short()
{
const size_t kb = 1024;
const size_t mb = kb * kb;
int devCount;
hipGetDeviceCount(&devCount);
printf("Found the following GPUs:\n");
for(int i = 0; i < devCount; ++i)
{
hipDeviceProp_t props;
hipGetDeviceProperties(&props, i);
printf(" | %d: %s\n", i, props.name);
printf(" | arch version / compute capability: %d.%d\n", props.major, props.minor);
printf(" | Global memory: %d MB\n", props.totalGlobalMem / mb);
}
}
void print_device_props_complete()
{
const int kb = 1024;
const int mb = kb * kb;
int devCount;
hipGetDeviceCount(&devCount);
printf("Found the following GPUs:\n");
for(int i = 0; i < devCount; ++i)
{
hipDeviceProp_t props;
hipGetDeviceProperties(&props, i);
printf(" | %d: %s\n", i, props.name);
printf(" | arch version / compute capability: %d.%d\n", props.major, props.minor);
printf(" | global memory: %d MB\n", props.totalGlobalMem / mb);
printf(" | shared memory: %d KB\n", props.sharedMemPerBlock / kb);
printf(" | constant memory: %d KB\n", props.totalConstMem / kb);
printf(" | 32b-registers per block: %d\n", props.regsPerBlock);
printf(" | warp size: %d\n", props.warpSize );
printf(" | max pitch: %d KB\n", props.memPitch / kb );
printf(" | threads per block: %d\n", props.maxThreadsPerBlock );
printf(" | max block dimensions: %d, %d, %d\n", props.maxThreadsDim[0], props.maxThreadsDim[1], props.maxThreadsDim[2] );
printf(" | max grid dimensions: %d, %d, %d\n", props.maxGridSize[0], props.maxGridSize[1], props.maxGridSize[2] );
printf(" | clock rate: %d Hz\n", props.clockRate);
}
}
extern "C" void gpu_print_info_short() {
print_device_props_short();
}
extern "C" void gpu_print_info_long() {
print_device_props_complete();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*! @file gpu_info.cpp
*! @brief print gpu info
*/
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
void print_device_props_short()
{
const size_t kb = 1024;
const size_t mb = kb * kb;
int devCount;
hipGetDeviceCount(&devCount);
printf("Found the following GPUs:\n");
for(int i = 0; i < devCount; ++i)
{
hipDeviceProp_t props;
hipGetDeviceProperties(&props, i);
printf(" | %d: %s\n", i, props.name);
printf(" | arch version / compute capability: %d.%d\n", props.major, props.minor);
printf(" | Global memory: %d MB\n", props.totalGlobalMem / mb);
}
}
void print_device_props_complete()
{
const int kb = 1024;
const int mb = kb * kb;
int devCount;
hipGetDeviceCount(&devCount);
printf("Found the following GPUs:\n");
for(int i = 0; i < devCount; ++i)
{
hipDeviceProp_t props;
hipGetDeviceProperties(&props, i);
printf(" | %d: %s\n", i, props.name);
printf(" | arch version / compute capability: %d.%d\n", props.major, props.minor);
printf(" | global memory: %d MB\n", props.totalGlobalMem / mb);
printf(" | shared memory: %d KB\n", props.sharedMemPerBlock / kb);
printf(" | constant memory: %d KB\n", props.totalConstMem / kb);
printf(" | 32b-registers per block: %d\n", props.regsPerBlock);
printf(" | warp size: %d\n", props.warpSize );
printf(" | max pitch: %d KB\n", props.memPitch / kb );
printf(" | threads per block: %d\n", props.maxThreadsPerBlock );
printf(" | max block dimensions: %d, %d, %d\n", props.maxThreadsDim[0], props.maxThreadsDim[1], props.maxThreadsDim[2] );
printf(" | max grid dimensions: %d, %d, %d\n", props.maxGridSize[0], props.maxGridSize[1], props.maxGridSize[2] );
printf(" | clock rate: %d Hz\n", props.clockRate);
}
}
extern "C" void gpu_print_info_short() {
print_device_props_short();
}
extern "C" void gpu_print_info_long() {
print_device_props_complete();
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*! @file gpu_info.cpp
*! @brief print gpu info
*/
#include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
void print_device_props_short()
{
const size_t kb = 1024;
const size_t mb = kb * kb;
int devCount;
hipGetDeviceCount(&devCount);
printf("Found the following GPUs:\n");
for(int i = 0; i < devCount; ++i)
{
hipDeviceProp_t props;
hipGetDeviceProperties(&props, i);
printf(" | %d: %s\n", i, props.name);
printf(" | arch version / compute capability: %d.%d\n", props.major, props.minor);
printf(" | Global memory: %d MB\n", props.totalGlobalMem / mb);
}
}
void print_device_props_complete()
{
const int kb = 1024;
const int mb = kb * kb;
int devCount;
hipGetDeviceCount(&devCount);
printf("Found the following GPUs:\n");
for(int i = 0; i < devCount; ++i)
{
hipDeviceProp_t props;
hipGetDeviceProperties(&props, i);
printf(" | %d: %s\n", i, props.name);
printf(" | arch version / compute capability: %d.%d\n", props.major, props.minor);
printf(" | global memory: %d MB\n", props.totalGlobalMem / mb);
printf(" | shared memory: %d KB\n", props.sharedMemPerBlock / kb);
printf(" | constant memory: %d KB\n", props.totalConstMem / kb);
printf(" | 32b-registers per block: %d\n", props.regsPerBlock);
printf(" | warp size: %d\n", props.warpSize );
printf(" | max pitch: %d KB\n", props.memPitch / kb );
printf(" | threads per block: %d\n", props.maxThreadsPerBlock );
printf(" | max block dimensions: %d, %d, %d\n", props.maxThreadsDim[0], props.maxThreadsDim[1], props.maxThreadsDim[2] );
printf(" | max grid dimensions: %d, %d, %d\n", props.maxGridSize[0], props.maxGridSize[1], props.maxGridSize[2] );
printf(" | clock rate: %d Hz\n", props.clockRate);
}
}
extern "C" void gpu_print_info_short() {
print_device_props_short();
}
extern "C" void gpu_print_info_long() {
print_device_props_complete();
} | .text
.file "gpu_info.hip"
.globl _Z24print_device_props_shortv # -- Begin function _Z24print_device_props_shortv
.p2align 4, 0x90
.type _Z24print_device_props_shortv,@function
_Z24print_device_props_shortv: # @_Z24print_device_props_shortv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl $.Lstr.1, %edi
callq puts@PLT
cmpl $0, 4(%rsp)
jle .LBB0_3
# %bb.1: # %.lr.ph
leaq 8(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.1, %edi
movl %ebp, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq printf
movl 368(%rsp), %esi
movl 372(%rsp), %edx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq 296(%rsp), %rsi
shrq $20, %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
incl %ebp
cmpl 4(%rsp), %ebp
jl .LBB0_2
.LBB0_3: # %._crit_edge
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z24print_device_props_shortv, .Lfunc_end0-_Z24print_device_props_shortv
.cfi_endproc
# -- End function
.globl _Z27print_device_props_completev # -- Begin function _Z27print_device_props_completev
.p2align 4, 0x90
.type _Z27print_device_props_completev,@function
_Z27print_device_props_completev: # @_Z27print_device_props_completev
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl $.Lstr.1, %edi
callq puts@PLT
cmpl $0, 4(%rsp)
jle .LBB1_3
# %bb.1: # %.lr.ph
leaq 8(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_2: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.1, %edi
movl %ebp, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq printf
movl 368(%rsp), %esi
movl 372(%rsp), %edx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq 296(%rsp), %rsi
shrq $20, %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movq 304(%rsp), %rsi
shrq $10, %rsi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movq 360(%rsp), %rsi
shrq $10, %rsi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl 312(%rsp), %esi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 316(%rsp), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movq 320(%rsp), %rsi
shrq $10, %rsi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 328(%rsp), %esi
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl 332(%rsp), %esi
movl 336(%rsp), %edx
movl 340(%rsp), %ecx
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl 344(%rsp), %esi
movl 348(%rsp), %edx
movl 352(%rsp), %ecx
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movl 356(%rsp), %esi
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
incl %ebp
cmpl 4(%rsp), %ebp
jl .LBB1_2
.LBB1_3: # %._crit_edge
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z27print_device_props_completev, .Lfunc_end1-_Z27print_device_props_completev
.cfi_endproc
# -- End function
.globl gpu_print_info_short # -- Begin function gpu_print_info_short
.p2align 4, 0x90
.type gpu_print_info_short,@function
gpu_print_info_short: # @gpu_print_info_short
.cfi_startproc
# %bb.0:
jmp _Z24print_device_props_shortv # TAILCALL
.Lfunc_end2:
.size gpu_print_info_short, .Lfunc_end2-gpu_print_info_short
.cfi_endproc
# -- End function
.globl gpu_print_info_long # -- Begin function gpu_print_info_long
.p2align 4, 0x90
.type gpu_print_info_long,@function
gpu_print_info_long: # @gpu_print_info_long
.cfi_startproc
# %bb.0:
jmp _Z27print_device_props_completev # TAILCALL
.Lfunc_end3:
.size gpu_print_info_long, .Lfunc_end3-gpu_print_info_long
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz " | %d: %s\n"
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " | arch version / compute capability: %d.%d\n"
.size .L.str.2, 46
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " | Global memory: %d MB\n"
.size .L.str.3, 26
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " | global memory: %d MB\n"
.size .L.str.4, 26
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " | shared memory: %d KB\n"
.size .L.str.5, 26
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " | constant memory: %d KB\n"
.size .L.str.6, 28
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " | 32b-registers per block: %d\n"
.size .L.str.7, 33
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " | warp size: %d\n"
.size .L.str.8, 19
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " | max pitch: %d KB\n"
.size .L.str.9, 22
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz " | threads per block: %d\n"
.size .L.str.10, 27
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz " | max block dimensions: %d, %d, %d\n"
.size .L.str.11, 38
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz " | max grid dimensions: %d, %d, %d\n"
.size .L.str.12, 37
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz " | clock rate: %d Hz\n"
.size .L.str.13, 23
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "Found the following GPUs:"
.size .Lstr.1, 26
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005b6be_00000000-6_gpu_info.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Found the following GPUs:\n"
.LC1:
.string " | %d: %s\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string " | arch version / compute capability: %d.%d\n"
.section .rodata.str1.1
.LC3:
.string " | Global memory: %d MB\n"
.text
.globl _Z24print_device_props_shortv
.type _Z24print_device_props_shortv, @function
_Z24print_device_props_shortv:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $1056, %rsp
.cfi_def_cfa_offset 1104
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L3
movl $0, %ebx
leaq 16(%rsp), %rbp
leaq .LC1(%rip), %r14
leaq .LC2(%rip), %r13
leaq .LC3(%rip), %r12
.L5:
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbp, %rcx
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %ecx
movl 376(%rsp), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rdx
shrq $20, %rdx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jg .L5
.L3:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z24print_device_props_shortv, .-_Z24print_device_props_shortv
.section .rodata.str1.1
.LC4:
.string " | global memory: %d MB\n"
.LC5:
.string " | shared memory: %d KB\n"
.LC6:
.string " | constant memory: %d KB\n"
.section .rodata.str1.8
.align 8
.LC7:
.string " | 32b-registers per block: %d\n"
.section .rodata.str1.1
.LC8:
.string " | warp size: %d\n"
.LC9:
.string " | max pitch: %d KB\n"
.LC10:
.string " | threads per block: %d\n"
.section .rodata.str1.8
.align 8
.LC11:
.string " | max block dimensions: %d, %d, %d\n"
.align 8
.LC12:
.string " | max grid dimensions: %d, %d, %d\n"
.section .rodata.str1.1
.LC13:
.string " | clock rate: %d Hz\n"
.text
.globl _Z27print_device_props_completev
.type _Z27print_device_props_completev, @function
_Z27print_device_props_completev:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L10
movl $0, %ebx
leaq .LC1(%rip), %r14
leaq .LC2(%rip), %r13
leaq .LC4(%rip), %r12
leaq .LC5(%rip), %rbp
.L12:
leaq 16(%rsp), %r15
movl %ebx, %esi
movq %r15, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %r15, %rcx
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %ecx
movl 376(%rsp), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rdx
shrq $20, %rdx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 312(%rsp), %rdx
shrq $10, %rdx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 368(%rsp), %rdx
shrq $10, %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 320(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 324(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 328(%rsp), %rdx
shrq $10, %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 364(%rsp), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jg .L12
.L10:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z27print_device_props_completev, .-_Z27print_device_props_completev
.globl gpu_print_info_short
.type gpu_print_info_short, @function
gpu_print_info_short:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24print_device_props_shortv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size gpu_print_info_short, .-gpu_print_info_short
.globl gpu_print_info_long
.type gpu_print_info_long, @function
gpu_print_info_long:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27print_device_props_completev
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size gpu_print_info_long, .-gpu_print_info_long
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpu_info.hip"
.globl _Z24print_device_props_shortv # -- Begin function _Z24print_device_props_shortv
.p2align 4, 0x90
.type _Z24print_device_props_shortv,@function
_Z24print_device_props_shortv: # @_Z24print_device_props_shortv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl $.Lstr.1, %edi
callq puts@PLT
cmpl $0, 4(%rsp)
jle .LBB0_3
# %bb.1: # %.lr.ph
leaq 8(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.1, %edi
movl %ebp, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq printf
movl 368(%rsp), %esi
movl 372(%rsp), %edx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq 296(%rsp), %rsi
shrq $20, %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
incl %ebp
cmpl 4(%rsp), %ebp
jl .LBB0_2
.LBB0_3: # %._crit_edge
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z24print_device_props_shortv, .Lfunc_end0-_Z24print_device_props_shortv
.cfi_endproc
# -- End function
.globl _Z27print_device_props_completev # -- Begin function _Z27print_device_props_completev
.p2align 4, 0x90
.type _Z27print_device_props_completev,@function
_Z27print_device_props_completev: # @_Z27print_device_props_completev
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl $.Lstr.1, %edi
callq puts@PLT
cmpl $0, 4(%rsp)
jle .LBB1_3
# %bb.1: # %.lr.ph
leaq 8(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_2: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.1, %edi
movl %ebp, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq printf
movl 368(%rsp), %esi
movl 372(%rsp), %edx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq 296(%rsp), %rsi
shrq $20, %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movq 304(%rsp), %rsi
shrq $10, %rsi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movq 360(%rsp), %rsi
shrq $10, %rsi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl 312(%rsp), %esi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 316(%rsp), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movq 320(%rsp), %rsi
shrq $10, %rsi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 328(%rsp), %esi
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl 332(%rsp), %esi
movl 336(%rsp), %edx
movl 340(%rsp), %ecx
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl 344(%rsp), %esi
movl 348(%rsp), %edx
movl 352(%rsp), %ecx
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movl 356(%rsp), %esi
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
incl %ebp
cmpl 4(%rsp), %ebp
jl .LBB1_2
.LBB1_3: # %._crit_edge
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z27print_device_props_completev, .Lfunc_end1-_Z27print_device_props_completev
.cfi_endproc
# -- End function
.globl gpu_print_info_short # -- Begin function gpu_print_info_short
.p2align 4, 0x90
.type gpu_print_info_short,@function
gpu_print_info_short: # @gpu_print_info_short
.cfi_startproc
# %bb.0:
jmp _Z24print_device_props_shortv # TAILCALL
.Lfunc_end2:
.size gpu_print_info_short, .Lfunc_end2-gpu_print_info_short
.cfi_endproc
# -- End function
.globl gpu_print_info_long # -- Begin function gpu_print_info_long
.p2align 4, 0x90
.type gpu_print_info_long,@function
gpu_print_info_long: # @gpu_print_info_long
.cfi_startproc
# %bb.0:
jmp _Z27print_device_props_completev # TAILCALL
.Lfunc_end3:
.size gpu_print_info_long, .Lfunc_end3-gpu_print_info_long
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz " | %d: %s\n"
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " | arch version / compute capability: %d.%d\n"
.size .L.str.2, 46
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " | Global memory: %d MB\n"
.size .L.str.3, 26
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " | global memory: %d MB\n"
.size .L.str.4, 26
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " | shared memory: %d KB\n"
.size .L.str.5, 26
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " | constant memory: %d KB\n"
.size .L.str.6, 28
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " | 32b-registers per block: %d\n"
.size .L.str.7, 33
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " | warp size: %d\n"
.size .L.str.8, 19
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " | max pitch: %d KB\n"
.size .L.str.9, 22
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz " | threads per block: %d\n"
.size .L.str.10, 27
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz " | max block dimensions: %d, %d, %d\n"
.size .L.str.11, 38
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz " | max grid dimensions: %d, %d, %d\n"
.size .L.str.12, 37
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz " | clock rate: %d Hz\n"
.size .L.str.13, 23
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "Found the following GPUs:"
.size .Lstr.1, 26
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <math.h>
#define N 8
#define THREAD_PER_BLOCK 2
__global__ void multiply(int * in1, int * in2, int * out, int size) {
int index = threadIdx.x + blockIdx.x * blockDim.x;
int startrow = (index / size) * size;
int startcol = index % size;
int i;
int sum = 0;
for(i = 0; i < size; ++i) {
sum += in1[startrow + i] * in2[startcol + i * size];
}
out[index] = sum;
}
int main()
{
int * in1, * in2, * out;
int * d_in1, * d_in2, * d_out;
int size = N * N * sizeof(int);
int i;
cudaMalloc((void**)&d_in1, size);
cudaMalloc((void**)&d_in2, size);
cudaMalloc((void**)&d_out, size);
in1 = (int *)malloc(size);
in2 = (int *)malloc(size);
out = (int *)malloc(size);
for(i = 0; i<N*N; ++i)
{
in1[i] = i%N;
in2[i] = i%N -1;
}
cudaMemcpy(d_in1, in1, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_in2, in2, size, cudaMemcpyHostToDevice);
multiply<<< N*N/THREAD_PER_BLOCK, THREAD_PER_BLOCK >>>(d_in1, d_in2, d_out, N);
cudaMemcpy(out, d_out, size, cudaMemcpyDeviceToHost);
for(i=0; i<N*N; ++i)
{
printf("%2d ", in1[i]);
if((i+1)%N == 0) {
printf("\n");
}
}
printf("--------\n");
for(i=0; i<N*N; ++i)
{
printf("%2d ", in2[i]);
if((i+1)%N == 0) {
printf("\n");
}
}
printf("--------\n");
for(i=0; i<N*N; ++i)
{
printf("%2d ", out[i]);
if((i+1)%N == 0) {
printf("\n");
}
}
free(in1); free(in2); free(out);
cudaFree(d_in1); cudaFree(d_in2);
cudaFree(d_out);
return 0;
} | code for sm_80
Function : _Z8multiplyPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IABS R8, c[0x0][0x178] ; /* 0x00005e0000087a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R18, -RZ, RZ, 0, 0 ; /* 0x00000000ff127435 */
/* 0x000fe200000001ff */
/*0050*/ I2F.RP R6, R8 ; /* 0x0000000800067306 */
/* 0x000e620000209400 */
/*0060*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e2e0000002100 */
/*0070*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x002e620000001000 */
/*0080*/ IMAD R2, R0, c[0x0][0x0], R3 ; /* 0x0000000000027a24 */
/* 0x001fca00078e0203 */
/*0090*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f26270 */
/*00a0*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x002fe40007ffe0ff */
/*00b0*/ IABS R6, R2 ; /* 0x0000000200067213 */
/* 0x000fe40000000000 */
/*00c0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*00d0*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*00e0*/ IADD3 R7, RZ, -R5, RZ ; /* 0x80000005ff077210 */
/* 0x002fca0007ffe0ff */
/*00f0*/ IMAD R7, R7, R8, RZ ; /* 0x0000000807077224 */
/* 0x000fc800078e02ff */
/*0100*/ IMAD.HI.U32 R5, R5, R7, R4 ; /* 0x0000000705057227 */
/* 0x000fe200078e0004 */
/*0110*/ MOV R4, c[0x0][0x178] ; /* 0x00005e0000047a02 */
/* 0x000fca0000000f00 */
/*0120*/ IMAD.HI.U32 R5, R5, R6, RZ ; /* 0x0000000605057227 */
/* 0x000fca00078e00ff */
/*0130*/ IADD3 R5, -R5, RZ, RZ ; /* 0x000000ff05057210 */
/* 0x000fca0007ffe1ff */
/*0140*/ IMAD R5, R8, R5, R6 ; /* 0x0000000508057224 */
/* 0x000fca00078e0206 */
/*0150*/ ISETP.GT.U32.AND P0, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fda0003f04070 */
/*0160*/ @!P0 IADD3 R5, R5, -R8, RZ ; /* 0x8000000805058210 */
/* 0x000fe40007ffe0ff */
/*0170*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe40003f05270 */
/*0180*/ ISETP.GT.U32.AND P2, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fda0003f44070 */
/*0190*/ @!P2 IADD3 R5, R5, -R8, RZ ; /* 0x800000080505a210 */
/* 0x000fe40007ffe0ff */
/*01a0*/ ISETP.GE.AND P2, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe40003f46270 */
/*01b0*/ @!P1 IADD3 R5, -R5, RZ, RZ ; /* 0x000000ff05059210 */
/* 0x000fe40007ffe1ff */
/*01c0*/ @!P0 LOP3.LUT R5, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff058a12 */
/* 0x000fd200078e33ff */
/*01d0*/ @!P2 BRA 0xd00 ; /* 0x00000b200000a947 */
/* 0x000fea0003800000 */
/*01e0*/ IADD3 R6, R4.reuse, -0x1, RZ ; /* 0xffffffff04067810 */
/* 0x040fe40007ffe0ff */
/*01f0*/ LOP3.LUT R7, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304077812 */
/* 0x000fe400078ec0ff */
/*0200*/ ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f06070 */
/*0210*/ MOV R18, RZ ; /* 0x000000ff00127202 */
/* 0x000fe40000000f00 */
/*0220*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x000fd20000000f00 */
/*0230*/ @!P0 BRA 0xbe0 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0240*/ IADD3 R8, -R7, c[0x0][0x178], RZ ; /* 0x00005e0007087a10 */
/* 0x000fe20007ffe1ff */
/*0250*/ HFMA2.MMA R26, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff1a7435 */
/* 0x000fe200000001ff */
/*0260*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0270*/ IADD3 R9, R2, -R5, RZ ; /* 0x8000000502097210 */
/* 0x000fe40007ffe0ff */
/*0280*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f04270 */
/*0290*/ MOV R18, RZ ; /* 0x000000ff00127202 */
/* 0x000fc80000000f00 */
/*02a0*/ IMAD.WIDE R26, R5, R26, c[0x0][0x168] ; /* 0x00005a00051a7625 */
/* 0x000fce00078e021a */
/*02b0*/ @!P0 BRA 0xa50 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*02c0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*02d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*02e0*/ @!P1 BRA 0x790 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*02f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0300*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0310*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x0000a2000c1e1900 */
/*0320*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0330*/ IMAD.WIDE R12, R9, 0x4, R12 ; /* 0x00000004090c7825 */
/* 0x000fca00078e020c */
/*0340*/ LDG.E R28, [R12.64] ; /* 0x000000040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0350*/ IMAD.WIDE R16, R4, 0x4, R26 ; /* 0x0000000404107825 */
/* 0x000fc600078e021a */
/*0360*/ LDG.E R23, [R12.64+0x4] ; /* 0x000004040c177981 */
/* 0x000ee6000c1e1900 */
/*0370*/ IMAD.WIDE R10, R4.reuse, 0x4, R16 ; /* 0x00000004040a7825 */
/* 0x040fe200078e0210 */
/*0380*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x0002e8000c1e1900 */
/*0390*/ LDG.E R25, [R10.64] ; /* 0x000000040a197981 */
/* 0x000968000c1e1900 */
/*03a0*/ LDG.E R24, [R12.64+0x8] ; /* 0x000008040c187981 */
/* 0x000f68000c1e1900 */
/*03b0*/ LDG.E R14, [R12.64+0xc] ; /* 0x00000c040c0e7981 */
/* 0x000f62000c1e1900 */
/*03c0*/ IMAD.WIDE R10, R4, 0x4, R10 ; /* 0x00000004040a7825 */
/* 0x010fc600078e020a */
/*03d0*/ LDG.E R26, [R12.64+0x10] ; /* 0x000010040c1a7981 */
/* 0x001f28000c1e1900 */
/*03e0*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x000122000c1e1900 */
/*03f0*/ IMAD.WIDE R20, R4, 0x4, R10 ; /* 0x0000000404147825 */
/* 0x000fca00078e020a */
/*0400*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000122000c1e1900 */
/*0410*/ IMAD.WIDE R16, R4, 0x4, R20 ; /* 0x0000000404107825 */
/* 0x002fc600078e0214 */
/*0420*/ LDG.E R10, [R12.64+0x18] ; /* 0x000018040c0a7981 */
/* 0x001f28000c1e1900 */
/*0430*/ LDG.E R21, [R12.64+0x1c] ; /* 0x00001c040c157981 */
/* 0x000f22000c1e1900 */
/*0440*/ IMAD R28, R19, R28, R18 ; /* 0x0000001c131c7224 */
/* 0x004fc600078e0212 */
/*0450*/ LDG.E R18, [R12.64+0x14] ; /* 0x000014040c127981 */
/* 0x000ea8000c1e1900 */
/*0460*/ LDG.E R19, [R16.64] ; /* 0x0000000410137981 */
/* 0x0000a2000c1e1900 */
/*0470*/ IMAD R28, R22, R23, R28 ; /* 0x00000017161c7224 */
/* 0x008fe400078e021c */
/*0480*/ IMAD.WIDE R16, R4, 0x4, R16 ; /* 0x0000000404107825 */
/* 0x001fca00078e0210 */
/*0490*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000ae2000c1e1900 */
/*04a0*/ IMAD.WIDE R22, R4, 0x4, R16 ; /* 0x0000000404167825 */
/* 0x000fca00078e0210 */
/*04b0*/ LDG.E R20, [R22.64] ; /* 0x0000000416147981 */
/* 0x0000e2000c1e1900 */
/*04c0*/ IMAD R16, R25, R24, R28 ; /* 0x0000001819107224 */
/* 0x020fe400078e021c */
/*04d0*/ IMAD.WIDE R24, R4.reuse, 0x4, R22 ; /* 0x0000000404187825 */
/* 0x040fe200078e0216 */
/*04e0*/ LDG.E R28, [R12.64+0x20] ; /* 0x000020040c1c7981 */
/* 0x000f68000c1e1900 */
/*04f0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x000362000c1e1900 */
/*0500*/ IMAD R16, R15, R14, R16 ; /* 0x0000000e0f107224 */
/* 0x010fe400078e0210 */
/*0510*/ IMAD.WIDE R14, R4, 0x4, R24 ; /* 0x00000004040e7825 */
/* 0x000fe200078e0218 */
/*0520*/ LDG.E R23, [R12.64+0x24] ; /* 0x000024040c177981 */
/* 0x001f26000c1e1900 */
/*0530*/ IMAD R26, R27, R26, R16 ; /* 0x0000001a1b1a7224 */
/* 0x000fc400078e0210 */
/*0540*/ IMAD.WIDE R16, R4, 0x4, R14 ; /* 0x0000000404107825 */
/* 0x000fe200078e020e */
/*0550*/ LDG.E R27, [R12.64+0x28] ; /* 0x000028040c1b7981 */
/* 0x000f28000c1e1900 */
/*0560*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000128000c1e1900 */
/*0570*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x000328000c1e1900 */
/*0580*/ LDG.E R15, [R12.64+0x30] ; /* 0x000030040c0f7981 */
/* 0x001f22000c1e1900 */
/*0590*/ IMAD R26, R19, R18, R26 ; /* 0x00000012131a7224 */
/* 0x004fc400078e021a */
/*05a0*/ IMAD.WIDE R18, R4, 0x4, R16 ; /* 0x0000000404127825 */
/* 0x000fc800078e0210 */
/*05b0*/ IMAD R26, R11, R10, R26 ; /* 0x0000000a0b1a7224 */
/* 0x008fe400078e021a */
/*05c0*/ IMAD.WIDE R10, R4, 0x4, R18 ; /* 0x00000004040a7825 */
/* 0x000fe400078e0212 */
/*05d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a4000c1e1900 */
/*05e0*/ IMAD R24, R20, R21, R26 ; /* 0x0000001514187224 */
/* 0x002fe400078e021a */
/*05f0*/ IMAD.WIDE R20, R4, 0x4, R10 ; /* 0x0000000404147825 */
/* 0x000fe200078e020a */
/*0600*/ LDG.E R26, [R12.64+0x2c] ; /* 0x00002c040c1a7981 */
/* 0x000ea8000c1e1900 */
/*0610*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0002e2000c1e1900 */
/*0620*/ IMAD R28, R29, R28, R24 ; /* 0x0000001c1d1c7224 */
/* 0x020fc600078e0218 */
/*0630*/ LDG.E R19, [R12.64+0x38] ; /* 0x000038040c137981 */
/* 0x001f62000c1e1900 */
/*0640*/ IMAD.WIDE R24, R4, 0x4, R20 ; /* 0x0000000404187825 */
/* 0x000fc600078e0214 */
/*0650*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000168000c1e1900 */
/*0660*/ LDG.E R11, [R12.64+0x34] ; /* 0x000034040c0b7981 */
/* 0x002f62000c1e1900 */
/*0670*/ IMAD.WIDE R16, R4, 0x4, R24 ; /* 0x0000000404107825 */
/* 0x000fc600078e0218 */
/*0680*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x000368000c1e1900 */
/*0690*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x001f68000c1e1900 */
/*06a0*/ LDG.E R24, [R12.64+0x3c] ; /* 0x00003c040c187981 */
/* 0x002f62000c1e1900 */
/*06b0*/ IMAD R14, R14, R23, R28 ; /* 0x000000170e0e7224 */
/* 0x010fe200078e021c */
/*06c0*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fc60007ffe0ff */
/*06d0*/ IMAD R27, R22, R27, R14 ; /* 0x0000001b161b7224 */
/* 0x000fe200078e020e */
/*06e0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe20003f24270 */
/*06f0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0700*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fc60007ffe0ff */
/*0710*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0720*/ IMAD R18, R18, R26, R27 ; /* 0x0000001a12127224 */
/* 0x004fc800078e021b */
/*0730*/ IMAD R10, R10, R15, R18 ; /* 0x0000000f0a0a7224 */
/* 0x008fe400078e0212 */
/*0740*/ IMAD.WIDE R26, R4, 0x4, R16 ; /* 0x00000004041a7825 */
/* 0x000fc800078e0210 */
/*0750*/ IMAD R10, R20, R11, R10 ; /* 0x0000000b140a7224 */
/* 0x020fc800078e020a */
/*0760*/ IMAD R10, R29, R19, R10 ; /* 0x000000131d0a7224 */
/* 0x000fc800078e020a */
/*0770*/ IMAD R18, R21, R24, R10 ; /* 0x0000001815127224 */
/* 0x000fe200078e020a */
/*0780*/ @P1 BRA 0x300 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0790*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*07a0*/ @!P1 BRA 0xa30 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*07b0*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*07c0*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x000ea2000c1e1900 */
/*07d0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fca0008000f00 */
/*07e0*/ IMAD.WIDE R10, R9, 0x4, R10 ; /* 0x00000004090a7825 */
/* 0x000fca00078e020a */
/*07f0*/ LDG.E R24, [R10.64] ; /* 0x000000040a187981 */
/* 0x000ea2000c1e1900 */
/*0800*/ IMAD.WIDE R22, R4, 0x4, R26 ; /* 0x0000000404167825 */
/* 0x000fc600078e021a */
/*0810*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0820*/ IMAD.WIDE R14, R4.reuse, 0x4, R22 ; /* 0x00000004040e7825 */
/* 0x040fe200078e0216 */
/*0830*/ LDG.E R29, [R10.64+0x8] ; /* 0x000008040a1d7981 */
/* 0x000f28000c1e1900 */
/*0840*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x0000e2000c1e1900 */
/*0850*/ IMAD.WIDE R16, R4, 0x4, R14 ; /* 0x0000000404107825 */
/* 0x000fc600078e020e */
/*0860*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000326000c1e1900 */
/*0870*/ IMAD.WIDE R12, R4.reuse, 0x4, R16 ; /* 0x00000004040c7825 */
/* 0x040fe200078e0210 */
/*0880*/ LDG.E R28, [R10.64+0xc] ; /* 0x00000c040a1c7981 */
/* 0x000f68000c1e1900 */
/*0890*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000362000c1e1900 */
/*08a0*/ IMAD.WIDE R20, R4, 0x4, R12 ; /* 0x0000000404147825 */
/* 0x000fc600078e020c */
/*08b0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000328000c1e1900 */
/*08c0*/ LDG.E R23, [R10.64+0x14] ; /* 0x000014040a177981 */
/* 0x001f68000c1e1900 */
/*08d0*/ LDG.E R16, [R10.64+0x18] ; /* 0x000018040a107981 */
/* 0x002f68000c1e1900 */
/*08e0*/ LDG.E R13, [R10.64+0x10] ; /* 0x000010040a0d7981 */
/* 0x000f62000c1e1900 */
/*08f0*/ IMAD R24, R19, R24, R18 ; /* 0x0000001813187224 */
/* 0x004fc400078e0212 */
/*0900*/ IMAD.WIDE R18, R4.reuse, 0x4, R20 ; /* 0x0000000404127825 */
/* 0x040fe400078e0214 */
/*0910*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ea8000c1e1900 */
/*0920*/ IMAD.WIDE R26, R4, 0x4, R18 ; /* 0x00000004041a7825 */
/* 0x000fe200078e0212 */
/*0930*/ LDG.E R15, [R18.64] ; /* 0x00000004120f7981 */
/* 0x0000a8000c1e1900 */
/*0940*/ LDG.E R19, [R10.64+0x1c] ; /* 0x00001c040a137981 */
/* 0x001ea8000c1e1900 */
/*0950*/ LDG.E R18, [R26.64] ; /* 0x000000041a127981 */
/* 0x0000a2000c1e1900 */
/*0960*/ IMAD R22, R22, R25, R24 ; /* 0x0000001916167224 */
/* 0x008fc800078e0218 */
/*0970*/ IMAD R14, R14, R29, R22 ; /* 0x0000001d0e0e7224 */
/* 0x010fc800078e0216 */
/*0980*/ IMAD R14, R17, R28, R14 ; /* 0x0000001c110e7224 */
/* 0x020fc800078e020e */
/*0990*/ IMAD R12, R12, R13, R14 ; /* 0x0000000d0c0c7224 */
/* 0x000fe200078e020e */
/*09a0*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*09b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*09c0*/ IMAD.WIDE R26, R4, 0x4, R26 ; /* 0x00000004041a7825 */
/* 0x001fe200078e021a */
/*09d0*/ IADD3 R6, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fe40007ffe0ff */
/*09e0*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*09f0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a00*/ IMAD R12, R20, R23, R12 ; /* 0x00000017140c7224 */
/* 0x004fc800078e020c */
/*0a10*/ IMAD R12, R15, R16, R12 ; /* 0x000000100f0c7224 */
/* 0x000fc800078e020c */
/*0a20*/ IMAD R18, R18, R19, R12 ; /* 0x0000001312127224 */
/* 0x000fe400078e020c */
/*0a30*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0a40*/ @!P0 BRA 0xbe0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0a50*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*0a60*/ IMAD.WIDE R12, R4, 0x4, R26 ; /* 0x00000004040c7825 */
/* 0x000fe200078e021a */
/*0a70*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*0a80*/ LDG.E R27, [R26.64] ; /* 0x000000041a1b7981 */
/* 0x000ea8000c1e1900 */
/*0a90*/ IMAD.WIDE R10, R9, 0x4, R10 ; /* 0x00000004090a7825 */
/* 0x000fc800078e020a */
/*0aa0*/ IMAD.WIDE R14, R4.reuse, 0x4, R12 ; /* 0x00000004040e7825 */
/* 0x040fe200078e020c */
/*0ab0*/ LDG.E R19, [R10.64] ; /* 0x000000040a137981 */
/* 0x000ea8000c1e1900 */
/*0ac0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee2000c1e1900 */
/*0ad0*/ IMAD.WIDE R16, R4, 0x4, R14 ; /* 0x0000000404107825 */
/* 0x000fc600078e020e */
/*0ae0*/ LDG.E R20, [R10.64+0x4] ; /* 0x000004040a147981 */
/* 0x000ee8000c1e1900 */
/*0af0*/ LDG.E R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x000f28000c1e1900 */
/*0b00*/ LDG.E R21, [R10.64+0x8] ; /* 0x000008040a157981 */
/* 0x000f28000c1e1900 */
/*0b10*/ LDG.E R23, [R10.64+0xc] ; /* 0x00000c040a177981 */
/* 0x000f68000c1e1900 */
/*0b20*/ LDG.E R24, [R16.64] ; /* 0x0000000410187981 */
/* 0x000f62000c1e1900 */
/*0b30*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fc80007ffe0ff */
/*0b40*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0b50*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0b60*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fc60007ffe0ff */
/*0b70*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0b80*/ IMAD R19, R27, R19, R18 ; /* 0x000000131b137224 */
/* 0x004fc800078e0212 */
/*0b90*/ IMAD R19, R12, R20, R19 ; /* 0x000000140c137224 */
/* 0x008fe400078e0213 */
/*0ba0*/ IMAD.WIDE R26, R4, 0x4, R16 ; /* 0x00000004041a7825 */
/* 0x000fc800078e0210 */
/*0bb0*/ IMAD R19, R22, R21, R19 ; /* 0x0000001516137224 */
/* 0x010fc800078e0213 */
/*0bc0*/ IMAD R18, R24, R23, R19 ; /* 0x0000001718127224 */
/* 0x020fe200078e0213 */
/*0bd0*/ @P0 BRA 0xa50 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0be0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*0bf0*/ @!P0 BRA 0xd00 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0c00*/ IADD3 R3, R3, R6, RZ ; /* 0x0000000603037210 */
/* 0x000fe20007ffe0ff */
/*0c10*/ HFMA2.MMA R10, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0a7435 */
/* 0x000fc800000001ff */
/*0c20*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x000fca00078e0203 */
/*0c30*/ IADD3 R0, -R5, R0, RZ ; /* 0x0000000005007210 */
/* 0x000fe20007ffe1ff */
/*0c40*/ IMAD R5, R6, c[0x0][0x178], R5 ; /* 0x00005e0006057a24 */
/* 0x000fc800078e0205 */
/*0c50*/ IMAD.WIDE R8, R0, R10, c[0x0][0x160] ; /* 0x0000580000087625 */
/* 0x000fc800078e020a */
/*0c60*/ IMAD.WIDE R10, R5, R10, c[0x0][0x168] ; /* 0x00005a00050a7625 */
/* 0x000fca00078e020a */
/*0c70*/ LDG.E R3, [R10.64] ; /* 0x000000040a037981 */
/* 0x0000a8000c1e1900 */
/*0c80*/ LDG.E R0, [R8.64] ; /* 0x0000000408007981 */
/* 0x0002a2000c1e1900 */
/*0c90*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fc80007ffe0ff */
/*0ca0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*0cb0*/ IMAD.WIDE R10, R4, 0x4, R10 ; /* 0x00000004040a7825 */
/* 0x001fe200078e020a */
/*0cc0*/ IADD3 R8, P1, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x002fc80007f3e0ff */
/*0cd0*/ IADD3.X R9, RZ, R9, RZ, P1, !PT ; /* 0x00000009ff097210 */
/* 0x000fe20000ffe4ff */
/*0ce0*/ IMAD R18, R3, R0, R18 ; /* 0x0000000003127224 */
/* 0x004fcc00078e0212 */
/*0cf0*/ @P0 BRA 0xc70 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0d00*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0d10*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0d20*/ STG.E [R2.64], R18 ; /* 0x0000001202007986 */
/* 0x000fe2000c101904 */
/*0d30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d40*/ BRA 0xd40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <math.h>
#define N 8
#define THREAD_PER_BLOCK 2
__global__ void multiply(int * in1, int * in2, int * out, int size) {
int index = threadIdx.x + blockIdx.x * blockDim.x;
int startrow = (index / size) * size;
int startcol = index % size;
int i;
int sum = 0;
for(i = 0; i < size; ++i) {
sum += in1[startrow + i] * in2[startcol + i * size];
}
out[index] = sum;
}
int main()
{
int * in1, * in2, * out;
int * d_in1, * d_in2, * d_out;
int size = N * N * sizeof(int);
int i;
cudaMalloc((void**)&d_in1, size);
cudaMalloc((void**)&d_in2, size);
cudaMalloc((void**)&d_out, size);
in1 = (int *)malloc(size);
in2 = (int *)malloc(size);
out = (int *)malloc(size);
for(i = 0; i<N*N; ++i)
{
in1[i] = i%N;
in2[i] = i%N -1;
}
cudaMemcpy(d_in1, in1, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_in2, in2, size, cudaMemcpyHostToDevice);
multiply<<< N*N/THREAD_PER_BLOCK, THREAD_PER_BLOCK >>>(d_in1, d_in2, d_out, N);
cudaMemcpy(out, d_out, size, cudaMemcpyDeviceToHost);
for(i=0; i<N*N; ++i)
{
printf("%2d ", in1[i]);
if((i+1)%N == 0) {
printf("\n");
}
}
printf("--------\n");
for(i=0; i<N*N; ++i)
{
printf("%2d ", in2[i]);
if((i+1)%N == 0) {
printf("\n");
}
}
printf("--------\n");
for(i=0; i<N*N; ++i)
{
printf("%2d ", out[i]);
if((i+1)%N == 0) {
printf("\n");
}
}
free(in1); free(in2); free(out);
cudaFree(d_in1); cudaFree(d_in2);
cudaFree(d_out);
return 0;
} | .file "tmpxft_0002c2e1_00000000-6_matrix_multiplication.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z8multiplyPiS_S_iPiS_S_i
.type _Z32__device_stub__Z8multiplyPiS_S_iPiS_S_i, @function
_Z32__device_stub__Z8multiplyPiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8multiplyPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z8multiplyPiS_S_iPiS_S_i, .-_Z32__device_stub__Z8multiplyPiS_S_iPiS_S_i
.globl _Z8multiplyPiS_S_i
.type _Z8multiplyPiS_S_i, @function
_Z8multiplyPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8multiplyPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8multiplyPiS_S_i, .-_Z8multiplyPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%2d "
.LC1:
.string "\n"
.LC2:
.string "--------\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
movl $256, %edi
call malloc@PLT
movq %rax, %rbp
movl $256, %edi
call malloc@PLT
movq %rax, %rbx
movl $256, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %edx
.L12:
movl %edx, %ecx
sarl $31, %ecx
shrl $29, %ecx
leal (%rcx,%rdx), %eax
andl $7, %eax
subl %ecx, %eax
movl %eax, 0(%rbp,%rdx,4)
subl $1, %eax
movl %eax, (%rbx,%rdx,4)
addq $1, %rdx
cmpq $64, %rdx
jne .L12
movl $1, %ecx
movl $256, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $256, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, 44(%rsp)
movl $1, 48(%rsp)
movl $32, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L13:
movl $2, %ecx
movl $256, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $1, %r13d
leaq .LC0(%rip), %r14
leaq .LC1(%rip), %r15
jmp .L15
.L26:
movl $8, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z8multiplyPiS_S_iPiS_S_i
jmp .L13
.L14:
addq $1, %r13
cmpq $65, %r13
je .L27
.L15:
movl -4(%rbp,%r13,4), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testb $7, %r13b
jne .L14
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L14
.L27:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %r13d
leaq .LC0(%rip), %r14
leaq .LC1(%rip), %r15
jmp .L17
.L16:
addq $1, %r13
cmpq $65, %r13
je .L28
.L17:
movl -4(%rbx,%r13,4), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testb $7, %r13b
jne .L16
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L16
.L28:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %r13d
leaq .LC0(%rip), %r14
leaq .LC1(%rip), %r15
jmp .L19
.L18:
addq $1, %r13
cmpq $65, %r13
je .L29
.L19:
movl -4(%r12,%r13,4), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testb $7, %r13b
jne .L18
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L18
.L29:
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z8multiplyPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z8multiplyPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <math.h>
#define N 8
#define THREAD_PER_BLOCK 2
__global__ void multiply(int * in1, int * in2, int * out, int size) {
int index = threadIdx.x + blockIdx.x * blockDim.x;
int startrow = (index / size) * size;
int startcol = index % size;
int i;
int sum = 0;
for(i = 0; i < size; ++i) {
sum += in1[startrow + i] * in2[startcol + i * size];
}
out[index] = sum;
}
int main()
{
int * in1, * in2, * out;
int * d_in1, * d_in2, * d_out;
int size = N * N * sizeof(int);
int i;
cudaMalloc((void**)&d_in1, size);
cudaMalloc((void**)&d_in2, size);
cudaMalloc((void**)&d_out, size);
in1 = (int *)malloc(size);
in2 = (int *)malloc(size);
out = (int *)malloc(size);
for(i = 0; i<N*N; ++i)
{
in1[i] = i%N;
in2[i] = i%N -1;
}
cudaMemcpy(d_in1, in1, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_in2, in2, size, cudaMemcpyHostToDevice);
multiply<<< N*N/THREAD_PER_BLOCK, THREAD_PER_BLOCK >>>(d_in1, d_in2, d_out, N);
cudaMemcpy(out, d_out, size, cudaMemcpyDeviceToHost);
for(i=0; i<N*N; ++i)
{
printf("%2d ", in1[i]);
if((i+1)%N == 0) {
printf("\n");
}
}
printf("--------\n");
for(i=0; i<N*N; ++i)
{
printf("%2d ", in2[i]);
if((i+1)%N == 0) {
printf("\n");
}
}
printf("--------\n");
for(i=0; i<N*N; ++i)
{
printf("%2d ", out[i]);
if((i+1)%N == 0) {
printf("\n");
}
}
free(in1); free(in2); free(out);
cudaFree(d_in1); cudaFree(d_in2);
cudaFree(d_out);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#define N 8
#define THREAD_PER_BLOCK 2
__global__ void multiply(int * in1, int * in2, int * out, int size) {
int index = threadIdx.x + blockIdx.x * blockDim.x;
int startrow = (index / size) * size;
int startcol = index % size;
int i;
int sum = 0;
for(i = 0; i < size; ++i) {
sum += in1[startrow + i] * in2[startcol + i * size];
}
out[index] = sum;
}
int main()
{
int * in1, * in2, * out;
int * d_in1, * d_in2, * d_out;
int size = N * N * sizeof(int);
int i;
hipMalloc((void**)&d_in1, size);
hipMalloc((void**)&d_in2, size);
hipMalloc((void**)&d_out, size);
in1 = (int *)malloc(size);
in2 = (int *)malloc(size);
out = (int *)malloc(size);
for(i = 0; i<N*N; ++i)
{
in1[i] = i%N;
in2[i] = i%N -1;
}
hipMemcpy(d_in1, in1, size, hipMemcpyHostToDevice);
hipMemcpy(d_in2, in2, size, hipMemcpyHostToDevice);
multiply<<< N*N/THREAD_PER_BLOCK, THREAD_PER_BLOCK >>>(d_in1, d_in2, d_out, N);
hipMemcpy(out, d_out, size, hipMemcpyDeviceToHost);
for(i=0; i<N*N; ++i)
{
printf("%2d ", in1[i]);
if((i+1)%N == 0) {
printf("\n");
}
}
printf("--------\n");
for(i=0; i<N*N; ++i)
{
printf("%2d ", in2[i]);
if((i+1)%N == 0) {
printf("\n");
}
}
printf("--------\n");
for(i=0; i<N*N; ++i)
{
printf("%2d ", out[i]);
if((i+1)%N == 0) {
printf("\n");
}
}
free(in1); free(in2); free(out);
hipFree(d_in1); hipFree(d_in2);
hipFree(d_out);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#define N 8
#define THREAD_PER_BLOCK 2
__global__ void multiply(int * in1, int * in2, int * out, int size) {
int index = threadIdx.x + blockIdx.x * blockDim.x;
int startrow = (index / size) * size;
int startcol = index % size;
int i;
int sum = 0;
for(i = 0; i < size; ++i) {
sum += in1[startrow + i] * in2[startcol + i * size];
}
out[index] = sum;
}
int main()
{
int * in1, * in2, * out;
int * d_in1, * d_in2, * d_out;
int size = N * N * sizeof(int);
int i;
hipMalloc((void**)&d_in1, size);
hipMalloc((void**)&d_in2, size);
hipMalloc((void**)&d_out, size);
in1 = (int *)malloc(size);
in2 = (int *)malloc(size);
out = (int *)malloc(size);
for(i = 0; i<N*N; ++i)
{
in1[i] = i%N;
in2[i] = i%N -1;
}
hipMemcpy(d_in1, in1, size, hipMemcpyHostToDevice);
hipMemcpy(d_in2, in2, size, hipMemcpyHostToDevice);
multiply<<< N*N/THREAD_PER_BLOCK, THREAD_PER_BLOCK >>>(d_in1, d_in2, d_out, N);
hipMemcpy(out, d_out, size, hipMemcpyDeviceToHost);
for(i=0; i<N*N; ++i)
{
printf("%2d ", in1[i]);
if((i+1)%N == 0) {
printf("\n");
}
}
printf("--------\n");
for(i=0; i<N*N; ++i)
{
printf("%2d ", in2[i]);
if((i+1)%N == 0) {
printf("\n");
}
}
printf("--------\n");
for(i=0; i<N*N; ++i)
{
printf("%2d ", out[i]);
if((i+1)%N == 0) {
printf("\n");
}
}
free(in1); free(in2); free(out);
hipFree(d_in1); hipFree(d_in2);
hipFree(d_out);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8multiplyPiS_S_i
.globl _Z8multiplyPiS_S_i
.p2align 8
.type _Z8multiplyPiS_S_i,@function
_Z8multiplyPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_cmp_lt_i32 s2, 1
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, 0
s_cbranch_scc1 .LBB0_3
s_ashr_i32 s4, s2, 31
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v4, 31, v1
s_add_i32 s5, s2, s4
s_xor_b32 s4, s5, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, v1, v4
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s5, 0, s4
v_xor_b32_e32 v5, v3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s5, v0
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
v_mad_u64_u32 v[2:3], null, v5, v0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v3, s4
v_sub_nc_u32_e32 v0, v5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s4, v0
v_cmp_le_u32_e32 vcc_lo, s4, v0
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s4, v0
v_cmp_le_u32_e32 vcc_lo, s4, v0
s_load_b128 s[4:7], s[0:1], 0x0
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v4
v_sub_nc_u32_e32 v2, v0, v4
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_2)
v_sub_nc_u32_e32 v4, v1, v2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v5, s3, v4
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s3, s3, 1
s_cmp_lg_u32 s2, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[7:8], 2, v[2:3]
v_add_nc_u32_e32 v2, s2, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b32 v3, v[7:8], off
global_load_b32 v7, v[5:6], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[5:6], null, v3, v7, v[0:1]
v_mov_b32_e32 v0, v5
s_cbranch_scc1 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v0, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8multiplyPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8multiplyPiS_S_i, .Lfunc_end0-_Z8multiplyPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8multiplyPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8multiplyPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#define N 8
#define THREAD_PER_BLOCK 2
__global__ void multiply(int * in1, int * in2, int * out, int size) {
int index = threadIdx.x + blockIdx.x * blockDim.x;
int startrow = (index / size) * size;
int startcol = index % size;
int i;
int sum = 0;
for(i = 0; i < size; ++i) {
sum += in1[startrow + i] * in2[startcol + i * size];
}
out[index] = sum;
}
int main()
{
int * in1, * in2, * out;
int * d_in1, * d_in2, * d_out;
int size = N * N * sizeof(int);
int i;
hipMalloc((void**)&d_in1, size);
hipMalloc((void**)&d_in2, size);
hipMalloc((void**)&d_out, size);
in1 = (int *)malloc(size);
in2 = (int *)malloc(size);
out = (int *)malloc(size);
for(i = 0; i<N*N; ++i)
{
in1[i] = i%N;
in2[i] = i%N -1;
}
hipMemcpy(d_in1, in1, size, hipMemcpyHostToDevice);
hipMemcpy(d_in2, in2, size, hipMemcpyHostToDevice);
multiply<<< N*N/THREAD_PER_BLOCK, THREAD_PER_BLOCK >>>(d_in1, d_in2, d_out, N);
hipMemcpy(out, d_out, size, hipMemcpyDeviceToHost);
for(i=0; i<N*N; ++i)
{
printf("%2d ", in1[i]);
if((i+1)%N == 0) {
printf("\n");
}
}
printf("--------\n");
for(i=0; i<N*N; ++i)
{
printf("%2d ", in2[i]);
if((i+1)%N == 0) {
printf("\n");
}
}
printf("--------\n");
for(i=0; i<N*N; ++i)
{
printf("%2d ", out[i]);
if((i+1)%N == 0) {
printf("\n");
}
}
free(in1); free(in2); free(out);
hipFree(d_in1); hipFree(d_in2);
hipFree(d_out);
return 0;
} | .text
.file "matrix_multiplication.hip"
.globl _Z23__device_stub__multiplyPiS_S_i # -- Begin function _Z23__device_stub__multiplyPiS_S_i
.p2align 4, 0x90
.type _Z23__device_stub__multiplyPiS_S_i,@function
_Z23__device_stub__multiplyPiS_S_i: # @_Z23__device_stub__multiplyPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8multiplyPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__multiplyPiS_S_i, .Lfunc_end0-_Z23__device_stub__multiplyPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
leaq 16(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
leaq 8(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %rbx
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %r14
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, %ecx
andl $7, %ecx
movl %ecx, (%rbx,%rax,4)
decl %ecx
movl %ecx, (%r14,%rax,4)
incq %rax
cmpq $64, %rax
jne .LBB1_1
# %bb.2:
movq 24(%rsp), %rdi
movl $256, %edx # imm = 0x100
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $256, %edx # imm = 0x100
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967298, %rdx # imm = 0x100000002
leaq 30(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $8, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z8multiplyPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $256, %edx # imm = 0x100
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $1, %r12d
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_5 Depth=1
incq %r12
cmpq $65, %r12
je .LBB1_8
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl -4(%rbx,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
testb $7, %r12b
jne .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB1_7
.LBB1_8:
movl $.Lstr.1, %edi
callq puts@PLT
movl $1, %r12d
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_11: # in Loop: Header=BB1_9 Depth=1
incq %r12
cmpq $65, %r12
je .LBB1_12
.LBB1_9: # =>This Inner Loop Header: Depth=1
movl -4(%r14,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
testb $7, %r12b
jne .LBB1_11
# %bb.10: # in Loop: Header=BB1_9 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB1_11
.LBB1_12:
movl $.Lstr.1, %edi
callq puts@PLT
movl $1, %r12d
jmp .LBB1_13
.p2align 4, 0x90
.LBB1_15: # in Loop: Header=BB1_13 Depth=1
incq %r12
cmpq $65, %r12
je .LBB1_16
.LBB1_13: # =>This Inner Loop Header: Depth=1
movl -4(%r15,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
testb $7, %r12b
jne .LBB1_15
# %bb.14: # in Loop: Header=BB1_13 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB1_15
.LBB1_16:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8multiplyPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8multiplyPiS_S_i,@object # @_Z8multiplyPiS_S_i
.section .rodata,"a",@progbits
.globl _Z8multiplyPiS_S_i
.p2align 3, 0x0
_Z8multiplyPiS_S_i:
.quad _Z23__device_stub__multiplyPiS_S_i
.size _Z8multiplyPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%2d "
.size .L.str, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8multiplyPiS_S_i"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "--------"
.size .Lstr.1, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__multiplyPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8multiplyPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8multiplyPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IABS R8, c[0x0][0x178] ; /* 0x00005e0000087a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R18, -RZ, RZ, 0, 0 ; /* 0x00000000ff127435 */
/* 0x000fe200000001ff */
/*0050*/ I2F.RP R6, R8 ; /* 0x0000000800067306 */
/* 0x000e620000209400 */
/*0060*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e2e0000002100 */
/*0070*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x002e620000001000 */
/*0080*/ IMAD R2, R0, c[0x0][0x0], R3 ; /* 0x0000000000027a24 */
/* 0x001fca00078e0203 */
/*0090*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f26270 */
/*00a0*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x002fe40007ffe0ff */
/*00b0*/ IABS R6, R2 ; /* 0x0000000200067213 */
/* 0x000fe40000000000 */
/*00c0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*00d0*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*00e0*/ IADD3 R7, RZ, -R5, RZ ; /* 0x80000005ff077210 */
/* 0x002fca0007ffe0ff */
/*00f0*/ IMAD R7, R7, R8, RZ ; /* 0x0000000807077224 */
/* 0x000fc800078e02ff */
/*0100*/ IMAD.HI.U32 R5, R5, R7, R4 ; /* 0x0000000705057227 */
/* 0x000fe200078e0004 */
/*0110*/ MOV R4, c[0x0][0x178] ; /* 0x00005e0000047a02 */
/* 0x000fca0000000f00 */
/*0120*/ IMAD.HI.U32 R5, R5, R6, RZ ; /* 0x0000000605057227 */
/* 0x000fca00078e00ff */
/*0130*/ IADD3 R5, -R5, RZ, RZ ; /* 0x000000ff05057210 */
/* 0x000fca0007ffe1ff */
/*0140*/ IMAD R5, R8, R5, R6 ; /* 0x0000000508057224 */
/* 0x000fca00078e0206 */
/*0150*/ ISETP.GT.U32.AND P0, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fda0003f04070 */
/*0160*/ @!P0 IADD3 R5, R5, -R8, RZ ; /* 0x8000000805058210 */
/* 0x000fe40007ffe0ff */
/*0170*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe40003f05270 */
/*0180*/ ISETP.GT.U32.AND P2, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fda0003f44070 */
/*0190*/ @!P2 IADD3 R5, R5, -R8, RZ ; /* 0x800000080505a210 */
/* 0x000fe40007ffe0ff */
/*01a0*/ ISETP.GE.AND P2, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe40003f46270 */
/*01b0*/ @!P1 IADD3 R5, -R5, RZ, RZ ; /* 0x000000ff05059210 */
/* 0x000fe40007ffe1ff */
/*01c0*/ @!P0 LOP3.LUT R5, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff058a12 */
/* 0x000fd200078e33ff */
/*01d0*/ @!P2 BRA 0xd00 ; /* 0x00000b200000a947 */
/* 0x000fea0003800000 */
/*01e0*/ IADD3 R6, R4.reuse, -0x1, RZ ; /* 0xffffffff04067810 */
/* 0x040fe40007ffe0ff */
/*01f0*/ LOP3.LUT R7, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304077812 */
/* 0x000fe400078ec0ff */
/*0200*/ ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f06070 */
/*0210*/ MOV R18, RZ ; /* 0x000000ff00127202 */
/* 0x000fe40000000f00 */
/*0220*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x000fd20000000f00 */
/*0230*/ @!P0 BRA 0xbe0 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0240*/ IADD3 R8, -R7, c[0x0][0x178], RZ ; /* 0x00005e0007087a10 */
/* 0x000fe20007ffe1ff */
/*0250*/ HFMA2.MMA R26, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff1a7435 */
/* 0x000fe200000001ff */
/*0260*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0270*/ IADD3 R9, R2, -R5, RZ ; /* 0x8000000502097210 */
/* 0x000fe40007ffe0ff */
/*0280*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f04270 */
/*0290*/ MOV R18, RZ ; /* 0x000000ff00127202 */
/* 0x000fc80000000f00 */
/*02a0*/ IMAD.WIDE R26, R5, R26, c[0x0][0x168] ; /* 0x00005a00051a7625 */
/* 0x000fce00078e021a */
/*02b0*/ @!P0 BRA 0xa50 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*02c0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*02d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*02e0*/ @!P1 BRA 0x790 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*02f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0300*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0310*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x0000a2000c1e1900 */
/*0320*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0330*/ IMAD.WIDE R12, R9, 0x4, R12 ; /* 0x00000004090c7825 */
/* 0x000fca00078e020c */
/*0340*/ LDG.E R28, [R12.64] ; /* 0x000000040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0350*/ IMAD.WIDE R16, R4, 0x4, R26 ; /* 0x0000000404107825 */
/* 0x000fc600078e021a */
/*0360*/ LDG.E R23, [R12.64+0x4] ; /* 0x000004040c177981 */
/* 0x000ee6000c1e1900 */
/*0370*/ IMAD.WIDE R10, R4.reuse, 0x4, R16 ; /* 0x00000004040a7825 */
/* 0x040fe200078e0210 */
/*0380*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x0002e8000c1e1900 */
/*0390*/ LDG.E R25, [R10.64] ; /* 0x000000040a197981 */
/* 0x000968000c1e1900 */
/*03a0*/ LDG.E R24, [R12.64+0x8] ; /* 0x000008040c187981 */
/* 0x000f68000c1e1900 */
/*03b0*/ LDG.E R14, [R12.64+0xc] ; /* 0x00000c040c0e7981 */
/* 0x000f62000c1e1900 */
/*03c0*/ IMAD.WIDE R10, R4, 0x4, R10 ; /* 0x00000004040a7825 */
/* 0x010fc600078e020a */
/*03d0*/ LDG.E R26, [R12.64+0x10] ; /* 0x000010040c1a7981 */
/* 0x001f28000c1e1900 */
/*03e0*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x000122000c1e1900 */
/*03f0*/ IMAD.WIDE R20, R4, 0x4, R10 ; /* 0x0000000404147825 */
/* 0x000fca00078e020a */
/*0400*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000122000c1e1900 */
/*0410*/ IMAD.WIDE R16, R4, 0x4, R20 ; /* 0x0000000404107825 */
/* 0x002fc600078e0214 */
/*0420*/ LDG.E R10, [R12.64+0x18] ; /* 0x000018040c0a7981 */
/* 0x001f28000c1e1900 */
/*0430*/ LDG.E R21, [R12.64+0x1c] ; /* 0x00001c040c157981 */
/* 0x000f22000c1e1900 */
/*0440*/ IMAD R28, R19, R28, R18 ; /* 0x0000001c131c7224 */
/* 0x004fc600078e0212 */
/*0450*/ LDG.E R18, [R12.64+0x14] ; /* 0x000014040c127981 */
/* 0x000ea8000c1e1900 */
/*0460*/ LDG.E R19, [R16.64] ; /* 0x0000000410137981 */
/* 0x0000a2000c1e1900 */
/*0470*/ IMAD R28, R22, R23, R28 ; /* 0x00000017161c7224 */
/* 0x008fe400078e021c */
/*0480*/ IMAD.WIDE R16, R4, 0x4, R16 ; /* 0x0000000404107825 */
/* 0x001fca00078e0210 */
/*0490*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000ae2000c1e1900 */
/*04a0*/ IMAD.WIDE R22, R4, 0x4, R16 ; /* 0x0000000404167825 */
/* 0x000fca00078e0210 */
/*04b0*/ LDG.E R20, [R22.64] ; /* 0x0000000416147981 */
/* 0x0000e2000c1e1900 */
/*04c0*/ IMAD R16, R25, R24, R28 ; /* 0x0000001819107224 */
/* 0x020fe400078e021c */
/*04d0*/ IMAD.WIDE R24, R4.reuse, 0x4, R22 ; /* 0x0000000404187825 */
/* 0x040fe200078e0216 */
/*04e0*/ LDG.E R28, [R12.64+0x20] ; /* 0x000020040c1c7981 */
/* 0x000f68000c1e1900 */
/*04f0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x000362000c1e1900 */
/*0500*/ IMAD R16, R15, R14, R16 ; /* 0x0000000e0f107224 */
/* 0x010fe400078e0210 */
/*0510*/ IMAD.WIDE R14, R4, 0x4, R24 ; /* 0x00000004040e7825 */
/* 0x000fe200078e0218 */
/*0520*/ LDG.E R23, [R12.64+0x24] ; /* 0x000024040c177981 */
/* 0x001f26000c1e1900 */
/*0530*/ IMAD R26, R27, R26, R16 ; /* 0x0000001a1b1a7224 */
/* 0x000fc400078e0210 */
/*0540*/ IMAD.WIDE R16, R4, 0x4, R14 ; /* 0x0000000404107825 */
/* 0x000fe200078e020e */
/*0550*/ LDG.E R27, [R12.64+0x28] ; /* 0x000028040c1b7981 */
/* 0x000f28000c1e1900 */
/*0560*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000128000c1e1900 */
/*0570*/ LDG.E R22, [R16.64] ; /* 0x0000000410167981 */
/* 0x000328000c1e1900 */
/*0580*/ LDG.E R15, [R12.64+0x30] ; /* 0x000030040c0f7981 */
/* 0x001f22000c1e1900 */
/*0590*/ IMAD R26, R19, R18, R26 ; /* 0x00000012131a7224 */
/* 0x004fc400078e021a */
/*05a0*/ IMAD.WIDE R18, R4, 0x4, R16 ; /* 0x0000000404127825 */
/* 0x000fc800078e0210 */
/*05b0*/ IMAD R26, R11, R10, R26 ; /* 0x0000000a0b1a7224 */
/* 0x008fe400078e021a */
/*05c0*/ IMAD.WIDE R10, R4, 0x4, R18 ; /* 0x00000004040a7825 */
/* 0x000fe400078e0212 */
/*05d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a4000c1e1900 */
/*05e0*/ IMAD R24, R20, R21, R26 ; /* 0x0000001514187224 */
/* 0x002fe400078e021a */
/*05f0*/ IMAD.WIDE R20, R4, 0x4, R10 ; /* 0x0000000404147825 */
/* 0x000fe200078e020a */
/*0600*/ LDG.E R26, [R12.64+0x2c] ; /* 0x00002c040c1a7981 */
/* 0x000ea8000c1e1900 */
/*0610*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0002e2000c1e1900 */
/*0620*/ IMAD R28, R29, R28, R24 ; /* 0x0000001c1d1c7224 */
/* 0x020fc600078e0218 */
/*0630*/ LDG.E R19, [R12.64+0x38] ; /* 0x000038040c137981 */
/* 0x001f62000c1e1900 */
/*0640*/ IMAD.WIDE R24, R4, 0x4, R20 ; /* 0x0000000404187825 */
/* 0x000fc600078e0214 */
/*0650*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000168000c1e1900 */
/*0660*/ LDG.E R11, [R12.64+0x34] ; /* 0x000034040c0b7981 */
/* 0x002f62000c1e1900 */
/*0670*/ IMAD.WIDE R16, R4, 0x4, R24 ; /* 0x0000000404107825 */
/* 0x000fc600078e0218 */
/*0680*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x000368000c1e1900 */
/*0690*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x001f68000c1e1900 */
/*06a0*/ LDG.E R24, [R12.64+0x3c] ; /* 0x00003c040c187981 */
/* 0x002f62000c1e1900 */
/*06b0*/ IMAD R14, R14, R23, R28 ; /* 0x000000170e0e7224 */
/* 0x010fe200078e021c */
/*06c0*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fc60007ffe0ff */
/*06d0*/ IMAD R27, R22, R27, R14 ; /* 0x0000001b161b7224 */
/* 0x000fe200078e020e */
/*06e0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe20003f24270 */
/*06f0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0700*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fc60007ffe0ff */
/*0710*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0720*/ IMAD R18, R18, R26, R27 ; /* 0x0000001a12127224 */
/* 0x004fc800078e021b */
/*0730*/ IMAD R10, R10, R15, R18 ; /* 0x0000000f0a0a7224 */
/* 0x008fe400078e0212 */
/*0740*/ IMAD.WIDE R26, R4, 0x4, R16 ; /* 0x00000004041a7825 */
/* 0x000fc800078e0210 */
/*0750*/ IMAD R10, R20, R11, R10 ; /* 0x0000000b140a7224 */
/* 0x020fc800078e020a */
/*0760*/ IMAD R10, R29, R19, R10 ; /* 0x000000131d0a7224 */
/* 0x000fc800078e020a */
/*0770*/ IMAD R18, R21, R24, R10 ; /* 0x0000001815127224 */
/* 0x000fe200078e020a */
/*0780*/ @P1 BRA 0x300 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*0790*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*07a0*/ @!P1 BRA 0xa30 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*07b0*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*07c0*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x000ea2000c1e1900 */
/*07d0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fca0008000f00 */
/*07e0*/ IMAD.WIDE R10, R9, 0x4, R10 ; /* 0x00000004090a7825 */
/* 0x000fca00078e020a */
/*07f0*/ LDG.E R24, [R10.64] ; /* 0x000000040a187981 */
/* 0x000ea2000c1e1900 */
/*0800*/ IMAD.WIDE R22, R4, 0x4, R26 ; /* 0x0000000404167825 */
/* 0x000fc600078e021a */
/*0810*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0820*/ IMAD.WIDE R14, R4.reuse, 0x4, R22 ; /* 0x00000004040e7825 */
/* 0x040fe200078e0216 */
/*0830*/ LDG.E R29, [R10.64+0x8] ; /* 0x000008040a1d7981 */
/* 0x000f28000c1e1900 */
/*0840*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x0000e2000c1e1900 */
/*0850*/ IMAD.WIDE R16, R4, 0x4, R14 ; /* 0x0000000404107825 */
/* 0x000fc600078e020e */
/*0860*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000326000c1e1900 */
/*0870*/ IMAD.WIDE R12, R4.reuse, 0x4, R16 ; /* 0x00000004040c7825 */
/* 0x040fe200078e0210 */
/*0880*/ LDG.E R28, [R10.64+0xc] ; /* 0x00000c040a1c7981 */
/* 0x000f68000c1e1900 */
/*0890*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000362000c1e1900 */
/*08a0*/ IMAD.WIDE R20, R4, 0x4, R12 ; /* 0x0000000404147825 */
/* 0x000fc600078e020c */
/*08b0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000328000c1e1900 */
/*08c0*/ LDG.E R23, [R10.64+0x14] ; /* 0x000014040a177981 */
/* 0x001f68000c1e1900 */
/*08d0*/ LDG.E R16, [R10.64+0x18] ; /* 0x000018040a107981 */
/* 0x002f68000c1e1900 */
/*08e0*/ LDG.E R13, [R10.64+0x10] ; /* 0x000010040a0d7981 */
/* 0x000f62000c1e1900 */
/*08f0*/ IMAD R24, R19, R24, R18 ; /* 0x0000001813187224 */
/* 0x004fc400078e0212 */
/*0900*/ IMAD.WIDE R18, R4.reuse, 0x4, R20 ; /* 0x0000000404127825 */
/* 0x040fe400078e0214 */
/*0910*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ea8000c1e1900 */
/*0920*/ IMAD.WIDE R26, R4, 0x4, R18 ; /* 0x00000004041a7825 */
/* 0x000fe200078e0212 */
/*0930*/ LDG.E R15, [R18.64] ; /* 0x00000004120f7981 */
/* 0x0000a8000c1e1900 */
/*0940*/ LDG.E R19, [R10.64+0x1c] ; /* 0x00001c040a137981 */
/* 0x001ea8000c1e1900 */
/*0950*/ LDG.E R18, [R26.64] ; /* 0x000000041a127981 */
/* 0x0000a2000c1e1900 */
/*0960*/ IMAD R22, R22, R25, R24 ; /* 0x0000001916167224 */
/* 0x008fc800078e0218 */
/*0970*/ IMAD R14, R14, R29, R22 ; /* 0x0000001d0e0e7224 */
/* 0x010fc800078e0216 */
/*0980*/ IMAD R14, R17, R28, R14 ; /* 0x0000001c110e7224 */
/* 0x020fc800078e020e */
/*0990*/ IMAD R12, R12, R13, R14 ; /* 0x0000000d0c0c7224 */
/* 0x000fe200078e020e */
/*09a0*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*09b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*09c0*/ IMAD.WIDE R26, R4, 0x4, R26 ; /* 0x00000004041a7825 */
/* 0x001fe200078e021a */
/*09d0*/ IADD3 R6, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fe40007ffe0ff */
/*09e0*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*09f0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a00*/ IMAD R12, R20, R23, R12 ; /* 0x00000017140c7224 */
/* 0x004fc800078e020c */
/*0a10*/ IMAD R12, R15, R16, R12 ; /* 0x000000100f0c7224 */
/* 0x000fc800078e020c */
/*0a20*/ IMAD R18, R18, R19, R12 ; /* 0x0000001312127224 */
/* 0x000fe400078e020c */
/*0a30*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0a40*/ @!P0 BRA 0xbe0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0a50*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*0a60*/ IMAD.WIDE R12, R4, 0x4, R26 ; /* 0x00000004040c7825 */
/* 0x000fe200078e021a */
/*0a70*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*0a80*/ LDG.E R27, [R26.64] ; /* 0x000000041a1b7981 */
/* 0x000ea8000c1e1900 */
/*0a90*/ IMAD.WIDE R10, R9, 0x4, R10 ; /* 0x00000004090a7825 */
/* 0x000fc800078e020a */
/*0aa0*/ IMAD.WIDE R14, R4.reuse, 0x4, R12 ; /* 0x00000004040e7825 */
/* 0x040fe200078e020c */
/*0ab0*/ LDG.E R19, [R10.64] ; /* 0x000000040a137981 */
/* 0x000ea8000c1e1900 */
/*0ac0*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ee2000c1e1900 */
/*0ad0*/ IMAD.WIDE R16, R4, 0x4, R14 ; /* 0x0000000404107825 */
/* 0x000fc600078e020e */
/*0ae0*/ LDG.E R20, [R10.64+0x4] ; /* 0x000004040a147981 */
/* 0x000ee8000c1e1900 */
/*0af0*/ LDG.E R22, [R14.64] ; /* 0x000000040e167981 */
/* 0x000f28000c1e1900 */
/*0b00*/ LDG.E R21, [R10.64+0x8] ; /* 0x000008040a157981 */
/* 0x000f28000c1e1900 */
/*0b10*/ LDG.E R23, [R10.64+0xc] ; /* 0x00000c040a177981 */
/* 0x000f68000c1e1900 */
/*0b20*/ LDG.E R24, [R16.64] ; /* 0x0000000410187981 */
/* 0x000f62000c1e1900 */
/*0b30*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fc80007ffe0ff */
/*0b40*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0b50*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0b60*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fc60007ffe0ff */
/*0b70*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0b80*/ IMAD R19, R27, R19, R18 ; /* 0x000000131b137224 */
/* 0x004fc800078e0212 */
/*0b90*/ IMAD R19, R12, R20, R19 ; /* 0x000000140c137224 */
/* 0x008fe400078e0213 */
/*0ba0*/ IMAD.WIDE R26, R4, 0x4, R16 ; /* 0x00000004041a7825 */
/* 0x000fc800078e0210 */
/*0bb0*/ IMAD R19, R22, R21, R19 ; /* 0x0000001516137224 */
/* 0x010fc800078e0213 */
/*0bc0*/ IMAD R18, R24, R23, R19 ; /* 0x0000001718127224 */
/* 0x020fe200078e0213 */
/*0bd0*/ @P0 BRA 0xa50 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0be0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*0bf0*/ @!P0 BRA 0xd00 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0c00*/ IADD3 R3, R3, R6, RZ ; /* 0x0000000603037210 */
/* 0x000fe20007ffe0ff */
/*0c10*/ HFMA2.MMA R10, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0a7435 */
/* 0x000fc800000001ff */
/*0c20*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x000fca00078e0203 */
/*0c30*/ IADD3 R0, -R5, R0, RZ ; /* 0x0000000005007210 */
/* 0x000fe20007ffe1ff */
/*0c40*/ IMAD R5, R6, c[0x0][0x178], R5 ; /* 0x00005e0006057a24 */
/* 0x000fc800078e0205 */
/*0c50*/ IMAD.WIDE R8, R0, R10, c[0x0][0x160] ; /* 0x0000580000087625 */
/* 0x000fc800078e020a */
/*0c60*/ IMAD.WIDE R10, R5, R10, c[0x0][0x168] ; /* 0x00005a00050a7625 */
/* 0x000fca00078e020a */
/*0c70*/ LDG.E R3, [R10.64] ; /* 0x000000040a037981 */
/* 0x0000a8000c1e1900 */
/*0c80*/ LDG.E R0, [R8.64] ; /* 0x0000000408007981 */
/* 0x0002a2000c1e1900 */
/*0c90*/ IADD3 R7, R7, -0x1, RZ ; /* 0xffffffff07077810 */
/* 0x000fc80007ffe0ff */
/*0ca0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*0cb0*/ IMAD.WIDE R10, R4, 0x4, R10 ; /* 0x00000004040a7825 */
/* 0x001fe200078e020a */
/*0cc0*/ IADD3 R8, P1, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x002fc80007f3e0ff */
/*0cd0*/ IADD3.X R9, RZ, R9, RZ, P1, !PT ; /* 0x00000009ff097210 */
/* 0x000fe20000ffe4ff */
/*0ce0*/ IMAD R18, R3, R0, R18 ; /* 0x0000000003127224 */
/* 0x004fcc00078e0212 */
/*0cf0*/ @P0 BRA 0xc70 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0d00*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0d10*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0d20*/ STG.E [R2.64], R18 ; /* 0x0000001202007986 */
/* 0x000fe2000c101904 */
/*0d30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d40*/ BRA 0xd40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8multiplyPiS_S_i
.globl _Z8multiplyPiS_S_i
.p2align 8
.type _Z8multiplyPiS_S_i,@function
_Z8multiplyPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_cmp_lt_i32 s2, 1
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, 0
s_cbranch_scc1 .LBB0_3
s_ashr_i32 s4, s2, 31
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v4, 31, v1
s_add_i32 s5, s2, s4
s_xor_b32 s4, s5, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, v1, v4
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s5, 0, s4
v_xor_b32_e32 v5, v3, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s5, v0
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
v_mad_u64_u32 v[2:3], null, v5, v0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v3, s4
v_sub_nc_u32_e32 v0, v5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s4, v0
v_cmp_le_u32_e32 vcc_lo, s4, v0
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v2, s4, v0
v_cmp_le_u32_e32 vcc_lo, s4, v0
s_load_b128 s[4:7], s[0:1], 0x0
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v4
v_sub_nc_u32_e32 v2, v0, v4
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_2)
v_sub_nc_u32_e32 v4, v1, v2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v5, s3, v4
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s3, s3, 1
s_cmp_lg_u32 s2, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[7:8], 2, v[2:3]
v_add_nc_u32_e32 v2, s2, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b32 v3, v[7:8], off
global_load_b32 v7, v[5:6], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[5:6], null, v3, v7, v[0:1]
v_mov_b32_e32 v0, v5
s_cbranch_scc1 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v0, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8multiplyPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8multiplyPiS_S_i, .Lfunc_end0-_Z8multiplyPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8multiplyPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8multiplyPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002c2e1_00000000-6_matrix_multiplication.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z8multiplyPiS_S_iPiS_S_i
.type _Z32__device_stub__Z8multiplyPiS_S_iPiS_S_i, @function
_Z32__device_stub__Z8multiplyPiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8multiplyPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z8multiplyPiS_S_iPiS_S_i, .-_Z32__device_stub__Z8multiplyPiS_S_iPiS_S_i
.globl _Z8multiplyPiS_S_i
.type _Z8multiplyPiS_S_i, @function
_Z8multiplyPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8multiplyPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8multiplyPiS_S_i, .-_Z8multiplyPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%2d "
.LC1:
.string "\n"
.LC2:
.string "--------\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
movl $256, %edi
call malloc@PLT
movq %rax, %rbp
movl $256, %edi
call malloc@PLT
movq %rax, %rbx
movl $256, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %edx
.L12:
movl %edx, %ecx
sarl $31, %ecx
shrl $29, %ecx
leal (%rcx,%rdx), %eax
andl $7, %eax
subl %ecx, %eax
movl %eax, 0(%rbp,%rdx,4)
subl $1, %eax
movl %eax, (%rbx,%rdx,4)
addq $1, %rdx
cmpq $64, %rdx
jne .L12
movl $1, %ecx
movl $256, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $256, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, 44(%rsp)
movl $1, 48(%rsp)
movl $32, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L13:
movl $2, %ecx
movl $256, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $1, %r13d
leaq .LC0(%rip), %r14
leaq .LC1(%rip), %r15
jmp .L15
.L26:
movl $8, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z8multiplyPiS_S_iPiS_S_i
jmp .L13
.L14:
addq $1, %r13
cmpq $65, %r13
je .L27
.L15:
movl -4(%rbp,%r13,4), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testb $7, %r13b
jne .L14
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L14
.L27:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %r13d
leaq .LC0(%rip), %r14
leaq .LC1(%rip), %r15
jmp .L17
.L16:
addq $1, %r13
cmpq $65, %r13
je .L28
.L17:
movl -4(%rbx,%r13,4), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testb $7, %r13b
jne .L16
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L16
.L28:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %r13d
leaq .LC0(%rip), %r14
leaq .LC1(%rip), %r15
jmp .L19
.L18:
addq $1, %r13
cmpq $65, %r13
je .L29
.L19:
movl -4(%r12,%r13,4), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testb $7, %r13b
jne .L18
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L18
.L29:
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z8multiplyPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z8multiplyPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_multiplication.hip"
.globl _Z23__device_stub__multiplyPiS_S_i # -- Begin function _Z23__device_stub__multiplyPiS_S_i
.p2align 4, 0x90
.type _Z23__device_stub__multiplyPiS_S_i,@function
_Z23__device_stub__multiplyPiS_S_i: # @_Z23__device_stub__multiplyPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8multiplyPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__multiplyPiS_S_i, .Lfunc_end0-_Z23__device_stub__multiplyPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
leaq 16(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
leaq 8(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %rbx
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %r14
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, %ecx
andl $7, %ecx
movl %ecx, (%rbx,%rax,4)
decl %ecx
movl %ecx, (%r14,%rax,4)
incq %rax
cmpq $64, %rax
jne .LBB1_1
# %bb.2:
movq 24(%rsp), %rdi
movl $256, %edx # imm = 0x100
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $256, %edx # imm = 0x100
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967298, %rdx # imm = 0x100000002
leaq 30(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $8, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z8multiplyPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $256, %edx # imm = 0x100
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $1, %r12d
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_5 Depth=1
incq %r12
cmpq $65, %r12
je .LBB1_8
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl -4(%rbx,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
testb $7, %r12b
jne .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB1_7
.LBB1_8:
movl $.Lstr.1, %edi
callq puts@PLT
movl $1, %r12d
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_11: # in Loop: Header=BB1_9 Depth=1
incq %r12
cmpq $65, %r12
je .LBB1_12
.LBB1_9: # =>This Inner Loop Header: Depth=1
movl -4(%r14,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
testb $7, %r12b
jne .LBB1_11
# %bb.10: # in Loop: Header=BB1_9 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB1_11
.LBB1_12:
movl $.Lstr.1, %edi
callq puts@PLT
movl $1, %r12d
jmp .LBB1_13
.p2align 4, 0x90
.LBB1_15: # in Loop: Header=BB1_13 Depth=1
incq %r12
cmpq $65, %r12
je .LBB1_16
.LBB1_13: # =>This Inner Loop Header: Depth=1
movl -4(%r15,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
testb $7, %r12b
jne .LBB1_15
# %bb.14: # in Loop: Header=BB1_13 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB1_15
.LBB1_16:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8multiplyPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8multiplyPiS_S_i,@object # @_Z8multiplyPiS_S_i
.section .rodata,"a",@progbits
.globl _Z8multiplyPiS_S_i
.p2align 3, 0x0
_Z8multiplyPiS_S_i:
.quad _Z23__device_stub__multiplyPiS_S_i
.size _Z8multiplyPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%2d "
.size .L.str, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8multiplyPiS_S_i"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "--------"
.size .Lstr.1, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__multiplyPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8multiplyPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ static void k_reorder_send_buf_total(int nr_prts, int nr_total_blocks, uint *d_bidx, uint *d_sums, float4 *d_xi4, float4 *d_pxi4, float4 *d_xchg_xi4, float4 *d_xchg_pxi4)
{
int i = threadIdx.x + THREADS_PER_BLOCK * blockIdx.x;
if (i >= nr_prts)
return;
if (d_bidx[i] == CUDA_BND_S_OOB) {
int j = d_sums[i];
d_xchg_xi4[j] = d_xi4[i];
d_xchg_pxi4[j] = d_pxi4[i];
}
} | code for sm_80
Function : _Z24k_reorder_send_buf_totaliiPjS_P6float4S1_S1_S1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, 0x200, R3 ; /* 0x0000020000007824 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0203 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ ISETP.NE.AND P0, PT, R2, 0xa, PT ; /* 0x0000000a0200780c */
/* 0x004fda0003f05270 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe20000011400 */
/*00d0*/ IMAD.SHL.U32 R12, R0.reuse, 0x10, RZ ; /* 0x00000010000c7824 */
/* 0x040fe200078e00ff */
/*00e0*/ LEA R10, P0, R0, c[0x0][0x170], 0x2 ; /* 0x00005c00000a7a11 */
/* 0x000fc800078010ff */
/*00f0*/ LEA.HI.X R11, R0.reuse, c[0x0][0x174], R3.reuse, 0x2, P0 ; /* 0x00005d00000b7a11 */
/* 0x140fe400000f1403 */
/*0100*/ SHF.L.U64.HI R0, R0, 0x4, R3 ; /* 0x0000000400007819 */
/* 0x000fe40000010203 */
/*0110*/ IADD3 R4, P0, R12, c[0x0][0x178], RZ ; /* 0x00005e000c047a10 */
/* 0x000fe20007f1e0ff */
/*0120*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea6000c1e1900 */
/*0130*/ IADD3.X R5, R0, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f0000057a10 */
/* 0x000fcc00007fe4ff */
/*0140*/ LDG.E.128 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1d00 */
/*0150*/ IMAD.MOV.U32 R9, RZ, RZ, 0x10 ; /* 0x00000010ff097424 */
/* 0x000fe200078e00ff */
/*0160*/ IADD3 R12, P0, R12, c[0x0][0x180], RZ ; /* 0x000060000c0c7a10 */
/* 0x000fc80007f1e0ff */
/*0170*/ IADD3.X R13, R0, c[0x0][0x184], RZ, P0, !PT ; /* 0x00006100000d7a10 */
/* 0x000fe200007fe4ff */
/*0180*/ IMAD.WIDE R2, R10, R9, c[0x0][0x188] ; /* 0x000062000a027625 */
/* 0x004fca00078e0209 */
/*0190*/ STG.E.128 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x008fe8000c101d04 */
/*01a0*/ LDG.E.128 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e1d00 */
/*01b0*/ IMAD.WIDE R8, R10, R9, c[0x0][0x190] ; /* 0x000064000a087625 */
/* 0x000fca00078e0209 */
/*01c0*/ STG.E.128 [R8.64], R12 ; /* 0x0000000c08007986 */
/* 0x004fe2000c101d04 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ static void k_reorder_send_buf_total(int nr_prts, int nr_total_blocks, uint *d_bidx, uint *d_sums, float4 *d_xi4, float4 *d_pxi4, float4 *d_xchg_xi4, float4 *d_xchg_pxi4)
{
int i = threadIdx.x + THREADS_PER_BLOCK * blockIdx.x;
if (i >= nr_prts)
return;
if (d_bidx[i] == CUDA_BND_S_OOB) {
int j = d_sums[i];
d_xchg_xi4[j] = d_xi4[i];
d_xchg_pxi4[j] = d_pxi4[i];
}
} | .file "tmpxft_0013ac2f_00000000-6_k_reorder_send_buf_total.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24k_reorder_send_buf_totaliiPjS_P6float4S1_S1_S1_, @function
_ZL24k_reorder_send_buf_totaliiPjS_P6float4S1_S1_S1_:
.LFB2052:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
movl %edi, 8(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 32(%rsp)
movq %r9, 40(%rsp)
movq 224(%rsp), %rax
movq %rax, 48(%rsp)
movq 232(%rsp), %rax
movq %rax, 56(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rax
movq %rax, 176(%rsp)
leaq 56(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _ZL24k_reorder_send_buf_totaliiPjS_P6float4S1_S1_S1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _ZL24k_reorder_send_buf_totaliiPjS_P6float4S1_S1_S1_, .-_ZL24k_reorder_send_buf_totaliiPjS_P6float4S1_S1_S1_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24k_reorder_send_buf_totaliiPjS_P6float4S1_S1_S1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL24k_reorder_send_buf_totaliiPjS_P6float4S1_S1_S1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ static void k_reorder_send_buf_total(int nr_prts, int nr_total_blocks, uint *d_bidx, uint *d_sums, float4 *d_xi4, float4 *d_pxi4, float4 *d_xchg_xi4, float4 *d_xchg_pxi4)
{
int i = threadIdx.x + THREADS_PER_BLOCK * blockIdx.x;
if (i >= nr_prts)
return;
if (d_bidx[i] == CUDA_BND_S_OOB) {
int j = d_sums[i];
d_xchg_xi4[j] = d_xi4[i];
d_xchg_pxi4[j] = d_pxi4[i];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ static void k_reorder_send_buf_total(int nr_prts, int nr_total_blocks, uint *d_bidx, uint *d_sums, float4 *d_xi4, float4 *d_pxi4, float4 *d_xchg_xi4, float4 *d_xchg_pxi4)
{
int i = threadIdx.x + THREADS_PER_BLOCK * blockIdx.x;
if (i >= nr_prts)
return;
if (d_bidx[i] == CUDA_BND_S_OOB) {
int j = d_sums[i];
d_xchg_xi4[j] = d_xi4[i];
d_xchg_pxi4[j] = d_pxi4[i];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ static void k_reorder_send_buf_total(int nr_prts, int nr_total_blocks, uint *d_bidx, uint *d_sums, float4 *d_xi4, float4 *d_pxi4, float4 *d_xchg_xi4, float4 *d_xchg_pxi4)
{
int i = threadIdx.x + THREADS_PER_BLOCK * blockIdx.x;
if (i >= nr_prts)
return;
if (d_bidx[i] == CUDA_BND_S_OOB) {
int j = d_sums[i];
d_xchg_xi4[j] = d_xi4[i];
d_xchg_pxi4[j] = d_pxi4[i];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_,"axG",@progbits,_ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_,comdat
.globl _ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_
.p2align 8
.type _ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_,@function
_ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_:
s_load_b32 s2, s[0:1], 0x0
v_lshl_add_u32 v0, s15, 9, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x8
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 10, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b256 s[4:11], s[0:1], 0x10
v_lshlrev_b64 v[6:7], 4, v[0:1]
s_load_b64 s[0:1], s[0:1], 0x30
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v7, vcc_lo
global_load_b32 v4, v[2:3], off
global_load_b128 v[0:3], v[0:1], off
s_waitcnt vmcnt(1)
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 4, v[4:5]
v_add_co_u32 v8, vcc_lo, s10, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, s8, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
s_waitcnt vmcnt(0)
global_store_b128 v[8:9], v[0:3], off
v_add_co_u32 v4, vcc_lo, s0, v4
global_load_b128 v[0:3], v[6:7], off
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_waitcnt vmcnt(0)
global_store_b128 v[4:5], v[0:3], off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 56
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_,"axG",@progbits,_ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_,comdat
.Lfunc_end0:
.size _ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_, .Lfunc_end0-_ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 56
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ static void k_reorder_send_buf_total(int nr_prts, int nr_total_blocks, uint *d_bidx, uint *d_sums, float4 *d_xi4, float4 *d_pxi4, float4 *d_xchg_xi4, float4 *d_xchg_pxi4)
{
int i = threadIdx.x + THREADS_PER_BLOCK * blockIdx.x;
if (i >= nr_prts)
return;
if (d_bidx[i] == CUDA_BND_S_OOB) {
int j = d_sums[i];
d_xchg_xi4[j] = d_xi4[i];
d_xchg_pxi4[j] = d_pxi4[i];
}
} | .text
.file "k_reorder_send_buf_total.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z24k_reorder_send_buf_totaliiPjS_P6float4S1_S1_S1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, 0x200, R3 ; /* 0x0000020000007824 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0203 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ ISETP.NE.AND P0, PT, R2, 0xa, PT ; /* 0x0000000a0200780c */
/* 0x004fda0003f05270 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe20000011400 */
/*00d0*/ IMAD.SHL.U32 R12, R0.reuse, 0x10, RZ ; /* 0x00000010000c7824 */
/* 0x040fe200078e00ff */
/*00e0*/ LEA R10, P0, R0, c[0x0][0x170], 0x2 ; /* 0x00005c00000a7a11 */
/* 0x000fc800078010ff */
/*00f0*/ LEA.HI.X R11, R0.reuse, c[0x0][0x174], R3.reuse, 0x2, P0 ; /* 0x00005d00000b7a11 */
/* 0x140fe400000f1403 */
/*0100*/ SHF.L.U64.HI R0, R0, 0x4, R3 ; /* 0x0000000400007819 */
/* 0x000fe40000010203 */
/*0110*/ IADD3 R4, P0, R12, c[0x0][0x178], RZ ; /* 0x00005e000c047a10 */
/* 0x000fe20007f1e0ff */
/*0120*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea6000c1e1900 */
/*0130*/ IADD3.X R5, R0, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f0000057a10 */
/* 0x000fcc00007fe4ff */
/*0140*/ LDG.E.128 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1d00 */
/*0150*/ IMAD.MOV.U32 R9, RZ, RZ, 0x10 ; /* 0x00000010ff097424 */
/* 0x000fe200078e00ff */
/*0160*/ IADD3 R12, P0, R12, c[0x0][0x180], RZ ; /* 0x000060000c0c7a10 */
/* 0x000fc80007f1e0ff */
/*0170*/ IADD3.X R13, R0, c[0x0][0x184], RZ, P0, !PT ; /* 0x00006100000d7a10 */
/* 0x000fe200007fe4ff */
/*0180*/ IMAD.WIDE R2, R10, R9, c[0x0][0x188] ; /* 0x000062000a027625 */
/* 0x004fca00078e0209 */
/*0190*/ STG.E.128 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x008fe8000c101d04 */
/*01a0*/ LDG.E.128 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e1d00 */
/*01b0*/ IMAD.WIDE R8, R10, R9, c[0x0][0x190] ; /* 0x000064000a087625 */
/* 0x000fca00078e0209 */
/*01c0*/ STG.E.128 [R8.64], R12 ; /* 0x0000000c08007986 */
/* 0x004fe2000c101d04 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_,"axG",@progbits,_ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_,comdat
.globl _ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_
.p2align 8
.type _ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_,@function
_ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_:
s_load_b32 s2, s[0:1], 0x0
v_lshl_add_u32 v0, s15, 9, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x8
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 10, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b256 s[4:11], s[0:1], 0x10
v_lshlrev_b64 v[6:7], 4, v[0:1]
s_load_b64 s[0:1], s[0:1], 0x30
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v7, vcc_lo
global_load_b32 v4, v[2:3], off
global_load_b128 v[0:3], v[0:1], off
s_waitcnt vmcnt(1)
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 4, v[4:5]
v_add_co_u32 v8, vcc_lo, s10, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, s8, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
s_waitcnt vmcnt(0)
global_store_b128 v[8:9], v[0:3], off
v_add_co_u32 v4, vcc_lo, s0, v4
global_load_b128 v[0:3], v[6:7], off
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_waitcnt vmcnt(0)
global_store_b128 v[4:5], v[0:3], off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 56
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_,"axG",@progbits,_ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_,comdat
.Lfunc_end0:
.size _ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_, .Lfunc_end0-_ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 56
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL24k_reorder_send_buf_totaliiPjS_P15HIP_vector_typeIfLj4EES2_S2_S2_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013ac2f_00000000-6_k_reorder_send_buf_total.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24k_reorder_send_buf_totaliiPjS_P6float4S1_S1_S1_, @function
_ZL24k_reorder_send_buf_totaliiPjS_P6float4S1_S1_S1_:
.LFB2052:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
movl %edi, 8(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 32(%rsp)
movq %r9, 40(%rsp)
movq 224(%rsp), %rax
movq %rax, 48(%rsp)
movq 232(%rsp), %rax
movq %rax, 56(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rax
movq %rax, 176(%rsp)
leaq 56(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _ZL24k_reorder_send_buf_totaliiPjS_P6float4S1_S1_S1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _ZL24k_reorder_send_buf_totaliiPjS_P6float4S1_S1_S1_, .-_ZL24k_reorder_send_buf_totaliiPjS_P6float4S1_S1_S1_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24k_reorder_send_buf_totaliiPjS_P6float4S1_S1_S1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL24k_reorder_send_buf_totaliiPjS_P6float4S1_S1_S1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "k_reorder_send_buf_total.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | ///
/// vecAddKernel00.cu
/// For CSU CS575 Spring 2011
/// Instructor: Wim Bohm
/// Based on code from the CUDA Programming Guide
/// By David Newman
/// Created: 2011-02-16
/// Last Modified: 2011-02-16 DVN
///
/// This Kernel adds two Vectors A and B in C on GPU
/// with coalesced memory access.
///
#include <stdio.h>
#include <stdlib.h>
__global__ void AddVectors(const float* A, const float* B, float* C, int N)
{
int i = threadIdx.x + (blockDim.x * blockIdx.x);
int max = blockDim.x * gridDim.x * N;
while ( i < max ) {
C[i] = A[i] + B[i];
i += blockDim.x * gridDim.x;
}
} | code for sm_80
Function : _Z10AddVectorsPKfS0_Pfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ ULDC UR5, c[0x0][0xc] ; /* 0x0000030000057ab9 */
/* 0x000fe20000000800 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fc6000f8e023f */
/*0060*/ ULDC UR5, c[0x0][0x178] ; /* 0x00005e0000057ab9 */
/* 0x000fe40000000800 */
/*0070*/ UIMAD UR5, UR4, UR5, URZ ; /* 0x00000005040572a4 */
/* 0x000fe2000f8e023f */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0090*/ ISETP.GE.AND P0, PT, R0, UR5, PT ; /* 0x0000000500007c0c */
/* 0x000fda000bf06270 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fe200000001ff */
/*00c0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fd20000000a00 */
/*00d0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0.reuse, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x040fe200078e0207 */
/*0120*/ IADD3 R0, R0, UR4, RZ ; /* 0x0000000400007c10 */
/* 0x000fc8000fffe0ff */
/*0130*/ ISETP.GE.AND P0, PT, R0, UR5, PT ; /* 0x0000000500007c0c */
/* 0x000fe2000bf06270 */
/*0140*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0150*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001ee000c101906 */
/*0160*/ @!P0 BRA 0xb0 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | ///
/// vecAddKernel00.cu
/// For CSU CS575 Spring 2011
/// Instructor: Wim Bohm
/// Based on code from the CUDA Programming Guide
/// By David Newman
/// Created: 2011-02-16
/// Last Modified: 2011-02-16 DVN
///
/// This Kernel adds two Vectors A and B in C on GPU
/// with coalesced memory access.
///
#include <stdio.h>
#include <stdlib.h>
__global__ void AddVectors(const float* A, const float* B, float* C, int N)
{
int i = threadIdx.x + (blockDim.x * blockIdx.x);
int max = blockDim.x * gridDim.x * N;
while ( i < max ) {
C[i] = A[i] + B[i];
i += blockDim.x * gridDim.x;
}
} | .file "tmpxft_00142409_00000000-6_vecaddKernel01.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z10AddVectorsPKfS0_PfiPKfS0_Pfi
.type _Z37__device_stub__Z10AddVectorsPKfS0_PfiPKfS0_Pfi, @function
_Z37__device_stub__Z10AddVectorsPKfS0_PfiPKfS0_Pfi:
.LFB2081:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10AddVectorsPKfS0_Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z37__device_stub__Z10AddVectorsPKfS0_PfiPKfS0_Pfi, .-_Z37__device_stub__Z10AddVectorsPKfS0_PfiPKfS0_Pfi
.globl _Z10AddVectorsPKfS0_Pfi
.type _Z10AddVectorsPKfS0_Pfi, @function
_Z10AddVectorsPKfS0_Pfi:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z10AddVectorsPKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z10AddVectorsPKfS0_Pfi, .-_Z10AddVectorsPKfS0_Pfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10AddVectorsPKfS0_Pfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10AddVectorsPKfS0_Pfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | ///
/// vecAddKernel00.cu
/// For CSU CS575 Spring 2011
/// Instructor: Wim Bohm
/// Based on code from the CUDA Programming Guide
/// By David Newman
/// Created: 2011-02-16
/// Last Modified: 2011-02-16 DVN
///
/// This Kernel adds two Vectors A and B in C on GPU
/// with coalesced memory access.
///
#include <stdio.h>
#include <stdlib.h>
__global__ void AddVectors(const float* A, const float* B, float* C, int N)
{
int i = threadIdx.x + (blockDim.x * blockIdx.x);
int max = blockDim.x * gridDim.x * N;
while ( i < max ) {
C[i] = A[i] + B[i];
i += blockDim.x * gridDim.x;
}
} | ///
/// vecAddKernel00.cu
/// For CSU CS575 Spring 2011
/// Instructor: Wim Bohm
/// Based on code from the CUDA Programming Guide
/// By David Newman
/// Created: 2011-02-16
/// Last Modified: 2011-02-16 DVN
///
/// This Kernel adds two Vectors A and B in C on GPU
/// with coalesced memory access.
///
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void AddVectors(const float* A, const float* B, float* C, int N)
{
int i = threadIdx.x + (blockDim.x * blockIdx.x);
int max = blockDim.x * gridDim.x * N;
while ( i < max ) {
C[i] = A[i] + B[i];
i += blockDim.x * gridDim.x;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | ///
/// vecAddKernel00.cu
/// For CSU CS575 Spring 2011
/// Instructor: Wim Bohm
/// Based on code from the CUDA Programming Guide
/// By David Newman
/// Created: 2011-02-16
/// Last Modified: 2011-02-16 DVN
///
/// This Kernel adds two Vectors A and B in C on GPU
/// with coalesced memory access.
///
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void AddVectors(const float* A, const float* B, float* C, int N)
{
int i = threadIdx.x + (blockDim.x * blockIdx.x);
int max = blockDim.x * gridDim.x * N;
while ( i < max ) {
C[i] = A[i] + B[i];
i += blockDim.x * gridDim.x;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10AddVectorsPKfS0_Pfi
.globl _Z10AddVectorsPKfS0_Pfi
.p2align 8
.type _Z10AddVectorsPKfS0_Pfi,@function
_Z10AddVectorsPKfS0_Pfi:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x20
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mul_i32 s8, s8, s2
s_mov_b32 s2, exec_lo
s_mul_i32 s9, s8, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmpx_gt_i32_e64 s9, v1
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_mov_b32 s1, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, s0, s2, v2
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_nc_u32_e32 v1, s8, v1
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s9, v1
global_store_b32 v[2:3], v0, off
s_or_b32 s1, vcc_lo, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10AddVectorsPKfS0_Pfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10AddVectorsPKfS0_Pfi, .Lfunc_end0-_Z10AddVectorsPKfS0_Pfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10AddVectorsPKfS0_Pfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10AddVectorsPKfS0_Pfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | ///
/// vecAddKernel00.cu
/// For CSU CS575 Spring 2011
/// Instructor: Wim Bohm
/// Based on code from the CUDA Programming Guide
/// By David Newman
/// Created: 2011-02-16
/// Last Modified: 2011-02-16 DVN
///
/// This Kernel adds two Vectors A and B in C on GPU
/// with coalesced memory access.
///
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void AddVectors(const float* A, const float* B, float* C, int N)
{
int i = threadIdx.x + (blockDim.x * blockIdx.x);
int max = blockDim.x * gridDim.x * N;
while ( i < max ) {
C[i] = A[i] + B[i];
i += blockDim.x * gridDim.x;
}
} | .text
.file "vecaddKernel01.hip"
.globl _Z25__device_stub__AddVectorsPKfS0_Pfi # -- Begin function _Z25__device_stub__AddVectorsPKfS0_Pfi
.p2align 4, 0x90
.type _Z25__device_stub__AddVectorsPKfS0_Pfi,@function
_Z25__device_stub__AddVectorsPKfS0_Pfi: # @_Z25__device_stub__AddVectorsPKfS0_Pfi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10AddVectorsPKfS0_Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__AddVectorsPKfS0_Pfi, .Lfunc_end0-_Z25__device_stub__AddVectorsPKfS0_Pfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10AddVectorsPKfS0_Pfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10AddVectorsPKfS0_Pfi,@object # @_Z10AddVectorsPKfS0_Pfi
.section .rodata,"a",@progbits
.globl _Z10AddVectorsPKfS0_Pfi
.p2align 3, 0x0
_Z10AddVectorsPKfS0_Pfi:
.quad _Z25__device_stub__AddVectorsPKfS0_Pfi
.size _Z10AddVectorsPKfS0_Pfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10AddVectorsPKfS0_Pfi"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__AddVectorsPKfS0_Pfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10AddVectorsPKfS0_Pfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10AddVectorsPKfS0_Pfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ ULDC UR5, c[0x0][0xc] ; /* 0x0000030000057ab9 */
/* 0x000fe20000000800 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fc6000f8e023f */
/*0060*/ ULDC UR5, c[0x0][0x178] ; /* 0x00005e0000057ab9 */
/* 0x000fe40000000800 */
/*0070*/ UIMAD UR5, UR4, UR5, URZ ; /* 0x00000005040572a4 */
/* 0x000fe2000f8e023f */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0090*/ ISETP.GE.AND P0, PT, R0, UR5, PT ; /* 0x0000000500007c0c */
/* 0x000fda000bf06270 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fe200000001ff */
/*00c0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fd20000000a00 */
/*00d0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0.reuse, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x040fe200078e0207 */
/*0120*/ IADD3 R0, R0, UR4, RZ ; /* 0x0000000400007c10 */
/* 0x000fc8000fffe0ff */
/*0130*/ ISETP.GE.AND P0, PT, R0, UR5, PT ; /* 0x0000000500007c0c */
/* 0x000fe2000bf06270 */
/*0140*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0150*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001ee000c101906 */
/*0160*/ @!P0 BRA 0xb0 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10AddVectorsPKfS0_Pfi
.globl _Z10AddVectorsPKfS0_Pfi
.p2align 8
.type _Z10AddVectorsPKfS0_Pfi,@function
_Z10AddVectorsPKfS0_Pfi:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s8, s[0:1], 0x20
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mul_i32 s8, s8, s2
s_mov_b32 s2, exec_lo
s_mul_i32 s9, s8, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmpx_gt_i32_e64 s9, v1
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_mov_b32 s1, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v2, s0, s2, v2
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_nc_u32_e32 v1, s8, v1
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s9, v1
global_store_b32 v[2:3], v0, off
s_or_b32 s1, vcc_lo, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10AddVectorsPKfS0_Pfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10AddVectorsPKfS0_Pfi, .Lfunc_end0-_Z10AddVectorsPKfS0_Pfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10AddVectorsPKfS0_Pfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10AddVectorsPKfS0_Pfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00142409_00000000-6_vecaddKernel01.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z10AddVectorsPKfS0_PfiPKfS0_Pfi
.type _Z37__device_stub__Z10AddVectorsPKfS0_PfiPKfS0_Pfi, @function
_Z37__device_stub__Z10AddVectorsPKfS0_PfiPKfS0_Pfi:
.LFB2081:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10AddVectorsPKfS0_Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z37__device_stub__Z10AddVectorsPKfS0_PfiPKfS0_Pfi, .-_Z37__device_stub__Z10AddVectorsPKfS0_PfiPKfS0_Pfi
.globl _Z10AddVectorsPKfS0_Pfi
.type _Z10AddVectorsPKfS0_Pfi, @function
_Z10AddVectorsPKfS0_Pfi:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z10AddVectorsPKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z10AddVectorsPKfS0_Pfi, .-_Z10AddVectorsPKfS0_Pfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10AddVectorsPKfS0_Pfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10AddVectorsPKfS0_Pfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vecaddKernel01.hip"
.globl _Z25__device_stub__AddVectorsPKfS0_Pfi # -- Begin function _Z25__device_stub__AddVectorsPKfS0_Pfi
.p2align 4, 0x90
.type _Z25__device_stub__AddVectorsPKfS0_Pfi,@function
_Z25__device_stub__AddVectorsPKfS0_Pfi: # @_Z25__device_stub__AddVectorsPKfS0_Pfi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10AddVectorsPKfS0_Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__AddVectorsPKfS0_Pfi, .Lfunc_end0-_Z25__device_stub__AddVectorsPKfS0_Pfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10AddVectorsPKfS0_Pfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10AddVectorsPKfS0_Pfi,@object # @_Z10AddVectorsPKfS0_Pfi
.section .rodata,"a",@progbits
.globl _Z10AddVectorsPKfS0_Pfi
.p2align 3, 0x0
_Z10AddVectorsPKfS0_Pfi:
.quad _Z25__device_stub__AddVectorsPKfS0_Pfi
.size _Z10AddVectorsPKfS0_Pfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10AddVectorsPKfS0_Pfi"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__AddVectorsPKfS0_Pfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10AddVectorsPKfS0_Pfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define ANGULAR_FLUX_INDEX(a,g,i,j,k,nang,ng,nx,ny) ((a)+((nang)*(g))+((nang)*(ng)*(i))+((nang)*(ng)*(nx)*(j))+((nang)*(ng)*(nx)*(ny)*(k)))
#define SCALAR_FLUX_MOMENTS_INDEX(m,g,i,j,k,cmom,ng,nx,ny) ((m)+((cmom-1)*(g))+((cmom-1)*(ng)*(i))+((cmom-1)*(ng)*(nx)*(j))+((cmom-1)*(ng)*(nx)*(ny)*(k)))
#define SCAT_COEFF_INDEX(a,l,o,nang,cmom) ((a)+((nang)*(l))+((nang)*(cmom)*o))
#define angular_flux_in_0(a,g,i,j,k) angular_flux_in_0[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_in_1(a,g,i,j,k) angular_flux_in_1[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_in_2(a,g,i,j,k) angular_flux_in_2[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_in_3(a,g,i,j,k) angular_flux_in_3[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_in_4(a,g,i,j,k) angular_flux_in_4[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_in_5(a,g,i,j,k) angular_flux_in_5[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_in_6(a,g,i,j,k) angular_flux_in_6[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_in_7(a,g,i,j,k) angular_flux_in_7[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_0(a,g,i,j,k) angular_flux_out_0[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_1(a,g,i,j,k) angular_flux_out_1[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_2(a,g,i,j,k) angular_flux_out_2[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_3(a,g,i,j,k) angular_flux_out_3[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_4(a,g,i,j,k) angular_flux_out_4[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_5(a,g,i,j,k) angular_flux_out_5[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_6(a,g,i,j,k) angular_flux_out_6[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_7(a,g,i,j,k) angular_flux_out_7[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define scalar_flux_moments(l,g,i,j,k) scalar_flux_moments[SCALAR_FLUX_MOMENTS_INDEX((l),(g),(i),(j),(k),cmom,ng,nx,ny)]
#define scat_coeff(a,l,o) scat_coeff[SCAT_COEFF_INDEX((a),(l),(o),nang,cmom)]
// We want to perform a weighted sum of angles in each cell in each energy group for each moment
// One work-group per cell per energy group, and reduce within a work-group
// Work-groups must be power of two sized
__global__ void reduce_flux_moments(
const unsigned int nx,
const unsigned int ny,
const unsigned int nz,
const unsigned int nang,
const unsigned int ng,
const unsigned int cmom,
const double * __restrict__ angular_flux_in_0,
const double * __restrict__ angular_flux_in_1,
const double * __restrict__ angular_flux_in_2,
const double * __restrict__ angular_flux_in_3,
const double * __restrict__ angular_flux_in_4,
const double * __restrict__ angular_flux_in_5,
const double * __restrict__ angular_flux_in_6,
const double * __restrict__ angular_flux_in_7,
const double * __restrict__ angular_flux_out_0,
const double * __restrict__ angular_flux_out_1,
const double * __restrict__ angular_flux_out_2,
const double * __restrict__ angular_flux_out_3,
const double * __restrict__ angular_flux_out_4,
const double * __restrict__ angular_flux_out_5,
const double * __restrict__ angular_flux_out_6,
const double * __restrict__ angular_flux_out_7,
const double * __restrict__ velocity_delta,
const double * __restrict__ quad_weights,
const double * __restrict__ scat_coeff,
double * __restrict__ scalar_flux_moments
)
{
extern __shared__ double local_scalar[];
const size_t a = threadIdx.x;
const size_t g = blockIdx.x;
const size_t global_id = blockIdx.y * blockDim.y + threadIdx.y;
const size_t i = global_id % nx;
const size_t j = (global_id / nx) % ny;
const size_t k = global_id / (nx * ny);
if (global_id >= nx * ny * nz) return;
for (unsigned int l = 0; l < cmom-1; l++)
{
// Load into local memory
local_scalar[a + (threadIdx.y * blockDim.x)] = 0.0;
for (unsigned int aa = a; aa < nang; aa += blockDim.x)
{
const double w = quad_weights[aa];
if (velocity_delta[g] != 0.0)
{
local_scalar[a + (threadIdx.y * blockDim.x)] +=
scat_coeff(aa,l+1,0) * w * (0.5 * (angular_flux_out_0(aa,g,i,j,k) + angular_flux_in_0(aa,g,i,j,k))) +
scat_coeff(aa,l+1,1) * w * (0.5 * (angular_flux_out_1(aa,g,i,j,k) + angular_flux_in_1(aa,g,i,j,k))) +
scat_coeff(aa,l+1,2) * w * (0.5 * (angular_flux_out_2(aa,g,i,j,k) + angular_flux_in_2(aa,g,i,j,k))) +
scat_coeff(aa,l+1,3) * w * (0.5 * (angular_flux_out_3(aa,g,i,j,k) + angular_flux_in_3(aa,g,i,j,k))) +
scat_coeff(aa,l+1,4) * w * (0.5 * (angular_flux_out_4(aa,g,i,j,k) + angular_flux_in_4(aa,g,i,j,k))) +
scat_coeff(aa,l+1,5) * w * (0.5 * (angular_flux_out_5(aa,g,i,j,k) + angular_flux_in_5(aa,g,i,j,k))) +
scat_coeff(aa,l+1,6) * w * (0.5 * (angular_flux_out_6(aa,g,i,j,k) + angular_flux_in_6(aa,g,i,j,k))) +
scat_coeff(aa,l+1,7) * w * (0.5 * (angular_flux_out_7(aa,g,i,j,k) + angular_flux_in_7(aa,g,i,j,k)));
}
else
{
local_scalar[a + (threadIdx.y * blockDim.x)] +=
scat_coeff(aa,l+1,0) * w * angular_flux_out_0(aa,g,i,j,k) +
scat_coeff(aa,l+1,1) * w * angular_flux_out_1(aa,g,i,j,k) +
scat_coeff(aa,l+1,2) * w * angular_flux_out_2(aa,g,i,j,k) +
scat_coeff(aa,l+1,3) * w * angular_flux_out_3(aa,g,i,j,k) +
scat_coeff(aa,l+1,4) * w * angular_flux_out_4(aa,g,i,j,k) +
scat_coeff(aa,l+1,5) * w * angular_flux_out_5(aa,g,i,j,k) +
scat_coeff(aa,l+1,6) * w * angular_flux_out_6(aa,g,i,j,k) +
scat_coeff(aa,l+1,7) * w * angular_flux_out_7(aa,g,i,j,k);
}
}
__syncthreads();
// Reduce in local memory
for (unsigned int offset = blockDim.x / 2; offset > 0; offset /= 2)
{
if (a < offset)
{
local_scalar[a + (threadIdx.y * blockDim.x)] += local_scalar[a + offset + (threadIdx.y * blockDim.x)];
}
__syncthreads();
}
// Save result
if (a == 0)
{
scalar_flux_moments(l,g,i,j,k) = local_scalar[0 + (threadIdx.y * blockDim.x)];
}
} // End of moment loop
} | .file "tmpxft_000a1dd4_00000000-6_reduce_flux_moments.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z102__device_stub__Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_PdjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd
.type _Z102__device_stub__Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_PdjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd, @function
_Z102__device_stub__Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_PdjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd:
.LFB2051:
.cfi_startproc
endbr64
subq $488, %rsp
.cfi_def_cfa_offset 496
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 472(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 256(%rsp)
leaq 24(%rsp), %rax
movq %rax, 264(%rsp)
leaq 20(%rsp), %rax
movq %rax, 272(%rsp)
leaq 16(%rsp), %rax
movq %rax, 280(%rsp)
leaq 12(%rsp), %rax
movq %rax, 288(%rsp)
leaq 8(%rsp), %rax
movq %rax, 296(%rsp)
movq 496(%rsp), %rax
movq %rax, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 304(%rsp)
movq 504(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 312(%rsp)
movq 512(%rsp), %rax
movq %rax, 48(%rsp)
leaq 48(%rsp), %rax
movq %rax, 320(%rsp)
movq 520(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 328(%rsp)
movq 528(%rsp), %rax
movq %rax, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, 336(%rsp)
movq 536(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 344(%rsp)
movq 544(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 352(%rsp)
movq 552(%rsp), %rax
movq %rax, 88(%rsp)
leaq 88(%rsp), %rax
movq %rax, 360(%rsp)
movq 560(%rsp), %rax
movq %rax, 96(%rsp)
leaq 96(%rsp), %rax
movq %rax, 368(%rsp)
movq 568(%rsp), %rax
movq %rax, 104(%rsp)
leaq 104(%rsp), %rax
movq %rax, 376(%rsp)
movq 576(%rsp), %rax
movq %rax, 112(%rsp)
leaq 112(%rsp), %rax
movq %rax, 384(%rsp)
movq 584(%rsp), %rax
movq %rax, 120(%rsp)
leaq 120(%rsp), %rax
movq %rax, 392(%rsp)
movq 592(%rsp), %rax
movq %rax, 128(%rsp)
leaq 128(%rsp), %rax
movq %rax, 400(%rsp)
movq 600(%rsp), %rax
movq %rax, 136(%rsp)
leaq 136(%rsp), %rax
movq %rax, 408(%rsp)
movq 608(%rsp), %rax
movq %rax, 144(%rsp)
leaq 144(%rsp), %rax
movq %rax, 416(%rsp)
movq 616(%rsp), %rax
movq %rax, 152(%rsp)
leaq 152(%rsp), %rax
movq %rax, 424(%rsp)
movq 624(%rsp), %rax
movq %rax, 160(%rsp)
leaq 160(%rsp), %rax
movq %rax, 432(%rsp)
movq 632(%rsp), %rax
movq %rax, 168(%rsp)
leaq 168(%rsp), %rax
movq %rax, 440(%rsp)
movq 640(%rsp), %rax
movq %rax, 176(%rsp)
leaq 176(%rsp), %rax
movq %rax, 448(%rsp)
movq 648(%rsp), %rax
movq %rax, 184(%rsp)
leaq 184(%rsp), %rax
movq %rax, 456(%rsp)
movl $1, 208(%rsp)
movl $1, 212(%rsp)
movl $1, 216(%rsp)
movl $1, 220(%rsp)
movl $1, 224(%rsp)
movl $1, 228(%rsp)
leaq 200(%rsp), %rcx
leaq 192(%rsp), %rdx
leaq 220(%rsp), %rsi
leaq 208(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 472(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $488, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 200(%rsp)
.cfi_def_cfa_offset 504
pushq 200(%rsp)
.cfi_def_cfa_offset 512
leaq 272(%rsp), %r9
movq 236(%rsp), %rcx
movl 244(%rsp), %r8d
movq 224(%rsp), %rsi
movl 232(%rsp), %edx
leaq _Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 496
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z102__device_stub__Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_PdjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd, .-_Z102__device_stub__Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_PdjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd
.globl _Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd
.type _Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd, @function
_Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 168(%rsp)
.cfi_def_cfa_offset 24
pushq 168(%rsp)
.cfi_def_cfa_offset 32
pushq 168(%rsp)
.cfi_def_cfa_offset 40
pushq 168(%rsp)
.cfi_def_cfa_offset 48
pushq 168(%rsp)
.cfi_def_cfa_offset 56
pushq 168(%rsp)
.cfi_def_cfa_offset 64
pushq 168(%rsp)
.cfi_def_cfa_offset 72
pushq 168(%rsp)
.cfi_def_cfa_offset 80
pushq 168(%rsp)
.cfi_def_cfa_offset 88
pushq 168(%rsp)
.cfi_def_cfa_offset 96
pushq 168(%rsp)
.cfi_def_cfa_offset 104
pushq 168(%rsp)
.cfi_def_cfa_offset 112
pushq 168(%rsp)
.cfi_def_cfa_offset 120
pushq 168(%rsp)
.cfi_def_cfa_offset 128
pushq 168(%rsp)
.cfi_def_cfa_offset 136
pushq 168(%rsp)
.cfi_def_cfa_offset 144
pushq 168(%rsp)
.cfi_def_cfa_offset 152
pushq 168(%rsp)
.cfi_def_cfa_offset 160
pushq 168(%rsp)
.cfi_def_cfa_offset 168
pushq 168(%rsp)
.cfi_def_cfa_offset 176
call _Z102__device_stub__Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_PdjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd
addq $168, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd, .-_Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define ANGULAR_FLUX_INDEX(a,g,i,j,k,nang,ng,nx,ny) ((a)+((nang)*(g))+((nang)*(ng)*(i))+((nang)*(ng)*(nx)*(j))+((nang)*(ng)*(nx)*(ny)*(k)))
#define SCALAR_FLUX_MOMENTS_INDEX(m,g,i,j,k,cmom,ng,nx,ny) ((m)+((cmom-1)*(g))+((cmom-1)*(ng)*(i))+((cmom-1)*(ng)*(nx)*(j))+((cmom-1)*(ng)*(nx)*(ny)*(k)))
#define SCAT_COEFF_INDEX(a,l,o,nang,cmom) ((a)+((nang)*(l))+((nang)*(cmom)*o))
#define angular_flux_in_0(a,g,i,j,k) angular_flux_in_0[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_in_1(a,g,i,j,k) angular_flux_in_1[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_in_2(a,g,i,j,k) angular_flux_in_2[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_in_3(a,g,i,j,k) angular_flux_in_3[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_in_4(a,g,i,j,k) angular_flux_in_4[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_in_5(a,g,i,j,k) angular_flux_in_5[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_in_6(a,g,i,j,k) angular_flux_in_6[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_in_7(a,g,i,j,k) angular_flux_in_7[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_0(a,g,i,j,k) angular_flux_out_0[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_1(a,g,i,j,k) angular_flux_out_1[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_2(a,g,i,j,k) angular_flux_out_2[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_3(a,g,i,j,k) angular_flux_out_3[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_4(a,g,i,j,k) angular_flux_out_4[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_5(a,g,i,j,k) angular_flux_out_5[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_6(a,g,i,j,k) angular_flux_out_6[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_7(a,g,i,j,k) angular_flux_out_7[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define scalar_flux_moments(l,g,i,j,k) scalar_flux_moments[SCALAR_FLUX_MOMENTS_INDEX((l),(g),(i),(j),(k),cmom,ng,nx,ny)]
#define scat_coeff(a,l,o) scat_coeff[SCAT_COEFF_INDEX((a),(l),(o),nang,cmom)]
// We want to perform a weighted sum of angles in each cell in each energy group for each moment
// One work-group per cell per energy group, and reduce within a work-group
// Work-groups must be power of two sized
__global__ void reduce_flux_moments(
const unsigned int nx,
const unsigned int ny,
const unsigned int nz,
const unsigned int nang,
const unsigned int ng,
const unsigned int cmom,
const double * __restrict__ angular_flux_in_0,
const double * __restrict__ angular_flux_in_1,
const double * __restrict__ angular_flux_in_2,
const double * __restrict__ angular_flux_in_3,
const double * __restrict__ angular_flux_in_4,
const double * __restrict__ angular_flux_in_5,
const double * __restrict__ angular_flux_in_6,
const double * __restrict__ angular_flux_in_7,
const double * __restrict__ angular_flux_out_0,
const double * __restrict__ angular_flux_out_1,
const double * __restrict__ angular_flux_out_2,
const double * __restrict__ angular_flux_out_3,
const double * __restrict__ angular_flux_out_4,
const double * __restrict__ angular_flux_out_5,
const double * __restrict__ angular_flux_out_6,
const double * __restrict__ angular_flux_out_7,
const double * __restrict__ velocity_delta,
const double * __restrict__ quad_weights,
const double * __restrict__ scat_coeff,
double * __restrict__ scalar_flux_moments
)
{
extern __shared__ double local_scalar[];
const size_t a = threadIdx.x;
const size_t g = blockIdx.x;
const size_t global_id = blockIdx.y * blockDim.y + threadIdx.y;
const size_t i = global_id % nx;
const size_t j = (global_id / nx) % ny;
const size_t k = global_id / (nx * ny);
if (global_id >= nx * ny * nz) return;
for (unsigned int l = 0; l < cmom-1; l++)
{
// Load into local memory
local_scalar[a + (threadIdx.y * blockDim.x)] = 0.0;
for (unsigned int aa = a; aa < nang; aa += blockDim.x)
{
const double w = quad_weights[aa];
if (velocity_delta[g] != 0.0)
{
local_scalar[a + (threadIdx.y * blockDim.x)] +=
scat_coeff(aa,l+1,0) * w * (0.5 * (angular_flux_out_0(aa,g,i,j,k) + angular_flux_in_0(aa,g,i,j,k))) +
scat_coeff(aa,l+1,1) * w * (0.5 * (angular_flux_out_1(aa,g,i,j,k) + angular_flux_in_1(aa,g,i,j,k))) +
scat_coeff(aa,l+1,2) * w * (0.5 * (angular_flux_out_2(aa,g,i,j,k) + angular_flux_in_2(aa,g,i,j,k))) +
scat_coeff(aa,l+1,3) * w * (0.5 * (angular_flux_out_3(aa,g,i,j,k) + angular_flux_in_3(aa,g,i,j,k))) +
scat_coeff(aa,l+1,4) * w * (0.5 * (angular_flux_out_4(aa,g,i,j,k) + angular_flux_in_4(aa,g,i,j,k))) +
scat_coeff(aa,l+1,5) * w * (0.5 * (angular_flux_out_5(aa,g,i,j,k) + angular_flux_in_5(aa,g,i,j,k))) +
scat_coeff(aa,l+1,6) * w * (0.5 * (angular_flux_out_6(aa,g,i,j,k) + angular_flux_in_6(aa,g,i,j,k))) +
scat_coeff(aa,l+1,7) * w * (0.5 * (angular_flux_out_7(aa,g,i,j,k) + angular_flux_in_7(aa,g,i,j,k)));
}
else
{
local_scalar[a + (threadIdx.y * blockDim.x)] +=
scat_coeff(aa,l+1,0) * w * angular_flux_out_0(aa,g,i,j,k) +
scat_coeff(aa,l+1,1) * w * angular_flux_out_1(aa,g,i,j,k) +
scat_coeff(aa,l+1,2) * w * angular_flux_out_2(aa,g,i,j,k) +
scat_coeff(aa,l+1,3) * w * angular_flux_out_3(aa,g,i,j,k) +
scat_coeff(aa,l+1,4) * w * angular_flux_out_4(aa,g,i,j,k) +
scat_coeff(aa,l+1,5) * w * angular_flux_out_5(aa,g,i,j,k) +
scat_coeff(aa,l+1,6) * w * angular_flux_out_6(aa,g,i,j,k) +
scat_coeff(aa,l+1,7) * w * angular_flux_out_7(aa,g,i,j,k);
}
}
__syncthreads();
// Reduce in local memory
for (unsigned int offset = blockDim.x / 2; offset > 0; offset /= 2)
{
if (a < offset)
{
local_scalar[a + (threadIdx.y * blockDim.x)] += local_scalar[a + offset + (threadIdx.y * blockDim.x)];
}
__syncthreads();
}
// Save result
if (a == 0)
{
scalar_flux_moments(l,g,i,j,k) = local_scalar[0 + (threadIdx.y * blockDim.x)];
}
} // End of moment loop
} | #include <hip/hip_runtime.h>
#define ANGULAR_FLUX_INDEX(a,g,i,j,k,nang,ng,nx,ny) ((a)+((nang)*(g))+((nang)*(ng)*(i))+((nang)*(ng)*(nx)*(j))+((nang)*(ng)*(nx)*(ny)*(k)))
#define SCALAR_FLUX_MOMENTS_INDEX(m,g,i,j,k,cmom,ng,nx,ny) ((m)+((cmom-1)*(g))+((cmom-1)*(ng)*(i))+((cmom-1)*(ng)*(nx)*(j))+((cmom-1)*(ng)*(nx)*(ny)*(k)))
#define SCAT_COEFF_INDEX(a,l,o,nang,cmom) ((a)+((nang)*(l))+((nang)*(cmom)*o))
#define angular_flux_in_0(a,g,i,j,k) angular_flux_in_0[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_in_1(a,g,i,j,k) angular_flux_in_1[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_in_2(a,g,i,j,k) angular_flux_in_2[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_in_3(a,g,i,j,k) angular_flux_in_3[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_in_4(a,g,i,j,k) angular_flux_in_4[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_in_5(a,g,i,j,k) angular_flux_in_5[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_in_6(a,g,i,j,k) angular_flux_in_6[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_in_7(a,g,i,j,k) angular_flux_in_7[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_0(a,g,i,j,k) angular_flux_out_0[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_1(a,g,i,j,k) angular_flux_out_1[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_2(a,g,i,j,k) angular_flux_out_2[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_3(a,g,i,j,k) angular_flux_out_3[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_4(a,g,i,j,k) angular_flux_out_4[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_5(a,g,i,j,k) angular_flux_out_5[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_6(a,g,i,j,k) angular_flux_out_6[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_7(a,g,i,j,k) angular_flux_out_7[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define scalar_flux_moments(l,g,i,j,k) scalar_flux_moments[SCALAR_FLUX_MOMENTS_INDEX((l),(g),(i),(j),(k),cmom,ng,nx,ny)]
#define scat_coeff(a,l,o) scat_coeff[SCAT_COEFF_INDEX((a),(l),(o),nang,cmom)]
// We want to perform a weighted sum of angles in each cell in each energy group for each moment
// One work-group per cell per energy group, and reduce within a work-group
// Work-groups must be power of two sized
__global__ void reduce_flux_moments(
const unsigned int nx,
const unsigned int ny,
const unsigned int nz,
const unsigned int nang,
const unsigned int ng,
const unsigned int cmom,
const double * __restrict__ angular_flux_in_0,
const double * __restrict__ angular_flux_in_1,
const double * __restrict__ angular_flux_in_2,
const double * __restrict__ angular_flux_in_3,
const double * __restrict__ angular_flux_in_4,
const double * __restrict__ angular_flux_in_5,
const double * __restrict__ angular_flux_in_6,
const double * __restrict__ angular_flux_in_7,
const double * __restrict__ angular_flux_out_0,
const double * __restrict__ angular_flux_out_1,
const double * __restrict__ angular_flux_out_2,
const double * __restrict__ angular_flux_out_3,
const double * __restrict__ angular_flux_out_4,
const double * __restrict__ angular_flux_out_5,
const double * __restrict__ angular_flux_out_6,
const double * __restrict__ angular_flux_out_7,
const double * __restrict__ velocity_delta,
const double * __restrict__ quad_weights,
const double * __restrict__ scat_coeff,
double * __restrict__ scalar_flux_moments
)
{
extern __shared__ double local_scalar[];
const size_t a = threadIdx.x;
const size_t g = blockIdx.x;
const size_t global_id = blockIdx.y * blockDim.y + threadIdx.y;
const size_t i = global_id % nx;
const size_t j = (global_id / nx) % ny;
const size_t k = global_id / (nx * ny);
if (global_id >= nx * ny * nz) return;
for (unsigned int l = 0; l < cmom-1; l++)
{
// Load into local memory
local_scalar[a + (threadIdx.y * blockDim.x)] = 0.0;
for (unsigned int aa = a; aa < nang; aa += blockDim.x)
{
const double w = quad_weights[aa];
if (velocity_delta[g] != 0.0)
{
local_scalar[a + (threadIdx.y * blockDim.x)] +=
scat_coeff(aa,l+1,0) * w * (0.5 * (angular_flux_out_0(aa,g,i,j,k) + angular_flux_in_0(aa,g,i,j,k))) +
scat_coeff(aa,l+1,1) * w * (0.5 * (angular_flux_out_1(aa,g,i,j,k) + angular_flux_in_1(aa,g,i,j,k))) +
scat_coeff(aa,l+1,2) * w * (0.5 * (angular_flux_out_2(aa,g,i,j,k) + angular_flux_in_2(aa,g,i,j,k))) +
scat_coeff(aa,l+1,3) * w * (0.5 * (angular_flux_out_3(aa,g,i,j,k) + angular_flux_in_3(aa,g,i,j,k))) +
scat_coeff(aa,l+1,4) * w * (0.5 * (angular_flux_out_4(aa,g,i,j,k) + angular_flux_in_4(aa,g,i,j,k))) +
scat_coeff(aa,l+1,5) * w * (0.5 * (angular_flux_out_5(aa,g,i,j,k) + angular_flux_in_5(aa,g,i,j,k))) +
scat_coeff(aa,l+1,6) * w * (0.5 * (angular_flux_out_6(aa,g,i,j,k) + angular_flux_in_6(aa,g,i,j,k))) +
scat_coeff(aa,l+1,7) * w * (0.5 * (angular_flux_out_7(aa,g,i,j,k) + angular_flux_in_7(aa,g,i,j,k)));
}
else
{
local_scalar[a + (threadIdx.y * blockDim.x)] +=
scat_coeff(aa,l+1,0) * w * angular_flux_out_0(aa,g,i,j,k) +
scat_coeff(aa,l+1,1) * w * angular_flux_out_1(aa,g,i,j,k) +
scat_coeff(aa,l+1,2) * w * angular_flux_out_2(aa,g,i,j,k) +
scat_coeff(aa,l+1,3) * w * angular_flux_out_3(aa,g,i,j,k) +
scat_coeff(aa,l+1,4) * w * angular_flux_out_4(aa,g,i,j,k) +
scat_coeff(aa,l+1,5) * w * angular_flux_out_5(aa,g,i,j,k) +
scat_coeff(aa,l+1,6) * w * angular_flux_out_6(aa,g,i,j,k) +
scat_coeff(aa,l+1,7) * w * angular_flux_out_7(aa,g,i,j,k);
}
}
__syncthreads();
// Reduce in local memory
for (unsigned int offset = blockDim.x / 2; offset > 0; offset /= 2)
{
if (a < offset)
{
local_scalar[a + (threadIdx.y * blockDim.x)] += local_scalar[a + offset + (threadIdx.y * blockDim.x)];
}
__syncthreads();
}
// Save result
if (a == 0)
{
scalar_flux_moments(l,g,i,j,k) = local_scalar[0 + (threadIdx.y * blockDim.x)];
}
} // End of moment loop
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define ANGULAR_FLUX_INDEX(a,g,i,j,k,nang,ng,nx,ny) ((a)+((nang)*(g))+((nang)*(ng)*(i))+((nang)*(ng)*(nx)*(j))+((nang)*(ng)*(nx)*(ny)*(k)))
#define SCALAR_FLUX_MOMENTS_INDEX(m,g,i,j,k,cmom,ng,nx,ny) ((m)+((cmom-1)*(g))+((cmom-1)*(ng)*(i))+((cmom-1)*(ng)*(nx)*(j))+((cmom-1)*(ng)*(nx)*(ny)*(k)))
#define SCAT_COEFF_INDEX(a,l,o,nang,cmom) ((a)+((nang)*(l))+((nang)*(cmom)*o))
#define angular_flux_in_0(a,g,i,j,k) angular_flux_in_0[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_in_1(a,g,i,j,k) angular_flux_in_1[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_in_2(a,g,i,j,k) angular_flux_in_2[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_in_3(a,g,i,j,k) angular_flux_in_3[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_in_4(a,g,i,j,k) angular_flux_in_4[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_in_5(a,g,i,j,k) angular_flux_in_5[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_in_6(a,g,i,j,k) angular_flux_in_6[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_in_7(a,g,i,j,k) angular_flux_in_7[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_0(a,g,i,j,k) angular_flux_out_0[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_1(a,g,i,j,k) angular_flux_out_1[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_2(a,g,i,j,k) angular_flux_out_2[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_3(a,g,i,j,k) angular_flux_out_3[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_4(a,g,i,j,k) angular_flux_out_4[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_5(a,g,i,j,k) angular_flux_out_5[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_6(a,g,i,j,k) angular_flux_out_6[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_7(a,g,i,j,k) angular_flux_out_7[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define scalar_flux_moments(l,g,i,j,k) scalar_flux_moments[SCALAR_FLUX_MOMENTS_INDEX((l),(g),(i),(j),(k),cmom,ng,nx,ny)]
#define scat_coeff(a,l,o) scat_coeff[SCAT_COEFF_INDEX((a),(l),(o),nang,cmom)]
// We want to perform a weighted sum of angles in each cell in each energy group for each moment
// One work-group per cell per energy group, and reduce within a work-group
// Work-groups must be power of two sized
__global__ void reduce_flux_moments(
const unsigned int nx,
const unsigned int ny,
const unsigned int nz,
const unsigned int nang,
const unsigned int ng,
const unsigned int cmom,
const double * __restrict__ angular_flux_in_0,
const double * __restrict__ angular_flux_in_1,
const double * __restrict__ angular_flux_in_2,
const double * __restrict__ angular_flux_in_3,
const double * __restrict__ angular_flux_in_4,
const double * __restrict__ angular_flux_in_5,
const double * __restrict__ angular_flux_in_6,
const double * __restrict__ angular_flux_in_7,
const double * __restrict__ angular_flux_out_0,
const double * __restrict__ angular_flux_out_1,
const double * __restrict__ angular_flux_out_2,
const double * __restrict__ angular_flux_out_3,
const double * __restrict__ angular_flux_out_4,
const double * __restrict__ angular_flux_out_5,
const double * __restrict__ angular_flux_out_6,
const double * __restrict__ angular_flux_out_7,
const double * __restrict__ velocity_delta,
const double * __restrict__ quad_weights,
const double * __restrict__ scat_coeff,
double * __restrict__ scalar_flux_moments
)
{
extern __shared__ double local_scalar[];
const size_t a = threadIdx.x;
const size_t g = blockIdx.x;
const size_t global_id = blockIdx.y * blockDim.y + threadIdx.y;
const size_t i = global_id % nx;
const size_t j = (global_id / nx) % ny;
const size_t k = global_id / (nx * ny);
if (global_id >= nx * ny * nz) return;
for (unsigned int l = 0; l < cmom-1; l++)
{
// Load into local memory
local_scalar[a + (threadIdx.y * blockDim.x)] = 0.0;
for (unsigned int aa = a; aa < nang; aa += blockDim.x)
{
const double w = quad_weights[aa];
if (velocity_delta[g] != 0.0)
{
local_scalar[a + (threadIdx.y * blockDim.x)] +=
scat_coeff(aa,l+1,0) * w * (0.5 * (angular_flux_out_0(aa,g,i,j,k) + angular_flux_in_0(aa,g,i,j,k))) +
scat_coeff(aa,l+1,1) * w * (0.5 * (angular_flux_out_1(aa,g,i,j,k) + angular_flux_in_1(aa,g,i,j,k))) +
scat_coeff(aa,l+1,2) * w * (0.5 * (angular_flux_out_2(aa,g,i,j,k) + angular_flux_in_2(aa,g,i,j,k))) +
scat_coeff(aa,l+1,3) * w * (0.5 * (angular_flux_out_3(aa,g,i,j,k) + angular_flux_in_3(aa,g,i,j,k))) +
scat_coeff(aa,l+1,4) * w * (0.5 * (angular_flux_out_4(aa,g,i,j,k) + angular_flux_in_4(aa,g,i,j,k))) +
scat_coeff(aa,l+1,5) * w * (0.5 * (angular_flux_out_5(aa,g,i,j,k) + angular_flux_in_5(aa,g,i,j,k))) +
scat_coeff(aa,l+1,6) * w * (0.5 * (angular_flux_out_6(aa,g,i,j,k) + angular_flux_in_6(aa,g,i,j,k))) +
scat_coeff(aa,l+1,7) * w * (0.5 * (angular_flux_out_7(aa,g,i,j,k) + angular_flux_in_7(aa,g,i,j,k)));
}
else
{
local_scalar[a + (threadIdx.y * blockDim.x)] +=
scat_coeff(aa,l+1,0) * w * angular_flux_out_0(aa,g,i,j,k) +
scat_coeff(aa,l+1,1) * w * angular_flux_out_1(aa,g,i,j,k) +
scat_coeff(aa,l+1,2) * w * angular_flux_out_2(aa,g,i,j,k) +
scat_coeff(aa,l+1,3) * w * angular_flux_out_3(aa,g,i,j,k) +
scat_coeff(aa,l+1,4) * w * angular_flux_out_4(aa,g,i,j,k) +
scat_coeff(aa,l+1,5) * w * angular_flux_out_5(aa,g,i,j,k) +
scat_coeff(aa,l+1,6) * w * angular_flux_out_6(aa,g,i,j,k) +
scat_coeff(aa,l+1,7) * w * angular_flux_out_7(aa,g,i,j,k);
}
}
__syncthreads();
// Reduce in local memory
for (unsigned int offset = blockDim.x / 2; offset > 0; offset /= 2)
{
if (a < offset)
{
local_scalar[a + (threadIdx.y * blockDim.x)] += local_scalar[a + offset + (threadIdx.y * blockDim.x)];
}
__syncthreads();
}
// Save result
if (a == 0)
{
scalar_flux_moments(l,g,i,j,k) = local_scalar[0 + (threadIdx.y * blockDim.x)];
}
} // End of moment loop
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd
.globl _Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd
.p2align 8
.type _Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd,@function
_Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd:
s_clause 0x2
s_load_b64 s[34:35], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x8
s_load_b32 s2, s[0:1], 0xc4
s_add_u32 s52, s0, 0xb8
s_addc_u32 s53, s1, 0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v1, s34
s_sub_i32 s4, 0, s34
s_lshr_b32 s2, s2, 16
s_mul_i32 s55, s35, s34
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_mul_i32 s3, s55, s3
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, s4, v4
s_mov_b32 s4, exec_lo
v_mul_hi_u32 v5, v4, v1
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v4, v5
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v2, s34
v_sub_nc_u32_e32 v4, v1, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v5, s34, v4
v_cmp_le_u32_e64 s2, s34, v4
v_cndmask_b32_e64 v4, v4, v5, s2
s_delay_alu instid0(VALU_DEP_1)
v_cmp_le_u32_e32 vcc_lo, s34, v4
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_18
s_load_b32 s54, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_add_i32 s3, s54, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s3, 0
s_cbranch_scc1 .LBB0_18
v_cvt_f32_u32_e32 v4, s35
v_cvt_f32_u32_e32 v5, s55
v_and_b32_e32 v11, 0x3ff, v0
s_clause 0x3
s_load_b256 s[4:11], s[0:1], 0x98
s_load_b256 s[16:23], s[0:1], 0x78
s_load_b256 s[24:31], s[0:1], 0x58
s_load_b256 s[36:43], s[0:1], 0x38
v_rcp_iflag_f32_e32 v4, v4
v_rcp_iflag_f32_e32 v5, v5
v_add_nc_u32_e32 v6, 1, v2
s_clause 0x1
s_load_b256 s[44:51], s[0:1], 0x18
s_load_b64 s[12:13], s[0:1], 0xc
s_load_b32 s1, s[52:53], 0xc
s_sub_i32 s0, 0, s35
s_mov_b32 s15, 0
s_mul_hi_u32 s53, s3, s14
s_mul_i32 s52, s3, s14
s_lshl_b64 s[56:57], s[14:15], 3
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v4, 0x4f7ffffe, v4 :: v_dual_mul_f32 v5, 0x4f7ffffe, v5
v_cndmask_b32_e64 v2, v2, v6, s2
s_sub_i32 s2, 0, s55
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v0, v4
v_add_nc_u32_e32 v4, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v6, s0, v0
v_cndmask_b32_e32 v8, v2, v4, vcc_lo
v_cvt_u32_f32_e32 v2, v5
s_waitcnt lgkmcnt(0)
s_and_b32 s33, s1, 0xffff
s_mul_hi_u32 s59, s12, s14
s_mul_i32 s58, s12, s14
v_mad_u64_u32 v[4:5], null, v8, s34, 0
v_mul_lo_u32 v7, s2, v2
v_mul_hi_u32 v6, v0, v6
s_mul_i32 s2, s13, s12
v_mul_u32_u24_e32 v10, s33, v3
v_mad_u32_u24 v12, v3, s33, v11
s_mul_i32 s14, s3, s13
v_sub_co_u32 v13, vcc_lo, v1, v4
v_mul_hi_u32 v9, v2, v7
v_add_nc_u32_e32 v0, v0, v6
v_sub_co_ci_u32_e32 v14, vcc_lo, 0, v5, vcc_lo
s_add_u32 s4, s4, s56
s_mul_i32 s56, s2, s34
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[6:7], null, v8, v0, 0
v_add_nc_u32_e32 v0, v2, v9
v_mad_u64_u32 v[2:3], null, v13, s2, s[58:59]
s_mul_i32 s34, s14, s34
s_addc_u32 s5, s5, s57
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[4:5], null, v1, v0, 0
v_mul_lo_u32 v6, v7, s35
s_cmp_gt_u32 s33, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_mov_b32_e32 v0, v3
s_mul_i32 s58, s34, s35
s_mul_i32 s57, s56, s35
s_cselect_b32 s13, -1, 0
v_mul_lo_u32 v9, v5, s55
v_mad_u64_u32 v[3:4], null, v14, s2, v[0:1]
v_sub_nc_u32_e32 v8, v8, v6
v_mad_u64_u32 v[6:7], null, v13, s14, 0
v_cmp_eq_u32_e64 s0, 0, v11
v_cmp_gt_u32_e64 s1, s12, v11
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_subrev_nc_u32_e32 v13, s35, v8
v_cmp_le_u32_e32 vcc_lo, s35, v8
v_sub_nc_u32_e32 v1, v1, v9
v_mov_b32_e32 v0, v7
v_cndmask_b32_e32 v4, v8, v13, vcc_lo
v_add_nc_u32_e32 v8, 1, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cmp_le_u32_e32 vcc_lo, s55, v1
v_lshl_add_u32 v13, v12, 3, 0
v_subrev_nc_u32_e32 v7, s35, v4
v_cmp_le_u32_e64 s2, s35, v4
v_cndmask_b32_e32 v15, v5, v8, vcc_lo
v_subrev_nc_u32_e32 v8, s55, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v16, v4, v7, s2
v_mad_u64_u32 v[4:5], null, v14, s14, v[0:1]
v_dual_cndmask_b32 v0, v1, v8 :: v_dual_add_nc_u32 v1, 1, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[8:9], null, v16, s56, v[2:3]
v_mad_u64_u32 v[2:3], null, v16, s34, 0
v_mov_b32_e32 v7, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_u32_e32 vcc_lo, s55, v0
s_lshl_b64 s[34:35], s[52:53], 3
s_add_u32 s2, s10, s34
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 3, v[6:7]
v_cndmask_b32_e32 v14, v15, v1, vcc_lo
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_addc_u32 s10, s11, s35
s_lshl_b32 s14, s54, 2
s_mul_i32 s11, s54, 5
v_mad_u64_u32 v[6:7], null, v14, s58, 0
v_mad_u64_u32 v[0:1], null, v14, s57, v[8:9]
v_add_co_u32 v8, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[4:5], 3, v[6:7]
v_add_co_u32 v2, vcc_lo, v8, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, v9, v3, vcc_lo
s_or_b32 s14, s14, 1
v_add_co_u32 v15, vcc_lo, v2, v4
s_mul_i32 s2, s54, 7
s_mul_i32 s10, s54, 6
s_mul_i32 s34, s12, s14
s_mul_i32 s14, s54, 3
s_lshl_b32 s35, s54, 1
v_lshl_add_u32 v14, v10, 3, 0
v_add_co_ci_u32_e32 v16, vcc_lo, v3, v5, vcc_lo
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v4, 0
s_add_i32 s2, s2, 1
s_or_b32 s10, s10, 1
s_add_i32 s11, s11, 1
s_add_i32 s14, s14, 1
s_or_b32 s52, s35, 1
s_add_i32 s54, s54, 1
s_mul_i32 s2, s12, s2
s_mul_i32 s10, s12, s10
s_mul_i32 s11, s12, s11
s_mul_i32 s35, s12, s14
s_mul_i32 s52, s12, s52
s_mul_i32 s53, s12, s54
s_mov_b32 s54, s12
s_mov_b32 s14, s15
s_branch .LBB0_4
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s55
s_add_i32 s14, s14, 1
s_add_i32 s2, s2, s12
s_add_i32 s10, s10, s12
s_add_i32 s11, s11, s12
s_add_i32 s34, s34, s12
s_add_i32 s35, s35, s12
s_add_i32 s52, s52, s12
s_add_i32 s53, s53, s12
s_add_i32 s54, s54, s12
s_cmp_lg_u32 s14, s3
s_cbranch_scc0 .LBB0_18
.LBB0_4:
v_mov_b32_e32 v3, v2
ds_store_b64 v13, v[2:3]
s_and_saveexec_b32 s55, s1
s_cbranch_execz .LBB0_12
s_load_b64 s[56:57], s[4:5], 0x0
ds_load_b64 v[5:6], v13
v_mov_b32_e32 v3, v11
s_waitcnt lgkmcnt(0)
v_cmp_eq_f64_e64 s56, s[56:57], 0
s_mov_b32 s57, 0
s_branch .LBB0_7
.LBB0_6:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[5:6], v[9:10]
v_add_nc_u32_e32 v3, s33, v3
v_cmp_le_u32_e32 vcc_lo, s12, v3
s_or_b32 s57, vcc_lo, s57
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s57
s_cbranch_execz .LBB0_11
.LBB0_7:
s_waitcnt vmcnt(0)
v_lshlrev_b64 v[7:8], 3, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
s_and_b32 vcc_lo, exec_lo, s56
global_load_b64 v[7:8], v[7:8], off
s_cbranch_vccz .LBB0_9
v_dual_mov_b32 v10, 0 :: v_dual_add_nc_u32 v9, s54, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[17:18], 3, v[9:10]
v_add_nc_u32_e32 v9, s53, v3
v_lshlrev_b64 v[19:20], 3, v[9:10]
v_add_nc_u32_e32 v9, s52, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[25:26], 3, v[9:10]
v_add_co_u32 v19, vcc_lo, s8, v19
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v20, vcc_lo, s9, v20, vcc_lo
v_add_co_u32 v21, vcc_lo, v0, v3
v_add_co_ci_u32_e32 v22, vcc_lo, v1, v4, vcc_lo
global_load_b64 v[19:20], v[19:20], off
v_add_co_u32 v17, vcc_lo, s8, v17
v_lshlrev_b64 v[21:22], 3, v[21:22]
v_add_co_ci_u32_e32 v18, vcc_lo, s9, v18, vcc_lo
v_add_nc_u32_e32 v9, s35, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v23, vcc_lo, s26, v21
v_add_co_ci_u32_e32 v24, vcc_lo, s27, v22, vcc_lo
global_load_b64 v[17:18], v[17:18], off
global_load_b64 v[23:24], v[23:24], off
v_add_co_u32 v25, vcc_lo, s8, v25
v_add_co_ci_u32_e32 v26, vcc_lo, s9, v26, vcc_lo
v_add_co_u32 v27, vcc_lo, s24, v21
v_add_co_ci_u32_e32 v28, vcc_lo, s25, v22, vcc_lo
global_load_b64 v[25:26], v[25:26], off
global_load_b64 v[27:28], v[27:28], off
v_lshlrev_b64 v[29:30], 3, v[9:10]
v_add_nc_u32_e32 v9, s34, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v29, vcc_lo, s8, v29
v_add_co_ci_u32_e32 v30, vcc_lo, s9, v30, vcc_lo
v_add_co_u32 v31, vcc_lo, s28, v21
v_add_co_ci_u32_e32 v32, vcc_lo, s29, v22, vcc_lo
global_load_b64 v[29:30], v[29:30], off
global_load_b64 v[31:32], v[31:32], off
v_lshlrev_b64 v[33:34], 3, v[9:10]
v_add_nc_u32_e32 v9, s11, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v33, vcc_lo, s8, v33
v_add_co_ci_u32_e32 v34, vcc_lo, s9, v34, vcc_lo
v_add_co_u32 v35, vcc_lo, s30, v21
v_add_co_ci_u32_e32 v36, vcc_lo, s31, v22, vcc_lo
global_load_b64 v[33:34], v[33:34], off
global_load_b64 v[35:36], v[35:36], off
v_lshlrev_b64 v[37:38], 3, v[9:10]
v_add_nc_u32_e32 v9, s10, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v37, vcc_lo, s8, v37
v_add_co_ci_u32_e32 v38, vcc_lo, s9, v38, vcc_lo
v_add_co_u32 v39, vcc_lo, s16, v21
v_add_co_ci_u32_e32 v40, vcc_lo, s17, v22, vcc_lo
global_load_b64 v[37:38], v[37:38], off
global_load_b64 v[39:40], v[39:40], off
v_lshlrev_b64 v[41:42], 3, v[9:10]
v_add_nc_u32_e32 v9, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v41, vcc_lo, s8, v41
v_add_co_ci_u32_e32 v42, vcc_lo, s9, v42, vcc_lo
v_add_co_u32 v43, vcc_lo, s18, v21
v_add_co_ci_u32_e32 v44, vcc_lo, s19, v22, vcc_lo
global_load_b64 v[41:42], v[41:42], off
global_load_b64 v[43:44], v[43:44], off
v_lshlrev_b64 v[9:10], 3, v[9:10]
v_add_co_u32 v45, vcc_lo, s20, v21
v_add_co_ci_u32_e32 v46, vcc_lo, s21, v22, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v9, vcc_lo, s8, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v10, vcc_lo
global_load_b64 v[45:46], v[45:46], off
global_load_b64 v[9:10], v[9:10], off
v_add_co_u32 v21, vcc_lo, s22, v21
v_add_co_ci_u32_e32 v22, vcc_lo, s23, v22, vcc_lo
global_load_b64 v[21:22], v[21:22], off
s_waitcnt vmcnt(15)
v_mul_f64 v[19:20], v[7:8], v[19:20]
s_waitcnt vmcnt(14)
v_mul_f64 v[17:18], v[7:8], v[17:18]
s_waitcnt vmcnt(13)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_mul_f64 v[19:20], v[19:20], v[23:24]
s_waitcnt vmcnt(12)
v_mul_f64 v[23:24], v[7:8], v[25:26]
s_waitcnt vmcnt(11)
v_fma_f64 v[17:18], v[17:18], v[27:28], v[19:20]
s_waitcnt vmcnt(10)
v_mul_f64 v[19:20], v[7:8], v[29:30]
s_waitcnt vmcnt(1)
v_mul_f64 v[9:10], v[7:8], v[9:10]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[17:18], v[23:24], v[31:32], v[17:18]
v_mul_f64 v[23:24], v[7:8], v[33:34]
v_fma_f64 v[17:18], v[19:20], v[35:36], v[17:18]
v_mul_f64 v[19:20], v[7:8], v[37:38]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[17:18], v[23:24], v[39:40], v[17:18]
v_mul_f64 v[23:24], v[7:8], v[41:42]
v_fma_f64 v[17:18], v[19:20], v[43:44], v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], v[23:24], v[45:46], v[17:18]
s_waitcnt vmcnt(0)
v_fma_f64 v[9:10], v[9:10], v[21:22], v[17:18]
s_cbranch_execnz .LBB0_6
s_branch .LBB0_10
.LBB0_9:
.LBB0_10:
v_add_co_u32 v9, vcc_lo, v0, v3
v_add_co_ci_u32_e32 v10, vcc_lo, v1, v4, vcc_lo
v_dual_mov_b32 v22, 0 :: v_dual_add_nc_u32 v21, s54, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 3, v[9:10]
v_lshlrev_b64 v[23:24], 3, v[21:22]
v_add_nc_u32_e32 v21, s53, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v17, vcc_lo, s26, v9
v_add_co_ci_u32_e32 v18, vcc_lo, s27, v10, vcc_lo
v_add_co_u32 v19, vcc_lo, s46, v9
v_add_co_ci_u32_e32 v20, vcc_lo, s47, v10, vcc_lo
v_lshlrev_b64 v[25:26], 3, v[21:22]
global_load_b64 v[17:18], v[17:18], off
global_load_b64 v[19:20], v[19:20], off
v_add_co_u32 v27, vcc_lo, s24, v9
v_add_co_ci_u32_e32 v28, vcc_lo, s25, v10, vcc_lo
v_add_co_u32 v29, vcc_lo, s44, v9
v_add_co_ci_u32_e32 v30, vcc_lo, s45, v10, vcc_lo
v_add_co_u32 v25, vcc_lo, s8, v25
v_add_co_ci_u32_e32 v26, vcc_lo, s9, v26, vcc_lo
global_load_b64 v[27:28], v[27:28], off
global_load_b64 v[29:30], v[29:30], off
global_load_b64 v[25:26], v[25:26], off
v_add_co_u32 v23, vcc_lo, s8, v23
v_add_co_ci_u32_e32 v24, vcc_lo, s9, v24, vcc_lo
v_add_co_u32 v31, vcc_lo, s28, v9
v_add_co_ci_u32_e32 v32, vcc_lo, s29, v10, vcc_lo
v_add_co_u32 v33, vcc_lo, s48, v9
v_add_co_ci_u32_e32 v34, vcc_lo, s49, v10, vcc_lo
global_load_b64 v[23:24], v[23:24], off
global_load_b64 v[31:32], v[31:32], off
global_load_b64 v[33:34], v[33:34], off
v_add_nc_u32_e32 v21, s52, v3
v_add_co_u32 v35, vcc_lo, s30, v9
v_add_co_ci_u32_e32 v36, vcc_lo, s31, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[37:38], 3, v[21:22]
v_add_co_u32 v39, vcc_lo, s50, v9
v_add_co_ci_u32_e32 v40, vcc_lo, s51, v10, vcc_lo
v_add_nc_u32_e32 v21, s35, v3
v_add_co_u32 v37, vcc_lo, s8, v37
v_add_co_ci_u32_e32 v38, vcc_lo, s9, v38, vcc_lo
global_load_b64 v[35:36], v[35:36], off
global_load_b64 v[39:40], v[39:40], off
global_load_b64 v[37:38], v[37:38], off
v_add_co_u32 v41, vcc_lo, s16, v9
v_lshlrev_b64 v[43:44], 3, v[21:22]
v_add_co_ci_u32_e32 v42, vcc_lo, s17, v10, vcc_lo
v_add_co_u32 v45, vcc_lo, s36, v9
v_add_co_ci_u32_e32 v46, vcc_lo, s37, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v43, vcc_lo, s8, v43
v_add_co_ci_u32_e32 v44, vcc_lo, s9, v44, vcc_lo
global_load_b64 v[41:42], v[41:42], off
global_load_b64 v[45:46], v[45:46], off
global_load_b64 v[43:44], v[43:44], off
v_add_nc_u32_e32 v21, s34, v3
v_add_co_u32 v47, vcc_lo, s18, v9
v_add_co_ci_u32_e32 v48, vcc_lo, s19, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[49:50], 3, v[21:22]
v_add_co_u32 v51, vcc_lo, s38, v9
v_add_co_ci_u32_e32 v52, vcc_lo, s39, v10, vcc_lo
v_add_nc_u32_e32 v21, s11, v3
v_add_co_u32 v49, vcc_lo, s8, v49
v_add_co_ci_u32_e32 v50, vcc_lo, s9, v50, vcc_lo
global_load_b64 v[47:48], v[47:48], off
global_load_b64 v[51:52], v[51:52], off
global_load_b64 v[49:50], v[49:50], off
v_add_co_u32 v53, vcc_lo, s20, v9
v_lshlrev_b64 v[55:56], 3, v[21:22]
v_add_co_ci_u32_e32 v54, vcc_lo, s21, v10, vcc_lo
v_add_co_u32 v57, vcc_lo, s40, v9
v_add_co_ci_u32_e32 v58, vcc_lo, s41, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v55, vcc_lo, s8, v55
v_add_co_ci_u32_e32 v56, vcc_lo, s9, v56, vcc_lo
global_load_b64 v[53:54], v[53:54], off
global_load_b64 v[57:58], v[57:58], off
global_load_b64 v[55:56], v[55:56], off
v_add_nc_u32_e32 v21, s10, v3
v_add_co_u32 v61, vcc_lo, s22, v9
v_add_co_ci_u32_e32 v62, vcc_lo, s23, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[59:60], 3, v[21:22]
v_add_nc_u32_e32 v21, s2, v3
v_add_co_u32 v59, vcc_lo, s8, v59
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v60, vcc_lo, s9, v60, vcc_lo
v_add_co_u32 v9, vcc_lo, s42, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s43, v10, vcc_lo
global_load_b64 v[59:60], v[59:60], off
global_load_b64 v[61:62], v[61:62], off
global_load_b64 v[9:10], v[9:10], off
v_lshlrev_b64 v[21:22], 3, v[21:22]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v21, vcc_lo, s8, v21
v_add_co_ci_u32_e32 v22, vcc_lo, s9, v22, vcc_lo
global_load_b64 v[21:22], v[21:22], off
s_waitcnt vmcnt(22)
v_add_f64 v[17:18], v[17:18], v[19:20]
s_waitcnt vmcnt(20)
v_add_f64 v[19:20], v[27:28], v[29:30]
s_waitcnt vmcnt(19)
v_mul_f64 v[25:26], v[7:8], v[25:26]
s_waitcnt vmcnt(18)
v_mul_f64 v[23:24], v[7:8], v[23:24]
s_waitcnt vmcnt(16)
v_add_f64 v[27:28], v[31:32], v[33:34]
v_mul_f64 v[17:18], v[17:18], 0.5
s_waitcnt vmcnt(13)
v_mul_f64 v[29:30], v[7:8], v[37:38]
v_mul_f64 v[19:20], v[19:20], 0.5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f64 v[27:28], v[27:28], 0.5
v_mul_f64 v[17:18], v[25:26], v[17:18]
v_add_f64 v[25:26], v[35:36], v[39:40]
s_waitcnt vmcnt(1)
v_add_f64 v[9:10], v[61:62], v[9:10]
s_delay_alu instid0(VALU_DEP_3)
v_fma_f64 v[17:18], v[23:24], v[19:20], v[17:18]
v_add_f64 v[19:20], v[41:42], v[45:46]
v_mul_f64 v[23:24], v[7:8], v[43:44]
v_mul_f64 v[25:26], v[25:26], 0.5
v_mul_f64 v[9:10], v[9:10], 0.5
v_fma_f64 v[17:18], v[29:30], v[27:28], v[17:18]
v_add_f64 v[27:28], v[47:48], v[51:52]
v_mul_f64 v[29:30], v[7:8], v[49:50]
v_mul_f64 v[19:20], v[19:20], 0.5
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_fma_f64 v[17:18], v[23:24], v[25:26], v[17:18]
v_add_f64 v[23:24], v[53:54], v[57:58]
v_mul_f64 v[25:26], v[7:8], v[55:56]
v_mul_f64 v[27:28], v[27:28], 0.5
v_fma_f64 v[17:18], v[29:30], v[19:20], v[17:18]
v_mul_f64 v[19:20], v[7:8], v[59:60]
v_mul_f64 v[23:24], v[23:24], 0.5
s_waitcnt vmcnt(0)
v_mul_f64 v[7:8], v[7:8], v[21:22]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], v[25:26], v[27:28], v[17:18]
v_fma_f64 v[17:18], v[19:20], v[23:24], v[17:18]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[9:10], v[7:8], v[9:10], v[17:18]
s_branch .LBB0_6
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s57
ds_store_b64 v13, v[5:6]
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s55
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s13
s_mov_b32 s55, s33
s_waitcnt vmcnt(0) lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_vccz .LBB0_16
.LBB0_13:
s_and_saveexec_b32 s55, s0
s_cbranch_execz .LBB0_3
ds_load_b64 v[5:6], v14
s_lshl_b64 s[56:57], s[14:15], 3
s_delay_alu instid0(SALU_CYCLE_1)
v_add_co_u32 v7, vcc_lo, v15, s56
v_add_co_ci_u32_e32 v8, vcc_lo, s57, v16, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b64 v[7:8], v[5:6], off
s_branch .LBB0_3
.p2align 6
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s57
s_cmp_lt_u32 s55, 4
s_mov_b32 s55, s56
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_13
.LBB0_16:
s_lshr_b32 s56, s55, 1
s_mov_b32 s57, exec_lo
v_cmpx_gt_u32_e64 s56, v11
s_cbranch_execz .LBB0_15
v_add_nc_u32_e32 v3, s56, v12
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v3, v3, 3, 0
ds_load_b64 v[5:6], v3
ds_load_b64 v[7:8], v13
s_waitcnt lgkmcnt(0)
v_add_f64 v[5:6], v[5:6], v[7:8]
ds_store_b64 v13, v[5:6]
s_branch .LBB0_15
.LBB0_18:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 440
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 63
.amdhsa_next_free_sgpr 60
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd, .Lfunc_end0-_Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .actual_access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 56
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 64
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 80
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 88
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 96
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 104
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 112
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 120
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 128
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 136
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 144
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 152
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 160
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 168
.size: 8
.value_kind: global_buffer
- .actual_access: write_only
.address_space: global
.offset: 176
.size: 8
.value_kind: global_buffer
- .offset: 184
.size: 4
.value_kind: hidden_block_count_x
- .offset: 188
.size: 4
.value_kind: hidden_block_count_y
- .offset: 192
.size: 4
.value_kind: hidden_block_count_z
- .offset: 196
.size: 2
.value_kind: hidden_group_size_x
- .offset: 198
.size: 2
.value_kind: hidden_group_size_y
- .offset: 200
.size: 2
.value_kind: hidden_group_size_z
- .offset: 202
.size: 2
.value_kind: hidden_remainder_x
- .offset: 204
.size: 2
.value_kind: hidden_remainder_y
- .offset: 206
.size: 2
.value_kind: hidden_remainder_z
- .offset: 224
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 232
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 240
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 248
.size: 2
.value_kind: hidden_grid_dims
- .offset: 304
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 440
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd
.private_segment_fixed_size: 0
.sgpr_count: 62
.sgpr_spill_count: 0
.symbol: _Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 63
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define ANGULAR_FLUX_INDEX(a,g,i,j,k,nang,ng,nx,ny) ((a)+((nang)*(g))+((nang)*(ng)*(i))+((nang)*(ng)*(nx)*(j))+((nang)*(ng)*(nx)*(ny)*(k)))
#define SCALAR_FLUX_MOMENTS_INDEX(m,g,i,j,k,cmom,ng,nx,ny) ((m)+((cmom-1)*(g))+((cmom-1)*(ng)*(i))+((cmom-1)*(ng)*(nx)*(j))+((cmom-1)*(ng)*(nx)*(ny)*(k)))
#define SCAT_COEFF_INDEX(a,l,o,nang,cmom) ((a)+((nang)*(l))+((nang)*(cmom)*o))
#define angular_flux_in_0(a,g,i,j,k) angular_flux_in_0[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_in_1(a,g,i,j,k) angular_flux_in_1[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_in_2(a,g,i,j,k) angular_flux_in_2[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_in_3(a,g,i,j,k) angular_flux_in_3[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_in_4(a,g,i,j,k) angular_flux_in_4[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_in_5(a,g,i,j,k) angular_flux_in_5[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_in_6(a,g,i,j,k) angular_flux_in_6[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_in_7(a,g,i,j,k) angular_flux_in_7[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_0(a,g,i,j,k) angular_flux_out_0[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_1(a,g,i,j,k) angular_flux_out_1[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_2(a,g,i,j,k) angular_flux_out_2[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_3(a,g,i,j,k) angular_flux_out_3[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_4(a,g,i,j,k) angular_flux_out_4[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_5(a,g,i,j,k) angular_flux_out_5[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_6(a,g,i,j,k) angular_flux_out_6[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define angular_flux_out_7(a,g,i,j,k) angular_flux_out_7[ANGULAR_FLUX_INDEX((a),(g),(i),(j),(k),nang,ng,nx,ny)]
#define scalar_flux_moments(l,g,i,j,k) scalar_flux_moments[SCALAR_FLUX_MOMENTS_INDEX((l),(g),(i),(j),(k),cmom,ng,nx,ny)]
#define scat_coeff(a,l,o) scat_coeff[SCAT_COEFF_INDEX((a),(l),(o),nang,cmom)]
// We want to perform a weighted sum of angles in each cell in each energy group for each moment
// One work-group per cell per energy group, and reduce within a work-group
// Work-groups must be power of two sized
__global__ void reduce_flux_moments(
const unsigned int nx,
const unsigned int ny,
const unsigned int nz,
const unsigned int nang,
const unsigned int ng,
const unsigned int cmom,
const double * __restrict__ angular_flux_in_0,
const double * __restrict__ angular_flux_in_1,
const double * __restrict__ angular_flux_in_2,
const double * __restrict__ angular_flux_in_3,
const double * __restrict__ angular_flux_in_4,
const double * __restrict__ angular_flux_in_5,
const double * __restrict__ angular_flux_in_6,
const double * __restrict__ angular_flux_in_7,
const double * __restrict__ angular_flux_out_0,
const double * __restrict__ angular_flux_out_1,
const double * __restrict__ angular_flux_out_2,
const double * __restrict__ angular_flux_out_3,
const double * __restrict__ angular_flux_out_4,
const double * __restrict__ angular_flux_out_5,
const double * __restrict__ angular_flux_out_6,
const double * __restrict__ angular_flux_out_7,
const double * __restrict__ velocity_delta,
const double * __restrict__ quad_weights,
const double * __restrict__ scat_coeff,
double * __restrict__ scalar_flux_moments
)
{
extern __shared__ double local_scalar[];
const size_t a = threadIdx.x;
const size_t g = blockIdx.x;
const size_t global_id = blockIdx.y * blockDim.y + threadIdx.y;
const size_t i = global_id % nx;
const size_t j = (global_id / nx) % ny;
const size_t k = global_id / (nx * ny);
if (global_id >= nx * ny * nz) return;
for (unsigned int l = 0; l < cmom-1; l++)
{
// Load into local memory
local_scalar[a + (threadIdx.y * blockDim.x)] = 0.0;
for (unsigned int aa = a; aa < nang; aa += blockDim.x)
{
const double w = quad_weights[aa];
if (velocity_delta[g] != 0.0)
{
local_scalar[a + (threadIdx.y * blockDim.x)] +=
scat_coeff(aa,l+1,0) * w * (0.5 * (angular_flux_out_0(aa,g,i,j,k) + angular_flux_in_0(aa,g,i,j,k))) +
scat_coeff(aa,l+1,1) * w * (0.5 * (angular_flux_out_1(aa,g,i,j,k) + angular_flux_in_1(aa,g,i,j,k))) +
scat_coeff(aa,l+1,2) * w * (0.5 * (angular_flux_out_2(aa,g,i,j,k) + angular_flux_in_2(aa,g,i,j,k))) +
scat_coeff(aa,l+1,3) * w * (0.5 * (angular_flux_out_3(aa,g,i,j,k) + angular_flux_in_3(aa,g,i,j,k))) +
scat_coeff(aa,l+1,4) * w * (0.5 * (angular_flux_out_4(aa,g,i,j,k) + angular_flux_in_4(aa,g,i,j,k))) +
scat_coeff(aa,l+1,5) * w * (0.5 * (angular_flux_out_5(aa,g,i,j,k) + angular_flux_in_5(aa,g,i,j,k))) +
scat_coeff(aa,l+1,6) * w * (0.5 * (angular_flux_out_6(aa,g,i,j,k) + angular_flux_in_6(aa,g,i,j,k))) +
scat_coeff(aa,l+1,7) * w * (0.5 * (angular_flux_out_7(aa,g,i,j,k) + angular_flux_in_7(aa,g,i,j,k)));
}
else
{
local_scalar[a + (threadIdx.y * blockDim.x)] +=
scat_coeff(aa,l+1,0) * w * angular_flux_out_0(aa,g,i,j,k) +
scat_coeff(aa,l+1,1) * w * angular_flux_out_1(aa,g,i,j,k) +
scat_coeff(aa,l+1,2) * w * angular_flux_out_2(aa,g,i,j,k) +
scat_coeff(aa,l+1,3) * w * angular_flux_out_3(aa,g,i,j,k) +
scat_coeff(aa,l+1,4) * w * angular_flux_out_4(aa,g,i,j,k) +
scat_coeff(aa,l+1,5) * w * angular_flux_out_5(aa,g,i,j,k) +
scat_coeff(aa,l+1,6) * w * angular_flux_out_6(aa,g,i,j,k) +
scat_coeff(aa,l+1,7) * w * angular_flux_out_7(aa,g,i,j,k);
}
}
__syncthreads();
// Reduce in local memory
for (unsigned int offset = blockDim.x / 2; offset > 0; offset /= 2)
{
if (a < offset)
{
local_scalar[a + (threadIdx.y * blockDim.x)] += local_scalar[a + offset + (threadIdx.y * blockDim.x)];
}
__syncthreads();
}
// Save result
if (a == 0)
{
scalar_flux_moments(l,g,i,j,k) = local_scalar[0 + (threadIdx.y * blockDim.x)];
}
} // End of moment loop
} | .text
.file "reduce_flux_moments.hip"
.globl _Z34__device_stub__reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd # -- Begin function _Z34__device_stub__reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd
.p2align 4, 0x90
.type _Z34__device_stub__reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd,@function
_Z34__device_stub__reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd: # @_Z34__device_stub__reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd
.cfi_startproc
# %bb.0:
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 304
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 28(%rsp), %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 88(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 304(%rsp), %rax
movq %rax, 128(%rsp)
leaq 312(%rsp), %rax
movq %rax, 136(%rsp)
leaq 320(%rsp), %rax
movq %rax, 144(%rsp)
leaq 328(%rsp), %rax
movq %rax, 152(%rsp)
leaq 336(%rsp), %rax
movq %rax, 160(%rsp)
leaq 344(%rsp), %rax
movq %rax, 168(%rsp)
leaq 352(%rsp), %rax
movq %rax, 176(%rsp)
leaq 360(%rsp), %rax
movq %rax, 184(%rsp)
leaq 368(%rsp), %rax
movq %rax, 192(%rsp)
leaq 376(%rsp), %rax
movq %rax, 200(%rsp)
leaq 384(%rsp), %rax
movq %rax, 208(%rsp)
leaq 392(%rsp), %rax
movq %rax, 216(%rsp)
leaq 400(%rsp), %rax
movq %rax, 224(%rsp)
leaq 408(%rsp), %rax
movq %rax, 232(%rsp)
leaq 416(%rsp), %rax
movq %rax, 240(%rsp)
leaq 424(%rsp), %rax
movq %rax, 248(%rsp)
leaq 432(%rsp), %rax
movq %rax, 256(%rsp)
leaq 440(%rsp), %rax
movq %rax, 264(%rsp)
leaq 448(%rsp), %rax
movq %rax, 272(%rsp)
leaq 456(%rsp), %rax
movq %rax, 280(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $312, %rsp # imm = 0x138
.cfi_adjust_cfa_offset -312
retq
.Lfunc_end0:
.size _Z34__device_stub__reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd, .Lfunc_end0-_Z34__device_stub__reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd,@object # @_Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd
.section .rodata,"a",@progbits
.globl _Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd
.p2align 3, 0x0
_Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd:
.quad _Z34__device_stub__reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd
.size _Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd"
.size .L__unnamed_1, 89
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a1dd4_00000000-6_reduce_flux_moments.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z102__device_stub__Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_PdjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd
.type _Z102__device_stub__Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_PdjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd, @function
_Z102__device_stub__Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_PdjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd:
.LFB2051:
.cfi_startproc
endbr64
subq $488, %rsp
.cfi_def_cfa_offset 496
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 472(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 256(%rsp)
leaq 24(%rsp), %rax
movq %rax, 264(%rsp)
leaq 20(%rsp), %rax
movq %rax, 272(%rsp)
leaq 16(%rsp), %rax
movq %rax, 280(%rsp)
leaq 12(%rsp), %rax
movq %rax, 288(%rsp)
leaq 8(%rsp), %rax
movq %rax, 296(%rsp)
movq 496(%rsp), %rax
movq %rax, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 304(%rsp)
movq 504(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 312(%rsp)
movq 512(%rsp), %rax
movq %rax, 48(%rsp)
leaq 48(%rsp), %rax
movq %rax, 320(%rsp)
movq 520(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 328(%rsp)
movq 528(%rsp), %rax
movq %rax, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, 336(%rsp)
movq 536(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 344(%rsp)
movq 544(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 352(%rsp)
movq 552(%rsp), %rax
movq %rax, 88(%rsp)
leaq 88(%rsp), %rax
movq %rax, 360(%rsp)
movq 560(%rsp), %rax
movq %rax, 96(%rsp)
leaq 96(%rsp), %rax
movq %rax, 368(%rsp)
movq 568(%rsp), %rax
movq %rax, 104(%rsp)
leaq 104(%rsp), %rax
movq %rax, 376(%rsp)
movq 576(%rsp), %rax
movq %rax, 112(%rsp)
leaq 112(%rsp), %rax
movq %rax, 384(%rsp)
movq 584(%rsp), %rax
movq %rax, 120(%rsp)
leaq 120(%rsp), %rax
movq %rax, 392(%rsp)
movq 592(%rsp), %rax
movq %rax, 128(%rsp)
leaq 128(%rsp), %rax
movq %rax, 400(%rsp)
movq 600(%rsp), %rax
movq %rax, 136(%rsp)
leaq 136(%rsp), %rax
movq %rax, 408(%rsp)
movq 608(%rsp), %rax
movq %rax, 144(%rsp)
leaq 144(%rsp), %rax
movq %rax, 416(%rsp)
movq 616(%rsp), %rax
movq %rax, 152(%rsp)
leaq 152(%rsp), %rax
movq %rax, 424(%rsp)
movq 624(%rsp), %rax
movq %rax, 160(%rsp)
leaq 160(%rsp), %rax
movq %rax, 432(%rsp)
movq 632(%rsp), %rax
movq %rax, 168(%rsp)
leaq 168(%rsp), %rax
movq %rax, 440(%rsp)
movq 640(%rsp), %rax
movq %rax, 176(%rsp)
leaq 176(%rsp), %rax
movq %rax, 448(%rsp)
movq 648(%rsp), %rax
movq %rax, 184(%rsp)
leaq 184(%rsp), %rax
movq %rax, 456(%rsp)
movl $1, 208(%rsp)
movl $1, 212(%rsp)
movl $1, 216(%rsp)
movl $1, 220(%rsp)
movl $1, 224(%rsp)
movl $1, 228(%rsp)
leaq 200(%rsp), %rcx
leaq 192(%rsp), %rdx
leaq 220(%rsp), %rsi
leaq 208(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 472(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $488, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 200(%rsp)
.cfi_def_cfa_offset 504
pushq 200(%rsp)
.cfi_def_cfa_offset 512
leaq 272(%rsp), %r9
movq 236(%rsp), %rcx
movl 244(%rsp), %r8d
movq 224(%rsp), %rsi
movl 232(%rsp), %edx
leaq _Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 496
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z102__device_stub__Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_PdjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd, .-_Z102__device_stub__Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_PdjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd
.globl _Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd
.type _Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd, @function
_Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 168(%rsp)
.cfi_def_cfa_offset 24
pushq 168(%rsp)
.cfi_def_cfa_offset 32
pushq 168(%rsp)
.cfi_def_cfa_offset 40
pushq 168(%rsp)
.cfi_def_cfa_offset 48
pushq 168(%rsp)
.cfi_def_cfa_offset 56
pushq 168(%rsp)
.cfi_def_cfa_offset 64
pushq 168(%rsp)
.cfi_def_cfa_offset 72
pushq 168(%rsp)
.cfi_def_cfa_offset 80
pushq 168(%rsp)
.cfi_def_cfa_offset 88
pushq 168(%rsp)
.cfi_def_cfa_offset 96
pushq 168(%rsp)
.cfi_def_cfa_offset 104
pushq 168(%rsp)
.cfi_def_cfa_offset 112
pushq 168(%rsp)
.cfi_def_cfa_offset 120
pushq 168(%rsp)
.cfi_def_cfa_offset 128
pushq 168(%rsp)
.cfi_def_cfa_offset 136
pushq 168(%rsp)
.cfi_def_cfa_offset 144
pushq 168(%rsp)
.cfi_def_cfa_offset 152
pushq 168(%rsp)
.cfi_def_cfa_offset 160
pushq 168(%rsp)
.cfi_def_cfa_offset 168
pushq 168(%rsp)
.cfi_def_cfa_offset 176
call _Z102__device_stub__Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_PdjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd
addq $168, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd, .-_Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reduce_flux_moments.hip"
.globl _Z34__device_stub__reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd # -- Begin function _Z34__device_stub__reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd
.p2align 4, 0x90
.type _Z34__device_stub__reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd,@function
_Z34__device_stub__reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd: # @_Z34__device_stub__reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd
.cfi_startproc
# %bb.0:
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 304
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 28(%rsp), %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 88(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 304(%rsp), %rax
movq %rax, 128(%rsp)
leaq 312(%rsp), %rax
movq %rax, 136(%rsp)
leaq 320(%rsp), %rax
movq %rax, 144(%rsp)
leaq 328(%rsp), %rax
movq %rax, 152(%rsp)
leaq 336(%rsp), %rax
movq %rax, 160(%rsp)
leaq 344(%rsp), %rax
movq %rax, 168(%rsp)
leaq 352(%rsp), %rax
movq %rax, 176(%rsp)
leaq 360(%rsp), %rax
movq %rax, 184(%rsp)
leaq 368(%rsp), %rax
movq %rax, 192(%rsp)
leaq 376(%rsp), %rax
movq %rax, 200(%rsp)
leaq 384(%rsp), %rax
movq %rax, 208(%rsp)
leaq 392(%rsp), %rax
movq %rax, 216(%rsp)
leaq 400(%rsp), %rax
movq %rax, 224(%rsp)
leaq 408(%rsp), %rax
movq %rax, 232(%rsp)
leaq 416(%rsp), %rax
movq %rax, 240(%rsp)
leaq 424(%rsp), %rax
movq %rax, 248(%rsp)
leaq 432(%rsp), %rax
movq %rax, 256(%rsp)
leaq 440(%rsp), %rax
movq %rax, 264(%rsp)
leaq 448(%rsp), %rax
movq %rax, 272(%rsp)
leaq 456(%rsp), %rax
movq %rax, 280(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $312, %rsp # imm = 0x138
.cfi_adjust_cfa_offset -312
retq
.Lfunc_end0:
.size _Z34__device_stub__reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd, .Lfunc_end0-_Z34__device_stub__reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd,@object # @_Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd
.section .rodata,"a",@progbits
.globl _Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd
.p2align 3, 0x0
_Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd:
.quad _Z34__device_stub__reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd
.size _Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd"
.size .L__unnamed_1, 89
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19reduce_flux_momentsjjjjjjPKdS0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_S0_Pd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void gpu_reduce(int *c, int size)
{
/*Identificaciones necesarios*/
int IDX_Thread = threadIdx.x;
int IDY_Thread = threadIdx.y;
int IDX_block = blockIdx.x;
int IDY_block = blockIdx.y;
int shapeGrid_X = gridDim.x;
int threads_per_block = blockDim.x * blockDim.y;
int position = threads_per_block * ((IDY_block * shapeGrid_X)+IDX_block)+((IDY_Thread*blockDim.x)+IDX_Thread);
if(position<size){
if(size%2 != 0)
{
if(c[position]<c[size-1])
{
c[position]=c[size-1];
}
}else{
if(c[position]<c[position+size/2])
{
c[position]=c[position+size/2];
}
}
}
} | code for sm_80
Function : _Z10gpu_reducePii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002200 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x002fc800078e0205 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x004fca00078e0207 */
/*0080*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R2, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff027435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ LOP3.LUT R2, R2, c[0x0][0x168], RZ, 0xc0, !PT ; /* 0x00005a0002027a12 */
/* 0x000fc800078ec0ff */
/*00e0*/ ISETP.NE.U32.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f05070 */
/*00f0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0205 */
/*0100*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x00016e000c1e1900 */
/*0110*/ @P0 BRA 0x1a0 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*0120*/ MOV R4, 0x1 ; /* 0x0000000100047802 */
/* 0x000fc80000000f00 */
/*0130*/ IADD3 R4, -R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fca0007ffe1ff */
/*0140*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0205 */
/*0150*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0160*/ ISETP.GE.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x024fda0003f06270 */
/*0170*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0180*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fca00078e00ff */
/*01b0*/ LEA.HI R4, R4, c[0x0][0x168], RZ, 0x1 ; /* 0x00005a0004047a11 */
/* 0x000fc800078f08ff */
/*01c0*/ SHF.R.S32.HI R5, RZ, 0x1, R4 ; /* 0x00000001ff057819 */
/* 0x000fca0000011404 */
/*01d0*/ IMAD.WIDE R4, R5, 0x4, R2 ; /* 0x0000000405047825 */
/* 0x000fcc00078e0202 */
/*01e0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*01f0*/ ISETP.GE.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x024fda0003f06270 */
/*0200*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0210*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void gpu_reduce(int *c, int size)
{
/*Identificaciones necesarios*/
int IDX_Thread = threadIdx.x;
int IDY_Thread = threadIdx.y;
int IDX_block = blockIdx.x;
int IDY_block = blockIdx.y;
int shapeGrid_X = gridDim.x;
int threads_per_block = blockDim.x * blockDim.y;
int position = threads_per_block * ((IDY_block * shapeGrid_X)+IDX_block)+((IDY_Thread*blockDim.x)+IDX_Thread);
if(position<size){
if(size%2 != 0)
{
if(c[position]<c[size-1])
{
c[position]=c[size-1];
}
}else{
if(c[position]<c[position+size/2])
{
c[position]=c[position+size/2];
}
}
}
} | .file "tmpxft_0014608c_00000000-6_gpu_reduce.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z10gpu_reducePiiPii
.type _Z31__device_stub__Z10gpu_reducePiiPii, @function
_Z31__device_stub__Z10gpu_reducePiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10gpu_reducePii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z10gpu_reducePiiPii, .-_Z31__device_stub__Z10gpu_reducePiiPii
.globl _Z10gpu_reducePii
.type _Z10gpu_reducePii, @function
_Z10gpu_reducePii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z10gpu_reducePiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10gpu_reducePii, .-_Z10gpu_reducePii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10gpu_reducePii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10gpu_reducePii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void gpu_reduce(int *c, int size)
{
/*Identificaciones necesarios*/
int IDX_Thread = threadIdx.x;
int IDY_Thread = threadIdx.y;
int IDX_block = blockIdx.x;
int IDY_block = blockIdx.y;
int shapeGrid_X = gridDim.x;
int threads_per_block = blockDim.x * blockDim.y;
int position = threads_per_block * ((IDY_block * shapeGrid_X)+IDX_block)+((IDY_Thread*blockDim.x)+IDX_Thread);
if(position<size){
if(size%2 != 0)
{
if(c[position]<c[size-1])
{
c[position]=c[size-1];
}
}else{
if(c[position]<c[position+size/2])
{
c[position]=c[position+size/2];
}
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gpu_reduce(int *c, int size)
{
/*Identificaciones necesarios*/
int IDX_Thread = threadIdx.x;
int IDY_Thread = threadIdx.y;
int IDX_block = blockIdx.x;
int IDY_block = blockIdx.y;
int shapeGrid_X = gridDim.x;
int threads_per_block = blockDim.x * blockDim.y;
int position = threads_per_block * ((IDY_block * shapeGrid_X)+IDX_block)+((IDY_Thread*blockDim.x)+IDX_Thread);
if(position<size){
if(size%2 != 0)
{
if(c[position]<c[size-1])
{
c[position]=c[size-1];
}
}else{
if(c[position]<c[position+size/2])
{
c[position]=c[position+size/2];
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gpu_reduce(int *c, int size)
{
/*Identificaciones necesarios*/
int IDX_Thread = threadIdx.x;
int IDY_Thread = threadIdx.y;
int IDX_block = blockIdx.x;
int IDY_block = blockIdx.y;
int shapeGrid_X = gridDim.x;
int threads_per_block = blockDim.x * blockDim.y;
int position = threads_per_block * ((IDY_block * shapeGrid_X)+IDX_block)+((IDY_Thread*blockDim.x)+IDX_Thread);
if(position<size){
if(size%2 != 0)
{
if(c[position]<c[size-1])
{
c[position]=c[size-1];
}
}else{
if(c[position]<c[position+size/2])
{
c[position]=c[position+size/2];
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10gpu_reducePii
.globl _Z10gpu_reducePii
.p2align 8
.type _Z10gpu_reducePii,@function
_Z10gpu_reducePii:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x10
s_load_b32 s4, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x8
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_lshr_b32 s5, s4, 16
s_add_i32 s3, s3, s14
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[4:5], null, s3, s5, v[1:2]
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, v4, s3, v[0:1]
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_7
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v2
s_bitcmp0_b32 s2, 0
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v3, v[0:1], off
s_cbranch_scc1 .LBB0_4
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[2:3], 2
s_add_u32 s3, s0, s4
s_addc_u32 s5, s1, s5
s_add_u32 s4, s3, -4
s_addc_u32 s5, s5, -1
s_load_b32 s4, s[4:5], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s4, v3
s_and_b32 s3, vcc_lo, exec_lo
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v4, s4
s_and_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_6
s_branch .LBB0_7
.LBB0_4:
.LBB0_5:
s_ashr_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, s2, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_and_not1_b32 s0, s3, exec_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v3, v4
s_and_b32 s1, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s3, s0, s1
s_and_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_7
.LBB0_6:
global_store_b32 v[0:1], v4, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10gpu_reducePii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10gpu_reducePii, .Lfunc_end0-_Z10gpu_reducePii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10gpu_reducePii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10gpu_reducePii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gpu_reduce(int *c, int size)
{
/*Identificaciones necesarios*/
int IDX_Thread = threadIdx.x;
int IDY_Thread = threadIdx.y;
int IDX_block = blockIdx.x;
int IDY_block = blockIdx.y;
int shapeGrid_X = gridDim.x;
int threads_per_block = blockDim.x * blockDim.y;
int position = threads_per_block * ((IDY_block * shapeGrid_X)+IDX_block)+((IDY_Thread*blockDim.x)+IDX_Thread);
if(position<size){
if(size%2 != 0)
{
if(c[position]<c[size-1])
{
c[position]=c[size-1];
}
}else{
if(c[position]<c[position+size/2])
{
c[position]=c[position+size/2];
}
}
}
} | .text
.file "gpu_reduce.hip"
.globl _Z25__device_stub__gpu_reducePii # -- Begin function _Z25__device_stub__gpu_reducePii
.p2align 4, 0x90
.type _Z25__device_stub__gpu_reducePii,@function
_Z25__device_stub__gpu_reducePii: # @_Z25__device_stub__gpu_reducePii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10gpu_reducePii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__gpu_reducePii, .Lfunc_end0-_Z25__device_stub__gpu_reducePii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10gpu_reducePii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10gpu_reducePii,@object # @_Z10gpu_reducePii
.section .rodata,"a",@progbits
.globl _Z10gpu_reducePii
.p2align 3, 0x0
_Z10gpu_reducePii:
.quad _Z25__device_stub__gpu_reducePii
.size _Z10gpu_reducePii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10gpu_reducePii"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__gpu_reducePii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10gpu_reducePii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10gpu_reducePii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002200 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x002fc800078e0205 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x004fca00078e0207 */
/*0080*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R2, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff027435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ LOP3.LUT R2, R2, c[0x0][0x168], RZ, 0xc0, !PT ; /* 0x00005a0002027a12 */
/* 0x000fc800078ec0ff */
/*00e0*/ ISETP.NE.U32.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f05070 */
/*00f0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0205 */
/*0100*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x00016e000c1e1900 */
/*0110*/ @P0 BRA 0x1a0 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*0120*/ MOV R4, 0x1 ; /* 0x0000000100047802 */
/* 0x000fc80000000f00 */
/*0130*/ IADD3 R4, -R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fca0007ffe1ff */
/*0140*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fcc00078e0205 */
/*0150*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0160*/ ISETP.GE.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x024fda0003f06270 */
/*0170*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0180*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fca00078e00ff */
/*01b0*/ LEA.HI R4, R4, c[0x0][0x168], RZ, 0x1 ; /* 0x00005a0004047a11 */
/* 0x000fc800078f08ff */
/*01c0*/ SHF.R.S32.HI R5, RZ, 0x1, R4 ; /* 0x00000001ff057819 */
/* 0x000fca0000011404 */
/*01d0*/ IMAD.WIDE R4, R5, 0x4, R2 ; /* 0x0000000405047825 */
/* 0x000fcc00078e0202 */
/*01e0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*01f0*/ ISETP.GE.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x024fda0003f06270 */
/*0200*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0210*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10gpu_reducePii
.globl _Z10gpu_reducePii
.p2align 8
.type _Z10gpu_reducePii,@function
_Z10gpu_reducePii:
s_clause 0x2
s_load_b32 s3, s[0:1], 0x10
s_load_b32 s4, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x8
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_lshr_b32 s5, s4, 16
s_add_i32 s3, s3, s14
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[4:5], null, s3, s5, v[1:2]
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, v4, s3, v[0:1]
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_7
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v2
s_bitcmp0_b32 s2, 0
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v3, v[0:1], off
s_cbranch_scc1 .LBB0_4
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[2:3], 2
s_add_u32 s3, s0, s4
s_addc_u32 s5, s1, s5
s_add_u32 s4, s3, -4
s_addc_u32 s5, s5, -1
s_load_b32 s4, s[4:5], 0x0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s4, v3
s_and_b32 s3, vcc_lo, exec_lo
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v4, s4
s_and_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_6
s_branch .LBB0_7
.LBB0_4:
.LBB0_5:
s_ashr_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, s2, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_and_not1_b32 s0, s3, exec_lo
global_load_b32 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_cmp_lt_i32_e32 vcc_lo, v3, v4
s_and_b32 s1, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s3, s0, s1
s_and_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_7
.LBB0_6:
global_store_b32 v[0:1], v4, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10gpu_reducePii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10gpu_reducePii, .Lfunc_end0-_Z10gpu_reducePii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10gpu_reducePii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10gpu_reducePii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014608c_00000000-6_gpu_reduce.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z10gpu_reducePiiPii
.type _Z31__device_stub__Z10gpu_reducePiiPii, @function
_Z31__device_stub__Z10gpu_reducePiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10gpu_reducePii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z10gpu_reducePiiPii, .-_Z31__device_stub__Z10gpu_reducePiiPii
.globl _Z10gpu_reducePii
.type _Z10gpu_reducePii, @function
_Z10gpu_reducePii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z10gpu_reducePiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10gpu_reducePii, .-_Z10gpu_reducePii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10gpu_reducePii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10gpu_reducePii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpu_reduce.hip"
.globl _Z25__device_stub__gpu_reducePii # -- Begin function _Z25__device_stub__gpu_reducePii
.p2align 4, 0x90
.type _Z25__device_stub__gpu_reducePii,@function
_Z25__device_stub__gpu_reducePii: # @_Z25__device_stub__gpu_reducePii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10gpu_reducePii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__gpu_reducePii, .Lfunc_end0-_Z25__device_stub__gpu_reducePii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10gpu_reducePii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10gpu_reducePii,@object # @_Z10gpu_reducePii
.section .rodata,"a",@progbits
.globl _Z10gpu_reducePii
.p2align 3, 0x0
_Z10gpu_reducePii:
.quad _Z25__device_stub__gpu_reducePii
.size _Z10gpu_reducePii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10gpu_reducePii"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__gpu_reducePii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10gpu_reducePii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <unistd.h>
#define TILE_SIZE 14
#define KERNEL_SIZE 5
#define BLOCK_SIZE (TILE_SIZE + (KERNEL_SIZE - 1))
// global variable, outsize any function
__constant__ float Mc[KERNEL_SIZE][KERNEL_SIZE];
__global__ void Convolution2D(float* d_M, float* d_N, float* d_P,int M_Width_row,int M_Width_col,int P_Width_row,int P_Width_col){
int tx = threadIdx.x;
int ty = threadIdx.y;
int row_o = blockIdx.y * TILE_SIZE + ty;
int col_o = blockIdx.x * TILE_SIZE + tx;
int row_i =row_o - ((KERNEL_SIZE - 1) / 2); // Assumes kernel size is 3
int col_i =col_o - ((KERNEL_SIZE - 1) / 2); // Assumes kernel size is 3
int i=0;
int j=0;
float output = 0.0f;
__shared__ float Ms[TILE_SIZE+KERNEL_SIZE-1][TILE_SIZE+KERNEL_SIZE-1];
if((row_i >= 0) && (row_i < M_Width_row) && (col_i >= 0) && (col_i < M_Width_col)){
Ms[ty][tx] = d_M[row_i*M_Width_col + col_i];
}
else{
Ms[ty][tx] = 0.0f;
}
if(ty < TILE_SIZE && tx < TILE_SIZE){
for(i = 0; i < KERNEL_SIZE; i++){
for(j = 0; j < KERNEL_SIZE; j++){
output += Mc[i][j] * Ms[i+ty][j+tx];
//printf("Mc[%d][%d]:%f Ms[%d][%d]:%f\n",i,j,Mc[i][j],i+ty,j+tx,Ms[i+ty][j+tx]);
}
}
// some threads do not write output
if(row_o < P_Width_row && col_o < P_Width_col){
d_P[row_o * P_Width_col + col_o] = output;
}
}
}
void verification(const float *N, const float *M, const float *P, int Rows, int Columns) ;
int main(int argc,char **argv){
float *d_M,*d_N,*d_P;
float *h_M,*h_N,*h_P;
// cudaEvent_t start,end;
// float time_ms=0;
// cudaEventCreate(&start);
// cudaEventCreate(&end);
h_M=(float*)malloc(sizeof(float)*TILE_SIZE*TILE_SIZE );
h_N=(float*)malloc(sizeof(float)*KERNEL_SIZE*KERNEL_SIZE);
h_P=(float*)malloc(sizeof(float)*TILE_SIZE*TILE_SIZE);
memset(h_P, 0,TILE_SIZE * TILE_SIZE * sizeof(float));
for(int i=0;i<TILE_SIZE*TILE_SIZE;i++){
h_M[i]=i+1;
}
for(int i=0;i<KERNEL_SIZE*KERNEL_SIZE;i++){
h_N[i]=100+i;
}
cudaMalloc((void**)&d_M, sizeof(float) *TILE_SIZE*TILE_SIZE);
cudaMalloc((void**)&d_N, sizeof(float) *KERNEL_SIZE*KERNEL_SIZE);
cudaMalloc((void**)&d_P, sizeof(float) *TILE_SIZE*TILE_SIZE);
cudaMemcpy(d_M,h_M,TILE_SIZE*TILE_SIZE*sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(d_P,h_P,TILE_SIZE*TILE_SIZE*sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(Mc, h_N, sizeof(float) * KERNEL_SIZE * KERNEL_SIZE,0,cudaMemcpyHostToDevice);
dim3 dimBlock(TILE_SIZE + (KERNEL_SIZE - 1), TILE_SIZE + (KERNEL_SIZE - 1));
// cudaEventRecord(start,0);
Convolution2D<<< 1,dimBlock>>>(d_M,d_N,d_P,TILE_SIZE,TILE_SIZE,TILE_SIZE,TILE_SIZE);
// cudaEventRecord(end,0);
//printf("Execution time for Cuda Convolution2D: %.2f ms \n\n",time_ms);
cudaMemcpy(h_P,d_P,TILE_SIZE*TILE_SIZE*sizeof(float),cudaMemcpyDeviceToHost);
verification(h_M, h_N, h_P, TILE_SIZE, TILE_SIZE);
free(h_P);
free(h_M);
free(h_N);
cudaFree(d_P);
cudaFree(d_M);
cudaFree(d_N);
return 0;
}
void verification(const float *N, const float *M, const float *P, int Rows, int Columns) {
int r, c, h, w;
int row_i, col_i;
bool equal;
float* results;
results = (float*)malloc(Rows * Columns * sizeof(float));
memset(results, 0, Rows * Columns * sizeof(float));
for (r = 0; r < Rows; r++) {
for (c = 0; c < Columns; c++) {
for (h = 0; h < KERNEL_SIZE; h++) {
for (w = 0; w < KERNEL_SIZE; w++) {
row_i = r - ((KERNEL_SIZE - 1) / 2) + h;
col_i = c - ((KERNEL_SIZE - 1) / 2) + w;
if ((row_i >= 0) && (row_i < Rows) && (col_i >= 0) && (col_i < Columns)) {
results[r*Columns + c] += (M[h*KERNEL_SIZE + w] * N[row_i*Columns + col_i]);
}
}
}
}
}
equal = true;
for (int i = 0; i < Rows * Columns && equal; i++) {
//printf("results[%d]:%f P[%d]:%f\n",i,results[i],i,P[i]);
if (abs(results[i] - P[i]) >= 0.001f) {
equal = false;
printf("NOT EQUAL!\n");
}
}
if (equal) {
printf("Results are equal!\n");
}
else {
printf("Results are NOT equal!\n");
}
free(results);
return;
}
#include <iostream>
#define MASK_WIDTH 3
#define MASK_RADIUS MASK_WIDTH / 2
#define TILE_WIDTH 8
#define W (TILE_WIDTH + MASK_WIDTH - 1)
/**
* GPU 2D Convolution using shared memory
*/ | code for sm_80
Function : _Z13Convolution2DPfS_S_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0040*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e680000002100 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0060*/ IMAD R0, R0, 0xe, R9 ; /* 0x0000000e00007824 */
/* 0x001fca00078e0209 */
/*0070*/ IADD3 R2, R0, -0x2, RZ ; /* 0xfffffffe00027810 */
/* 0x000fe20007ffe0ff */
/*0080*/ IMAD R3, R3, 0xe, R6 ; /* 0x0000000e03037824 */
/* 0x002fc600078e0206 */
/*0090*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x000fc80003f06270 */
/*00a0*/ ISETP.GT.AND P0, PT, R0, 0x1, !P0 ; /* 0x000000010000780c */
/* 0x000fe40004704270 */
/*00b0*/ IADD3 R5, R3.reuse, -0x2, RZ ; /* 0xfffffffe03057810 */
/* 0x040fe40007ffe0ff */
/*00c0*/ ISETP.GT.AND P0, PT, R3, 0x1, P0 ; /* 0x000000010300780c */
/* 0x000fc80000704270 */
/*00d0*/ ISETP.LT.AND P0, PT, R5, c[0x0][0x17c], P0 ; /* 0x00005f0005007a0c */
/* 0x000fda0000701270 */
/*00e0*/ @P0 MOV R4, 0x4 ; /* 0x0000000400040802 */
/* 0x000fe20000000f00 */
/*00f0*/ @P0 IMAD R5, R2, c[0x0][0x17c], R5 ; /* 0x00005f0002050a24 */
/* 0x000fe200078e0205 */
/*0100*/ @!P0 MOV R7, RZ ; /* 0x000000ff00078202 */
/* 0x000fc60000000f00 */
/*0110*/ @P0 IMAD.WIDE R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005040625 */
/* 0x000fca00078e0204 */
/*0120*/ @P0 LDG.E R7, [R4.64] ; /* 0x0000000404070981 */
/* 0x000ea2000c1e1900 */
/*0130*/ ISETP.GT.AND P1, PT, R6, 0xd, PT ; /* 0x0000000d0600780c */
/* 0x000fe20003f24270 */
/*0140*/ IMAD R2, R9, 0x12, R6 ; /* 0x0000001209027824 */
/* 0x000fc600078e0206 */
/*0150*/ ISETP.GT.OR P1, PT, R9, 0xd, P1 ; /* 0x0000000d0900780c */
/* 0x000fe40000f24670 */
/*0160*/ @!P0 STS [R2.X4], RZ ; /* 0x000000ff02008388 */
/* 0x0001e80000004800 */
/*0170*/ @P0 STS [R2.X4], R7 ; /* 0x0000000702000388 */
/* 0x0041ee0000004800 */
/*0180*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0190*/ LDS R6, [R2.X4+0x4] ; /* 0x0000040002067984 */
/* 0x000e620000004800 */
/*01a0*/ FFMA R7, R7, c[0x3][0x0], RZ ; /* 0x00c0000007077a23 */
/* 0x001fe200000000ff */
/*01b0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x184], PT ; /* 0x0000610003007a0c */
/* 0x000fc40003f06270 */
/*01c0*/ LDS R8, [R2.X4+0x8] ; /* 0x0000080002087984 */
/* 0x000e240000004800 */
/*01d0*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x180], P0 ; /* 0x0000600000007a0c */
/* 0x000fe40000706670 */
/*01e0*/ LDS R9, [R2.X4+0xc] ; /* 0x00000c0002097984 */
/* 0x000ea80000004800 */
/*01f0*/ LDS R10, [R2.X4+0x10] ; /* 0x00001000020a7984 */
/* 0x000ee80000004800 */
/*0200*/ LDS R11, [R2.X4+0x48] ; /* 0x00004800020b7984 */
/* 0x000f280000004800 */
/*0210*/ LDS R12, [R2.X4+0x4c] ; /* 0x00004c00020c7984 */
/* 0x000f680000004800 */
/*0220*/ LDS R13, [R2.X4+0x50] ; /* 0x00005000020d7984 */
/* 0x000f680000004800 */
/*0230*/ LDS R14, [R2.X4+0x54] ; /* 0x00005400020e7984 */
/* 0x000f680000004800 */
/*0240*/ LDS R4, [R2.X4+0x58] ; /* 0x0000580002047984 */
/* 0x000f680000004800 */
/*0250*/ LDS R5, [R2.X4+0x90] ; /* 0x0000900002057984 */
/* 0x000f620000004800 */
/*0260*/ FFMA R7, R6, c[0x3][0x4], R7 ; /* 0x00c0010006077a23 */
/* 0x002fc60000000007 */
/*0270*/ LDS R16, [R2.X4+0xe8] ; /* 0x0000e80002107984 */
/* 0x000fe20000004800 */
/*0280*/ FFMA R8, R8, c[0x3][0x8], R7 ; /* 0x00c0020008087a23 */
/* 0x001fc60000000007 */
/*0290*/ LDS R6, [R2.X4+0x94] ; /* 0x0000940002067984 */
/* 0x000e220000004800 */
/*02a0*/ FFMA R9, R9, c[0x3][0xc], R8 ; /* 0x00c0030009097a23 */
/* 0x004fc60000000008 */
/*02b0*/ LDS R7, [R2.X4+0x98] ; /* 0x0000980002077984 */
/* 0x000e620000004800 */
/*02c0*/ FFMA R10, R10, c[0x3][0x10], R9 ; /* 0x00c004000a0a7a23 */
/* 0x008fc60000000009 */
/*02d0*/ LDS R8, [R2.X4+0x9c] ; /* 0x00009c0002087984 */
/* 0x000ea20000004800 */
/*02e0*/ FFMA R11, R11, c[0x3][0x14], R10 ; /* 0x00c005000b0b7a23 */
/* 0x010fc6000000000a */
/*02f0*/ LDS R9, [R2.X4+0xa0] ; /* 0x0000a00002097984 */
/* 0x000ee20000004800 */
/*0300*/ FFMA R12, R12, c[0x3][0x18], R11 ; /* 0x00c006000c0c7a23 */
/* 0x020fc6000000000b */
/*0310*/ LDS R10, [R2.X4+0xd8] ; /* 0x0000d800020a7984 */
/* 0x000f220000004800 */
/*0320*/ FFMA R13, R13, c[0x3][0x1c], R12 ; /* 0x00c007000d0d7a23 */
/* 0x000fc6000000000c */
/*0330*/ LDS R11, [R2.X4+0xdc] ; /* 0x0000dc00020b7984 */
/* 0x000f620000004800 */
/*0340*/ FFMA R13, R14, c[0x3][0x20], R13 ; /* 0x00c008000e0d7a23 */
/* 0x000fc6000000000d */
/*0350*/ LDS R12, [R2.X4+0xe0] ; /* 0x0000e000020c7984 */
/* 0x000f620000004800 */
/*0360*/ FFMA R4, R4, c[0x3][0x24], R13 ; /* 0x00c0090004047a23 */
/* 0x000fc6000000000d */
/*0370*/ LDS R14, [R2.X4+0xe4] ; /* 0x0000e400020e7984 */
/* 0x000f620000004800 */
/*0380*/ FFMA R5, R5, c[0x3][0x28], R4 ; /* 0x00c00a0005057a23 */
/* 0x000fc60000000004 */
/*0390*/ LDS R13, [R2.X4+0x128] ; /* 0x00012800020d7984 */
/* 0x000fe80000004800 */
/*03a0*/ LDS R4, [R2.X4+0x120] ; /* 0x0001200002047984 */
/* 0x000f620000004800 */
/*03b0*/ FFMA R6, R6, c[0x3][0x2c], R5 ; /* 0x00c00b0006067a23 */
/* 0x001fc60000000005 */
/*03c0*/ LDS R5, [R2.X4+0x124] ; /* 0x0001240002057984 */
/* 0x000e220000004800 */
/*03d0*/ FFMA R7, R7, c[0x3][0x30], R6 ; /* 0x00c00c0007077a23 */
/* 0x002fc80000000006 */
/*03e0*/ FFMA R8, R8, c[0x3][0x34], R7 ; /* 0x00c00d0008087a23 */
/* 0x004fe40000000007 */
/*03f0*/ LDS R7, [R2.X4+0x12c] ; /* 0x00012c0002077984 */
/* 0x0002a40000004800 */
/*0400*/ FFMA R9, R9, c[0x3][0x38], R8 ; /* 0x00c00e0009097a23 */
/* 0x008fc80000000008 */
/*0410*/ FFMA R10, R10, c[0x3][0x3c], R9 ; /* 0x00c00f000a0a7a23 */
/* 0x010fe40000000009 */
/*0420*/ LDS R9, [R2.X4+0x130] ; /* 0x0001300002097984 */
/* 0x0002e40000004800 */
/*0430*/ FFMA R11, R11, c[0x3][0x40], R10 ; /* 0x00c010000b0b7a23 */
/* 0x020fc8000000000a */
/*0440*/ FFMA R11, R12, c[0x3][0x44], R11 ; /* 0x00c011000c0b7a23 */
/* 0x000fc8000000000b */
/*0450*/ FFMA R11, R14, c[0x3][0x48], R11 ; /* 0x00c012000e0b7a23 */
/* 0x000fc8000000000b */
/*0460*/ FFMA R11, R16, c[0x3][0x4c], R11 ; /* 0x00c01300100b7a23 */
/* 0x000fc8000000000b */
/*0470*/ FFMA R4, R4, c[0x3][0x50], R11 ; /* 0x00c0140004047a23 */
/* 0x000fc8000000000b */
/*0480*/ FFMA R4, R5, c[0x3][0x54], R4 ; /* 0x00c0150005047a23 */
/* 0x001fc80000000004 */
/*0490*/ FFMA R4, R13, c[0x3][0x58], R4 ; /* 0x00c016000d047a23 */
/* 0x000fe20000000004 */
/*04a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fec0003800000 */
/*04b0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x002fe200000001ff */
/*04c0*/ IMAD R3, R0, c[0x0][0x184], R3 ; /* 0x0000610000037a24 */
/* 0x000fe400078e0203 */
/*04d0*/ FFMA R4, R7, c[0x3][0x5c], R4 ; /* 0x00c0170007047a23 */
/* 0x004fc80000000004 */
/*04e0*/ FFMA R9, R9, c[0x3][0x60], R4 ; /* 0x00c0180009097a23 */
/* 0x008fc60000000004 */
/*04f0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0500*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*0510*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0520*/ BRA 0x520; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <unistd.h>
#define TILE_SIZE 14
#define KERNEL_SIZE 5
#define BLOCK_SIZE (TILE_SIZE + (KERNEL_SIZE - 1))
// global variable, outsize any function
__constant__ float Mc[KERNEL_SIZE][KERNEL_SIZE];
__global__ void Convolution2D(float* d_M, float* d_N, float* d_P,int M_Width_row,int M_Width_col,int P_Width_row,int P_Width_col){
int tx = threadIdx.x;
int ty = threadIdx.y;
int row_o = blockIdx.y * TILE_SIZE + ty;
int col_o = blockIdx.x * TILE_SIZE + tx;
int row_i =row_o - ((KERNEL_SIZE - 1) / 2); // Assumes kernel size is 3
int col_i =col_o - ((KERNEL_SIZE - 1) / 2); // Assumes kernel size is 3
int i=0;
int j=0;
float output = 0.0f;
__shared__ float Ms[TILE_SIZE+KERNEL_SIZE-1][TILE_SIZE+KERNEL_SIZE-1];
if((row_i >= 0) && (row_i < M_Width_row) && (col_i >= 0) && (col_i < M_Width_col)){
Ms[ty][tx] = d_M[row_i*M_Width_col + col_i];
}
else{
Ms[ty][tx] = 0.0f;
}
if(ty < TILE_SIZE && tx < TILE_SIZE){
for(i = 0; i < KERNEL_SIZE; i++){
for(j = 0; j < KERNEL_SIZE; j++){
output += Mc[i][j] * Ms[i+ty][j+tx];
//printf("Mc[%d][%d]:%f Ms[%d][%d]:%f\n",i,j,Mc[i][j],i+ty,j+tx,Ms[i+ty][j+tx]);
}
}
// some threads do not write output
if(row_o < P_Width_row && col_o < P_Width_col){
d_P[row_o * P_Width_col + col_o] = output;
}
}
}
void verification(const float *N, const float *M, const float *P, int Rows, int Columns) ;
int main(int argc,char **argv){
float *d_M,*d_N,*d_P;
float *h_M,*h_N,*h_P;
// cudaEvent_t start,end;
// float time_ms=0;
// cudaEventCreate(&start);
// cudaEventCreate(&end);
h_M=(float*)malloc(sizeof(float)*TILE_SIZE*TILE_SIZE );
h_N=(float*)malloc(sizeof(float)*KERNEL_SIZE*KERNEL_SIZE);
h_P=(float*)malloc(sizeof(float)*TILE_SIZE*TILE_SIZE);
memset(h_P, 0,TILE_SIZE * TILE_SIZE * sizeof(float));
for(int i=0;i<TILE_SIZE*TILE_SIZE;i++){
h_M[i]=i+1;
}
for(int i=0;i<KERNEL_SIZE*KERNEL_SIZE;i++){
h_N[i]=100+i;
}
cudaMalloc((void**)&d_M, sizeof(float) *TILE_SIZE*TILE_SIZE);
cudaMalloc((void**)&d_N, sizeof(float) *KERNEL_SIZE*KERNEL_SIZE);
cudaMalloc((void**)&d_P, sizeof(float) *TILE_SIZE*TILE_SIZE);
cudaMemcpy(d_M,h_M,TILE_SIZE*TILE_SIZE*sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(d_P,h_P,TILE_SIZE*TILE_SIZE*sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(Mc, h_N, sizeof(float) * KERNEL_SIZE * KERNEL_SIZE,0,cudaMemcpyHostToDevice);
dim3 dimBlock(TILE_SIZE + (KERNEL_SIZE - 1), TILE_SIZE + (KERNEL_SIZE - 1));
// cudaEventRecord(start,0);
Convolution2D<<< 1,dimBlock>>>(d_M,d_N,d_P,TILE_SIZE,TILE_SIZE,TILE_SIZE,TILE_SIZE);
// cudaEventRecord(end,0);
//printf("Execution time for Cuda Convolution2D: %.2f ms \n\n",time_ms);
cudaMemcpy(h_P,d_P,TILE_SIZE*TILE_SIZE*sizeof(float),cudaMemcpyDeviceToHost);
verification(h_M, h_N, h_P, TILE_SIZE, TILE_SIZE);
free(h_P);
free(h_M);
free(h_N);
cudaFree(d_P);
cudaFree(d_M);
cudaFree(d_N);
return 0;
}
void verification(const float *N, const float *M, const float *P, int Rows, int Columns) {
int r, c, h, w;
int row_i, col_i;
bool equal;
float* results;
results = (float*)malloc(Rows * Columns * sizeof(float));
memset(results, 0, Rows * Columns * sizeof(float));
for (r = 0; r < Rows; r++) {
for (c = 0; c < Columns; c++) {
for (h = 0; h < KERNEL_SIZE; h++) {
for (w = 0; w < KERNEL_SIZE; w++) {
row_i = r - ((KERNEL_SIZE - 1) / 2) + h;
col_i = c - ((KERNEL_SIZE - 1) / 2) + w;
if ((row_i >= 0) && (row_i < Rows) && (col_i >= 0) && (col_i < Columns)) {
results[r*Columns + c] += (M[h*KERNEL_SIZE + w] * N[row_i*Columns + col_i]);
}
}
}
}
}
equal = true;
for (int i = 0; i < Rows * Columns && equal; i++) {
//printf("results[%d]:%f P[%d]:%f\n",i,results[i],i,P[i]);
if (abs(results[i] - P[i]) >= 0.001f) {
equal = false;
printf("NOT EQUAL!\n");
}
}
if (equal) {
printf("Results are equal!\n");
}
else {
printf("Results are NOT equal!\n");
}
free(results);
return;
}
#include <iostream>
#define MASK_WIDTH 3
#define MASK_RADIUS MASK_WIDTH / 2
#define TILE_WIDTH 8
#define W (TILE_WIDTH + MASK_WIDTH - 1)
/**
* GPU 2D Convolution using shared memory
*/ | .file "tmpxft_000c3c3e_00000000-6_lab6.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3686:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3686:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "NOT EQUAL!\n"
.LC3:
.string "Results are NOT equal!\n"
.LC4:
.string "Results are equal!\n"
.text
.globl _Z12verificationPKfS0_S0_ii
.type _Z12verificationPKfS0_S0_ii, @function
_Z12verificationPKfS0_S0_ii:
.LFB2071:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r14
movq %rsi, %r15
movq %rdx, 48(%rsp)
movl %ecx, %ebx
movl %r8d, %ebp
movl %ecx, %eax
imull %r8d, %eax
movl %eax, 44(%rsp)
cltq
leaq 0(,%rax,4), %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
movq %r12, %rcx
movq %r12, %rdx
movl $0, %esi
movq %rax, %rdi
call __memset_chk@PLT
testl %ebx, %ebx
jle .L4
leal 3(%rbx), %edi
leal (%rbp,%rbp), %eax
negl %eax
movl $0, %edx
movl $3, %r13d
leal 3(%rbp), %esi
movq %r12, 56(%rsp)
movl %edi, 36(%rsp)
movl %eax, 40(%rsp)
movq %r14, 8(%rsp)
jmp .L5
.L25:
leal (%rsi,%rax), %r14d
movslq %r14d, %r14
leal (%rax,%r8), %r11d
movslq %r11d, %r11
movss (%r15,%r14,4), %xmm0
movq 8(%rsp), %r14
mulss (%r14,%r11,4), %xmm0
addss (%r10), %xmm0
movss %xmm0, (%r10)
.L6:
addl $1, %eax
cmpl %ecx, %eax
je .L24
.L7:
cmpl %edx, %ebx
jle .L6
movl %eax, %r14d
orl %edx, %r14d
js .L6
cmpl %eax, %ebp
jg .L25
jmp .L6
.L24:
addl $5, %r9d
addl %ebp, %r8d
addl $1, %edx
cmpl %r13d, %edx
je .L8
.L10:
movl %r12d, %eax
leal 2(%r9), %r11d
movl %r11d, %esi
jmp .L7
.L8:
movl %edi, %esi
addl $1, %ecx
addl $1, %r12d
cmpl %edi, %ecx
je .L21
.L11:
movl 28(%rsp), %eax
leal (%rax,%rcx), %edx
movslq %edx, %rdx
movq 16(%rsp), %rax
leaq (%rax,%rdx,4), %r10
movl $3, %r9d
subl %ecx, %r9d
leal -5(%r13), %edx
movl 24(%rsp), %r8d
movl %esi, %edi
jmp .L10
.L21:
movl 32(%rsp), %edx
.L9:
addl $1, %r13d
addl %ebp, %edx
movl 36(%rsp), %eax
cmpl %eax, %r13d
je .L22
.L5:
testl %ebp, %ebp
jle .L9
movl 40(%rsp), %eax
addl %edx, %eax
movl %eax, 24(%rsp)
movl $-2, %r12d
movl $3, %ecx
leal -3(%rdx), %eax
movl %edx, 32(%rsp)
movl %eax, 28(%rsp)
jmp .L11
.L22:
movq 56(%rsp), %r12
.L4:
cmpl $0, 44(%rsp)
jle .L12
movl $0, %eax
movss .LC0(%rip), %xmm1
movq 16(%rsp), %rdx
movq 48(%rsp), %rcx
jmp .L16
.L20:
addq $4, %rax
cmpq %rax, %r12
je .L12
.L16:
movss (%rdx,%rax), %xmm0
subss (%rcx,%rax), %xmm0
andps %xmm1, %xmm0
comiss .LC1(%rip), %xmm0
jb .L20
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L15:
movq 16(%rsp), %rdi
call free@PLT
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L15
.cfi_endproc
.LFE2071:
.size _Z12verificationPKfS0_S0_ii, .-_Z12verificationPKfS0_S0_ii
.globl _Z41__device_stub__Z13Convolution2DPfS_S_iiiiPfS_S_iiii
.type _Z41__device_stub__Z13Convolution2DPfS_S_iiiiPfS_S_iiii, @function
_Z41__device_stub__Z13Convolution2DPfS_S_iiiiPfS_S_iiii:
.LFB3708:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13Convolution2DPfS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3708:
.size _Z41__device_stub__Z13Convolution2DPfS_S_iiiiPfS_S_iiii, .-_Z41__device_stub__Z13Convolution2DPfS_S_iiiiPfS_S_iiii
.globl _Z13Convolution2DPfS_S_iiii
.type _Z13Convolution2DPfS_S_iiii, @function
_Z13Convolution2DPfS_S_iiii:
.LFB3709:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z41__device_stub__Z13Convolution2DPfS_S_iiiiPfS_S_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3709:
.size _Z13Convolution2DPfS_S_iiii, .-_Z13Convolution2DPfS_S_iiii
.globl main
.type main, @function
main:
.LFB2070:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $784, %edi
call malloc@PLT
movq %rax, %rbx
movl $100, %edi
call malloc@PLT
movq %rax, %rbp
movl $784, %edi
call malloc@PLT
movq %rax, %r12
movl $98, %ecx
movl $0, %eax
movq %r12, %rdi
rep stosq
movl $1, %eax
.L35:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, -4(%rbx,%rax,4)
addq $1, %rax
cmpq $197, %rax
jne .L35
movl $0, %eax
.L36:
leal 100(%rax), %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $25, %rax
jne .L36
leaq 8(%rsp), %rdi
movl $784, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $100, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $784, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $784, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $784, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %r8d
movl $0, %ecx
movl $100, %edx
movq %rbp, %rsi
leaq _ZL2Mc(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $18, 32(%rsp)
movl $18, 36(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L37:
movl $2, %ecx
movl $784, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $14, %r8d
movl $14, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z12verificationPKfS0_S0_ii
movq %r12, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L43
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 104
pushq $14
.cfi_def_cfa_offset 112
movl $14, %r9d
movl $14, %r8d
movl $14, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z41__device_stub__Z13Convolution2DPfS_S_iiiiPfS_S_iiii
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L37
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z13Convolution2DPfS_S_iiii"
.LC6:
.string "Mc"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3711:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z13Convolution2DPfS_S_iiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $100, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2Mc(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3711:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL2Mc
.comm _ZL2Mc,100,32
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC0:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 981668463
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
#include <unistd.h>
#define TILE_SIZE 14
#define KERNEL_SIZE 5
#define BLOCK_SIZE (TILE_SIZE + (KERNEL_SIZE - 1))
// global variable, outsize any function
__constant__ float Mc[KERNEL_SIZE][KERNEL_SIZE];
__global__ void Convolution2D(float* d_M, float* d_N, float* d_P,int M_Width_row,int M_Width_col,int P_Width_row,int P_Width_col){
int tx = threadIdx.x;
int ty = threadIdx.y;
int row_o = blockIdx.y * TILE_SIZE + ty;
int col_o = blockIdx.x * TILE_SIZE + tx;
int row_i =row_o - ((KERNEL_SIZE - 1) / 2); // Assumes kernel size is 3
int col_i =col_o - ((KERNEL_SIZE - 1) / 2); // Assumes kernel size is 3
int i=0;
int j=0;
float output = 0.0f;
__shared__ float Ms[TILE_SIZE+KERNEL_SIZE-1][TILE_SIZE+KERNEL_SIZE-1];
if((row_i >= 0) && (row_i < M_Width_row) && (col_i >= 0) && (col_i < M_Width_col)){
Ms[ty][tx] = d_M[row_i*M_Width_col + col_i];
}
else{
Ms[ty][tx] = 0.0f;
}
if(ty < TILE_SIZE && tx < TILE_SIZE){
for(i = 0; i < KERNEL_SIZE; i++){
for(j = 0; j < KERNEL_SIZE; j++){
output += Mc[i][j] * Ms[i+ty][j+tx];
//printf("Mc[%d][%d]:%f Ms[%d][%d]:%f\n",i,j,Mc[i][j],i+ty,j+tx,Ms[i+ty][j+tx]);
}
}
// some threads do not write output
if(row_o < P_Width_row && col_o < P_Width_col){
d_P[row_o * P_Width_col + col_o] = output;
}
}
}
void verification(const float *N, const float *M, const float *P, int Rows, int Columns) ;
int main(int argc,char **argv){
float *d_M,*d_N,*d_P;
float *h_M,*h_N,*h_P;
// cudaEvent_t start,end;
// float time_ms=0;
// cudaEventCreate(&start);
// cudaEventCreate(&end);
h_M=(float*)malloc(sizeof(float)*TILE_SIZE*TILE_SIZE );
h_N=(float*)malloc(sizeof(float)*KERNEL_SIZE*KERNEL_SIZE);
h_P=(float*)malloc(sizeof(float)*TILE_SIZE*TILE_SIZE);
memset(h_P, 0,TILE_SIZE * TILE_SIZE * sizeof(float));
for(int i=0;i<TILE_SIZE*TILE_SIZE;i++){
h_M[i]=i+1;
}
for(int i=0;i<KERNEL_SIZE*KERNEL_SIZE;i++){
h_N[i]=100+i;
}
cudaMalloc((void**)&d_M, sizeof(float) *TILE_SIZE*TILE_SIZE);
cudaMalloc((void**)&d_N, sizeof(float) *KERNEL_SIZE*KERNEL_SIZE);
cudaMalloc((void**)&d_P, sizeof(float) *TILE_SIZE*TILE_SIZE);
cudaMemcpy(d_M,h_M,TILE_SIZE*TILE_SIZE*sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(d_P,h_P,TILE_SIZE*TILE_SIZE*sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpyToSymbol(Mc, h_N, sizeof(float) * KERNEL_SIZE * KERNEL_SIZE,0,cudaMemcpyHostToDevice);
dim3 dimBlock(TILE_SIZE + (KERNEL_SIZE - 1), TILE_SIZE + (KERNEL_SIZE - 1));
// cudaEventRecord(start,0);
Convolution2D<<< 1,dimBlock>>>(d_M,d_N,d_P,TILE_SIZE,TILE_SIZE,TILE_SIZE,TILE_SIZE);
// cudaEventRecord(end,0);
//printf("Execution time for Cuda Convolution2D: %.2f ms \n\n",time_ms);
cudaMemcpy(h_P,d_P,TILE_SIZE*TILE_SIZE*sizeof(float),cudaMemcpyDeviceToHost);
verification(h_M, h_N, h_P, TILE_SIZE, TILE_SIZE);
free(h_P);
free(h_M);
free(h_N);
cudaFree(d_P);
cudaFree(d_M);
cudaFree(d_N);
return 0;
}
void verification(const float *N, const float *M, const float *P, int Rows, int Columns) {
int r, c, h, w;
int row_i, col_i;
bool equal;
float* results;
results = (float*)malloc(Rows * Columns * sizeof(float));
memset(results, 0, Rows * Columns * sizeof(float));
for (r = 0; r < Rows; r++) {
for (c = 0; c < Columns; c++) {
for (h = 0; h < KERNEL_SIZE; h++) {
for (w = 0; w < KERNEL_SIZE; w++) {
row_i = r - ((KERNEL_SIZE - 1) / 2) + h;
col_i = c - ((KERNEL_SIZE - 1) / 2) + w;
if ((row_i >= 0) && (row_i < Rows) && (col_i >= 0) && (col_i < Columns)) {
results[r*Columns + c] += (M[h*KERNEL_SIZE + w] * N[row_i*Columns + col_i]);
}
}
}
}
}
equal = true;
for (int i = 0; i < Rows * Columns && equal; i++) {
//printf("results[%d]:%f P[%d]:%f\n",i,results[i],i,P[i]);
if (abs(results[i] - P[i]) >= 0.001f) {
equal = false;
printf("NOT EQUAL!\n");
}
}
if (equal) {
printf("Results are equal!\n");
}
else {
printf("Results are NOT equal!\n");
}
free(results);
return;
}
#include <iostream>
#define MASK_WIDTH 3
#define MASK_RADIUS MASK_WIDTH / 2
#define TILE_WIDTH 8
#define W (TILE_WIDTH + MASK_WIDTH - 1)
/**
* GPU 2D Convolution using shared memory
*/ | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <unistd.h>
#define TILE_SIZE 14
#define KERNEL_SIZE 5
#define BLOCK_SIZE (TILE_SIZE + (KERNEL_SIZE - 1))
// global variable, outsize any function
__constant__ float Mc[KERNEL_SIZE][KERNEL_SIZE];
__global__ void Convolution2D(float* d_M, float* d_N, float* d_P,int M_Width_row,int M_Width_col,int P_Width_row,int P_Width_col){
int tx = threadIdx.x;
int ty = threadIdx.y;
int row_o = blockIdx.y * TILE_SIZE + ty;
int col_o = blockIdx.x * TILE_SIZE + tx;
int row_i =row_o - ((KERNEL_SIZE - 1) / 2); // Assumes kernel size is 3
int col_i =col_o - ((KERNEL_SIZE - 1) / 2); // Assumes kernel size is 3
int i=0;
int j=0;
float output = 0.0f;
__shared__ float Ms[TILE_SIZE+KERNEL_SIZE-1][TILE_SIZE+KERNEL_SIZE-1];
if((row_i >= 0) && (row_i < M_Width_row) && (col_i >= 0) && (col_i < M_Width_col)){
Ms[ty][tx] = d_M[row_i*M_Width_col + col_i];
}
else{
Ms[ty][tx] = 0.0f;
}
if(ty < TILE_SIZE && tx < TILE_SIZE){
for(i = 0; i < KERNEL_SIZE; i++){
for(j = 0; j < KERNEL_SIZE; j++){
output += Mc[i][j] * Ms[i+ty][j+tx];
//printf("Mc[%d][%d]:%f Ms[%d][%d]:%f\n",i,j,Mc[i][j],i+ty,j+tx,Ms[i+ty][j+tx]);
}
}
// some threads do not write output
if(row_o < P_Width_row && col_o < P_Width_col){
d_P[row_o * P_Width_col + col_o] = output;
}
}
}
void verification(const float *N, const float *M, const float *P, int Rows, int Columns) ;
int main(int argc,char **argv){
float *d_M,*d_N,*d_P;
float *h_M,*h_N,*h_P;
// cudaEvent_t start,end;
// float time_ms=0;
// cudaEventCreate(&start);
// cudaEventCreate(&end);
h_M=(float*)malloc(sizeof(float)*TILE_SIZE*TILE_SIZE );
h_N=(float*)malloc(sizeof(float)*KERNEL_SIZE*KERNEL_SIZE);
h_P=(float*)malloc(sizeof(float)*TILE_SIZE*TILE_SIZE);
memset(h_P, 0,TILE_SIZE * TILE_SIZE * sizeof(float));
for(int i=0;i<TILE_SIZE*TILE_SIZE;i++){
h_M[i]=i+1;
}
for(int i=0;i<KERNEL_SIZE*KERNEL_SIZE;i++){
h_N[i]=100+i;
}
hipMalloc((void**)&d_M, sizeof(float) *TILE_SIZE*TILE_SIZE);
hipMalloc((void**)&d_N, sizeof(float) *KERNEL_SIZE*KERNEL_SIZE);
hipMalloc((void**)&d_P, sizeof(float) *TILE_SIZE*TILE_SIZE);
hipMemcpy(d_M,h_M,TILE_SIZE*TILE_SIZE*sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(d_P,h_P,TILE_SIZE*TILE_SIZE*sizeof(float),hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(Mc), h_N, sizeof(float) * KERNEL_SIZE * KERNEL_SIZE,0,hipMemcpyHostToDevice);
dim3 dimBlock(TILE_SIZE + (KERNEL_SIZE - 1), TILE_SIZE + (KERNEL_SIZE - 1));
// cudaEventRecord(start,0);
Convolution2D<<< 1,dimBlock>>>(d_M,d_N,d_P,TILE_SIZE,TILE_SIZE,TILE_SIZE,TILE_SIZE);
// cudaEventRecord(end,0);
//printf("Execution time for Cuda Convolution2D: %.2f ms \n\n",time_ms);
hipMemcpy(h_P,d_P,TILE_SIZE*TILE_SIZE*sizeof(float),hipMemcpyDeviceToHost);
verification(h_M, h_N, h_P, TILE_SIZE, TILE_SIZE);
free(h_P);
free(h_M);
free(h_N);
hipFree(d_P);
hipFree(d_M);
hipFree(d_N);
return 0;
}
void verification(const float *N, const float *M, const float *P, int Rows, int Columns) {
int r, c, h, w;
int row_i, col_i;
bool equal;
float* results;
results = (float*)malloc(Rows * Columns * sizeof(float));
memset(results, 0, Rows * Columns * sizeof(float));
for (r = 0; r < Rows; r++) {
for (c = 0; c < Columns; c++) {
for (h = 0; h < KERNEL_SIZE; h++) {
for (w = 0; w < KERNEL_SIZE; w++) {
row_i = r - ((KERNEL_SIZE - 1) / 2) + h;
col_i = c - ((KERNEL_SIZE - 1) / 2) + w;
if ((row_i >= 0) && (row_i < Rows) && (col_i >= 0) && (col_i < Columns)) {
results[r*Columns + c] += (M[h*KERNEL_SIZE + w] * N[row_i*Columns + col_i]);
}
}
}
}
}
equal = true;
for (int i = 0; i < Rows * Columns && equal; i++) {
//printf("results[%d]:%f P[%d]:%f\n",i,results[i],i,P[i]);
if (abs(results[i] - P[i]) >= 0.001f) {
equal = false;
printf("NOT EQUAL!\n");
}
}
if (equal) {
printf("Results are equal!\n");
}
else {
printf("Results are NOT equal!\n");
}
free(results);
return;
}
#include <iostream>
#define MASK_WIDTH 3
#define MASK_RADIUS MASK_WIDTH / 2
#define TILE_WIDTH 8
#define W (TILE_WIDTH + MASK_WIDTH - 1)
/**
* GPU 2D Convolution using shared memory
*/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <unistd.h>
#define TILE_SIZE 14
#define KERNEL_SIZE 5
#define BLOCK_SIZE (TILE_SIZE + (KERNEL_SIZE - 1))
// global variable, outsize any function
__constant__ float Mc[KERNEL_SIZE][KERNEL_SIZE];
__global__ void Convolution2D(float* d_M, float* d_N, float* d_P,int M_Width_row,int M_Width_col,int P_Width_row,int P_Width_col){
int tx = threadIdx.x;
int ty = threadIdx.y;
int row_o = blockIdx.y * TILE_SIZE + ty;
int col_o = blockIdx.x * TILE_SIZE + tx;
int row_i =row_o - ((KERNEL_SIZE - 1) / 2); // Assumes kernel size is 3
int col_i =col_o - ((KERNEL_SIZE - 1) / 2); // Assumes kernel size is 3
int i=0;
int j=0;
float output = 0.0f;
__shared__ float Ms[TILE_SIZE+KERNEL_SIZE-1][TILE_SIZE+KERNEL_SIZE-1];
if((row_i >= 0) && (row_i < M_Width_row) && (col_i >= 0) && (col_i < M_Width_col)){
Ms[ty][tx] = d_M[row_i*M_Width_col + col_i];
}
else{
Ms[ty][tx] = 0.0f;
}
if(ty < TILE_SIZE && tx < TILE_SIZE){
for(i = 0; i < KERNEL_SIZE; i++){
for(j = 0; j < KERNEL_SIZE; j++){
output += Mc[i][j] * Ms[i+ty][j+tx];
//printf("Mc[%d][%d]:%f Ms[%d][%d]:%f\n",i,j,Mc[i][j],i+ty,j+tx,Ms[i+ty][j+tx]);
}
}
// some threads do not write output
if(row_o < P_Width_row && col_o < P_Width_col){
d_P[row_o * P_Width_col + col_o] = output;
}
}
}
void verification(const float *N, const float *M, const float *P, int Rows, int Columns) ;
int main(int argc,char **argv){
float *d_M,*d_N,*d_P;
float *h_M,*h_N,*h_P;
// cudaEvent_t start,end;
// float time_ms=0;
// cudaEventCreate(&start);
// cudaEventCreate(&end);
h_M=(float*)malloc(sizeof(float)*TILE_SIZE*TILE_SIZE );
h_N=(float*)malloc(sizeof(float)*KERNEL_SIZE*KERNEL_SIZE);
h_P=(float*)malloc(sizeof(float)*TILE_SIZE*TILE_SIZE);
memset(h_P, 0,TILE_SIZE * TILE_SIZE * sizeof(float));
for(int i=0;i<TILE_SIZE*TILE_SIZE;i++){
h_M[i]=i+1;
}
for(int i=0;i<KERNEL_SIZE*KERNEL_SIZE;i++){
h_N[i]=100+i;
}
hipMalloc((void**)&d_M, sizeof(float) *TILE_SIZE*TILE_SIZE);
hipMalloc((void**)&d_N, sizeof(float) *KERNEL_SIZE*KERNEL_SIZE);
hipMalloc((void**)&d_P, sizeof(float) *TILE_SIZE*TILE_SIZE);
hipMemcpy(d_M,h_M,TILE_SIZE*TILE_SIZE*sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(d_P,h_P,TILE_SIZE*TILE_SIZE*sizeof(float),hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(Mc), h_N, sizeof(float) * KERNEL_SIZE * KERNEL_SIZE,0,hipMemcpyHostToDevice);
dim3 dimBlock(TILE_SIZE + (KERNEL_SIZE - 1), TILE_SIZE + (KERNEL_SIZE - 1));
// cudaEventRecord(start,0);
Convolution2D<<< 1,dimBlock>>>(d_M,d_N,d_P,TILE_SIZE,TILE_SIZE,TILE_SIZE,TILE_SIZE);
// cudaEventRecord(end,0);
//printf("Execution time for Cuda Convolution2D: %.2f ms \n\n",time_ms);
hipMemcpy(h_P,d_P,TILE_SIZE*TILE_SIZE*sizeof(float),hipMemcpyDeviceToHost);
verification(h_M, h_N, h_P, TILE_SIZE, TILE_SIZE);
free(h_P);
free(h_M);
free(h_N);
hipFree(d_P);
hipFree(d_M);
hipFree(d_N);
return 0;
}
void verification(const float *N, const float *M, const float *P, int Rows, int Columns) {
int r, c, h, w;
int row_i, col_i;
bool equal;
float* results;
results = (float*)malloc(Rows * Columns * sizeof(float));
memset(results, 0, Rows * Columns * sizeof(float));
for (r = 0; r < Rows; r++) {
for (c = 0; c < Columns; c++) {
for (h = 0; h < KERNEL_SIZE; h++) {
for (w = 0; w < KERNEL_SIZE; w++) {
row_i = r - ((KERNEL_SIZE - 1) / 2) + h;
col_i = c - ((KERNEL_SIZE - 1) / 2) + w;
if ((row_i >= 0) && (row_i < Rows) && (col_i >= 0) && (col_i < Columns)) {
results[r*Columns + c] += (M[h*KERNEL_SIZE + w] * N[row_i*Columns + col_i]);
}
}
}
}
}
equal = true;
for (int i = 0; i < Rows * Columns && equal; i++) {
//printf("results[%d]:%f P[%d]:%f\n",i,results[i],i,P[i]);
if (abs(results[i] - P[i]) >= 0.001f) {
equal = false;
printf("NOT EQUAL!\n");
}
}
if (equal) {
printf("Results are equal!\n");
}
else {
printf("Results are NOT equal!\n");
}
free(results);
return;
}
#include <iostream>
#define MASK_WIDTH 3
#define MASK_RADIUS MASK_WIDTH / 2
#define TILE_WIDTH 8
#define W (TILE_WIDTH + MASK_WIDTH - 1)
/**
* GPU 2D Convolution using shared memory
*/ | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13Convolution2DPfS_S_iiii
.globl _Z13Convolution2DPfS_S_iiii
.p2align 8
.type _Z13Convolution2DPfS_S_iiii,@function
_Z13Convolution2DPfS_S_iiii:
v_bfe_u32 v4, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s15, 14, v[4:5]
v_mov_b32_e32 v5, 0
v_mad_u64_u32 v[2:3], null, s14, 14, v[0:1]
v_cmpx_lt_i32_e32 1, v1
s_cbranch_execz .LBB0_4
s_load_b64 s[4:5], s[0:1], 0x18
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v6, -2, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v3, -2, v2
v_cmp_lt_i32_e64 s3, 1, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v3
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s2, s3
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_3
s_load_b64 s[8:9], s[0:1], 0x0
v_mad_u64_u32 v[7:8], null, v6, s5, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[5:6], 2, v[7:8]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s8, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
global_load_b32 v5, v[5:6], off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s6
v_lshlrev_b32_e32 v3, 2, v0
v_max_u32_e32 v0, v4, v0
s_mov_b32 s2, exec_lo
v_mad_u32_u24 v3, v4, 0x48, v3
s_waitcnt vmcnt(0)
ds_store_b32 v3, v5
v_cmpx_gt_u32_e32 14, v0
s_cbranch_execz .LBB0_11
v_mov_b32_e32 v0, 0
s_mov_b32 s6, 0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, Mc@rel32@lo+4
s_addc_u32 s3, s3, Mc@rel32@hi+12
.p2align 6
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b64 s[4:5], s[2:3]
s_mov_b32 s7, 0
.LBB0_7:
s_delay_alu instid0(SALU_CYCLE_1)
v_add_nc_u32_e32 v4, s7, v3
s_load_b32 s8, s[4:5], 0x0
s_add_i32 s7, s7, 4
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
ds_load_b32 v4, v4
s_cmp_lg_u32 s7, 20
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v0, s8, v4
s_cbranch_scc1 .LBB0_7
s_add_i32 s6, s6, 1
v_add_nc_u32_e32 v3, 0x48, v3
s_add_u32 s2, s2, 20
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s6, 5
s_cbranch_scc1 .LBB0_6
s_load_b64 s[2:3], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
v_cmp_gt_i32_e64 s2, s3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_11
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v1, s3, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[1:2], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13Convolution2DPfS_S_iiii
.amdhsa_group_segment_fixed_size 1296
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13Convolution2DPfS_S_iiii, .Lfunc_end0-_Z13Convolution2DPfS_S_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected Mc
.type Mc,@object
.section .bss,"aw",@nobits
.globl Mc
.p2align 4, 0x0
Mc:
.zero 100
.size Mc, 100
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym Mc
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 1296
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13Convolution2DPfS_S_iiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13Convolution2DPfS_S_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <unistd.h>
#define TILE_SIZE 14
#define KERNEL_SIZE 5
#define BLOCK_SIZE (TILE_SIZE + (KERNEL_SIZE - 1))
// global variable, outsize any function
__constant__ float Mc[KERNEL_SIZE][KERNEL_SIZE];
__global__ void Convolution2D(float* d_M, float* d_N, float* d_P,int M_Width_row,int M_Width_col,int P_Width_row,int P_Width_col){
int tx = threadIdx.x;
int ty = threadIdx.y;
int row_o = blockIdx.y * TILE_SIZE + ty;
int col_o = blockIdx.x * TILE_SIZE + tx;
int row_i =row_o - ((KERNEL_SIZE - 1) / 2); // Assumes kernel size is 3
int col_i =col_o - ((KERNEL_SIZE - 1) / 2); // Assumes kernel size is 3
int i=0;
int j=0;
float output = 0.0f;
__shared__ float Ms[TILE_SIZE+KERNEL_SIZE-1][TILE_SIZE+KERNEL_SIZE-1];
if((row_i >= 0) && (row_i < M_Width_row) && (col_i >= 0) && (col_i < M_Width_col)){
Ms[ty][tx] = d_M[row_i*M_Width_col + col_i];
}
else{
Ms[ty][tx] = 0.0f;
}
if(ty < TILE_SIZE && tx < TILE_SIZE){
for(i = 0; i < KERNEL_SIZE; i++){
for(j = 0; j < KERNEL_SIZE; j++){
output += Mc[i][j] * Ms[i+ty][j+tx];
//printf("Mc[%d][%d]:%f Ms[%d][%d]:%f\n",i,j,Mc[i][j],i+ty,j+tx,Ms[i+ty][j+tx]);
}
}
// some threads do not write output
if(row_o < P_Width_row && col_o < P_Width_col){
d_P[row_o * P_Width_col + col_o] = output;
}
}
}
void verification(const float *N, const float *M, const float *P, int Rows, int Columns) ;
int main(int argc,char **argv){
float *d_M,*d_N,*d_P;
float *h_M,*h_N,*h_P;
// cudaEvent_t start,end;
// float time_ms=0;
// cudaEventCreate(&start);
// cudaEventCreate(&end);
h_M=(float*)malloc(sizeof(float)*TILE_SIZE*TILE_SIZE );
h_N=(float*)malloc(sizeof(float)*KERNEL_SIZE*KERNEL_SIZE);
h_P=(float*)malloc(sizeof(float)*TILE_SIZE*TILE_SIZE);
memset(h_P, 0,TILE_SIZE * TILE_SIZE * sizeof(float));
for(int i=0;i<TILE_SIZE*TILE_SIZE;i++){
h_M[i]=i+1;
}
for(int i=0;i<KERNEL_SIZE*KERNEL_SIZE;i++){
h_N[i]=100+i;
}
hipMalloc((void**)&d_M, sizeof(float) *TILE_SIZE*TILE_SIZE);
hipMalloc((void**)&d_N, sizeof(float) *KERNEL_SIZE*KERNEL_SIZE);
hipMalloc((void**)&d_P, sizeof(float) *TILE_SIZE*TILE_SIZE);
hipMemcpy(d_M,h_M,TILE_SIZE*TILE_SIZE*sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(d_P,h_P,TILE_SIZE*TILE_SIZE*sizeof(float),hipMemcpyHostToDevice);
hipMemcpyToSymbol(HIP_SYMBOL(Mc), h_N, sizeof(float) * KERNEL_SIZE * KERNEL_SIZE,0,hipMemcpyHostToDevice);
dim3 dimBlock(TILE_SIZE + (KERNEL_SIZE - 1), TILE_SIZE + (KERNEL_SIZE - 1));
// cudaEventRecord(start,0);
Convolution2D<<< 1,dimBlock>>>(d_M,d_N,d_P,TILE_SIZE,TILE_SIZE,TILE_SIZE,TILE_SIZE);
// cudaEventRecord(end,0);
//printf("Execution time for Cuda Convolution2D: %.2f ms \n\n",time_ms);
hipMemcpy(h_P,d_P,TILE_SIZE*TILE_SIZE*sizeof(float),hipMemcpyDeviceToHost);
verification(h_M, h_N, h_P, TILE_SIZE, TILE_SIZE);
free(h_P);
free(h_M);
free(h_N);
hipFree(d_P);
hipFree(d_M);
hipFree(d_N);
return 0;
}
void verification(const float *N, const float *M, const float *P, int Rows, int Columns) {
int r, c, h, w;
int row_i, col_i;
bool equal;
float* results;
results = (float*)malloc(Rows * Columns * sizeof(float));
memset(results, 0, Rows * Columns * sizeof(float));
for (r = 0; r < Rows; r++) {
for (c = 0; c < Columns; c++) {
for (h = 0; h < KERNEL_SIZE; h++) {
for (w = 0; w < KERNEL_SIZE; w++) {
row_i = r - ((KERNEL_SIZE - 1) / 2) + h;
col_i = c - ((KERNEL_SIZE - 1) / 2) + w;
if ((row_i >= 0) && (row_i < Rows) && (col_i >= 0) && (col_i < Columns)) {
results[r*Columns + c] += (M[h*KERNEL_SIZE + w] * N[row_i*Columns + col_i]);
}
}
}
}
}
equal = true;
for (int i = 0; i < Rows * Columns && equal; i++) {
//printf("results[%d]:%f P[%d]:%f\n",i,results[i],i,P[i]);
if (abs(results[i] - P[i]) >= 0.001f) {
equal = false;
printf("NOT EQUAL!\n");
}
}
if (equal) {
printf("Results are equal!\n");
}
else {
printf("Results are NOT equal!\n");
}
free(results);
return;
}
#include <iostream>
#define MASK_WIDTH 3
#define MASK_RADIUS MASK_WIDTH / 2
#define TILE_WIDTH 8
#define W (TILE_WIDTH + MASK_WIDTH - 1)
/**
* GPU 2D Convolution using shared memory
*/ | .text
.file "lab6.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__Convolution2DPfS_S_iiii # -- Begin function _Z28__device_stub__Convolution2DPfS_S_iiii
.p2align 4, 0x90
.type _Z28__device_stub__Convolution2DPfS_S_iiii,@function
_Z28__device_stub__Convolution2DPfS_S_iiii: # @_Z28__device_stub__Convolution2DPfS_S_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13Convolution2DPfS_S_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z28__device_stub__Convolution2DPfS_S_iiii, .Lfunc_end0-_Z28__device_stub__Convolution2DPfS_S_iiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $168, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $784, %edi # imm = 0x310
callq malloc
movq %rax, %rbx
movl $100, %edi
callq malloc
movq %rax, %r14
movl $784, %edi # imm = 0x310
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
movl $784, %edx # imm = 0x310
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq 1(%r12), %rax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r12,4)
movq %rax, %r12
cmpq $196, %rax
jne .LBB1_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # %.preheader
# =>This Inner Loop Header: Depth=1
leal 100(%rax), %ecx
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq $25, %rax
jne .LBB1_3
# %bb.4:
leaq 8(%rsp), %rdi
movl $784, %esi # imm = 0x310
callq hipMalloc
leaq 32(%rsp), %rdi
movl $100, %esi
callq hipMalloc
movq %rsp, %rdi
movl $784, %esi # imm = 0x310
callq hipMalloc
movq 8(%rsp), %rdi
movl $784, %edx # imm = 0x310
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $784, %edx # imm = 0x310
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movl $Mc, %edi
movl $100, %edx
movq %r14, %rsi
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $77309411346, %rdx # imm = 0x1200000012
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 8(%rsp), %rax
movq 32(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $14, 28(%rsp)
movl $14, 24(%rsp)
movl $14, 20(%rsp)
movl $14, 16(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z13Convolution2DPfS_S_iiii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq (%rsp), %rsi
movl $784, %edx # imm = 0x310
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $14, %ecx
movl $14, %r8d
callq _Z12verificationPKfS0_S0_ii
movq %r15, %rdi
callq free
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z12verificationPKfS0_S0_ii
.LCPI2_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_1:
.long 0x3a83126f # float 0.00100000005
.text
.globl _Z12verificationPKfS0_S0_ii
.p2align 4, 0x90
.type _Z12verificationPKfS0_S0_ii,@function
_Z12verificationPKfS0_S0_ii: # @_Z12verificationPKfS0_S0_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebx
movq %rdx, 48(%rsp) # 8-byte Spill
movq %rsi, %r14
movq %rdi, 24(%rsp) # 8-byte Spill
movl %r8d, 12(%rsp) # 4-byte Spill
movl %r8d, %eax
imull %ecx, %eax
movl %eax, 44(%rsp) # 4-byte Spill
movslq %eax, %r13
shlq $2, %r13
movq %r13, %rdi
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
movq %rax, %rdi
xorl %esi, %esi
movq %r13, %rdx
callq memset@PLT
testl %ebx, %ebx
jle .LBB2_15
# %bb.1: # %.preheader61.lr.ph
movslq 12(%rsp), %rax # 4-byte Folded Reload
movl %ebx, %ecx
movl %eax, %edx
leaq (,%rax,8), %rsi
subq %rsi, 24(%rsp) # 8-byte Folded Spill
leaq (,%rax,4), %rsi
xorl %edi, %edi
movq %rdi, 32(%rsp) # 8-byte Spill
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_14: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movq 32(%rsp), %r8 # 8-byte Reload
incq %r8
addq %rsi, 24(%rsp) # 8-byte Folded Spill
movq %r8, %rdi
movq %r8, 32(%rsp) # 8-byte Spill
cmpq %rcx, %r8
je .LBB2_15
.LBB2_2: # %.preheader61
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
# Child Loop BB2_5 Depth 3
# Child Loop BB2_6 Depth 4
cmpl $0, 12(%rsp) # 4-byte Folded Reload
jle .LBB2_14
# %bb.3: # %.preheader60.lr.ph
# in Loop: Header=BB2_2 Depth=1
movq 32(%rsp), %rdi # 8-byte Reload
leaq -2(%rdi), %r8
imulq %rax, %rdi
movq 16(%rsp), %r9 # 8-byte Reload
leaq (%r9,%rdi,4), %r9
movq 24(%rsp), %r10 # 8-byte Reload
xorl %edi, %edi
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_13: # in Loop: Header=BB2_4 Depth=2
incq %rdi
addq $4, %r10
cmpq %rdx, %rdi
je .LBB2_14
.LBB2_4: # %.preheader60
# Parent Loop BB2_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_5 Depth 3
# Child Loop BB2_6 Depth 4
movq %r10, %r13
movq %r14, %r15
xorl %ebp, %ebp
jmp .LBB2_5
.p2align 4, 0x90
.LBB2_12: # in Loop: Header=BB2_5 Depth=3
incq %rbp
addq $20, %r15
addq %rsi, %r13
cmpq $5, %rbp
je .LBB2_13
.LBB2_5: # %.preheader59
# Parent Loop BB2_2 Depth=1
# Parent Loop BB2_4 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB2_6 Depth 4
leaq (%r8,%rbp), %rbx
movq $-2, %r12
jmp .LBB2_6
.p2align 4, 0x90
.LBB2_11: # in Loop: Header=BB2_6 Depth=4
incq %r12
cmpq $3, %r12
je .LBB2_12
.LBB2_6: # Parent Loop BB2_2 Depth=1
# Parent Loop BB2_4 Depth=2
# Parent Loop BB2_5 Depth=3
# => This Inner Loop Header: Depth=4
testq %rbx, %rbx
js .LBB2_11
# %bb.7: # in Loop: Header=BB2_6 Depth=4
cmpq %rcx, %rbx
jge .LBB2_11
# %bb.8: # in Loop: Header=BB2_6 Depth=4
movq %rdi, %r11
addq %r12, %r11
js .LBB2_11
# %bb.9: # in Loop: Header=BB2_6 Depth=4
cmpq %rax, %r11
jge .LBB2_11
# %bb.10: # in Loop: Header=BB2_6 Depth=4
movss 8(%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%r13,%r12,4), %xmm0
addss (%r9,%rdi,4), %xmm0
movss %xmm0, (%r9,%rdi,4)
jmp .LBB2_11
.LBB2_15: # %.preheader
movl 44(%rsp), %eax # 4-byte Reload
testl %eax, %eax
jle .LBB2_16
# %bb.17: # %.lr.ph.preheader
movl %eax, %r14d
movb $1, %al
movl $1, %r15d
movaps .LCPI2_0(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movss .LCPI2_1(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movq 16(%rsp), %rbx # 8-byte Reload
movq 48(%rsp), %r12 # 8-byte Reload
.p2align 4, 0x90
.LBB2_18: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss -4(%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss -4(%r12,%r15,4), %xmm0
andps %xmm1, %xmm0
ucomiss %xmm2, %xmm0
jb .LBB2_20
# %bb.19: # in Loop: Header=BB2_18 Depth=1
movl $.Lstr.2, %edi
callq puts@PLT
movss .LCPI2_1(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movaps .LCPI2_0(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
xorl %eax, %eax
.LBB2_20: # in Loop: Header=BB2_18 Depth=1
cmpq %r14, %r15
jae .LBB2_22
# %bb.21: # in Loop: Header=BB2_18 Depth=1
movl %eax, %ecx
andb $1, %cl
incq %r15
testb %cl, %cl
jne .LBB2_18
.LBB2_22: # %._crit_edge68
movl $.Lstr.1, %ecx
movl $.Lstr, %edi
testb $1, %al
cmovneq %rcx, %rdi
jmp .LBB2_23
.LBB2_16:
movl $.Lstr.1, %edi
movq 16(%rsp), %rbx # 8-byte Reload
.LBB2_23: # %.critedge
callq puts@PLT
movq %rbx, %rdi
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp free # TAILCALL
.Lfunc_end2:
.size _Z12verificationPKfS0_S0_ii, .Lfunc_end2-_Z12verificationPKfS0_S0_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13Convolution2DPfS_S_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $Mc, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $100, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type Mc,@object # @Mc
.local Mc
.comm Mc,100,16
.type _Z13Convolution2DPfS_S_iiii,@object # @_Z13Convolution2DPfS_S_iiii
.section .rodata,"a",@progbits
.globl _Z13Convolution2DPfS_S_iiii
.p2align 3, 0x0
_Z13Convolution2DPfS_S_iiii:
.quad _Z28__device_stub__Convolution2DPfS_S_iiii
.size _Z13Convolution2DPfS_S_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13Convolution2DPfS_S_iiii"
.size .L__unnamed_1, 28
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "Mc"
.size .L__unnamed_2, 3
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Results are NOT equal!"
.size .Lstr, 23
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Results are equal!"
.size .Lstr.1, 19
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "NOT EQUAL!"
.size .Lstr.2, 11
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__Convolution2DPfS_S_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym Mc
.addrsig_sym _Z13Convolution2DPfS_S_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13Convolution2DPfS_S_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_TID.Y ; /* 0x0000000000097919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0040*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e680000002100 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0060*/ IMAD R0, R0, 0xe, R9 ; /* 0x0000000e00007824 */
/* 0x001fca00078e0209 */
/*0070*/ IADD3 R2, R0, -0x2, RZ ; /* 0xfffffffe00027810 */
/* 0x000fe20007ffe0ff */
/*0080*/ IMAD R3, R3, 0xe, R6 ; /* 0x0000000e03037824 */
/* 0x002fc600078e0206 */
/*0090*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x000fc80003f06270 */
/*00a0*/ ISETP.GT.AND P0, PT, R0, 0x1, !P0 ; /* 0x000000010000780c */
/* 0x000fe40004704270 */
/*00b0*/ IADD3 R5, R3.reuse, -0x2, RZ ; /* 0xfffffffe03057810 */
/* 0x040fe40007ffe0ff */
/*00c0*/ ISETP.GT.AND P0, PT, R3, 0x1, P0 ; /* 0x000000010300780c */
/* 0x000fc80000704270 */
/*00d0*/ ISETP.LT.AND P0, PT, R5, c[0x0][0x17c], P0 ; /* 0x00005f0005007a0c */
/* 0x000fda0000701270 */
/*00e0*/ @P0 MOV R4, 0x4 ; /* 0x0000000400040802 */
/* 0x000fe20000000f00 */
/*00f0*/ @P0 IMAD R5, R2, c[0x0][0x17c], R5 ; /* 0x00005f0002050a24 */
/* 0x000fe200078e0205 */
/*0100*/ @!P0 MOV R7, RZ ; /* 0x000000ff00078202 */
/* 0x000fc60000000f00 */
/*0110*/ @P0 IMAD.WIDE R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005040625 */
/* 0x000fca00078e0204 */
/*0120*/ @P0 LDG.E R7, [R4.64] ; /* 0x0000000404070981 */
/* 0x000ea2000c1e1900 */
/*0130*/ ISETP.GT.AND P1, PT, R6, 0xd, PT ; /* 0x0000000d0600780c */
/* 0x000fe20003f24270 */
/*0140*/ IMAD R2, R9, 0x12, R6 ; /* 0x0000001209027824 */
/* 0x000fc600078e0206 */
/*0150*/ ISETP.GT.OR P1, PT, R9, 0xd, P1 ; /* 0x0000000d0900780c */
/* 0x000fe40000f24670 */
/*0160*/ @!P0 STS [R2.X4], RZ ; /* 0x000000ff02008388 */
/* 0x0001e80000004800 */
/*0170*/ @P0 STS [R2.X4], R7 ; /* 0x0000000702000388 */
/* 0x0041ee0000004800 */
/*0180*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0190*/ LDS R6, [R2.X4+0x4] ; /* 0x0000040002067984 */
/* 0x000e620000004800 */
/*01a0*/ FFMA R7, R7, c[0x3][0x0], RZ ; /* 0x00c0000007077a23 */
/* 0x001fe200000000ff */
/*01b0*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x184], PT ; /* 0x0000610003007a0c */
/* 0x000fc40003f06270 */
/*01c0*/ LDS R8, [R2.X4+0x8] ; /* 0x0000080002087984 */
/* 0x000e240000004800 */
/*01d0*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x180], P0 ; /* 0x0000600000007a0c */
/* 0x000fe40000706670 */
/*01e0*/ LDS R9, [R2.X4+0xc] ; /* 0x00000c0002097984 */
/* 0x000ea80000004800 */
/*01f0*/ LDS R10, [R2.X4+0x10] ; /* 0x00001000020a7984 */
/* 0x000ee80000004800 */
/*0200*/ LDS R11, [R2.X4+0x48] ; /* 0x00004800020b7984 */
/* 0x000f280000004800 */
/*0210*/ LDS R12, [R2.X4+0x4c] ; /* 0x00004c00020c7984 */
/* 0x000f680000004800 */
/*0220*/ LDS R13, [R2.X4+0x50] ; /* 0x00005000020d7984 */
/* 0x000f680000004800 */
/*0230*/ LDS R14, [R2.X4+0x54] ; /* 0x00005400020e7984 */
/* 0x000f680000004800 */
/*0240*/ LDS R4, [R2.X4+0x58] ; /* 0x0000580002047984 */
/* 0x000f680000004800 */
/*0250*/ LDS R5, [R2.X4+0x90] ; /* 0x0000900002057984 */
/* 0x000f620000004800 */
/*0260*/ FFMA R7, R6, c[0x3][0x4], R7 ; /* 0x00c0010006077a23 */
/* 0x002fc60000000007 */
/*0270*/ LDS R16, [R2.X4+0xe8] ; /* 0x0000e80002107984 */
/* 0x000fe20000004800 */
/*0280*/ FFMA R8, R8, c[0x3][0x8], R7 ; /* 0x00c0020008087a23 */
/* 0x001fc60000000007 */
/*0290*/ LDS R6, [R2.X4+0x94] ; /* 0x0000940002067984 */
/* 0x000e220000004800 */
/*02a0*/ FFMA R9, R9, c[0x3][0xc], R8 ; /* 0x00c0030009097a23 */
/* 0x004fc60000000008 */
/*02b0*/ LDS R7, [R2.X4+0x98] ; /* 0x0000980002077984 */
/* 0x000e620000004800 */
/*02c0*/ FFMA R10, R10, c[0x3][0x10], R9 ; /* 0x00c004000a0a7a23 */
/* 0x008fc60000000009 */
/*02d0*/ LDS R8, [R2.X4+0x9c] ; /* 0x00009c0002087984 */
/* 0x000ea20000004800 */
/*02e0*/ FFMA R11, R11, c[0x3][0x14], R10 ; /* 0x00c005000b0b7a23 */
/* 0x010fc6000000000a */
/*02f0*/ LDS R9, [R2.X4+0xa0] ; /* 0x0000a00002097984 */
/* 0x000ee20000004800 */
/*0300*/ FFMA R12, R12, c[0x3][0x18], R11 ; /* 0x00c006000c0c7a23 */
/* 0x020fc6000000000b */
/*0310*/ LDS R10, [R2.X4+0xd8] ; /* 0x0000d800020a7984 */
/* 0x000f220000004800 */
/*0320*/ FFMA R13, R13, c[0x3][0x1c], R12 ; /* 0x00c007000d0d7a23 */
/* 0x000fc6000000000c */
/*0330*/ LDS R11, [R2.X4+0xdc] ; /* 0x0000dc00020b7984 */
/* 0x000f620000004800 */
/*0340*/ FFMA R13, R14, c[0x3][0x20], R13 ; /* 0x00c008000e0d7a23 */
/* 0x000fc6000000000d */
/*0350*/ LDS R12, [R2.X4+0xe0] ; /* 0x0000e000020c7984 */
/* 0x000f620000004800 */
/*0360*/ FFMA R4, R4, c[0x3][0x24], R13 ; /* 0x00c0090004047a23 */
/* 0x000fc6000000000d */
/*0370*/ LDS R14, [R2.X4+0xe4] ; /* 0x0000e400020e7984 */
/* 0x000f620000004800 */
/*0380*/ FFMA R5, R5, c[0x3][0x28], R4 ; /* 0x00c00a0005057a23 */
/* 0x000fc60000000004 */
/*0390*/ LDS R13, [R2.X4+0x128] ; /* 0x00012800020d7984 */
/* 0x000fe80000004800 */
/*03a0*/ LDS R4, [R2.X4+0x120] ; /* 0x0001200002047984 */
/* 0x000f620000004800 */
/*03b0*/ FFMA R6, R6, c[0x3][0x2c], R5 ; /* 0x00c00b0006067a23 */
/* 0x001fc60000000005 */
/*03c0*/ LDS R5, [R2.X4+0x124] ; /* 0x0001240002057984 */
/* 0x000e220000004800 */
/*03d0*/ FFMA R7, R7, c[0x3][0x30], R6 ; /* 0x00c00c0007077a23 */
/* 0x002fc80000000006 */
/*03e0*/ FFMA R8, R8, c[0x3][0x34], R7 ; /* 0x00c00d0008087a23 */
/* 0x004fe40000000007 */
/*03f0*/ LDS R7, [R2.X4+0x12c] ; /* 0x00012c0002077984 */
/* 0x0002a40000004800 */
/*0400*/ FFMA R9, R9, c[0x3][0x38], R8 ; /* 0x00c00e0009097a23 */
/* 0x008fc80000000008 */
/*0410*/ FFMA R10, R10, c[0x3][0x3c], R9 ; /* 0x00c00f000a0a7a23 */
/* 0x010fe40000000009 */
/*0420*/ LDS R9, [R2.X4+0x130] ; /* 0x0001300002097984 */
/* 0x0002e40000004800 */
/*0430*/ FFMA R11, R11, c[0x3][0x40], R10 ; /* 0x00c010000b0b7a23 */
/* 0x020fc8000000000a */
/*0440*/ FFMA R11, R12, c[0x3][0x44], R11 ; /* 0x00c011000c0b7a23 */
/* 0x000fc8000000000b */
/*0450*/ FFMA R11, R14, c[0x3][0x48], R11 ; /* 0x00c012000e0b7a23 */
/* 0x000fc8000000000b */
/*0460*/ FFMA R11, R16, c[0x3][0x4c], R11 ; /* 0x00c01300100b7a23 */
/* 0x000fc8000000000b */
/*0470*/ FFMA R4, R4, c[0x3][0x50], R11 ; /* 0x00c0140004047a23 */
/* 0x000fc8000000000b */
/*0480*/ FFMA R4, R5, c[0x3][0x54], R4 ; /* 0x00c0150005047a23 */
/* 0x001fc80000000004 */
/*0490*/ FFMA R4, R13, c[0x3][0x58], R4 ; /* 0x00c016000d047a23 */
/* 0x000fe20000000004 */
/*04a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fec0003800000 */
/*04b0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x002fe200000001ff */
/*04c0*/ IMAD R3, R0, c[0x0][0x184], R3 ; /* 0x0000610000037a24 */
/* 0x000fe400078e0203 */
/*04d0*/ FFMA R4, R7, c[0x3][0x5c], R4 ; /* 0x00c0170007047a23 */
/* 0x004fc80000000004 */
/*04e0*/ FFMA R9, R9, c[0x3][0x60], R4 ; /* 0x00c0180009097a23 */
/* 0x008fc60000000004 */
/*04f0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0500*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*0510*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0520*/ BRA 0x520; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13Convolution2DPfS_S_iiii
.globl _Z13Convolution2DPfS_S_iiii
.p2align 8
.type _Z13Convolution2DPfS_S_iiii,@function
_Z13Convolution2DPfS_S_iiii:
v_bfe_u32 v4, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s15, 14, v[4:5]
v_mov_b32_e32 v5, 0
v_mad_u64_u32 v[2:3], null, s14, 14, v[0:1]
v_cmpx_lt_i32_e32 1, v1
s_cbranch_execz .LBB0_4
s_load_b64 s[4:5], s[0:1], 0x18
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v6, -2, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v3, -2, v2
v_cmp_lt_i32_e64 s3, 1, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v3
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s2, s3
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_3
s_load_b64 s[8:9], s[0:1], 0x0
v_mad_u64_u32 v[7:8], null, v6, s5, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[5:6], 2, v[7:8]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s8, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
global_load_b32 v5, v[5:6], off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_or_b32 exec_lo, exec_lo, s6
v_lshlrev_b32_e32 v3, 2, v0
v_max_u32_e32 v0, v4, v0
s_mov_b32 s2, exec_lo
v_mad_u32_u24 v3, v4, 0x48, v3
s_waitcnt vmcnt(0)
ds_store_b32 v3, v5
v_cmpx_gt_u32_e32 14, v0
s_cbranch_execz .LBB0_11
v_mov_b32_e32 v0, 0
s_mov_b32 s6, 0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, Mc@rel32@lo+4
s_addc_u32 s3, s3, Mc@rel32@hi+12
.p2align 6
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b64 s[4:5], s[2:3]
s_mov_b32 s7, 0
.LBB0_7:
s_delay_alu instid0(SALU_CYCLE_1)
v_add_nc_u32_e32 v4, s7, v3
s_load_b32 s8, s[4:5], 0x0
s_add_i32 s7, s7, 4
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
ds_load_b32 v4, v4
s_cmp_lg_u32 s7, 20
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v0, s8, v4
s_cbranch_scc1 .LBB0_7
s_add_i32 s6, s6, 1
v_add_nc_u32_e32 v3, 0x48, v3
s_add_u32 s2, s2, 20
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s6, 5
s_cbranch_scc1 .LBB0_6
s_load_b64 s[2:3], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
v_cmp_gt_i32_e64 s2, s3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_11
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v1, s3, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[1:2], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13Convolution2DPfS_S_iiii
.amdhsa_group_segment_fixed_size 1296
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13Convolution2DPfS_S_iiii, .Lfunc_end0-_Z13Convolution2DPfS_S_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected Mc
.type Mc,@object
.section .bss,"aw",@nobits
.globl Mc
.p2align 4, 0x0
Mc:
.zero 100
.size Mc, 100
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym Mc
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 1296
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13Convolution2DPfS_S_iiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13Convolution2DPfS_S_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c3c3e_00000000-6_lab6.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3686:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3686:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "NOT EQUAL!\n"
.LC3:
.string "Results are NOT equal!\n"
.LC4:
.string "Results are equal!\n"
.text
.globl _Z12verificationPKfS0_S0_ii
.type _Z12verificationPKfS0_S0_ii, @function
_Z12verificationPKfS0_S0_ii:
.LFB2071:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, %r14
movq %rsi, %r15
movq %rdx, 48(%rsp)
movl %ecx, %ebx
movl %r8d, %ebp
movl %ecx, %eax
imull %r8d, %eax
movl %eax, 44(%rsp)
cltq
leaq 0(,%rax,4), %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
movq %r12, %rcx
movq %r12, %rdx
movl $0, %esi
movq %rax, %rdi
call __memset_chk@PLT
testl %ebx, %ebx
jle .L4
leal 3(%rbx), %edi
leal (%rbp,%rbp), %eax
negl %eax
movl $0, %edx
movl $3, %r13d
leal 3(%rbp), %esi
movq %r12, 56(%rsp)
movl %edi, 36(%rsp)
movl %eax, 40(%rsp)
movq %r14, 8(%rsp)
jmp .L5
.L25:
leal (%rsi,%rax), %r14d
movslq %r14d, %r14
leal (%rax,%r8), %r11d
movslq %r11d, %r11
movss (%r15,%r14,4), %xmm0
movq 8(%rsp), %r14
mulss (%r14,%r11,4), %xmm0
addss (%r10), %xmm0
movss %xmm0, (%r10)
.L6:
addl $1, %eax
cmpl %ecx, %eax
je .L24
.L7:
cmpl %edx, %ebx
jle .L6
movl %eax, %r14d
orl %edx, %r14d
js .L6
cmpl %eax, %ebp
jg .L25
jmp .L6
.L24:
addl $5, %r9d
addl %ebp, %r8d
addl $1, %edx
cmpl %r13d, %edx
je .L8
.L10:
movl %r12d, %eax
leal 2(%r9), %r11d
movl %r11d, %esi
jmp .L7
.L8:
movl %edi, %esi
addl $1, %ecx
addl $1, %r12d
cmpl %edi, %ecx
je .L21
.L11:
movl 28(%rsp), %eax
leal (%rax,%rcx), %edx
movslq %edx, %rdx
movq 16(%rsp), %rax
leaq (%rax,%rdx,4), %r10
movl $3, %r9d
subl %ecx, %r9d
leal -5(%r13), %edx
movl 24(%rsp), %r8d
movl %esi, %edi
jmp .L10
.L21:
movl 32(%rsp), %edx
.L9:
addl $1, %r13d
addl %ebp, %edx
movl 36(%rsp), %eax
cmpl %eax, %r13d
je .L22
.L5:
testl %ebp, %ebp
jle .L9
movl 40(%rsp), %eax
addl %edx, %eax
movl %eax, 24(%rsp)
movl $-2, %r12d
movl $3, %ecx
leal -3(%rdx), %eax
movl %edx, 32(%rsp)
movl %eax, 28(%rsp)
jmp .L11
.L22:
movq 56(%rsp), %r12
.L4:
cmpl $0, 44(%rsp)
jle .L12
movl $0, %eax
movss .LC0(%rip), %xmm1
movq 16(%rsp), %rdx
movq 48(%rsp), %rcx
jmp .L16
.L20:
addq $4, %rax
cmpq %rax, %r12
je .L12
.L16:
movss (%rdx,%rax), %xmm0
subss (%rcx,%rax), %xmm0
andps %xmm1, %xmm0
comiss .LC1(%rip), %xmm0
jb .L20
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L15:
movq 16(%rsp), %rdi
call free@PLT
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L15
.cfi_endproc
.LFE2071:
.size _Z12verificationPKfS0_S0_ii, .-_Z12verificationPKfS0_S0_ii
.globl _Z41__device_stub__Z13Convolution2DPfS_S_iiiiPfS_S_iiii
.type _Z41__device_stub__Z13Convolution2DPfS_S_iiiiPfS_S_iiii, @function
_Z41__device_stub__Z13Convolution2DPfS_S_iiiiPfS_S_iiii:
.LFB3708:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13Convolution2DPfS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3708:
.size _Z41__device_stub__Z13Convolution2DPfS_S_iiiiPfS_S_iiii, .-_Z41__device_stub__Z13Convolution2DPfS_S_iiiiPfS_S_iiii
.globl _Z13Convolution2DPfS_S_iiii
.type _Z13Convolution2DPfS_S_iiii, @function
_Z13Convolution2DPfS_S_iiii:
.LFB3709:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z41__device_stub__Z13Convolution2DPfS_S_iiiiPfS_S_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3709:
.size _Z13Convolution2DPfS_S_iiii, .-_Z13Convolution2DPfS_S_iiii
.globl main
.type main, @function
main:
.LFB2070:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $784, %edi
call malloc@PLT
movq %rax, %rbx
movl $100, %edi
call malloc@PLT
movq %rax, %rbp
movl $784, %edi
call malloc@PLT
movq %rax, %r12
movl $98, %ecx
movl $0, %eax
movq %r12, %rdi
rep stosq
movl $1, %eax
.L35:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, -4(%rbx,%rax,4)
addq $1, %rax
cmpq $197, %rax
jne .L35
movl $0, %eax
.L36:
leal 100(%rax), %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $25, %rax
jne .L36
leaq 8(%rsp), %rdi
movl $784, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $100, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $784, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $784, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $784, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %r8d
movl $0, %ecx
movl $100, %edx
movq %rbp, %rsi
leaq _ZL2Mc(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $18, 32(%rsp)
movl $18, 36(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L37:
movl $2, %ecx
movl $784, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $14, %r8d
movl $14, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z12verificationPKfS0_S0_ii
movq %r12, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L43
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 104
pushq $14
.cfi_def_cfa_offset 112
movl $14, %r9d
movl $14, %r8d
movl $14, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z41__device_stub__Z13Convolution2DPfS_S_iiiiPfS_S_iiii
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L37
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z13Convolution2DPfS_S_iiii"
.LC6:
.string "Mc"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3711:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z13Convolution2DPfS_S_iiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $100, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2Mc(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3711:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL2Mc
.comm _ZL2Mc,100,32
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC0:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 981668463
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "lab6.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z28__device_stub__Convolution2DPfS_S_iiii # -- Begin function _Z28__device_stub__Convolution2DPfS_S_iiii
.p2align 4, 0x90
.type _Z28__device_stub__Convolution2DPfS_S_iiii,@function
_Z28__device_stub__Convolution2DPfS_S_iiii: # @_Z28__device_stub__Convolution2DPfS_S_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13Convolution2DPfS_S_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z28__device_stub__Convolution2DPfS_S_iiii, .Lfunc_end0-_Z28__device_stub__Convolution2DPfS_S_iiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $168, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $784, %edi # imm = 0x310
callq malloc
movq %rax, %rbx
movl $100, %edi
callq malloc
movq %rax, %r14
movl $784, %edi # imm = 0x310
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
movl $784, %edx # imm = 0x310
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq 1(%r12), %rax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r12,4)
movq %rax, %r12
cmpq $196, %rax
jne .LBB1_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # %.preheader
# =>This Inner Loop Header: Depth=1
leal 100(%rax), %ecx
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq $25, %rax
jne .LBB1_3
# %bb.4:
leaq 8(%rsp), %rdi
movl $784, %esi # imm = 0x310
callq hipMalloc
leaq 32(%rsp), %rdi
movl $100, %esi
callq hipMalloc
movq %rsp, %rdi
movl $784, %esi # imm = 0x310
callq hipMalloc
movq 8(%rsp), %rdi
movl $784, %edx # imm = 0x310
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $784, %edx # imm = 0x310
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movl $Mc, %edi
movl $100, %edx
movq %r14, %rsi
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $77309411346, %rdx # imm = 0x1200000012
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 8(%rsp), %rax
movq 32(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $14, 28(%rsp)
movl $14, 24(%rsp)
movl $14, 20(%rsp)
movl $14, 16(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z13Convolution2DPfS_S_iiii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq (%rsp), %rsi
movl $784, %edx # imm = 0x310
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
movl $14, %ecx
movl $14, %r8d
callq _Z12verificationPKfS0_S0_ii
movq %r15, %rdi
callq free
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z12verificationPKfS0_S0_ii
.LCPI2_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI2_1:
.long 0x3a83126f # float 0.00100000005
.text
.globl _Z12verificationPKfS0_S0_ii
.p2align 4, 0x90
.type _Z12verificationPKfS0_S0_ii,@function
_Z12verificationPKfS0_S0_ii: # @_Z12verificationPKfS0_S0_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebx
movq %rdx, 48(%rsp) # 8-byte Spill
movq %rsi, %r14
movq %rdi, 24(%rsp) # 8-byte Spill
movl %r8d, 12(%rsp) # 4-byte Spill
movl %r8d, %eax
imull %ecx, %eax
movl %eax, 44(%rsp) # 4-byte Spill
movslq %eax, %r13
shlq $2, %r13
movq %r13, %rdi
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
movq %rax, %rdi
xorl %esi, %esi
movq %r13, %rdx
callq memset@PLT
testl %ebx, %ebx
jle .LBB2_15
# %bb.1: # %.preheader61.lr.ph
movslq 12(%rsp), %rax # 4-byte Folded Reload
movl %ebx, %ecx
movl %eax, %edx
leaq (,%rax,8), %rsi
subq %rsi, 24(%rsp) # 8-byte Folded Spill
leaq (,%rax,4), %rsi
xorl %edi, %edi
movq %rdi, 32(%rsp) # 8-byte Spill
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_14: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movq 32(%rsp), %r8 # 8-byte Reload
incq %r8
addq %rsi, 24(%rsp) # 8-byte Folded Spill
movq %r8, %rdi
movq %r8, 32(%rsp) # 8-byte Spill
cmpq %rcx, %r8
je .LBB2_15
.LBB2_2: # %.preheader61
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
# Child Loop BB2_5 Depth 3
# Child Loop BB2_6 Depth 4
cmpl $0, 12(%rsp) # 4-byte Folded Reload
jle .LBB2_14
# %bb.3: # %.preheader60.lr.ph
# in Loop: Header=BB2_2 Depth=1
movq 32(%rsp), %rdi # 8-byte Reload
leaq -2(%rdi), %r8
imulq %rax, %rdi
movq 16(%rsp), %r9 # 8-byte Reload
leaq (%r9,%rdi,4), %r9
movq 24(%rsp), %r10 # 8-byte Reload
xorl %edi, %edi
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_13: # in Loop: Header=BB2_4 Depth=2
incq %rdi
addq $4, %r10
cmpq %rdx, %rdi
je .LBB2_14
.LBB2_4: # %.preheader60
# Parent Loop BB2_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_5 Depth 3
# Child Loop BB2_6 Depth 4
movq %r10, %r13
movq %r14, %r15
xorl %ebp, %ebp
jmp .LBB2_5
.p2align 4, 0x90
.LBB2_12: # in Loop: Header=BB2_5 Depth=3
incq %rbp
addq $20, %r15
addq %rsi, %r13
cmpq $5, %rbp
je .LBB2_13
.LBB2_5: # %.preheader59
# Parent Loop BB2_2 Depth=1
# Parent Loop BB2_4 Depth=2
# => This Loop Header: Depth=3
# Child Loop BB2_6 Depth 4
leaq (%r8,%rbp), %rbx
movq $-2, %r12
jmp .LBB2_6
.p2align 4, 0x90
.LBB2_11: # in Loop: Header=BB2_6 Depth=4
incq %r12
cmpq $3, %r12
je .LBB2_12
.LBB2_6: # Parent Loop BB2_2 Depth=1
# Parent Loop BB2_4 Depth=2
# Parent Loop BB2_5 Depth=3
# => This Inner Loop Header: Depth=4
testq %rbx, %rbx
js .LBB2_11
# %bb.7: # in Loop: Header=BB2_6 Depth=4
cmpq %rcx, %rbx
jge .LBB2_11
# %bb.8: # in Loop: Header=BB2_6 Depth=4
movq %rdi, %r11
addq %r12, %r11
js .LBB2_11
# %bb.9: # in Loop: Header=BB2_6 Depth=4
cmpq %rax, %r11
jge .LBB2_11
# %bb.10: # in Loop: Header=BB2_6 Depth=4
movss 8(%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%r13,%r12,4), %xmm0
addss (%r9,%rdi,4), %xmm0
movss %xmm0, (%r9,%rdi,4)
jmp .LBB2_11
.LBB2_15: # %.preheader
movl 44(%rsp), %eax # 4-byte Reload
testl %eax, %eax
jle .LBB2_16
# %bb.17: # %.lr.ph.preheader
movl %eax, %r14d
movb $1, %al
movl $1, %r15d
movaps .LCPI2_0(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movss .LCPI2_1(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movq 16(%rsp), %rbx # 8-byte Reload
movq 48(%rsp), %r12 # 8-byte Reload
.p2align 4, 0x90
.LBB2_18: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss -4(%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss -4(%r12,%r15,4), %xmm0
andps %xmm1, %xmm0
ucomiss %xmm2, %xmm0
jb .LBB2_20
# %bb.19: # in Loop: Header=BB2_18 Depth=1
movl $.Lstr.2, %edi
callq puts@PLT
movss .LCPI2_1(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
movaps .LCPI2_0(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
xorl %eax, %eax
.LBB2_20: # in Loop: Header=BB2_18 Depth=1
cmpq %r14, %r15
jae .LBB2_22
# %bb.21: # in Loop: Header=BB2_18 Depth=1
movl %eax, %ecx
andb $1, %cl
incq %r15
testb %cl, %cl
jne .LBB2_18
.LBB2_22: # %._crit_edge68
movl $.Lstr.1, %ecx
movl $.Lstr, %edi
testb $1, %al
cmovneq %rcx, %rdi
jmp .LBB2_23
.LBB2_16:
movl $.Lstr.1, %edi
movq 16(%rsp), %rbx # 8-byte Reload
.LBB2_23: # %.critedge
callq puts@PLT
movq %rbx, %rdi
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp free # TAILCALL
.Lfunc_end2:
.size _Z12verificationPKfS0_S0_ii, .Lfunc_end2-_Z12verificationPKfS0_S0_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13Convolution2DPfS_S_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $Mc, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $100, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type Mc,@object # @Mc
.local Mc
.comm Mc,100,16
.type _Z13Convolution2DPfS_S_iiii,@object # @_Z13Convolution2DPfS_S_iiii
.section .rodata,"a",@progbits
.globl _Z13Convolution2DPfS_S_iiii
.p2align 3, 0x0
_Z13Convolution2DPfS_S_iiii:
.quad _Z28__device_stub__Convolution2DPfS_S_iiii
.size _Z13Convolution2DPfS_S_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13Convolution2DPfS_S_iiii"
.size .L__unnamed_1, 28
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "Mc"
.size .L__unnamed_2, 3
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Results are NOT equal!"
.size .Lstr, 23
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Results are equal!"
.size .Lstr.1, 19
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "NOT EQUAL!"
.size .Lstr.2, 11
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__Convolution2DPfS_S_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym Mc
.addrsig_sym _Z13Convolution2DPfS_S_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <ctime>
#include <cmath>
#define N (1024)
__global__ void kernel(float *dev)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (N % idx == 0) {
dev[idx] = (float) idx;
}
}
int main (int argc, char *argv[])
{
//------------------— GPU PART —----------------—
float arr [N];
float *dev = NULL;
cudaMalloc(&dev, N * sizeof(float));
kernel<<<2, 512>>> (dev);
cudaMemcpy(&arr, dev, N * sizeof(float), cudaMemcpyDeviceToHost);
for (int idx = 0; idx < N; idx++)
{
if (arr[idx] != 0) {
printf("%f ", arr[idx]);
}
}
cudaFree(dev);
return 0;
} | code for sm_80
Function : _Z6kernelPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ IABS R6, R0.reuse ; /* 0x0000000000067213 */
/* 0x080fe40000000000 */
/*0050*/ IABS R7, R0 ; /* 0x0000000000077213 */
/* 0x000fe40000000000 */
/*0060*/ I2F.RP R4, R6 ; /* 0x0000000600047306 */
/* 0x000e240000209400 */
/*0070*/ IADD3 R8, RZ, -R7, RZ ; /* 0x80000007ff087210 */
/* 0x000fcc0007ffe0ff */
/*0080*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0090*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*00a0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00b0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe200078e00ff */
/*00c0*/ IADD3 R5, RZ, -R3, RZ ; /* 0x80000003ff057210 */
/* 0x002fca0007ffe0ff */
/*00d0*/ IMAD R5, R5, R6, RZ ; /* 0x0000000605057224 */
/* 0x000fc800078e02ff */
/*00e0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*00f0*/ IMAD.HI.U32 R3, R3, 0x400, RZ ; /* 0x0000040003037827 */
/* 0x000fc800078e00ff */
/*0100*/ IMAD R3, R3, R8, 0x400 ; /* 0x0000040003037424 */
/* 0x000fca00078e0208 */
/*0110*/ ISETP.GT.U32.AND P0, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fda0003f04070 */
/*0120*/ @!P0 IMAD.IADD R3, R3, 0x1, -R6 ; /* 0x0000000103038824 */
/* 0x000fe200078e0a06 */
/*0130*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc80003f05270 */
/*0140*/ ISETP.GT.U32.AND P1, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fda0003f24070 */
/*0150*/ @!P1 IADD3 R3, R3, -R6, RZ ; /* 0x8000000603039210 */
/* 0x000fe40007ffe0ff */
/*0160*/ @!P0 LOP3.LUT R3, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff038212 */
/* 0x000fc800078e33ff */
/*0170*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0180*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0190*/ I2F R5, R0 ; /* 0x0000000000057306 */
/* 0x000e220000201400 */
/*01a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*01b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*01c0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*01d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <ctime>
#include <cmath>
#define N (1024)
__global__ void kernel(float *dev)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (N % idx == 0) {
dev[idx] = (float) idx;
}
}
int main (int argc, char *argv[])
{
//------------------— GPU PART —----------------—
float arr [N];
float *dev = NULL;
cudaMalloc(&dev, N * sizeof(float));
kernel<<<2, 512>>> (dev);
cudaMemcpy(&arr, dev, N * sizeof(float), cudaMemcpyDeviceToHost);
for (int idx = 0; idx < N; idx++)
{
if (arr[idx] != 0) {
printf("%f ", arr[idx]);
}
}
cudaFree(dev);
return 0;
} | .file "tmpxft_0014d308_00000000-6_LR2_VorobevAV.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z6kernelPfPf
.type _Z25__device_stub__Z6kernelPfPf, @function
_Z25__device_stub__Z6kernelPfPf:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z25__device_stub__Z6kernelPfPf, .-_Z25__device_stub__Z6kernelPfPf
.globl _Z6kernelPf
.type _Z6kernelPf, @function
_Z6kernelPf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z6kernelPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelPf, .-_Z6kernelPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%f "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $4096, %rsp
.cfi_def_cfa_offset 4128
orq $0, (%rsp)
subq $48, %rsp
.cfi_def_cfa_offset 4176
movq %fs:40, %rax
movq %rax, 4136(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq %rsp, %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $2, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L12:
leaq 32(%rsp), %rbx
movl $2, %ecx
movl $4096, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 4128(%rsp), %rbp
leaq .LC1(%rip), %r12
jmp .L15
.L20:
movq (%rsp), %rdi
call _Z25__device_stub__Z6kernelPfPf
jmp .L12
.L17:
cvtss2sd %xmm0, %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L13:
addq $4, %rbx
cmpq %rbp, %rbx
je .L21
.L15:
movss (%rbx), %xmm0
pxor %xmm1, %xmm1
ucomiss %xmm1, %xmm0
jp .L17
je .L13
jmp .L17
.L21:
movq (%rsp), %rdi
call cudaFree@PLT
movq 4136(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $4144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z6kernelPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <ctime>
#include <cmath>
#define N (1024)
__global__ void kernel(float *dev)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (N % idx == 0) {
dev[idx] = (float) idx;
}
}
int main (int argc, char *argv[])
{
//------------------— GPU PART —----------------—
float arr [N];
float *dev = NULL;
cudaMalloc(&dev, N * sizeof(float));
kernel<<<2, 512>>> (dev);
cudaMemcpy(&arr, dev, N * sizeof(float), cudaMemcpyDeviceToHost);
for (int idx = 0; idx < N; idx++)
{
if (arr[idx] != 0) {
printf("%f ", arr[idx]);
}
}
cudaFree(dev);
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <ctime>
#include <cmath>
#define N (1024)
__global__ void kernel(float *dev)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (N % idx == 0) {
dev[idx] = (float) idx;
}
}
int main (int argc, char *argv[])
{
//------------------— GPU PART —----------------—
float arr [N];
float *dev = NULL;
hipMalloc(&dev, N * sizeof(float));
kernel<<<2, 512>>> (dev);
hipMemcpy(&arr, dev, N * sizeof(float), hipMemcpyDeviceToHost);
for (int idx = 0; idx < N; idx++)
{
if (arr[idx] != 0) {
printf("%f ", arr[idx]);
}
}
hipFree(dev);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <ctime>
#include <cmath>
#define N (1024)
__global__ void kernel(float *dev)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (N % idx == 0) {
dev[idx] = (float) idx;
}
}
int main (int argc, char *argv[])
{
//------------------— GPU PART —----------------—
float arr [N];
float *dev = NULL;
hipMalloc(&dev, N * sizeof(float));
kernel<<<2, 512>>> (dev);
hipMemcpy(&arr, dev, N * sizeof(float), hipMemcpyDeviceToHost);
for (int idx = 0; idx < N; idx++)
{
if (arr[idx] != 0) {
printf("%f ", arr[idx]);
}
}
hipFree(dev);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPf
.globl _Z6kernelPf
.p2align 8
.type _Z6kernelPf,@function
_Z6kernelPf:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_ashrrev_i32_e32 v0, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v1, v0
v_xor_b32_e32 v0, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cvt_f32_u32_e32 v2, v0
v_sub_nc_u32_e32 v3, 0, v0
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v2, v2
v_mul_lo_u32 v3, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v2, v3
v_add_nc_u32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v2, 22, v2
v_mul_lo_u32 v2, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, 0x400, v2
v_sub_nc_u32_e32 v3, v2, v0
v_cmp_ge_u32_e32 vcc_lo, v2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_sub_nc_u32_e32 v3, v2, v0
v_cmp_ge_u32_e32 vcc_lo, v2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v2, v3, vcc_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_cvt_f32_i32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPf, .Lfunc_end0-_Z6kernelPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <ctime>
#include <cmath>
#define N (1024)
__global__ void kernel(float *dev)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (N % idx == 0) {
dev[idx] = (float) idx;
}
}
int main (int argc, char *argv[])
{
//------------------— GPU PART —----------------—
float arr [N];
float *dev = NULL;
hipMalloc(&dev, N * sizeof(float));
kernel<<<2, 512>>> (dev);
hipMemcpy(&arr, dev, N * sizeof(float), hipMemcpyDeviceToHost);
for (int idx = 0; idx < N; idx++)
{
if (arr[idx] != 0) {
printf("%f ", arr[idx]);
}
}
hipFree(dev);
return 0;
} | .text
.file "LR2_VorobevAV.hip"
.globl _Z21__device_stub__kernelPf # -- Begin function _Z21__device_stub__kernelPf
.p2align 4, 0x90
.type _Z21__device_stub__kernelPf,@function
_Z21__device_stub__kernelPf: # @_Z21__device_stub__kernelPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z6kernelPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPf, .Lfunc_end0-_Z21__device_stub__kernelPf
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x00000000 # float 0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $4160, %rsp # imm = 0x1040
.cfi_def_cfa_offset 4176
.cfi_offset %rbx, -16
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 510(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z6kernelPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 64(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_3 Depth=1
incq %rbx
cmpq $1024, %rbx # imm = 0x400
je .LBB1_6
.LBB1_3: # =>This Inner Loop Header: Depth=1
movss 64(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss .LCPI1_0(%rip), %xmm0
jne .LBB1_4
jnp .LBB1_5
.LBB1_4: # in Loop: Header=BB1_3 Depth=1
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
jmp .LBB1_5
.LBB1_6:
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $4160, %rsp # imm = 0x1040
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPf,@object # @_Z6kernelPf
.section .rodata,"a",@progbits
.globl _Z6kernelPf
.p2align 3, 0x0
_Z6kernelPf:
.quad _Z21__device_stub__kernelPf
.size _Z6kernelPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPf"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ IABS R6, R0.reuse ; /* 0x0000000000067213 */
/* 0x080fe40000000000 */
/*0050*/ IABS R7, R0 ; /* 0x0000000000077213 */
/* 0x000fe40000000000 */
/*0060*/ I2F.RP R4, R6 ; /* 0x0000000600047306 */
/* 0x000e240000209400 */
/*0070*/ IADD3 R8, RZ, -R7, RZ ; /* 0x80000007ff087210 */
/* 0x000fcc0007ffe0ff */
/*0080*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0090*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*00a0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00b0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe200078e00ff */
/*00c0*/ IADD3 R5, RZ, -R3, RZ ; /* 0x80000003ff057210 */
/* 0x002fca0007ffe0ff */
/*00d0*/ IMAD R5, R5, R6, RZ ; /* 0x0000000605057224 */
/* 0x000fc800078e02ff */
/*00e0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*00f0*/ IMAD.HI.U32 R3, R3, 0x400, RZ ; /* 0x0000040003037827 */
/* 0x000fc800078e00ff */
/*0100*/ IMAD R3, R3, R8, 0x400 ; /* 0x0000040003037424 */
/* 0x000fca00078e0208 */
/*0110*/ ISETP.GT.U32.AND P0, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fda0003f04070 */
/*0120*/ @!P0 IMAD.IADD R3, R3, 0x1, -R6 ; /* 0x0000000103038824 */
/* 0x000fe200078e0a06 */
/*0130*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc80003f05270 */
/*0140*/ ISETP.GT.U32.AND P1, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fda0003f24070 */
/*0150*/ @!P1 IADD3 R3, R3, -R6, RZ ; /* 0x8000000603039210 */
/* 0x000fe40007ffe0ff */
/*0160*/ @!P0 LOP3.LUT R3, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff038212 */
/* 0x000fc800078e33ff */
/*0170*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0180*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0190*/ I2F R5, R0 ; /* 0x0000000000057306 */
/* 0x000e220000201400 */
/*01a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*01b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*01c0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*01d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPf
.globl _Z6kernelPf
.p2align 8
.type _Z6kernelPf,@function
_Z6kernelPf:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_ashrrev_i32_e32 v0, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v1, v0
v_xor_b32_e32 v0, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cvt_f32_u32_e32 v2, v0
v_sub_nc_u32_e32 v3, 0, v0
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v2, v2
v_mul_lo_u32 v3, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v2, v3
v_add_nc_u32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v2, 22, v2
v_mul_lo_u32 v2, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, 0x400, v2
v_sub_nc_u32_e32 v3, v2, v0
v_cmp_ge_u32_e32 vcc_lo, v2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_sub_nc_u32_e32 v3, v2, v0
v_cmp_ge_u32_e32 vcc_lo, v2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v2, v3, vcc_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_cvt_f32_i32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPf, .Lfunc_end0-_Z6kernelPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014d308_00000000-6_LR2_VorobevAV.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z6kernelPfPf
.type _Z25__device_stub__Z6kernelPfPf, @function
_Z25__device_stub__Z6kernelPfPf:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernelPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z25__device_stub__Z6kernelPfPf, .-_Z25__device_stub__Z6kernelPfPf
.globl _Z6kernelPf
.type _Z6kernelPf, @function
_Z6kernelPf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z6kernelPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelPf, .-_Z6kernelPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%f "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $4096, %rsp
.cfi_def_cfa_offset 4128
orq $0, (%rsp)
subq $48, %rsp
.cfi_def_cfa_offset 4176
movq %fs:40, %rax
movq %rax, 4136(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq %rsp, %rdi
movl $4096, %esi
call cudaMalloc@PLT
movl $512, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $2, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L12:
leaq 32(%rsp), %rbx
movl $2, %ecx
movl $4096, %edx
movq (%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 4128(%rsp), %rbp
leaq .LC1(%rip), %r12
jmp .L15
.L20:
movq (%rsp), %rdi
call _Z25__device_stub__Z6kernelPfPf
jmp .L12
.L17:
cvtss2sd %xmm0, %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
.L13:
addq $4, %rbx
cmpq %rbp, %rbx
je .L21
.L15:
movss (%rbx), %xmm0
pxor %xmm1, %xmm1
ucomiss %xmm1, %xmm0
jp .L17
je .L13
jmp .L17
.L21:
movq (%rsp), %rdi
call cudaFree@PLT
movq 4136(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $4144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z6kernelPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "LR2_VorobevAV.hip"
.globl _Z21__device_stub__kernelPf # -- Begin function _Z21__device_stub__kernelPf
.p2align 4, 0x90
.type _Z21__device_stub__kernelPf,@function
_Z21__device_stub__kernelPf: # @_Z21__device_stub__kernelPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z6kernelPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPf, .Lfunc_end0-_Z21__device_stub__kernelPf
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x00000000 # float 0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $4160, %rsp # imm = 0x1040
.cfi_def_cfa_offset 4176
.cfi_offset %rbx, -16
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 510(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z6kernelPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 64(%rsp), %rdi
movl $4096, %edx # imm = 0x1000
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_3 Depth=1
incq %rbx
cmpq $1024, %rbx # imm = 0x400
je .LBB1_6
.LBB1_3: # =>This Inner Loop Header: Depth=1
movss 64(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss .LCPI1_0(%rip), %xmm0
jne .LBB1_4
jnp .LBB1_5
.LBB1_4: # in Loop: Header=BB1_3 Depth=1
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
jmp .LBB1_5
.LBB1_6:
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $4160, %rsp # imm = 0x1040
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPf,@object # @_Z6kernelPf
.section .rodata,"a",@progbits
.globl _Z6kernelPf
.p2align 3, 0x0
_Z6kernelPf:
.quad _Z21__device_stub__kernelPf
.size _Z6kernelPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPf"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "matrix.cuh"
#include <stdexcept>
#define THREAD_X 8
#define THREAD_Y 8
/**
* @brief The cuda kernel to add two 2D matrices.
*
* @tparam T, the type of value to retrieve.
*
* @param[in] width, the width of the two matrices.
* @param[in] height, the height of the two matrices.
* @param[in] m, the first matrix.
* @param[in] n, the second matrix.
* @param[out] output, 1D array containing the add result.
*
*/
template <typename T>
__global__ void addKernel(const int _width, const int _height, const T* _m, const T* _n, T* _output)
{
const auto col = threadIdx.x + blockIdx.x * blockDim.x;
const auto row = threadIdx.y + blockIdx.y * blockDim.y;
if (col >= _width || row >= _height) return;
const auto index = row * _width + col;
_output[index] = _m[index] + _n[index];
}
/**
* @brief Launch the cuda kernel to add two 2D matrices.
*
* @param[in] width, the width of the two matrices.
* @param[in] height, the height of the two matrices.
* @param[in] h_matrix1, the first matrix.
* @param[in] h_matrix2, the second matrix.
*
* @returns the result of the add inside 1D host vector.
*/
const thrust::host_vector<int> launchAdd(const int _width, const int _height, const int _width2, const int _height2, const thrust::host_vector<int>& h_matrix1, const thrust::host_vector<int>& h_matrix2)
{
if (_width != _width2 || _height != _height2) {
throw std::length_error("matrix1 width height != matrix2 width height");
}
else {
const dim3 blocks(_width / THREAD_X + 1, _height / THREAD_Y + 1);
const dim3 threads(THREAD_X, THREAD_Y);
const thrust::device_vector<int> d_matrix1 = h_matrix1;
const int* matrix1BufferArray = thrust::raw_pointer_cast(&d_matrix1[0]);
const thrust::device_vector<int> d_matrix2 = h_matrix2;
const int* matrix2BufferArray = thrust::raw_pointer_cast(&d_matrix2[0]);
thrust::device_vector<int> d_result(_width * _height);
int* resultBufferArray = thrust::raw_pointer_cast(&d_result[0]);
addKernel << <blocks, threads >> > (_width, _height, matrix1BufferArray, matrix2BufferArray, resultBufferArray);
cudaDeviceSynchronize();
const thrust::host_vector<int> h_result = d_result;
return h_result;
}
}
/**
* @brief The cuda kernel to minus two 2D matrices.
*
* @tparam T, the type of value to retrieve.
*
* @param[in] width, the width of the two matrices.
* @param[in] height, the height of the two matrices.
* @param[in] m, the first matrix.
* @param[in] n, the second matrix.
* @param[out] output, 1D array containing the minus result.
*
*/
template <typename T>
__global__ void minusKernel(const int _width, const int _height, const T* _m, const T* _n, T* _output)
{
const auto col = threadIdx.x + blockIdx.x * blockDim.x;
const auto row = threadIdx.y + blockIdx.y * blockDim.y;
if (col >= _width || row >= _height) return;
const auto index = row * _width + col;
_output[index] = _m[index] - _n[index];
}
/**
* @brief Launch the cuda kernel to minus two 2D matrices.
*
* @param[in] width, the width of the two matrices.
* @param[in] height, the height of the two matrices.
* @param[in] h_matrix1, the first matrix.
* @param[in] h_matrix2, the second matrix.
*
* @returns the result of the add inside 1D host vector.
*/
const thrust::host_vector<int> launchMinus(const int _width, const int _height, const int _width2, const int _height2, const thrust::host_vector<int>& h_matrix1, const thrust::host_vector<int>& h_matrix2)
{
if (_width != _width2 || _height != _height2) {
throw std::length_error("matrix1 width height != matrix2 width height");
}
else {
const dim3 blocks(_width / THREAD_X + 1, _height / THREAD_Y + 1);
const dim3 threads(THREAD_X, THREAD_Y);
const thrust::device_vector<int> d_matrix1 = h_matrix1;
const int* matrix1BufferArray = thrust::raw_pointer_cast(&d_matrix1[0]);
const thrust::device_vector<int> d_matrix2 = h_matrix2;
const int* matrix2BufferArray = thrust::raw_pointer_cast(&d_matrix2[0]);
thrust::device_vector<int> d_result(_width * _height);
int* resultBufferArray = thrust::raw_pointer_cast(&d_result[0]);
minusKernel << <blocks, threads >> > (_width, _height, matrix1BufferArray, matrix2BufferArray, resultBufferArray);
cudaDeviceSynchronize();
const thrust::host_vector<int> h_result = d_result;
return h_result;
}
}
/**
* @brief The cuda kernel to apply Hadamard operation to two 2D matrices.
*
* @tparam T, the type of value to retrieve.
*
* @param[in] width, the width of the two matrices.
* @param[in] height, the height of the two matrices.
* @param[in] m, the first matrix.
* @param[in] n, the second matrix.
* @param[out] output, 1D array containing the Hadamard result.
*
*/
template <typename T>
__global__ void hadamardKernel(const int _width, const int _height, const T* _m, const T* _n, T* _output)
{
const auto col = threadIdx.x + blockIdx.x * blockDim.x;
const auto row = threadIdx.y + blockIdx.y * blockDim.y;
if (col >= _width || row >= _height) return;
const auto index = row * _width + col;
_output[index] = _m[index] * _n[index];
}
/**
* @brief Launch the cuda kernel to apply the Hadamard product to two 2D matrices.
*
* @param[in] width, the width of the two matrices.
* @param[in] height, the height of the two matrices.
* @param[in] h_matrix1, the first matrix.
* @param[in] h_matrix2, the second matrix.
*
* @returns the result of the Hadamard product inside 1D host vector.
*/
const thrust::host_vector<int> launchHadamard(const int _width, const int _height, const int _width2, const int _height2, const thrust::host_vector<int>& h_matrix1, const thrust::host_vector<int>& h_matrix2)
{
if (_width != _width2 || _height != _height2) {
throw std::length_error("matrix1 width height != matrix2 width height");
}
else {
const dim3 blocks(_width / THREAD_X + 1, _height / THREAD_Y + 1);
const dim3 threads(THREAD_X, THREAD_Y);
const thrust::device_vector<int> d_matrix1 = h_matrix1;
const int* matrix1BufferArray = thrust::raw_pointer_cast(&d_matrix1[0]);
const thrust::device_vector<int> d_matrix2 = h_matrix2;
const int* matrix2BufferArray = thrust::raw_pointer_cast(&d_matrix2[0]);
thrust::device_vector<int> d_result(_width * _height);
int* resultBufferArray = thrust::raw_pointer_cast(&d_result[0]);
minusKernel << <blocks, threads >> > (_width, _height, matrix1BufferArray, matrix2BufferArray, resultBufferArray);
cudaDeviceSynchronize();
const thrust::host_vector<int> h_result = d_result;
return h_result;
}
}
/**
* @brief The cuda kernel to apply the multiplication of two matrices.
*
* @tparam T, the type of value to retrieve.
*
* @param[in] width, the width of the m matrix.
* @param[in] height, the height of the n matrix.
* @param[in] n, the first matrix.
* @param[in] m, the second matrix.
* @param[out] output, 1D array containing the multiplication result.
*
*/
template <typename T>
__global__ void multKernel(const int _width, const int _height, const T* _m, const T* _n, T* _output)
{
const auto col = threadIdx.x + blockIdx.x * blockDim.x;
const auto row = threadIdx.y + blockIdx.y * blockDim.y;
if (col >= _width || row >= _height) return;
T tmpSum = 0;
for (auto i = 0; i < _width; ++i) {
tmpSum += _m[row * _width + i] * _n[i * _width + col];
}
_output[row * _width + col] = tmpSum;
}
/**
* @brief Launch the cuda kernel to apply the multiplication of two matrices.
*
* @param[in] width, the width of the h_matrix1.
* @param[in] height, the height of the h_matrix1.
* @param[in] width2, the width of the h_matrix2.
* @param[in] height2, the height of the h_matrix2.
* @param[in] h_matrix1, the first matrix.
* @param[in] h_matrix2, the second matrix.
*
* @returns width, height and the result of the Hadamard product inside 1D host vector.
*/
const std::tuple<int, int, thrust::host_vector<int>> launchMultiplication(const int _width, const int _height, const int _width2, const int _height2, const thrust::host_vector<int>& h_matrix1, const thrust::host_vector<int>& h_matrix2)
{
if (_height != _width2) {
throw std::length_error("matrix1 height != matrix2 width");
}
else {
const dim3 blocks(_width2 / THREAD_X + 1, _height / THREAD_Y + 1);
const dim3 threads(THREAD_X, THREAD_Y);
const thrust::device_vector<int> d_matrix1 = h_matrix1;
const int* matrix1BufferArray = thrust::raw_pointer_cast(&d_matrix1[0]);
const thrust::device_vector<int> d_matrix2 = h_matrix2;
const int* matrix2BufferArray = thrust::raw_pointer_cast(&d_matrix2[0]);
thrust::device_vector<int> d_result(_width2 * _height);
int* resultBufferArray = thrust::raw_pointer_cast(&d_result[0]);
minusKernel << <blocks, threads >> > (_width2, _height, matrix1BufferArray, matrix2BufferArray, resultBufferArray);
cudaDeviceSynchronize();
const thrust::host_vector<int> h_result = d_result;
return std::make_tuple(_width2, _height, h_result);
}
}
/**
* @brief The cuda kernel to transpose the matrix.
*
* @tparam T, the type of value to retrieve.
*
* @param[in] width, the width of the m matrix.
* @param[in] height, the height of the m matrix.
* @param[in] m, the matrix.
* @param[out] output, 1D array containing the result.
*
*/
template <typename T>
__global__ void transposeKernel(const int _width, const int _height, const T* _m, T* _output)
{
const auto col = threadIdx.x + blockIdx.x * blockDim.x;
const auto row = threadIdx.y + blockIdx.y * blockDim.y;
if (col >= _width || row >= _height) return;
_output[row + _height * col] = _m[col + _width * row];
}
/**
* @brief Launch the cuda kernel to transpose the matrix.
*
* @param[in] width, the width of the m matrix.
* @param[in] height, the height of the m matrix.
* @param[in] m, the matrix.
*
* @returns the result of the transposed matrix inside a 1D host vector.
*/
const std::tuple<int, int, thrust::host_vector<int>> launchTransposition(const int _width, const int _height, const thrust::host_vector<int>& h_matrix)
{
const dim3 blocks(_width / THREAD_X + 1, _height / THREAD_Y + 1);
const dim3 threads(THREAD_X, THREAD_Y);
const thrust::device_vector<int> d_matrix1 = h_matrix;
const int* matrixBufferArray = thrust::raw_pointer_cast(&d_matrix1[0]);
thrust::device_vector<int> d_result(_width * _height);
int* resultBufferArray = thrust::raw_pointer_cast(&d_result[0]);
transposeKernel << <blocks, threads >> > (_width, _height, matrixBufferArray, resultBufferArray);
cudaDeviceSynchronize();
const thrust::host_vector<int> h_result = d_result;
return std::make_tuple(_height, _width, h_result);;
}
/**
* @brief The cuda kernel to rotate at 90° the matrix.
*
* @tparam T, the type of value to retrieve.
*
* @param[in] size, the width of the m matrix.
* @param[in] m, the matrix.
* @param[out] output, 1D array containing the result.
*
*/
template <typename T>
__global__ void rotate90MatrixKernel(const int _size, const T* _m, T* _output)
{
const auto layer = threadIdx.x + blockIdx.x * blockDim.x;
const auto index = threadIdx.y + blockIdx.y * blockDim.y;
const auto first = layer;
const auto last = _size - 1 - layer;
if (layer >= _size / 2 || index >= last) return;
const auto offset = index - first;
//Left -> top
_output[first * _size + index] = _m[(last - offset) * _size + first];
//Bottom -> left
_output[(last - offset) * _size + first] = _m[last * _size + last - offset];
//Right -> bottom
_output[last * _size + last - offset] = _m[index * _size + last];
//Top -> right
_output[index * _size + last] = _m[first * _size + index];
}
/**
* @brief Launch the cuda kernel to rotate the matrix.
*
* @param[in] width, the width of the m matrix.
* @param[in] height, the height of the m matrix.
* @param[in] m, the matrix.
*
* @returns the result of the rotated matrix inside a 1D host vector.
*/
const thrust::host_vector<int> launchRotation90Dgr(const int _width, const int _height, const thrust::host_vector<int>& h_matrix)
{
if (_width != _height){
throw std::length_error(" _width != _height");
}
else
{
const dim3 blocks(_width / THREAD_X + 1, _height / THREAD_Y + 1);
const dim3 threads(THREAD_X, THREAD_Y);
const thrust::device_vector<int> d_matrix1 = h_matrix;
const int* matrixBufferArray = thrust::raw_pointer_cast(&d_matrix1[0]);
thrust::device_vector<int> d_result(_width * _height);
int* resultBufferArray = thrust::raw_pointer_cast(&d_result[0]);
rotate90MatrixKernel << <blocks, threads >> > (_width, matrixBufferArray, resultBufferArray);
cudaDeviceSynchronize();
const thrust::host_vector<int> h_result = d_result;
return h_result;
}
}
/**
* @brief The cuda kernel to upper triangular the matrix.
*
* @tparam T, the type of value to retrieve.
*
* @param[in] size, the width of the m matrix.
* @param[out] m, the matrix result.
*
*/
template <typename T>
__global__ void upperTriangularMatrixKernel(const int _size, T* _m)
{
const auto col = threadIdx.x + blockIdx.x * blockDim.x;
const auto row = threadIdx.y + blockIdx.y * blockDim.y;
if (col >= _size - 1 || row <= row + 1 || row >= _size) return;
T temp = _m[row * _size + col] / _m[col * _size + col];
for (auto k = 0; k < _size + 1; ++k) {
_m[row * _size + k] -= (_m[col * _size + k] * temp);
}
}
/**
* @brief Launch the cuda kernel to upper triangular the matrix.
*
* @param[in] width, the width of the m matrix.
* @param[in] height, the height of the m matrix.
* @param[out] h_matrix, the matrix.
*
* @returns the result of the rotated matrix inside a 1D host vector.
*/
const thrust::host_vector<int> launchUpperTriangular(const int _width, const int _height, const thrust::host_vector<int>& h_matrix)
{
if (_width != _height){
throw std::length_error(" _width != _height");
}
else {
const dim3 blocks(_width / THREAD_X + 1, _height / THREAD_Y + 1);
const dim3 threads(THREAD_X, THREAD_Y);
thrust::device_vector<int> d_matrix1 = h_matrix;
int* matrixBufferArray = thrust::raw_pointer_cast(&d_matrix1[0]);
upperTriangularMatrixKernel << <blocks, threads >> > (_width, matrixBufferArray);
cudaDeviceSynchronize();
const thrust::host_vector<int> h_result = d_matrix1;
return h_result;
}
} | #include "hip/hip_runtime.h"
#include "thrust/device_vector.h"
#include "thrust/host_vector.h"
const thrust::host_vector<int> launchAdd(const int _width, const int _height, const int _width2, const int _height2, const thrust::host_vector<int>& h_matrix1, const thrust::host_vector<int>& h_matrix2);
const thrust::host_vector<int> launchMinus(const int _width, const int _height, const int _width2, const int _height2, const thrust::host_vector<int>& h_matrix1, const thrust::host_vector<int>& h_matrix2);
const thrust::host_vector<int> launchHadamard(const int _width, const int _height, const int _width2, const int _height2, const thrust::host_vector<int>& h_matrix1, const thrust::host_vector<int>& h_matrix2);
const thrust::host_vector<int> launchRotation90Dgr(const int _width, const int _height, const thrust::host_vector<int>& h_matrix);
const thrust::host_vector<int> launchUpperTriangular(const int _width, const int _height, const thrust::host_vector<int>& h_matrix);
const std::tuple<int, int, thrust::host_vector<int>> launchMultiplication(const int _width, const int _height, const int _width2, const int _height2, const thrust::host_vector<int>& h_matrix1, const thrust::host_vector<int>& h_matrix2);
const std::tuple<int, int, thrust::host_vector<int>> launchTransposition(const int _width, const int _height, const thrust::host_vector<int>& h_matrix); |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include "thrust/device_vector.h"
#include "thrust/host_vector.h"
const thrust::host_vector<int> launchAdd(const int _width, const int _height, const int _width2, const int _height2, const thrust::host_vector<int>& h_matrix1, const thrust::host_vector<int>& h_matrix2);
const thrust::host_vector<int> launchMinus(const int _width, const int _height, const int _width2, const int _height2, const thrust::host_vector<int>& h_matrix1, const thrust::host_vector<int>& h_matrix2);
const thrust::host_vector<int> launchHadamard(const int _width, const int _height, const int _width2, const int _height2, const thrust::host_vector<int>& h_matrix1, const thrust::host_vector<int>& h_matrix2);
const thrust::host_vector<int> launchRotation90Dgr(const int _width, const int _height, const thrust::host_vector<int>& h_matrix);
const thrust::host_vector<int> launchUpperTriangular(const int _width, const int _height, const thrust::host_vector<int>& h_matrix);
const std::tuple<int, int, thrust::host_vector<int>> launchMultiplication(const int _width, const int _height, const int _width2, const int _height2, const thrust::host_vector<int>& h_matrix1, const thrust::host_vector<int>& h_matrix2);
const std::tuple<int, int, thrust::host_vector<int>> launchTransposition(const int _width, const int _height, const thrust::host_vector<int>& h_matrix); | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include "thrust/device_vector.h"
#include "thrust/host_vector.h"
const thrust::host_vector<int> launchAdd(const int _width, const int _height, const int _width2, const int _height2, const thrust::host_vector<int>& h_matrix1, const thrust::host_vector<int>& h_matrix2);
const thrust::host_vector<int> launchMinus(const int _width, const int _height, const int _width2, const int _height2, const thrust::host_vector<int>& h_matrix1, const thrust::host_vector<int>& h_matrix2);
const thrust::host_vector<int> launchHadamard(const int _width, const int _height, const int _width2, const int _height2, const thrust::host_vector<int>& h_matrix1, const thrust::host_vector<int>& h_matrix2);
const thrust::host_vector<int> launchRotation90Dgr(const int _width, const int _height, const thrust::host_vector<int>& h_matrix);
const thrust::host_vector<int> launchUpperTriangular(const int _width, const int _height, const thrust::host_vector<int>& h_matrix);
const std::tuple<int, int, thrust::host_vector<int>> launchMultiplication(const int _width, const int _height, const int _width2, const int _height2, const thrust::host_vector<int>& h_matrix1, const thrust::host_vector<int>& h_matrix2);
const std::tuple<int, int, thrust::host_vector<int>> launchTransposition(const int _width, const int _height, const thrust::host_vector<int>& h_matrix); | .text
.file "matrix.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe400078210ff */
/*00b0*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fc40003f04100 */
/*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fd600008f1403 */
/*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */
/* 0x000fe40000011404 */
/*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */
/* 0x000fca00078e00ff */
/*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fc80003f04070 */
/*0150*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x001fca00078e00ff */
/*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fca00078e00ff */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z27upperTriangularMatrixKernelIiEviPT_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe40000000000 */
/*0030*/ ULDC UR5, c[0x0][0x160] ; /* 0x0000580000057ab9 */
/* 0x000fe20000000800 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ UIADD3 UR4, -UR4, UR5, URZ ; /* 0x0000000504047290 */
/* 0x000fc6000fffe13f */
/*0060*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0070*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0090*/ ISETP.GE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fe2000bf06070 */
/*00a0*/ IMAD R2, R2, c[0x0][0x4], R5 ; /* 0x0000010002027a24 */
/* 0x002fca00078e0205 */
/*00b0*/ ISETP.NE.OR P0, PT, R2, -0x1, P0 ; /* 0xffffffff0200780c */
/* 0x000fc80000705670 */
/*00c0*/ ISETP.GE.U32.OR P0, PT, R2, c[0x0][0x160], P0 ; /* 0x0000580002007a0c */
/* 0x000fda0000706470 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0100*/ IMAD R3, R0, c[0x0][0x160], R0 ; /* 0x0000580000037a24 */
/* 0x000fc800078e0200 */
/*0110*/ IMAD.WIDE.U32 R2, R3, R4, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fcc00078e0004 */
/*0120*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0130*/ IADD3 R7, R0, -c[0x0][0x160], RZ ; /* 0x8000580000077a10 */
/* 0x000fca0007ffe0ff */
/*0140*/ IMAD.WIDE.U32 R6, R7, R4, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fcc00078e0004 */
/*0150*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ee2000c1e1900 */
/*0160*/ ISETP.LE.AND P0, PT, RZ, c[0x0][0x160], PT ; /* 0x00005800ff007a0c */
/* 0x000fe40003f03270 */
/*0170*/ IABS R10, R2.reuse ; /* 0x00000002000a7213 */
/* 0x084fe40000000000 */
/*0180*/ IABS R11, R2 ; /* 0x00000002000b7213 */
/* 0x000fe40000000000 */
/*0190*/ I2F.RP R5, R10 ; /* 0x0000000a00057306 */
/* 0x000e240000209400 */
/*01a0*/ IADD3 R11, RZ, -R11, RZ ; /* 0x8000000bff0b7210 */
/* 0x000fe40007ffe0ff */
/*01b0*/ IABS R6, R7 ; /* 0x0000000700067213 */
/* 0x008fc40000000000 */
/*01c0*/ LOP3.LUT R7, R7, R2, RZ, 0x3c, !PT ; /* 0x0000000207077212 */
/* 0x000fe400078e3cff */
/*01d0*/ MUFU.RCP R5, R5 ; /* 0x0000000500057308 */
/* 0x001e240000001000 */
/*01e0*/ IADD3 R8, R5, 0xffffffe, RZ ; /* 0x0ffffffe05087810 */
/* 0x001fcc0007ffe0ff */
/*01f0*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000064000021f000 */
/*0200*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x001fe400078e00ff */
/*0210*/ IMAD.MOV R3, RZ, RZ, -R9 ; /* 0x000000ffff037224 */
/* 0x002fc800078e0a09 */
/*0220*/ IMAD R3, R3, R10, RZ ; /* 0x0000000a03037224 */
/* 0x000fc800078e02ff */
/*0230*/ IMAD.HI.U32 R9, R9, R3, R8 ; /* 0x0000000309097227 */
/* 0x000fc800078e0008 */
/*0240*/ IMAD.MOV.U32 R3, RZ, RZ, R11 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000b */
/*0250*/ IMAD.HI.U32 R5, R9, R6, RZ ; /* 0x0000000609057227 */
/* 0x000fc800078e00ff */
/*0260*/ IMAD R3, R5, R3, R6 ; /* 0x0000000305037224 */
/* 0x000fca00078e0206 */
/*0270*/ ISETP.GT.U32.AND P2, PT, R10, R3, PT ; /* 0x000000030a00720c */
/* 0x000fda0003f44070 */
/*0280*/ @!P2 IADD3 R3, R3, -R10, RZ ; /* 0x8000000a0303a210 */
/* 0x000fc80007ffe0ff */
/*0290*/ ISETP.GE.U32.AND P1, PT, R3, R10, PT ; /* 0x0000000a0300720c */
/* 0x000fe20003f26070 */
/*02a0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fd80003800000 */
/*02b0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff037624 */
/* 0x000fe200078e00ff */
/*02c0*/ ISETP.GE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f06270 */
/*02d0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fe200078e00ff */
/*02e0*/ @!P2 IADD3 R5, R5, 0x1, RZ ; /* 0x000000010505a810 */
/* 0x000fe20007ffe0ff */
/*02f0*/ IMAD.MOV.U32 R17, RZ, RZ, RZ ; /* 0x000000ffff117224 */
/* 0x000fe200078e00ff */
/*0300*/ ISETP.GE.U32.AND P3, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f66070 */
/*0310*/ ISETP.NE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f45270 */
/*0320*/ IADD3 R8, R9, c[0x0][0x160], RZ ; /* 0x0000580009087a10 */
/* 0x000fc40007ffe0ff */
/*0330*/ @P1 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105051810 */
/* 0x000fe40007ffe0ff */
/*0340*/ LOP3.LUT R8, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308087812 */
/* 0x000fe400078ec0ff */
/*0350*/ @!P0 IADD3 R5, -R5, RZ, RZ ; /* 0x000000ff05058210 */
/* 0x000fe40007ffe1ff */
/*0360*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc60003f25270 */
/*0370*/ @!P2 LOP3.LUT R5, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff05a212 */
/* 0x000fe200078e33ff */
/*0380*/ @!P3 BRA 0x670 ; /* 0x000002e00000b947 */
/* 0x000ff20003800000 */
/*0390*/ IADD3 R14, R8, -c[0x0][0x160], RZ ; /* 0x80005800080e7a10 */
/* 0x000fe20007ffe0ff */
/*03a0*/ IMAD R15, R0.reuse, R3.reuse, 0x3 ; /* 0x00000003000f7424 */
/* 0x0c0fe200078e0203 */
/*03b0*/ IADD3 R13, -R3, 0x3, RZ ; /* 0x00000003030d7810 */
/* 0x000fe20007ffe1ff */
/*03c0*/ IMAD R12, R0, R3, 0x1 ; /* 0x00000001000c7424 */
/* 0x000fe200078e0203 */
/*03d0*/ IADD3 R14, R14, -0x1, RZ ; /* 0xffffffff0e0e7810 */
/* 0x000fe20007ffe0ff */
/*03e0*/ IMAD.MOV.U32 R17, RZ, RZ, RZ ; /* 0x000000ffff117224 */
/* 0x000fc800078e00ff */
/*03f0*/ IMAD R7, R0, c[0x0][0x160], R17 ; /* 0x0000580000077a24 */
/* 0x001fe200078e0211 */
/*0400*/ IADD3 R11, R17, -c[0x0][0x160], RZ ; /* 0x80005800110b7a10 */
/* 0x000fc60007ffe0ff */
/*0410*/ IMAD.WIDE.U32 R6, R7, R4, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fc800078e0004 */
/*0420*/ IMAD.WIDE.U32 R10, R11, R4, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x000fe400078e0004 */
/*0430*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*0440*/ LDG.E R2, [R10.64] ; /* 0x000000040a027981 */
/* 0x000ee2000c1e1900 */
/*0450*/ IMAD.IADD R19, R12, 0x1, R17 ; /* 0x000000010c137824 */
/* 0x000fe200078e0211 */
/*0460*/ IADD3 R3, R17, -c[0x0][0x160], R9 ; /* 0x8000580011037a10 */
/* 0x000fc60007ffe009 */
/*0470*/ IMAD.WIDE.U32 R18, R19, R4, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x000fe200078e0004 */
/*0480*/ IADD3 R23, -R6, RZ, RZ ; /* 0x000000ff06177210 */
/* 0x004fca0007ffe1ff */
/*0490*/ IMAD R23, R5, R23, R2 ; /* 0x0000001705177224 */
/* 0x008fe400078e0202 */
/*04a0*/ IMAD.WIDE.U32 R2, R3, R4, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fc600078e0004 */
/*04b0*/ STG.E [R10.64], R23 ; /* 0x000000170a007986 */
/* 0x0001e8000c101904 */
/*04c0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea8000c1e1900 */
/*04d0*/ LDG.E R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ee2000c1e1900 */
/*04e0*/ IADD3 R21, R15, -0x1, RZ ; /* 0xffffffff0f157810 */
/* 0x000fe40007ffe0ff */
/*04f0*/ IADD3 R7, R13, -0x1, RZ ; /* 0xffffffff0d077810 */
/* 0x000fc60007ffe0ff */
/*0500*/ IMAD.WIDE.U32 R20, R21, R4, c[0x0][0x168] ; /* 0x00005a0015147625 */
/* 0x000fc800078e0004 */
/*0510*/ IMAD.WIDE.U32 R6, R7, R4, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x000fc800078e0004 */
/*0520*/ IMAD.MOV R25, RZ, RZ, -R18 ; /* 0x000000ffff197224 */
/* 0x004fc800078e0a12 */
/*0530*/ IMAD R25, R5, R25, R16 ; /* 0x0000001905197224 */
/* 0x008fca00078e0210 */
/*0540*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0550*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000ea8000c1e1900 */
/*0560*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x001ee2000c1e1900 */
/*0570*/ IMAD.WIDE.U32 R18, R15, R4, c[0x0][0x168] ; /* 0x00005a000f127625 */
/* 0x000fe200078e0004 */
/*0580*/ IADD3 R23, -R20, RZ, RZ ; /* 0x000000ff14177210 */
/* 0x004fca0007ffe1ff */
/*0590*/ IMAD R23, R5, R23, R10 ; /* 0x0000001705177224 */
/* 0x008fe400078e020a */
/*05a0*/ IMAD.WIDE.U32 R10, R13, R4, c[0x0][0x168] ; /* 0x00005a000d0a7625 */
/* 0x000fc600078e0004 */
/*05b0*/ STG.E [R6.64], R23 ; /* 0x0000001706007986 */
/* 0x0001e8000c101904 */
/*05c0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea8000c1e1900 */
/*05d0*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x000ee2000c1e1900 */
/*05e0*/ IADD3 R17, R17, 0x4, RZ ; /* 0x0000000411117810 */
/* 0x000fe40007ffe0ff */
/*05f0*/ IADD3 R13, R13, 0x4, RZ ; /* 0x000000040d0d7810 */
/* 0x000fc40007ffe0ff */
/*0600*/ IADD3 R15, R15, 0x4, RZ ; /* 0x000000040f0f7810 */
/* 0x000fe20007ffe0ff */
/*0610*/ IMAD.IADD R2, R14, 0x1, R17 ; /* 0x000000010e027824 */
/* 0x002fca00078e0211 */
/*0620*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0630*/ IMAD.MOV R22, RZ, RZ, -R18 ; /* 0x000000ffff167224 */
/* 0x004fc800078e0a12 */
/*0640*/ IMAD R3, R5, R22, R16 ; /* 0x0000001605037224 */
/* 0x008fca00078e0210 */
/*0650*/ STG.E [R10.64], R3 ; /* 0x000000030a007986 */
/* 0x0001e6000c101904 */
/*0660*/ @P0 BRA 0x3f0 ; /* 0xfffffd8000000947 */
/* 0x000fea000383ffff */
/*0670*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0680*/ IMAD R9, R0, c[0x0][0x160], R17 ; /* 0x0000580000097a24 */
/* 0x000fe200078e0211 */
/*0690*/ IADD3 R17, R17, -c[0x0][0x160], RZ ; /* 0x8000580011117a10 */
/* 0x000fc60007ffe0ff */
/*06a0*/ IMAD.WIDE.U32 R2, R9, R4, c[0x0][0x168] ; /* 0x00005a0009027625 */
/* 0x001fc800078e0004 */
/*06b0*/ IMAD.WIDE.U32 R6, R17.reuse, R4, c[0x0][0x168] ; /* 0x00005a0011067625 */
/* 0x040fe400078e0004 */
/*06c0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*06d0*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000ee2000c1e1900 */
/*06e0*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fe40007ffe0ff */
/*06f0*/ IADD3 R17, R17, 0x1, RZ ; /* 0x0000000111117810 */
/* 0x000fe40007ffe0ff */
/*0700*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc40003f05270 */
/*0710*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fe40007ffe0ff */
/*0720*/ IADD3 R11, -R2, RZ, RZ ; /* 0x000000ff020b7210 */
/* 0x004fca0007ffe1ff */
/*0730*/ IMAD R11, R5, R11, R0 ; /* 0x0000000b050b7224 */
/* 0x008fca00078e0200 */
/*0740*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0001e2000c101904 */
/*0750*/ @P0 BRA 0x6a0 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*0760*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0770*/ BRA 0x770; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z20rotate90MatrixKernelIiEviPKT_PS0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x160] ; /* 0x0000580000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ ULEA.HI UR4, UR4, UR4, URZ, 0x1 ; /* 0x0000000404047291 */
/* 0x000fe2000f8f083f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e260000002100 */
/*0050*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011404 */
/*0060*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e680000002600 */
/*0070*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e620000002200 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0090*/ LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff027212 */
/* 0x000fe400078e33ff */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fe2000bf06070 */
/*00b0*/ IMAD R9, R9, c[0x0][0x4], R4 ; /* 0x0000010009097a24 */
/* 0x002fe200078e0204 */
/*00c0*/ IADD3 R8, R2, c[0x0][0x160], RZ ; /* 0x0000580002087a10 */
/* 0x000fc80007ffe0ff */
/*00d0*/ ISETP.GE.U32.OR P0, PT, R9, R8, P0 ; /* 0x000000080900720c */
/* 0x000fda0000706470 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ HFMA2.MMA R17, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff117435 */
/* 0x000fe200000001ff */
/*0100*/ IADD3 R5, R8, R0, -R9 ; /* 0x0000000008057210 */
/* 0x000fe20007ffe809 */
/*0110*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0120*/ IMAD R10, R5, c[0x0][0x160], R0 ; /* 0x00005800050a7a24 */
/* 0x000fc800078e0200 */
/*0130*/ IMAD.WIDE.U32 R2, R10, R17, c[0x0][0x168] ; /* 0x00005a000a027625 */
/* 0x000fca00078e0011 */
/*0140*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000ea2000c1e1900 */
/*0150*/ IMAD R0, R0, c[0x0][0x160], R9 ; /* 0x0000580000007a24 */
/* 0x000fe400078e0209 */
/*0160*/ IMAD R12, R8, c[0x0][0x160], R5 ; /* 0x00005800080c7a24 */
/* 0x000fe400078e0205 */
/*0170*/ IMAD.WIDE.U32 R4, R0, R17, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0011 */
/*0180*/ IMAD.WIDE.U32 R6, R12, R17.reuse, c[0x0][0x168] ; /* 0x00005a000c067625 */
/* 0x080fe200078e0011 */
/*0190*/ STG.E [R4.64], R15 ; /* 0x0000000f04007986 */
/* 0x0041ea000c101904 */
/*01a0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea2000c1e1900 */
/*01b0*/ IMAD R14, R9, c[0x0][0x160], R8 ; /* 0x00005800090e7a24 */
/* 0x000fe400078e0208 */
/*01c0*/ IMAD.WIDE.U32 R8, R10, R17, c[0x0][0x170] ; /* 0x00005c000a087625 */
/* 0x000fc800078e0011 */
/*01d0*/ IMAD.WIDE.U32 R10, R14, R17.reuse, c[0x0][0x168] ; /* 0x00005a000e0a7625 */
/* 0x080fe200078e0011 */
/*01e0*/ STG.E [R8.64], R7 ; /* 0x0000000708007986 */
/* 0x004fea000c101904 */
/*01f0*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ea2000c1e1900 */
/*0200*/ IMAD.WIDE.U32 R2, R12, R17, c[0x0][0x170] ; /* 0x00005c000c027625 */
/* 0x000fc800078e0011 */
/*0210*/ IMAD.WIDE.U32 R12, R0, R17.reuse, c[0x0][0x168] ; /* 0x00005a00000c7625 */
/* 0x080fe200078e0011 */
/*0220*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x004fea000c101904 */
/*0230*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IMAD.WIDE.U32 R4, R14, R17, c[0x0][0x170] ; /* 0x00005c000e047625 */
/* 0x001fca00078e0011 */
/*0250*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x004fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15transposeKernelIiEviiPKT_PS0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R5, R5, c[0x0][0x4], R2 ; /* 0x0000010005057a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x164], PT ; /* 0x0000590005007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x160], P0 ; /* 0x0000580000007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R2, R5, c[0x0][0x160], R0 ; /* 0x0000580005027a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE.U32 R2, R2, R4, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0004 */
/*00e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD R5, R0, c[0x0][0x164], R5 ; /* 0x0000590000057a24 */
/* 0x000fc800078e0205 */
/*0100*/ IMAD.WIDE.U32 R4, R5, R4, c[0x0][0x170] ; /* 0x00005c0005047625 */
/* 0x000fca00078e0004 */
/*0110*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11minusKernelIiEviiPKT_S2_PS0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x164], PT ; /* 0x0000590003007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x160], P0 ; /* 0x0000580000007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R3, c[0x0][0x160], R0 ; /* 0x0000580003007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE.U32 R4, R0, R7, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0007 */
/*00e0*/ IMAD.WIDE.U32 R2, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x0c0fe400078e0007 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE.U32 R6, R0, R7, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x000fe200078e0007 */
/*0120*/ IADD3 R9, -R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe1ff */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9addKernelIiEviiPKT_S2_PS0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R3, c[0x0][0x164], PT ; /* 0x0000590003007a0c */
/* 0x000fe20003f06070 */
/*0070*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.U32.OR P0, PT, R0, c[0x0][0x160], P0 ; /* 0x0000580000007a0c */
/* 0x000fda0000706470 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R3, c[0x0][0x160], R0 ; /* 0x0000580003007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE.U32 R4, R0, R7, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0007 */
/*00e0*/ IMAD.WIDE.U32 R2, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x0c0fe400078e0007 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE.U32 R6, R0, R7, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x000fe200078e0007 */
/*0120*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void applyLinearFunction(int *size, const short *x, short *y, short *a, short *b) {
const long ix = threadIdx.x + blockIdx.x * (long)blockDim.x;
if (ix < *size) {
y[ix] = *a + *b * x[ix];
}
} | code for sm_80
Function : _Z19applyLinearFunctionPiPKsPsS2_S2_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0050*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fc600078e00ff */
/*0060*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0070*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e240000002500 */
/*0080*/ IMAD.WIDE.U32 R2, R7, c[0x0][0x0], R2 ; /* 0x0000000007027a25 */
/* 0x001fe200078e0002 */
/*0090*/ SHF.R.S32.HI R7, RZ, 0x1f, R5 ; /* 0x0000001fff077819 */
/* 0x004fc80000011405 */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fc80003f06070 */
/*00b0*/ ISETP.GE.AND.EX P0, PT, R3, R7, PT, P0 ; /* 0x000000070300720c */
/* 0x000fda0003f06300 */
/*00c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00d0*/ SHF.L.U32 R8, R2.reuse, 0x1, RZ ; /* 0x0000000102087819 */
/* 0x040fe400000006ff */
/*00e0*/ SHF.L.U64.HI R9, R2, 0x1, R3 ; /* 0x0000000102097819 */
/* 0x000fe20000010203 */
/*00f0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff027624 */
/* 0x000fe200078e00ff */
/*0100*/ IADD3 R6, P0, R8, c[0x0][0x168], RZ ; /* 0x00005a0008067a10 */
/* 0x000fe20007f1e0ff */
/*0110*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff037624 */
/* 0x000fc600078e00ff */
/*0120*/ IADD3.X R7, R9, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0009077a10 */
/* 0x000fe200007fe4ff */
/*0130*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff057624 */
/* 0x000fe200078e00ff */
/*0140*/ MOV R4, c[0x0][0x178] ; /* 0x00005e0000047a02 */
/* 0x000fe20000000f00 */
/*0150*/ LDG.E.U16 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1500 */
/*0160*/ LDG.E.U16 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee8000c1e1500 */
/*0170*/ LDG.E.U16 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000f22000c1e1500 */
/*0180*/ IADD3 R8, P0, R8, c[0x0][0x170], RZ ; /* 0x00005c0008087a10 */
/* 0x000fc80007f1e0ff */
/*0190*/ IADD3.X R9, R9, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0009097a10 */
/* 0x000fe400007fe4ff */
/*01a0*/ PRMT R11, R2, 0x9910, RZ ; /* 0x00009910020b7816 */
/* 0x004fe400000000ff */
/*01b0*/ PRMT R0, R6, 0x9910, RZ ; /* 0x0000991006007816 */
/* 0x008fca00000000ff */
/*01c0*/ IMAD R11, R11, R0, R4 ; /* 0x000000000b0b7224 */
/* 0x010fca00078e0204 */
/*01d0*/ STG.E.U16 [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x000fe2000c101504 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void applyLinearFunction(int *size, const short *x, short *y, short *a, short *b) {
const long ix = threadIdx.x + blockIdx.x * (long)blockDim.x;
if (ix < *size) {
y[ix] = *a + *b * x[ix];
}
} | .file "tmpxft_0007ba22_00000000-6_applyLinearFunction.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z19applyLinearFunctionPiPKsPsS2_S2_PiPKsPsS2_S2_
.type _Z50__device_stub__Z19applyLinearFunctionPiPKsPsS2_S2_PiPKsPsS2_S2_, @function
_Z50__device_stub__Z19applyLinearFunctionPiPKsPsS2_S2_PiPKsPsS2_S2_:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19applyLinearFunctionPiPKsPsS2_S2_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z19applyLinearFunctionPiPKsPsS2_S2_PiPKsPsS2_S2_, .-_Z50__device_stub__Z19applyLinearFunctionPiPKsPsS2_S2_PiPKsPsS2_S2_
.globl _Z19applyLinearFunctionPiPKsPsS2_S2_
.type _Z19applyLinearFunctionPiPKsPsS2_S2_, @function
_Z19applyLinearFunctionPiPKsPsS2_S2_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z19applyLinearFunctionPiPKsPsS2_S2_PiPKsPsS2_S2_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19applyLinearFunctionPiPKsPsS2_S2_, .-_Z19applyLinearFunctionPiPKsPsS2_S2_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19applyLinearFunctionPiPKsPsS2_S2_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19applyLinearFunctionPiPKsPsS2_S2_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void applyLinearFunction(int *size, const short *x, short *y, short *a, short *b) {
const long ix = threadIdx.x + blockIdx.x * (long)blockDim.x;
if (ix < *size) {
y[ix] = *a + *b * x[ix];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void applyLinearFunction(int *size, const short *x, short *y, short *a, short *b) {
const long ix = threadIdx.x + blockIdx.x * (long)blockDim.x;
if (ix < *size) {
y[ix] = *a + *b * x[ix];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void applyLinearFunction(int *size, const short *x, short *y, short *a, short *b) {
const long ix = threadIdx.x + blockIdx.x * (long)blockDim.x;
if (ix < *size) {
y[ix] = *a + *b * x[ix];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19applyLinearFunctionPiPKsPsS2_S2_
.globl _Z19applyLinearFunctionPiPKsPsS2_S2_
.p2align 8
.type _Z19applyLinearFunctionPiPKsPsS2_S2_,@function
_Z19applyLinearFunctionPiPKsPsS2_S2_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s4, s[0:1], 0x34
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[2:3], 0x0
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s3, s15, v[0:1]
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[2:3]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x8
v_lshlrev_b64 v[2:3], 1, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_load_u16 v0, v1, s[4:5]
global_load_u16 v1, v1, s[6:7]
global_load_u16 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_mad_u16 v4, v4, v1, v0
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
global_store_b16 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19applyLinearFunctionPiPKsPsS2_S2_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19applyLinearFunctionPiPKsPsS2_S2_, .Lfunc_end0-_Z19applyLinearFunctionPiPKsPsS2_S2_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19applyLinearFunctionPiPKsPsS2_S2_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19applyLinearFunctionPiPKsPsS2_S2_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void applyLinearFunction(int *size, const short *x, short *y, short *a, short *b) {
const long ix = threadIdx.x + blockIdx.x * (long)blockDim.x;
if (ix < *size) {
y[ix] = *a + *b * x[ix];
}
} | .text
.file "applyLinearFunction.hip"
.globl _Z34__device_stub__applyLinearFunctionPiPKsPsS2_S2_ # -- Begin function _Z34__device_stub__applyLinearFunctionPiPKsPsS2_S2_
.p2align 4, 0x90
.type _Z34__device_stub__applyLinearFunctionPiPKsPsS2_S2_,@function
_Z34__device_stub__applyLinearFunctionPiPKsPsS2_S2_: # @_Z34__device_stub__applyLinearFunctionPiPKsPsS2_S2_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19applyLinearFunctionPiPKsPsS2_S2_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z34__device_stub__applyLinearFunctionPiPKsPsS2_S2_, .Lfunc_end0-_Z34__device_stub__applyLinearFunctionPiPKsPsS2_S2_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19applyLinearFunctionPiPKsPsS2_S2_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19applyLinearFunctionPiPKsPsS2_S2_,@object # @_Z19applyLinearFunctionPiPKsPsS2_S2_
.section .rodata,"a",@progbits
.globl _Z19applyLinearFunctionPiPKsPsS2_S2_
.p2align 3, 0x0
_Z19applyLinearFunctionPiPKsPsS2_S2_:
.quad _Z34__device_stub__applyLinearFunctionPiPKsPsS2_S2_
.size _Z19applyLinearFunctionPiPKsPsS2_S2_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19applyLinearFunctionPiPKsPsS2_S2_"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__applyLinearFunctionPiPKsPsS2_S2_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19applyLinearFunctionPiPKsPsS2_S2_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19applyLinearFunctionPiPKsPsS2_S2_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0050*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fc600078e00ff */
/*0060*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0070*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e240000002500 */
/*0080*/ IMAD.WIDE.U32 R2, R7, c[0x0][0x0], R2 ; /* 0x0000000007027a25 */
/* 0x001fe200078e0002 */
/*0090*/ SHF.R.S32.HI R7, RZ, 0x1f, R5 ; /* 0x0000001fff077819 */
/* 0x004fc80000011405 */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fc80003f06070 */
/*00b0*/ ISETP.GE.AND.EX P0, PT, R3, R7, PT, P0 ; /* 0x000000070300720c */
/* 0x000fda0003f06300 */
/*00c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00d0*/ SHF.L.U32 R8, R2.reuse, 0x1, RZ ; /* 0x0000000102087819 */
/* 0x040fe400000006ff */
/*00e0*/ SHF.L.U64.HI R9, R2, 0x1, R3 ; /* 0x0000000102097819 */
/* 0x000fe20000010203 */
/*00f0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff027624 */
/* 0x000fe200078e00ff */
/*0100*/ IADD3 R6, P0, R8, c[0x0][0x168], RZ ; /* 0x00005a0008067a10 */
/* 0x000fe20007f1e0ff */
/*0110*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff037624 */
/* 0x000fc600078e00ff */
/*0120*/ IADD3.X R7, R9, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0009077a10 */
/* 0x000fe200007fe4ff */
/*0130*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff057624 */
/* 0x000fe200078e00ff */
/*0140*/ MOV R4, c[0x0][0x178] ; /* 0x00005e0000047a02 */
/* 0x000fe20000000f00 */
/*0150*/ LDG.E.U16 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1500 */
/*0160*/ LDG.E.U16 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee8000c1e1500 */
/*0170*/ LDG.E.U16 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000f22000c1e1500 */
/*0180*/ IADD3 R8, P0, R8, c[0x0][0x170], RZ ; /* 0x00005c0008087a10 */
/* 0x000fc80007f1e0ff */
/*0190*/ IADD3.X R9, R9, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0009097a10 */
/* 0x000fe400007fe4ff */
/*01a0*/ PRMT R11, R2, 0x9910, RZ ; /* 0x00009910020b7816 */
/* 0x004fe400000000ff */
/*01b0*/ PRMT R0, R6, 0x9910, RZ ; /* 0x0000991006007816 */
/* 0x008fca00000000ff */
/*01c0*/ IMAD R11, R11, R0, R4 ; /* 0x000000000b0b7224 */
/* 0x010fca00078e0204 */
/*01d0*/ STG.E.U16 [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x000fe2000c101504 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19applyLinearFunctionPiPKsPsS2_S2_
.globl _Z19applyLinearFunctionPiPKsPsS2_S2_
.p2align 8
.type _Z19applyLinearFunctionPiPKsPsS2_S2_,@function
_Z19applyLinearFunctionPiPKsPsS2_S2_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s4, s[0:1], 0x34
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[2:3], 0x0
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s3, s15, v[0:1]
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[2:3]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x8
v_lshlrev_b64 v[2:3], 1, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
s_clause 0x1
global_load_u16 v0, v1, s[4:5]
global_load_u16 v1, v1, s[6:7]
global_load_u16 v4, v[4:5], off
s_waitcnt vmcnt(0)
v_mad_u16 v4, v4, v1, v0
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
global_store_b16 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19applyLinearFunctionPiPKsPsS2_S2_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19applyLinearFunctionPiPKsPsS2_S2_, .Lfunc_end0-_Z19applyLinearFunctionPiPKsPsS2_S2_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19applyLinearFunctionPiPKsPsS2_S2_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19applyLinearFunctionPiPKsPsS2_S2_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007ba22_00000000-6_applyLinearFunction.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z19applyLinearFunctionPiPKsPsS2_S2_PiPKsPsS2_S2_
.type _Z50__device_stub__Z19applyLinearFunctionPiPKsPsS2_S2_PiPKsPsS2_S2_, @function
_Z50__device_stub__Z19applyLinearFunctionPiPKsPsS2_S2_PiPKsPsS2_S2_:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19applyLinearFunctionPiPKsPsS2_S2_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z50__device_stub__Z19applyLinearFunctionPiPKsPsS2_S2_PiPKsPsS2_S2_, .-_Z50__device_stub__Z19applyLinearFunctionPiPKsPsS2_S2_PiPKsPsS2_S2_
.globl _Z19applyLinearFunctionPiPKsPsS2_S2_
.type _Z19applyLinearFunctionPiPKsPsS2_S2_, @function
_Z19applyLinearFunctionPiPKsPsS2_S2_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z19applyLinearFunctionPiPKsPsS2_S2_PiPKsPsS2_S2_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19applyLinearFunctionPiPKsPsS2_S2_, .-_Z19applyLinearFunctionPiPKsPsS2_S2_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19applyLinearFunctionPiPKsPsS2_S2_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19applyLinearFunctionPiPKsPsS2_S2_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "applyLinearFunction.hip"
.globl _Z34__device_stub__applyLinearFunctionPiPKsPsS2_S2_ # -- Begin function _Z34__device_stub__applyLinearFunctionPiPKsPsS2_S2_
.p2align 4, 0x90
.type _Z34__device_stub__applyLinearFunctionPiPKsPsS2_S2_,@function
_Z34__device_stub__applyLinearFunctionPiPKsPsS2_S2_: # @_Z34__device_stub__applyLinearFunctionPiPKsPsS2_S2_
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19applyLinearFunctionPiPKsPsS2_S2_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z34__device_stub__applyLinearFunctionPiPKsPsS2_S2_, .Lfunc_end0-_Z34__device_stub__applyLinearFunctionPiPKsPsS2_S2_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19applyLinearFunctionPiPKsPsS2_S2_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19applyLinearFunctionPiPKsPsS2_S2_,@object # @_Z19applyLinearFunctionPiPKsPsS2_S2_
.section .rodata,"a",@progbits
.globl _Z19applyLinearFunctionPiPKsPsS2_S2_
.p2align 3, 0x0
_Z19applyLinearFunctionPiPKsPsS2_S2_:
.quad _Z34__device_stub__applyLinearFunctionPiPKsPsS2_S2_
.size _Z19applyLinearFunctionPiPKsPsS2_S2_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19applyLinearFunctionPiPKsPsS2_S2_"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__applyLinearFunctionPiPKsPsS2_S2_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19applyLinearFunctionPiPKsPsS2_S2_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include <stdio.h>
#include <stdlib.h> //srand()
//#include <stdbool.h>
//#define block 514
extern "C" void smooth_global_outer(float* b, float* a, int n, int loop, int BLOCK);
extern "C" void smooth_shared_outer(float* b, float* a, int n, int loop, int BLOCK);
//(2) 裝置核心(global 版).
__global__ void smooth_global(float* b, float* a, int n){
int k = blockIdx.x*blockDim.x+threadIdx.x;
if(k==0){
b[k]=(2*a[0]+a[1])*0.25;
}
else if(k==n-1){
b[k]=(a[n-2]+2*a[n-1])*0.25;
}
else if(k<n){
b[k]=(a[k-1]+2*a[k]+a[k+1])*0.25;
}
}
//(3) 裝置核心(shared 版).
__global__ void smooth_shared(float* b, float* a, int n, int BLOCK){
int base = blockIdx.x*blockDim.x;
int t = threadIdx.x;
//__shared__ float s[BLOCK+2];//宣告共享記憶體.
extern __shared__ float s[];//宣告共享記憶體.
//載入主要資料 s[1]~s[BLOCK]
// s[0] <-- a[base-1] (左邊界)
// s[1] <-- a[base]
// s[2] <-- a[base+1]
// s[3] <-- a[base+2]
// ...
// s[BLOCK] <-- a[base+BLOCK-1]
// s[BLOCK+1] <-- a[base+BLOCK] (右邊界)
if(base+t<n){
s[t+1]=a[base+t];
}
if(t==0){
//左邊界.
if(base==0){
s[0]=0;
}
else{
s[0]=a[base-1]; //載入邊界資料 s[0] & s[BLOCK+1] (只用兩個執行緒處理)
}
}
if(t==32){ //*** 使用獨立的 warp 讓 branch 更快 ***
if(base+BLOCK>=n){ //右邊界.
s[n-base+1]=0;
}
else{
s[BLOCK+1] = a[base+BLOCK];
}
}
__syncthreads(); //同步化 (確保共享記憶體已寫入)
if(base+t<n){
b[base+t]=(s[t]+2*s[t+1]+s[t+2])*0.25; //輸出三點加權平均值
}
};
extern "C" void smooth_global_outer(float* b, float* a, int n, int loop, int BLOCK)
{
dim3 block(BLOCK, 1, 1);
dim3 grid(n/BLOCK+1, 1, 1);
for(int k=0; k<loop; k++)
{
smooth_global<<< grid, block >>>(b, a, n);
}
}
extern "C" void smooth_shared_outer(float* b, float* a, int n, int loop, int BLOCK)
{
dim3 block(BLOCK, 1, 1);
dim3 grid(n/BLOCK+1, 1, 1);
for(int k=0; k<loop; k++){
smooth_shared<<< grid, block, BLOCK+2 >>>(b, a, n, BLOCK);
}
} | code for sm_80
Function : _Z13smooth_sharedPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0xf0 ; /* 0x000000b000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a24 */
/* 0x001fc800078e02ff */
/*0060*/ IMAD.IADD R4, R0, 0x1, R7 ; /* 0x0000000100047824 */
/* 0x002fe200078e0207 */
/*0070*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc80003f25270 */
/*0080*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 BRA 0xe0 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*00b0*/ IMAD.WIDE R2, R4, R3, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0203 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ STS [R7.X4+0x4], R2 ; /* 0x0000040207007388 */
/* 0x0041e40000004800 */
/*00e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*00f0*/ BSSY B0, 0x1b0 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0100*/ @P1 BRA 0x1a0 ; /* 0x0000009000001947 */
/* 0x000fea0003800000 */
/*0110*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f25270 */
/*0120*/ @!P1 BRA 0x190 ; /* 0x0000006000009947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R2, R0, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x001fe20007ffe0ff */
/*0140*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0150*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0203 */
/*0160*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0170*/ STS [RZ], R2 ; /* 0x00000002ff007388 */
/* 0x0041e20000000800 */
/*0180*/ BRA 0x1a0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0190*/ STS [RZ], RZ ; /* 0x000000ffff007388 */
/* 0x000fe40000000800 */
/*01a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.NE.AND P1, PT, R7, 0x20, PT ; /* 0x000000200700780c */
/* 0x000fe20003f25270 */
/*01c0*/ BSSY B0, 0x2b0 ; /* 0x000000e000007945 */
/* 0x000fd80003800000 */
/*01d0*/ @P1 BRA 0x2a0 ; /* 0x000000c000001947 */
/* 0x000fea0003800000 */
/*01e0*/ IADD3 R2, R0, c[0x0][0x174], RZ ; /* 0x00005d0000027a10 */
/* 0x001fc80007ffe0ff */
/*01f0*/ ISETP.GE.AND P1, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f26270 */
/*0200*/ @P1 MOV R3, 0x1 ; /* 0x0000000100031802 */
/* 0x000fc80000000f00 */
/*0210*/ @P1 IADD3 R0, -R0, c[0x0][0x170], R3 ; /* 0x00005c0000001a10 */
/* 0x000fca0007ffe103 */
/*0220*/ @P1 IMAD.SHL.U32 R0, R0, 0x4, RZ ; /* 0x0000000400001824 */
/* 0x000fca00078e00ff */
/*0230*/ @P1 STS [R0], RZ ; /* 0x000000ff00001388 */
/* 0x0001e20000000800 */
/*0240*/ @P1 BRA 0x2a0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0250*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fd400000001ff */
/*0260*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0205 */
/*0270*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0280*/ IMAD R5, R5, c[0x0][0x174], R5 ; /* 0x00005d0005057a24 */
/* 0x000fca00078e0205 */
/*0290*/ STS [R5], R2 ; /* 0x0000000205007388 */
/* 0x0043e40000000800 */
/*02a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02d0*/ LDS R0, [R7.X4] ; /* 0x0000000007007984 */
/* 0x001fe80000004800 */
/*02e0*/ LDS R3, [R7.X4+0x4] ; /* 0x0000040007037984 */
/* 0x000e280000004800 */
/*02f0*/ LDS R5, [R7.X4+0x8] ; /* 0x0000080007057984 */
/* 0x002e620000004800 */
/*0300*/ FFMA R0, R3, 2, R0 ; /* 0x4000000003007823 */
/* 0x001fe20000000000 */
/*0310*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fc60000000f00 */
/*0320*/ FADD R0, R0, R5 ; /* 0x0000000500007221 */
/* 0x002fe40000000000 */
/*0330*/ IMAD.WIDE R2, R4, R3, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fc800078e0203 */
/*0340*/ FMUL R5, R0, 0.25 ; /* 0x3e80000000057820 */
/* 0x000fca0000400000 */
/*0350*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0360*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0370*/ BRA 0x370; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13smooth_globalPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0060*/ @!P0 BRA 0x200 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0070*/ MOV R6, c[0x0][0x170] ; /* 0x00005c0000067a02 */
/* 0x000fe20000000f00 */
/*0080*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fc600000001ff */
/*0090*/ IADD3 R3, R6, -0x1, RZ ; /* 0xffffffff06037810 */
/* 0x000fc80007ffe0ff */
/*00a0*/ ISETP.NE.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x000fc60003f05270 */
/*00b0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00c0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0207 */
/*00d0*/ @!P0 BRA 0x180 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R7, [R4.64+-0x4] ; /* 0xfffffc0404077981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R9, [R4.64+0x4] ; /* 0x0000040404097981 */
/* 0x000ee2000c1e1900 */
/*0130*/ FFMA R0, R0, 2, R7 ; /* 0x4000000000007823 */
/* 0x004fc80000000007 */
/*0140*/ FADD R0, R0, R9 ; /* 0x0000000900007221 */
/* 0x008fc80000000000 */
/*0150*/ FMUL R7, R0, 0.25 ; /* 0x3e80000000077820 */
/* 0x000fca0000400000 */
/*0160*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ IADD3 R6, R6, -0x2, RZ ; /* 0xfffffffe06067810 */
/* 0x000fe20007ffe0ff */
/*0190*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fcc00078e0207 */
/*01b0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea4000c1e1900 */
/*01c0*/ FFMA R0, R4, 2, R7 ; /* 0x4000000004007823 */
/* 0x004fc80000000007 */
/*01d0*/ FMUL R9, R0, 0.25 ; /* 0x3e80000000097820 */
/* 0x000fca0000400000 */
/*01e0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe40000000f00 */
/*0210*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fca0000000f00 */
/*0220*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R5, [R2.64+0x4] ; /* 0x0000040402057981 */
/* 0x000ea2000c1e1900 */
/*0240*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*0250*/ FFMA R0, R0, 2, R5 ; /* 0x4000000000007823 */
/* 0x004fe20000000005 */
/*0260*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fc60000000f00 */
/*0270*/ FMUL R7, R0, 0.25 ; /* 0x3e80000000077820 */
/* 0x000fca0000400000 */
/*0280*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ BRA 0x2a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <stdio.h>
#include <stdlib.h> //srand()
//#include <stdbool.h>
//#define block 514
extern "C" void smooth_global_outer(float* b, float* a, int n, int loop, int BLOCK);
extern "C" void smooth_shared_outer(float* b, float* a, int n, int loop, int BLOCK);
//(2) 裝置核心(global 版).
__global__ void smooth_global(float* b, float* a, int n){
int k = blockIdx.x*blockDim.x+threadIdx.x;
if(k==0){
b[k]=(2*a[0]+a[1])*0.25;
}
else if(k==n-1){
b[k]=(a[n-2]+2*a[n-1])*0.25;
}
else if(k<n){
b[k]=(a[k-1]+2*a[k]+a[k+1])*0.25;
}
}
//(3) 裝置核心(shared 版).
__global__ void smooth_shared(float* b, float* a, int n, int BLOCK){
int base = blockIdx.x*blockDim.x;
int t = threadIdx.x;
//__shared__ float s[BLOCK+2];//宣告共享記憶體.
extern __shared__ float s[];//宣告共享記憶體.
//載入主要資料 s[1]~s[BLOCK]
// s[0] <-- a[base-1] (左邊界)
// s[1] <-- a[base]
// s[2] <-- a[base+1]
// s[3] <-- a[base+2]
// ...
// s[BLOCK] <-- a[base+BLOCK-1]
// s[BLOCK+1] <-- a[base+BLOCK] (右邊界)
if(base+t<n){
s[t+1]=a[base+t];
}
if(t==0){
//左邊界.
if(base==0){
s[0]=0;
}
else{
s[0]=a[base-1]; //載入邊界資料 s[0] & s[BLOCK+1] (只用兩個執行緒處理)
}
}
if(t==32){ //*** 使用獨立的 warp 讓 branch 更快 ***
if(base+BLOCK>=n){ //右邊界.
s[n-base+1]=0;
}
else{
s[BLOCK+1] = a[base+BLOCK];
}
}
__syncthreads(); //同步化 (確保共享記憶體已寫入)
if(base+t<n){
b[base+t]=(s[t]+2*s[t+1]+s[t+2])*0.25; //輸出三點加權平均值
}
};
extern "C" void smooth_global_outer(float* b, float* a, int n, int loop, int BLOCK)
{
dim3 block(BLOCK, 1, 1);
dim3 grid(n/BLOCK+1, 1, 1);
for(int k=0; k<loop; k++)
{
smooth_global<<< grid, block >>>(b, a, n);
}
}
extern "C" void smooth_shared_outer(float* b, float* a, int n, int loop, int BLOCK)
{
dim3 block(BLOCK, 1, 1);
dim3 grid(n/BLOCK+1, 1, 1);
for(int k=0; k<loop; k++){
smooth_shared<<< grid, block, BLOCK+2 >>>(b, a, n, BLOCK);
}
} | .file "tmpxft_000c98ea_00000000-6_test9_cu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z13smooth_globalPfS_iPfS_i
.type _Z36__device_stub__Z13smooth_globalPfS_iPfS_i, @function
_Z36__device_stub__Z13smooth_globalPfS_iPfS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13smooth_globalPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z36__device_stub__Z13smooth_globalPfS_iPfS_i, .-_Z36__device_stub__Z13smooth_globalPfS_iPfS_i
.globl _Z13smooth_globalPfS_i
.type _Z13smooth_globalPfS_i, @function
_Z13smooth_globalPfS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13smooth_globalPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z13smooth_globalPfS_i, .-_Z13smooth_globalPfS_i
.globl smooth_global_outer
.type smooth_global_outer, @function
smooth_global_outer:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movl %edx, %r12d
movl %r8d, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl %edx, %eax
cltd
idivl %r8d
addl $1, %eax
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
testl %ecx, %ecx
jle .L11
movq %rdi, %r13
movq %rsi, %r14
movl %ecx, %ebp
movl $0, %ebx
jmp .L14
.L13:
addl $1, %ebx
cmpl %ebx, %ebp
je .L11
.L14:
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl 28(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movl %r12d, %edx
movq %r14, %rsi
movq %r13, %rdi
call _Z36__device_stub__Z13smooth_globalPfS_iPfS_i
jmp .L13
.L11:
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size smooth_global_outer, .-smooth_global_outer
.globl _Z37__device_stub__Z13smooth_sharedPfS_iiPfS_ii
.type _Z37__device_stub__Z13smooth_sharedPfS_iiPfS_ii, @function
_Z37__device_stub__Z13smooth_sharedPfS_iiPfS_ii:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13smooth_sharedPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z37__device_stub__Z13smooth_sharedPfS_iiPfS_ii, .-_Z37__device_stub__Z13smooth_sharedPfS_iiPfS_ii
.globl _Z13smooth_sharedPfS_ii
.type _Z13smooth_sharedPfS_ii, @function
_Z13smooth_sharedPfS_ii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13smooth_sharedPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z13smooth_sharedPfS_ii, .-_Z13smooth_sharedPfS_ii
.globl smooth_shared_outer
.type smooth_shared_outer, @function
smooth_shared_outer:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movl %edx, %r14d
movl %r8d, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl %edx, %eax
cltd
idivl %r8d
addl $1, %eax
movl %eax, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
testl %ecx, %ecx
jle .L25
movq %rsi, %r15
movl %ecx, %ebp
movl %r8d, %r13d
movl $0, %ebx
leal 2(%r8), %r12d
movslq %r12d, %r12
jmp .L28
.L27:
addl $1, %ebx
cmpl %ebx, %ebp
je .L25
.L28:
movl 32(%rsp), %ecx
movl $0, %r9d
movq %r12, %r8
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L27
movl %r13d, %ecx
movl %r14d, %edx
movq %r15, %rsi
movq 8(%rsp), %rdi
call _Z37__device_stub__Z13smooth_sharedPfS_iiPfS_ii
jmp .L27
.L25:
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size smooth_shared_outer, .-smooth_shared_outer
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13smooth_sharedPfS_ii"
.LC1:
.string "_Z13smooth_globalPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13smooth_sharedPfS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13smooth_globalPfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <stdio.h>
#include <stdlib.h> //srand()
//#include <stdbool.h>
//#define block 514
extern "C" void smooth_global_outer(float* b, float* a, int n, int loop, int BLOCK);
extern "C" void smooth_shared_outer(float* b, float* a, int n, int loop, int BLOCK);
//(2) 裝置核心(global 版).
__global__ void smooth_global(float* b, float* a, int n){
int k = blockIdx.x*blockDim.x+threadIdx.x;
if(k==0){
b[k]=(2*a[0]+a[1])*0.25;
}
else if(k==n-1){
b[k]=(a[n-2]+2*a[n-1])*0.25;
}
else if(k<n){
b[k]=(a[k-1]+2*a[k]+a[k+1])*0.25;
}
}
//(3) 裝置核心(shared 版).
__global__ void smooth_shared(float* b, float* a, int n, int BLOCK){
int base = blockIdx.x*blockDim.x;
int t = threadIdx.x;
//__shared__ float s[BLOCK+2];//宣告共享記憶體.
extern __shared__ float s[];//宣告共享記憶體.
//載入主要資料 s[1]~s[BLOCK]
// s[0] <-- a[base-1] (左邊界)
// s[1] <-- a[base]
// s[2] <-- a[base+1]
// s[3] <-- a[base+2]
// ...
// s[BLOCK] <-- a[base+BLOCK-1]
// s[BLOCK+1] <-- a[base+BLOCK] (右邊界)
if(base+t<n){
s[t+1]=a[base+t];
}
if(t==0){
//左邊界.
if(base==0){
s[0]=0;
}
else{
s[0]=a[base-1]; //載入邊界資料 s[0] & s[BLOCK+1] (只用兩個執行緒處理)
}
}
if(t==32){ //*** 使用獨立的 warp 讓 branch 更快 ***
if(base+BLOCK>=n){ //右邊界.
s[n-base+1]=0;
}
else{
s[BLOCK+1] = a[base+BLOCK];
}
}
__syncthreads(); //同步化 (確保共享記憶體已寫入)
if(base+t<n){
b[base+t]=(s[t]+2*s[t+1]+s[t+2])*0.25; //輸出三點加權平均值
}
};
extern "C" void smooth_global_outer(float* b, float* a, int n, int loop, int BLOCK)
{
dim3 block(BLOCK, 1, 1);
dim3 grid(n/BLOCK+1, 1, 1);
for(int k=0; k<loop; k++)
{
smooth_global<<< grid, block >>>(b, a, n);
}
}
extern "C" void smooth_shared_outer(float* b, float* a, int n, int loop, int BLOCK)
{
dim3 block(BLOCK, 1, 1);
dim3 grid(n/BLOCK+1, 1, 1);
for(int k=0; k<loop; k++){
smooth_shared<<< grid, block, BLOCK+2 >>>(b, a, n, BLOCK);
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h> //srand()
//#include <stdbool.h>
//#define block 514
extern "C" void smooth_global_outer(float* b, float* a, int n, int loop, int BLOCK);
extern "C" void smooth_shared_outer(float* b, float* a, int n, int loop, int BLOCK);
//(2) 裝置核心(global 版).
__global__ void smooth_global(float* b, float* a, int n){
int k = blockIdx.x*blockDim.x+threadIdx.x;
if(k==0){
b[k]=(2*a[0]+a[1])*0.25;
}
else if(k==n-1){
b[k]=(a[n-2]+2*a[n-1])*0.25;
}
else if(k<n){
b[k]=(a[k-1]+2*a[k]+a[k+1])*0.25;
}
}
//(3) 裝置核心(shared 版).
__global__ void smooth_shared(float* b, float* a, int n, int BLOCK){
int base = blockIdx.x*blockDim.x;
int t = threadIdx.x;
//__shared__ float s[BLOCK+2];//宣告共享記憶體.
extern __shared__ float s[];//宣告共享記憶體.
//載入主要資料 s[1]~s[BLOCK]
// s[0] <-- a[base-1] (左邊界)
// s[1] <-- a[base]
// s[2] <-- a[base+1]
// s[3] <-- a[base+2]
// ...
// s[BLOCK] <-- a[base+BLOCK-1]
// s[BLOCK+1] <-- a[base+BLOCK] (右邊界)
if(base+t<n){
s[t+1]=a[base+t];
}
if(t==0){
//左邊界.
if(base==0){
s[0]=0;
}
else{
s[0]=a[base-1]; //載入邊界資料 s[0] & s[BLOCK+1] (只用兩個執行緒處理)
}
}
if(t==32){ //*** 使用獨立的 warp 讓 branch 更快 ***
if(base+BLOCK>=n){ //右邊界.
s[n-base+1]=0;
}
else{
s[BLOCK+1] = a[base+BLOCK];
}
}
__syncthreads(); //同步化 (確保共享記憶體已寫入)
if(base+t<n){
b[base+t]=(s[t]+2*s[t+1]+s[t+2])*0.25; //輸出三點加權平均值
}
};
extern "C" void smooth_global_outer(float* b, float* a, int n, int loop, int BLOCK)
{
dim3 block(BLOCK, 1, 1);
dim3 grid(n/BLOCK+1, 1, 1);
for(int k=0; k<loop; k++)
{
smooth_global<<< grid, block >>>(b, a, n);
}
}
extern "C" void smooth_shared_outer(float* b, float* a, int n, int loop, int BLOCK)
{
dim3 block(BLOCK, 1, 1);
dim3 grid(n/BLOCK+1, 1, 1);
for(int k=0; k<loop; k++){
smooth_shared<<< grid, block, BLOCK+2 >>>(b, a, n, BLOCK);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h> //srand()
//#include <stdbool.h>
//#define block 514
extern "C" void smooth_global_outer(float* b, float* a, int n, int loop, int BLOCK);
extern "C" void smooth_shared_outer(float* b, float* a, int n, int loop, int BLOCK);
//(2) 裝置核心(global 版).
__global__ void smooth_global(float* b, float* a, int n){
int k = blockIdx.x*blockDim.x+threadIdx.x;
if(k==0){
b[k]=(2*a[0]+a[1])*0.25;
}
else if(k==n-1){
b[k]=(a[n-2]+2*a[n-1])*0.25;
}
else if(k<n){
b[k]=(a[k-1]+2*a[k]+a[k+1])*0.25;
}
}
//(3) 裝置核心(shared 版).
__global__ void smooth_shared(float* b, float* a, int n, int BLOCK){
int base = blockIdx.x*blockDim.x;
int t = threadIdx.x;
//__shared__ float s[BLOCK+2];//宣告共享記憶體.
extern __shared__ float s[];//宣告共享記憶體.
//載入主要資料 s[1]~s[BLOCK]
// s[0] <-- a[base-1] (左邊界)
// s[1] <-- a[base]
// s[2] <-- a[base+1]
// s[3] <-- a[base+2]
// ...
// s[BLOCK] <-- a[base+BLOCK-1]
// s[BLOCK+1] <-- a[base+BLOCK] (右邊界)
if(base+t<n){
s[t+1]=a[base+t];
}
if(t==0){
//左邊界.
if(base==0){
s[0]=0;
}
else{
s[0]=a[base-1]; //載入邊界資料 s[0] & s[BLOCK+1] (只用兩個執行緒處理)
}
}
if(t==32){ //*** 使用獨立的 warp 讓 branch 更快 ***
if(base+BLOCK>=n){ //右邊界.
s[n-base+1]=0;
}
else{
s[BLOCK+1] = a[base+BLOCK];
}
}
__syncthreads(); //同步化 (確保共享記憶體已寫入)
if(base+t<n){
b[base+t]=(s[t]+2*s[t+1]+s[t+2])*0.25; //輸出三點加權平均值
}
};
extern "C" void smooth_global_outer(float* b, float* a, int n, int loop, int BLOCK)
{
dim3 block(BLOCK, 1, 1);
dim3 grid(n/BLOCK+1, 1, 1);
for(int k=0; k<loop; k++)
{
smooth_global<<< grid, block >>>(b, a, n);
}
}
extern "C" void smooth_shared_outer(float* b, float* a, int n, int loop, int BLOCK)
{
dim3 block(BLOCK, 1, 1);
dim3 grid(n/BLOCK+1, 1, 1);
for(int k=0; k<loop; k++){
smooth_shared<<< grid, block, BLOCK+2 >>>(b, a, n, BLOCK);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13smooth_globalPfS_i
.globl _Z13smooth_globalPfS_i
.p2align 8
.type _Z13smooth_globalPfS_i,@function
_Z13smooth_globalPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_ne_u32_e32 0, v1
s_xor_b32 s8, exec_lo, s2
s_cbranch_execnz .LBB0_3
s_and_not1_saveexec_b32 s0, s8
s_cbranch_execnz .LBB0_10
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_3:
s_load_b32 s2, s[0:1], 0x10
s_mov_b32 s1, exec_lo
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmpx_ne_u32_e64 s0, v1
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB0_7
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_6
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_clause 0x1
global_load_b32 v4, v[2:3], off offset:-4
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, 2.0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v3, v4
v_mul_f32_e32 v2, 0x3e800000, v2
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
.LBB0_7:
s_and_not1_saveexec_b32 s9, s1
s_cbranch_execz .LBB0_9
s_ashr_i32 s3, s2, 31
v_mov_b32_e32 v0, 0
s_lshl_b64 s[2:3], s[2:3], 2
v_ashrrev_i32_e32 v2, 31, v1
s_add_u32 s2, s6, s2
s_addc_u32 s3, s7, s3
s_ashr_i32 s1, s0, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[0:1], 2
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, s1
s_clause 0x1
global_load_b32 v3, v0, s[2:3] offset:-8
global_load_b32 v0, v0, s[0:1]
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, 2.0, v0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v2, 0x3e800000, v3
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s9
s_and_not1_saveexec_b32 s0, s8
s_cbranch_execz .LBB0_2
.LBB0_10:
v_mov_b32_e32 v2, 0
global_load_b64 v[0:1], v2, s[6:7]
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v1, 2.0, v0
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v0, 0x3e800000, v1
global_store_b32 v2, v0, s[4:5]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13smooth_globalPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13smooth_globalPfS_i, .Lfunc_end0-_Z13smooth_globalPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13smooth_sharedPfS_ii
.globl _Z13smooth_sharedPfS_ii
.p2align 8
.type _Z13smooth_sharedPfS_ii,@function
_Z13smooth_sharedPfS_ii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s2
v_add_nc_u32_e32 v1, s6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s2, s3, v1
v_ashrrev_i32_e32 v2, 31, v1
s_and_saveexec_b32 s7, s2
s_cbranch_execz .LBB1_2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v3, v[3:4], off
v_lshl_add_u32 v4, v0, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v4, v3 offset:4
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s7
s_mov_b32 s8, 0
s_mov_b32 s7, exec_lo
v_cmpx_lt_i32_e32 31, v0
s_xor_b32 s7, exec_lo, s7
v_cmp_eq_u32_e32 vcc_lo, 32, v0
s_and_b32 s8, vcc_lo, exec_lo
s_and_not1_saveexec_b32 s9, s7
s_cbranch_execz .LBB1_10
s_mov_b32 s7, 0
s_mov_b32 s11, s8
s_mov_b32 s10, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_9
s_cmp_eq_u32 s6, 0
s_cbranch_scc1 .LBB1_8
s_ashr_i32 s7, s6, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[12:13], s[6:7], 2
s_add_u32 s7, s4, s12
s_addc_u32 s11, s5, s13
s_add_u32 s12, s7, -4
s_addc_u32 s13, s11, -1
s_load_b32 s7, s[12:13], 0x0
.LBB1_8:
v_cmp_eq_u32_e32 vcc_lo, 32, v0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, s7
s_and_not1_b32 s7, s8, exec_lo
s_and_b32 s11, vcc_lo, exec_lo
ds_store_b32 v3, v4
s_or_b32 s11, s7, s11
.LBB1_9:
s_or_b32 exec_lo, exec_lo, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s7, s8, exec_lo
s_and_b32 s8, s11, exec_lo
s_or_b32 s8, s7, s8
.LBB1_10:
s_or_b32 exec_lo, exec_lo, s9
s_and_saveexec_b32 s7, s8
s_cbranch_execz .LBB1_16
s_load_b32 s10, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_add_i32 s8, s6, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s8, s3
s_cbranch_scc1 .LBB1_13
s_sub_i32 s3, s3, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s6, s3, 1
s_mov_b32 s3, 0
s_cbranch_execz .LBB1_14
s_branch .LBB1_15
.LBB1_13:
.LBB1_14:
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[8:9], 2
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_add_i32 s6, s10, 1
s_load_b32 s3, s[4:5], 0x0
.LBB1_15:
s_lshl_b32 s4, s6, 2
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v4, s3
s_add_i32 s4, s4, 0
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v3, s4
ds_store_b32 v3, v4
.LBB1_16:
s_or_b32 exec_lo, exec_lo, s7
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_18
v_lshl_add_u32 v0, v0, 2, 0
s_load_b64 s[0:1], s[0:1], 0x0
ds_load_2addr_b32 v[3:4], v0 offset1:1
ds_load_b32 v0, v0 offset:8
s_waitcnt lgkmcnt(0)
v_fma_f32 v3, 2.0, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v3, v0, v3
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mul_f32_e32 v2, 0x3e800000, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB1_18:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13smooth_sharedPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13smooth_sharedPfS_ii, .Lfunc_end1-_Z13smooth_sharedPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13smooth_globalPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13smooth_globalPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13smooth_sharedPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13smooth_sharedPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h> //srand()
//#include <stdbool.h>
//#define block 514
extern "C" void smooth_global_outer(float* b, float* a, int n, int loop, int BLOCK);
extern "C" void smooth_shared_outer(float* b, float* a, int n, int loop, int BLOCK);
//(2) 裝置核心(global 版).
__global__ void smooth_global(float* b, float* a, int n){
int k = blockIdx.x*blockDim.x+threadIdx.x;
if(k==0){
b[k]=(2*a[0]+a[1])*0.25;
}
else if(k==n-1){
b[k]=(a[n-2]+2*a[n-1])*0.25;
}
else if(k<n){
b[k]=(a[k-1]+2*a[k]+a[k+1])*0.25;
}
}
//(3) 裝置核心(shared 版).
__global__ void smooth_shared(float* b, float* a, int n, int BLOCK){
int base = blockIdx.x*blockDim.x;
int t = threadIdx.x;
//__shared__ float s[BLOCK+2];//宣告共享記憶體.
extern __shared__ float s[];//宣告共享記憶體.
//載入主要資料 s[1]~s[BLOCK]
// s[0] <-- a[base-1] (左邊界)
// s[1] <-- a[base]
// s[2] <-- a[base+1]
// s[3] <-- a[base+2]
// ...
// s[BLOCK] <-- a[base+BLOCK-1]
// s[BLOCK+1] <-- a[base+BLOCK] (右邊界)
if(base+t<n){
s[t+1]=a[base+t];
}
if(t==0){
//左邊界.
if(base==0){
s[0]=0;
}
else{
s[0]=a[base-1]; //載入邊界資料 s[0] & s[BLOCK+1] (只用兩個執行緒處理)
}
}
if(t==32){ //*** 使用獨立的 warp 讓 branch 更快 ***
if(base+BLOCK>=n){ //右邊界.
s[n-base+1]=0;
}
else{
s[BLOCK+1] = a[base+BLOCK];
}
}
__syncthreads(); //同步化 (確保共享記憶體已寫入)
if(base+t<n){
b[base+t]=(s[t]+2*s[t+1]+s[t+2])*0.25; //輸出三點加權平均值
}
};
extern "C" void smooth_global_outer(float* b, float* a, int n, int loop, int BLOCK)
{
dim3 block(BLOCK, 1, 1);
dim3 grid(n/BLOCK+1, 1, 1);
for(int k=0; k<loop; k++)
{
smooth_global<<< grid, block >>>(b, a, n);
}
}
extern "C" void smooth_shared_outer(float* b, float* a, int n, int loop, int BLOCK)
{
dim3 block(BLOCK, 1, 1);
dim3 grid(n/BLOCK+1, 1, 1);
for(int k=0; k<loop; k++){
smooth_shared<<< grid, block, BLOCK+2 >>>(b, a, n, BLOCK);
}
} | .text
.file "test9_cu.hip"
.globl _Z28__device_stub__smooth_globalPfS_i # -- Begin function _Z28__device_stub__smooth_globalPfS_i
.p2align 4, 0x90
.type _Z28__device_stub__smooth_globalPfS_i,@function
_Z28__device_stub__smooth_globalPfS_i: # @_Z28__device_stub__smooth_globalPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13smooth_globalPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__smooth_globalPfS_i, .Lfunc_end0-_Z28__device_stub__smooth_globalPfS_i
.cfi_endproc
# -- End function
.globl _Z28__device_stub__smooth_sharedPfS_ii # -- Begin function _Z28__device_stub__smooth_sharedPfS_ii
.p2align 4, 0x90
.type _Z28__device_stub__smooth_sharedPfS_ii,@function
_Z28__device_stub__smooth_sharedPfS_ii: # @_Z28__device_stub__smooth_sharedPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13smooth_sharedPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z28__device_stub__smooth_sharedPfS_ii, .Lfunc_end1-_Z28__device_stub__smooth_sharedPfS_ii
.cfi_endproc
# -- End function
.globl smooth_global_outer # -- Begin function smooth_global_outer
.p2align 4, 0x90
.type smooth_global_outer,@function
smooth_global_outer: # @smooth_global_outer
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movl %edx, %eax
cltd
idivl %r8d
testl %ecx, %ecx
jle .LBB2_5
# %bb.1:
movl %ecx, %ebx
movq %rsi, %r14
movq %rdi, %r15
movl %eax, %r12d
movl %r8d, %r13d
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r13
incl %r12d
orq %rax, %r12
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_4: # in Loop: Header=BB2_2 Depth=1
decl %ebx
je .LBB2_5
.LBB2_2: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3: # in Loop: Header=BB2_2 Depth=1
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movl %ebp, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z13smooth_globalPfS_i, %edi
leaq 80(%rsp), %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_4
.LBB2_5: # %._crit_edge
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size smooth_global_outer, .Lfunc_end2-smooth_global_outer
.cfi_endproc
# -- End function
.globl smooth_shared_outer # -- Begin function smooth_shared_outer
.p2align 4, 0x90
.type smooth_shared_outer,@function
smooth_shared_outer: # @smooth_shared_outer
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r14d
movq %rsi, 24(%rsp) # 8-byte Spill
movq %rdi, 16(%rsp) # 8-byte Spill
movl %edx, %eax
cltd
idivl %r8d
testl %ecx, %ecx
jle .LBB3_5
# %bb.1: # %.lr.ph
movl %r8d, %ebx
movl %ecx, %ebp
movl %eax, %r13d
movl %r8d, %r15d
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r15
incl %r13d
orq %rax, %r13
leal 2(%rbx), %eax
movslq %eax, %r12
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_4: # in Loop: Header=BB3_2 Depth=1
decl %ebp
je .LBB3_5
.LBB3_2: # =>This Inner Loop Header: Depth=1
movq %r13, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
movq %r12, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3: # in Loop: Header=BB3_2 Depth=1
movq 16(%rsp), %rax # 8-byte Reload
movq %rax, 88(%rsp)
movq 24(%rsp), %rax # 8-byte Reload
movq %rax, 80(%rsp)
movl %r14d, 12(%rsp)
movl %ebx, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z13smooth_sharedPfS_ii, %edi
leaq 96(%rsp), %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_4
.LBB3_5: # %._crit_edge
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size smooth_shared_outer, .Lfunc_end3-smooth_shared_outer
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13smooth_globalPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13smooth_sharedPfS_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13smooth_globalPfS_i,@object # @_Z13smooth_globalPfS_i
.section .rodata,"a",@progbits
.globl _Z13smooth_globalPfS_i
.p2align 3, 0x0
_Z13smooth_globalPfS_i:
.quad _Z28__device_stub__smooth_globalPfS_i
.size _Z13smooth_globalPfS_i, 8
.type _Z13smooth_sharedPfS_ii,@object # @_Z13smooth_sharedPfS_ii
.globl _Z13smooth_sharedPfS_ii
.p2align 3, 0x0
_Z13smooth_sharedPfS_ii:
.quad _Z28__device_stub__smooth_sharedPfS_ii
.size _Z13smooth_sharedPfS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13smooth_globalPfS_i"
.size .L__unnamed_1, 23
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13smooth_sharedPfS_ii"
.size .L__unnamed_2, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__smooth_globalPfS_i
.addrsig_sym _Z28__device_stub__smooth_sharedPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13smooth_globalPfS_i
.addrsig_sym _Z13smooth_sharedPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13smooth_sharedPfS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0xf0 ; /* 0x000000b000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a24 */
/* 0x001fc800078e02ff */
/*0060*/ IMAD.IADD R4, R0, 0x1, R7 ; /* 0x0000000100047824 */
/* 0x002fe200078e0207 */
/*0070*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fc80003f25270 */
/*0080*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 BRA 0xe0 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*00b0*/ IMAD.WIDE R2, R4, R3, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0203 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ STS [R7.X4+0x4], R2 ; /* 0x0000040207007388 */
/* 0x0041e40000004800 */
/*00e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*00f0*/ BSSY B0, 0x1b0 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0100*/ @P1 BRA 0x1a0 ; /* 0x0000009000001947 */
/* 0x000fea0003800000 */
/*0110*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f25270 */
/*0120*/ @!P1 BRA 0x190 ; /* 0x0000006000009947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R2, R0, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x001fe20007ffe0ff */
/*0140*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0150*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0203 */
/*0160*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0170*/ STS [RZ], R2 ; /* 0x00000002ff007388 */
/* 0x0041e20000000800 */
/*0180*/ BRA 0x1a0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0190*/ STS [RZ], RZ ; /* 0x000000ffff007388 */
/* 0x000fe40000000800 */
/*01a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.NE.AND P1, PT, R7, 0x20, PT ; /* 0x000000200700780c */
/* 0x000fe20003f25270 */
/*01c0*/ BSSY B0, 0x2b0 ; /* 0x000000e000007945 */
/* 0x000fd80003800000 */
/*01d0*/ @P1 BRA 0x2a0 ; /* 0x000000c000001947 */
/* 0x000fea0003800000 */
/*01e0*/ IADD3 R2, R0, c[0x0][0x174], RZ ; /* 0x00005d0000027a10 */
/* 0x001fc80007ffe0ff */
/*01f0*/ ISETP.GE.AND P1, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f26270 */
/*0200*/ @P1 MOV R3, 0x1 ; /* 0x0000000100031802 */
/* 0x000fc80000000f00 */
/*0210*/ @P1 IADD3 R0, -R0, c[0x0][0x170], R3 ; /* 0x00005c0000001a10 */
/* 0x000fca0007ffe103 */
/*0220*/ @P1 IMAD.SHL.U32 R0, R0, 0x4, RZ ; /* 0x0000000400001824 */
/* 0x000fca00078e00ff */
/*0230*/ @P1 STS [R0], RZ ; /* 0x000000ff00001388 */
/* 0x0001e20000000800 */
/*0240*/ @P1 BRA 0x2a0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0250*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fd400000001ff */
/*0260*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0205 */
/*0270*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0280*/ IMAD R5, R5, c[0x0][0x174], R5 ; /* 0x00005d0005057a24 */
/* 0x000fca00078e0205 */
/*0290*/ STS [R5], R2 ; /* 0x0000000205007388 */
/* 0x0043e40000000800 */
/*02a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02d0*/ LDS R0, [R7.X4] ; /* 0x0000000007007984 */
/* 0x001fe80000004800 */
/*02e0*/ LDS R3, [R7.X4+0x4] ; /* 0x0000040007037984 */
/* 0x000e280000004800 */
/*02f0*/ LDS R5, [R7.X4+0x8] ; /* 0x0000080007057984 */
/* 0x002e620000004800 */
/*0300*/ FFMA R0, R3, 2, R0 ; /* 0x4000000003007823 */
/* 0x001fe20000000000 */
/*0310*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fc60000000f00 */
/*0320*/ FADD R0, R0, R5 ; /* 0x0000000500007221 */
/* 0x002fe40000000000 */
/*0330*/ IMAD.WIDE R2, R4, R3, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fc800078e0203 */
/*0340*/ FMUL R5, R0, 0.25 ; /* 0x3e80000000057820 */
/* 0x000fca0000400000 */
/*0350*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0360*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0370*/ BRA 0x370; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13smooth_globalPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0060*/ @!P0 BRA 0x200 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0070*/ MOV R6, c[0x0][0x170] ; /* 0x00005c0000067a02 */
/* 0x000fe20000000f00 */
/*0080*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fc600000001ff */
/*0090*/ IADD3 R3, R6, -0x1, RZ ; /* 0xffffffff06037810 */
/* 0x000fc80007ffe0ff */
/*00a0*/ ISETP.NE.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x000fc60003f05270 */
/*00b0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00c0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0207 */
/*00d0*/ @!P0 BRA 0x180 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R7, [R4.64+-0x4] ; /* 0xfffffc0404077981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R9, [R4.64+0x4] ; /* 0x0000040404097981 */
/* 0x000ee2000c1e1900 */
/*0130*/ FFMA R0, R0, 2, R7 ; /* 0x4000000000007823 */
/* 0x004fc80000000007 */
/*0140*/ FADD R0, R0, R9 ; /* 0x0000000900007221 */
/* 0x008fc80000000000 */
/*0150*/ FMUL R7, R0, 0.25 ; /* 0x3e80000000077820 */
/* 0x000fca0000400000 */
/*0160*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ IADD3 R6, R6, -0x2, RZ ; /* 0xfffffffe06067810 */
/* 0x000fe20007ffe0ff */
/*0190*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fcc00078e0207 */
/*01b0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea4000c1e1900 */
/*01c0*/ FFMA R0, R4, 2, R7 ; /* 0x4000000004007823 */
/* 0x004fc80000000007 */
/*01d0*/ FMUL R9, R0, 0.25 ; /* 0x3e80000000097820 */
/* 0x000fca0000400000 */
/*01e0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe40000000f00 */
/*0210*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fca0000000f00 */
/*0220*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R5, [R2.64+0x4] ; /* 0x0000040402057981 */
/* 0x000ea2000c1e1900 */
/*0240*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*0250*/ FFMA R0, R0, 2, R5 ; /* 0x4000000000007823 */
/* 0x004fe20000000005 */
/*0260*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fc60000000f00 */
/*0270*/ FMUL R7, R0, 0.25 ; /* 0x3e80000000077820 */
/* 0x000fca0000400000 */
/*0280*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ BRA 0x2a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13smooth_globalPfS_i
.globl _Z13smooth_globalPfS_i
.p2align 8
.type _Z13smooth_globalPfS_i,@function
_Z13smooth_globalPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_ne_u32_e32 0, v1
s_xor_b32 s8, exec_lo, s2
s_cbranch_execnz .LBB0_3
s_and_not1_saveexec_b32 s0, s8
s_cbranch_execnz .LBB0_10
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_3:
s_load_b32 s2, s[0:1], 0x10
s_mov_b32 s1, exec_lo
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmpx_ne_u32_e64 s0, v1
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB0_7
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_6
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_clause 0x1
global_load_b32 v4, v[2:3], off offset:-4
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, 2.0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v3, v4
v_mul_f32_e32 v2, 0x3e800000, v2
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s3
.LBB0_7:
s_and_not1_saveexec_b32 s9, s1
s_cbranch_execz .LBB0_9
s_ashr_i32 s3, s2, 31
v_mov_b32_e32 v0, 0
s_lshl_b64 s[2:3], s[2:3], 2
v_ashrrev_i32_e32 v2, 31, v1
s_add_u32 s2, s6, s2
s_addc_u32 s3, s7, s3
s_ashr_i32 s1, s0, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[0:1], 2
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, s1
s_clause 0x1
global_load_b32 v3, v0, s[2:3] offset:-8
global_load_b32 v0, v0, s[0:1]
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, 2.0, v0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v2, 0x3e800000, v3
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s9
s_and_not1_saveexec_b32 s0, s8
s_cbranch_execz .LBB0_2
.LBB0_10:
v_mov_b32_e32 v2, 0
global_load_b64 v[0:1], v2, s[6:7]
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v1, 2.0, v0
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v0, 0x3e800000, v1
global_store_b32 v2, v0, s[4:5]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13smooth_globalPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13smooth_globalPfS_i, .Lfunc_end0-_Z13smooth_globalPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13smooth_sharedPfS_ii
.globl _Z13smooth_sharedPfS_ii
.p2align 8
.type _Z13smooth_sharedPfS_ii,@function
_Z13smooth_sharedPfS_ii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s2
v_add_nc_u32_e32 v1, s6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s2, s3, v1
v_ashrrev_i32_e32 v2, 31, v1
s_and_saveexec_b32 s7, s2
s_cbranch_execz .LBB1_2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v3, v[3:4], off
v_lshl_add_u32 v4, v0, 2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v4, v3 offset:4
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s7
s_mov_b32 s8, 0
s_mov_b32 s7, exec_lo
v_cmpx_lt_i32_e32 31, v0
s_xor_b32 s7, exec_lo, s7
v_cmp_eq_u32_e32 vcc_lo, 32, v0
s_and_b32 s8, vcc_lo, exec_lo
s_and_not1_saveexec_b32 s9, s7
s_cbranch_execz .LBB1_10
s_mov_b32 s7, 0
s_mov_b32 s11, s8
s_mov_b32 s10, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_9
s_cmp_eq_u32 s6, 0
s_cbranch_scc1 .LBB1_8
s_ashr_i32 s7, s6, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[12:13], s[6:7], 2
s_add_u32 s7, s4, s12
s_addc_u32 s11, s5, s13
s_add_u32 s12, s7, -4
s_addc_u32 s13, s11, -1
s_load_b32 s7, s[12:13], 0x0
.LBB1_8:
v_cmp_eq_u32_e32 vcc_lo, 32, v0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, s7
s_and_not1_b32 s7, s8, exec_lo
s_and_b32 s11, vcc_lo, exec_lo
ds_store_b32 v3, v4
s_or_b32 s11, s7, s11
.LBB1_9:
s_or_b32 exec_lo, exec_lo, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s7, s8, exec_lo
s_and_b32 s8, s11, exec_lo
s_or_b32 s8, s7, s8
.LBB1_10:
s_or_b32 exec_lo, exec_lo, s9
s_and_saveexec_b32 s7, s8
s_cbranch_execz .LBB1_16
s_load_b32 s10, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_add_i32 s8, s6, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s8, s3
s_cbranch_scc1 .LBB1_13
s_sub_i32 s3, s3, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s6, s3, 1
s_mov_b32 s3, 0
s_cbranch_execz .LBB1_14
s_branch .LBB1_15
.LBB1_13:
.LBB1_14:
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[8:9], 2
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_add_i32 s6, s10, 1
s_load_b32 s3, s[4:5], 0x0
.LBB1_15:
s_lshl_b32 s4, s6, 2
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v4, s3
s_add_i32 s4, s4, 0
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v3, s4
ds_store_b32 v3, v4
.LBB1_16:
s_or_b32 exec_lo, exec_lo, s7
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_18
v_lshl_add_u32 v0, v0, 2, 0
s_load_b64 s[0:1], s[0:1], 0x0
ds_load_2addr_b32 v[3:4], v0 offset1:1
ds_load_b32 v0, v0 offset:8
s_waitcnt lgkmcnt(0)
v_fma_f32 v3, 2.0, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v3, v0, v3
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mul_f32_e32 v2, 0x3e800000, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB1_18:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13smooth_sharedPfS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13smooth_sharedPfS_ii, .Lfunc_end1-_Z13smooth_sharedPfS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13smooth_globalPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13smooth_globalPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13smooth_sharedPfS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13smooth_sharedPfS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c98ea_00000000-6_test9_cu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z13smooth_globalPfS_iPfS_i
.type _Z36__device_stub__Z13smooth_globalPfS_iPfS_i, @function
_Z36__device_stub__Z13smooth_globalPfS_iPfS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13smooth_globalPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z36__device_stub__Z13smooth_globalPfS_iPfS_i, .-_Z36__device_stub__Z13smooth_globalPfS_iPfS_i
.globl _Z13smooth_globalPfS_i
.type _Z13smooth_globalPfS_i, @function
_Z13smooth_globalPfS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13smooth_globalPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z13smooth_globalPfS_i, .-_Z13smooth_globalPfS_i
.globl smooth_global_outer
.type smooth_global_outer, @function
smooth_global_outer:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movl %edx, %r12d
movl %r8d, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl %edx, %eax
cltd
idivl %r8d
addl $1, %eax
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
testl %ecx, %ecx
jle .L11
movq %rdi, %r13
movq %rsi, %r14
movl %ecx, %ebp
movl $0, %ebx
jmp .L14
.L13:
addl $1, %ebx
cmpl %ebx, %ebp
je .L11
.L14:
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl 28(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movl %r12d, %edx
movq %r14, %rsi
movq %r13, %rdi
call _Z36__device_stub__Z13smooth_globalPfS_iPfS_i
jmp .L13
.L11:
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size smooth_global_outer, .-smooth_global_outer
.globl _Z37__device_stub__Z13smooth_sharedPfS_iiPfS_ii
.type _Z37__device_stub__Z13smooth_sharedPfS_iiPfS_ii, @function
_Z37__device_stub__Z13smooth_sharedPfS_iiPfS_ii:
.LFB2085:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13smooth_sharedPfS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z37__device_stub__Z13smooth_sharedPfS_iiPfS_ii, .-_Z37__device_stub__Z13smooth_sharedPfS_iiPfS_ii
.globl _Z13smooth_sharedPfS_ii
.type _Z13smooth_sharedPfS_ii, @function
_Z13smooth_sharedPfS_ii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13smooth_sharedPfS_iiPfS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z13smooth_sharedPfS_ii, .-_Z13smooth_sharedPfS_ii
.globl smooth_shared_outer
.type smooth_shared_outer, @function
smooth_shared_outer:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movl %edx, %r14d
movl %r8d, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl %edx, %eax
cltd
idivl %r8d
addl $1, %eax
movl %eax, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
testl %ecx, %ecx
jle .L25
movq %rsi, %r15
movl %ecx, %ebp
movl %r8d, %r13d
movl $0, %ebx
leal 2(%r8), %r12d
movslq %r12d, %r12
jmp .L28
.L27:
addl $1, %ebx
cmpl %ebx, %ebp
je .L25
.L28:
movl 32(%rsp), %ecx
movl $0, %r9d
movq %r12, %r8
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L27
movl %r13d, %ecx
movl %r14d, %edx
movq %r15, %rsi
movq 8(%rsp), %rdi
call _Z37__device_stub__Z13smooth_sharedPfS_iiPfS_ii
jmp .L27
.L25:
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size smooth_shared_outer, .-smooth_shared_outer
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13smooth_sharedPfS_ii"
.LC1:
.string "_Z13smooth_globalPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13smooth_sharedPfS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13smooth_globalPfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test9_cu.hip"
.globl _Z28__device_stub__smooth_globalPfS_i # -- Begin function _Z28__device_stub__smooth_globalPfS_i
.p2align 4, 0x90
.type _Z28__device_stub__smooth_globalPfS_i,@function
_Z28__device_stub__smooth_globalPfS_i: # @_Z28__device_stub__smooth_globalPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13smooth_globalPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__smooth_globalPfS_i, .Lfunc_end0-_Z28__device_stub__smooth_globalPfS_i
.cfi_endproc
# -- End function
.globl _Z28__device_stub__smooth_sharedPfS_ii # -- Begin function _Z28__device_stub__smooth_sharedPfS_ii
.p2align 4, 0x90
.type _Z28__device_stub__smooth_sharedPfS_ii,@function
_Z28__device_stub__smooth_sharedPfS_ii: # @_Z28__device_stub__smooth_sharedPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13smooth_sharedPfS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z28__device_stub__smooth_sharedPfS_ii, .Lfunc_end1-_Z28__device_stub__smooth_sharedPfS_ii
.cfi_endproc
# -- End function
.globl smooth_global_outer # -- Begin function smooth_global_outer
.p2align 4, 0x90
.type smooth_global_outer,@function
smooth_global_outer: # @smooth_global_outer
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movl %edx, %eax
cltd
idivl %r8d
testl %ecx, %ecx
jle .LBB2_5
# %bb.1:
movl %ecx, %ebx
movq %rsi, %r14
movq %rdi, %r15
movl %eax, %r12d
movl %r8d, %r13d
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r13
incl %r12d
orq %rax, %r12
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_4: # in Loop: Header=BB2_2 Depth=1
decl %ebx
je .LBB2_5
.LBB2_2: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3: # in Loop: Header=BB2_2 Depth=1
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movl %ebp, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z13smooth_globalPfS_i, %edi
leaq 80(%rsp), %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_4
.LBB2_5: # %._crit_edge
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size smooth_global_outer, .Lfunc_end2-smooth_global_outer
.cfi_endproc
# -- End function
.globl smooth_shared_outer # -- Begin function smooth_shared_outer
.p2align 4, 0x90
.type smooth_shared_outer,@function
smooth_shared_outer: # @smooth_shared_outer
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %r14d
movq %rsi, 24(%rsp) # 8-byte Spill
movq %rdi, 16(%rsp) # 8-byte Spill
movl %edx, %eax
cltd
idivl %r8d
testl %ecx, %ecx
jle .LBB3_5
# %bb.1: # %.lr.ph
movl %r8d, %ebx
movl %ecx, %ebp
movl %eax, %r13d
movl %r8d, %r15d
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r15
incl %r13d
orq %rax, %r13
leal 2(%rbx), %eax
movslq %eax, %r12
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_4: # in Loop: Header=BB3_2 Depth=1
decl %ebp
je .LBB3_5
.LBB3_2: # =>This Inner Loop Header: Depth=1
movq %r13, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
movq %r12, %r8
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3: # in Loop: Header=BB3_2 Depth=1
movq 16(%rsp), %rax # 8-byte Reload
movq %rax, 88(%rsp)
movq 24(%rsp), %rax # 8-byte Reload
movq %rax, 80(%rsp)
movl %r14d, 12(%rsp)
movl %ebx, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z13smooth_sharedPfS_ii, %edi
leaq 96(%rsp), %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_4
.LBB3_5: # %._crit_edge
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size smooth_shared_outer, .Lfunc_end3-smooth_shared_outer
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13smooth_globalPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13smooth_sharedPfS_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13smooth_globalPfS_i,@object # @_Z13smooth_globalPfS_i
.section .rodata,"a",@progbits
.globl _Z13smooth_globalPfS_i
.p2align 3, 0x0
_Z13smooth_globalPfS_i:
.quad _Z28__device_stub__smooth_globalPfS_i
.size _Z13smooth_globalPfS_i, 8
.type _Z13smooth_sharedPfS_ii,@object # @_Z13smooth_sharedPfS_ii
.globl _Z13smooth_sharedPfS_ii
.p2align 3, 0x0
_Z13smooth_sharedPfS_ii:
.quad _Z28__device_stub__smooth_sharedPfS_ii
.size _Z13smooth_sharedPfS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13smooth_globalPfS_i"
.size .L__unnamed_1, 23
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13smooth_sharedPfS_ii"
.size .L__unnamed_2, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__smooth_globalPfS_i
.addrsig_sym _Z28__device_stub__smooth_sharedPfS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13smooth_globalPfS_i
.addrsig_sym _Z13smooth_sharedPfS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void UpdateScalars(float *WHAT , float *WITH , float AMOUNT , float *MASS) {
int idx = threadIdx.x + blockIdx.x * blockDim.x; // this defines the element
WHAT[idx] += AMOUNT*WITH[idx]/MASS[idx];
} | code for sm_80
Function : _Z13UpdateScalarsPfS_fS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc800078e0200 */
/*0060*/ IMAD.WIDE R4, R0, R7, c[0x0][0x178] ; /* 0x00005e0000047625 */
/* 0x000fcc00078e0207 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R2, R0, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0207 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ee2000c1e1900 */
/*00a0*/ BSSY B0, 0x170 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*00b0*/ MUFU.RCP R8, R5 ; /* 0x0000000500087308 */
/* 0x004e220000001000 */
/*00c0*/ FMUL R6, R2, c[0x0][0x170] ; /* 0x00005c0002067a20 */
/* 0x008fce0000400000 */
/*00d0*/ FCHK P0, R6, R5 ; /* 0x0000000506007302 */
/* 0x000e620000000000 */
/*00e0*/ FFMA R7, -R5, R8, 1 ; /* 0x3f80000005077423 */
/* 0x001fc80000000108 */
/*00f0*/ FFMA R7, R8, R7, R8 ; /* 0x0000000708077223 */
/* 0x000fc80000000008 */
/*0100*/ FFMA R8, R6, R7, RZ ; /* 0x0000000706087223 */
/* 0x000fc800000000ff */
/*0110*/ FFMA R9, -R5, R8, R6 ; /* 0x0000000805097223 */
/* 0x000fc80000000106 */
/*0120*/ FFMA R7, R7, R9, R8 ; /* 0x0000000907077223 */
/* 0x000fe20000000008 */
/*0130*/ @!P0 BRA 0x160 ; /* 0x0000002000008947 */
/* 0x002fea0003800000 */
/*0140*/ MOV R2, 0x160 ; /* 0x0000016000027802 */
/* 0x000fe40000000f00 */
/*0150*/ CALL.REL.NOINC 0x1d0 ; /* 0x0000007000007944 */
/* 0x000fea0003c00000 */
/*0160*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0180*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0190*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*01a0*/ FADD R7, R0, R7 ; /* 0x0000000700077221 */
/* 0x004fca0000000000 */
/*01b0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ SHF.R.U32.HI R4, RZ, 0x17, R5.reuse ; /* 0x00000017ff047819 */
/* 0x100fe20000011605 */
/*01e0*/ BSSY B1, 0x830 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*01f0*/ SHF.R.U32.HI R3, RZ, 0x17, R6.reuse ; /* 0x00000017ff037819 */
/* 0x100fe20000011606 */
/*0200*/ IMAD.MOV.U32 R7, RZ, RZ, R6 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0006 */
/*0210*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fe200078ec0ff */
/*0220*/ IMAD.MOV.U32 R8, RZ, RZ, R5 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0005 */
/*0230*/ LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03037812 */
/* 0x000fe400078ec0ff */
/*0240*/ IADD3 R11, R4, -0x1, RZ ; /* 0xffffffff040b7810 */
/* 0x000fe40007ffe0ff */
/*0250*/ IADD3 R10, R3, -0x1, RZ ; /* 0xffffffff030a7810 */
/* 0x000fc40007ffe0ff */
/*0260*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fc80003f04070 */
/*0270*/ ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; /* 0x000000fd0a00780c */
/* 0x000fda0000704470 */
/*0280*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0290*/ @!P0 BRA 0x410 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*02a0*/ FSETP.GTU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fe40003f1c200 */
/*02b0*/ FSETP.GTU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fc80003f3c200 */
/*02c0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*02d0*/ @P0 BRA 0x810 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*02e0*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c807 */
/*02f0*/ @!P0 BRA 0x7f0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0300*/ FSETP.NEU.FTZ.AND P2, PT, |R6|.reuse, +INF , PT ; /* 0x7f8000000600780b */
/* 0x040fe40003f5d200 */
/*0310*/ FSETP.NEU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fe40003f3d200 */
/*0320*/ FSETP.NEU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fd60003f1d200 */
/*0330*/ @!P1 BRA !P2, 0x7f0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0340*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*0350*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0360*/ @P1 BRA 0x7d0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0370*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*0380*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0390*/ @P0 BRA 0x7a0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*03a0*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f06270 */
/*03b0*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f26270 */
/*03c0*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*03d0*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*03e0*/ @!P0 FFMA R7, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f80000006078823 */
/* 0x000fe400000000ff */
/*03f0*/ @!P1 FFMA R8, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005089823 */
/* 0x000fe200000000ff */
/*0400*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*0410*/ LEA R5, R4, 0xc0800000, 0x17 ; /* 0xc080000004057811 */
/* 0x000fe200078eb8ff */
/*0420*/ BSSY B2, 0x790 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*0430*/ IMAD.IADD R8, R8, 0x1, -R5 ; /* 0x0000000108087824 */
/* 0x000fe200078e0a05 */
/*0440*/ IADD3 R5, R3, -0x7f, RZ ; /* 0xffffff8103057810 */
/* 0x000fc60007ffe0ff */
/*0450*/ MUFU.RCP R6, R8 ; /* 0x0000000800067308 */
/* 0x000e220000001000 */
/*0460*/ FADD.FTZ R10, -R8, -RZ ; /* 0x800000ff080a7221 */
/* 0x000fe40000010100 */
/*0470*/ IMAD R7, R5, -0x800000, R7 ; /* 0xff80000005077824 */
/* 0x000fe400078e0207 */
/*0480*/ FFMA R3, R6, R10, 1 ; /* 0x3f80000006037423 */
/* 0x001fc8000000000a */
/*0490*/ FFMA R12, R6, R3, R6 ; /* 0x00000003060c7223 */
/* 0x000fc80000000006 */
/*04a0*/ FFMA R3, R7, R12, RZ ; /* 0x0000000c07037223 */
/* 0x000fc800000000ff */
/*04b0*/ FFMA R6, R10, R3, R7 ; /* 0x000000030a067223 */
/* 0x000fc80000000007 */
/*04c0*/ FFMA R11, R12, R6, R3 ; /* 0x000000060c0b7223 */
/* 0x000fe20000000003 */
/*04d0*/ IADD3 R6, R5, 0x7f, -R4 ; /* 0x0000007f05067810 */
/* 0x000fc60007ffe804 */
/*04e0*/ FFMA R7, R10, R11, R7 ; /* 0x0000000b0a077223 */
/* 0x000fe40000000007 */
/*04f0*/ IMAD.IADD R6, R6, 0x1, R9 ; /* 0x0000000106067824 */
/* 0x000fe400078e0209 */
/*0500*/ FFMA R3, R12, R7, R11 ; /* 0x000000070c037223 */
/* 0x000fca000000000b */
/*0510*/ SHF.R.U32.HI R4, RZ, 0x17, R3 ; /* 0x00000017ff047819 */
/* 0x000fc80000011603 */
/*0520*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*0530*/ IMAD.IADD R8, R4, 0x1, R6 ; /* 0x0000000104087824 */
/* 0x000fca00078e0206 */
/*0540*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fc80007ffe0ff */
/*0550*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*0560*/ @!P0 BRA 0x770 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0570*/ ISETP.GT.AND P0, PT, R8, 0xfe, PT ; /* 0x000000fe0800780c */
/* 0x000fda0003f04270 */
/*0580*/ @P0 BRA 0x740 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0590*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*05a0*/ @P0 BRA 0x780 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*05b0*/ ISETP.GE.AND P0, PT, R8, -0x18, PT ; /* 0xffffffe80800780c */
/* 0x000fe40003f06270 */
/*05c0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*05d0*/ @!P0 BRA 0x780 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*05e0*/ FFMA.RZ R4, R12, R7.reuse, R11.reuse ; /* 0x000000070c047223 */
/* 0x180fe2000000c00b */
/*05f0*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f45270 */
/*0600*/ FFMA.RM R5, R12, R7.reuse, R11.reuse ; /* 0x000000070c057223 */
/* 0x180fe2000000400b */
/*0610*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f25270 */
/*0620*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */
/* 0x000fe200078ec0ff */
/*0630*/ FFMA.RP R4, R12, R7, R11 ; /* 0x000000070c047223 */
/* 0x000fe2000000800b */
/*0640*/ IADD3 R7, R8, 0x20, RZ ; /* 0x0000002008077810 */
/* 0x000fe20007ffe0ff */
/*0650*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0a08 */
/*0660*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe400078efcff */
/*0670*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fc40003f1d000 */
/*0680*/ SHF.L.U32 R7, R6, R7, RZ ; /* 0x0000000706077219 */
/* 0x000fe400000006ff */
/*0690*/ SEL R5, R8, RZ, P2 ; /* 0x000000ff08057207 */
/* 0x000fe40001000000 */
/*06a0*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*06b0*/ SHF.R.U32.HI R5, RZ, R5, R6 ; /* 0x00000005ff057219 */
/* 0x000fe40000011606 */
/*06c0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*06d0*/ SHF.R.U32.HI R7, RZ, 0x1, R5 ; /* 0x00000001ff077819 */
/* 0x000fc40000011605 */
/*06e0*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*06f0*/ LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef807 */
/*0700*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */
/* 0x000fca00078ec0ff */
/*0710*/ IMAD.IADD R4, R7, 0x1, R4 ; /* 0x0000000107047824 */
/* 0x000fca00078e0204 */
/*0720*/ LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304037212 */
/* 0x000fe200078efcff */
/*0730*/ BRA 0x780 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0740*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0750*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0760*/ BRA 0x780 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0770*/ IMAD R3, R6, 0x800000, R3 ; /* 0x0080000006037824 */
/* 0x000fe400078e0203 */
/*0780*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0790*/ BRA 0x820 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*07a0*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fc800078e4807 */
/*07b0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*07c0*/ BRA 0x820 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*07d0*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fe200078e4807 */
/*07e0*/ BRA 0x820 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*07f0*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0800*/ BRA 0x820 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0810*/ FADD.FTZ R3, R6, R5 ; /* 0x0000000506037221 */
/* 0x000fe40000010000 */
/*0820*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0830*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x001fe400078e0003 */
/*0840*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0850*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff7a002007950 */
/* 0x000fea0003c3ffff */
/*0860*/ BRA 0x860; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void UpdateScalars(float *WHAT , float *WITH , float AMOUNT , float *MASS) {
int idx = threadIdx.x + blockIdx.x * blockDim.x; // this defines the element
WHAT[idx] += AMOUNT*WITH[idx]/MASS[idx];
} | .file "tmpxft_0009f6d7_00000000-6_UpdateScalars.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z13UpdateScalarsPfS_fS_PfS_fS_
.type _Z38__device_stub__Z13UpdateScalarsPfS_fS_PfS_fS_, @function
_Z38__device_stub__Z13UpdateScalarsPfS_fS_PfS_fS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13UpdateScalarsPfS_fS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z13UpdateScalarsPfS_fS_PfS_fS_, .-_Z38__device_stub__Z13UpdateScalarsPfS_fS_PfS_fS_
.globl _Z13UpdateScalarsPfS_fS_
.type _Z13UpdateScalarsPfS_fS_, @function
_Z13UpdateScalarsPfS_fS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13UpdateScalarsPfS_fS_PfS_fS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13UpdateScalarsPfS_fS_, .-_Z13UpdateScalarsPfS_fS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13UpdateScalarsPfS_fS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13UpdateScalarsPfS_fS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void UpdateScalars(float *WHAT , float *WITH , float AMOUNT , float *MASS) {
int idx = threadIdx.x + blockIdx.x * blockDim.x; // this defines the element
WHAT[idx] += AMOUNT*WITH[idx]/MASS[idx];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void UpdateScalars(float *WHAT , float *WITH , float AMOUNT , float *MASS) {
int idx = threadIdx.x + blockIdx.x * blockDim.x; // this defines the element
WHAT[idx] += AMOUNT*WITH[idx]/MASS[idx];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void UpdateScalars(float *WHAT , float *WITH , float AMOUNT , float *MASS) {
int idx = threadIdx.x + blockIdx.x * blockDim.x; // this defines the element
WHAT[idx] += AMOUNT*WITH[idx]/MASS[idx];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13UpdateScalarsPfS_fS_
.globl _Z13UpdateScalarsPfS_fS_
.p2align 8
.type _Z13UpdateScalarsPfS_fS_,@function
_Z13UpdateScalarsPfS_fS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b32 s0, s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v4, v[0:1], off
s_waitcnt vmcnt(2)
v_mul_f32_e32 v2, s0, v2
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v5, null, v3, v3, v2
v_rcp_f32_e32 v6, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v7, -v5, v6, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v7, v6
v_div_scale_f32 v7, vcc_lo, v2, v3, v2
v_mul_f32_e32 v8, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v9, -v5, v8, v7
v_fmac_f32_e32 v8, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, -v5, v8, v7
v_div_fmas_f32 v5, v5, v6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f32 v2, v5, v3, v2
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v4, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13UpdateScalarsPfS_fS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13UpdateScalarsPfS_fS_, .Lfunc_end0-_Z13UpdateScalarsPfS_fS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13UpdateScalarsPfS_fS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13UpdateScalarsPfS_fS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void UpdateScalars(float *WHAT , float *WITH , float AMOUNT , float *MASS) {
int idx = threadIdx.x + blockIdx.x * blockDim.x; // this defines the element
WHAT[idx] += AMOUNT*WITH[idx]/MASS[idx];
} | .text
.file "UpdateScalars.hip"
.globl _Z28__device_stub__UpdateScalarsPfS_fS_ # -- Begin function _Z28__device_stub__UpdateScalarsPfS_fS_
.p2align 4, 0x90
.type _Z28__device_stub__UpdateScalarsPfS_fS_,@function
_Z28__device_stub__UpdateScalarsPfS_fS_: # @_Z28__device_stub__UpdateScalarsPfS_fS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 4(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13UpdateScalarsPfS_fS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__UpdateScalarsPfS_fS_, .Lfunc_end0-_Z28__device_stub__UpdateScalarsPfS_fS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13UpdateScalarsPfS_fS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13UpdateScalarsPfS_fS_,@object # @_Z13UpdateScalarsPfS_fS_
.section .rodata,"a",@progbits
.globl _Z13UpdateScalarsPfS_fS_
.p2align 3, 0x0
_Z13UpdateScalarsPfS_fS_:
.quad _Z28__device_stub__UpdateScalarsPfS_fS_
.size _Z13UpdateScalarsPfS_fS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13UpdateScalarsPfS_fS_"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__UpdateScalarsPfS_fS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13UpdateScalarsPfS_fS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13UpdateScalarsPfS_fS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc800078e0200 */
/*0060*/ IMAD.WIDE R4, R0, R7, c[0x0][0x178] ; /* 0x00005e0000047625 */
/* 0x000fcc00078e0207 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R2, R0, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0207 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ee2000c1e1900 */
/*00a0*/ BSSY B0, 0x170 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*00b0*/ MUFU.RCP R8, R5 ; /* 0x0000000500087308 */
/* 0x004e220000001000 */
/*00c0*/ FMUL R6, R2, c[0x0][0x170] ; /* 0x00005c0002067a20 */
/* 0x008fce0000400000 */
/*00d0*/ FCHK P0, R6, R5 ; /* 0x0000000506007302 */
/* 0x000e620000000000 */
/*00e0*/ FFMA R7, -R5, R8, 1 ; /* 0x3f80000005077423 */
/* 0x001fc80000000108 */
/*00f0*/ FFMA R7, R8, R7, R8 ; /* 0x0000000708077223 */
/* 0x000fc80000000008 */
/*0100*/ FFMA R8, R6, R7, RZ ; /* 0x0000000706087223 */
/* 0x000fc800000000ff */
/*0110*/ FFMA R9, -R5, R8, R6 ; /* 0x0000000805097223 */
/* 0x000fc80000000106 */
/*0120*/ FFMA R7, R7, R9, R8 ; /* 0x0000000907077223 */
/* 0x000fe20000000008 */
/*0130*/ @!P0 BRA 0x160 ; /* 0x0000002000008947 */
/* 0x002fea0003800000 */
/*0140*/ MOV R2, 0x160 ; /* 0x0000016000027802 */
/* 0x000fe40000000f00 */
/*0150*/ CALL.REL.NOINC 0x1d0 ; /* 0x0000007000007944 */
/* 0x000fea0003c00000 */
/*0160*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0180*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0190*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*01a0*/ FADD R7, R0, R7 ; /* 0x0000000700077221 */
/* 0x004fca0000000000 */
/*01b0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ SHF.R.U32.HI R4, RZ, 0x17, R5.reuse ; /* 0x00000017ff047819 */
/* 0x100fe20000011605 */
/*01e0*/ BSSY B1, 0x830 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*01f0*/ SHF.R.U32.HI R3, RZ, 0x17, R6.reuse ; /* 0x00000017ff037819 */
/* 0x100fe20000011606 */
/*0200*/ IMAD.MOV.U32 R7, RZ, RZ, R6 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0006 */
/*0210*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fe200078ec0ff */
/*0220*/ IMAD.MOV.U32 R8, RZ, RZ, R5 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0005 */
/*0230*/ LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03037812 */
/* 0x000fe400078ec0ff */
/*0240*/ IADD3 R11, R4, -0x1, RZ ; /* 0xffffffff040b7810 */
/* 0x000fe40007ffe0ff */
/*0250*/ IADD3 R10, R3, -0x1, RZ ; /* 0xffffffff030a7810 */
/* 0x000fc40007ffe0ff */
/*0260*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fc80003f04070 */
/*0270*/ ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; /* 0x000000fd0a00780c */
/* 0x000fda0000704470 */
/*0280*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0290*/ @!P0 BRA 0x410 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*02a0*/ FSETP.GTU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fe40003f1c200 */
/*02b0*/ FSETP.GTU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fc80003f3c200 */
/*02c0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*02d0*/ @P0 BRA 0x810 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*02e0*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c807 */
/*02f0*/ @!P0 BRA 0x7f0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0300*/ FSETP.NEU.FTZ.AND P2, PT, |R6|.reuse, +INF , PT ; /* 0x7f8000000600780b */
/* 0x040fe40003f5d200 */
/*0310*/ FSETP.NEU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fe40003f3d200 */
/*0320*/ FSETP.NEU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fd60003f1d200 */
/*0330*/ @!P1 BRA !P2, 0x7f0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0340*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*0350*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0360*/ @P1 BRA 0x7d0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0370*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*0380*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0390*/ @P0 BRA 0x7a0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*03a0*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f06270 */
/*03b0*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f26270 */
/*03c0*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*03d0*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*03e0*/ @!P0 FFMA R7, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f80000006078823 */
/* 0x000fe400000000ff */
/*03f0*/ @!P1 FFMA R8, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005089823 */
/* 0x000fe200000000ff */
/*0400*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*0410*/ LEA R5, R4, 0xc0800000, 0x17 ; /* 0xc080000004057811 */
/* 0x000fe200078eb8ff */
/*0420*/ BSSY B2, 0x790 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*0430*/ IMAD.IADD R8, R8, 0x1, -R5 ; /* 0x0000000108087824 */
/* 0x000fe200078e0a05 */
/*0440*/ IADD3 R5, R3, -0x7f, RZ ; /* 0xffffff8103057810 */
/* 0x000fc60007ffe0ff */
/*0450*/ MUFU.RCP R6, R8 ; /* 0x0000000800067308 */
/* 0x000e220000001000 */
/*0460*/ FADD.FTZ R10, -R8, -RZ ; /* 0x800000ff080a7221 */
/* 0x000fe40000010100 */
/*0470*/ IMAD R7, R5, -0x800000, R7 ; /* 0xff80000005077824 */
/* 0x000fe400078e0207 */
/*0480*/ FFMA R3, R6, R10, 1 ; /* 0x3f80000006037423 */
/* 0x001fc8000000000a */
/*0490*/ FFMA R12, R6, R3, R6 ; /* 0x00000003060c7223 */
/* 0x000fc80000000006 */
/*04a0*/ FFMA R3, R7, R12, RZ ; /* 0x0000000c07037223 */
/* 0x000fc800000000ff */
/*04b0*/ FFMA R6, R10, R3, R7 ; /* 0x000000030a067223 */
/* 0x000fc80000000007 */
/*04c0*/ FFMA R11, R12, R6, R3 ; /* 0x000000060c0b7223 */
/* 0x000fe20000000003 */
/*04d0*/ IADD3 R6, R5, 0x7f, -R4 ; /* 0x0000007f05067810 */
/* 0x000fc60007ffe804 */
/*04e0*/ FFMA R7, R10, R11, R7 ; /* 0x0000000b0a077223 */
/* 0x000fe40000000007 */
/*04f0*/ IMAD.IADD R6, R6, 0x1, R9 ; /* 0x0000000106067824 */
/* 0x000fe400078e0209 */
/*0500*/ FFMA R3, R12, R7, R11 ; /* 0x000000070c037223 */
/* 0x000fca000000000b */
/*0510*/ SHF.R.U32.HI R4, RZ, 0x17, R3 ; /* 0x00000017ff047819 */
/* 0x000fc80000011603 */
/*0520*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*0530*/ IMAD.IADD R8, R4, 0x1, R6 ; /* 0x0000000104087824 */
/* 0x000fca00078e0206 */
/*0540*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fc80007ffe0ff */
/*0550*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*0560*/ @!P0 BRA 0x770 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0570*/ ISETP.GT.AND P0, PT, R8, 0xfe, PT ; /* 0x000000fe0800780c */
/* 0x000fda0003f04270 */
/*0580*/ @P0 BRA 0x740 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0590*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*05a0*/ @P0 BRA 0x780 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*05b0*/ ISETP.GE.AND P0, PT, R8, -0x18, PT ; /* 0xffffffe80800780c */
/* 0x000fe40003f06270 */
/*05c0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*05d0*/ @!P0 BRA 0x780 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*05e0*/ FFMA.RZ R4, R12, R7.reuse, R11.reuse ; /* 0x000000070c047223 */
/* 0x180fe2000000c00b */
/*05f0*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f45270 */
/*0600*/ FFMA.RM R5, R12, R7.reuse, R11.reuse ; /* 0x000000070c057223 */
/* 0x180fe2000000400b */
/*0610*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f25270 */
/*0620*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */
/* 0x000fe200078ec0ff */
/*0630*/ FFMA.RP R4, R12, R7, R11 ; /* 0x000000070c047223 */
/* 0x000fe2000000800b */
/*0640*/ IADD3 R7, R8, 0x20, RZ ; /* 0x0000002008077810 */
/* 0x000fe20007ffe0ff */
/*0650*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0a08 */
/*0660*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe400078efcff */
/*0670*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fc40003f1d000 */
/*0680*/ SHF.L.U32 R7, R6, R7, RZ ; /* 0x0000000706077219 */
/* 0x000fe400000006ff */
/*0690*/ SEL R5, R8, RZ, P2 ; /* 0x000000ff08057207 */
/* 0x000fe40001000000 */
/*06a0*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*06b0*/ SHF.R.U32.HI R5, RZ, R5, R6 ; /* 0x00000005ff057219 */
/* 0x000fe40000011606 */
/*06c0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*06d0*/ SHF.R.U32.HI R7, RZ, 0x1, R5 ; /* 0x00000001ff077819 */
/* 0x000fc40000011605 */
/*06e0*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*06f0*/ LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef807 */
/*0700*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */
/* 0x000fca00078ec0ff */
/*0710*/ IMAD.IADD R4, R7, 0x1, R4 ; /* 0x0000000107047824 */
/* 0x000fca00078e0204 */
/*0720*/ LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304037212 */
/* 0x000fe200078efcff */
/*0730*/ BRA 0x780 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0740*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0750*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0760*/ BRA 0x780 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0770*/ IMAD R3, R6, 0x800000, R3 ; /* 0x0080000006037824 */
/* 0x000fe400078e0203 */
/*0780*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0790*/ BRA 0x820 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*07a0*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fc800078e4807 */
/*07b0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*07c0*/ BRA 0x820 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*07d0*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fe200078e4807 */
/*07e0*/ BRA 0x820 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*07f0*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0800*/ BRA 0x820 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0810*/ FADD.FTZ R3, R6, R5 ; /* 0x0000000506037221 */
/* 0x000fe40000010000 */
/*0820*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0830*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x001fe400078e0003 */
/*0840*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0850*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff7a002007950 */
/* 0x000fea0003c3ffff */
/*0860*/ BRA 0x860; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13UpdateScalarsPfS_fS_
.globl _Z13UpdateScalarsPfS_fS_
.p2align 8
.type _Z13UpdateScalarsPfS_fS_,@function
_Z13UpdateScalarsPfS_fS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b32 s0, s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v4, v[0:1], off
s_waitcnt vmcnt(2)
v_mul_f32_e32 v2, s0, v2
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v5, null, v3, v3, v2
v_rcp_f32_e32 v6, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v7, -v5, v6, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v7, v6
v_div_scale_f32 v7, vcc_lo, v2, v3, v2
v_mul_f32_e32 v8, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v9, -v5, v8, v7
v_fmac_f32_e32 v8, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, -v5, v8, v7
v_div_fmas_f32 v5, v5, v6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fixup_f32 v2, v5, v3, v2
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v4, v2
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13UpdateScalarsPfS_fS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13UpdateScalarsPfS_fS_, .Lfunc_end0-_Z13UpdateScalarsPfS_fS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13UpdateScalarsPfS_fS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13UpdateScalarsPfS_fS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009f6d7_00000000-6_UpdateScalars.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z13UpdateScalarsPfS_fS_PfS_fS_
.type _Z38__device_stub__Z13UpdateScalarsPfS_fS_PfS_fS_, @function
_Z38__device_stub__Z13UpdateScalarsPfS_fS_PfS_fS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13UpdateScalarsPfS_fS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z13UpdateScalarsPfS_fS_PfS_fS_, .-_Z38__device_stub__Z13UpdateScalarsPfS_fS_PfS_fS_
.globl _Z13UpdateScalarsPfS_fS_
.type _Z13UpdateScalarsPfS_fS_, @function
_Z13UpdateScalarsPfS_fS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13UpdateScalarsPfS_fS_PfS_fS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13UpdateScalarsPfS_fS_, .-_Z13UpdateScalarsPfS_fS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13UpdateScalarsPfS_fS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13UpdateScalarsPfS_fS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "UpdateScalars.hip"
.globl _Z28__device_stub__UpdateScalarsPfS_fS_ # -- Begin function _Z28__device_stub__UpdateScalarsPfS_fS_
.p2align 4, 0x90
.type _Z28__device_stub__UpdateScalarsPfS_fS_,@function
_Z28__device_stub__UpdateScalarsPfS_fS_: # @_Z28__device_stub__UpdateScalarsPfS_fS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 4(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13UpdateScalarsPfS_fS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__UpdateScalarsPfS_fS_, .Lfunc_end0-_Z28__device_stub__UpdateScalarsPfS_fS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13UpdateScalarsPfS_fS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13UpdateScalarsPfS_fS_,@object # @_Z13UpdateScalarsPfS_fS_
.section .rodata,"a",@progbits
.globl _Z13UpdateScalarsPfS_fS_
.p2align 3, 0x0
_Z13UpdateScalarsPfS_fS_:
.quad _Z28__device_stub__UpdateScalarsPfS_fS_
.size _Z13UpdateScalarsPfS_fS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13UpdateScalarsPfS_fS_"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__UpdateScalarsPfS_fS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13UpdateScalarsPfS_fS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void process_kernel1(float *A, float *B, float *C, int N)
{
int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x+ blockIdx.x;
int threadNum = threadIdx.z * (blockDim.x* blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
int globalThreadId = blockNum * (blockDim.x * blockDim.y * blockDim.z) +threadNum;
if (globalThreadId<N)
{
C[globalThreadId] = sin(A[globalThreadId]) + cos(B[globalThreadId]);
}
}
__global__ void process_kernel2(float *A, float *C, int N)
{
int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x+ blockIdx.x;
int threadNum = threadIdx.z * (blockDim.x* blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
int globalThreadId = blockNum * (blockDim.x * blockDim.y * blockDim.z) +threadNum;
if (globalThreadId<N)
{
C[globalThreadId] = log(A[globalThreadId]);
}
}
__global__ void process_kernel3(float *A, float *C, int N)
{
int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x+ blockIdx.x;
int threadNum = threadIdx.z * (blockDim.x* blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
int globalThreadId = blockNum * (blockDim.x * blockDim.y * blockDim.z) +threadNum;
if (globalThreadId<N)
{
C[globalThreadId] = sqrt(A[globalThreadId]);
}
} | .file "tmpxft_000cb71f_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z15process_kernel1PfS_S_iPfS_S_i
.type _Z40__device_stub__Z15process_kernel1PfS_S_iPfS_S_i, @function
_Z40__device_stub__Z15process_kernel1PfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15process_kernel1PfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z15process_kernel1PfS_S_iPfS_S_i, .-_Z40__device_stub__Z15process_kernel1PfS_S_iPfS_S_i
.globl _Z15process_kernel1PfS_S_i
.type _Z15process_kernel1PfS_S_i, @function
_Z15process_kernel1PfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15process_kernel1PfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15process_kernel1PfS_S_i, .-_Z15process_kernel1PfS_S_i
.globl _Z38__device_stub__Z15process_kernel2PfS_iPfS_i
.type _Z38__device_stub__Z15process_kernel2PfS_iPfS_i, @function
_Z38__device_stub__Z15process_kernel2PfS_iPfS_i:
.LFB2053:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15process_kernel2PfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z38__device_stub__Z15process_kernel2PfS_iPfS_i, .-_Z38__device_stub__Z15process_kernel2PfS_iPfS_i
.globl _Z15process_kernel2PfS_i
.type _Z15process_kernel2PfS_i, @function
_Z15process_kernel2PfS_i:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15process_kernel2PfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z15process_kernel2PfS_i, .-_Z15process_kernel2PfS_i
.globl _Z38__device_stub__Z15process_kernel3PfS_iPfS_i
.type _Z38__device_stub__Z15process_kernel3PfS_iPfS_i, @function
_Z38__device_stub__Z15process_kernel3PfS_iPfS_i:
.LFB2055:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15process_kernel3PfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z38__device_stub__Z15process_kernel3PfS_iPfS_i, .-_Z38__device_stub__Z15process_kernel3PfS_iPfS_i
.globl _Z15process_kernel3PfS_i
.type _Z15process_kernel3PfS_i, @function
_Z15process_kernel3PfS_i:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15process_kernel3PfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z15process_kernel3PfS_i, .-_Z15process_kernel3PfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15process_kernel3PfS_i"
.LC1:
.string "_Z15process_kernel2PfS_i"
.LC2:
.string "_Z15process_kernel1PfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15process_kernel3PfS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z15process_kernel2PfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z15process_kernel1PfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void process_kernel1(float *A, float *B, float *C, int N)
{
int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x+ blockIdx.x;
int threadNum = threadIdx.z * (blockDim.x* blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
int globalThreadId = blockNum * (blockDim.x * blockDim.y * blockDim.z) +threadNum;
if (globalThreadId<N)
{
C[globalThreadId] = sin(A[globalThreadId]) + cos(B[globalThreadId]);
}
}
__global__ void process_kernel2(float *A, float *C, int N)
{
int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x+ blockIdx.x;
int threadNum = threadIdx.z * (blockDim.x* blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
int globalThreadId = blockNum * (blockDim.x * blockDim.y * blockDim.z) +threadNum;
if (globalThreadId<N)
{
C[globalThreadId] = log(A[globalThreadId]);
}
}
__global__ void process_kernel3(float *A, float *C, int N)
{
int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x+ blockIdx.x;
int threadNum = threadIdx.z * (blockDim.x* blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
int globalThreadId = blockNum * (blockDim.x * blockDim.y * blockDim.z) +threadNum;
if (globalThreadId<N)
{
C[globalThreadId] = sqrt(A[globalThreadId]);
}
} | #include <hip/hip_runtime.h>
__global__ void process_kernel1(float *A, float *B, float *C, int N)
{
int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x+ blockIdx.x;
int threadNum = threadIdx.z * (blockDim.x* blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
int globalThreadId = blockNum * (blockDim.x * blockDim.y * blockDim.z) +threadNum;
if (globalThreadId<N)
{
C[globalThreadId] = sin(A[globalThreadId]) + cos(B[globalThreadId]);
}
}
__global__ void process_kernel2(float *A, float *C, int N)
{
int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x+ blockIdx.x;
int threadNum = threadIdx.z * (blockDim.x* blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
int globalThreadId = blockNum * (blockDim.x * blockDim.y * blockDim.z) +threadNum;
if (globalThreadId<N)
{
C[globalThreadId] = log(A[globalThreadId]);
}
}
__global__ void process_kernel3(float *A, float *C, int N)
{
int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x+ blockIdx.x;
int threadNum = threadIdx.z * (blockDim.x* blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
int globalThreadId = blockNum * (blockDim.x * blockDim.y * blockDim.z) +threadNum;
if (globalThreadId<N)
{
C[globalThreadId] = sqrt(A[globalThreadId]);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void process_kernel1(float *A, float *B, float *C, int N)
{
int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x+ blockIdx.x;
int threadNum = threadIdx.z * (blockDim.x* blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
int globalThreadId = blockNum * (blockDim.x * blockDim.y * blockDim.z) +threadNum;
if (globalThreadId<N)
{
C[globalThreadId] = sin(A[globalThreadId]) + cos(B[globalThreadId]);
}
}
__global__ void process_kernel2(float *A, float *C, int N)
{
int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x+ blockIdx.x;
int threadNum = threadIdx.z * (blockDim.x* blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
int globalThreadId = blockNum * (blockDim.x * blockDim.y * blockDim.z) +threadNum;
if (globalThreadId<N)
{
C[globalThreadId] = log(A[globalThreadId]);
}
}
__global__ void process_kernel3(float *A, float *C, int N)
{
int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x+ blockIdx.x;
int threadNum = threadIdx.z * (blockDim.x* blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
int globalThreadId = blockNum * (blockDim.x * blockDim.y * blockDim.z) +threadNum;
if (globalThreadId<N)
{
C[globalThreadId] = sqrt(A[globalThreadId]);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15process_kernel1PfS_S_i
.globl _Z15process_kernel1PfS_S_i
.p2align 8
.type _Z15process_kernel1PfS_S_i,@function
_Z15process_kernel1PfS_S_i:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x20
s_load_b64 s[4:5], s[0:1], 0x2c
v_bfe_u32 v1, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s14
s_mul_i32 s2, s3, s2
s_and_b32 s3, s5, 0xffff
s_add_i32 s2, s2, s13
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s2, s3, v[1:2]
v_bfe_u32 v1, v0, 10, 10
s_load_b32 s2, s[0:1], 0x18
s_lshr_b32 s3, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, v2, s3, v[1:2]
v_and_b32_e32 v2, 0x3ff, v0
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, v3, s3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_10
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_mov_b32 s3, exec_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v3, 0x7fffffff, v2
v_cmpx_ngt_f32_e64 0x48000000, |v2|
s_xor_b32 s4, exec_lo, s3
s_cbranch_execz .LBB0_3
s_mov_b32 s2, 0x7fffff
v_mov_b32_e32 v6, 0
v_and_or_b32 v14, v3, s2, 0x800000
v_lshrrev_b32_e32 v11, 23, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[4:5], null, v14, 0xfe5163ab, 0
v_add_nc_u32_e32 v12, 0xffffff88, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_u32_e32 vcc_lo, 63, v12
v_mad_u64_u32 v[7:8], null, v14, 0x3c439041, v[5:6]
v_cndmask_b32_e64 v13, 0, 0xffffffc0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v5, v8
v_add_nc_u32_e32 v13, v13, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[8:9], null, v14, 0xdb629599, v[5:6]
v_cmp_lt_u32_e64 s2, 31, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v15, 0, 0xffffffe0, s2
v_dual_mov_b32 v5, v9 :: v_dual_cndmask_b32 v4, v8, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v15, v15, v13
v_mad_u64_u32 v[9:10], null, v14, 0xf534ddc0, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s3, 31, v15
v_mov_b32_e32 v5, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v7, v9, v7, vcc_lo
v_mad_u64_u32 v[10:11], null, v14, 0xfc2757d1, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v4, v7, v4, s2
v_mov_b32_e32 v5, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[11:12], null, v14, 0x4e441529, v[5:6]
v_mov_b32_e32 v5, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[12:13], null, v14, 0xa2f9836e, v[5:6]
v_cndmask_b32_e64 v5, 0, 0xffffffe0, s3
v_dual_cndmask_b32 v6, v11, v9 :: v_dual_add_nc_u32 v5, v5, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v12, v12, v10 :: v_dual_cndmask_b32 v11, v13, v11
v_cndmask_b32_e32 v10, v10, v8, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v9, v12, v6, s2
v_cndmask_b32_e64 v11, v11, v12, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v6, v6, v10, s2
v_sub_nc_u32_e32 v12, 32, v5
v_cndmask_b32_e64 v10, v10, v7, s2
v_cndmask_b32_e64 v11, v11, v9, s3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v9, v9, v6, s3
v_cndmask_b32_e64 v6, v6, v10, s3
v_cndmask_b32_e64 v4, v10, v4, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v13, v11, v9, v12
v_alignbit_b32 v8, v9, v6, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v5, v13, v11, vcc_lo
v_alignbit_b32 v11, v6, v4, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v7, v8, v9, vcc_lo
v_bfe_u32 v8, v5, 29, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v6, v11, v6, vcc_lo
v_alignbit_b32 v9, v5, v7, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v10, 0, v8
v_alignbit_b32 v7, v7, v6, 30
v_alignbit_b32 v4, v6, v4, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v9, v9, v10
v_xor_b32_e32 v6, v7, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v4, v4, v10
v_clz_i32_u32_e32 v11, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v11, 32, v11
v_sub_nc_u32_e32 v7, 31, v11
v_lshlrev_b32_e32 v13, 23, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_alignbit_b32 v9, v9, v6, v7
v_alignbit_b32 v4, v6, v4, v7
v_lshrrev_b32_e32 v7, 29, v5
v_alignbit_b32 v6, v9, v4, 9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v7, 31, v7
v_lshrrev_b32_e32 v9, 9, v9
v_clz_i32_u32_e32 v10, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v12, 0.5, v7
v_min_u32_e32 v10, 32, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v12, v12, v13
v_sub_nc_u32_e32 v14, 31, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v4, v6, v4, v14
v_or_b32_e32 v6, v9, v12
v_add_lshl_u32 v9, v10, v11, 23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v4, 9, v4
v_mul_f32_e32 v10, 0x3fc90fda, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v4, v4, v9
v_fma_f32 v9, v6, 0x3fc90fda, -v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, 0x33000000, v4
v_fmamk_f32 v6, v6, 0x33a22168, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v4, v4, v7
v_fmac_f32_e32 v6, 0x3fc90fda, v4
v_lshrrev_b32_e32 v5, 30, v5
s_delay_alu instid0(VALU_DEP_1)
v_dual_add_f32 v4, v10, v6 :: v_dual_add_nc_u32 v5, v8, v5
.LBB0_3:
s_and_not1_saveexec_b32 s2, s4
v_mul_f32_e64 v4, 0x3f22f983, |v2|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v5, v4
v_fma_f32 v4, v5, 0xbfc90fda, |v2|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v4, v5, 0xb3a22168, v4
v_fmamk_f32 v4, v5, 0xa7c234c4, v4
v_cvt_i32_f32_e32 v5, v5
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[2:3], s[0:1], 0x8
v_lshlrev_b64 v[6:7], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_mov_b32 s3, exec_lo
global_load_b32 v6, v[6:7], off
s_waitcnt vmcnt(0)
v_cmpx_ngt_f32_e64 0x48000000, |v6|
s_xor_b32 s4, exec_lo, s3
s_cbranch_execz .LBB0_7
v_dual_mov_b32 v9, 0 :: v_dual_and_b32 v14, 0x7fffffff, v6
s_mov_b32 s2, 0x7fffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_and_or_b32 v17, v14, s2, 0x800000
v_lshrrev_b32_e32 v14, 23, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[7:8], null, v17, 0xfe5163ab, 0
v_add_nc_u32_e32 v15, 0xffffff88, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_u32_e32 vcc_lo, 63, v15
v_mad_u64_u32 v[10:11], null, v17, 0x3c439041, v[8:9]
v_cndmask_b32_e64 v16, 0, 0xffffffc0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v8, v11
v_add_nc_u32_e32 v16, v16, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[11:12], null, v17, 0xdb629599, v[8:9]
v_cmp_lt_u32_e64 s2, 31, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v18, 0, 0xffffffe0, s2
v_dual_mov_b32 v8, v12 :: v_dual_cndmask_b32 v7, v11, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v18, v18, v16
v_mad_u64_u32 v[12:13], null, v17, 0xf534ddc0, v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s3, 31, v18
v_mov_b32_e32 v8, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v10, v12, v10, vcc_lo
v_mad_u64_u32 v[13:14], null, v17, 0xfc2757d1, v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v7, v10, v7, s2
v_mov_b32_e32 v8, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[14:15], null, v17, 0x4e441529, v[8:9]
v_mov_b32_e32 v8, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[15:16], null, v17, 0xa2f9836e, v[8:9]
v_cndmask_b32_e64 v8, 0, 0xffffffe0, s3
v_dual_cndmask_b32 v9, v14, v12 :: v_dual_add_nc_u32 v8, v8, v18
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v15, v15, v13 :: v_dual_cndmask_b32 v14, v16, v14
v_cndmask_b32_e32 v13, v13, v11, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v12, v15, v9, s2
v_cndmask_b32_e64 v14, v14, v15, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v9, v9, v13, s2
v_sub_nc_u32_e32 v15, 32, v8
v_cndmask_b32_e64 v13, v13, v10, s2
v_cndmask_b32_e64 v14, v14, v12, s3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v12, v12, v9, s3
v_cndmask_b32_e64 v9, v9, v13, s3
v_cndmask_b32_e64 v7, v13, v7, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v16, v14, v12, v15
v_alignbit_b32 v11, v12, v9, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v8, v16, v14, vcc_lo
v_alignbit_b32 v14, v9, v7, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v10, v11, v12, vcc_lo
v_bfe_u32 v11, v8, 29, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v9, v14, v9, vcc_lo
v_alignbit_b32 v12, v8, v10, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v13, 0, v11
v_alignbit_b32 v10, v10, v9, 30
v_alignbit_b32 v7, v9, v7, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v12, v12, v13
v_xor_b32_e32 v9, v10, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v7, v7, v13
v_clz_i32_u32_e32 v14, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v14, 32, v14
v_sub_nc_u32_e32 v10, 31, v14
v_lshlrev_b32_e32 v16, 23, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_alignbit_b32 v12, v12, v9, v10
v_alignbit_b32 v7, v9, v7, v10
v_lshrrev_b32_e32 v10, 29, v8
v_alignbit_b32 v9, v12, v7, 9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v10, 31, v10
v_lshrrev_b32_e32 v12, 9, v12
v_clz_i32_u32_e32 v13, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v15, 0.5, v10
v_min_u32_e32 v13, 32, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v15, v15, v16
v_sub_nc_u32_e32 v17, 31, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v7, v9, v7, v17
v_or_b32_e32 v9, v12, v15
v_add_lshl_u32 v12, v13, v14, 23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v7, 9, v7
v_mul_f32_e32 v13, 0x3fc90fda, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v7, v7, v12
v_fma_f32 v12, v9, 0x3fc90fda, -v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v7, 0x33000000, v7
v_fmamk_f32 v9, v9, 0x33a22168, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v7, v7, v10
v_fmac_f32_e32 v9, 0x3fc90fda, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, v13, v9
v_lshrrev_b32_e32 v8, 30, v8
v_add_nc_u32_e32 v8, v11, v8
.LBB0_7:
s_and_not1_saveexec_b32 s2, s4
v_mul_f32_e64 v7, 0x3f22f983, |v6|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v8, v7
v_fma_f32 v7, v8, 0xbfc90fda, |v6|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v7, v8, 0xb3a22168, v7
v_fmamk_f32 v7, v8, 0xa7c234c4, v7
v_cvt_i32_f32_e32 v8, v8
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_dual_mul_f32 v9, v4, v4 :: v_dual_mul_f32 v10, v7, v7
s_mov_b32 s2, 0xb94c1982
s_mov_b32 s3, 0x37d75334
s_load_b64 s[0:1], s[0:1], 0x10
v_dual_fmaak_f32 v11, s2, v9, 0x3c0881c4 :: v_dual_fmaak_f32 v14, s2, v10, 0x3c0881c4
v_dual_fmaak_f32 v12, s3, v9, 0xbab64f3b :: v_dual_fmaak_f32 v15, s3, v10, 0xbab64f3b
v_and_b32_e32 v13, 1, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_fmaak_f32 v11, v9, v11, 0xbe2aaa9d :: v_dual_fmaak_f32 v14, v10, v14, 0xbe2aaa9d
v_dual_fmaak_f32 v12, v9, v12, 0x3d2aabf7 :: v_dual_lshlrev_b32 v5, 30, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_fmaak_f32 v15, v10, v15, 0x3d2aabf7 :: v_dual_and_b32 v16, 1, v8
v_dual_mul_f32 v11, v9, v11 :: v_dual_mul_f32 v14, v10, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmaak_f32 v12, v9, v12, 0xbf000004
v_cmp_eq_u32_e32 vcc_lo, 0, v13
v_dual_fmac_f32 v4, v4, v11 :: v_dual_and_b32 v5, 0x80000000, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_dual_fmac_f32 v7, v7, v14 :: v_dual_lshlrev_b32 v8, 30, v8
v_fma_f32 v9, v9, v12, 1.0
v_fmaak_f32 v15, v10, v15, 0xbf000004
v_xor_b32_e32 v3, v3, v2
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_and_b32_e32 v8, 0x80000000, v8
v_cndmask_b32_e32 v4, v9, v4, vcc_lo
v_fma_f32 v10, v10, v15, 1.0
v_cmp_eq_u32_e32 vcc_lo, 0, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor3_b32 v3, v3, v5, v4
v_cndmask_b32_e64 v7, -v7, v10, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x1f8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor_b32_e32 v4, v8, v7
v_cndmask_b32_e32 v2, 0x7fc00000, v3, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v6, 0x1f8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v3, 0x7fc00000, v4, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15process_kernel1PfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 19
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15process_kernel1PfS_S_i, .Lfunc_end0-_Z15process_kernel1PfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15process_kernel2PfS_i
.globl _Z15process_kernel2PfS_i
.p2align 8
.type _Z15process_kernel2PfS_i,@function
_Z15process_kernel2PfS_i:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b64 s[4:5], s[0:1], 0x24
v_bfe_u32 v1, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s14
s_mul_i32 s2, s3, s2
s_and_b32 s3, s5, 0xffff
s_add_i32 s2, s2, s13
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s2, s3, v[1:2]
v_bfe_u32 v1, v0, 10, 10
s_load_b32 s2, s[0:1], 0x10
s_lshr_b32 s3, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, v2, s3, v[1:2]
v_and_b32_e32 v2, 0x3ff, v0
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, v3, s3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, 0x800000, v2
v_cndmask_b32_e64 v3, 1.0, 0x4f800000, vcc_lo
v_mul_f32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_log_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x3f317217, v2
v_fma_f32 v4, v2, 0x3f317217, -v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v4, v2, 0x3377d1cf, v4
v_add_f32_e32 v3, v3, v4
v_cndmask_b32_e64 v4, 0, 0x41b17218, vcc_lo
v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v2|
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_sub_f32_e32 v2, v2, v4
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15process_kernel2PfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z15process_kernel2PfS_i, .Lfunc_end1-_Z15process_kernel2PfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15process_kernel3PfS_i
.globl _Z15process_kernel3PfS_i
.p2align 8
.type _Z15process_kernel3PfS_i,@function
_Z15process_kernel3PfS_i:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b64 s[4:5], s[0:1], 0x24
v_bfe_u32 v1, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s14
s_mul_i32 s2, s3, s2
s_and_b32 s3, s5, 0xffff
s_add_i32 s2, s2, s13
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s2, s3, v[1:2]
v_bfe_u32 v1, v0, 10, 10
s_load_b32 s2, s[0:1], 0x10
s_lshr_b32 s3, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, v2, s3, v[1:2]
v_and_b32_e32 v2, 0x3ff, v0
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, v3, s3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB2_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v3, 0x4f800000, v2
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v4, -1, v3
v_add_nc_u32_e32 v5, 1, v3
v_fma_f32 v6, -v4, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v7, -v5, v3, v2
v_cmp_ge_f32_e64 s0, 0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v3, v3, v4, s0
v_cmp_lt_f32_e64 s0, 0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v5, s0
v_mul_f32_e32 v4, 0x37800000, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x260
v_cndmask_b32_e32 v2, v3, v2, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15process_kernel3PfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z15process_kernel3PfS_i, .Lfunc_end2-_Z15process_kernel3PfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15process_kernel1PfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15process_kernel1PfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 19
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15process_kernel2PfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15process_kernel2PfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15process_kernel3PfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15process_kernel3PfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void process_kernel1(float *A, float *B, float *C, int N)
{
int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x+ blockIdx.x;
int threadNum = threadIdx.z * (blockDim.x* blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
int globalThreadId = blockNum * (blockDim.x * blockDim.y * blockDim.z) +threadNum;
if (globalThreadId<N)
{
C[globalThreadId] = sin(A[globalThreadId]) + cos(B[globalThreadId]);
}
}
__global__ void process_kernel2(float *A, float *C, int N)
{
int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x+ blockIdx.x;
int threadNum = threadIdx.z * (blockDim.x* blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
int globalThreadId = blockNum * (blockDim.x * blockDim.y * blockDim.z) +threadNum;
if (globalThreadId<N)
{
C[globalThreadId] = log(A[globalThreadId]);
}
}
__global__ void process_kernel3(float *A, float *C, int N)
{
int blockNum = blockIdx.z * (gridDim.x * gridDim.y) + blockIdx.y * gridDim.x+ blockIdx.x;
int threadNum = threadIdx.z * (blockDim.x* blockDim.y) + threadIdx.y * (blockDim.x) + threadIdx.x;
int globalThreadId = blockNum * (blockDim.x * blockDim.y * blockDim.z) +threadNum;
if (globalThreadId<N)
{
C[globalThreadId] = sqrt(A[globalThreadId]);
}
} | .text
.file "kernel.hip"
.globl _Z30__device_stub__process_kernel1PfS_S_i # -- Begin function _Z30__device_stub__process_kernel1PfS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__process_kernel1PfS_S_i,@function
_Z30__device_stub__process_kernel1PfS_S_i: # @_Z30__device_stub__process_kernel1PfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15process_kernel1PfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__process_kernel1PfS_S_i, .Lfunc_end0-_Z30__device_stub__process_kernel1PfS_S_i
.cfi_endproc
# -- End function
.globl _Z30__device_stub__process_kernel2PfS_i # -- Begin function _Z30__device_stub__process_kernel2PfS_i
.p2align 4, 0x90
.type _Z30__device_stub__process_kernel2PfS_i,@function
_Z30__device_stub__process_kernel2PfS_i: # @_Z30__device_stub__process_kernel2PfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15process_kernel2PfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z30__device_stub__process_kernel2PfS_i, .Lfunc_end1-_Z30__device_stub__process_kernel2PfS_i
.cfi_endproc
# -- End function
.globl _Z30__device_stub__process_kernel3PfS_i # -- Begin function _Z30__device_stub__process_kernel3PfS_i
.p2align 4, 0x90
.type _Z30__device_stub__process_kernel3PfS_i,@function
_Z30__device_stub__process_kernel3PfS_i: # @_Z30__device_stub__process_kernel3PfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15process_kernel3PfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z30__device_stub__process_kernel3PfS_i, .Lfunc_end2-_Z30__device_stub__process_kernel3PfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15process_kernel1PfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15process_kernel2PfS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15process_kernel3PfS_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15process_kernel1PfS_S_i,@object # @_Z15process_kernel1PfS_S_i
.section .rodata,"a",@progbits
.globl _Z15process_kernel1PfS_S_i
.p2align 3, 0x0
_Z15process_kernel1PfS_S_i:
.quad _Z30__device_stub__process_kernel1PfS_S_i
.size _Z15process_kernel1PfS_S_i, 8
.type _Z15process_kernel2PfS_i,@object # @_Z15process_kernel2PfS_i
.globl _Z15process_kernel2PfS_i
.p2align 3, 0x0
_Z15process_kernel2PfS_i:
.quad _Z30__device_stub__process_kernel2PfS_i
.size _Z15process_kernel2PfS_i, 8
.type _Z15process_kernel3PfS_i,@object # @_Z15process_kernel3PfS_i
.globl _Z15process_kernel3PfS_i
.p2align 3, 0x0
_Z15process_kernel3PfS_i:
.quad _Z30__device_stub__process_kernel3PfS_i
.size _Z15process_kernel3PfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15process_kernel1PfS_S_i"
.size .L__unnamed_1, 27
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15process_kernel2PfS_i"
.size .L__unnamed_2, 25
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z15process_kernel3PfS_i"
.size .L__unnamed_3, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__process_kernel1PfS_S_i
.addrsig_sym _Z30__device_stub__process_kernel2PfS_i
.addrsig_sym _Z30__device_stub__process_kernel3PfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15process_kernel1PfS_S_i
.addrsig_sym _Z15process_kernel2PfS_i
.addrsig_sym _Z15process_kernel3PfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000cb71f_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z15process_kernel1PfS_S_iPfS_S_i
.type _Z40__device_stub__Z15process_kernel1PfS_S_iPfS_S_i, @function
_Z40__device_stub__Z15process_kernel1PfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15process_kernel1PfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z15process_kernel1PfS_S_iPfS_S_i, .-_Z40__device_stub__Z15process_kernel1PfS_S_iPfS_S_i
.globl _Z15process_kernel1PfS_S_i
.type _Z15process_kernel1PfS_S_i, @function
_Z15process_kernel1PfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15process_kernel1PfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15process_kernel1PfS_S_i, .-_Z15process_kernel1PfS_S_i
.globl _Z38__device_stub__Z15process_kernel2PfS_iPfS_i
.type _Z38__device_stub__Z15process_kernel2PfS_iPfS_i, @function
_Z38__device_stub__Z15process_kernel2PfS_iPfS_i:
.LFB2053:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15process_kernel2PfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z38__device_stub__Z15process_kernel2PfS_iPfS_i, .-_Z38__device_stub__Z15process_kernel2PfS_iPfS_i
.globl _Z15process_kernel2PfS_i
.type _Z15process_kernel2PfS_i, @function
_Z15process_kernel2PfS_i:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15process_kernel2PfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z15process_kernel2PfS_i, .-_Z15process_kernel2PfS_i
.globl _Z38__device_stub__Z15process_kernel3PfS_iPfS_i
.type _Z38__device_stub__Z15process_kernel3PfS_iPfS_i, @function
_Z38__device_stub__Z15process_kernel3PfS_iPfS_i:
.LFB2055:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15process_kernel3PfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z38__device_stub__Z15process_kernel3PfS_iPfS_i, .-_Z38__device_stub__Z15process_kernel3PfS_iPfS_i
.globl _Z15process_kernel3PfS_i
.type _Z15process_kernel3PfS_i, @function
_Z15process_kernel3PfS_i:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15process_kernel3PfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z15process_kernel3PfS_i, .-_Z15process_kernel3PfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15process_kernel3PfS_i"
.LC1:
.string "_Z15process_kernel2PfS_i"
.LC2:
.string "_Z15process_kernel1PfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15process_kernel3PfS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z15process_kernel2PfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z15process_kernel1PfS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z30__device_stub__process_kernel1PfS_S_i # -- Begin function _Z30__device_stub__process_kernel1PfS_S_i
.p2align 4, 0x90
.type _Z30__device_stub__process_kernel1PfS_S_i,@function
_Z30__device_stub__process_kernel1PfS_S_i: # @_Z30__device_stub__process_kernel1PfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15process_kernel1PfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__process_kernel1PfS_S_i, .Lfunc_end0-_Z30__device_stub__process_kernel1PfS_S_i
.cfi_endproc
# -- End function
.globl _Z30__device_stub__process_kernel2PfS_i # -- Begin function _Z30__device_stub__process_kernel2PfS_i
.p2align 4, 0x90
.type _Z30__device_stub__process_kernel2PfS_i,@function
_Z30__device_stub__process_kernel2PfS_i: # @_Z30__device_stub__process_kernel2PfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15process_kernel2PfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z30__device_stub__process_kernel2PfS_i, .Lfunc_end1-_Z30__device_stub__process_kernel2PfS_i
.cfi_endproc
# -- End function
.globl _Z30__device_stub__process_kernel3PfS_i # -- Begin function _Z30__device_stub__process_kernel3PfS_i
.p2align 4, 0x90
.type _Z30__device_stub__process_kernel3PfS_i,@function
_Z30__device_stub__process_kernel3PfS_i: # @_Z30__device_stub__process_kernel3PfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15process_kernel3PfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z30__device_stub__process_kernel3PfS_i, .Lfunc_end2-_Z30__device_stub__process_kernel3PfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15process_kernel1PfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15process_kernel2PfS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15process_kernel3PfS_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15process_kernel1PfS_S_i,@object # @_Z15process_kernel1PfS_S_i
.section .rodata,"a",@progbits
.globl _Z15process_kernel1PfS_S_i
.p2align 3, 0x0
_Z15process_kernel1PfS_S_i:
.quad _Z30__device_stub__process_kernel1PfS_S_i
.size _Z15process_kernel1PfS_S_i, 8
.type _Z15process_kernel2PfS_i,@object # @_Z15process_kernel2PfS_i
.globl _Z15process_kernel2PfS_i
.p2align 3, 0x0
_Z15process_kernel2PfS_i:
.quad _Z30__device_stub__process_kernel2PfS_i
.size _Z15process_kernel2PfS_i, 8
.type _Z15process_kernel3PfS_i,@object # @_Z15process_kernel3PfS_i
.globl _Z15process_kernel3PfS_i
.p2align 3, 0x0
_Z15process_kernel3PfS_i:
.quad _Z30__device_stub__process_kernel3PfS_i
.size _Z15process_kernel3PfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15process_kernel1PfS_S_i"
.size .L__unnamed_1, 27
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15process_kernel2PfS_i"
.size .L__unnamed_2, 25
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z15process_kernel3PfS_i"
.size .L__unnamed_3, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__process_kernel1PfS_S_i
.addrsig_sym _Z30__device_stub__process_kernel2PfS_i
.addrsig_sym _Z30__device_stub__process_kernel3PfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15process_kernel1PfS_S_i
.addrsig_sym _Z15process_kernel2PfS_i
.addrsig_sym _Z15process_kernel3PfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <pthread.h>
#define ARR_SIZE 10
#define NUM_DEVICE 2
#define NUM_THR 8
typedef struct {
int *arr;
int *dev_arr;
int *dev_result;
int *result;
int dev_num;
int thr_num;
} cuda_st;
__global__ void kernel_fc(int *dev_arr, int *dev_result)
{
int idx = threadIdx.x;
printf("dev_arr[%d] = %d\n", idx, dev_arr[idx]);
atomicAdd(dev_result, dev_arr[idx]);
}
void *thread_func(void* struc)
{
cuda_st * data = (cuda_st*)struc;
printf("thread %d func start\n", data->thr_num);
printf("arr %d = ", data->dev_num);
for(int i=0; i<10; i++) {
printf("%d ", data->arr[i]);
}
printf("\n");
cudaSetDevice(data->dev_num);
cudaMemcpy(data->dev_arr, data->arr, sizeof(int)*ARR_SIZE, cudaMemcpyHostToDevice);
kernel_fc<<<1,ARR_SIZE>>>(data->dev_arr, data->dev_result);
cudaMemcpy(data->result, data->dev_result, sizeof(int), cudaMemcpyDeviceToHost);
printf("thread %d func exit\n", data->thr_num);
return NULL;
}
int main(void)
{
// Make object
cuda_st cuda[NUM_DEVICE][NUM_THR];
// Make thread
pthread_t pthread[NUM_DEVICE*NUM_THR];
// Host array memory allocation
int *arr[NUM_DEVICE];
for(int i=0; i<NUM_DEVICE; i++) {
arr[i] = (int*)malloc(sizeof(int)*ARR_SIZE);
}
// Fill this host array up with specified data
for(int i=0; i<NUM_DEVICE; i++) {
for(int j=0; j<ARR_SIZE; j++) {
arr[i][j] = i*ARR_SIZE+j;
}
}
// To confirm host array data
for(int i=0; i<NUM_DEVICE; i++) {
printf("arr[%d] = ", i);
for(int j=0; j<ARR_SIZE; j++) {
printf("%d ", arr[i][j]);
}
printf("\n");
}
// Result memory allocation
int *result[NUM_DEVICE];
for(int i=0; i<NUM_DEVICE; i++) {
result[i] = (int*)malloc(sizeof(int));
memset(result[i], 0, sizeof(int));
}
// Device array memory allocation
int *dev_arr[NUM_DEVICE];
for(int i=0; i<NUM_DEVICE; i++) {
cudaSetDevice(i);
cudaMalloc(&dev_arr[i], sizeof(int)*ARR_SIZE);
}
// Device result memory allocation
int *dev_result[NUM_DEVICE];
for(int i=0; i<NUM_DEVICE; i++) {
cudaSetDevice(i);
cudaMalloc(&dev_result[i], sizeof(int));
cudaMemset(dev_result[i], 0, sizeof(int));
}
// Connect these pointers with object
for (int i=0; i<NUM_DEVICE; i++)
for (int j=0; j<NUM_THR; j++) {
cuda[i][j].arr = arr[i];
cuda[i][j].dev_arr = dev_arr[i];
cuda[i][j].result = result[i];
cuda[i][j].dev_result = dev_result[i];
cuda[i][j].dev_num = i;
cuda[i][j].thr_num = j;
}
// Create and excute pthread
for(int i=0; i<NUM_DEVICE; i++)
for (int j=0; j<NUM_THR; j++) {
pthread_create(&pthread[(i*NUM_THR)+j], NULL, thread_func, (void*)&cuda[i][j]);
}
// Join pthread
for(int i=0; i<NUM_DEVICE*NUM_THR; i++) {
pthread_join(pthread[i], NULL);
}
for(int i=0; i<NUM_DEVICE; i++)
for (int j=0; j < NUM_THR; j++) {
printf("result[%d][%d] = %d\n", i,j, (*cuda[i][j].result));
}
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z9kernel_fcPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff117424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe40007ffe0ff */
/*0050*/ IMAD.WIDE R16, R8, R17, c[0x0][0x160] ; /* 0x0000580008107625 */
/* 0x001fca00078e0211 */
/*0060*/ LDG.E R9, [R16.64] ; /* 0x0000002410097981 */
/* 0x000ea2000c1e1900 */
/*0070*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0080*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0090*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*00b0*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0000660000000a00 */
/*00c0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*00d0*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0041e80000100a00 */
/*00e0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x003fc60000000000 */
/*00f0*/ MOV R11, 0x160 ; /* 0x00000160000b7802 */
/* 0x000fe40000000f00 */
/*0100*/ MOV R20, 0xe0 ; /* 0x000000e000147802 */
/* 0x000fc40000000f00 */
/*0110*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0120*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0130*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0140*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0150*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*0160*/ LDG.E R16, [R16.64] ; /* 0x0000002410107981 */
/* 0x000ea2000c1e1900 */
/*0170*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe200038e0100 */
/*0180*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*0190*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fe200080e0000 */
/*01a0*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000e220000000000 */
/*01b0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fc800078e00ff */
/*01c0*/ ISETP.EQ.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x001fe2000bf02070 */
/*01d0*/ REDUX.SUM UR5, R16 ; /* 0x00000000100573c4 */
/* 0x004e24000000c000 */
/*01e0*/ IMAD.U32 R5, RZ, RZ, UR5 ; /* 0x00000005ff057e24 */
/* 0x001fd4000f8e00ff */
/*01f0*/ @P0 RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200098e */
/* 0x000fe2000c10e1a4 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <pthread.h>
#define ARR_SIZE 10
#define NUM_DEVICE 2
#define NUM_THR 8
typedef struct {
int *arr;
int *dev_arr;
int *dev_result;
int *result;
int dev_num;
int thr_num;
} cuda_st;
__global__ void kernel_fc(int *dev_arr, int *dev_result)
{
int idx = threadIdx.x;
printf("dev_arr[%d] = %d\n", idx, dev_arr[idx]);
atomicAdd(dev_result, dev_arr[idx]);
}
void *thread_func(void* struc)
{
cuda_st * data = (cuda_st*)struc;
printf("thread %d func start\n", data->thr_num);
printf("arr %d = ", data->dev_num);
for(int i=0; i<10; i++) {
printf("%d ", data->arr[i]);
}
printf("\n");
cudaSetDevice(data->dev_num);
cudaMemcpy(data->dev_arr, data->arr, sizeof(int)*ARR_SIZE, cudaMemcpyHostToDevice);
kernel_fc<<<1,ARR_SIZE>>>(data->dev_arr, data->dev_result);
cudaMemcpy(data->result, data->dev_result, sizeof(int), cudaMemcpyDeviceToHost);
printf("thread %d func exit\n", data->thr_num);
return NULL;
}
int main(void)
{
// Make object
cuda_st cuda[NUM_DEVICE][NUM_THR];
// Make thread
pthread_t pthread[NUM_DEVICE*NUM_THR];
// Host array memory allocation
int *arr[NUM_DEVICE];
for(int i=0; i<NUM_DEVICE; i++) {
arr[i] = (int*)malloc(sizeof(int)*ARR_SIZE);
}
// Fill this host array up with specified data
for(int i=0; i<NUM_DEVICE; i++) {
for(int j=0; j<ARR_SIZE; j++) {
arr[i][j] = i*ARR_SIZE+j;
}
}
// To confirm host array data
for(int i=0; i<NUM_DEVICE; i++) {
printf("arr[%d] = ", i);
for(int j=0; j<ARR_SIZE; j++) {
printf("%d ", arr[i][j]);
}
printf("\n");
}
// Result memory allocation
int *result[NUM_DEVICE];
for(int i=0; i<NUM_DEVICE; i++) {
result[i] = (int*)malloc(sizeof(int));
memset(result[i], 0, sizeof(int));
}
// Device array memory allocation
int *dev_arr[NUM_DEVICE];
for(int i=0; i<NUM_DEVICE; i++) {
cudaSetDevice(i);
cudaMalloc(&dev_arr[i], sizeof(int)*ARR_SIZE);
}
// Device result memory allocation
int *dev_result[NUM_DEVICE];
for(int i=0; i<NUM_DEVICE; i++) {
cudaSetDevice(i);
cudaMalloc(&dev_result[i], sizeof(int));
cudaMemset(dev_result[i], 0, sizeof(int));
}
// Connect these pointers with object
for (int i=0; i<NUM_DEVICE; i++)
for (int j=0; j<NUM_THR; j++) {
cuda[i][j].arr = arr[i];
cuda[i][j].dev_arr = dev_arr[i];
cuda[i][j].result = result[i];
cuda[i][j].dev_result = dev_result[i];
cuda[i][j].dev_num = i;
cuda[i][j].thr_num = j;
}
// Create and excute pthread
for(int i=0; i<NUM_DEVICE; i++)
for (int j=0; j<NUM_THR; j++) {
pthread_create(&pthread[(i*NUM_THR)+j], NULL, thread_func, (void*)&cuda[i][j]);
}
// Join pthread
for(int i=0; i<NUM_DEVICE*NUM_THR; i++) {
pthread_join(pthread[i], NULL);
}
for(int i=0; i<NUM_DEVICE; i++)
for (int j=0; j < NUM_THR; j++) {
printf("result[%d][%d] = %d\n", i,j, (*cuda[i][j].result));
}
cudaDeviceReset();
return 0;
} | .file "tmpxft_00182e62_00000000-6_multiGpuThread.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2071:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2071:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "arr[%d] = "
.LC1:
.string "%d "
.LC2:
.string "\n"
.LC3:
.string "result[%d][%d] = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2068:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $856, %rsp
.cfi_def_cfa_offset 912
movq %fs:40, %rax
movq %rax, 840(%rsp)
xorl %eax, %eax
movl $40, %edi
call malloc@PLT
movq %rax, %r14
movq %rax, 16(%rsp)
movl $40, %edi
call malloc@PLT
movq %rax, %r13
movq %rax, 24(%rsp)
movl $0, %eax
.L4:
movl %eax, (%r14,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L4
movl $0, %eax
.L5:
leal 10(%rax), %edx
movl %edx, 0(%r13,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L5
leaq 16(%rsp), %rbp
movl $0, %r15d
leaq .LC1(%rip), %r12
.L7:
movl %r15d, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
.L6:
movq 0(%rbp), %rax
movl (%rax,%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $40, %rbx
jne .L6
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r15d
addq $8, %rbp
cmpl $2, %r15d
jne .L7
movl $4, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, (%rax)
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, (%rax)
movl $0, %edi
call cudaSetDevice@PLT
leaq 32(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $1, %edi
call cudaSetDevice@PLT
leaq 40(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $0, %edi
call cudaSetDevice@PLT
leaq 48(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $4, %edx
movl $0, %esi
movq 48(%rsp), %rdi
call cudaMemset@PLT
movl $1, %edi
call cudaSetDevice@PLT
leaq 56(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $4, %edx
movl $0, %esi
movq 56(%rsp), %rdi
call cudaMemset@PLT
movq 32(%rsp), %rsi
movq 48(%rsp), %rcx
leaq 192(%rsp), %rax
movq %rax, 8(%rsp)
movl $0, %edx
.L8:
movq %r14, (%rax)
movq %rsi, 8(%rax)
movq %rbp, 24(%rax)
movq %rcx, 16(%rax)
movl $0, 32(%rax)
movl %edx, 36(%rax)
addl $1, %edx
addq $40, %rax
cmpl $8, %edx
jne .L8
movq 40(%rsp), %rsi
movq 56(%rsp), %rcx
leaq 512(%rsp), %rbp
movq %rbp, %rax
movl $0, %edx
.L9:
movq %r13, (%rax)
movq %rsi, 8(%rax)
movq %rbx, 24(%rax)
movq %rcx, 16(%rax)
movl $1, 32(%rax)
movl %edx, 36(%rax)
addl $1, %edx
addq $40, %rax
cmpl $8, %edx
jne .L9
leaq 64(%rsp), %rbx
movq 8(%rsp), %r12
leaq 320(%r12), %r15
movq %rbx, %r13
leaq _Z11thread_funcPv(%rip), %r14
.L10:
movq %r12, %rcx
movq %r14, %rdx
movl $0, %esi
movq %r13, %rdi
call pthread_create@PLT
addq $8, %r13
addq $40, %r12
cmpq %r15, %r12
jne .L10
leaq 128(%rsp), %r12
movq 8(%rsp), %r14
addq $640, %r14
leaq _Z11thread_funcPv(%rip), %r13
.L11:
movq %rbp, %rcx
movq %r13, %rdx
movl $0, %esi
movq %r12, %rdi
call pthread_create@PLT
addq $8, %r12
addq $40, %rbp
cmpq %r14, %rbp
jne .L11
leaq 128(%rbx), %rbp
.L12:
movq (%rbx), %rdi
movl $0, %esi
call pthread_join@PLT
addq $8, %rbx
cmpq %rbx, %rbp
jne .L12
leaq 216(%rsp), %rbp
movl $0, %ebx
leaq .LC3(%rip), %r12
.L13:
movq 0(%rbp), %rax
movl (%rax), %r8d
movl %ebx, %ecx
movl $0, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
addq $40, %rbp
cmpl $8, %ebx
jne .L13
leaq 536(%rsp), %rbp
movl $0, %ebx
leaq .LC3(%rip), %r12
.L14:
movq 0(%rbp), %rax
movl (%rax), %r8d
movl %ebx, %ecx
movl $1, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
addq $40, %rbp
cmpl $8, %ebx
jne .L14
call cudaDeviceReset@PLT
movq 840(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $856, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2068:
.size main, .-main
.globl _Z30__device_stub__Z9kernel_fcPiS_PiS_
.type _Z30__device_stub__Z9kernel_fcPiS_PiS_, @function
_Z30__device_stub__Z9kernel_fcPiS_PiS_:
.LFB2093:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9kernel_fcPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2093:
.size _Z30__device_stub__Z9kernel_fcPiS_PiS_, .-_Z30__device_stub__Z9kernel_fcPiS_PiS_
.globl _Z9kernel_fcPiS_
.type _Z9kernel_fcPiS_, @function
_Z9kernel_fcPiS_:
.LFB2094:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9kernel_fcPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2094:
.size _Z9kernel_fcPiS_, .-_Z9kernel_fcPiS_
.section .rodata.str1.1
.LC4:
.string "thread %d func start\n"
.LC5:
.string "arr %d = "
.LC6:
.string "thread %d func exit\n"
.text
.globl _Z11thread_funcPv
.type _Z11thread_funcPv, @function
_Z11thread_funcPv:
.LFB2067:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movl 36(%rdi), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 32(%rbp), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC1(%rip), %r12
.L38:
movq 0(%rbp), %rax
movl (%rax,%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $40, %rbx
jne .L38
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 32(%rbp), %edi
call cudaSetDevice@PLT
movq 0(%rbp), %rsi
movq 8(%rbp), %rdi
movl $1, %ecx
movl $40, %edx
call cudaMemcpy@PLT
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L39:
movq 16(%rbp), %rsi
movq 24(%rbp), %rdi
movl $2, %ecx
movl $4, %edx
call cudaMemcpy@PLT
movl 36(%rbp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
movq 16(%rbp), %rsi
movq 8(%rbp), %rdi
call _Z30__device_stub__Z9kernel_fcPiS_PiS_
jmp .L39
.cfi_endproc
.LFE2067:
.size _Z11thread_funcPv, .-_Z11thread_funcPv
.section .rodata.str1.1
.LC7:
.string "_Z9kernel_fcPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z9kernel_fcPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <pthread.h>
#define ARR_SIZE 10
#define NUM_DEVICE 2
#define NUM_THR 8
typedef struct {
int *arr;
int *dev_arr;
int *dev_result;
int *result;
int dev_num;
int thr_num;
} cuda_st;
__global__ void kernel_fc(int *dev_arr, int *dev_result)
{
int idx = threadIdx.x;
printf("dev_arr[%d] = %d\n", idx, dev_arr[idx]);
atomicAdd(dev_result, dev_arr[idx]);
}
void *thread_func(void* struc)
{
cuda_st * data = (cuda_st*)struc;
printf("thread %d func start\n", data->thr_num);
printf("arr %d = ", data->dev_num);
for(int i=0; i<10; i++) {
printf("%d ", data->arr[i]);
}
printf("\n");
cudaSetDevice(data->dev_num);
cudaMemcpy(data->dev_arr, data->arr, sizeof(int)*ARR_SIZE, cudaMemcpyHostToDevice);
kernel_fc<<<1,ARR_SIZE>>>(data->dev_arr, data->dev_result);
cudaMemcpy(data->result, data->dev_result, sizeof(int), cudaMemcpyDeviceToHost);
printf("thread %d func exit\n", data->thr_num);
return NULL;
}
int main(void)
{
// Make object
cuda_st cuda[NUM_DEVICE][NUM_THR];
// Make thread
pthread_t pthread[NUM_DEVICE*NUM_THR];
// Host array memory allocation
int *arr[NUM_DEVICE];
for(int i=0; i<NUM_DEVICE; i++) {
arr[i] = (int*)malloc(sizeof(int)*ARR_SIZE);
}
// Fill this host array up with specified data
for(int i=0; i<NUM_DEVICE; i++) {
for(int j=0; j<ARR_SIZE; j++) {
arr[i][j] = i*ARR_SIZE+j;
}
}
// To confirm host array data
for(int i=0; i<NUM_DEVICE; i++) {
printf("arr[%d] = ", i);
for(int j=0; j<ARR_SIZE; j++) {
printf("%d ", arr[i][j]);
}
printf("\n");
}
// Result memory allocation
int *result[NUM_DEVICE];
for(int i=0; i<NUM_DEVICE; i++) {
result[i] = (int*)malloc(sizeof(int));
memset(result[i], 0, sizeof(int));
}
// Device array memory allocation
int *dev_arr[NUM_DEVICE];
for(int i=0; i<NUM_DEVICE; i++) {
cudaSetDevice(i);
cudaMalloc(&dev_arr[i], sizeof(int)*ARR_SIZE);
}
// Device result memory allocation
int *dev_result[NUM_DEVICE];
for(int i=0; i<NUM_DEVICE; i++) {
cudaSetDevice(i);
cudaMalloc(&dev_result[i], sizeof(int));
cudaMemset(dev_result[i], 0, sizeof(int));
}
// Connect these pointers with object
for (int i=0; i<NUM_DEVICE; i++)
for (int j=0; j<NUM_THR; j++) {
cuda[i][j].arr = arr[i];
cuda[i][j].dev_arr = dev_arr[i];
cuda[i][j].result = result[i];
cuda[i][j].dev_result = dev_result[i];
cuda[i][j].dev_num = i;
cuda[i][j].thr_num = j;
}
// Create and excute pthread
for(int i=0; i<NUM_DEVICE; i++)
for (int j=0; j<NUM_THR; j++) {
pthread_create(&pthread[(i*NUM_THR)+j], NULL, thread_func, (void*)&cuda[i][j]);
}
// Join pthread
for(int i=0; i<NUM_DEVICE*NUM_THR; i++) {
pthread_join(pthread[i], NULL);
}
for(int i=0; i<NUM_DEVICE; i++)
for (int j=0; j < NUM_THR; j++) {
printf("result[%d][%d] = %d\n", i,j, (*cuda[i][j].result));
}
cudaDeviceReset();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <pthread.h>
#define ARR_SIZE 10
#define NUM_DEVICE 2
#define NUM_THR 8
typedef struct {
int *arr;
int *dev_arr;
int *dev_result;
int *result;
int dev_num;
int thr_num;
} cuda_st;
__global__ void kernel_fc(int *dev_arr, int *dev_result)
{
int idx = threadIdx.x;
printf("dev_arr[%d] = %d\n", idx, dev_arr[idx]);
atomicAdd(dev_result, dev_arr[idx]);
}
void *thread_func(void* struc)
{
cuda_st * data = (cuda_st*)struc;
printf("thread %d func start\n", data->thr_num);
printf("arr %d = ", data->dev_num);
for(int i=0; i<10; i++) {
printf("%d ", data->arr[i]);
}
printf("\n");
hipSetDevice(data->dev_num);
hipMemcpy(data->dev_arr, data->arr, sizeof(int)*ARR_SIZE, hipMemcpyHostToDevice);
kernel_fc<<<1,ARR_SIZE>>>(data->dev_arr, data->dev_result);
hipMemcpy(data->result, data->dev_result, sizeof(int), hipMemcpyDeviceToHost);
printf("thread %d func exit\n", data->thr_num);
return NULL;
}
int main(void)
{
// Make object
cuda_st cuda[NUM_DEVICE][NUM_THR];
// Make thread
pthread_t pthread[NUM_DEVICE*NUM_THR];
// Host array memory allocation
int *arr[NUM_DEVICE];
for(int i=0; i<NUM_DEVICE; i++) {
arr[i] = (int*)malloc(sizeof(int)*ARR_SIZE);
}
// Fill this host array up with specified data
for(int i=0; i<NUM_DEVICE; i++) {
for(int j=0; j<ARR_SIZE; j++) {
arr[i][j] = i*ARR_SIZE+j;
}
}
// To confirm host array data
for(int i=0; i<NUM_DEVICE; i++) {
printf("arr[%d] = ", i);
for(int j=0; j<ARR_SIZE; j++) {
printf("%d ", arr[i][j]);
}
printf("\n");
}
// Result memory allocation
int *result[NUM_DEVICE];
for(int i=0; i<NUM_DEVICE; i++) {
result[i] = (int*)malloc(sizeof(int));
memset(result[i], 0, sizeof(int));
}
// Device array memory allocation
int *dev_arr[NUM_DEVICE];
for(int i=0; i<NUM_DEVICE; i++) {
hipSetDevice(i);
hipMalloc(&dev_arr[i], sizeof(int)*ARR_SIZE);
}
// Device result memory allocation
int *dev_result[NUM_DEVICE];
for(int i=0; i<NUM_DEVICE; i++) {
hipSetDevice(i);
hipMalloc(&dev_result[i], sizeof(int));
hipMemset(dev_result[i], 0, sizeof(int));
}
// Connect these pointers with object
for (int i=0; i<NUM_DEVICE; i++)
for (int j=0; j<NUM_THR; j++) {
cuda[i][j].arr = arr[i];
cuda[i][j].dev_arr = dev_arr[i];
cuda[i][j].result = result[i];
cuda[i][j].dev_result = dev_result[i];
cuda[i][j].dev_num = i;
cuda[i][j].thr_num = j;
}
// Create and excute pthread
for(int i=0; i<NUM_DEVICE; i++)
for (int j=0; j<NUM_THR; j++) {
pthread_create(&pthread[(i*NUM_THR)+j], NULL, thread_func, (void*)&cuda[i][j]);
}
// Join pthread
for(int i=0; i<NUM_DEVICE*NUM_THR; i++) {
pthread_join(pthread[i], NULL);
}
for(int i=0; i<NUM_DEVICE; i++)
for (int j=0; j < NUM_THR; j++) {
printf("result[%d][%d] = %d\n", i,j, (*cuda[i][j].result));
}
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <pthread.h>
#define ARR_SIZE 10
#define NUM_DEVICE 2
#define NUM_THR 8
typedef struct {
int *arr;
int *dev_arr;
int *dev_result;
int *result;
int dev_num;
int thr_num;
} cuda_st;
__global__ void kernel_fc(int *dev_arr, int *dev_result)
{
int idx = threadIdx.x;
printf("dev_arr[%d] = %d\n", idx, dev_arr[idx]);
atomicAdd(dev_result, dev_arr[idx]);
}
void *thread_func(void* struc)
{
cuda_st * data = (cuda_st*)struc;
printf("thread %d func start\n", data->thr_num);
printf("arr %d = ", data->dev_num);
for(int i=0; i<10; i++) {
printf("%d ", data->arr[i]);
}
printf("\n");
hipSetDevice(data->dev_num);
hipMemcpy(data->dev_arr, data->arr, sizeof(int)*ARR_SIZE, hipMemcpyHostToDevice);
kernel_fc<<<1,ARR_SIZE>>>(data->dev_arr, data->dev_result);
hipMemcpy(data->result, data->dev_result, sizeof(int), hipMemcpyDeviceToHost);
printf("thread %d func exit\n", data->thr_num);
return NULL;
}
int main(void)
{
// Make object
cuda_st cuda[NUM_DEVICE][NUM_THR];
// Make thread
pthread_t pthread[NUM_DEVICE*NUM_THR];
// Host array memory allocation
int *arr[NUM_DEVICE];
for(int i=0; i<NUM_DEVICE; i++) {
arr[i] = (int*)malloc(sizeof(int)*ARR_SIZE);
}
// Fill this host array up with specified data
for(int i=0; i<NUM_DEVICE; i++) {
for(int j=0; j<ARR_SIZE; j++) {
arr[i][j] = i*ARR_SIZE+j;
}
}
// To confirm host array data
for(int i=0; i<NUM_DEVICE; i++) {
printf("arr[%d] = ", i);
for(int j=0; j<ARR_SIZE; j++) {
printf("%d ", arr[i][j]);
}
printf("\n");
}
// Result memory allocation
int *result[NUM_DEVICE];
for(int i=0; i<NUM_DEVICE; i++) {
result[i] = (int*)malloc(sizeof(int));
memset(result[i], 0, sizeof(int));
}
// Device array memory allocation
int *dev_arr[NUM_DEVICE];
for(int i=0; i<NUM_DEVICE; i++) {
hipSetDevice(i);
hipMalloc(&dev_arr[i], sizeof(int)*ARR_SIZE);
}
// Device result memory allocation
int *dev_result[NUM_DEVICE];
for(int i=0; i<NUM_DEVICE; i++) {
hipSetDevice(i);
hipMalloc(&dev_result[i], sizeof(int));
hipMemset(dev_result[i], 0, sizeof(int));
}
// Connect these pointers with object
for (int i=0; i<NUM_DEVICE; i++)
for (int j=0; j<NUM_THR; j++) {
cuda[i][j].arr = arr[i];
cuda[i][j].dev_arr = dev_arr[i];
cuda[i][j].result = result[i];
cuda[i][j].dev_result = dev_result[i];
cuda[i][j].dev_num = i;
cuda[i][j].thr_num = j;
}
// Create and excute pthread
for(int i=0; i<NUM_DEVICE; i++)
for (int j=0; j<NUM_THR; j++) {
pthread_create(&pthread[(i*NUM_THR)+j], NULL, thread_func, (void*)&cuda[i][j]);
}
// Join pthread
for(int i=0; i<NUM_DEVICE*NUM_THR; i++) {
pthread_join(pthread[i], NULL);
}
for(int i=0; i<NUM_DEVICE; i++)
for (int j=0; j < NUM_THR; j++) {
printf("result[%d][%d] = %d\n", i,j, (*cuda[i][j].result));
}
hipDeviceReset();
return 0;
} | .text
.file "multiGpuThread.hip"
.globl _Z24__device_stub__kernel_fcPiS_ # -- Begin function _Z24__device_stub__kernel_fcPiS_
.p2align 4, 0x90
.type _Z24__device_stub__kernel_fcPiS_,@function
_Z24__device_stub__kernel_fcPiS_: # @_Z24__device_stub__kernel_fcPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9kernel_fcPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__kernel_fcPiS_, .Lfunc_end0-_Z24__device_stub__kernel_fcPiS_
.cfi_endproc
# -- End function
.globl _Z11thread_funcPv # -- Begin function _Z11thread_funcPv
.p2align 4, 0x90
.type _Z11thread_funcPv,@function
_Z11thread_funcPv: # @_Z11thread_funcPv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
movl 36(%rdi), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl 32(%rbx), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq (%rbx), %rax
movl (%rax,%r14,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $10, %r14
jne .LBB1_1
# %bb.2:
movl $10, %edi
callq putchar@PLT
movl 32(%rbx), %edi
callq hipSetDevice
movq (%rbx), %rsi
movq 8(%rbx), %rdi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rbx), %rax
movq 16(%rbx), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9kernel_fcPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 16(%rbx), %rsi
movq 24(%rbx), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 36(%rbx), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11thread_funcPv, .Lfunc_end1-_Z11thread_funcPv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $832, %rsp # imm = 0x340
.cfi_def_cfa_offset 880
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl $40, %edi
callq malloc
movq %rax, (%rsp,%rbx,8)
incq %rbx
cmpq $1, %rbx
je .LBB2_1
# %bb.2: # %.preheader94.preheader
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_3: # %.preheader94
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
movq (%rsp,%rcx,8), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_3 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rax,%rsi), %edi
movl %edi, (%rdx,%rsi,4)
incq %rsi
cmpq $10, %rsi
jne .LBB2_4
# %bb.5: # in Loop: Header=BB2_3 Depth=1
leaq 1(%rcx), %rdx
addq $10, %rax
testq %rcx, %rcx
movq %rdx, %rcx
je .LBB2_3
# %bb.6: # %.preheader93.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_7: # %.preheader93
# =>This Loop Header: Depth=1
# Child Loop BB2_8 Depth 2
movl $.L.str.5, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movq (%rsp,%rbx,8), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_8: # Parent Loop BB2_7 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r15,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $10, %r15
jne .LBB2_8
# %bb.9: # in Loop: Header=BB2_7 Depth=1
movl $10, %edi
callq putchar@PLT
leaq 1(%rbx), %rax
testq %rbx, %rbx
movq %rax, %rbx
je .LBB2_7
# %bb.10:
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_11: # =>This Inner Loop Header: Depth=1
movl $4, %edi
callq malloc
movq %rax, 48(%rsp,%rbx,8)
movl $0, (%rax)
incq %rbx
cmpq $1, %rbx
je .LBB2_11
# %bb.12:
leaq 32(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_13: # =>This Inner Loop Header: Depth=1
movl %r14d, %edi
callq hipSetDevice
movl $40, %esi
movq %rbx, %rdi
callq hipMalloc
incq %r14
addq $8, %rbx
cmpq $1, %r14
je .LBB2_13
# %bb.14:
leaq 16(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_15: # =>This Inner Loop Header: Depth=1
movl %r14d, %edi
callq hipSetDevice
movl $4, %esi
movq %rbx, %rdi
callq hipMalloc
movq (%rbx), %rdi
movl $4, %edx
xorl %esi, %esi
callq hipMemset
incq %r14
addq $8, %rbx
cmpq $1, %r14
je .LBB2_15
# %bb.16: # %.preheader91.preheader
leaq 228(%rsp), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_17: # %.preheader91
# =>This Loop Header: Depth=1
# Child Loop BB2_18 Depth 2
movq (%rsp,%rcx,8), %rdx
movq 32(%rsp,%rcx,8), %rsi
movq 48(%rsp,%rcx,8), %rdi
movq 16(%rsp,%rcx,8), %r8
movq %rax, %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB2_18: # Parent Loop BB2_17 Depth=1
# => This Inner Loop Header: Depth=2
movq %rdx, -36(%r9)
movq %rsi, -28(%r9)
movq %rdi, -12(%r9)
movq %r8, -20(%r9)
movl %ecx, -4(%r9)
movl %r10d, (%r9)
incq %r10
addq $40, %r9
cmpq $8, %r10
jne .LBB2_18
# %bb.19: # in Loop: Header=BB2_17 Depth=1
leaq 1(%rcx), %rdx
addq $320, %rax # imm = 0x140
testq %rcx, %rcx
movq %rdx, %rcx
je .LBB2_17
# %bb.20: # %.preheader89.preheader
leaq 192(%rsp), %r14
leaq 64(%rsp), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_21: # %.preheader89
# =>This Loop Header: Depth=1
# Child Loop BB2_22 Depth 2
xorl %r13d, %r13d
movq %r14, %rbx
.p2align 4, 0x90
.LBB2_22: # Parent Loop BB2_21 Depth=1
# => This Inner Loop Header: Depth=2
leaq (%r15,%r13), %rdi
movl $_Z11thread_funcPv, %edx
xorl %esi, %esi
movq %rbx, %rcx
callq pthread_create
addq $40, %rbx
addq $8, %r13
cmpq $64, %r13
jne .LBB2_22
# %bb.23: # in Loop: Header=BB2_21 Depth=1
leaq 1(%r12), %rax
addq $320, %r14 # imm = 0x140
addq $64, %r15
testq %r12, %r12
movq %rax, %r12
je .LBB2_21
# %bb.24: # %.preheader88.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_25: # %.preheader88
# =>This Inner Loop Header: Depth=1
movq 64(%rsp,%rbx,8), %rdi
xorl %esi, %esi
callq pthread_join
incq %rbx
cmpq $16, %rbx
jne .LBB2_25
# %bb.26: # %.preheader.preheader
leaq 216(%rsp), %r15
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_27: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_28 Depth 2
movq %r15, %r12
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_28: # Parent Loop BB2_27 Depth=1
# => This Inner Loop Header: Depth=2
movq (%r12), %rax
movl (%rax), %ecx
movl $.L.str.6, %edi
movl %ebx, %esi
movl %r14d, %edx
xorl %eax, %eax
callq printf
incq %r14
addq $40, %r12
cmpq $8, %r14
jne .LBB2_28
# %bb.29: # in Loop: Header=BB2_27 Depth=1
leaq 1(%rbx), %rax
addq $320, %r15 # imm = 0x140
testq %rbx, %rbx
movq %rax, %rbx
je .LBB2_27
# %bb.30:
callq hipDeviceReset
xorl %eax, %eax
addq $832, %rsp # imm = 0x340
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9kernel_fcPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9kernel_fcPiS_,@object # @_Z9kernel_fcPiS_
.section .rodata,"a",@progbits
.globl _Z9kernel_fcPiS_
.p2align 3, 0x0
_Z9kernel_fcPiS_:
.quad _Z24__device_stub__kernel_fcPiS_
.size _Z9kernel_fcPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "thread %d func start\n"
.size .L.str, 22
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "arr %d = "
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d "
.size .L.str.2, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "thread %d func exit\n"
.size .L.str.4, 21
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "arr[%d] = "
.size .L.str.5, 11
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "result[%d][%d] = %d\n"
.size .L.str.6, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9kernel_fcPiS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__kernel_fcPiS_
.addrsig_sym _Z11thread_funcPv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9kernel_fcPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00182e62_00000000-6_multiGpuThread.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2071:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2071:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "arr[%d] = "
.LC1:
.string "%d "
.LC2:
.string "\n"
.LC3:
.string "result[%d][%d] = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2068:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $856, %rsp
.cfi_def_cfa_offset 912
movq %fs:40, %rax
movq %rax, 840(%rsp)
xorl %eax, %eax
movl $40, %edi
call malloc@PLT
movq %rax, %r14
movq %rax, 16(%rsp)
movl $40, %edi
call malloc@PLT
movq %rax, %r13
movq %rax, 24(%rsp)
movl $0, %eax
.L4:
movl %eax, (%r14,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L4
movl $0, %eax
.L5:
leal 10(%rax), %edx
movl %edx, 0(%r13,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L5
leaq 16(%rsp), %rbp
movl $0, %r15d
leaq .LC1(%rip), %r12
.L7:
movl %r15d, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
.L6:
movq 0(%rbp), %rax
movl (%rax,%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $40, %rbx
jne .L6
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r15d
addq $8, %rbp
cmpl $2, %r15d
jne .L7
movl $4, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, (%rax)
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, (%rax)
movl $0, %edi
call cudaSetDevice@PLT
leaq 32(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $1, %edi
call cudaSetDevice@PLT
leaq 40(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $0, %edi
call cudaSetDevice@PLT
leaq 48(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $4, %edx
movl $0, %esi
movq 48(%rsp), %rdi
call cudaMemset@PLT
movl $1, %edi
call cudaSetDevice@PLT
leaq 56(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $4, %edx
movl $0, %esi
movq 56(%rsp), %rdi
call cudaMemset@PLT
movq 32(%rsp), %rsi
movq 48(%rsp), %rcx
leaq 192(%rsp), %rax
movq %rax, 8(%rsp)
movl $0, %edx
.L8:
movq %r14, (%rax)
movq %rsi, 8(%rax)
movq %rbp, 24(%rax)
movq %rcx, 16(%rax)
movl $0, 32(%rax)
movl %edx, 36(%rax)
addl $1, %edx
addq $40, %rax
cmpl $8, %edx
jne .L8
movq 40(%rsp), %rsi
movq 56(%rsp), %rcx
leaq 512(%rsp), %rbp
movq %rbp, %rax
movl $0, %edx
.L9:
movq %r13, (%rax)
movq %rsi, 8(%rax)
movq %rbx, 24(%rax)
movq %rcx, 16(%rax)
movl $1, 32(%rax)
movl %edx, 36(%rax)
addl $1, %edx
addq $40, %rax
cmpl $8, %edx
jne .L9
leaq 64(%rsp), %rbx
movq 8(%rsp), %r12
leaq 320(%r12), %r15
movq %rbx, %r13
leaq _Z11thread_funcPv(%rip), %r14
.L10:
movq %r12, %rcx
movq %r14, %rdx
movl $0, %esi
movq %r13, %rdi
call pthread_create@PLT
addq $8, %r13
addq $40, %r12
cmpq %r15, %r12
jne .L10
leaq 128(%rsp), %r12
movq 8(%rsp), %r14
addq $640, %r14
leaq _Z11thread_funcPv(%rip), %r13
.L11:
movq %rbp, %rcx
movq %r13, %rdx
movl $0, %esi
movq %r12, %rdi
call pthread_create@PLT
addq $8, %r12
addq $40, %rbp
cmpq %r14, %rbp
jne .L11
leaq 128(%rbx), %rbp
.L12:
movq (%rbx), %rdi
movl $0, %esi
call pthread_join@PLT
addq $8, %rbx
cmpq %rbx, %rbp
jne .L12
leaq 216(%rsp), %rbp
movl $0, %ebx
leaq .LC3(%rip), %r12
.L13:
movq 0(%rbp), %rax
movl (%rax), %r8d
movl %ebx, %ecx
movl $0, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
addq $40, %rbp
cmpl $8, %ebx
jne .L13
leaq 536(%rsp), %rbp
movl $0, %ebx
leaq .LC3(%rip), %r12
.L14:
movq 0(%rbp), %rax
movl (%rax), %r8d
movl %ebx, %ecx
movl $1, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
addq $40, %rbp
cmpl $8, %ebx
jne .L14
call cudaDeviceReset@PLT
movq 840(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $856, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2068:
.size main, .-main
.globl _Z30__device_stub__Z9kernel_fcPiS_PiS_
.type _Z30__device_stub__Z9kernel_fcPiS_PiS_, @function
_Z30__device_stub__Z9kernel_fcPiS_PiS_:
.LFB2093:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9kernel_fcPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2093:
.size _Z30__device_stub__Z9kernel_fcPiS_PiS_, .-_Z30__device_stub__Z9kernel_fcPiS_PiS_
.globl _Z9kernel_fcPiS_
.type _Z9kernel_fcPiS_, @function
_Z9kernel_fcPiS_:
.LFB2094:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9kernel_fcPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2094:
.size _Z9kernel_fcPiS_, .-_Z9kernel_fcPiS_
.section .rodata.str1.1
.LC4:
.string "thread %d func start\n"
.LC5:
.string "arr %d = "
.LC6:
.string "thread %d func exit\n"
.text
.globl _Z11thread_funcPv
.type _Z11thread_funcPv, @function
_Z11thread_funcPv:
.LFB2067:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movl 36(%rdi), %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 32(%rbp), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC1(%rip), %r12
.L38:
movq 0(%rbp), %rax
movl (%rax,%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $40, %rbx
jne .L38
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 32(%rbp), %edi
call cudaSetDevice@PLT
movq 0(%rbp), %rsi
movq 8(%rbp), %rdi
movl $1, %ecx
movl $40, %edx
call cudaMemcpy@PLT
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L39:
movq 16(%rbp), %rsi
movq 24(%rbp), %rdi
movl $2, %ecx
movl $4, %edx
call cudaMemcpy@PLT
movl 36(%rbp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
movq 16(%rbp), %rsi
movq 8(%rbp), %rdi
call _Z30__device_stub__Z9kernel_fcPiS_PiS_
jmp .L39
.cfi_endproc
.LFE2067:
.size _Z11thread_funcPv, .-_Z11thread_funcPv
.section .rodata.str1.1
.LC7:
.string "_Z9kernel_fcPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z9kernel_fcPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "multiGpuThread.hip"
.globl _Z24__device_stub__kernel_fcPiS_ # -- Begin function _Z24__device_stub__kernel_fcPiS_
.p2align 4, 0x90
.type _Z24__device_stub__kernel_fcPiS_,@function
_Z24__device_stub__kernel_fcPiS_: # @_Z24__device_stub__kernel_fcPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9kernel_fcPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__kernel_fcPiS_, .Lfunc_end0-_Z24__device_stub__kernel_fcPiS_
.cfi_endproc
# -- End function
.globl _Z11thread_funcPv # -- Begin function _Z11thread_funcPv
.p2align 4, 0x90
.type _Z11thread_funcPv,@function
_Z11thread_funcPv: # @_Z11thread_funcPv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
movl 36(%rdi), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl 32(%rbx), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq (%rbx), %rax
movl (%rax,%r14,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $10, %r14
jne .LBB1_1
# %bb.2:
movl $10, %edi
callq putchar@PLT
movl 32(%rbx), %edi
callq hipSetDevice
movq (%rbx), %rsi
movq 8(%rbx), %rdi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rbx), %rax
movq 16(%rbx), %rcx
movq %rax, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9kernel_fcPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 16(%rbx), %rsi
movq 24(%rbx), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 36(%rbx), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11thread_funcPv, .Lfunc_end1-_Z11thread_funcPv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $832, %rsp # imm = 0x340
.cfi_def_cfa_offset 880
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl $40, %edi
callq malloc
movq %rax, (%rsp,%rbx,8)
incq %rbx
cmpq $1, %rbx
je .LBB2_1
# %bb.2: # %.preheader94.preheader
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_3: # %.preheader94
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
movq (%rsp,%rcx,8), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_3 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rax,%rsi), %edi
movl %edi, (%rdx,%rsi,4)
incq %rsi
cmpq $10, %rsi
jne .LBB2_4
# %bb.5: # in Loop: Header=BB2_3 Depth=1
leaq 1(%rcx), %rdx
addq $10, %rax
testq %rcx, %rcx
movq %rdx, %rcx
je .LBB2_3
# %bb.6: # %.preheader93.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_7: # %.preheader93
# =>This Loop Header: Depth=1
# Child Loop BB2_8 Depth 2
movl $.L.str.5, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movq (%rsp,%rbx,8), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_8: # Parent Loop BB2_7 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r15,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq $10, %r15
jne .LBB2_8
# %bb.9: # in Loop: Header=BB2_7 Depth=1
movl $10, %edi
callq putchar@PLT
leaq 1(%rbx), %rax
testq %rbx, %rbx
movq %rax, %rbx
je .LBB2_7
# %bb.10:
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_11: # =>This Inner Loop Header: Depth=1
movl $4, %edi
callq malloc
movq %rax, 48(%rsp,%rbx,8)
movl $0, (%rax)
incq %rbx
cmpq $1, %rbx
je .LBB2_11
# %bb.12:
leaq 32(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_13: # =>This Inner Loop Header: Depth=1
movl %r14d, %edi
callq hipSetDevice
movl $40, %esi
movq %rbx, %rdi
callq hipMalloc
incq %r14
addq $8, %rbx
cmpq $1, %r14
je .LBB2_13
# %bb.14:
leaq 16(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_15: # =>This Inner Loop Header: Depth=1
movl %r14d, %edi
callq hipSetDevice
movl $4, %esi
movq %rbx, %rdi
callq hipMalloc
movq (%rbx), %rdi
movl $4, %edx
xorl %esi, %esi
callq hipMemset
incq %r14
addq $8, %rbx
cmpq $1, %r14
je .LBB2_15
# %bb.16: # %.preheader91.preheader
leaq 228(%rsp), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_17: # %.preheader91
# =>This Loop Header: Depth=1
# Child Loop BB2_18 Depth 2
movq (%rsp,%rcx,8), %rdx
movq 32(%rsp,%rcx,8), %rsi
movq 48(%rsp,%rcx,8), %rdi
movq 16(%rsp,%rcx,8), %r8
movq %rax, %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB2_18: # Parent Loop BB2_17 Depth=1
# => This Inner Loop Header: Depth=2
movq %rdx, -36(%r9)
movq %rsi, -28(%r9)
movq %rdi, -12(%r9)
movq %r8, -20(%r9)
movl %ecx, -4(%r9)
movl %r10d, (%r9)
incq %r10
addq $40, %r9
cmpq $8, %r10
jne .LBB2_18
# %bb.19: # in Loop: Header=BB2_17 Depth=1
leaq 1(%rcx), %rdx
addq $320, %rax # imm = 0x140
testq %rcx, %rcx
movq %rdx, %rcx
je .LBB2_17
# %bb.20: # %.preheader89.preheader
leaq 192(%rsp), %r14
leaq 64(%rsp), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_21: # %.preheader89
# =>This Loop Header: Depth=1
# Child Loop BB2_22 Depth 2
xorl %r13d, %r13d
movq %r14, %rbx
.p2align 4, 0x90
.LBB2_22: # Parent Loop BB2_21 Depth=1
# => This Inner Loop Header: Depth=2
leaq (%r15,%r13), %rdi
movl $_Z11thread_funcPv, %edx
xorl %esi, %esi
movq %rbx, %rcx
callq pthread_create
addq $40, %rbx
addq $8, %r13
cmpq $64, %r13
jne .LBB2_22
# %bb.23: # in Loop: Header=BB2_21 Depth=1
leaq 1(%r12), %rax
addq $320, %r14 # imm = 0x140
addq $64, %r15
testq %r12, %r12
movq %rax, %r12
je .LBB2_21
# %bb.24: # %.preheader88.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_25: # %.preheader88
# =>This Inner Loop Header: Depth=1
movq 64(%rsp,%rbx,8), %rdi
xorl %esi, %esi
callq pthread_join
incq %rbx
cmpq $16, %rbx
jne .LBB2_25
# %bb.26: # %.preheader.preheader
leaq 216(%rsp), %r15
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_27: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_28 Depth 2
movq %r15, %r12
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_28: # Parent Loop BB2_27 Depth=1
# => This Inner Loop Header: Depth=2
movq (%r12), %rax
movl (%rax), %ecx
movl $.L.str.6, %edi
movl %ebx, %esi
movl %r14d, %edx
xorl %eax, %eax
callq printf
incq %r14
addq $40, %r12
cmpq $8, %r14
jne .LBB2_28
# %bb.29: # in Loop: Header=BB2_27 Depth=1
leaq 1(%rbx), %rax
addq $320, %r15 # imm = 0x140
testq %rbx, %rbx
movq %rax, %rbx
je .LBB2_27
# %bb.30:
callq hipDeviceReset
xorl %eax, %eax
addq $832, %rsp # imm = 0x340
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9kernel_fcPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9kernel_fcPiS_,@object # @_Z9kernel_fcPiS_
.section .rodata,"a",@progbits
.globl _Z9kernel_fcPiS_
.p2align 3, 0x0
_Z9kernel_fcPiS_:
.quad _Z24__device_stub__kernel_fcPiS_
.size _Z9kernel_fcPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "thread %d func start\n"
.size .L.str, 22
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "arr %d = "
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d "
.size .L.str.2, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "thread %d func exit\n"
.size .L.str.4, 21
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "arr[%d] = "
.size .L.str.5, 11
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "result[%d][%d] = %d\n"
.size .L.str.6, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9kernel_fcPiS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__kernel_fcPiS_
.addrsig_sym _Z11thread_funcPv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9kernel_fcPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //each kernel process one node
__global__ void largeKernel(int *offset, int *col_id, int *large, int sizeLarge, int *color, int currentColor)
{
__shared__ bool set[1];
//get the node from large array
if(blockIdx.x < sizeLarge)
{
set[0]=1;
int node = large[blockIdx.x];
if(color[node]==0)
{
int neighLen = offset[node+1]-offset[node];
for(int i = threadIdx.x; i<neighLen; i=i+blockDim.x)
{
int item = col_id[offset[node]+i];
if(item >= node && color[item]==0)
set[0]=0;
}
__syncthreads();
if(threadIdx.x == 0){
if(set[0] == 1)
color[node]=currentColor;
}
}
}
} | code for sm_80
Function : _Z11largeKernelPiS_S_iS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x001fda0003f06070 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ IMAD.WIDE.U32 R4, R4, R7, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fca00078e0007 */
/*0070*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*0080*/ IMAD.WIDE R2, R0, R7, c[0x0][0x180] ; /* 0x0000600000027625 */
/* 0x004fca00078e0207 */
/*0090*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ HFMA2.MMA R8, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff087435 */
/* 0x000fd400000001ff */
/*00b0*/ PRMT R5, R8, 0x7610, R5 ; /* 0x0000761008057816 */
/* 0x000fca0000000005 */
/*00c0*/ STS.U8 [RZ], R5 ; /* 0x00000005ff007388 */
/* 0x0001e20000000000 */
/*00d0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x004fda0003f05270 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x001fca00078e0207 */
/*0100*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R7, [R4.64+0x4] ; /* 0x0000040404077981 */
/* 0x000ea2000c1e1900 */
/*0120*/ BSSY B0, 0x280 ; /* 0x0000015000007945 */
/* 0x000fe60003800000 */
/*0130*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002100 */
/*0140*/ IMAD.IADD R7, R7, 0x1, -R6 ; /* 0x0000000107077824 */
/* 0x004fca00078e0a06 */
/*0150*/ ISETP.GE.AND P0, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x001fda0003f06270 */
/*0160*/ @P0 BRA 0x270 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R8, RZ, RZ, R10 ; /* 0x000000ffff087224 */
/* 0x000fca00078e000a */
/*0180*/ IADD3 R4, R6, R8, RZ ; /* 0x0000000806047210 */
/* 0x000fe20007ffe0ff */
/*0190*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc800078e00ff */
/*01a0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fcc00078e0209 */
/*01b0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*01c0*/ IADD3 R8, R8, c[0x0][0x0], RZ ; /* 0x0000000008087a10 */
/* 0x000fe20007ffe0ff */
/*01d0*/ BSSY B1, 0x260 ; /* 0x0000008000017945 */
/* 0x000fe60003800000 */
/*01e0*/ ISETP.GE.AND P0, PT, R8, R7, PT ; /* 0x000000070800720c */
/* 0x000fe40003f06270 */
/*01f0*/ ISETP.GE.AND P1, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x004fda0003f26270 */
/*0200*/ @!P1 BRA 0x250 ; /* 0x0000004000009947 */
/* 0x000fea0003800000 */
/*0210*/ IMAD.WIDE R4, R5, R9, c[0x0][0x180] ; /* 0x0000600005047625 */
/* 0x000fcc00078e0209 */
/*0220*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*0230*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x004fda0003f25270 */
/*0240*/ @!P1 STS.U8 [RZ], RZ ; /* 0x000000ffff009388 */
/* 0x000fe40000000000 */
/*0250*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0260*/ @!P0 BRA 0x180 ; /* 0xffffff1000008947 */
/* 0x000fea000383ffff */
/*0270*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0290*/ LDS.U8 R0, [RZ] ; /* 0x00000000ff007984 */
/* 0x000e240000000000 */
/*02a0*/ ISETP.NE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x001fc80003f05270 */
/*02b0*/ ISETP.NE.OR P0, PT, R10, RZ, P0 ; /* 0x000000ff0a00720c */
/* 0x000fda0000705670 */
/*02c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02d0*/ MOV R5, c[0x0][0x188] ; /* 0x0000620000057a02 */
/* 0x000fca0000000f00 */
/*02e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //each kernel process one node
__global__ void largeKernel(int *offset, int *col_id, int *large, int sizeLarge, int *color, int currentColor)
{
__shared__ bool set[1];
//get the node from large array
if(blockIdx.x < sizeLarge)
{
set[0]=1;
int node = large[blockIdx.x];
if(color[node]==0)
{
int neighLen = offset[node+1]-offset[node];
for(int i = threadIdx.x; i<neighLen; i=i+blockDim.x)
{
int item = col_id[offset[node]+i];
if(item >= node && color[item]==0)
set[0]=0;
}
__syncthreads();
if(threadIdx.x == 0){
if(set[0] == 1)
color[node]=currentColor;
}
}
}
} | .file "tmpxft_0013fec5_00000000-6_largeKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z11largeKernelPiS_S_iS_iPiS_S_iS_i
.type _Z39__device_stub__Z11largeKernelPiS_S_iS_iPiS_S_iS_i, @function
_Z39__device_stub__Z11largeKernelPiS_S_iS_iPiS_S_iS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 16(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11largeKernelPiS_S_iS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z11largeKernelPiS_S_iS_iPiS_S_iS_i, .-_Z39__device_stub__Z11largeKernelPiS_S_iS_iPiS_S_iS_i
.globl _Z11largeKernelPiS_S_iS_i
.type _Z11largeKernelPiS_S_iS_i, @function
_Z11largeKernelPiS_S_iS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z11largeKernelPiS_S_iS_iPiS_S_iS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11largeKernelPiS_S_iS_i, .-_Z11largeKernelPiS_S_iS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11largeKernelPiS_S_iS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11largeKernelPiS_S_iS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //each kernel process one node
__global__ void largeKernel(int *offset, int *col_id, int *large, int sizeLarge, int *color, int currentColor)
{
__shared__ bool set[1];
//get the node from large array
if(blockIdx.x < sizeLarge)
{
set[0]=1;
int node = large[blockIdx.x];
if(color[node]==0)
{
int neighLen = offset[node+1]-offset[node];
for(int i = threadIdx.x; i<neighLen; i=i+blockDim.x)
{
int item = col_id[offset[node]+i];
if(item >= node && color[item]==0)
set[0]=0;
}
__syncthreads();
if(threadIdx.x == 0){
if(set[0] == 1)
color[node]=currentColor;
}
}
}
} | #include <hip/hip_runtime.h>
//each kernel process one node
__global__ void largeKernel(int *offset, int *col_id, int *large, int sizeLarge, int *color, int currentColor)
{
__shared__ bool set[1];
//get the node from large array
if(blockIdx.x < sizeLarge)
{
set[0]=1;
int node = large[blockIdx.x];
if(color[node]==0)
{
int neighLen = offset[node+1]-offset[node];
for(int i = threadIdx.x; i<neighLen; i=i+blockDim.x)
{
int item = col_id[offset[node]+i];
if(item >= node && color[item]==0)
set[0]=0;
}
__syncthreads();
if(threadIdx.x == 0){
if(set[0] == 1)
color[node]=currentColor;
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
//each kernel process one node
__global__ void largeKernel(int *offset, int *col_id, int *large, int sizeLarge, int *color, int currentColor)
{
__shared__ bool set[1];
//get the node from large array
if(blockIdx.x < sizeLarge)
{
set[0]=1;
int node = large[blockIdx.x];
if(color[node]==0)
{
int neighLen = offset[node+1]-offset[node];
for(int i = threadIdx.x; i<neighLen; i=i+blockDim.x)
{
int item = col_id[offset[node]+i];
if(item >= node && color[item]==0)
set[0]=0;
}
__syncthreads();
if(threadIdx.x == 0){
if(set[0] == 1)
color[node]=currentColor;
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11largeKernelPiS_S_iS_i
.globl _Z11largeKernelPiS_S_iS_i
.p2align 8
.type _Z11largeKernelPiS_S_iS_i,@function
_Z11largeKernelPiS_S_iS_i:
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_ge_u32 s15, s3
s_cbranch_scc1 .LBB0_2
s_load_b64 s[4:5], s[0:1], 0x10
s_mov_b32 s2, s15
s_mov_b32 s3, 0
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 1
s_lshl_b64 s[6:7], s[2:3], 2
s_load_b64 s[2:3], s[0:1], 0x20
ds_store_b8 v1, v2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s6
s_addc_u32 s5, s5, s7
s_load_b32 s6, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s7, s6, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[6:7], 2
s_add_u32 s4, s2, s8
s_addc_u32 s5, s3, s9
s_load_b32 s7, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s7, 0
s_cbranch_scc0 .LBB0_3
.LBB0_2:
s_endpgm
.LBB0_3:
s_load_b64 s[10:11], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_u32 s8, s10, s8
s_addc_u32 s9, s11, s9
s_load_b64 s[8:9], s[8:9], 0x0
s_waitcnt lgkmcnt(0)
s_sub_i32 s7, s9, s8
s_mov_b32 s9, exec_lo
v_cmpx_gt_i32_e64 s7, v0
s_cbranch_execz .LBB0_9
s_clause 0x1
s_load_b32 s12, s[0:1], 0x3c
s_load_b64 s[10:11], s[0:1], 0x8
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, v0
s_mov_b32 s13, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s12, s12, 0xffff
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s14
v_add_nc_u32_e32 v4, s12, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s7, v4
s_or_b32 s13, vcc_lo, s13
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB0_9
.LBB0_6:
v_add_nc_u32_e32 v1, s8, v4
s_mov_b32 s14, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s10, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s11, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_cmpx_le_i32_e64 s6, v1
s_cbranch_execz .LBB0_5
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 0, v1
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v1, 0
ds_store_b8 v3, v1
s_branch .LBB0_5
.LBB0_9:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s9
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmp_eq_u32_e32 vcc_lo, 0, v0
ds_load_u8 v2, v1
s_waitcnt lgkmcnt(0)
v_cmp_ne_u16_e64 s2, 0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b32 s0, s[0:1], 0x28
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v0, s0
global_store_b32 v1, v0, s[4:5]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11largeKernelPiS_S_iS_i
.amdhsa_group_segment_fixed_size 1
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11largeKernelPiS_S_iS_i, .Lfunc_end0-_Z11largeKernelPiS_S_iS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11largeKernelPiS_S_iS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11largeKernelPiS_S_iS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
//each kernel process one node
__global__ void largeKernel(int *offset, int *col_id, int *large, int sizeLarge, int *color, int currentColor)
{
__shared__ bool set[1];
//get the node from large array
if(blockIdx.x < sizeLarge)
{
set[0]=1;
int node = large[blockIdx.x];
if(color[node]==0)
{
int neighLen = offset[node+1]-offset[node];
for(int i = threadIdx.x; i<neighLen; i=i+blockDim.x)
{
int item = col_id[offset[node]+i];
if(item >= node && color[item]==0)
set[0]=0;
}
__syncthreads();
if(threadIdx.x == 0){
if(set[0] == 1)
color[node]=currentColor;
}
}
}
} | .text
.file "largeKernel.hip"
.globl _Z26__device_stub__largeKernelPiS_S_iS_i # -- Begin function _Z26__device_stub__largeKernelPiS_S_iS_i
.p2align 4, 0x90
.type _Z26__device_stub__largeKernelPiS_S_iS_i,@function
_Z26__device_stub__largeKernelPiS_S_iS_i: # @_Z26__device_stub__largeKernelPiS_S_iS_i
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 64(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11largeKernelPiS_S_iS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z26__device_stub__largeKernelPiS_S_iS_i, .Lfunc_end0-_Z26__device_stub__largeKernelPiS_S_iS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11largeKernelPiS_S_iS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11largeKernelPiS_S_iS_i,@object # @_Z11largeKernelPiS_S_iS_i
.section .rodata,"a",@progbits
.globl _Z11largeKernelPiS_S_iS_i
.p2align 3, 0x0
_Z11largeKernelPiS_S_iS_i:
.quad _Z26__device_stub__largeKernelPiS_S_iS_i
.size _Z11largeKernelPiS_S_iS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11largeKernelPiS_S_iS_i"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__largeKernelPiS_S_iS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11largeKernelPiS_S_iS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11largeKernelPiS_S_iS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x001fda0003f06070 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ IMAD.WIDE.U32 R4, R4, R7, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fca00078e0007 */
/*0070*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*0080*/ IMAD.WIDE R2, R0, R7, c[0x0][0x180] ; /* 0x0000600000027625 */
/* 0x004fca00078e0207 */
/*0090*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ HFMA2.MMA R8, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff087435 */
/* 0x000fd400000001ff */
/*00b0*/ PRMT R5, R8, 0x7610, R5 ; /* 0x0000761008057816 */
/* 0x000fca0000000005 */
/*00c0*/ STS.U8 [RZ], R5 ; /* 0x00000005ff007388 */
/* 0x0001e20000000000 */
/*00d0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x004fda0003f05270 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x001fca00078e0207 */
/*0100*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R7, [R4.64+0x4] ; /* 0x0000040404077981 */
/* 0x000ea2000c1e1900 */
/*0120*/ BSSY B0, 0x280 ; /* 0x0000015000007945 */
/* 0x000fe60003800000 */
/*0130*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002100 */
/*0140*/ IMAD.IADD R7, R7, 0x1, -R6 ; /* 0x0000000107077824 */
/* 0x004fca00078e0a06 */
/*0150*/ ISETP.GE.AND P0, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x001fda0003f06270 */
/*0160*/ @P0 BRA 0x270 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R8, RZ, RZ, R10 ; /* 0x000000ffff087224 */
/* 0x000fca00078e000a */
/*0180*/ IADD3 R4, R6, R8, RZ ; /* 0x0000000806047210 */
/* 0x000fe20007ffe0ff */
/*0190*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc800078e00ff */
/*01a0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fcc00078e0209 */
/*01b0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*01c0*/ IADD3 R8, R8, c[0x0][0x0], RZ ; /* 0x0000000008087a10 */
/* 0x000fe20007ffe0ff */
/*01d0*/ BSSY B1, 0x260 ; /* 0x0000008000017945 */
/* 0x000fe60003800000 */
/*01e0*/ ISETP.GE.AND P0, PT, R8, R7, PT ; /* 0x000000070800720c */
/* 0x000fe40003f06270 */
/*01f0*/ ISETP.GE.AND P1, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x004fda0003f26270 */
/*0200*/ @!P1 BRA 0x250 ; /* 0x0000004000009947 */
/* 0x000fea0003800000 */
/*0210*/ IMAD.WIDE R4, R5, R9, c[0x0][0x180] ; /* 0x0000600005047625 */
/* 0x000fcc00078e0209 */
/*0220*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*0230*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x004fda0003f25270 */
/*0240*/ @!P1 STS.U8 [RZ], RZ ; /* 0x000000ffff009388 */
/* 0x000fe40000000000 */
/*0250*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0260*/ @!P0 BRA 0x180 ; /* 0xffffff1000008947 */
/* 0x000fea000383ffff */
/*0270*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0290*/ LDS.U8 R0, [RZ] ; /* 0x00000000ff007984 */
/* 0x000e240000000000 */
/*02a0*/ ISETP.NE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x001fc80003f05270 */
/*02b0*/ ISETP.NE.OR P0, PT, R10, RZ, P0 ; /* 0x000000ff0a00720c */
/* 0x000fda0000705670 */
/*02c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02d0*/ MOV R5, c[0x0][0x188] ; /* 0x0000620000057a02 */
/* 0x000fca0000000f00 */
/*02e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11largeKernelPiS_S_iS_i
.globl _Z11largeKernelPiS_S_iS_i
.p2align 8
.type _Z11largeKernelPiS_S_iS_i,@function
_Z11largeKernelPiS_S_iS_i:
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_ge_u32 s15, s3
s_cbranch_scc1 .LBB0_2
s_load_b64 s[4:5], s[0:1], 0x10
s_mov_b32 s2, s15
s_mov_b32 s3, 0
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 1
s_lshl_b64 s[6:7], s[2:3], 2
s_load_b64 s[2:3], s[0:1], 0x20
ds_store_b8 v1, v2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s6
s_addc_u32 s5, s5, s7
s_load_b32 s6, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s7, s6, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[6:7], 2
s_add_u32 s4, s2, s8
s_addc_u32 s5, s3, s9
s_load_b32 s7, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s7, 0
s_cbranch_scc0 .LBB0_3
.LBB0_2:
s_endpgm
.LBB0_3:
s_load_b64 s[10:11], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_u32 s8, s10, s8
s_addc_u32 s9, s11, s9
s_load_b64 s[8:9], s[8:9], 0x0
s_waitcnt lgkmcnt(0)
s_sub_i32 s7, s9, s8
s_mov_b32 s9, exec_lo
v_cmpx_gt_i32_e64 s7, v0
s_cbranch_execz .LBB0_9
s_clause 0x1
s_load_b32 s12, s[0:1], 0x3c
s_load_b64 s[10:11], s[0:1], 0x8
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, v0
s_mov_b32 s13, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s12, s12, 0xffff
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s14
v_add_nc_u32_e32 v4, s12, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s7, v4
s_or_b32 s13, vcc_lo, s13
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB0_9
.LBB0_6:
v_add_nc_u32_e32 v1, s8, v4
s_mov_b32 s14, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s10, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s11, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_cmpx_le_i32_e64 s6, v1
s_cbranch_execz .LBB0_5
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 0, v1
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v1, 0
ds_store_b8 v3, v1
s_branch .LBB0_5
.LBB0_9:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s9
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmp_eq_u32_e32 vcc_lo, 0, v0
ds_load_u8 v2, v1
s_waitcnt lgkmcnt(0)
v_cmp_ne_u16_e64 s2, 0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b32 s0, s[0:1], 0x28
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v0, s0
global_store_b32 v1, v0, s[4:5]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11largeKernelPiS_S_iS_i
.amdhsa_group_segment_fixed_size 1
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11largeKernelPiS_S_iS_i, .Lfunc_end0-_Z11largeKernelPiS_S_iS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11largeKernelPiS_S_iS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11largeKernelPiS_S_iS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013fec5_00000000-6_largeKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z11largeKernelPiS_S_iS_iPiS_S_iS_i
.type _Z39__device_stub__Z11largeKernelPiS_S_iS_iPiS_S_iS_i, @function
_Z39__device_stub__Z11largeKernelPiS_S_iS_iPiS_S_iS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 16(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11largeKernelPiS_S_iS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z11largeKernelPiS_S_iS_iPiS_S_iS_i, .-_Z39__device_stub__Z11largeKernelPiS_S_iS_iPiS_S_iS_i
.globl _Z11largeKernelPiS_S_iS_i
.type _Z11largeKernelPiS_S_iS_i, @function
_Z11largeKernelPiS_S_iS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z11largeKernelPiS_S_iS_iPiS_S_iS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11largeKernelPiS_S_iS_i, .-_Z11largeKernelPiS_S_iS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11largeKernelPiS_S_iS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11largeKernelPiS_S_iS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "largeKernel.hip"
.globl _Z26__device_stub__largeKernelPiS_S_iS_i # -- Begin function _Z26__device_stub__largeKernelPiS_S_iS_i
.p2align 4, 0x90
.type _Z26__device_stub__largeKernelPiS_S_iS_i,@function
_Z26__device_stub__largeKernelPiS_S_iS_i: # @_Z26__device_stub__largeKernelPiS_S_iS_i
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 64(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11largeKernelPiS_S_iS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z26__device_stub__largeKernelPiS_S_iS_i, .Lfunc_end0-_Z26__device_stub__largeKernelPiS_S_iS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11largeKernelPiS_S_iS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11largeKernelPiS_S_iS_i,@object # @_Z11largeKernelPiS_S_iS_i
.section .rodata,"a",@progbits
.globl _Z11largeKernelPiS_S_iS_i
.p2align 3, 0x0
_Z11largeKernelPiS_S_iS_i:
.quad _Z26__device_stub__largeKernelPiS_S_iS_i
.size _Z11largeKernelPiS_S_iS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11largeKernelPiS_S_iS_i"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__largeKernelPiS_S_iS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11largeKernelPiS_S_iS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Taken from the NVIDIA "2_Graphics\simpleGL" sample:
// A kernel that modifies the z-coordinates of a rectangular
// grid of vertices, based on a time value, so that they
// form an animated sine wave
extern "C"
__global__ void simple_vbo_kernel(
float4 *pos, unsigned int width, unsigned int height, float time)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
// calculate uv coordinates
float u = x / (float) width;
float v = y / (float) height;
u = u*2.0f - 1.0f;
v = v*2.0f - 1.0f;
// calculate simple sine wave pattern
float freq = 4.0f;
float w = sinf(u*freq + time) * cosf(v*freq + time) * 0.5f;
// write output vertex
pos[y*width+x] = make_float4(u, w, v, 1.0f);
} | .file "tmpxft_000dc745_00000000-6_JCudaDriverSimpleGLKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z17simple_vbo_kernelP6float4jjfP6float4jjf
.type _Z46__device_stub__Z17simple_vbo_kernelP6float4jjfP6float4jjf, @function
_Z46__device_stub__Z17simple_vbo_kernelP6float4jjfP6float4jjf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq simple_vbo_kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z17simple_vbo_kernelP6float4jjfP6float4jjf, .-_Z46__device_stub__Z17simple_vbo_kernelP6float4jjfP6float4jjf
.globl simple_vbo_kernel
.type simple_vbo_kernel, @function
simple_vbo_kernel:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z17simple_vbo_kernelP6float4jjfP6float4jjf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size simple_vbo_kernel, .-simple_vbo_kernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "simple_vbo_kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq simple_vbo_kernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Taken from the NVIDIA "2_Graphics\simpleGL" sample:
// A kernel that modifies the z-coordinates of a rectangular
// grid of vertices, based on a time value, so that they
// form an animated sine wave
extern "C"
__global__ void simple_vbo_kernel(
float4 *pos, unsigned int width, unsigned int height, float time)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
// calculate uv coordinates
float u = x / (float) width;
float v = y / (float) height;
u = u*2.0f - 1.0f;
v = v*2.0f - 1.0f;
// calculate simple sine wave pattern
float freq = 4.0f;
float w = sinf(u*freq + time) * cosf(v*freq + time) * 0.5f;
// write output vertex
pos[y*width+x] = make_float4(u, w, v, 1.0f);
} | #include <hip/hip_runtime.h>
// Taken from the NVIDIA "2_Graphics\simpleGL" sample:
// A kernel that modifies the z-coordinates of a rectangular
// grid of vertices, based on a time value, so that they
// form an animated sine wave
extern "C"
__global__ void simple_vbo_kernel(
float4 *pos, unsigned int width, unsigned int height, float time)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
// calculate uv coordinates
float u = x / (float) width;
float v = y / (float) height;
u = u*2.0f - 1.0f;
v = v*2.0f - 1.0f;
// calculate simple sine wave pattern
float freq = 4.0f;
float w = sinf(u*freq + time) * cosf(v*freq + time) * 0.5f;
// write output vertex
pos[y*width+x] = make_float4(u, w, v, 1.0f);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// Taken from the NVIDIA "2_Graphics\simpleGL" sample:
// A kernel that modifies the z-coordinates of a rectangular
// grid of vertices, based on a time value, so that they
// form an animated sine wave
extern "C"
__global__ void simple_vbo_kernel(
float4 *pos, unsigned int width, unsigned int height, float time)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
// calculate uv coordinates
float u = x / (float) width;
float v = y / (float) height;
u = u*2.0f - 1.0f;
v = v*2.0f - 1.0f;
// calculate simple sine wave pattern
float freq = 4.0f;
float w = sinf(u*freq + time) * cosf(v*freq + time) * 0.5f;
// write output vertex
pos[y*width+x] = make_float4(u, w, v, 1.0f);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected simple_vbo_kernel
.globl simple_vbo_kernel
.p2align 8
.type simple_vbo_kernel,@function
simple_vbo_kernel:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x8
v_and_b32_e32 v1, 0x3ff, v0
s_load_b32 s5, s[0:1], 0x10
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s14, s2, v[1:2]
v_cvt_f32_u32_e32 v1, s4
v_cvt_f32_u32_e32 v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v4, null, v1, v1, v3
v_div_scale_f32 v7, vcc_lo, v3, v1, v3
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_mul_f32_e32 v6, v7, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v6, v7
v_fmac_f32_e32 v6, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v6, v7
v_div_fmas_f32 v4, v4, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v1, v4, v1, v3
v_fma_f32 v1, v1, 2.0, -1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, v1, 4.0, s5
v_and_b32_e32 v7, 0x7fffffff, v6
v_cmpx_ngt_f32_e64 0x48000000, |v6|
s_xor_b32 s7, exec_lo, s3
s_cbranch_execz .LBB0_2
s_mov_b32 s2, 0x7fffff
v_mov_b32_e32 v5, 0
v_and_or_b32 v15, v7, s2, 0x800000
v_lshrrev_b32_e32 v12, 23, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, v15, 0xfe5163ab, 0
v_add_nc_u32_e32 v13, 0xffffff88, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_u32_e32 vcc_lo, 63, v13
v_mad_u64_u32 v[8:9], null, v15, 0x3c439041, v[4:5]
v_cndmask_b32_e64 v14, 0, 0xffffffc0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v4, v9
v_mad_u64_u32 v[9:10], null, v15, 0xdb629599, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v3, v9, v3 :: v_dual_add_nc_u32 v14, v14, v13
v_mov_b32_e32 v4, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s2, 31, v14
v_mad_u64_u32 v[10:11], null, v15, 0xf534ddc0, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v16, 0, 0xffffffe0, s2
v_add_nc_u32_e32 v16, v16, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mov_b32_e32 v4, v11
v_cndmask_b32_e32 v8, v10, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_u32_e64 s3, 31, v16
v_mad_u64_u32 v[11:12], null, v15, 0xfc2757d1, v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v8, v3, s2
v_mov_b32_e32 v4, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[12:13], null, v15, 0x4e441529, v[4:5]
v_mov_b32_e32 v4, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[13:14], null, v15, 0xa2f9836e, v[4:5]
v_cndmask_b32_e64 v4, 0, 0xffffffe0, s3
v_cndmask_b32_e32 v5, v12, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_dual_cndmask_b32 v13, v13, v11 :: v_dual_add_nc_u32 v4, v4, v16
v_dual_cndmask_b32 v12, v14, v12 :: v_dual_cndmask_b32 v11, v11, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e32 vcc_lo, 0, v4
v_cndmask_b32_e64 v10, v13, v5, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v12, v12, v13, s2
v_cndmask_b32_e64 v5, v5, v11, s2
v_sub_nc_u32_e32 v13, 32, v4
v_cndmask_b32_e64 v11, v11, v8, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v12, v12, v10, s3
v_cndmask_b32_e64 v10, v10, v5, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v5, v5, v11, s3
v_cndmask_b32_e64 v3, v11, v3, s3
v_alignbit_b32 v14, v12, v10, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_alignbit_b32 v9, v10, v5, v13
v_cndmask_b32_e32 v4, v14, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v12, v5, v3, v13
v_cndmask_b32_e32 v8, v9, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_bfe_u32 v9, v4, 29, 1
v_cndmask_b32_e32 v5, v12, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v10, v4, v8, 30
v_sub_nc_u32_e32 v11, 0, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_alignbit_b32 v8, v8, v5, 30
v_alignbit_b32 v3, v5, v3, 30
v_xor_b32_e32 v10, v10, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v5, v8, v11
v_xor_b32_e32 v3, v3, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_clz_i32_u32_e32 v12, v10
v_min_u32_e32 v12, 32, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v8, 31, v12
v_lshlrev_b32_e32 v14, 23, v12
v_alignbit_b32 v10, v10, v5, v8
v_alignbit_b32 v3, v5, v3, v8
v_lshrrev_b32_e32 v8, 29, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_alignbit_b32 v5, v10, v3, 9
v_lshlrev_b32_e32 v8, 31, v8
v_lshrrev_b32_e32 v10, 9, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_clz_i32_u32_e32 v11, v5
v_or_b32_e32 v13, 0.5, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_min_u32_e32 v11, 32, v11
v_sub_nc_u32_e32 v13, v13, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v15, 31, v11
v_alignbit_b32 v3, v5, v3, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_or_b32_e32 v5, v10, v13
v_add_lshl_u32 v10, v11, v12, 23
v_lshrrev_b32_e32 v3, 9, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v11, 0x3fc90fda, v5
v_sub_nc_u32_e32 v3, v3, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v10, v5, 0x3fc90fda, -v11
v_add_nc_u32_e32 v3, 0x33000000, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmamk_f32 v5, v5, 0x33a22168, v10
v_or_b32_e32 v3, v3, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, 0x3fc90fda, v3
v_lshrrev_b32_e32 v3, 30, v4
v_dual_add_f32 v8, v11, v5 :: v_dual_add_nc_u32 v9, v9, v3
.LBB0_2:
s_or_saveexec_b32 s3, s7
s_lshr_b32 s2, s6, 16
s_xor_b32 exec_lo, exec_lo, s3
v_mul_f32_e64 v3, 0x3f22f983, |v6|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v3, v3
v_fma_f32 v4, v3, 0xbfc90fda, |v6|
v_cvt_i32_f32_e32 v9, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v4, v3, 0xb3a22168, v4
v_fmamk_f32 v8, v3, 0xa7c234c4, v4
s_or_b32 exec_lo, exec_lo, s3
s_load_b32 s3, s[0:1], 0xc
v_bfe_u32 v0, v0, 10, 10
s_and_b32 s2, 0xffff, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v0, v4
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v3, s3
s_mov_b32 s3, exec_lo
v_div_scale_f32 v5, null, v3, v3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v10, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v11, -v5, v10, 1.0
v_fmac_f32_e32 v10, v11, v10
v_div_scale_f32 v11, vcc_lo, v0, v3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v12, v11, v10
v_fma_f32 v13, -v5, v12, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v12, v13, v10
v_fma_f32 v5, -v5, v12, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v5, v5, v10, v12
v_div_fixup_f32 v0, v5, v3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, v0, 2.0, -1.0
v_fma_f32 v0, v3, 4.0, s5
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ngt_f32_e64 0x48000000, |v0|
s_xor_b32 s5, exec_lo, s3
s_cbranch_execz .LBB0_6
v_dual_mov_b32 v12, 0 :: v_dual_and_b32 v5, 0x7fffffff, v0
s_mov_b32 s2, 0x7fffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_and_or_b32 v20, v5, s2, 0x800000
v_lshrrev_b32_e32 v5, 23, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[10:11], null, v20, 0xfe5163ab, 0
v_add_nc_u32_e32 v5, 0xffffff88, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_u32_e32 vcc_lo, 63, v5
v_mad_u64_u32 v[13:14], null, v20, 0x3c439041, v[11:12]
v_cndmask_b32_e64 v18, 0, 0xffffffc0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v11, v14
v_add_nc_u32_e32 v5, v18, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[14:15], null, v20, 0xdb629599, v[11:12]
v_cmp_lt_u32_e64 s2, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v19, 0, 0xffffffe0, s2
v_dual_mov_b32 v11, v15 :: v_dual_cndmask_b32 v10, v14, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, v19, v5
v_mad_u64_u32 v[15:16], null, v20, 0xf534ddc0, v[11:12]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s3, 31, v5
v_mov_b32_e32 v11, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[16:17], null, v20, 0xfc2757d1, v[11:12]
v_mov_b32_e32 v11, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[17:18], null, v20, 0x4e441529, v[11:12]
v_mov_b32_e32 v11, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[18:19], null, v20, 0xa2f9836e, v[11:12]
v_cndmask_b32_e64 v11, 0, 0xffffffe0, s3
v_dual_cndmask_b32 v12, v17, v15 :: v_dual_add_nc_u32 v5, v11, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v18, v18, v16 :: v_dual_cndmask_b32 v17, v19, v17
v_dual_cndmask_b32 v16, v16, v14 :: v_dual_cndmask_b32 v11, v15, v13
v_cmp_eq_u32_e32 vcc_lo, 0, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v13, v18, v12, s2
v_cndmask_b32_e64 v15, v17, v18, s2
s_delay_alu instid0(VALU_DEP_4)
v_cndmask_b32_e64 v12, v12, v16, s2
v_sub_nc_u32_e32 v17, 32, v5
v_cndmask_b32_e64 v16, v16, v11, s2
v_cndmask_b32_e64 v10, v11, v10, s2
v_cndmask_b32_e64 v15, v15, v13, s3
v_cndmask_b32_e64 v13, v13, v12, s3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v12, v12, v16, s3
v_cndmask_b32_e64 v10, v16, v10, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v18, v15, v13, v17
v_alignbit_b32 v14, v13, v12, v17
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v16, v12, v10, v17
v_cndmask_b32_e32 v5, v18, v15, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v11, v14, v13 :: v_dual_cndmask_b32 v12, v16, v12
v_bfe_u32 v13, v5, 29, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v14, v5, v11, 30
v_alignbit_b32 v11, v11, v12, 30
v_alignbit_b32 v10, v12, v10, 30
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v15, 0, v13
v_xor_b32_e32 v14, v14, v15
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor_b32_e32 v11, v11, v15
v_xor_b32_e32 v10, v10, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_clz_i32_u32_e32 v16, v14
v_min_u32_e32 v16, 32, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v12, 31, v16
v_lshlrev_b32_e32 v18, 23, v16
v_alignbit_b32 v14, v14, v11, v12
v_alignbit_b32 v10, v11, v10, v12
v_lshrrev_b32_e32 v12, 29, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_alignbit_b32 v11, v14, v10, 9
v_lshlrev_b32_e32 v12, 31, v12
v_lshrrev_b32_e32 v14, 9, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_clz_i32_u32_e32 v15, v11
v_or_b32_e32 v17, 0.5, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_min_u32_e32 v15, 32, v15
v_sub_nc_u32_e32 v17, v17, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v19, 31, v15
v_alignbit_b32 v10, v11, v10, v19
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_or_b32_e32 v11, v14, v17
v_add_lshl_u32 v14, v15, v16, 23
v_lshrrev_b32_e32 v10, 9, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v15, 0x3fc90fda, v11
v_sub_nc_u32_e32 v10, v10, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v14, v11, 0x3fc90fda, -v15
v_add_nc_u32_e32 v10, 0x33000000, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmamk_f32 v11, v11, 0x33a22168, v14
v_or_b32_e32 v10, v10, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v11, 0x3fc90fda, v10
v_lshrrev_b32_e32 v10, 30, v5
v_dual_add_f32 v5, v15, v11 :: v_dual_add_nc_u32 v10, v13, v10
.LBB0_6:
s_and_not1_saveexec_b32 s2, s5
v_mul_f32_e64 v5, 0x3f22f983, |v0|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v10, v5
v_fma_f32 v5, v10, 0xbfc90fda, |v0|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v5, v10, 0xb3a22168, v5
v_fmamk_f32 v5, v10, 0xa7c234c4, v5
v_cvt_i32_f32_e32 v10, v10
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_dual_mul_f32 v11, v8, v8 :: v_dual_mul_f32 v12, v5, v5
s_mov_b32 s2, 0xb94c1982
s_mov_b32 s3, 0x37d75334
v_xor_b32_e32 v7, v7, v6
v_dual_fmaak_f32 v13, s2, v11, 0x3c0881c4 :: v_dual_lshlrev_b32 v16, 30, v9
v_dual_fmaak_f32 v14, s3, v11, 0xbab64f3b :: v_dual_fmaak_f32 v17, s3, v12, 0xbab64f3b
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmaak_f32 v13, v11, v13, 0xbe2aaa9d
v_dual_fmaak_f32 v14, v11, v14, 0x3d2aabf7 :: v_dual_and_b32 v9, 1, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmaak_f32 v17, v12, v17, 0x3d2aabf7
v_dual_mul_f32 v13, v11, v13 :: v_dual_and_b32 v16, 0x80000000, v16
v_fmaak_f32 v15, s2, v12, 0x3c0881c4
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_fmaak_f32 v14, v11, v14, 0xbf000004
v_cmp_eq_u32_e32 vcc_lo, 0, v9
v_fmaak_f32 v17, v12, v17, 0xbf000004
v_dual_fmac_f32 v8, v8, v13 :: v_dual_and_b32 v13, 1, v10
v_fma_f32 v11, v11, v14, 1.0
v_dual_fmaak_f32 v15, v12, v15, 0xbe2aaa9d :: v_dual_lshlrev_b32 v10, 30, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_dual_cndmask_b32 v8, v11, v8 :: v_dual_mul_f32 v15, v12, v15
v_fma_f32 v12, v12, v17, 1.0
v_cmp_eq_u32_e32 vcc_lo, 0, v13
v_and_b32_e32 v9, 0x80000000, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_xor3_b32 v7, v7, v16, v8
v_fmac_f32_e32 v5, v5, v15
v_cndmask_b32_e64 v5, -v5, v12, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v6, 0x1f8
s_delay_alu instid0(VALU_DEP_2)
v_xor_b32_e32 v8, v9, v5
v_mad_u64_u32 v[5:6], null, v4, s4, v[2:3]
v_cndmask_b32_e32 v7, 0x7fc00000, v7, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v0, 0x1f8
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, 1.0
v_cndmask_b32_e32 v0, 0x7fc00000, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 4, v[5:6]
v_mul_f32_e32 v0, v7, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_mul_f32_e32 v2, 0.5, v0
global_store_b128 v[5:6], v[1:4], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel simple_vbo_kernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size simple_vbo_kernel, .Lfunc_end0-simple_vbo_kernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: simple_vbo_kernel
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: simple_vbo_kernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// Taken from the NVIDIA "2_Graphics\simpleGL" sample:
// A kernel that modifies the z-coordinates of a rectangular
// grid of vertices, based on a time value, so that they
// form an animated sine wave
extern "C"
__global__ void simple_vbo_kernel(
float4 *pos, unsigned int width, unsigned int height, float time)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
// calculate uv coordinates
float u = x / (float) width;
float v = y / (float) height;
u = u*2.0f - 1.0f;
v = v*2.0f - 1.0f;
// calculate simple sine wave pattern
float freq = 4.0f;
float w = sinf(u*freq + time) * cosf(v*freq + time) * 0.5f;
// write output vertex
pos[y*width+x] = make_float4(u, w, v, 1.0f);
} | .text
.file "JCudaDriverSimpleGLKernel.hip"
.globl __device_stub__simple_vbo_kernel # -- Begin function __device_stub__simple_vbo_kernel
.p2align 4, 0x90
.type __device_stub__simple_vbo_kernel,@function
__device_stub__simple_vbo_kernel: # @__device_stub__simple_vbo_kernel
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movss %xmm0, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $simple_vbo_kernel, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__simple_vbo_kernel, .Lfunc_end0-__device_stub__simple_vbo_kernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $simple_vbo_kernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type simple_vbo_kernel,@object # @simple_vbo_kernel
.section .rodata,"a",@progbits
.globl simple_vbo_kernel
.p2align 3, 0x0
simple_vbo_kernel:
.quad __device_stub__simple_vbo_kernel
.size simple_vbo_kernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "simple_vbo_kernel"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__simple_vbo_kernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym simple_vbo_kernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000dc745_00000000-6_JCudaDriverSimpleGLKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z17simple_vbo_kernelP6float4jjfP6float4jjf
.type _Z46__device_stub__Z17simple_vbo_kernelP6float4jjfP6float4jjf, @function
_Z46__device_stub__Z17simple_vbo_kernelP6float4jjfP6float4jjf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq simple_vbo_kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z17simple_vbo_kernelP6float4jjfP6float4jjf, .-_Z46__device_stub__Z17simple_vbo_kernelP6float4jjfP6float4jjf
.globl simple_vbo_kernel
.type simple_vbo_kernel, @function
simple_vbo_kernel:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z17simple_vbo_kernelP6float4jjfP6float4jjf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size simple_vbo_kernel, .-simple_vbo_kernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "simple_vbo_kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq simple_vbo_kernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "JCudaDriverSimpleGLKernel.hip"
.globl __device_stub__simple_vbo_kernel # -- Begin function __device_stub__simple_vbo_kernel
.p2align 4, 0x90
.type __device_stub__simple_vbo_kernel,@function
__device_stub__simple_vbo_kernel: # @__device_stub__simple_vbo_kernel
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movss %xmm0, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $simple_vbo_kernel, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__simple_vbo_kernel, .Lfunc_end0-__device_stub__simple_vbo_kernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $simple_vbo_kernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type simple_vbo_kernel,@object # @simple_vbo_kernel
.section .rodata,"a",@progbits
.globl simple_vbo_kernel
.p2align 3, 0x0
simple_vbo_kernel:
.quad __device_stub__simple_vbo_kernel
.size simple_vbo_kernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "simple_vbo_kernel"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__simple_vbo_kernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym simple_vbo_kernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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