system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void convolution1d_tiles_constant_kernel(int *In, int *Out){
unsigned int index = blockIdx.x * blockDim.x + threadIdx.x; // Index 1d iterator.
__shared__ int Tile[TILE_SIZE + Mask_size - 1];
int n = Mask_size/2;
int halo_left_index = (blockIdx.x - 1 ) * blockDim.x + threadIdx.x;
if (threadIdx.x >= blockDim.x - n ){
Tile[threadIdx.x - (blockDim.x - n )] = (halo_left_index < 0) ? 0 : In[halo_left_index];
}
if(index<N_elements){Tile[n + threadIdx.x] = In[index];
}else{Tile[n + threadIdx.x] = 0;}
int halo_right_index = (blockIdx.x + 1 ) * blockDim.x + threadIdx.x;
if (threadIdx.x < n) {
Tile[n + blockDim.x + threadIdx.x]= (halo_right_index >= N_elements) ? 0 : In[halo_right_index];
}
__syncthreads();
int Value = 0;
for (unsigned int j = 0; j < Mask_size; j ++) {
Value += Tile[threadIdx.x + j] * Global_Mask[j];
}
Out[index] = Value;
} | code for sm_80
Function : _Z35convolution1d_tiles_constant_kernelPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0x170 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*0050*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e640000002500 */
/*0060*/ IADD3 R3, R9, -0x1, RZ ; /* 0xffffffff09037810 */
/* 0x000fc80007ffe0ff */
/*0070*/ ISETP.GE.U32.AND P0, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x001fe20003f06070 */
/*0080*/ IMAD R2, R0.reuse, R9, -c[0x0][0x0] ; /* 0x8000000000027624 */
/* 0x042fe400078e0209 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x000fc600078e0207 */
/*00a0*/ IADD3 R4, R2, R7, RZ ; /* 0x0000000702047210 */
/* 0x000fce0007ffe0ff */
/*00b0*/ @!P0 BRA 0x160 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*00c0*/ ISETP.GE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f06270 */
/*00d0*/ BSSY B1, 0x150 ; /* 0x0000007000017945 */
/* 0x000fe20003800000 */
/*00e0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fe200000001ff */
/*00f0*/ IMAD.IADD R5, R7, 0x1, -R3 ; /* 0x0000000107057824 */
/* 0x000fd400078e0a03 */
/*0100*/ @!P0 BRA 0x140 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0120*/ IMAD.WIDE R2, R4, R3, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0203 */
/*0130*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000164000c1e1900 */
/*0140*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0150*/ STS [R5.X4], R2 ; /* 0x0000000205007388 */
/* 0x0203e40000004800 */
/*0160*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0170*/ ISETP.GE.U32.AND P0, PT, R0, 0x20, PT ; /* 0x000000200000780c */
/* 0x000fe20003f06070 */
/*0180*/ BSSY B0, 0x210 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0190*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fd60003f25270 */
/*01a0*/ @P0 STS [R7.X4+0x4], RZ ; /* 0x000004ff07000388 */
/* 0x0005e20000004800 */
/*01b0*/ @P0 BRA 0x200 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*01c0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x001fca0000000f00 */
/*01d0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x002fcc00078e0003 */
/*01e0*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ee8000c1e1900 */
/*01f0*/ STS [R7.X4+0x4], R2 ; /* 0x0000040207007388 */
/* 0x0081e40000004800 */
/*0200*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0210*/ BSSY B0, 0x2f0 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0220*/ LEA R2, R9, R4, 0x1 ; /* 0x0000000409027211 */
/* 0x003fe200078e08ff */
/*0230*/ @P1 BRA 0x2e0 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*0240*/ ISETP.GT.AND P0, PT, R2, 0x1f, PT ; /* 0x0000001f0200780c */
/* 0x000fe20003f04270 */
/*0250*/ BSSY B1, 0x2d0 ; /* 0x0000007000017945 */
/* 0x000fe20003800000 */
/*0260*/ LEA R4, R9, 0x4, 0x2 ; /* 0x0000000409047811 */
/* 0x000fe200078e10ff */
/*0270*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fd400078e00ff */
/*0280*/ @P0 BRA 0x2c0 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0290*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*02a0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*02b0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000164000c1e1900 */
/*02c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*02d0*/ STS [R4], R3 ; /* 0x0000000304007388 */
/* 0x0203e40000000800 */
/*02e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0300*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fca00000001ff */
/*0310*/ ULDC.S8 UR4, c[0x3][0x0] ; /* 0x00c0000000047ab9 */
/* 0x000fe40000000200 */
/*0320*/ ULDC.S8 UR5, c[0x3][0x1] ; /* 0x00c0004000057ab9 */
/* 0x000fe20000000200 */
/*0330*/ LDS R2, [R7.X4] ; /* 0x0000000007027984 */
/* 0x001e280000004800 */
/*0340*/ LDS R3, [R7.X4+0x4] ; /* 0x0000040007037984 */
/* 0x002e680000004800 */
/*0350*/ LDS R5, [R7.X4+0x8] ; /* 0x0000080007057984 */
/* 0x000ee20000004800 */
/*0360*/ IMAD R2, R2, UR4, RZ ; /* 0x0000000402027c24 */
/* 0x001fe2000f8e02ff */
/*0370*/ UMOV UR4, UR5 ; /* 0x0000000500047c82 */
/* 0x000fc60008000000 */
/*0380*/ IMAD R4, R3, UR4, R2 ; /* 0x0000000403047c24 */
/* 0x002fe2000f8e0202 */
/*0390*/ ULDC.S8 UR4, c[0x3][0x2] ; /* 0x00c0008000047ab9 */
/* 0x000fe20000000200 */
/*03a0*/ IMAD.WIDE.U32 R2, R0, R9, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0009 */
/*03b0*/ IMAD R5, R5, UR4, R4 ; /* 0x0000000405057c24 */
/* 0x008fca000f8e0204 */
/*03c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101906 */
/*03d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03e0*/ BRA 0x3e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void convolution1d_tiles_constant_kernel(int *In, int *Out){
unsigned int index = blockIdx.x * blockDim.x + threadIdx.x; // Index 1d iterator.
__shared__ int Tile[TILE_SIZE + Mask_size - 1];
int n = Mask_size/2;
int halo_left_index = (blockIdx.x - 1 ) * blockDim.x + threadIdx.x;
if (threadIdx.x >= blockDim.x - n ){
Tile[threadIdx.x - (blockDim.x - n )] = (halo_left_index < 0) ? 0 : In[halo_left_index];
}
if(index<N_elements){Tile[n + threadIdx.x] = In[index];
}else{Tile[n + threadIdx.x] = 0;}
int halo_right_index = (blockIdx.x + 1 ) * blockDim.x + threadIdx.x;
if (threadIdx.x < n) {
Tile[n + blockDim.x + threadIdx.x]= (halo_right_index >= N_elements) ? 0 : In[halo_right_index];
}
__syncthreads();
int Value = 0;
for (unsigned int j = 0; j < Mask_size; j ++) {
Value += Tile[threadIdx.x + j] * Global_Mask[j];
}
Out[index] = Value;
} | .file "tmpxft_00101d7b_00000000-6_convolution1d_tiles_constant_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z57__device_stub__Z35convolution1d_tiles_constant_kernelPiS_PiS_
.type _Z57__device_stub__Z35convolution1d_tiles_constant_kernelPiS_PiS_, @function
_Z57__device_stub__Z35convolution1d_tiles_constant_kernelPiS_PiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z35convolution1d_tiles_constant_kernelPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z57__device_stub__Z35convolution1d_tiles_constant_kernelPiS_PiS_, .-_Z57__device_stub__Z35convolution1d_tiles_constant_kernelPiS_PiS_
.globl _Z35convolution1d_tiles_constant_kernelPiS_
.type _Z35convolution1d_tiles_constant_kernelPiS_, @function
_Z35convolution1d_tiles_constant_kernelPiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z57__device_stub__Z35convolution1d_tiles_constant_kernelPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z35convolution1d_tiles_constant_kernelPiS_, .-_Z35convolution1d_tiles_constant_kernelPiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z35convolution1d_tiles_constant_kernelPiS_"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Global_Mask"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z35convolution1d_tiles_constant_kernelPiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $9, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11Global_Mask(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL11Global_Mask
.comm _ZL11Global_Mask,9,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void convolution1d_tiles_constant_kernel(int *In, int *Out){
unsigned int index = blockIdx.x * blockDim.x + threadIdx.x; // Index 1d iterator.
__shared__ int Tile[TILE_SIZE + Mask_size - 1];
int n = Mask_size/2;
int halo_left_index = (blockIdx.x - 1 ) * blockDim.x + threadIdx.x;
if (threadIdx.x >= blockDim.x - n ){
Tile[threadIdx.x - (blockDim.x - n )] = (halo_left_index < 0) ? 0 : In[halo_left_index];
}
if(index<N_elements){Tile[n + threadIdx.x] = In[index];
}else{Tile[n + threadIdx.x] = 0;}
int halo_right_index = (blockIdx.x + 1 ) * blockDim.x + threadIdx.x;
if (threadIdx.x < n) {
Tile[n + blockDim.x + threadIdx.x]= (halo_right_index >= N_elements) ? 0 : In[halo_right_index];
}
__syncthreads();
int Value = 0;
for (unsigned int j = 0; j < Mask_size; j ++) {
Value += Tile[threadIdx.x + j] * Global_Mask[j];
}
Out[index] = Value;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void convolution1d_tiles_constant_kernel(int *In, int *Out){
unsigned int index = blockIdx.x * blockDim.x + threadIdx.x; // Index 1d iterator.
__shared__ int Tile[TILE_SIZE + Mask_size - 1];
int n = Mask_size/2;
int halo_left_index = (blockIdx.x - 1 ) * blockDim.x + threadIdx.x;
if (threadIdx.x >= blockDim.x - n ){
Tile[threadIdx.x - (blockDim.x - n )] = (halo_left_index < 0) ? 0 : In[halo_left_index];
}
if(index<N_elements){Tile[n + threadIdx.x] = In[index];
}else{Tile[n + threadIdx.x] = 0;}
int halo_right_index = (blockIdx.x + 1 ) * blockDim.x + threadIdx.x;
if (threadIdx.x < n) {
Tile[n + blockDim.x + threadIdx.x]= (halo_right_index >= N_elements) ? 0 : In[halo_right_index];
}
__syncthreads();
int Value = 0;
for (unsigned int j = 0; j < Mask_size; j ++) {
Value += Tile[threadIdx.x + j] * Global_Mask[j];
}
Out[index] = Value;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void convolution1d_tiles_constant_kernel(int *In, int *Out){
unsigned int index = blockIdx.x * blockDim.x + threadIdx.x; // Index 1d iterator.
__shared__ int Tile[TILE_SIZE + Mask_size - 1];
int n = Mask_size/2;
int halo_left_index = (blockIdx.x - 1 ) * blockDim.x + threadIdx.x;
if (threadIdx.x >= blockDim.x - n ){
Tile[threadIdx.x - (blockDim.x - n )] = (halo_left_index < 0) ? 0 : In[halo_left_index];
}
if(index<N_elements){Tile[n + threadIdx.x] = In[index];
}else{Tile[n + threadIdx.x] = 0;}
int halo_right_index = (blockIdx.x + 1 ) * blockDim.x + threadIdx.x;
if (threadIdx.x < n) {
Tile[n + blockDim.x + threadIdx.x]= (halo_right_index >= N_elements) ? 0 : In[halo_right_index];
}
__syncthreads();
int Value = 0;
for (unsigned int j = 0; j < Mask_size; j ++) {
Value += Tile[threadIdx.x + j] * Global_Mask[j];
}
Out[index] = Value;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z35convolution1d_tiles_constant_kernelPiS_
.globl _Z35convolution1d_tiles_constant_kernelPiS_
.p2align 8
.type _Z35convolution1d_tiles_constant_kernelPiS_,@function
_Z35convolution1d_tiles_constant_kernelPiS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s4, -1
v_cmpx_le_u32_e64 s6, v0
s_cbranch_execz .LBB0_4
s_add_i32 s7, s15, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s7, s4, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s7, exec_lo
v_cmpx_lt_i32_e32 -1, v1
s_cbranch_execz .LBB0_3
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_b32 v2, v[1:2], off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s7
v_subrev_nc_u32_e32 v1, s6, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 2, v1
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s5
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_gt_u32_e32 32, v1
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v2, v[2:3], off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s5
v_lshlrev_b32_e32 v3, 2, v0
s_mov_b32 s5, exec_lo
s_waitcnt vmcnt(0)
ds_store_b32 v3, v2 offset:4
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_10
s_add_i32 s15, s15, 1
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[2:3], null, s15, s4, v[0:1]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_gt_i32_e32 32, v2
s_cbranch_execz .LBB0_9
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v3, v[2:3], off
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s6
s_lshl_b32 s2, s4, 2
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v2, s2
s_waitcnt vmcnt(0)
ds_store_b32 v2, v3 offset:4
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s5
v_dual_mov_b32 v5, 0 :: v_dual_lshlrev_b32 v2, 2, v0
v_mov_b32_e32 v0, 0
s_mov_b32 s4, 0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, Global_Mask@rel32@lo+4
s_addc_u32 s3, s3, Global_Mask@rel32@hi+12
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_11:
global_load_i8 v6, v5, s[2:3]
v_add_nc_u32_e32 v3, s4, v2
s_add_i32 s4, s4, 4
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s4, 12
ds_load_b32 v7, v3
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, v7, v6, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v0, v3
s_cbranch_scc0 .LBB0_11
s_load_b64 s[0:1], s[0:1], 0x8
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z35convolution1d_tiles_constant_kernelPiS_
.amdhsa_group_segment_fixed_size 136
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z35convolution1d_tiles_constant_kernelPiS_, .Lfunc_end0-_Z35convolution1d_tiles_constant_kernelPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected Global_Mask
.type Global_Mask,@object
.section .bss,"aw",@nobits
.globl Global_Mask
Global_Mask:
.zero 9
.size Global_Mask, 9
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym Global_Mask
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 136
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z35convolution1d_tiles_constant_kernelPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z35convolution1d_tiles_constant_kernelPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void convolution1d_tiles_constant_kernel(int *In, int *Out){
unsigned int index = blockIdx.x * blockDim.x + threadIdx.x; // Index 1d iterator.
__shared__ int Tile[TILE_SIZE + Mask_size - 1];
int n = Mask_size/2;
int halo_left_index = (blockIdx.x - 1 ) * blockDim.x + threadIdx.x;
if (threadIdx.x >= blockDim.x - n ){
Tile[threadIdx.x - (blockDim.x - n )] = (halo_left_index < 0) ? 0 : In[halo_left_index];
}
if(index<N_elements){Tile[n + threadIdx.x] = In[index];
}else{Tile[n + threadIdx.x] = 0;}
int halo_right_index = (blockIdx.x + 1 ) * blockDim.x + threadIdx.x;
if (threadIdx.x < n) {
Tile[n + blockDim.x + threadIdx.x]= (halo_right_index >= N_elements) ? 0 : In[halo_right_index];
}
__syncthreads();
int Value = 0;
for (unsigned int j = 0; j < Mask_size; j ++) {
Value += Tile[threadIdx.x + j] * Global_Mask[j];
}
Out[index] = Value;
} | .text
.file "convolution1d_tiles_constant_kernel.hip"
.globl _Z50__device_stub__convolution1d_tiles_constant_kernelPiS_ # -- Begin function _Z50__device_stub__convolution1d_tiles_constant_kernelPiS_
.p2align 4, 0x90
.type _Z50__device_stub__convolution1d_tiles_constant_kernelPiS_,@function
_Z50__device_stub__convolution1d_tiles_constant_kernelPiS_: # @_Z50__device_stub__convolution1d_tiles_constant_kernelPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z35convolution1d_tiles_constant_kernelPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z50__device_stub__convolution1d_tiles_constant_kernelPiS_, .Lfunc_end0-_Z50__device_stub__convolution1d_tiles_constant_kernelPiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z35convolution1d_tiles_constant_kernelPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $Global_Mask, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $9, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type Global_Mask,@object # @Global_Mask
.local Global_Mask
.comm Global_Mask,9,1
.type _Z35convolution1d_tiles_constant_kernelPiS_,@object # @_Z35convolution1d_tiles_constant_kernelPiS_
.section .rodata,"a",@progbits
.globl _Z35convolution1d_tiles_constant_kernelPiS_
.p2align 3, 0x0
_Z35convolution1d_tiles_constant_kernelPiS_:
.quad _Z50__device_stub__convolution1d_tiles_constant_kernelPiS_
.size _Z35convolution1d_tiles_constant_kernelPiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z35convolution1d_tiles_constant_kernelPiS_"
.size .L__unnamed_1, 44
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "Global_Mask"
.size .L__unnamed_2, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z50__device_stub__convolution1d_tiles_constant_kernelPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym Global_Mask
.addrsig_sym _Z35convolution1d_tiles_constant_kernelPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z35convolution1d_tiles_constant_kernelPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0x170 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*0050*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e640000002500 */
/*0060*/ IADD3 R3, R9, -0x1, RZ ; /* 0xffffffff09037810 */
/* 0x000fc80007ffe0ff */
/*0070*/ ISETP.GE.U32.AND P0, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x001fe20003f06070 */
/*0080*/ IMAD R2, R0.reuse, R9, -c[0x0][0x0] ; /* 0x8000000000027624 */
/* 0x042fe400078e0209 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R7 ; /* 0x0000000000007a24 */
/* 0x000fc600078e0207 */
/*00a0*/ IADD3 R4, R2, R7, RZ ; /* 0x0000000702047210 */
/* 0x000fce0007ffe0ff */
/*00b0*/ @!P0 BRA 0x160 ; /* 0x000000a000008947 */
/* 0x000fea0003800000 */
/*00c0*/ ISETP.GE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f06270 */
/*00d0*/ BSSY B1, 0x150 ; /* 0x0000007000017945 */
/* 0x000fe20003800000 */
/*00e0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fe200000001ff */
/*00f0*/ IMAD.IADD R5, R7, 0x1, -R3 ; /* 0x0000000107057824 */
/* 0x000fd400078e0a03 */
/*0100*/ @!P0 BRA 0x140 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0120*/ IMAD.WIDE R2, R4, R3, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0203 */
/*0130*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000164000c1e1900 */
/*0140*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0150*/ STS [R5.X4], R2 ; /* 0x0000000205007388 */
/* 0x0203e40000004800 */
/*0160*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0170*/ ISETP.GE.U32.AND P0, PT, R0, 0x20, PT ; /* 0x000000200000780c */
/* 0x000fe20003f06070 */
/*0180*/ BSSY B0, 0x210 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0190*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fd60003f25270 */
/*01a0*/ @P0 STS [R7.X4+0x4], RZ ; /* 0x000004ff07000388 */
/* 0x0005e20000004800 */
/*01b0*/ @P0 BRA 0x200 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*01c0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x001fca0000000f00 */
/*01d0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x002fcc00078e0003 */
/*01e0*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ee8000c1e1900 */
/*01f0*/ STS [R7.X4+0x4], R2 ; /* 0x0000040207007388 */
/* 0x0081e40000004800 */
/*0200*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0210*/ BSSY B0, 0x2f0 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0220*/ LEA R2, R9, R4, 0x1 ; /* 0x0000000409027211 */
/* 0x003fe200078e08ff */
/*0230*/ @P1 BRA 0x2e0 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*0240*/ ISETP.GT.AND P0, PT, R2, 0x1f, PT ; /* 0x0000001f0200780c */
/* 0x000fe20003f04270 */
/*0250*/ BSSY B1, 0x2d0 ; /* 0x0000007000017945 */
/* 0x000fe20003800000 */
/*0260*/ LEA R4, R9, 0x4, 0x2 ; /* 0x0000000409047811 */
/* 0x000fe200078e10ff */
/*0270*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fd400078e00ff */
/*0280*/ @P0 BRA 0x2c0 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0290*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*02a0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*02b0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000164000c1e1900 */
/*02c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*02d0*/ STS [R4], R3 ; /* 0x0000000304007388 */
/* 0x0203e40000000800 */
/*02e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0300*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fca00000001ff */
/*0310*/ ULDC.S8 UR4, c[0x3][0x0] ; /* 0x00c0000000047ab9 */
/* 0x000fe40000000200 */
/*0320*/ ULDC.S8 UR5, c[0x3][0x1] ; /* 0x00c0004000057ab9 */
/* 0x000fe20000000200 */
/*0330*/ LDS R2, [R7.X4] ; /* 0x0000000007027984 */
/* 0x001e280000004800 */
/*0340*/ LDS R3, [R7.X4+0x4] ; /* 0x0000040007037984 */
/* 0x002e680000004800 */
/*0350*/ LDS R5, [R7.X4+0x8] ; /* 0x0000080007057984 */
/* 0x000ee20000004800 */
/*0360*/ IMAD R2, R2, UR4, RZ ; /* 0x0000000402027c24 */
/* 0x001fe2000f8e02ff */
/*0370*/ UMOV UR4, UR5 ; /* 0x0000000500047c82 */
/* 0x000fc60008000000 */
/*0380*/ IMAD R4, R3, UR4, R2 ; /* 0x0000000403047c24 */
/* 0x002fe2000f8e0202 */
/*0390*/ ULDC.S8 UR4, c[0x3][0x2] ; /* 0x00c0008000047ab9 */
/* 0x000fe20000000200 */
/*03a0*/ IMAD.WIDE.U32 R2, R0, R9, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0009 */
/*03b0*/ IMAD R5, R5, UR4, R4 ; /* 0x0000000405057c24 */
/* 0x008fca000f8e0204 */
/*03c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101906 */
/*03d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03e0*/ BRA 0x3e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z35convolution1d_tiles_constant_kernelPiS_
.globl _Z35convolution1d_tiles_constant_kernelPiS_
.p2align 8
.type _Z35convolution1d_tiles_constant_kernelPiS_,@function
_Z35convolution1d_tiles_constant_kernelPiS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s6, s4, -1
v_cmpx_le_u32_e64 s6, v0
s_cbranch_execz .LBB0_4
s_add_i32 s7, s15, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s7, s4, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s7, exec_lo
v_cmpx_lt_i32_e32 -1, v1
s_cbranch_execz .LBB0_3
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_b32 v2, v[1:2], off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s7
v_subrev_nc_u32_e32 v1, s6, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v1, 2, v1
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s5
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_gt_u32_e32 32, v1
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v2, v[2:3], off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s5
v_lshlrev_b32_e32 v3, 2, v0
s_mov_b32 s5, exec_lo
s_waitcnt vmcnt(0)
ds_store_b32 v3, v2 offset:4
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_10
s_add_i32 s15, s15, 1
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[2:3], null, s15, s4, v[0:1]
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_gt_i32_e32 32, v2
s_cbranch_execz .LBB0_9
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v3, v[2:3], off
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s6
s_lshl_b32 s2, s4, 2
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v2, s2
s_waitcnt vmcnt(0)
ds_store_b32 v2, v3 offset:4
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s5
v_dual_mov_b32 v5, 0 :: v_dual_lshlrev_b32 v2, 2, v0
v_mov_b32_e32 v0, 0
s_mov_b32 s4, 0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, Global_Mask@rel32@lo+4
s_addc_u32 s3, s3, Global_Mask@rel32@hi+12
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_11:
global_load_i8 v6, v5, s[2:3]
v_add_nc_u32_e32 v3, s4, v2
s_add_i32 s4, s4, 4
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s4, 12
ds_load_b32 v7, v3
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, v7, v6, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v0, v3
s_cbranch_scc0 .LBB0_11
s_load_b64 s[0:1], s[0:1], 0x8
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z35convolution1d_tiles_constant_kernelPiS_
.amdhsa_group_segment_fixed_size 136
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z35convolution1d_tiles_constant_kernelPiS_, .Lfunc_end0-_Z35convolution1d_tiles_constant_kernelPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected Global_Mask
.type Global_Mask,@object
.section .bss,"aw",@nobits
.globl Global_Mask
Global_Mask:
.zero 9
.size Global_Mask, 9
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym Global_Mask
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 136
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z35convolution1d_tiles_constant_kernelPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z35convolution1d_tiles_constant_kernelPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00101d7b_00000000-6_convolution1d_tiles_constant_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z57__device_stub__Z35convolution1d_tiles_constant_kernelPiS_PiS_
.type _Z57__device_stub__Z35convolution1d_tiles_constant_kernelPiS_PiS_, @function
_Z57__device_stub__Z35convolution1d_tiles_constant_kernelPiS_PiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z35convolution1d_tiles_constant_kernelPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z57__device_stub__Z35convolution1d_tiles_constant_kernelPiS_PiS_, .-_Z57__device_stub__Z35convolution1d_tiles_constant_kernelPiS_PiS_
.globl _Z35convolution1d_tiles_constant_kernelPiS_
.type _Z35convolution1d_tiles_constant_kernelPiS_, @function
_Z35convolution1d_tiles_constant_kernelPiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z57__device_stub__Z35convolution1d_tiles_constant_kernelPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z35convolution1d_tiles_constant_kernelPiS_, .-_Z35convolution1d_tiles_constant_kernelPiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z35convolution1d_tiles_constant_kernelPiS_"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Global_Mask"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z35convolution1d_tiles_constant_kernelPiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $9, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11Global_Mask(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL11Global_Mask
.comm _ZL11Global_Mask,9,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "convolution1d_tiles_constant_kernel.hip"
.globl _Z50__device_stub__convolution1d_tiles_constant_kernelPiS_ # -- Begin function _Z50__device_stub__convolution1d_tiles_constant_kernelPiS_
.p2align 4, 0x90
.type _Z50__device_stub__convolution1d_tiles_constant_kernelPiS_,@function
_Z50__device_stub__convolution1d_tiles_constant_kernelPiS_: # @_Z50__device_stub__convolution1d_tiles_constant_kernelPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z35convolution1d_tiles_constant_kernelPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z50__device_stub__convolution1d_tiles_constant_kernelPiS_, .Lfunc_end0-_Z50__device_stub__convolution1d_tiles_constant_kernelPiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z35convolution1d_tiles_constant_kernelPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $Global_Mask, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $9, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type Global_Mask,@object # @Global_Mask
.local Global_Mask
.comm Global_Mask,9,1
.type _Z35convolution1d_tiles_constant_kernelPiS_,@object # @_Z35convolution1d_tiles_constant_kernelPiS_
.section .rodata,"a",@progbits
.globl _Z35convolution1d_tiles_constant_kernelPiS_
.p2align 3, 0x0
_Z35convolution1d_tiles_constant_kernelPiS_:
.quad _Z50__device_stub__convolution1d_tiles_constant_kernelPiS_
.size _Z35convolution1d_tiles_constant_kernelPiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z35convolution1d_tiles_constant_kernelPiS_"
.size .L__unnamed_1, 44
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "Global_Mask"
.size .L__unnamed_2, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z50__device_stub__convolution1d_tiles_constant_kernelPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym Global_Mask
.addrsig_sym _Z35convolution1d_tiles_constant_kernelPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void sumMatrixOnGPUMix(float *MatA, float *MatB, float *MatC, int nx, int ny)
{
unsigned int nxthreads = gridDim.x * blockDim.x;
unsigned int iy = blockIdx.y;
unsigned int ix = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int ix2 = ix + nxthreads;
unsigned int idx = iy * nx + ix;
unsigned int idx2 = iy * nx + ix2;
if (iy < ny)
{
if (ix < nx)
MatC[idx] = MatA[idx] + MatB[idx];
if (ix2 < nx)
MatC[idx2] = MatA[idx2] + MatB[idx2];
}
} | code for sm_80
Function : _Z17sumMatrixOnGPUMixPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R11, SR_CTAID.Y ; /* 0x00000000000b7919 */
/* 0x000e280000002600 */
/*0020*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R11, c[0x0][0x17c], PT ; /* 0x00005f000b007a0c */
/* 0x001fe20003f06070 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fd800078e0203 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06070 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd80000000a00 */
/*0090*/ @!P0 MOV R9, 0x4 ; /* 0x0000000400098802 */
/* 0x000fe20000000f00 */
/*00a0*/ @!P0 IMAD R6, R11, c[0x0][0x178], R0 ; /* 0x00005e000b068a24 */
/* 0x000fc800078e0200 */
/*00b0*/ @!P0 IMAD.WIDE.U32 R4, R6, R9, c[0x0][0x168] ; /* 0x00005a0006048625 */
/* 0x000fc800078e0009 */
/*00c0*/ @!P0 IMAD.WIDE.U32 R2, R6, R9, c[0x0][0x160] ; /* 0x0000580006028625 */
/* 0x000fe400078e0009 */
/*00d0*/ @!P0 LDG.E R4, [R4.64] ; /* 0x0000000404048981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ @!P0 LDG.E R3, [R2.64] ; /* 0x0000000402038981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ MOV R7, c[0x0][0xc] ; /* 0x0000030000077a02 */
/* 0x000fca0000000f00 */
/*0100*/ IMAD R0, R7, c[0x0][0x0], R0 ; /* 0x0000000007007a24 */
/* 0x000fe400078e0200 */
/*0110*/ @!P0 IMAD.WIDE.U32 R6, R6, R9, c[0x0][0x170] ; /* 0x00005c0006068625 */
/* 0x000fc600078e0009 */
/*0120*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f26070 */
/*0130*/ @!P0 FADD R9, R4, R3 ; /* 0x0000000304098221 */
/* 0x004fca0000000000 */
/*0140*/ @!P0 STG.E [R6.64], R9 ; /* 0x0000000906008986 */
/* 0x0001ee000c101904 */
/*0150*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0160*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fe200000001ff */
/*0170*/ IMAD R0, R11, c[0x0][0x178], R0 ; /* 0x00005e000b007a24 */
/* 0x000fd200078e0200 */
/*0180*/ IMAD.WIDE.U32 R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0007 */
/*0190*/ IMAD.WIDE.U32 R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0007 */
/*01a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*01b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*01c0*/ IMAD.WIDE.U32 R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0007 */
/*01d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*01e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void sumMatrixOnGPUMix(float *MatA, float *MatB, float *MatC, int nx, int ny)
{
unsigned int nxthreads = gridDim.x * blockDim.x;
unsigned int iy = blockIdx.y;
unsigned int ix = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int ix2 = ix + nxthreads;
unsigned int idx = iy * nx + ix;
unsigned int idx2 = iy * nx + ix2;
if (iy < ny)
{
if (ix < nx)
MatC[idx] = MatA[idx] + MatB[idx];
if (ix2 < nx)
MatC[idx2] = MatA[idx2] + MatB[idx2];
}
} | .file "tmpxft_000d39ee_00000000-6_sumMatrixOnGPUMix.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z17sumMatrixOnGPUMixPfS_S_iiPfS_S_ii
.type _Z43__device_stub__Z17sumMatrixOnGPUMixPfS_S_iiPfS_S_ii, @function
_Z43__device_stub__Z17sumMatrixOnGPUMixPfS_S_iiPfS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17sumMatrixOnGPUMixPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z43__device_stub__Z17sumMatrixOnGPUMixPfS_S_iiPfS_S_ii, .-_Z43__device_stub__Z17sumMatrixOnGPUMixPfS_S_iiPfS_S_ii
.globl _Z17sumMatrixOnGPUMixPfS_S_ii
.type _Z17sumMatrixOnGPUMixPfS_S_ii, @function
_Z17sumMatrixOnGPUMixPfS_S_ii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z17sumMatrixOnGPUMixPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z17sumMatrixOnGPUMixPfS_S_ii, .-_Z17sumMatrixOnGPUMixPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17sumMatrixOnGPUMixPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17sumMatrixOnGPUMixPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void sumMatrixOnGPUMix(float *MatA, float *MatB, float *MatC, int nx, int ny)
{
unsigned int nxthreads = gridDim.x * blockDim.x;
unsigned int iy = blockIdx.y;
unsigned int ix = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int ix2 = ix + nxthreads;
unsigned int idx = iy * nx + ix;
unsigned int idx2 = iy * nx + ix2;
if (iy < ny)
{
if (ix < nx)
MatC[idx] = MatA[idx] + MatB[idx];
if (ix2 < nx)
MatC[idx2] = MatA[idx2] + MatB[idx2];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sumMatrixOnGPUMix(float *MatA, float *MatB, float *MatC, int nx, int ny)
{
unsigned int nxthreads = gridDim.x * blockDim.x;
unsigned int iy = blockIdx.y;
unsigned int ix = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int ix2 = ix + nxthreads;
unsigned int idx = iy * nx + ix;
unsigned int idx2 = iy * nx + ix2;
if (iy < ny)
{
if (ix < nx)
MatC[idx] = MatA[idx] + MatB[idx];
if (ix2 < nx)
MatC[idx2] = MatA[idx2] + MatB[idx2];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sumMatrixOnGPUMix(float *MatA, float *MatB, float *MatC, int nx, int ny)
{
unsigned int nxthreads = gridDim.x * blockDim.x;
unsigned int iy = blockIdx.y;
unsigned int ix = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int ix2 = ix + nxthreads;
unsigned int idx = iy * nx + ix;
unsigned int idx2 = iy * nx + ix2;
if (iy < ny)
{
if (ix < nx)
MatC[idx] = MatA[idx] + MatB[idx];
if (ix2 < nx)
MatC[idx2] = MatA[idx2] + MatB[idx2];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17sumMatrixOnGPUMixPfS_S_ii
.globl _Z17sumMatrixOnGPUMixPfS_S_ii
.p2align 8
.type _Z17sumMatrixOnGPUMixPfS_S_ii,@function
_Z17sumMatrixOnGPUMixPfS_S_ii:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_ge_u32 s15, s2
s_cbranch_scc1 .LBB0_5
s_clause 0x4
s_load_b32 s8, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x20
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_mov_b32 s9, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s8, 0xffff
s_mul_i32 s15, s15, s2
v_mad_u64_u32 v[1:2], null, s14, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s2, v1
s_cbranch_execz .LBB0_3
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v2, s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v4
global_store_b32 v[2:3], v0, off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s3, s8, v[1:2]
v_cmp_gt_u32_e32 vcc_lo, s2, v2
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_5
v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, s15, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17sumMatrixOnGPUMixPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17sumMatrixOnGPUMixPfS_S_ii, .Lfunc_end0-_Z17sumMatrixOnGPUMixPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17sumMatrixOnGPUMixPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17sumMatrixOnGPUMixPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sumMatrixOnGPUMix(float *MatA, float *MatB, float *MatC, int nx, int ny)
{
unsigned int nxthreads = gridDim.x * blockDim.x;
unsigned int iy = blockIdx.y;
unsigned int ix = threadIdx.x + blockIdx.x * blockDim.x;
unsigned int ix2 = ix + nxthreads;
unsigned int idx = iy * nx + ix;
unsigned int idx2 = iy * nx + ix2;
if (iy < ny)
{
if (ix < nx)
MatC[idx] = MatA[idx] + MatB[idx];
if (ix2 < nx)
MatC[idx2] = MatA[idx2] + MatB[idx2];
}
} | .text
.file "sumMatrixOnGPUMix.hip"
.globl _Z32__device_stub__sumMatrixOnGPUMixPfS_S_ii # -- Begin function _Z32__device_stub__sumMatrixOnGPUMixPfS_S_ii
.p2align 4, 0x90
.type _Z32__device_stub__sumMatrixOnGPUMixPfS_S_ii,@function
_Z32__device_stub__sumMatrixOnGPUMixPfS_S_ii: # @_Z32__device_stub__sumMatrixOnGPUMixPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17sumMatrixOnGPUMixPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__sumMatrixOnGPUMixPfS_S_ii, .Lfunc_end0-_Z32__device_stub__sumMatrixOnGPUMixPfS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17sumMatrixOnGPUMixPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17sumMatrixOnGPUMixPfS_S_ii,@object # @_Z17sumMatrixOnGPUMixPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z17sumMatrixOnGPUMixPfS_S_ii
.p2align 3, 0x0
_Z17sumMatrixOnGPUMixPfS_S_ii:
.quad _Z32__device_stub__sumMatrixOnGPUMixPfS_S_ii
.size _Z17sumMatrixOnGPUMixPfS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17sumMatrixOnGPUMixPfS_S_ii"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__sumMatrixOnGPUMixPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17sumMatrixOnGPUMixPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17sumMatrixOnGPUMixPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R11, SR_CTAID.Y ; /* 0x00000000000b7919 */
/* 0x000e280000002600 */
/*0020*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R11, c[0x0][0x17c], PT ; /* 0x00005f000b007a0c */
/* 0x001fe20003f06070 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fd800078e0203 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06070 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd80000000a00 */
/*0090*/ @!P0 MOV R9, 0x4 ; /* 0x0000000400098802 */
/* 0x000fe20000000f00 */
/*00a0*/ @!P0 IMAD R6, R11, c[0x0][0x178], R0 ; /* 0x00005e000b068a24 */
/* 0x000fc800078e0200 */
/*00b0*/ @!P0 IMAD.WIDE.U32 R4, R6, R9, c[0x0][0x168] ; /* 0x00005a0006048625 */
/* 0x000fc800078e0009 */
/*00c0*/ @!P0 IMAD.WIDE.U32 R2, R6, R9, c[0x0][0x160] ; /* 0x0000580006028625 */
/* 0x000fe400078e0009 */
/*00d0*/ @!P0 LDG.E R4, [R4.64] ; /* 0x0000000404048981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ @!P0 LDG.E R3, [R2.64] ; /* 0x0000000402038981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ MOV R7, c[0x0][0xc] ; /* 0x0000030000077a02 */
/* 0x000fca0000000f00 */
/*0100*/ IMAD R0, R7, c[0x0][0x0], R0 ; /* 0x0000000007007a24 */
/* 0x000fe400078e0200 */
/*0110*/ @!P0 IMAD.WIDE.U32 R6, R6, R9, c[0x0][0x170] ; /* 0x00005c0006068625 */
/* 0x000fc600078e0009 */
/*0120*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f26070 */
/*0130*/ @!P0 FADD R9, R4, R3 ; /* 0x0000000304098221 */
/* 0x004fca0000000000 */
/*0140*/ @!P0 STG.E [R6.64], R9 ; /* 0x0000000906008986 */
/* 0x0001ee000c101904 */
/*0150*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0160*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fe200000001ff */
/*0170*/ IMAD R0, R11, c[0x0][0x178], R0 ; /* 0x00005e000b007a24 */
/* 0x000fd200078e0200 */
/*0180*/ IMAD.WIDE.U32 R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0007 */
/*0190*/ IMAD.WIDE.U32 R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0007 */
/*01a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*01b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*01c0*/ IMAD.WIDE.U32 R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0007 */
/*01d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*01e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17sumMatrixOnGPUMixPfS_S_ii
.globl _Z17sumMatrixOnGPUMixPfS_S_ii
.p2align 8
.type _Z17sumMatrixOnGPUMixPfS_S_ii,@function
_Z17sumMatrixOnGPUMixPfS_S_ii:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_ge_u32 s15, s2
s_cbranch_scc1 .LBB0_5
s_clause 0x4
s_load_b32 s8, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x20
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_mov_b32 s9, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s8, 0xffff
s_mul_i32 s15, s15, s2
v_mad_u64_u32 v[1:2], null, s14, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s2, v1
s_cbranch_execz .LBB0_3
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v2, s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v4
global_store_b32 v[2:3], v0, off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s3, s8, v[1:2]
v_cmp_gt_u32_e32 vcc_lo, s2, v2
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_5
v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, s15, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17sumMatrixOnGPUMixPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17sumMatrixOnGPUMixPfS_S_ii, .Lfunc_end0-_Z17sumMatrixOnGPUMixPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17sumMatrixOnGPUMixPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17sumMatrixOnGPUMixPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d39ee_00000000-6_sumMatrixOnGPUMix.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z17sumMatrixOnGPUMixPfS_S_iiPfS_S_ii
.type _Z43__device_stub__Z17sumMatrixOnGPUMixPfS_S_iiPfS_S_ii, @function
_Z43__device_stub__Z17sumMatrixOnGPUMixPfS_S_iiPfS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17sumMatrixOnGPUMixPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z43__device_stub__Z17sumMatrixOnGPUMixPfS_S_iiPfS_S_ii, .-_Z43__device_stub__Z17sumMatrixOnGPUMixPfS_S_iiPfS_S_ii
.globl _Z17sumMatrixOnGPUMixPfS_S_ii
.type _Z17sumMatrixOnGPUMixPfS_S_ii, @function
_Z17sumMatrixOnGPUMixPfS_S_ii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z17sumMatrixOnGPUMixPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z17sumMatrixOnGPUMixPfS_S_ii, .-_Z17sumMatrixOnGPUMixPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17sumMatrixOnGPUMixPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17sumMatrixOnGPUMixPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sumMatrixOnGPUMix.hip"
.globl _Z32__device_stub__sumMatrixOnGPUMixPfS_S_ii # -- Begin function _Z32__device_stub__sumMatrixOnGPUMixPfS_S_ii
.p2align 4, 0x90
.type _Z32__device_stub__sumMatrixOnGPUMixPfS_S_ii,@function
_Z32__device_stub__sumMatrixOnGPUMixPfS_S_ii: # @_Z32__device_stub__sumMatrixOnGPUMixPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17sumMatrixOnGPUMixPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__sumMatrixOnGPUMixPfS_S_ii, .Lfunc_end0-_Z32__device_stub__sumMatrixOnGPUMixPfS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17sumMatrixOnGPUMixPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17sumMatrixOnGPUMixPfS_S_ii,@object # @_Z17sumMatrixOnGPUMixPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z17sumMatrixOnGPUMixPfS_S_ii
.p2align 3, 0x0
_Z17sumMatrixOnGPUMixPfS_S_ii:
.quad _Z32__device_stub__sumMatrixOnGPUMixPfS_S_ii
.size _Z17sumMatrixOnGPUMixPfS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17sumMatrixOnGPUMixPfS_S_ii"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__sumMatrixOnGPUMixPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17sumMatrixOnGPUMixPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cmath>
#include <iostream>
#include <random>
#include <ctime>
/**
* generate random double with range: @fMin ~ @fMax
*/
double fRand(double fMin, double fMax)
{
std::random_device rd;
std::mt19937 gen(rd());
std::uniform_real_distribution<> dis(fMin, fMax);
double a = dis(gen);
return a;
}
/**
* create balls with radius @r, coordinate (@_x, @_y), velocity vector <@v_x, @v_y>
*/
struct Obstacle
{
public:
double _x, _y, v_x, v_y, r;
Obstacle()
{
_x = fRand(-100.0, 100.0);
_y = fRand(-100.0, 100.0);
v_x = fRand(0.0, 5.0);
v_y = fRand(0.0, 5.0);
r = 1.0;
}
};
/**
* @n obstacles
* for each obstacle, return time elapsed when collison starts @t_s and ends @t_e
* stored in @list[]
*/
__global__ void intersectTime_g(int n, Obstacle points[], double list[])
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
// process each obstacle
for(int j = index; j < n; j += stride)
{
Obstacle a = points[j];
//distance @d b/w obstacle and scooter
double d = sqrt(a._x * a._x + a._y * a._y);
//distance travelled when collision starts @d_s and ends @d_e
double d_s = d - 2.0;
double d_e = d + 2.0;
//velocity @v of obstacle
double v = sqrt(a.v_x * a.v_x + a.v_y * a.v_y);
//time elapsed when collision starts @t_s and ends @t_e
double t_s = d_s / v;
double t_e = d_e / v;
//store in list[j]
list[2 * j] = t_s;
list[2 * j + 1] = t_e;
//for test output
//printf("GPU: (%.2lf, %.2lf), v = %.3lf, t_s = %.2lf, t_e = %.2lf\n", a._x, a._y, v, t_s, t_e);
}
}
void intersectTime_c(int n, Obstacle points[], double list[])
{
for(int j = 0; j < n; j++)
{
Obstacle a = points[j];
//distance @d b/w obstacle and scooter
double d = sqrt(a._x * a._x + a._y * a._y);
//distance travelled when collision starts @d_s and ends @d_e
double d_s = d - 2.0;
double d_e = d + 2.0;
//velocity @v of obstacle
double v = sqrt(a.v_x * a.v_x + a.v_y * a.v_y);
//time elapsed when collision starts @t_s and ends @t_e
double t_s = d_s / v;
double t_e = d_e / v;
//store in list[j]
list[2 * j] = t_s;
list[2 * j + 1] = t_e;
// for test output
//printf("CPU: (%.2lf, %.2lf), v = %.3lf, t_s = %.2lf, t_e = %.2lf\n",a._x, a._y, v, t_s, t_e);
}
}
int main()
{
//(@n*10) obstacles
for(int n = 0; n < 100; n++)
{
double total_time_c = 0.0;
double total_time_g = 0.0;
Obstacle* points_g;
cudaMallocManaged(&points_g, n * 10 * sizeof(Obstacle));
double* list_g;
cudaMallocManaged(&list_g, n * 10 * 2 * sizeof(double));
for(int s = 0; s < 1000; s++)
{
//create same set of points for both CPU and GPU
Obstacle * points = new Obstacle[n * 10];
for(int i = 0; i < n * 10; i++)
{
points[i] = Obstacle();
}
//GPU
//copy points to GPU
cudaMemcpy(points_g, points, n * 10 * sizeof(Obstacle), cudaMemcpyHostToDevice);
//initialize list: store 2 time data for each obstacle
//process obstacles
int blockSize = 256;
int numBlocks = (n * 10 + blockSize - 1) / blockSize;
//timing
clock_t time = clock();
intersectTime_g<<<numBlocks, blockSize>>>(n * 10, points_g, list_g);
cudaMemcpy(points, points_g, n * 10 * sizeof(Obstacle), cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
time = clock() - time;
double elapsed_g = time / (double) CLOCKS_PER_SEC;
total_time_g += elapsed_g;
//CPU
double* list_c = new double[n * 10 * 2];
clock_t e = clock();
intersectTime_c(n * 10, points, list_c);
e = clock() - e;
double elapsed_c = e / (double) CLOCKS_PER_SEC;
total_time_c += elapsed_c;
}
printf("%d GPU: %.8lf s ", (n * 10), total_time_g);
printf("CPU: %.8lf s ", total_time_c);
printf("%.2lf \n", total_time_c / total_time_g);
cudaFree(points_g);
cudaFree(list_g);
}
} | .file "tmpxft_00002458_00000000-6_discrete.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4761:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4761:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15intersectTime_ciP8ObstaclePd
.type _Z15intersectTime_ciP8ObstaclePd, @function
_Z15intersectTime_ciP8ObstaclePd:
.LFB4757:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L3
movq %rdx, %rax
movslq %edi, %rdi
salq $4, %rdi
addq %rdi, %rdx
movsd .LC0(%rip), %xmm4
.L5:
movsd (%rsi), %xmm0
movsd 8(%rsi), %xmm3
movsd 16(%rsi), %xmm1
movsd 24(%rsi), %xmm2
mulsd %xmm0, %xmm0
mulsd %xmm3, %xmm3
addsd %xmm3, %xmm0
sqrtsd %xmm0, %xmm0
movapd %xmm0, %xmm3
subsd %xmm4, %xmm3
addsd %xmm4, %xmm0
mulsd %xmm1, %xmm1
mulsd %xmm2, %xmm2
addsd %xmm2, %xmm1
sqrtsd %xmm1, %xmm1
divsd %xmm1, %xmm3
movsd %xmm3, (%rax)
divsd %xmm1, %xmm0
movsd %xmm0, 8(%rax)
addq $40, %rsi
addq $16, %rax
cmpq %rdx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE4757:
.size _Z15intersectTime_ciP8ObstaclePd, .-_Z15intersectTime_ciP8ObstaclePd
.globl _Z46__device_stub__Z15intersectTime_giP8ObstaclePdiP8ObstaclePd
.type _Z46__device_stub__Z15intersectTime_giP8ObstaclePdiP8ObstaclePd, @function
_Z46__device_stub__Z15intersectTime_giP8ObstaclePdiP8ObstaclePd:
.LFB4783:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15intersectTime_giP8ObstaclePd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4783:
.size _Z46__device_stub__Z15intersectTime_giP8ObstaclePdiP8ObstaclePd, .-_Z46__device_stub__Z15intersectTime_giP8ObstaclePdiP8ObstaclePd
.globl _Z15intersectTime_giP8ObstaclePd
.type _Z15intersectTime_giP8ObstaclePd, @function
_Z15intersectTime_giP8ObstaclePd:
.LFB4784:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z15intersectTime_giP8ObstaclePdiP8ObstaclePd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4784:
.size _Z15intersectTime_giP8ObstaclePd, .-_Z15intersectTime_giP8ObstaclePd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z15intersectTime_giP8ObstaclePd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4786:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z15intersectTime_giP8ObstaclePd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4786:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv,comdat
.align 2
.weak _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
.type _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv, @function
_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv:
.LFB5466:
.cfi_startproc
endbr64
movq %rdi, %rdx
leaq 1816(%rdi), %r9
movq %rdi, %rcx
movl $2567483615, %r8d
.L19:
movq (%rcx), %rax
andq $-2147483648, %rax
movq 8(%rcx), %rsi
andl $2147483647, %esi
orq %rsi, %rax
movq %rax, %rsi
shrq %rsi
xorq 3176(%rcx), %rsi
andl $1, %eax
cmovne %r8, %rax
xorq %rsi, %rax
movq %rax, (%rcx)
addq $8, %rcx
cmpq %r9, %rcx
jne .L19
leaq 3168(%rdi), %r8
movl $2567483615, %esi
.L21:
movq 1816(%rdx), %rax
andq $-2147483648, %rax
movq 1824(%rdx), %rcx
andl $2147483647, %ecx
orq %rcx, %rax
movq %rax, %rcx
shrq %rcx
xorq (%rdx), %rcx
andl $1, %eax
cmovne %rsi, %rax
xorq %rcx, %rax
movq %rax, 1816(%rdx)
addq $8, %rdx
cmpq %r8, %rdx
jne .L21
movq 4984(%rdi), %rax
andq $-2147483648, %rax
movq (%rdi), %rdx
andl $2147483647, %edx
orq %rdx, %rax
movq %rax, %rdx
shrq %rdx
xorq 3168(%rdi), %rdx
andl $1, %eax
movl $2567483615, %ecx
cmovne %rcx, %rax
xorq %rdx, %rax
movq %rax, 4984(%rdi)
movq $0, 4992(%rdi)
ret
.cfi_endproc
.LFE5466:
.size _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv, .-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
.text
.globl _Z5fRanddd
.type _Z5fRanddd, @function
_Z5fRanddd:
.LFB4753:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4753
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $4096, %rsp
.cfi_def_cfa_offset 4112
orq $0, (%rsp)
subq $4096, %rsp
.cfi_def_cfa_offset 8208
orq $0, (%rsp)
subq $1856, %rsp
.cfi_def_cfa_offset 10064
movsd %xmm0, 16(%rsp)
movsd %xmm1, 24(%rsp)
movq %fs:40, %rax
movq %rax, 10040(%rsp)
xorl %eax, %eax
leaq 5040(%rsp), %rsi
leaq 5056(%rsp), %rax
movq %rax, 5040(%rsp)
movl $1634100580, 5056(%rsp)
movl $1953264993, 5059(%rsp)
movq $7, 5048(%rsp)
movb $0, 5063(%rsp)
leaq 32(%rsp), %rdi
.LEHB0:
call _ZNSt13random_device7_M_initERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@PLT
.LEHE0:
movq 5040(%rsp), %rdi
leaq 5056(%rsp), %rax
cmpq %rax, %rdi
je .L26
movq 5056(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L26:
leaq 32(%rsp), %rdi
.LEHB1:
call _ZNSt13random_device9_M_getvalEv@PLT
.LEHE1:
movl %eax, %eax
movq %rax, 5040(%rsp)
movl $1, %ecx
movabsq $945986875574848801, %rdi
.L30:
movq 5032(%rsp,%rcx,8), %rax
movq %rax, %rdx
shrq $30, %rdx
xorq %rdx, %rax
imulq $1812433253, %rax, %rsi
movq %rcx, %rdx
shrq $4, %rdx
movq %rdx, %rax
mulq %rdi
shrq %rdx
imulq $624, %rdx, %rdx
movq %rcx, %rax
subq %rdx, %rax
addl %esi, %eax
movq %rax, 5040(%rsp,%rcx,8)
addq $1, %rcx
cmpq $624, %rcx
jne .L30
movq $624, 10032(%rsp)
movl $2, %ebx
movq $0x000000000, 8(%rsp)
movsd .LC3(%rip), %xmm5
movsd %xmm5, (%rsp)
jmp .L34
.L41:
endbr64
movq %rax, %rbx
leaq 5040(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 10040(%rsp), %rax
subq %fs:40, %rax
je .L29
call __stack_chk_fail@PLT
.L29:
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L47:
leaq 5040(%rsp), %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
jmp .L31
.L32:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
.L33:
mulsd (%rsp), %xmm0
addsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
flds .LC5(%rip)
fmull (%rsp)
fstpl (%rsp)
subq $1, %rbx
je .L46
.L34:
cmpq $623, 10032(%rsp)
ja .L47
.L31:
movq 10032(%rsp), %rax
leaq 1(%rax), %rdx
movq %rdx, 10032(%rsp)
movq 5040(%rsp,%rax,8), %rax
movq %rax, %rdx
shrq $11, %rdx
movl %edx, %edx
xorq %rdx, %rax
movq %rax, %rdx
salq $7, %rdx
andl $2636928640, %edx
xorq %rdx, %rax
movq %rax, %rdx
salq $15, %rdx
andl $4022730752, %edx
xorq %rdx, %rax
movq %rax, %rdx
shrq $18, %rdx
xorq %rdx, %rax
js .L32
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
jmp .L33
.L46:
divsd (%rsp), %xmm0
comisd .LC3(%rip), %xmm0
jnb .L48
.L35:
movsd 24(%rsp), %xmm1
movsd 16(%rsp), %xmm4
subsd %xmm4, %xmm1
mulsd %xmm1, %xmm0
addsd %xmm4, %xmm0
movq %xmm0, %rbx
leaq 32(%rsp), %rdi
call _ZNSt13random_device7_M_finiEv@PLT
movq 10040(%rsp), %rax
subq %fs:40, %rax
jne .L49
movq %rbx, %xmm0
addq $10048, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
movsd .LC4(%rip), %xmm0
jmp .L35
.L40:
endbr64
movq %rax, %rbx
leaq 32(%rsp), %rdi
call _ZNSt13random_device7_M_finiEv@PLT
movq 10040(%rsp), %rax
subq %fs:40, %rax
je .L37
call __stack_chk_fail@PLT
.L37:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L49:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4753:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4753:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4753-.LLSDACSB4753
.LLSDACSB4753:
.uleb128 .LEHB0-.LFB4753
.uleb128 .LEHE0-.LEHB0
.uleb128 .L41-.LFB4753
.uleb128 0
.uleb128 .LEHB1-.LFB4753
.uleb128 .LEHE1-.LEHB1
.uleb128 .L40-.LFB4753
.uleb128 0
.uleb128 .LEHB2-.LFB4753
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB4753
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE4753:
.text
.size _Z5fRanddd, .-_Z5fRanddd
.section .rodata.str1.1,"aMS",@progbits,1
.LC11:
.string "%d GPU: %.8lf s "
.LC12:
.string "CPU: %.8lf s "
.LC13:
.string "%.2lf \n"
.text
.globl main
.type main, @function
main:
.LFB4758:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4758
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq $0, 48(%rsp)
movq $-1, 40(%rsp)
jmp .L57
.L68:
movsd %xmm0, 0(%rbp)
movsd .LC7(%rip), %xmm1
movsd .LC8(%rip), %xmm0
.LEHB4:
call _Z5fRanddd
movsd %xmm0, 8(%rbp)
movsd .LC9(%rip), %xmm1
pxor %xmm0, %xmm0
call _Z5fRanddd
movsd %xmm0, 16(%rbp)
movsd .LC9(%rip), %xmm1
pxor %xmm0, %xmm0
call _Z5fRanddd
movsd %xmm0, 24(%rbp)
movq .LC3(%rip), %rax
movq %rax, 32(%rbp)
addq $40, %rbp
subq $1, %r14
js .L51
.L52:
movsd .LC7(%rip), %xmm1
movsd .LC8(%rip), %xmm0
call _Z5fRanddd
.LEHE4:
jmp .L68
.L51:
cmpl $0, 48(%rsp)
jle .L53
movq %r12, %rbx
movq 72(%rsp), %rax
leaq (%rax,%r12), %r15
movq .LC3(%rip), %r14
movq %r12, 16(%rsp)
movq %r13, 24(%rsp)
.L54:
movsd .LC7(%rip), %xmm1
movsd .LC8(%rip), %xmm0
.LEHB5:
call _Z5fRanddd
movq %xmm0, %r13
movsd .LC7(%rip), %xmm1
movsd .LC8(%rip), %xmm0
call _Z5fRanddd
movq %xmm0, %r12
movsd .LC9(%rip), %xmm1
pxor %xmm0, %xmm0
call _Z5fRanddd
movq %xmm0, %rbp
movsd .LC9(%rip), %xmm1
pxor %xmm0, %xmm0
call _Z5fRanddd
movq %r13, (%rbx)
movq %r12, 8(%rbx)
movq %rbp, 16(%rbx)
movsd %xmm0, 24(%rbx)
movq %r14, 32(%rbx)
addq $40, %rbx
cmpq %r15, %rbx
jne .L54
movq 16(%rsp), %r12
movq 24(%rsp), %r13
.L53:
movl $1, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
call clock@PLT
movq %rax, %rbx
movl $256, 108(%rsp)
movl $1, 112(%rsp)
movl 68(%rsp), %eax
movl %eax, 96(%rsp)
movl $1, 100(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L69
.L55:
movl $2, %ecx
movq %r13, %rdx
movq 80(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC10(%rip), %xmm0
addsd (%rsp), %xmm0
movsd %xmm0, (%rsp)
movq 56(%rsp), %rdi
call _Znam@PLT
movq %rax, %rbp
call clock@PLT
movq %rax, %rbx
movq %rbp, %rdx
movq %r12, %rsi
movl 36(%rsp), %edi
call _Z15intersectTime_ciP8ObstaclePd
call clock@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC10(%rip), %xmm0
addsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
subl $1, 64(%rsp)
je .L70
.L56:
movq %r13, %rdi
call _Znam@PLT
movq %rax, %r12
movq 40(%rsp), %r14
testq %r14, %r14
js .L51
movq %rax, %rbp
jmp .L52
.L69:
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
movl 36(%rsp), %edi
call _Z46__device_stub__Z15intersectTime_giP8ObstaclePdiP8ObstaclePd
jmp .L55
.L70:
movsd (%rsp), %xmm0
movl 36(%rsp), %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm4
divsd (%rsp), %xmm4
movapd %xmm4, %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
addq $10, 40(%rsp)
movq 40(%rsp), %rax
addq $10, 48(%rsp)
cmpq $999, %rax
je .L71
.L57:
movq 48(%rsp), %rbx
movl %ebx, 36(%rsp)
leaq (%rbx,%rbx,4), %rax
leaq 0(,%rax,8), %r13
leaq 80(%rsp), %rdi
movl $1, %edx
movq %r13, %rsi
call cudaMallocManaged@PLT
salq $4, %rbx
movq %rbx, 56(%rsp)
leaq 88(%rsp), %rdi
movl $1, %edx
movq %rbx, %rsi
call cudaMallocManaged@PLT
movq 40(%rsp), %rcx
movl %ecx, %eax
addl $511, %eax
movl %ecx, %edx
addl $256, %edx
cmovns %edx, %eax
sarl $8, %eax
movl %eax, 68(%rsp)
movl %ecx, %eax
movl $1000, 64(%rsp)
movq $0x000000000, (%rsp)
movq $0x000000000, 8(%rsp)
leaq 5(%rax,%rax,4), %rax
salq $3, %rax
movq %rax, 72(%rsp)
jmp .L56
.L71:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L72
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L61:
.cfi_restore_state
endbr64
movq %rax, %rbx
movq %r12, %rdi
call _ZdaPv@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
je .L59
call __stack_chk_fail@PLT
.L59:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE5:
.L72:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4758:
.section .gcc_except_table
.LLSDA4758:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4758-.LLSDACSB4758
.LLSDACSB4758:
.uleb128 .LEHB4-.LFB4758
.uleb128 .LEHE4-.LEHB4
.uleb128 .L61-.LFB4758
.uleb128 0
.uleb128 .LEHB5-.LFB4758
.uleb128 .LEHE5-.LEHB5
.uleb128 0
.uleb128 0
.LLSDACSE4758:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1073741824
.align 8
.LC3:
.long 0
.long 1072693248
.align 8
.LC4:
.long -1
.long 1072693247
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1333788672
.section .rodata.cst8
.align 8
.LC7:
.long 0
.long 1079574528
.align 8
.LC8:
.long 0
.long -1067909120
.align 8
.LC9:
.long 0
.long 1075052544
.align 8
.LC10:
.long 0
.long 1093567616
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cmath>
#include <iostream>
#include <random>
#include <ctime>
/**
* generate random double with range: @fMin ~ @fMax
*/
double fRand(double fMin, double fMax)
{
std::random_device rd;
std::mt19937 gen(rd());
std::uniform_real_distribution<> dis(fMin, fMax);
double a = dis(gen);
return a;
}
/**
* create balls with radius @r, coordinate (@_x, @_y), velocity vector <@v_x, @v_y>
*/
struct Obstacle
{
public:
double _x, _y, v_x, v_y, r;
Obstacle()
{
_x = fRand(-100.0, 100.0);
_y = fRand(-100.0, 100.0);
v_x = fRand(0.0, 5.0);
v_y = fRand(0.0, 5.0);
r = 1.0;
}
};
/**
* @n obstacles
* for each obstacle, return time elapsed when collison starts @t_s and ends @t_e
* stored in @list[]
*/
__global__ void intersectTime_g(int n, Obstacle points[], double list[])
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
// process each obstacle
for(int j = index; j < n; j += stride)
{
Obstacle a = points[j];
//distance @d b/w obstacle and scooter
double d = sqrt(a._x * a._x + a._y * a._y);
//distance travelled when collision starts @d_s and ends @d_e
double d_s = d - 2.0;
double d_e = d + 2.0;
//velocity @v of obstacle
double v = sqrt(a.v_x * a.v_x + a.v_y * a.v_y);
//time elapsed when collision starts @t_s and ends @t_e
double t_s = d_s / v;
double t_e = d_e / v;
//store in list[j]
list[2 * j] = t_s;
list[2 * j + 1] = t_e;
//for test output
//printf("GPU: (%.2lf, %.2lf), v = %.3lf, t_s = %.2lf, t_e = %.2lf\n", a._x, a._y, v, t_s, t_e);
}
}
void intersectTime_c(int n, Obstacle points[], double list[])
{
for(int j = 0; j < n; j++)
{
Obstacle a = points[j];
//distance @d b/w obstacle and scooter
double d = sqrt(a._x * a._x + a._y * a._y);
//distance travelled when collision starts @d_s and ends @d_e
double d_s = d - 2.0;
double d_e = d + 2.0;
//velocity @v of obstacle
double v = sqrt(a.v_x * a.v_x + a.v_y * a.v_y);
//time elapsed when collision starts @t_s and ends @t_e
double t_s = d_s / v;
double t_e = d_e / v;
//store in list[j]
list[2 * j] = t_s;
list[2 * j + 1] = t_e;
// for test output
//printf("CPU: (%.2lf, %.2lf), v = %.3lf, t_s = %.2lf, t_e = %.2lf\n",a._x, a._y, v, t_s, t_e);
}
}
int main()
{
//(@n*10) obstacles
for(int n = 0; n < 100; n++)
{
double total_time_c = 0.0;
double total_time_g = 0.0;
Obstacle* points_g;
cudaMallocManaged(&points_g, n * 10 * sizeof(Obstacle));
double* list_g;
cudaMallocManaged(&list_g, n * 10 * 2 * sizeof(double));
for(int s = 0; s < 1000; s++)
{
//create same set of points for both CPU and GPU
Obstacle * points = new Obstacle[n * 10];
for(int i = 0; i < n * 10; i++)
{
points[i] = Obstacle();
}
//GPU
//copy points to GPU
cudaMemcpy(points_g, points, n * 10 * sizeof(Obstacle), cudaMemcpyHostToDevice);
//initialize list: store 2 time data for each obstacle
//process obstacles
int blockSize = 256;
int numBlocks = (n * 10 + blockSize - 1) / blockSize;
//timing
clock_t time = clock();
intersectTime_g<<<numBlocks, blockSize>>>(n * 10, points_g, list_g);
cudaMemcpy(points, points_g, n * 10 * sizeof(Obstacle), cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
time = clock() - time;
double elapsed_g = time / (double) CLOCKS_PER_SEC;
total_time_g += elapsed_g;
//CPU
double* list_c = new double[n * 10 * 2];
clock_t e = clock();
intersectTime_c(n * 10, points, list_c);
e = clock() - e;
double elapsed_c = e / (double) CLOCKS_PER_SEC;
total_time_c += elapsed_c;
}
printf("%d GPU: %.8lf s ", (n * 10), total_time_g);
printf("CPU: %.8lf s ", total_time_c);
printf("%.2lf \n", total_time_c / total_time_g);
cudaFree(points_g);
cudaFree(list_g);
}
} | #include <hip/hip_runtime.h>
#include <cmath>
#include <iostream>
#include <random>
#include <ctime>
/**
* generate random double with range: @fMin ~ @fMax
*/
double fRand(double fMin, double fMax)
{
std::random_device rd;
std::mt19937 gen(rd());
std::uniform_real_distribution<> dis(fMin, fMax);
double a = dis(gen);
return a;
}
/**
* create balls with radius @r, coordinate (@_x, @_y), velocity vector <@v_x, @v_y>
*/
struct Obstacle
{
public:
double _x, _y, v_x, v_y, r;
Obstacle()
{
_x = fRand(-100.0, 100.0);
_y = fRand(-100.0, 100.0);
v_x = fRand(0.0, 5.0);
v_y = fRand(0.0, 5.0);
r = 1.0;
}
};
/**
* @n obstacles
* for each obstacle, return time elapsed when collison starts @t_s and ends @t_e
* stored in @list[]
*/
__global__ void intersectTime_g(int n, Obstacle points[], double list[])
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
// process each obstacle
for(int j = index; j < n; j += stride)
{
Obstacle a = points[j];
//distance @d b/w obstacle and scooter
double d = sqrt(a._x * a._x + a._y * a._y);
//distance travelled when collision starts @d_s and ends @d_e
double d_s = d - 2.0;
double d_e = d + 2.0;
//velocity @v of obstacle
double v = sqrt(a.v_x * a.v_x + a.v_y * a.v_y);
//time elapsed when collision starts @t_s and ends @t_e
double t_s = d_s / v;
double t_e = d_e / v;
//store in list[j]
list[2 * j] = t_s;
list[2 * j + 1] = t_e;
//for test output
//printf("GPU: (%.2lf, %.2lf), v = %.3lf, t_s = %.2lf, t_e = %.2lf\n", a._x, a._y, v, t_s, t_e);
}
}
void intersectTime_c(int n, Obstacle points[], double list[])
{
for(int j = 0; j < n; j++)
{
Obstacle a = points[j];
//distance @d b/w obstacle and scooter
double d = sqrt(a._x * a._x + a._y * a._y);
//distance travelled when collision starts @d_s and ends @d_e
double d_s = d - 2.0;
double d_e = d + 2.0;
//velocity @v of obstacle
double v = sqrt(a.v_x * a.v_x + a.v_y * a.v_y);
//time elapsed when collision starts @t_s and ends @t_e
double t_s = d_s / v;
double t_e = d_e / v;
//store in list[j]
list[2 * j] = t_s;
list[2 * j + 1] = t_e;
// for test output
//printf("CPU: (%.2lf, %.2lf), v = %.3lf, t_s = %.2lf, t_e = %.2lf\n",a._x, a._y, v, t_s, t_e);
}
}
int main()
{
//(@n*10) obstacles
for(int n = 0; n < 100; n++)
{
double total_time_c = 0.0;
double total_time_g = 0.0;
Obstacle* points_g;
hipMallocManaged(&points_g, n * 10 * sizeof(Obstacle));
double* list_g;
hipMallocManaged(&list_g, n * 10 * 2 * sizeof(double));
for(int s = 0; s < 1000; s++)
{
//create same set of points for both CPU and GPU
Obstacle * points = new Obstacle[n * 10];
for(int i = 0; i < n * 10; i++)
{
points[i] = Obstacle();
}
//GPU
//copy points to GPU
hipMemcpy(points_g, points, n * 10 * sizeof(Obstacle), hipMemcpyHostToDevice);
//initialize list: store 2 time data for each obstacle
//process obstacles
int blockSize = 256;
int numBlocks = (n * 10 + blockSize - 1) / blockSize;
//timing
clock_t time = clock();
intersectTime_g<<<numBlocks, blockSize>>>(n * 10, points_g, list_g);
hipMemcpy(points, points_g, n * 10 * sizeof(Obstacle), hipMemcpyDeviceToHost);
hipDeviceSynchronize();
time = clock() - time;
double elapsed_g = time / (double) CLOCKS_PER_SEC;
total_time_g += elapsed_g;
//CPU
double* list_c = new double[n * 10 * 2];
clock_t e = clock();
intersectTime_c(n * 10, points, list_c);
e = clock() - e;
double elapsed_c = e / (double) CLOCKS_PER_SEC;
total_time_c += elapsed_c;
}
printf("%d GPU: %.8lf s ", (n * 10), total_time_g);
printf("CPU: %.8lf s ", total_time_c);
printf("%.2lf \n", total_time_c / total_time_g);
hipFree(points_g);
hipFree(list_g);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cmath>
#include <iostream>
#include <random>
#include <ctime>
/**
* generate random double with range: @fMin ~ @fMax
*/
double fRand(double fMin, double fMax)
{
std::random_device rd;
std::mt19937 gen(rd());
std::uniform_real_distribution<> dis(fMin, fMax);
double a = dis(gen);
return a;
}
/**
* create balls with radius @r, coordinate (@_x, @_y), velocity vector <@v_x, @v_y>
*/
struct Obstacle
{
public:
double _x, _y, v_x, v_y, r;
Obstacle()
{
_x = fRand(-100.0, 100.0);
_y = fRand(-100.0, 100.0);
v_x = fRand(0.0, 5.0);
v_y = fRand(0.0, 5.0);
r = 1.0;
}
};
/**
* @n obstacles
* for each obstacle, return time elapsed when collison starts @t_s and ends @t_e
* stored in @list[]
*/
__global__ void intersectTime_g(int n, Obstacle points[], double list[])
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
// process each obstacle
for(int j = index; j < n; j += stride)
{
Obstacle a = points[j];
//distance @d b/w obstacle and scooter
double d = sqrt(a._x * a._x + a._y * a._y);
//distance travelled when collision starts @d_s and ends @d_e
double d_s = d - 2.0;
double d_e = d + 2.0;
//velocity @v of obstacle
double v = sqrt(a.v_x * a.v_x + a.v_y * a.v_y);
//time elapsed when collision starts @t_s and ends @t_e
double t_s = d_s / v;
double t_e = d_e / v;
//store in list[j]
list[2 * j] = t_s;
list[2 * j + 1] = t_e;
//for test output
//printf("GPU: (%.2lf, %.2lf), v = %.3lf, t_s = %.2lf, t_e = %.2lf\n", a._x, a._y, v, t_s, t_e);
}
}
void intersectTime_c(int n, Obstacle points[], double list[])
{
for(int j = 0; j < n; j++)
{
Obstacle a = points[j];
//distance @d b/w obstacle and scooter
double d = sqrt(a._x * a._x + a._y * a._y);
//distance travelled when collision starts @d_s and ends @d_e
double d_s = d - 2.0;
double d_e = d + 2.0;
//velocity @v of obstacle
double v = sqrt(a.v_x * a.v_x + a.v_y * a.v_y);
//time elapsed when collision starts @t_s and ends @t_e
double t_s = d_s / v;
double t_e = d_e / v;
//store in list[j]
list[2 * j] = t_s;
list[2 * j + 1] = t_e;
// for test output
//printf("CPU: (%.2lf, %.2lf), v = %.3lf, t_s = %.2lf, t_e = %.2lf\n",a._x, a._y, v, t_s, t_e);
}
}
int main()
{
//(@n*10) obstacles
for(int n = 0; n < 100; n++)
{
double total_time_c = 0.0;
double total_time_g = 0.0;
Obstacle* points_g;
hipMallocManaged(&points_g, n * 10 * sizeof(Obstacle));
double* list_g;
hipMallocManaged(&list_g, n * 10 * 2 * sizeof(double));
for(int s = 0; s < 1000; s++)
{
//create same set of points for both CPU and GPU
Obstacle * points = new Obstacle[n * 10];
for(int i = 0; i < n * 10; i++)
{
points[i] = Obstacle();
}
//GPU
//copy points to GPU
hipMemcpy(points_g, points, n * 10 * sizeof(Obstacle), hipMemcpyHostToDevice);
//initialize list: store 2 time data for each obstacle
//process obstacles
int blockSize = 256;
int numBlocks = (n * 10 + blockSize - 1) / blockSize;
//timing
clock_t time = clock();
intersectTime_g<<<numBlocks, blockSize>>>(n * 10, points_g, list_g);
hipMemcpy(points, points_g, n * 10 * sizeof(Obstacle), hipMemcpyDeviceToHost);
hipDeviceSynchronize();
time = clock() - time;
double elapsed_g = time / (double) CLOCKS_PER_SEC;
total_time_g += elapsed_g;
//CPU
double* list_c = new double[n * 10 * 2];
clock_t e = clock();
intersectTime_c(n * 10, points, list_c);
e = clock() - e;
double elapsed_c = e / (double) CLOCKS_PER_SEC;
total_time_c += elapsed_c;
}
printf("%d GPU: %.8lf s ", (n * 10), total_time_g);
printf("CPU: %.8lf s ", total_time_c);
printf("%.2lf \n", total_time_c / total_time_g);
hipFree(points_g);
hipFree(list_g);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15intersectTime_giP8ObstaclePd
.globl _Z15intersectTime_giP8ObstaclePd
.p2align 8
.type _Z15intersectTime_giP8ObstaclePd,@function
_Z15intersectTime_giP8ObstaclePd:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x0
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s2, 0xffff
s_mov_b32 s2, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s7, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s6, v1
s_cbranch_execz .LBB0_3
s_load_b128 s[0:3], s[0:1], 0x8
s_load_b32 s4, s[4:5], 0x0
v_lshlrev_b32_e32 v2, 1, v1
s_mov_b32 s8, 0
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[4:5], null, v1, 40, s[0:1]
s_mul_i32 s1, s4, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_lshl_b32 s4, s1, 1
s_mul_hi_i32 s5, s1, 40
s_mul_i32 s7, s1, 40
v_add_co_u32 v4, vcc_lo, v4, 16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
.LBB0_2:
s_clause 0x1
global_load_b128 v[6:9], v[4:5], off offset:-16
global_load_b128 v[10:13], v[4:5], off
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v1, s1, v1
s_waitcnt vmcnt(1)
v_mul_f64 v[8:9], v[8:9], v[8:9]
s_waitcnt vmcnt(0)
v_mul_f64 v[12:13], v[12:13], v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[6:7], v[6:7], v[6:7], v[8:9]
v_fma_f64 v[8:9], v[10:11], v[10:11], v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[6:7]
v_cmp_gt_f64_e64 s0, 0x10000000, v[8:9]
v_cndmask_b32_e64 v0, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v0, 8, v0
v_ldexp_f64 v[6:7], v[6:7], v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v0, 0, 1, s0
v_lshlrev_b32_e32 v0, 8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_ldexp_f64 v[8:9], v[8:9], v0
v_cndmask_b32_e64 v0, 0, 0xffffff80, vcc_lo
v_rsq_f64_e32 v[10:11], v[6:7]
v_cmp_class_f64_e64 vcc_lo, v[6:7], 0x260
v_rsq_f64_e32 v[12:13], v[8:9]
s_waitcnt_depctr 0xfff
v_mul_f64 v[14:15], v[6:7], v[10:11]
v_mul_f64 v[10:11], v[10:11], 0.5
v_mul_f64 v[16:17], v[8:9], v[12:13]
v_mul_f64 v[12:13], v[12:13], 0.5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[18:19], -v[10:11], v[14:15], 0.5
v_fma_f64 v[20:21], -v[12:13], v[16:17], 0.5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
v_fma_f64 v[10:11], v[10:11], v[18:19], v[10:11]
v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
v_fma_f64 v[12:13], v[12:13], v[20:21], v[12:13]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[18:19], -v[14:15], v[14:15], v[6:7]
v_fma_f64 v[20:21], -v[16:17], v[16:17], v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[14:15], v[18:19], v[10:11], v[14:15]
v_fma_f64 v[16:17], v[20:21], v[12:13], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[18:19], -v[14:15], v[14:15], v[6:7]
v_fma_f64 v[20:21], -v[16:17], v[16:17], v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], v[18:19], v[10:11], v[14:15]
v_fma_f64 v[12:13], v[20:21], v[12:13], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ldexp_f64 v[10:11], v[10:11], v0
v_cndmask_b32_e64 v0, 0, 0xffffff80, s0
v_cmp_class_f64_e64 s0, v[8:9], 0x260
v_ldexp_f64 v[12:13], v[12:13], v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v7, v11, v7 :: v_dual_cndmask_b32 v6, v10, v6
v_add_f64 v[10:11], v[6:7], -2.0
v_add_f64 v[6:7], v[6:7], 2.0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v9, v13, v9, s0
v_cndmask_b32_e64 v8, v12, v8, s0
v_div_scale_f64 v[12:13], null, v[8:9], v[8:9], v[10:11]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_scale_f64 v[14:15], null, v[8:9], v[8:9], v[6:7]
v_div_scale_f64 v[24:25], vcc_lo, v[10:11], v[8:9], v[10:11]
v_rcp_f64_e32 v[16:17], v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_rcp_f64_e32 v[18:19], v[14:15]
s_waitcnt_depctr 0xfff
v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
v_fma_f64 v[22:23], -v[14:15], v[18:19], 1.0
v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[18:19], v[18:19], v[22:23], v[18:19]
v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[22:23], -v[14:15], v[18:19], 1.0
v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
v_div_scale_f64 v[20:21], s0, v[6:7], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[18:19], v[18:19], v[22:23], v[18:19]
v_mul_f64 v[22:23], v[24:25], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[26:27], v[20:21], v[18:19]
v_fma_f64 v[12:13], -v[12:13], v[22:23], v[24:25]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[14:15], -v[14:15], v[26:27], v[20:21]
v_div_fmas_f64 v[12:13], v[12:13], v[16:17], v[22:23]
s_mov_b32 vcc_lo, s0
s_delay_alu instid0(VALU_DEP_2)
v_div_fmas_f64 v[14:15], v[14:15], v[18:19], v[26:27]
v_add_co_u32 v4, vcc_lo, v4, s7
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s6, v1
s_or_b32 s8, vcc_lo, s8
v_div_fixup_f64 v[10:11], v[12:13], v[8:9], v[10:11]
v_lshlrev_b64 v[12:13], 3, v[2:3]
v_div_fixup_f64 v[6:7], v[14:15], v[8:9], v[6:7]
v_add_nc_u32_e32 v8, 1, v2
v_add_nc_u32_e32 v2, s4, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v12, s0, s2, v12
v_ashrrev_i32_e32 v9, 31, v8
v_add_co_ci_u32_e64 v13, s0, s3, v13, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 3, v[8:9]
v_add_co_u32 v8, s0, s2, v8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v9, s0, s3, v9, s0
s_clause 0x1
global_store_b64 v[12:13], v[10:11], off
global_store_b64 v[8:9], v[6:7], off
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15intersectTime_giP8ObstaclePd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 28
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15intersectTime_giP8ObstaclePd, .Lfunc_end0-_Z15intersectTime_giP8ObstaclePd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15intersectTime_giP8ObstaclePd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15intersectTime_giP8ObstaclePd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 28
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cmath>
#include <iostream>
#include <random>
#include <ctime>
/**
* generate random double with range: @fMin ~ @fMax
*/
double fRand(double fMin, double fMax)
{
std::random_device rd;
std::mt19937 gen(rd());
std::uniform_real_distribution<> dis(fMin, fMax);
double a = dis(gen);
return a;
}
/**
* create balls with radius @r, coordinate (@_x, @_y), velocity vector <@v_x, @v_y>
*/
struct Obstacle
{
public:
double _x, _y, v_x, v_y, r;
Obstacle()
{
_x = fRand(-100.0, 100.0);
_y = fRand(-100.0, 100.0);
v_x = fRand(0.0, 5.0);
v_y = fRand(0.0, 5.0);
r = 1.0;
}
};
/**
* @n obstacles
* for each obstacle, return time elapsed when collison starts @t_s and ends @t_e
* stored in @list[]
*/
__global__ void intersectTime_g(int n, Obstacle points[], double list[])
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
// process each obstacle
for(int j = index; j < n; j += stride)
{
Obstacle a = points[j];
//distance @d b/w obstacle and scooter
double d = sqrt(a._x * a._x + a._y * a._y);
//distance travelled when collision starts @d_s and ends @d_e
double d_s = d - 2.0;
double d_e = d + 2.0;
//velocity @v of obstacle
double v = sqrt(a.v_x * a.v_x + a.v_y * a.v_y);
//time elapsed when collision starts @t_s and ends @t_e
double t_s = d_s / v;
double t_e = d_e / v;
//store in list[j]
list[2 * j] = t_s;
list[2 * j + 1] = t_e;
//for test output
//printf("GPU: (%.2lf, %.2lf), v = %.3lf, t_s = %.2lf, t_e = %.2lf\n", a._x, a._y, v, t_s, t_e);
}
}
void intersectTime_c(int n, Obstacle points[], double list[])
{
for(int j = 0; j < n; j++)
{
Obstacle a = points[j];
//distance @d b/w obstacle and scooter
double d = sqrt(a._x * a._x + a._y * a._y);
//distance travelled when collision starts @d_s and ends @d_e
double d_s = d - 2.0;
double d_e = d + 2.0;
//velocity @v of obstacle
double v = sqrt(a.v_x * a.v_x + a.v_y * a.v_y);
//time elapsed when collision starts @t_s and ends @t_e
double t_s = d_s / v;
double t_e = d_e / v;
//store in list[j]
list[2 * j] = t_s;
list[2 * j + 1] = t_e;
// for test output
//printf("CPU: (%.2lf, %.2lf), v = %.3lf, t_s = %.2lf, t_e = %.2lf\n",a._x, a._y, v, t_s, t_e);
}
}
int main()
{
//(@n*10) obstacles
for(int n = 0; n < 100; n++)
{
double total_time_c = 0.0;
double total_time_g = 0.0;
Obstacle* points_g;
hipMallocManaged(&points_g, n * 10 * sizeof(Obstacle));
double* list_g;
hipMallocManaged(&list_g, n * 10 * 2 * sizeof(double));
for(int s = 0; s < 1000; s++)
{
//create same set of points for both CPU and GPU
Obstacle * points = new Obstacle[n * 10];
for(int i = 0; i < n * 10; i++)
{
points[i] = Obstacle();
}
//GPU
//copy points to GPU
hipMemcpy(points_g, points, n * 10 * sizeof(Obstacle), hipMemcpyHostToDevice);
//initialize list: store 2 time data for each obstacle
//process obstacles
int blockSize = 256;
int numBlocks = (n * 10 + blockSize - 1) / blockSize;
//timing
clock_t time = clock();
intersectTime_g<<<numBlocks, blockSize>>>(n * 10, points_g, list_g);
hipMemcpy(points, points_g, n * 10 * sizeof(Obstacle), hipMemcpyDeviceToHost);
hipDeviceSynchronize();
time = clock() - time;
double elapsed_g = time / (double) CLOCKS_PER_SEC;
total_time_g += elapsed_g;
//CPU
double* list_c = new double[n * 10 * 2];
clock_t e = clock();
intersectTime_c(n * 10, points, list_c);
e = clock() - e;
double elapsed_c = e / (double) CLOCKS_PER_SEC;
total_time_c += elapsed_c;
}
printf("%d GPU: %.8lf s ", (n * 10), total_time_g);
printf("CPU: %.8lf s ", total_time_c);
printf("%.2lf \n", total_time_c / total_time_g);
hipFree(points_g);
hipFree(list_g);
}
} | .text
.file "discrete.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z5fRanddd
.LCPI0_0:
.long 0x4f800000 # float 4.2949673E+9
.LCPI0_1:
.long 0x40000000 # float 2
.LCPI0_2:
.long 0x5f000000 # float 9.22337203E+18
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI0_3:
.quad 0x3ff0000000000000 # double 1
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI0_4:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI0_5:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.text
.globl _Z5fRanddd
.p2align 4, 0x90
.type _Z5fRanddd,@function
_Z5fRanddd: # @_Z5fRanddd
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $10088, %rsp # imm = 0x2768
.cfi_def_cfa_offset 10112
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movsd %xmm1, 56(%rsp) # 8-byte Spill
movsd %xmm0, 48(%rsp) # 8-byte Spill
leaq 104(%rsp), %r14
movq %r14, 88(%rsp)
movl $1634100580, 104(%rsp) # imm = 0x61666564
movl $1953264993, 107(%rsp) # imm = 0x746C7561
movq $7, 96(%rsp)
movb $0, 111(%rsp)
.Ltmp0:
leaq 5088(%rsp), %rdi
leaq 88(%rsp), %rsi
callq _ZNSt13random_device7_M_initERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Ltmp1:
# %bb.1:
movq 88(%rsp), %rdi
cmpq %r14, %rdi
je .LBB0_3
# %bb.2: # %.critedge.i.i.i
callq _ZdlPv
.LBB0_3: # %_ZNSt13random_deviceC2Ev.exit
.Ltmp3:
leaq 5088(%rsp), %rdi
callq _ZNSt13random_device9_M_getvalEv
.Ltmp4:
# %bb.4: # %_ZNSt13random_deviceclEv.exit
movl %eax, %eax
movq %rax, 88(%rsp)
movl $1, %ecx
.p2align 4, 0x90
.LBB0_5: # =>This Inner Loop Header: Depth=1
movq %rax, %rdx
shrq $30, %rdx
xorl %eax, %edx
imull $1812433253, %edx, %eax # imm = 0x6C078965
addl %ecx, %eax
movq %rax, 88(%rsp,%rcx,8)
incq %rcx
cmpq $624, %rcx # imm = 0x270
jne .LBB0_5
# %bb.6: # %_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEC2Em.exit
movq $624, 5080(%rsp) # imm = 0x270
flds .LCPI0_0(%rip)
fstpt (%rsp)
callq logl
fstpt 24(%rsp) # 10-byte Folded Spill
flds .LCPI0_1(%rip)
fstpt (%rsp)
callq logl
fldt 24(%rsp) # 10-byte Folded Reload
fdivp %st, %st(1)
flds .LCPI0_2(%rip)
xorl %ecx, %ecx
fxch %st(1)
fucomi %st(1), %st
fldz
fcmovnb %st(2), %st
fstp %st(2)
fsubp %st, %st(1)
setae %cl
fnstcw 20(%rsp)
movzwl 20(%rsp), %eax
orl $3072, %eax # imm = 0xC00
movw %ax, 22(%rsp)
fldcw 22(%rsp)
fistpll 80(%rsp)
fldcw 20(%rsp)
shlq $63, %rcx
xorq 80(%rsp), %rcx
leaq 52(%rcx), %rax
xorl %edx, %edx
divq %rcx
movq %rax, %rbx
cmpq $1, %rax
adcq $0, %rbx
xorps %xmm0, %xmm0
movsd %xmm0, 24(%rsp) # 8-byte Spill
movsd .LCPI0_3(%rip), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 40(%rsp) # 8-byte Spill
leaq 88(%rsp), %r14
.p2align 4, 0x90
.LBB0_7: # =>This Inner Loop Header: Depth=1
.Ltmp6:
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.Ltmp7:
# %bb.8: # %.noexc
# in Loop: Header=BB0_7 Depth=1
movq %rax, %xmm0
punpckldq .LCPI0_4(%rip), %xmm0 # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
subpd .LCPI0_5(%rip), %xmm0
movapd %xmm0, %xmm1
unpckhpd %xmm0, %xmm1 # xmm1 = xmm1[1],xmm0[1]
addsd %xmm0, %xmm1
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd %xmm0, %xmm1
movsd %xmm0, 72(%rsp)
fldl 72(%rsp)
fmuls .LCPI0_0(%rip)
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd %xmm1, %xmm0
movsd %xmm0, 24(%rsp) # 8-byte Spill
fstpl 64(%rsp)
movsd 64(%rsp), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 40(%rsp) # 8-byte Spill
decq %rbx
jne .LBB0_7
# %bb.9:
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd 40(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 24(%rsp) # 8-byte Spill
ucomisd .LCPI0_3(%rip), %xmm0
jae .LBB0_10
.LBB0_11: # %_ZNSt25uniform_real_distributionIdEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEdRT_.exit
.Ltmp12:
leaq 5088(%rsp), %rdi
callq _ZNSt13random_device7_M_finiEv
.Ltmp13:
# %bb.12: # %_ZNSt13random_deviceD2Ev.exit
movsd 56(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd 48(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
subsd %xmm1, %xmm0
mulsd 24(%rsp), %xmm0 # 8-byte Folded Reload
addsd %xmm1, %xmm0
addq $10088, %rsp # imm = 0x2768
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_10:
.cfi_def_cfa_offset 10112
movsd .LCPI0_3(%rip), %xmm0 # xmm0 = mem[0],zero
xorpd %xmm1, %xmm1
callq nextafter
movsd %xmm0, 24(%rsp) # 8-byte Spill
jmp .LBB0_11
.LBB0_19:
.Ltmp14:
movq %rax, %rdi
callq __clang_call_terminate
.LBB0_16:
.Ltmp5:
jmp .LBB0_18
.LBB0_13:
.Ltmp2:
movq %rax, %rbx
movq 88(%rsp), %rdi
cmpq %r14, %rdi
je .LBB0_15
# %bb.14: # %.critedge.i.i6.i
callq _ZdlPv
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.LBB0_17:
.Ltmp8:
.LBB0_18:
movq %rax, %rbx
.Ltmp9:
leaq 5088(%rsp), %rdi
callq _ZNSt13random_device7_M_finiEv
.Ltmp10:
.LBB0_15: # %common.resume
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.LBB0_20:
.Ltmp11:
movq %rax, %rdi
callq __clang_call_terminate
.Lfunc_end0:
.size _Z5fRanddd, .Lfunc_end0-_Z5fRanddd
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp13-.Ltmp12 # Call between .Ltmp12 and .Ltmp13
.uleb128 .Ltmp14-.Lfunc_begin0 # jumps to .Ltmp14
.byte 1 # On action: 1
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp9-.Ltmp13 # Call between .Ltmp13 and .Ltmp9
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 1 # On action: 1
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Lfunc_end0-.Ltmp10 # Call between .Ltmp10 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.text
.globl _Z30__device_stub__intersectTime_giP8ObstaclePd # -- Begin function _Z30__device_stub__intersectTime_giP8ObstaclePd
.p2align 4, 0x90
.type _Z30__device_stub__intersectTime_giP8ObstaclePd,@function
_Z30__device_stub__intersectTime_giP8ObstaclePd: # @_Z30__device_stub__intersectTime_giP8ObstaclePd
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15intersectTime_giP8ObstaclePd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z30__device_stub__intersectTime_giP8ObstaclePd, .Lfunc_end1-_Z30__device_stub__intersectTime_giP8ObstaclePd
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z15intersectTime_ciP8ObstaclePd
.LCPI2_0:
.quad 0xc000000000000000 # double -2
.LCPI2_1:
.quad 0x4000000000000000 # double 2
.text
.globl _Z15intersectTime_ciP8ObstaclePd
.p2align 4, 0x90
.type _Z15intersectTime_ciP8ObstaclePd,@function
_Z15intersectTime_ciP8ObstaclePd: # @_Z15intersectTime_ciP8ObstaclePd
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB2_10
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $24, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rsi, %r14
movl %edi, %r15d
addq $24, %r14
shlq $4, %r15
xorl %r12d, %r12d
xorpd %xmm2, %xmm2
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_6: # in Loop: Header=BB2_2 Depth=1
xorps %xmm0, %xmm0
sqrtsd %xmm3, %xmm0
.LBB2_8: # %.lr.ph.split.split
# in Loop: Header=BB2_2 Depth=1
divsd %xmm0, %xmm5
divsd %xmm0, %xmm1
movsd %xmm5, (%rbx,%r12)
movsd %xmm1, 8(%rbx,%r12)
addq $40, %r14
addq $16, %r12
cmpq %r12, %r15
je .LBB2_9
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsd -24(%r14), %xmm1 # xmm1 = mem[0],zero
movsd -16(%r14), %xmm0 # xmm0 = mem[0],zero
movsd -8(%r14), %xmm4 # xmm4 = mem[0],zero
movsd (%r14), %xmm3 # xmm3 = mem[0],zero
mulsd %xmm1, %xmm1
mulsd %xmm0, %xmm0
addsd %xmm1, %xmm0
ucomisd %xmm2, %xmm0
jb .LBB2_4
# %bb.3: # in Loop: Header=BB2_2 Depth=1
xorps %xmm1, %xmm1
sqrtsd %xmm0, %xmm1
jmp .LBB2_5
.p2align 4, 0x90
.LBB2_4: # %call.sqrt
# in Loop: Header=BB2_2 Depth=1
movsd %xmm3, 16(%rsp) # 8-byte Spill
movsd %xmm4, 8(%rsp) # 8-byte Spill
callq sqrt
movsd 8(%rsp), %xmm4 # 8-byte Reload
# xmm4 = mem[0],zero
movsd 16(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
xorpd %xmm2, %xmm2
movapd %xmm0, %xmm1
.LBB2_5: # %.lr.ph.split
# in Loop: Header=BB2_2 Depth=1
movapd %xmm1, %xmm5
addsd .LCPI2_0(%rip), %xmm5
addsd .LCPI2_1(%rip), %xmm1
mulsd %xmm4, %xmm4
mulsd %xmm3, %xmm3
addsd %xmm4, %xmm3
ucomisd %xmm2, %xmm3
jae .LBB2_6
# %bb.7: # %call.sqrt31
# in Loop: Header=BB2_2 Depth=1
movapd %xmm3, %xmm0
movsd %xmm1, 16(%rsp) # 8-byte Spill
movsd %xmm5, 8(%rsp) # 8-byte Spill
callq sqrt
movsd 8(%rsp), %xmm5 # 8-byte Reload
# xmm5 = mem[0],zero
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
xorpd %xmm2, %xmm2
jmp .LBB2_8
.LBB2_9:
addq $24, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB2_10: # %._crit_edge
retq
.Lfunc_end2:
.size _Z15intersectTime_ciP8ObstaclePd, .Lfunc_end2-_Z15intersectTime_ciP8ObstaclePd
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0xc059000000000000 # double -100
.LCPI3_1:
.quad 0x4059000000000000 # double 100
.LCPI3_2:
.quad 0x4014000000000000 # double 5
.LCPI3_3:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967296, %rax # imm = 0x100000000
xorl %ecx, %ecx
addq $256, %rax # imm = 0x100
movq %rax, 80(%rsp) # 8-byte Spill
movabsq $4607182418800017408, %r12 # imm = 0x3FF0000000000000
xorl %ebx, %ebx
jmp .LBB3_1
.p2align 4, 0x90
.LBB3_15: # in Loop: Header=BB3_1 Depth=1
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
movq 48(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %edi
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd 8(%rsp), %xmm0 # 8-byte Folded Reload
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq 24(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
movq 56(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
movq 32(%rsp), %rbx # 8-byte Reload
incq %rbx
movq 64(%rsp), %rcx # 8-byte Reload
addq $10, %rcx
cmpq $100, %rbx
je .LBB3_16
.LBB3_1: # =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
# Child Loop BB3_4 Depth 3
# Child Loop BB3_11 Depth 3
cmpq $1, %rcx
movq %rcx, 64(%rsp) # 8-byte Spill
movq %rcx, %rax
adcq $0, %rax
shlq $3, %rax
leaq (%rax,%rax,4), %rbp
leaq (%rbx,%rbx), %rax
leaq (%rax,%rax,4), %r14
imulq $400, %rbx, %r15 # imm = 0x190
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movq %r15, %rsi
movl $1, %edx
callq hipMallocManaged
movq %rbx, 32(%rsp) # 8-byte Spill
movq %rbx, %rax
shlq $5, %rax
leaq (%rax,%rax,4), %rsi
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
movl $1, %edx
callq hipMallocManaged
movq %r15, %rdi
leal 255(%r14), %ecx
shrl $8, %ecx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rcx
movq %rcx, 88(%rsp) # 8-byte Spill
movq %r14, 48(%rsp) # 8-byte Spill
leaq (%r14,%r14,4), %rax
movq %rax, 72(%rsp) # 8-byte Spill
xorpd %xmm0, %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
movsd %xmm0, 8(%rsp) # 8-byte Spill
xorl %r15d, %r15d
movq %rdi, 96(%rsp) # 8-byte Spill
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_14: # %_Z15intersectTime_ciP8ObstaclePd.exit
# in Loop: Header=BB3_2 Depth=2
movq 24(%rsp), %rsi
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.cfi_escape 0x2e, 0x00
callq clock
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movsd .LCPI3_3(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm1, %xmm0
movsd 8(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
addsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp) # 8-byte Spill
.cfi_escape 0x2e, 0x00
callq clock
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
callq clock
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI3_3(%rip), %xmm0
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
addsd %xmm0, %xmm1
movsd %xmm1, 16(%rsp) # 8-byte Spill
incl %r15d
cmpl $1000, %r15d # imm = 0x3E8
movq %r14, %rdi
je .LBB3_15
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB3_4 Depth 3
# Child Loop BB3_11 Depth 3
.cfi_escape 0x2e, 0x00
callq _Znam
movq %rax, %r13
cmpq $0, 32(%rsp) # 8-byte Folded Reload
je .LBB3_12
# %bb.3: # in Loop: Header=BB3_2 Depth=2
movq 72(%rsp), %rax # 8-byte Reload
leaq (,%rax,8), %r14
addq %r13, %r14
movq %r13, %rbx
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_1 Depth=1
# Parent Loop BB3_2 Depth=2
# => This Inner Loop Header: Depth=3
.Ltmp15:
.cfi_escape 0x2e, 0x00
movsd .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero
callq _Z5fRanddd
.Ltmp16:
# %bb.5: # %.noexc
# in Loop: Header=BB3_4 Depth=3
movsd %xmm0, (%rbx)
.Ltmp17:
.cfi_escape 0x2e, 0x00
movsd .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero
callq _Z5fRanddd
.Ltmp18:
# %bb.6: # %.noexc50
# in Loop: Header=BB3_4 Depth=3
movsd %xmm0, 8(%rbx)
.Ltmp19:
.cfi_escape 0x2e, 0x00
xorpd %xmm0, %xmm0
movsd .LCPI3_2(%rip), %xmm1 # xmm1 = mem[0],zero
callq _Z5fRanddd
.Ltmp20:
# %bb.7: # %.noexc51
# in Loop: Header=BB3_4 Depth=3
movsd %xmm0, 16(%rbx)
.Ltmp21:
.cfi_escape 0x2e, 0x00
xorpd %xmm0, %xmm0
movsd .LCPI3_2(%rip), %xmm1 # xmm1 = mem[0],zero
callq _Z5fRanddd
.Ltmp22:
# %bb.8: # %_ZN8ObstacleC2Ev.exit
# in Loop: Header=BB3_4 Depth=3
movsd %xmm0, 24(%rbx)
movq %r12, 32(%rbx)
addq $40, %rbx
cmpq %r14, %rbx
jne .LBB3_4
# %bb.9: # %.loopexit
# in Loop: Header=BB3_2 Depth=2
cmpq $0, 32(%rsp) # 8-byte Folded Reload
movsd .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero
movsd .LCPI3_1(%rip), %xmm2 # xmm2 = mem[0],zero
je .LBB3_12
# %bb.10: # %.lr.ph.preheader
# in Loop: Header=BB3_2 Depth=2
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_11: # %.lr.ph
# Parent Loop BB3_1 Depth=1
# Parent Loop BB3_2 Depth=2
# => This Inner Loop Header: Depth=3
.cfi_escape 0x2e, 0x00
movapd %xmm1, %xmm0
movaps %xmm2, %xmm1
callq _Z5fRanddd
movsd %xmm0, 120(%rsp) # 8-byte Spill
.cfi_escape 0x2e, 0x00
movsd .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero
callq _Z5fRanddd
movsd %xmm0, 112(%rsp) # 8-byte Spill
.cfi_escape 0x2e, 0x00
xorpd %xmm0, %xmm0
movsd .LCPI3_2(%rip), %xmm1 # xmm1 = mem[0],zero
callq _Z5fRanddd
movsd %xmm0, 104(%rsp) # 8-byte Spill
.cfi_escape 0x2e, 0x00
xorpd %xmm0, %xmm0
movsd .LCPI3_2(%rip), %xmm1 # xmm1 = mem[0],zero
callq _Z5fRanddd
movsd .LCPI3_1(%rip), %xmm2 # xmm2 = mem[0],zero
movsd .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero
movsd 120(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
movsd %xmm3, (%r13,%rbx)
movsd 112(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
movsd %xmm3, 8(%r13,%rbx)
movsd 104(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
movsd %xmm3, 16(%r13,%rbx)
movsd %xmm0, 24(%r13,%rbx)
movq %r12, 32(%r13,%rbx)
addq $40, %rbx
cmpq %rbx, %rbp
jne .LBB3_11
.LBB3_12: # %._crit_edge
# in Loop: Header=BB3_2 Depth=2
movq 24(%rsp), %rdi
.cfi_escape 0x2e, 0x00
movq %r13, %rsi
movq 96(%rsp), %r14 # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
.cfi_escape 0x2e, 0x00
callq clock
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movq 88(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq 80(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_14
# %bb.13: # in Loop: Header=BB3_2 Depth=2
movq 24(%rsp), %rax
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx # 8-byte Reload
movl %edx, 44(%rsp)
movq %rax, 184(%rsp)
movq %rcx, 176(%rsp)
leaq 44(%rsp), %rax
movq %rax, 192(%rsp)
leaq 184(%rsp), %rax
movq %rax, 200(%rsp)
leaq 176(%rsp), %rax
movq %rax, 208(%rsp)
.cfi_escape 0x2e, 0x00
leaq 160(%rsp), %rdi
leaq 144(%rsp), %rsi
leaq 136(%rsp), %rdx
leaq 128(%rsp), %rcx
callq __hipPopCallConfiguration
movq 160(%rsp), %rsi
movl 168(%rsp), %edx
movq 144(%rsp), %rcx
movl 152(%rsp), %r8d
.cfi_escape 0x2e, 0x10
movl $_Z15intersectTime_giP8ObstaclePd, %edi
leaq 192(%rsp), %r9
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 144(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_14
.LBB3_16:
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_17:
.cfi_def_cfa_offset 272
.Ltmp23:
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _ZdaPv
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table3:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Lfunc_begin1-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp15-.Lfunc_begin1 # Call between .Lfunc_begin1 and .Ltmp15
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp22-.Ltmp15 # Call between .Ltmp15 and .Ltmp22
.uleb128 .Ltmp23-.Lfunc_begin1 # jumps to .Ltmp23
.byte 0 # On action: cleanup
.uleb128 .Ltmp22-.Lfunc_begin1 # >> Call Site 3 <<
.uleb128 .Lfunc_end3-.Ltmp22 # Call between .Ltmp22 and .Lfunc_end3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.p2align 2, 0x0
# -- End function
.section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat
.hidden __clang_call_terminate # -- Begin function __clang_call_terminate
.weak __clang_call_terminate
.p2align 4, 0x90
.type __clang_call_terminate,@function
__clang_call_terminate: # @__clang_call_terminate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq __cxa_begin_catch
callq _ZSt9terminatev
.Lfunc_end4:
.size __clang_call_terminate, .Lfunc_end4-__clang_call_terminate
.cfi_endproc
# -- End function
.section .text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,comdat
.weak _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv # -- Begin function _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.p2align 4, 0x90
.type _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,@function
_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv: # @_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.cfi_startproc
# %bb.0:
cmpq $624, 4992(%rdi) # imm = 0x270
jb .LBB5_6
# %bb.1: # %.preheader.preheader
movl $2567483615, %eax # imm = 0x9908B0DF
xorl %edx, %edx
movq $-2147483648, %rcx # imm = 0x80000000
.p2align 4, 0x90
.LBB5_2: # %.preheader
# =>This Inner Loop Header: Depth=1
movq (%rdi,%rdx,8), %rsi
andq %rcx, %rsi
movq 8(%rdi,%rdx,8), %r8
movl %r8d, %r9d
andl $2147483646, %r9d # imm = 0x7FFFFFFE
orq %rsi, %r9
shrq %r9
xorq 3176(%rdi,%rdx,8), %r9
andl $1, %r8d
negl %r8d
andl %eax, %r8d
xorq %r9, %r8
movq %r8, (%rdi,%rdx,8)
leaq 1(%rdx), %rsi
movq %rsi, %rdx
cmpq $227, %rsi
jne .LBB5_2
# %bb.3: # %.preheader.i.preheader
movl $228, %ecx
movq $-2147483648, %rdx # imm = 0x80000000
.p2align 4, 0x90
.LBB5_4: # %.preheader.i
# =>This Inner Loop Header: Depth=1
movq -8(%rdi,%rcx,8), %rsi
andq %rdx, %rsi
movq (%rdi,%rcx,8), %r8
movl %r8d, %r9d
andl $2147483646, %r9d # imm = 0x7FFFFFFE
orq %rsi, %r9
shrq %r9
xorq -1824(%rdi,%rcx,8), %r9
andl $1, %r8d
negl %r8d
andl %eax, %r8d
xorq %r9, %r8
movq %r8, -8(%rdi,%rcx,8)
incq %rcx
cmpq $624, %rcx # imm = 0x270
jne .LBB5_4
# %bb.5: # %_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv.exit
movq $-2147483648, %rcx # imm = 0x80000000
andq 4984(%rdi), %rcx
movq (%rdi), %rdx
movl %edx, %esi
andl $2147483646, %esi # imm = 0x7FFFFFFE
orq %rcx, %rsi
shrq %rsi
xorq 3168(%rdi), %rsi
andl $1, %edx
negl %edx
andl %eax, %edx
xorq %rsi, %rdx
movq %rdx, 4984(%rdi)
movq $0, 4992(%rdi)
.LBB5_6:
movq 4992(%rdi), %rax
leaq 1(%rax), %rcx
movq %rcx, 4992(%rdi)
movq (%rdi,%rax,8), %rax
movq %rax, %rcx
shrq $11, %rcx
movl %ecx, %ecx
xorq %rax, %rcx
movl %ecx, %eax
shll $7, %eax
andl $-1658038656, %eax # imm = 0x9D2C5680
xorq %rcx, %rax
movl %eax, %ecx
shll $15, %ecx
andl $-272236544, %ecx # imm = 0xEFC60000
xorq %rax, %rcx
movq %rcx, %rax
shrq $18, %rax
xorq %rcx, %rax
retq
.Lfunc_end5:
.size _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv, .Lfunc_end5-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15intersectTime_giP8ObstaclePd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15intersectTime_giP8ObstaclePd,@object # @_Z15intersectTime_giP8ObstaclePd
.section .rodata,"a",@progbits
.globl _Z15intersectTime_giP8ObstaclePd
.p2align 3, 0x0
_Z15intersectTime_giP8ObstaclePd:
.quad _Z30__device_stub__intersectTime_giP8ObstaclePd
.size _Z15intersectTime_giP8ObstaclePd, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d GPU: %.8lf s "
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CPU: %.8lf s "
.size .L.str.1, 16
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%.2lf \n"
.size .L.str.2, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "default"
.size .L.str.3, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z15intersectTime_giP8ObstaclePd"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Z30__device_stub__intersectTime_giP8ObstaclePd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z15intersectTime_giP8ObstaclePd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void clock_block(clock_t* d_o, volatile long clock_count)
{
volatile long clock_offset = 0;
long temp_clock = clock_count;
while (clock_offset < temp_clock)
{
clock_offset++;
}
d_o[0] = clock_offset;
}
/*
__global__ void clock_block(clock_t* d_o, clock_t clock_count)
{
clock_t start_clock = clock64();
clock_t clock_offset = 0;
while (clock_offset < clock_count)
{
clock_offset = clock64() - start_clock;
}
d_o[0] = clock_offset;
}
*/ | code for sm_80
Function : _Z11clock_blockPll
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ISETP.LT.U32.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe20003f01070 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x000fe4000001ff00 */
/*0050*/ ISETP.GT.AND.EX P0, PT, R2, RZ, PT, P0 ; /* 0x000000ff0200720c */
/* 0x000fda0003f04300 */
/*0060*/ @!P0 BRA 0x210 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0070*/ IADD3 R0, P0, -R4, c[0x0][0x168], RZ ; /* 0x00005a0004007a10 */
/* 0x000fc80007f1e1ff */
/*0080*/ ISETP.GT.U32.AND P1, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f24070 */
/*0090*/ IADD3.X R0, ~R5, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0005007a10 */
/* 0x000fe400007fe5ff */
/*00a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*00b0*/ ISETP.GT.AND.EX P1, PT, R0, RZ, PT, P1 ; /* 0x000000ff0000720c */
/* 0x000fda0003f24310 */
/*00c0*/ @!P1 BRA 0x160 ; /* 0x0000009000009947 */
/* 0x000fea0003800000 */
/*00d0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fe200078e00ff */
/*00e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80003f0e170 */
/*00f0*/ IADD3 R0, P1, R0, -0x3, RZ ; /* 0xfffffffd00007810 */
/* 0x000fc80007f3e0ff */
/*0100*/ IADD3.X R2, R2, -0x1, RZ, P1, !PT ; /* 0xffffffff02027810 */
/* 0x000fe40000ffe4ff */
/*0110*/ IADD3 R4, P1, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fca0007f3e0ff */
/*0120*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0605 */
/*0130*/ ISETP.GE.U32.AND P1, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fc80003f26070 */
/*0140*/ ISETP.GE.AND.EX P1, PT, R5, R2, PT, P1 ; /* 0x000000020500720c */
/* 0x000fda0003f26310 */
/*0150*/ @!P1 BRA 0x110 ; /* 0xffffffb000009947 */
/* 0x000fea000383ffff */
/*0160*/ IADD3 R0, P2, -R4, c[0x0][0x168], RZ ; /* 0x00005a0004007a10 */
/* 0x000fc80007f5e1ff */
/*0170*/ ISETP.GT.U32.AND P1, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe40003f24070 */
/*0180*/ IADD3.X R0, ~R5, c[0x0][0x16c], RZ, P2, !PT ; /* 0x00005b0005007a10 */
/* 0x000fc800017fe5ff */
/*0190*/ ISETP.GT.AND.EX P1, PT, R0, RZ, PT, P1 ; /* 0x000000ff0000720c */
/* 0x000fda0003f24310 */
/*01a0*/ @P1 PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000181c */
/* 0x000fe40003f0e170 */
/*01b0*/ @P1 IADD3 R4, P2, R4, 0x2, RZ ; /* 0x0000000204041810 */
/* 0x000fca0007f5e0ff */
/*01c0*/ @P1 IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff051224 */
/* 0x000fe200010e0605 */
/*01d0*/ ISETP.LT.U32.AND P1, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fca0003f21070 */
/*01e0*/ ISETP.LT.OR.EX P0, PT, R5, c[0x0][0x16c], P0, P1 ; /* 0x00005b0005007a0c */
/* 0x000fda0000701710 */
/*01f0*/ @P0 IADD3 R4, P1, R4, 0x1, RZ ; /* 0x0000000104040810 */
/* 0x000fca0007f3e0ff */
/*0200*/ @P0 IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff050224 */
/* 0x000fe400008e0605 */
/*0210*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe400078e00ff */
/*0220*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*0230*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101b04 */
/*0240*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0250*/ BRA 0x250; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void clock_block(clock_t* d_o, volatile long clock_count)
{
volatile long clock_offset = 0;
long temp_clock = clock_count;
while (clock_offset < temp_clock)
{
clock_offset++;
}
d_o[0] = clock_offset;
}
/*
__global__ void clock_block(clock_t* d_o, clock_t clock_count)
{
clock_t start_clock = clock64();
clock_t clock_offset = 0;
while (clock_offset < clock_count)
{
clock_offset = clock64() - start_clock;
}
d_o[0] = clock_offset;
}
*/ | .file "tmpxft_0014e0da_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z11clock_blockPllPll
.type _Z32__device_stub__Z11clock_blockPllPll, @function
_Z32__device_stub__Z11clock_blockPllPll:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11clock_blockPll(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z11clock_blockPllPll, .-_Z32__device_stub__Z11clock_blockPllPll
.globl _Z11clock_blockPll
.type _Z11clock_blockPll, @function
_Z11clock_blockPll:
.LFB2052:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rsi, 8(%rsp)
movq 8(%rsp), %rsi
call _Z32__device_stub__Z11clock_blockPllPll
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11clock_blockPll, .-_Z11clock_blockPll
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11clock_blockPll"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11clock_blockPll(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void clock_block(clock_t* d_o, volatile long clock_count)
{
volatile long clock_offset = 0;
long temp_clock = clock_count;
while (clock_offset < temp_clock)
{
clock_offset++;
}
d_o[0] = clock_offset;
}
/*
__global__ void clock_block(clock_t* d_o, clock_t clock_count)
{
clock_t start_clock = clock64();
clock_t clock_offset = 0;
while (clock_offset < clock_count)
{
clock_offset = clock64() - start_clock;
}
d_o[0] = clock_offset;
}
*/ | #include <hip/hip_runtime.h>
__global__ void clock_block(clock_t* d_o, volatile long clock_count)
{
volatile long clock_offset = 0;
long temp_clock = clock_count;
while (clock_offset < temp_clock)
{
clock_offset++;
}
d_o[0] = clock_offset;
}
/*
__global__ void clock_block(clock_t* d_o, clock_t clock_count)
{
clock_t start_clock = clock64();
clock_t clock_offset = 0;
while (clock_offset < clock_count)
{
clock_offset = clock64() - start_clock;
}
d_o[0] = clock_offset;
}
*/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void clock_block(clock_t* d_o, volatile long clock_count)
{
volatile long clock_offset = 0;
long temp_clock = clock_count;
while (clock_offset < temp_clock)
{
clock_offset++;
}
d_o[0] = clock_offset;
}
/*
__global__ void clock_block(clock_t* d_o, clock_t clock_count)
{
clock_t start_clock = clock64();
clock_t clock_offset = 0;
while (clock_offset < clock_count)
{
clock_offset = clock64() - start_clock;
}
d_o[0] = clock_offset;
}
*/ | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11clock_blockPll
.globl _Z11clock_blockPll
.p2align 8
.type _Z11clock_blockPll,@function
_Z11clock_blockPll:
s_load_b64 s[4:5], s[0:1], 0x8
s_mov_b64 s[2:3], src_private_base
s_mov_b32 s2, 8
v_mov_b32_e32 v0, 0
v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
s_mov_b32 s2, 16
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v7, s3 :: v_dual_mov_b32 v6, s2
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v4, s4
v_mov_b32_e32 v5, s5
s_mov_b32 s5, 0
s_mov_b32 s4, exec_lo
flat_store_b64 v[2:3], v[4:5] dlc
s_waitcnt_vscnt null, 0x0
flat_store_b64 v[6:7], v[0:1] dlc
s_waitcnt_vscnt null, 0x0
flat_load_b64 v[0:1], v[2:3] glc dlc
s_waitcnt vmcnt(0)
flat_load_b64 v[2:3], v[6:7] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmpx_lt_i64_e64 v[2:3], v[0:1]
s_cbranch_execz .LBB0_3
s_mov_b64 s[6:7], src_private_base
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mov_b32 s3, s7
v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
.LBB0_2:
flat_load_b64 v[4:5], v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
flat_store_b64 v[2:3], v[4:5] dlc
s_waitcnt_vscnt null, 0x0
flat_load_b64 v[4:5], v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_ge_i64_e32 vcc_lo, v[4:5], v[0:1]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s4
s_mov_b64 s[2:3], src_private_base
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 16 :: v_dual_mov_b32 v1, s3
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v2, 0
flat_load_b64 v[0:1], v[0:1] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
global_store_b64 v2, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11clock_blockPll
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 24
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11clock_blockPll, .Lfunc_end0-_Z11clock_blockPll
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11clock_blockPll
.private_segment_fixed_size: 24
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z11clock_blockPll.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void clock_block(clock_t* d_o, volatile long clock_count)
{
volatile long clock_offset = 0;
long temp_clock = clock_count;
while (clock_offset < temp_clock)
{
clock_offset++;
}
d_o[0] = clock_offset;
}
/*
__global__ void clock_block(clock_t* d_o, clock_t clock_count)
{
clock_t start_clock = clock64();
clock_t clock_offset = 0;
while (clock_offset < clock_count)
{
clock_offset = clock64() - start_clock;
}
d_o[0] = clock_offset;
}
*/ | .text
.file "test.hip"
.globl _Z26__device_stub__clock_blockPll # -- Begin function _Z26__device_stub__clock_blockPll
.p2align 4, 0x90
.type _Z26__device_stub__clock_blockPll,@function
_Z26__device_stub__clock_blockPll: # @_Z26__device_stub__clock_blockPll
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11clock_blockPll, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__clock_blockPll, .Lfunc_end0-_Z26__device_stub__clock_blockPll
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11clock_blockPll, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11clock_blockPll,@object # @_Z11clock_blockPll
.section .rodata,"a",@progbits
.globl _Z11clock_blockPll
.p2align 3, 0x0
_Z11clock_blockPll:
.quad _Z26__device_stub__clock_blockPll
.size _Z11clock_blockPll, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11clock_blockPll"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__clock_blockPll
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11clock_blockPll
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11clock_blockPll
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ISETP.LT.U32.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe20003f01070 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x000fe4000001ff00 */
/*0050*/ ISETP.GT.AND.EX P0, PT, R2, RZ, PT, P0 ; /* 0x000000ff0200720c */
/* 0x000fda0003f04300 */
/*0060*/ @!P0 BRA 0x210 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0070*/ IADD3 R0, P0, -R4, c[0x0][0x168], RZ ; /* 0x00005a0004007a10 */
/* 0x000fc80007f1e1ff */
/*0080*/ ISETP.GT.U32.AND P1, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f24070 */
/*0090*/ IADD3.X R0, ~R5, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0005007a10 */
/* 0x000fe400007fe5ff */
/*00a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*00b0*/ ISETP.GT.AND.EX P1, PT, R0, RZ, PT, P1 ; /* 0x000000ff0000720c */
/* 0x000fda0003f24310 */
/*00c0*/ @!P1 BRA 0x160 ; /* 0x0000009000009947 */
/* 0x000fea0003800000 */
/*00d0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fe200078e00ff */
/*00e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80003f0e170 */
/*00f0*/ IADD3 R0, P1, R0, -0x3, RZ ; /* 0xfffffffd00007810 */
/* 0x000fc80007f3e0ff */
/*0100*/ IADD3.X R2, R2, -0x1, RZ, P1, !PT ; /* 0xffffffff02027810 */
/* 0x000fe40000ffe4ff */
/*0110*/ IADD3 R4, P1, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fca0007f3e0ff */
/*0120*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0605 */
/*0130*/ ISETP.GE.U32.AND P1, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fc80003f26070 */
/*0140*/ ISETP.GE.AND.EX P1, PT, R5, R2, PT, P1 ; /* 0x000000020500720c */
/* 0x000fda0003f26310 */
/*0150*/ @!P1 BRA 0x110 ; /* 0xffffffb000009947 */
/* 0x000fea000383ffff */
/*0160*/ IADD3 R0, P2, -R4, c[0x0][0x168], RZ ; /* 0x00005a0004007a10 */
/* 0x000fc80007f5e1ff */
/*0170*/ ISETP.GT.U32.AND P1, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe40003f24070 */
/*0180*/ IADD3.X R0, ~R5, c[0x0][0x16c], RZ, P2, !PT ; /* 0x00005b0005007a10 */
/* 0x000fc800017fe5ff */
/*0190*/ ISETP.GT.AND.EX P1, PT, R0, RZ, PT, P1 ; /* 0x000000ff0000720c */
/* 0x000fda0003f24310 */
/*01a0*/ @P1 PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000181c */
/* 0x000fe40003f0e170 */
/*01b0*/ @P1 IADD3 R4, P2, R4, 0x2, RZ ; /* 0x0000000204041810 */
/* 0x000fca0007f5e0ff */
/*01c0*/ @P1 IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff051224 */
/* 0x000fe200010e0605 */
/*01d0*/ ISETP.LT.U32.AND P1, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fca0003f21070 */
/*01e0*/ ISETP.LT.OR.EX P0, PT, R5, c[0x0][0x16c], P0, P1 ; /* 0x00005b0005007a0c */
/* 0x000fda0000701710 */
/*01f0*/ @P0 IADD3 R4, P1, R4, 0x1, RZ ; /* 0x0000000104040810 */
/* 0x000fca0007f3e0ff */
/*0200*/ @P0 IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff050224 */
/* 0x000fe400008e0605 */
/*0210*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe400078e00ff */
/*0220*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*0230*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101b04 */
/*0240*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0250*/ BRA 0x250; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11clock_blockPll
.globl _Z11clock_blockPll
.p2align 8
.type _Z11clock_blockPll,@function
_Z11clock_blockPll:
s_load_b64 s[4:5], s[0:1], 0x8
s_mov_b64 s[2:3], src_private_base
s_mov_b32 s2, 8
v_mov_b32_e32 v0, 0
v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
s_mov_b32 s2, 16
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v7, s3 :: v_dual_mov_b32 v6, s2
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v4, s4
v_mov_b32_e32 v5, s5
s_mov_b32 s5, 0
s_mov_b32 s4, exec_lo
flat_store_b64 v[2:3], v[4:5] dlc
s_waitcnt_vscnt null, 0x0
flat_store_b64 v[6:7], v[0:1] dlc
s_waitcnt_vscnt null, 0x0
flat_load_b64 v[0:1], v[2:3] glc dlc
s_waitcnt vmcnt(0)
flat_load_b64 v[2:3], v[6:7] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmpx_lt_i64_e64 v[2:3], v[0:1]
s_cbranch_execz .LBB0_3
s_mov_b64 s[6:7], src_private_base
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mov_b32 s3, s7
v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
.LBB0_2:
flat_load_b64 v[4:5], v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
flat_store_b64 v[2:3], v[4:5] dlc
s_waitcnt_vscnt null, 0x0
flat_load_b64 v[4:5], v[2:3] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_ge_i64_e32 vcc_lo, v[4:5], v[0:1]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s4
s_mov_b64 s[2:3], src_private_base
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 16 :: v_dual_mov_b32 v1, s3
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v2, 0
flat_load_b64 v[0:1], v[0:1] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
global_store_b64 v2, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11clock_blockPll
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 24
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11clock_blockPll, .Lfunc_end0-_Z11clock_blockPll
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11clock_blockPll
.private_segment_fixed_size: 24
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z11clock_blockPll.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014e0da_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z11clock_blockPllPll
.type _Z32__device_stub__Z11clock_blockPllPll, @function
_Z32__device_stub__Z11clock_blockPllPll:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11clock_blockPll(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z11clock_blockPllPll, .-_Z32__device_stub__Z11clock_blockPllPll
.globl _Z11clock_blockPll
.type _Z11clock_blockPll, @function
_Z11clock_blockPll:
.LFB2052:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rsi, 8(%rsp)
movq 8(%rsp), %rsi
call _Z32__device_stub__Z11clock_blockPllPll
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11clock_blockPll, .-_Z11clock_blockPll
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11clock_blockPll"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11clock_blockPll(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl _Z26__device_stub__clock_blockPll # -- Begin function _Z26__device_stub__clock_blockPll
.p2align 4, 0x90
.type _Z26__device_stub__clock_blockPll,@function
_Z26__device_stub__clock_blockPll: # @_Z26__device_stub__clock_blockPll
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11clock_blockPll, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__clock_blockPll, .Lfunc_end0-_Z26__device_stub__clock_blockPll
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11clock_blockPll, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11clock_blockPll,@object # @_Z11clock_blockPll
.section .rodata,"a",@progbits
.globl _Z11clock_blockPll
.p2align 3, 0x0
_Z11clock_blockPll:
.quad _Z26__device_stub__clock_blockPll
.size _Z11clock_blockPll, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11clock_blockPll"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__clock_blockPll
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11clock_blockPll
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
// Función kernel que se ejecuta en la GPU
__global__ void saxpy(float *x, float *y, float a, int numElementos)
{
int tid= blockDim.x * blockIdx.x + threadIdx.x;
if (tid < numElementos)
{
y[tid] = a * x[tid] + y[tid];
}
}
int main(void)
{
// Definimos tamaños: 1M de elementos (2^20)
int numElementos = 1<<20; //
size_t tamano = numElementos * sizeof(float);
//Definimos variables
float *h_x, *h_y, *d_x, *d_y;
// Reservamos memoria en el host
h_x = (float *)malloc(tamano);
h_y = (float *)malloc(tamano);
// Asignamos valores en el host
for (int i = 0; i < numElementos; i++)
{
h_x[i] = 1.0f;
h_y[i] = 2.0f;
}
float a = 5.0f;
// Reservamos memoria en el device
cudaMalloc(&d_x, tamano);
cudaMalloc(&d_y, tamano);
// Traspasamos datos de host a device
cudaMemcpy(d_x, h_x, tamano, cudaMemcpyHostToDevice);
cudaMemcpy(d_y, h_y, tamano, cudaMemcpyHostToDevice);
//Lanzamos el kernel CUDA
int hilosPorBloque = 8;
int totalBloques =(numElementos + hilosPorBloque - 1) / hilosPorBloque;
saxpy<<<totalBloques, hilosPorBloque>>>(d_x, d_y, 5.0f, tamano);
// Traspasamos datos de device a host
cudaMemcpy(h_y, d_y, tamano, cudaMemcpyDeviceToHost);
// Verificamos resultado
float Error = 0.0f;
int i;
for (i = 0; i < 10; i++) {
Error = Error + abs(h_y[i] - 7.0f);
printf("%2.8f", h_x[i]);
}
printf("Error: %f\n", Error);
// Liberamos memoria device
cudaFree(d_x);
cudaFree(d_y);
// Liberamos memoria host
free(h_x);
free(h_y);
return 0;
} | code for sm_80
Function : _Z5saxpyPfS_fi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x174], PT ; /* 0x00005d0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe400078e0205 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FFMA R7, R2, c[0x0][0x170], R7 ; /* 0x00005c0002077a23 */
/* 0x004fca0000000007 */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
// Función kernel que se ejecuta en la GPU
__global__ void saxpy(float *x, float *y, float a, int numElementos)
{
int tid= blockDim.x * blockIdx.x + threadIdx.x;
if (tid < numElementos)
{
y[tid] = a * x[tid] + y[tid];
}
}
int main(void)
{
// Definimos tamaños: 1M de elementos (2^20)
int numElementos = 1<<20; //
size_t tamano = numElementos * sizeof(float);
//Definimos variables
float *h_x, *h_y, *d_x, *d_y;
// Reservamos memoria en el host
h_x = (float *)malloc(tamano);
h_y = (float *)malloc(tamano);
// Asignamos valores en el host
for (int i = 0; i < numElementos; i++)
{
h_x[i] = 1.0f;
h_y[i] = 2.0f;
}
float a = 5.0f;
// Reservamos memoria en el device
cudaMalloc(&d_x, tamano);
cudaMalloc(&d_y, tamano);
// Traspasamos datos de host a device
cudaMemcpy(d_x, h_x, tamano, cudaMemcpyHostToDevice);
cudaMemcpy(d_y, h_y, tamano, cudaMemcpyHostToDevice);
//Lanzamos el kernel CUDA
int hilosPorBloque = 8;
int totalBloques =(numElementos + hilosPorBloque - 1) / hilosPorBloque;
saxpy<<<totalBloques, hilosPorBloque>>>(d_x, d_y, 5.0f, tamano);
// Traspasamos datos de device a host
cudaMemcpy(h_y, d_y, tamano, cudaMemcpyDeviceToHost);
// Verificamos resultado
float Error = 0.0f;
int i;
for (i = 0; i < 10; i++) {
Error = Error + abs(h_y[i] - 7.0f);
printf("%2.8f", h_x[i]);
}
printf("Error: %f\n", Error);
// Liberamos memoria device
cudaFree(d_x);
cudaFree(d_y);
// Liberamos memoria host
free(h_x);
free(h_y);
return 0;
} | .file "tmpxft_0018f03b_00000000-6_saxpy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z5saxpyPfS_fiPfS_fi
.type _Z28__device_stub__Z5saxpyPfS_fiPfS_fi, @function
_Z28__device_stub__Z5saxpyPfS_fiPfS_fi:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5saxpyPfS_fi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z5saxpyPfS_fiPfS_fi, .-_Z28__device_stub__Z5saxpyPfS_fiPfS_fi
.globl _Z5saxpyPfS_fi
.type _Z5saxpyPfS_fi, @function
_Z5saxpyPfS_fi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5saxpyPfS_fiPfS_fi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5saxpyPfS_fi, .-_Z5saxpyPfS_fi
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "%2.8f"
.LC7:
.string "Error: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %eax
movss .LC1(%rip), %xmm1
movss .LC2(%rip), %xmm0
.L12:
movss %xmm1, 0(%rbp,%rax)
movss %xmm0, (%rbx,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L12
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $8, 44(%rsp)
movl $1, 48(%rsp)
movl $131072, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $4194304, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0, %r12d
movl $0x00000000, 12(%rsp)
leaq .LC6(%rip), %r13
.L14:
movss (%rbx,%r12), %xmm0
subss .LC4(%rip), %xmm0
andps .LC5(%rip), %xmm0
addss 12(%rsp), %xmm0
movss %xmm0, 12(%rsp)
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%r12), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %r12
cmpq $40, %r12
jne .L14
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $4194304, %edx
movss .LC3(%rip), %xmm0
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z28__device_stub__Z5saxpyPfS_fiPfS_fi
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z5saxpyPfS_fi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z5saxpyPfS_fi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1073741824
.align 4
.LC3:
.long 1084227584
.align 4
.LC4:
.long 1088421888
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC5:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
// Función kernel que se ejecuta en la GPU
__global__ void saxpy(float *x, float *y, float a, int numElementos)
{
int tid= blockDim.x * blockIdx.x + threadIdx.x;
if (tid < numElementos)
{
y[tid] = a * x[tid] + y[tid];
}
}
int main(void)
{
// Definimos tamaños: 1M de elementos (2^20)
int numElementos = 1<<20; //
size_t tamano = numElementos * sizeof(float);
//Definimos variables
float *h_x, *h_y, *d_x, *d_y;
// Reservamos memoria en el host
h_x = (float *)malloc(tamano);
h_y = (float *)malloc(tamano);
// Asignamos valores en el host
for (int i = 0; i < numElementos; i++)
{
h_x[i] = 1.0f;
h_y[i] = 2.0f;
}
float a = 5.0f;
// Reservamos memoria en el device
cudaMalloc(&d_x, tamano);
cudaMalloc(&d_y, tamano);
// Traspasamos datos de host a device
cudaMemcpy(d_x, h_x, tamano, cudaMemcpyHostToDevice);
cudaMemcpy(d_y, h_y, tamano, cudaMemcpyHostToDevice);
//Lanzamos el kernel CUDA
int hilosPorBloque = 8;
int totalBloques =(numElementos + hilosPorBloque - 1) / hilosPorBloque;
saxpy<<<totalBloques, hilosPorBloque>>>(d_x, d_y, 5.0f, tamano);
// Traspasamos datos de device a host
cudaMemcpy(h_y, d_y, tamano, cudaMemcpyDeviceToHost);
// Verificamos resultado
float Error = 0.0f;
int i;
for (i = 0; i < 10; i++) {
Error = Error + abs(h_y[i] - 7.0f);
printf("%2.8f", h_x[i]);
}
printf("Error: %f\n", Error);
// Liberamos memoria device
cudaFree(d_x);
cudaFree(d_y);
// Liberamos memoria host
free(h_x);
free(h_y);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
// Función kernel que se ejecuta en la GPU
__global__ void saxpy(float *x, float *y, float a, int numElementos)
{
int tid= blockDim.x * blockIdx.x + threadIdx.x;
if (tid < numElementos)
{
y[tid] = a * x[tid] + y[tid];
}
}
int main(void)
{
// Definimos tamaños: 1M de elementos (2^20)
int numElementos = 1<<20; //
size_t tamano = numElementos * sizeof(float);
//Definimos variables
float *h_x, *h_y, *d_x, *d_y;
// Reservamos memoria en el host
h_x = (float *)malloc(tamano);
h_y = (float *)malloc(tamano);
// Asignamos valores en el host
for (int i = 0; i < numElementos; i++)
{
h_x[i] = 1.0f;
h_y[i] = 2.0f;
}
float a = 5.0f;
// Reservamos memoria en el device
hipMalloc(&d_x, tamano);
hipMalloc(&d_y, tamano);
// Traspasamos datos de host a device
hipMemcpy(d_x, h_x, tamano, hipMemcpyHostToDevice);
hipMemcpy(d_y, h_y, tamano, hipMemcpyHostToDevice);
//Lanzamos el kernel CUDA
int hilosPorBloque = 8;
int totalBloques =(numElementos + hilosPorBloque - 1) / hilosPorBloque;
saxpy<<<totalBloques, hilosPorBloque>>>(d_x, d_y, 5.0f, tamano);
// Traspasamos datos de device a host
hipMemcpy(h_y, d_y, tamano, hipMemcpyDeviceToHost);
// Verificamos resultado
float Error = 0.0f;
int i;
for (i = 0; i < 10; i++) {
Error = Error + abs(h_y[i] - 7.0f);
printf("%2.8f", h_x[i]);
}
printf("Error: %f\n", Error);
// Liberamos memoria device
hipFree(d_x);
hipFree(d_y);
// Liberamos memoria host
free(h_x);
free(h_y);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
// Función kernel que se ejecuta en la GPU
__global__ void saxpy(float *x, float *y, float a, int numElementos)
{
int tid= blockDim.x * blockIdx.x + threadIdx.x;
if (tid < numElementos)
{
y[tid] = a * x[tid] + y[tid];
}
}
int main(void)
{
// Definimos tamaños: 1M de elementos (2^20)
int numElementos = 1<<20; //
size_t tamano = numElementos * sizeof(float);
//Definimos variables
float *h_x, *h_y, *d_x, *d_y;
// Reservamos memoria en el host
h_x = (float *)malloc(tamano);
h_y = (float *)malloc(tamano);
// Asignamos valores en el host
for (int i = 0; i < numElementos; i++)
{
h_x[i] = 1.0f;
h_y[i] = 2.0f;
}
float a = 5.0f;
// Reservamos memoria en el device
hipMalloc(&d_x, tamano);
hipMalloc(&d_y, tamano);
// Traspasamos datos de host a device
hipMemcpy(d_x, h_x, tamano, hipMemcpyHostToDevice);
hipMemcpy(d_y, h_y, tamano, hipMemcpyHostToDevice);
//Lanzamos el kernel CUDA
int hilosPorBloque = 8;
int totalBloques =(numElementos + hilosPorBloque - 1) / hilosPorBloque;
saxpy<<<totalBloques, hilosPorBloque>>>(d_x, d_y, 5.0f, tamano);
// Traspasamos datos de device a host
hipMemcpy(h_y, d_y, tamano, hipMemcpyDeviceToHost);
// Verificamos resultado
float Error = 0.0f;
int i;
for (i = 0; i < 10; i++) {
Error = Error + abs(h_y[i] - 7.0f);
printf("%2.8f", h_x[i]);
}
printf("Error: %f\n", Error);
// Liberamos memoria device
hipFree(d_x);
hipFree(d_y);
// Liberamos memoria host
free(h_x);
free(h_y);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5saxpyPfS_fi
.globl _Z5saxpyPfS_fi
.p2align 8
.type _Z5saxpyPfS_fi,@function
_Z5saxpyPfS_fi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, s0, v2
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5saxpyPfS_fi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5saxpyPfS_fi, .Lfunc_end0-_Z5saxpyPfS_fi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5saxpyPfS_fi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5saxpyPfS_fi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
// Función kernel que se ejecuta en la GPU
__global__ void saxpy(float *x, float *y, float a, int numElementos)
{
int tid= blockDim.x * blockIdx.x + threadIdx.x;
if (tid < numElementos)
{
y[tid] = a * x[tid] + y[tid];
}
}
int main(void)
{
// Definimos tamaños: 1M de elementos (2^20)
int numElementos = 1<<20; //
size_t tamano = numElementos * sizeof(float);
//Definimos variables
float *h_x, *h_y, *d_x, *d_y;
// Reservamos memoria en el host
h_x = (float *)malloc(tamano);
h_y = (float *)malloc(tamano);
// Asignamos valores en el host
for (int i = 0; i < numElementos; i++)
{
h_x[i] = 1.0f;
h_y[i] = 2.0f;
}
float a = 5.0f;
// Reservamos memoria en el device
hipMalloc(&d_x, tamano);
hipMalloc(&d_y, tamano);
// Traspasamos datos de host a device
hipMemcpy(d_x, h_x, tamano, hipMemcpyHostToDevice);
hipMemcpy(d_y, h_y, tamano, hipMemcpyHostToDevice);
//Lanzamos el kernel CUDA
int hilosPorBloque = 8;
int totalBloques =(numElementos + hilosPorBloque - 1) / hilosPorBloque;
saxpy<<<totalBloques, hilosPorBloque>>>(d_x, d_y, 5.0f, tamano);
// Traspasamos datos de device a host
hipMemcpy(h_y, d_y, tamano, hipMemcpyDeviceToHost);
// Verificamos resultado
float Error = 0.0f;
int i;
for (i = 0; i < 10; i++) {
Error = Error + abs(h_y[i] - 7.0f);
printf("%2.8f", h_x[i]);
}
printf("Error: %f\n", Error);
// Liberamos memoria device
hipFree(d_x);
hipFree(d_y);
// Liberamos memoria host
free(h_x);
free(h_y);
return 0;
} | .text
.file "saxpy.hip"
.globl _Z20__device_stub__saxpyPfS_fi # -- Begin function _Z20__device_stub__saxpyPfS_fi
.p2align 4, 0x90
.type _Z20__device_stub__saxpyPfS_fi,@function
_Z20__device_stub__saxpyPfS_fi: # @_Z20__device_stub__saxpyPfS_fi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5saxpyPfS_fi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__saxpyPfS_fi, .Lfunc_end0-_Z20__device_stub__saxpyPfS_fi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0xc0e00000 # float -7
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
movl $1073741824, (%r14,%rax,4) # imm = 0x40000000
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq %rsp, %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq 8(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967304, %rdx # imm = 0x100000008
leaq 131064(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $1084227584, 28(%rsp) # imm = 0x40A00000
movl $4194304, 24(%rsp) # imm = 0x400000
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5saxpyPfS_fi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorps %xmm1, %xmm1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss .LCPI1_0(%rip), %xmm0
andps .LCPI1_1(%rip), %xmm0
addss %xmm0, %xmm1
movss %xmm1, 20(%rsp) # 4-byte Spill
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movss 20(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
incq %r15
cmpq $10, %r15
jne .LBB1_5
# %bb.6:
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5saxpyPfS_fi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5saxpyPfS_fi,@object # @_Z5saxpyPfS_fi
.section .rodata,"a",@progbits
.globl _Z5saxpyPfS_fi
.p2align 3, 0x0
_Z5saxpyPfS_fi:
.quad _Z20__device_stub__saxpyPfS_fi
.size _Z5saxpyPfS_fi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%2.8f"
.size .L.str, 6
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error: %f\n"
.size .L.str.1, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5saxpyPfS_fi"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__saxpyPfS_fi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5saxpyPfS_fi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5saxpyPfS_fi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x174], PT ; /* 0x00005d0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe400078e0205 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FFMA R7, R2, c[0x0][0x170], R7 ; /* 0x00005c0002077a23 */
/* 0x004fca0000000007 */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5saxpyPfS_fi
.globl _Z5saxpyPfS_fi
.p2align 8
.type _Z5saxpyPfS_fi,@function
_Z5saxpyPfS_fi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, s0, v2
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5saxpyPfS_fi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5saxpyPfS_fi, .Lfunc_end0-_Z5saxpyPfS_fi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5saxpyPfS_fi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5saxpyPfS_fi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018f03b_00000000-6_saxpy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z5saxpyPfS_fiPfS_fi
.type _Z28__device_stub__Z5saxpyPfS_fiPfS_fi, @function
_Z28__device_stub__Z5saxpyPfS_fiPfS_fi:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5saxpyPfS_fi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z28__device_stub__Z5saxpyPfS_fiPfS_fi, .-_Z28__device_stub__Z5saxpyPfS_fiPfS_fi
.globl _Z5saxpyPfS_fi
.type _Z5saxpyPfS_fi, @function
_Z5saxpyPfS_fi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5saxpyPfS_fiPfS_fi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5saxpyPfS_fi, .-_Z5saxpyPfS_fi
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "%2.8f"
.LC7:
.string "Error: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %eax
movss .LC1(%rip), %xmm1
movss .LC2(%rip), %xmm0
.L12:
movss %xmm1, 0(%rbp,%rax)
movss %xmm0, (%rbx,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L12
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $8, 44(%rsp)
movl $1, 48(%rsp)
movl $131072, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $4194304, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0, %r12d
movl $0x00000000, 12(%rsp)
leaq .LC6(%rip), %r13
.L14:
movss (%rbx,%r12), %xmm0
subss .LC4(%rip), %xmm0
andps .LC5(%rip), %xmm0
addss 12(%rsp), %xmm0
movss %xmm0, 12(%rsp)
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%r12), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %r12
cmpq $40, %r12
jne .L14
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $4194304, %edx
movss .LC3(%rip), %xmm0
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z28__device_stub__Z5saxpyPfS_fiPfS_fi
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z5saxpyPfS_fi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z5saxpyPfS_fi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC2:
.long 1073741824
.align 4
.LC3:
.long 1084227584
.align 4
.LC4:
.long 1088421888
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC5:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "saxpy.hip"
.globl _Z20__device_stub__saxpyPfS_fi # -- Begin function _Z20__device_stub__saxpyPfS_fi
.p2align 4, 0x90
.type _Z20__device_stub__saxpyPfS_fi,@function
_Z20__device_stub__saxpyPfS_fi: # @_Z20__device_stub__saxpyPfS_fi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
movl %edx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5saxpyPfS_fi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__saxpyPfS_fi, .Lfunc_end0-_Z20__device_stub__saxpyPfS_fi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0xc0e00000 # float -7
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
movl $1073741824, (%r14,%rax,4) # imm = 0x40000000
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq %rsp, %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq 8(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967304, %rdx # imm = 0x100000008
leaq 131064(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $1084227584, 28(%rsp) # imm = 0x40A00000
movl $4194304, 24(%rsp) # imm = 0x400000
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5saxpyPfS_fi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
xorps %xmm1, %xmm1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss .LCPI1_0(%rip), %xmm0
andps .LCPI1_1(%rip), %xmm0
addss %xmm0, %xmm1
movss %xmm1, 20(%rsp) # 4-byte Spill
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movss 20(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
incq %r15
cmpq $10, %r15
jne .LBB1_5
# %bb.6:
xorps %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5saxpyPfS_fi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5saxpyPfS_fi,@object # @_Z5saxpyPfS_fi
.section .rodata,"a",@progbits
.globl _Z5saxpyPfS_fi
.p2align 3, 0x0
_Z5saxpyPfS_fi:
.quad _Z20__device_stub__saxpyPfS_fi
.size _Z5saxpyPfS_fi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%2.8f"
.size .L.str, 6
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error: %f\n"
.size .L.str.1, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5saxpyPfS_fi"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__saxpyPfS_fi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5saxpyPfS_fi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "Dummy.cuh"
#include <cmath>
__host__ __device__ Dummy::Dummy() : counter(0) { ; }
__device__ void Dummy::incrementCounterDevice()
{
++counter;
magicNumber = counter * 5 * pow((double)3, __double2int_rd(magicNumber) % 100) + counter * magicNumber + counter * 2 * pow((double)2, __double2int_rd(magicNumber) % 50) + counter * magicNumber;
}
__host__ void Dummy::incrementCounterHostHost()
{
++counter;
magicNumber = counter * 5 * pow(3, ((int)magicNumber % 100)) + counter * magicNumber + counter * 2 * pow(2, ((int)magicNumber % 50)) + counter * magicNumber;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "Dummy.cuh"
#include <cmath>
__host__ __device__ Dummy::Dummy() : counter(0) { ; }
__device__ void Dummy::incrementCounterDevice()
{
++counter;
magicNumber = counter * 5 * pow((double)3, __double2int_rd(magicNumber) % 100) + counter * magicNumber + counter * 2 * pow((double)2, __double2int_rd(magicNumber) % 50) + counter * magicNumber;
}
__host__ void Dummy::incrementCounterHostHost()
{
++counter;
magicNumber = counter * 5 * pow(3, ((int)magicNumber % 100)) + counter * magicNumber + counter * 2 * pow(2, ((int)magicNumber % 50)) + counter * magicNumber;
} | .file "tmpxft_0002cbea_00000000-6_Dummy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2038:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2038:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.align 2
.globl _ZN5DummyC2Ev
.type _ZN5DummyC2Ev, @function
_ZN5DummyC2Ev:
.LFB2032:
.cfi_startproc
endbr64
movl $0, (%rdi)
ret
.cfi_endproc
.LFE2032:
.size _ZN5DummyC2Ev, .-_ZN5DummyC2Ev
.globl _ZN5DummyC1Ev
.set _ZN5DummyC1Ev,_ZN5DummyC2Ev
.align 2
.globl _ZN5Dummy22incrementCounterDeviceEv
.type _ZN5Dummy22incrementCounterDeviceEv, @function
_ZN5Dummy22incrementCounterDeviceEv:
.LFB2034:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2034:
.size _ZN5Dummy22incrementCounterDeviceEv, .-_ZN5Dummy22incrementCounterDeviceEv
.align 2
.globl _ZN5Dummy24incrementCounterHostHostEv
.type _ZN5Dummy24incrementCounterHostHostEv, @function
_ZN5Dummy24incrementCounterHostHostEv:
.LFB2035:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $16, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r12
movl (%rdi), %eax
leal 1(%rax), %ebx
movl %ebx, (%rdi)
movsd 8(%rdi), %xmm4
movsd %xmm4, (%rsp)
cvttsd2sil %xmm4, %r13d
movslq %r13d, %rax
imulq $1374389535, %rax, %rax
movq %rax, %rbp
shrq $32, %rbp
sarq $37, %rax
movl %r13d, %r14d
sarl $31, %r14d
subl %r14d, %eax
imull $100, %eax, %eax
movl %r13d, %edx
subl %eax, %edx
pxor %xmm1, %xmm1
cvtsi2sdl %edx, %xmm1
movsd .LC0(%rip), %xmm0
call pow@PLT
movsd %xmm0, 8(%rsp)
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
movapd %xmm0, %xmm3
mulsd (%rsp), %xmm3
movsd %xmm3, (%rsp)
sarl $4, %ebp
subl %r14d, %ebp
imull $50, %ebp, %ebp
subl %ebp, %r13d
pxor %xmm1, %xmm1
cvtsi2sdl %r13d, %xmm1
movsd .LC1(%rip), %xmm0
call pow@PLT
movapd %xmm0, %xmm2
leal (%rbx,%rbx,4), %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd 8(%rsp), %xmm0
movsd (%rsp), %xmm3
addsd %xmm3, %xmm0
addl %ebx, %ebx
pxor %xmm1, %xmm1
cvtsi2sdl %ebx, %xmm1
mulsd %xmm2, %xmm1
addsd %xmm1, %xmm0
addsd %xmm3, %xmm0
movsd %xmm0, 8(%r12)
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2035:
.size _ZN5Dummy24incrementCounterHostHostEv, .-_ZN5Dummy24incrementCounterHostHostEv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1074266112
.align 8
.LC1:
.long 0
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "Dummy.cuh"
#include <cmath>
__host__ __device__ Dummy::Dummy() : counter(0) { ; }
__device__ void Dummy::incrementCounterDevice()
{
++counter;
magicNumber = counter * 5 * pow((double)3, __double2int_rd(magicNumber) % 100) + counter * magicNumber + counter * 2 * pow((double)2, __double2int_rd(magicNumber) % 50) + counter * magicNumber;
}
__host__ void Dummy::incrementCounterHostHost()
{
++counter;
magicNumber = counter * 5 * pow(3, ((int)magicNumber % 100)) + counter * magicNumber + counter * 2 * pow(2, ((int)magicNumber % 50)) + counter * magicNumber;
} | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
class Managed {
public:
void *operator new(size_t len) {
void *ptr;
hipMallocManaged(&ptr, len);
hipDeviceSynchronize();
return ptr;
}
void *operator new[](size_t len) {
void *ptr;
hipMallocManaged(&ptr, len);
hipDeviceSynchronize();
return ptr;
}
void operator delete(void *ptr) {
hipDeviceSynchronize();
hipFree(ptr);
}
void operator delete[](void *ptr) {
hipDeviceSynchronize();
hipFree(ptr);
}
};
class Dummy : public Managed
{
public:
int counter;
double magicNumber;
__host__ __device__ Dummy();
__device__ void incrementCounterDevice();
__host__ void incrementCounterHostHost();
}; |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
class Managed {
public:
void *operator new(size_t len) {
void *ptr;
hipMallocManaged(&ptr, len);
hipDeviceSynchronize();
return ptr;
}
void *operator new[](size_t len) {
void *ptr;
hipMallocManaged(&ptr, len);
hipDeviceSynchronize();
return ptr;
}
void operator delete(void *ptr) {
hipDeviceSynchronize();
hipFree(ptr);
}
void operator delete[](void *ptr) {
hipDeviceSynchronize();
hipFree(ptr);
}
};
class Dummy : public Managed
{
public:
int counter;
double magicNumber;
__host__ __device__ Dummy();
__device__ void incrementCounterDevice();
__host__ void incrementCounterHostHost();
}; | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
class Managed {
public:
void *operator new(size_t len) {
void *ptr;
hipMallocManaged(&ptr, len);
hipDeviceSynchronize();
return ptr;
}
void *operator new[](size_t len) {
void *ptr;
hipMallocManaged(&ptr, len);
hipDeviceSynchronize();
return ptr;
}
void operator delete(void *ptr) {
hipDeviceSynchronize();
hipFree(ptr);
}
void operator delete[](void *ptr) {
hipDeviceSynchronize();
hipFree(ptr);
}
};
class Dummy : public Managed
{
public:
int counter;
double magicNumber;
__host__ __device__ Dummy();
__device__ void incrementCounterDevice();
__host__ void incrementCounterHostHost();
}; | .text
.file "Dummy.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002cbea_00000000-6_Dummy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2038:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2038:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.align 2
.globl _ZN5DummyC2Ev
.type _ZN5DummyC2Ev, @function
_ZN5DummyC2Ev:
.LFB2032:
.cfi_startproc
endbr64
movl $0, (%rdi)
ret
.cfi_endproc
.LFE2032:
.size _ZN5DummyC2Ev, .-_ZN5DummyC2Ev
.globl _ZN5DummyC1Ev
.set _ZN5DummyC1Ev,_ZN5DummyC2Ev
.align 2
.globl _ZN5Dummy22incrementCounterDeviceEv
.type _ZN5Dummy22incrementCounterDeviceEv, @function
_ZN5Dummy22incrementCounterDeviceEv:
.LFB2034:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2034:
.size _ZN5Dummy22incrementCounterDeviceEv, .-_ZN5Dummy22incrementCounterDeviceEv
.align 2
.globl _ZN5Dummy24incrementCounterHostHostEv
.type _ZN5Dummy24incrementCounterHostHostEv, @function
_ZN5Dummy24incrementCounterHostHostEv:
.LFB2035:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $16, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r12
movl (%rdi), %eax
leal 1(%rax), %ebx
movl %ebx, (%rdi)
movsd 8(%rdi), %xmm4
movsd %xmm4, (%rsp)
cvttsd2sil %xmm4, %r13d
movslq %r13d, %rax
imulq $1374389535, %rax, %rax
movq %rax, %rbp
shrq $32, %rbp
sarq $37, %rax
movl %r13d, %r14d
sarl $31, %r14d
subl %r14d, %eax
imull $100, %eax, %eax
movl %r13d, %edx
subl %eax, %edx
pxor %xmm1, %xmm1
cvtsi2sdl %edx, %xmm1
movsd .LC0(%rip), %xmm0
call pow@PLT
movsd %xmm0, 8(%rsp)
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
movapd %xmm0, %xmm3
mulsd (%rsp), %xmm3
movsd %xmm3, (%rsp)
sarl $4, %ebp
subl %r14d, %ebp
imull $50, %ebp, %ebp
subl %ebp, %r13d
pxor %xmm1, %xmm1
cvtsi2sdl %r13d, %xmm1
movsd .LC1(%rip), %xmm0
call pow@PLT
movapd %xmm0, %xmm2
leal (%rbx,%rbx,4), %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd 8(%rsp), %xmm0
movsd (%rsp), %xmm3
addsd %xmm3, %xmm0
addl %ebx, %ebx
pxor %xmm1, %xmm1
cvtsi2sdl %ebx, %xmm1
mulsd %xmm2, %xmm1
addsd %xmm1, %xmm0
addsd %xmm3, %xmm0
movsd %xmm0, 8(%r12)
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2035:
.size _ZN5Dummy24incrementCounterHostHostEv, .-_ZN5Dummy24incrementCounterHostHostEv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1074266112
.align 8
.LC1:
.long 0
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Dummy.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
Implement your CUDA kernel in this file
*/
/*
* Solves the Panfilov model using an explicit numerical scheme.
* Based on code orginally provided by Xing Cai, Simula Research Laboratory
* and reimplementation by Scott B. Baden, UCSD
*
* Modified and restructured by Didem Unat, Koc University
*
* Refer to "Detailed Numerical Analyses of the Aliev-Panfilov Model on GPGPU"
* https://www.simula.no/publications/detailed-numerical-analyses-aliev-panfilov-model-gpgpu
* by Xing Cai, Didem Unat and Scott Baden
*
*/
#include <stdio.h>
#include <assert.h>
#include <stdlib.h>
#include <iostream>
#include <iomanip>
#include <string.h>
#include <math.h>
#include <sys/time.h>
#include <getopt.h>
using namespace std;
#define TILE_DIM 16
// External functions
//extern "C" void splot(double **E, double T, int niter, int m, int n);
void cmdLine(int argc, char *argv[], double &T, int &n, int &px, int &py, int &plot_freq, int &no_comm, int &num_threads){
/// Command line arguments
// Default value of the domain sizes
static struct option long_options[] = {
{"n", required_argument, 0, 'n'},
{"px", required_argument, 0, 'x'},
{"py", required_argument, 0, 'y'},
{"tfinal", required_argument, 0, 't'},
{"plot", required_argument, 0, 'p'},
{"nocomm", no_argument, 0, 'k'},
{"numthreads", required_argument, 0, 'o'},
};
// Process command line arguments
int ac;
for (ac = 1; ac < argc; ac++)
{
int c;
while ((c = getopt_long(argc, argv, "n:x:y:t:kp:o:", long_options, NULL)) != -1)
{
switch (c)
{
// Size of the computational box
case 'n':
n = atoi(optarg);
break;
// X processor geometry
case 'x':
px = atoi(optarg);
// Y processor geometry
case 'y':
py = atoi(optarg);
// Length of simulation, in simulated time units
case 't':
T = atof(optarg);
break;
// Turn off communication
case 'k':
no_comm = 1;
break;
// Plot the excitation variable
case 'p':
plot_freq = atoi(optarg);
break;
// Plot the excitation variable
case 'o':
num_threads = atoi(optarg);
break;
// Error
default:
printf("Usage: a.out [-n <domain size>] [-t <final time >]\n\t [-p <plot frequency>]\n\t[-px <x processor geometry> [-py <y proc. geometry] [-k turn off communication] [-o <Number of OpenMP threads>]\n");
exit(-1);
}
}
}
}
// Utilities
//
// Timer
// Make successive calls and take a difference to get the elapsed time.
static const double kMicro = 1.0e-6;
double getTime(){
struct timeval TV;
struct timezone TZ;
const int RC = gettimeofday(&TV, &TZ);
if (RC == -1)
{
cerr << "ERROR: Bad call to gettimeofday" << endl;
return (-1);
}
return (((double)TV.tv_sec) + kMicro * ((double)TV.tv_usec));
}
// end getTime()
// Allocate a 2D array
double **alloc2D(int m, int n){
double **E;
int nx = n, ny = m;
E = (double **)malloc(sizeof(double *) * ny + sizeof(double) * nx * ny);
assert(E);
int row;
for (row = 0; row < ny; row++)
E[row] = (double *)(E + ny) + row * nx;
return (E);
}
// Reports statistics about the computation
// These values should not vary (except to within roundoff)
// when we use different numbers of processes to solve the problem
double stats(double **E, int m, int n, double *_mx){
double mx = -1;
double l2norm = 0;
int col, row;
for (row = 1; row <= m; row++)
for (col = 1; col <= n; col++)
{
l2norm += E[row][col] * E[row][col];
if (E[row][col] > mx)
mx = E[row][col];
}
*_mx = mx;
l2norm /= (double)((m) * (n));
l2norm = sqrt(l2norm);
return l2norm;
}
double stats1D(double *E, int m, int n, double *_mx, int WIDTH){
double mx = -1;
double l2norm = 0;
int col, row;
int index = -1;
for (row = 1; row <= m; row++) {
for (col = 1; col <= n; col++){
index = row * WIDTH + col;
l2norm += E[index] * E[index];
if (E[index] > mx) {
mx = E[index];
}
}
}
*_mx = mx;
l2norm /= (double)((m) * (n));
l2norm = sqrt(l2norm);
return l2norm;
}
__global__ void simulate_version1(const double alpha, const int n, const int m, const double kk, const double dt, const double a, const double epsilon, const double M1, const double M2, const double b, double* E_1D, double* E_prev_1D, double* R_1D, int WIDTH){
int RADIUS = 1;
int row = blockIdx.y * blockDim.y + threadIdx.y + RADIUS;
int col = blockIdx.x * blockDim.x + threadIdx.x + RADIUS;
if (row < (WIDTH -1) && col < (WIDTH -1)) {
E_1D[row*WIDTH+col] = E_prev_1D[row*WIDTH+col] + alpha * (E_prev_1D[row*WIDTH+(col+1)] + E_prev_1D[row*WIDTH + (col-1)] - 4 * E_prev_1D[row*WIDTH+ col] + E_prev_1D[(row + 1)*WIDTH + col] + E_prev_1D[(row - 1) * WIDTH + col]);
}
}
void simulate(double **E, double **E_prev, double **R, const double alpha, const int n, const int m, const double kk, const double dt, const double a, const double epsilon, const double M1, const double M2, const double b, double* E_1D, double* E_prev_1D, double* R_1D, int WIDTH){
int col, row;
/*
* Copy data from boundary of the computational box
* to the padding region, set up for differencing
* on the boundary of the computational box
* Using mirror boundaries
*/
for (row = 1; row <= m; row++) {
E_prev[row][0] = E_prev[row][2];
E_prev_1D[row* WIDTH + 0] = E_prev_1D[row*WIDTH + 2];
}
for (row = 1; row <= m; row++) {
E_prev[row][n + 1] = E_prev[row][n - 1];
E_prev_1D[row*WIDTH+ (n+1)] = E_prev_1D[row*WIDTH + (n-1)];
}
for (col = 1; col <= n; col++) {
E_prev[0][col] = E_prev[2][col];
E_prev_1D[0*WIDTH+col] = E_prev_1D[2*WIDTH+ col];
}
for (col = 1; col <= n; col++) {
E_prev[m + 1][col] = E_prev[m - 1][col];
E_prev_1D[(m+1)*WIDTH+ col] = E_prev_1D[(m-1)*WIDTH+ col];
}
// ================ Kernel Setup ==============
// double *d_E_1D, *d_E_prev_1D, *d_R_1D;
// const dim3 block_size(TILE_DIM, TILE_DIM);
// const dim3 num_blocks(WIDTH / block_size.x, WIDTH / block_size.y);
// int Total_Bytes = WIDTH * WIDTH * sizeof(double);
// // Allocate space on the device
// cudaMalloc( &d_E_1D, Total_Bytes) ;
// cudaMalloc( &d_E_prev_1D,Total_Bytes) ;
// cudaMalloc(&d_R_1D, Total_Bytes);
// // Copy input data to device
// cudaMemcpy(d_E_1D, E_1D, Total_Bytes, cudaMemcpyHostToDevice) ;
// cudaMemcpy(d_E_prev_1D, E_prev_1D, Total_Bytes, cudaMemcpyHostToDevice) ;
// cudaMemcpy(d_R_1D, R_1D, Total_Bytes, cudaMemcpyHostToDevice) ;
// // simulate_version1<<<num_blocks, block_size>>>(alpha, n, m, kk, dt, a, epsilon, M1, M2, b, d_E_1D, d_E_prev_1D, d_R_1D, WIDTH);
// cudaMemcpy(E_1D ,d_E_1D, Total_Bytes, cudaMemcpyDeviceToHost);
// cudaFree(d_E_1D);
// cudaFree(d_E_prev_1D);
// cudaFree(d_R_1D);
// =================================================
// Solve for the excitation, the PDE
for (row = 1; row <= m; row++){
for (col = 1; col <= n; col++){
E[row][col] = E_prev[row][col] + alpha * (E_prev[row][col + 1] + E_prev[row][col - 1] - 4 * E_prev[row][col] + E_prev[row + 1][col] + E_prev[row - 1][col]);
E_1D[row*WIDTH+col] = E_prev_1D[row*WIDTH+col] + alpha * (E_prev_1D[row*WIDTH+(col+1)] + E_prev_1D[row*WIDTH + (col-1)] - 4 * E_prev_1D[row*WIDTH+ col] + E_prev_1D[(row + 1)*WIDTH + col] + E_prev_1D[(row - 1) * WIDTH + col]);
}
}
/*
* Solve the ODE, advancing excitation and recovery to the
* next timtestep
*/
int index = -1;
for (row = 1; row <= m; row++){
for (col = 1; col <= n; col++) {
E[row][col] = E[row][col] - dt * (kk * E[row][col] * (E[row][col] - a) * (E[row][col] - 1) + E[row][col] * R[row][col]);
index = row * WIDTH + col;
E_1D[index] = E_1D[index] - dt * (kk * E_1D[index] * (E_1D[index] - a) * (E_1D[index] - 1) + E_1D[index] * R_1D[index]);
}
}
for (row = 1; row <= m; row++){
for (col = 1; col <= n; col++) {
R[row][col] = R[row][col] + dt * (epsilon + M1 * R[row][col] / (E[row][col] + M2)) * (-R[row][col] - kk * E[row][col] * (E[row][col] - b - 1));
index = row * WIDTH + col;
R_1D[index] = R_1D[index] + dt * (epsilon + M1 * R_1D[index] / (E_1D[index] + M2)) * (-R_1D[index] - kk * E_1D[index] * (E_1D[index] - b - 1));
}
}
}
// Main program
int main(int argc, char **argv){
/*
* Solution arrays
* E is the "Excitation" variable, a voltage
* R is the "Recovery" variable
* E_prev is the Excitation variable for the previous timestep,
* and is used in time integration
*/
cout<< "\n Hello I am waris"<<endl;
double **E, **R, **E_prev;
double * E_1D, *R_1D, *E_prev_1D;
// Various constants - these definitions shouldn't change
const double a = 0.1, b = 0.1, kk = 8.0, M1 = 0.07, M2 = 0.3, epsilon = 0.01, d = 5e-5;
double T = 1000.0;
int m = 200, n = 200;
int plot_freq = 0;
int px = 1, py = 1;
int no_comm = 0;
int num_threads = 1;
int WIDTH;
//int size;
cmdLine(argc, argv, T, n, px, py, plot_freq, no_comm, num_threads);
m = n;
// Allocate contiguous memory for solution arrays
// The computational box is defined on [1:m+1,1:n+1]
// We pad the arrays in order to facilitate differencing on the
// boundaries of the computation box
int Total_Bytes = (m+2) * (n+2) *sizeof(double);
WIDTH = m+2;
E = alloc2D(m + 2, n + 2);
E_prev = alloc2D(m + 2, n + 2);
R = alloc2D(m + 2, n + 2);
E_1D = (double *) malloc (Total_Bytes);
E_prev_1D = (double *) malloc (Total_Bytes);
R_1D = (double *) malloc (Total_Bytes);
int col, row;
// Initialization
for (row = 1; row <= m; row++) {
for (col = 1; col <= n; col++) {
E_prev[row][col] = 0;
R[row][col] = 0;
E_prev_1D[row*WIDTH + col] = 0;
R_1D[row*WIDTH + col] = 0;
}
}
for (row = 1; row <= m; row++) {
for (col = n / 2 + 1; col <= n; col++) {
E_prev[row][col] = 1.0;
E_prev_1D[row*WIDTH + col] = 1.0;
}
}
for (row = m / 2 + 1; row <= m; row++) {
for (col = 1; col <= n; col++) {
R[row][col] = 1.0;
R_1D[row*WIDTH + col] = 1.0;
}
}
//cout<< "check 1"<<endl;
double dx = 1.0 / n;
// For time integration, these values shouldn't change
double rp = kk * (b + 1) * (b + 1) / 4;
double dte = (dx * dx) / (d * 4 + ((dx * dx)) * (rp + kk));
double dtr = 1 / (epsilon + ((M1 / M2) * rp));
double dt = (dte < dtr) ? 0.95 * dte : 0.95 * dtr;
double alpha = d * dt / (dx * dx);
cout << "Grid Size : " << n << endl;
cout << "Duration of Sim : " << T << endl;
cout << "Time step dt : " << dt << endl;
cout << "Process geometry: " << px << " x " << py << endl;
if (no_comm) {
cout << "Communication : DISABLED" << endl;
}
cout << endl;
// Start the timer
double t0 = getTime();
// Simulated time is different from the integer timestep number
// Simulated time
double t = 0.0;
// Integer timestep number
int niter = 0;
while (t < T){
t += dt;
niter++;
simulate(E, E_prev, R, alpha, n, m, kk, dt, a, epsilon, M1, M2, b, E_1D, E_prev_1D, R_1D, WIDTH);
//swap current E with previous E
double **tmp = E;
E = E_prev;
E_prev = tmp;
double *tmp2 = E_1D;
E_1D = E_prev_1D;
E_prev_1D = tmp2;
// if (plot_freq){
// int k = (int)(t / plot_freq);
// if ((t - k * plot_freq) < dt){
// splot(E, t, niter, m + 2, n + 2);
// }
// }
} //end of while loop
double time_elapsed = getTime() - t0;
double Gflops = (double)(niter * (1E-9 * n * n) * 28.0) / time_elapsed;
double BW = (double)(niter * 1E-9 * (n * n * sizeof(double) * 4.0)) / time_elapsed;
cout << "Number of Iterations : " << niter << endl;
cout << "Elapsed Time (sec) : " << time_elapsed << endl;
cout << "Sustained Gflops Rate : " << Gflops << endl;
cout << "Sustained Bandwidth (GB/sec): " << BW << endl << endl;
double mx;
double l2norm = stats(E_prev, m, n, &mx);
cout << "Max: " << mx << " L2norm: " << l2norm << endl;
l2norm = stats1D(E_prev_1D, m, n, &mx, WIDTH);
cout << "1D Max : " << mx << " 1D L2norm: " << l2norm << endl;
// if (plot_freq){
// cout << "\n\nEnter any input to close the program and the plot..." << endl;
// getchar();
// }
free(E);
free(E_prev);
free(R);
free(E_1D);
free(E_prev_1D);
free(R_1D);
return 0;
}
/* **********************************************************
* Author : Urvashi R.V. [04/06/2004]
* Modified by Didem Unat [03/23/18]
*************************************************************/
//#include <stdio.h>
/* Function to plot the 2D array
* 'gnuplot' is instantiated via a pipe and
* the values to be plotted are passed through, along
* with gnuplot commands */
// FILE *gnu = NULL;
// void splot(double **U, double T, int niter, int m, int n){
// int col, row;
// if (gnu == NULL)
// gnu = popen("gnuplot", "w");
// double mx = -1, mn = 32768;
// for (row = 0; row < m; row++)
// for (col = 0; col < n; col++)
// {
// if (U[row][col] > mx)
// mx = U[row][col];
// if (U[row][col] < mn)
// mn = U[row][col];
// }
// fprintf(gnu, "set title \"T = %f [niter = %d]\"\n", T, niter);
// fprintf(gnu, "set size square\n");
// fprintf(gnu, "set key off\n");
// fprintf(gnu, "set pm3d map\n");
// // Various color schemes
// fprintf(gnu, "set palette defined (-3 \"blue\", 0 \"white\", 1 \"red\")\n");
// // fprintf(gnu,"set palette rgbformulae 22, 13, 31\n");
// // fprintf(gnu,"set palette rgbformulae 30, 31, 32\n");
// fprintf(gnu, "splot [0:%d] [0:%d][%f:%f] \"-\"\n", m - 1, n - 1, mn, mx);
// for (row = 0; row < m; row++)
// {
// for (col = 0; col < n; col++)
// {
// fprintf(gnu, "%d %d %f\n", col, row, U[col][row]);
// }
// fprintf(gnu, "\n");
// }
// fprintf(gnu, "e\n");
// fflush(gnu);
// return;
// } | code for sm_80
Function : _Z17simulate_version1diidddddddPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R14, SR_CTAID.X ; /* 0x00000000000e7919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x1c0] ; /* 0x0000700000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0050*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0060*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0070*/ IMAD R14, R14, c[0x0][0x0], R5 ; /* 0x000000000e0e7a24 */
/* 0x001fca00078e0205 */
/*0080*/ IADD3 R0, R14, 0x1, RZ ; /* 0x000000010e007810 */
/* 0x000fe20007ffe0ff */
/*0090*/ IMAD R2, R2, c[0x0][0x4], R3 ; /* 0x0000010002027a24 */
/* 0x002fc600078e0203 */
/*00a0*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fe4000bf06270 */
/*00b0*/ IADD3 R3, R2, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x000fc80007ffe0ff */
/*00c0*/ ISETP.GE.OR P0, PT, R3, UR4, P0 ; /* 0x0000000403007c0c */
/* 0x000fda0008706670 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ HFMA2.MMA R0, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff007435 */
/* 0x000fe200000001ff */
/*00f0*/ IMAD R3, R3, c[0x0][0x1c0], R14 ; /* 0x0000700003037a24 */
/* 0x000fe200078e020e */
/*0100*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0110*/ IMAD.WIDE R6, R3.reuse, R0, c[0x0][0x1b0] ; /* 0x00006c0003067625 */
/* 0x040fe200078e0200 */
/*0120*/ IADD3 R13, R3, c[0x0][0x1c0], RZ ; /* 0x00007000030d7a10 */
/* 0x000fc80007ffe0ff */
/*0130*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ea8000c1e1b00 */
/*0140*/ LDG.E.64 R10, [R6.64+0x10] ; /* 0x00001004060a7981 */
/* 0x000ea2000c1e1b00 */
/*0150*/ IMAD.WIDE R12, R13, R0, c[0x0][0x1b0] ; /* 0x00006c000d0c7625 */
/* 0x000fc600078e0200 */
/*0160*/ LDG.E.64 R4, [R6.64+0x8] ; /* 0x0000080406047981 */
/* 0x000ee2000c1e1b00 */
/*0170*/ IMAD R15, R2, c[0x0][0x1c0], R14 ; /* 0x00007000020f7a24 */
/* 0x000fc600078e020e */
/*0180*/ LDG.E.64 R12, [R12.64+0x8] ; /* 0x000008040c0c7981 */
/* 0x000f22000c1e1b00 */
/*0190*/ IMAD.WIDE R14, R15, R0, c[0x0][0x1b0] ; /* 0x00006c000f0e7625 */
/* 0x000fcc00078e0200 */
/*01a0*/ LDG.E.64 R14, [R14.64+0x8] ; /* 0x000008040e0e7981 */
/* 0x000f62000c1e1b00 */
/*01b0*/ IMAD.WIDE R2, R3, R0, c[0x0][0x1a8] ; /* 0x00006a0003027625 */
/* 0x000fe200078e0200 */
/*01c0*/ DADD R8, R8, R10 ; /* 0x0000000008087229 */
/* 0x004ecc000000000a */
/*01d0*/ DFMA R8, R4, -4, R8 ; /* 0xc01000000408782b */
/* 0x008f0c0000000008 */
/*01e0*/ DADD R8, R8, R12 ; /* 0x0000000008087229 */
/* 0x010f4c000000000c */
/*01f0*/ DADD R8, R8, R14 ; /* 0x0000000008087229 */
/* 0x020e0c000000000e */
/*0200*/ DFMA R8, R8, c[0x0][0x160], R4 ; /* 0x0000580008087a2b */
/* 0x001e0e0000000004 */
/*0210*/ STG.E.64 [R2.64+0x8], R8 ; /* 0x0000080802007986 */
/* 0x001fe2000c101b04 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
Implement your CUDA kernel in this file
*/
/*
* Solves the Panfilov model using an explicit numerical scheme.
* Based on code orginally provided by Xing Cai, Simula Research Laboratory
* and reimplementation by Scott B. Baden, UCSD
*
* Modified and restructured by Didem Unat, Koc University
*
* Refer to "Detailed Numerical Analyses of the Aliev-Panfilov Model on GPGPU"
* https://www.simula.no/publications/detailed-numerical-analyses-aliev-panfilov-model-gpgpu
* by Xing Cai, Didem Unat and Scott Baden
*
*/
#include <stdio.h>
#include <assert.h>
#include <stdlib.h>
#include <iostream>
#include <iomanip>
#include <string.h>
#include <math.h>
#include <sys/time.h>
#include <getopt.h>
using namespace std;
#define TILE_DIM 16
// External functions
//extern "C" void splot(double **E, double T, int niter, int m, int n);
void cmdLine(int argc, char *argv[], double &T, int &n, int &px, int &py, int &plot_freq, int &no_comm, int &num_threads){
/// Command line arguments
// Default value of the domain sizes
static struct option long_options[] = {
{"n", required_argument, 0, 'n'},
{"px", required_argument, 0, 'x'},
{"py", required_argument, 0, 'y'},
{"tfinal", required_argument, 0, 't'},
{"plot", required_argument, 0, 'p'},
{"nocomm", no_argument, 0, 'k'},
{"numthreads", required_argument, 0, 'o'},
};
// Process command line arguments
int ac;
for (ac = 1; ac < argc; ac++)
{
int c;
while ((c = getopt_long(argc, argv, "n:x:y:t:kp:o:", long_options, NULL)) != -1)
{
switch (c)
{
// Size of the computational box
case 'n':
n = atoi(optarg);
break;
// X processor geometry
case 'x':
px = atoi(optarg);
// Y processor geometry
case 'y':
py = atoi(optarg);
// Length of simulation, in simulated time units
case 't':
T = atof(optarg);
break;
// Turn off communication
case 'k':
no_comm = 1;
break;
// Plot the excitation variable
case 'p':
plot_freq = atoi(optarg);
break;
// Plot the excitation variable
case 'o':
num_threads = atoi(optarg);
break;
// Error
default:
printf("Usage: a.out [-n <domain size>] [-t <final time >]\n\t [-p <plot frequency>]\n\t[-px <x processor geometry> [-py <y proc. geometry] [-k turn off communication] [-o <Number of OpenMP threads>]\n");
exit(-1);
}
}
}
}
// Utilities
//
// Timer
// Make successive calls and take a difference to get the elapsed time.
static const double kMicro = 1.0e-6;
double getTime(){
struct timeval TV;
struct timezone TZ;
const int RC = gettimeofday(&TV, &TZ);
if (RC == -1)
{
cerr << "ERROR: Bad call to gettimeofday" << endl;
return (-1);
}
return (((double)TV.tv_sec) + kMicro * ((double)TV.tv_usec));
}
// end getTime()
// Allocate a 2D array
double **alloc2D(int m, int n){
double **E;
int nx = n, ny = m;
E = (double **)malloc(sizeof(double *) * ny + sizeof(double) * nx * ny);
assert(E);
int row;
for (row = 0; row < ny; row++)
E[row] = (double *)(E + ny) + row * nx;
return (E);
}
// Reports statistics about the computation
// These values should not vary (except to within roundoff)
// when we use different numbers of processes to solve the problem
double stats(double **E, int m, int n, double *_mx){
double mx = -1;
double l2norm = 0;
int col, row;
for (row = 1; row <= m; row++)
for (col = 1; col <= n; col++)
{
l2norm += E[row][col] * E[row][col];
if (E[row][col] > mx)
mx = E[row][col];
}
*_mx = mx;
l2norm /= (double)((m) * (n));
l2norm = sqrt(l2norm);
return l2norm;
}
double stats1D(double *E, int m, int n, double *_mx, int WIDTH){
double mx = -1;
double l2norm = 0;
int col, row;
int index = -1;
for (row = 1; row <= m; row++) {
for (col = 1; col <= n; col++){
index = row * WIDTH + col;
l2norm += E[index] * E[index];
if (E[index] > mx) {
mx = E[index];
}
}
}
*_mx = mx;
l2norm /= (double)((m) * (n));
l2norm = sqrt(l2norm);
return l2norm;
}
__global__ void simulate_version1(const double alpha, const int n, const int m, const double kk, const double dt, const double a, const double epsilon, const double M1, const double M2, const double b, double* E_1D, double* E_prev_1D, double* R_1D, int WIDTH){
int RADIUS = 1;
int row = blockIdx.y * blockDim.y + threadIdx.y + RADIUS;
int col = blockIdx.x * blockDim.x + threadIdx.x + RADIUS;
if (row < (WIDTH -1) && col < (WIDTH -1)) {
E_1D[row*WIDTH+col] = E_prev_1D[row*WIDTH+col] + alpha * (E_prev_1D[row*WIDTH+(col+1)] + E_prev_1D[row*WIDTH + (col-1)] - 4 * E_prev_1D[row*WIDTH+ col] + E_prev_1D[(row + 1)*WIDTH + col] + E_prev_1D[(row - 1) * WIDTH + col]);
}
}
void simulate(double **E, double **E_prev, double **R, const double alpha, const int n, const int m, const double kk, const double dt, const double a, const double epsilon, const double M1, const double M2, const double b, double* E_1D, double* E_prev_1D, double* R_1D, int WIDTH){
int col, row;
/*
* Copy data from boundary of the computational box
* to the padding region, set up for differencing
* on the boundary of the computational box
* Using mirror boundaries
*/
for (row = 1; row <= m; row++) {
E_prev[row][0] = E_prev[row][2];
E_prev_1D[row* WIDTH + 0] = E_prev_1D[row*WIDTH + 2];
}
for (row = 1; row <= m; row++) {
E_prev[row][n + 1] = E_prev[row][n - 1];
E_prev_1D[row*WIDTH+ (n+1)] = E_prev_1D[row*WIDTH + (n-1)];
}
for (col = 1; col <= n; col++) {
E_prev[0][col] = E_prev[2][col];
E_prev_1D[0*WIDTH+col] = E_prev_1D[2*WIDTH+ col];
}
for (col = 1; col <= n; col++) {
E_prev[m + 1][col] = E_prev[m - 1][col];
E_prev_1D[(m+1)*WIDTH+ col] = E_prev_1D[(m-1)*WIDTH+ col];
}
// ================ Kernel Setup ==============
// double *d_E_1D, *d_E_prev_1D, *d_R_1D;
// const dim3 block_size(TILE_DIM, TILE_DIM);
// const dim3 num_blocks(WIDTH / block_size.x, WIDTH / block_size.y);
// int Total_Bytes = WIDTH * WIDTH * sizeof(double);
// // Allocate space on the device
// cudaMalloc( &d_E_1D, Total_Bytes) ;
// cudaMalloc( &d_E_prev_1D,Total_Bytes) ;
// cudaMalloc(&d_R_1D, Total_Bytes);
// // Copy input data to device
// cudaMemcpy(d_E_1D, E_1D, Total_Bytes, cudaMemcpyHostToDevice) ;
// cudaMemcpy(d_E_prev_1D, E_prev_1D, Total_Bytes, cudaMemcpyHostToDevice) ;
// cudaMemcpy(d_R_1D, R_1D, Total_Bytes, cudaMemcpyHostToDevice) ;
// // simulate_version1<<<num_blocks, block_size>>>(alpha, n, m, kk, dt, a, epsilon, M1, M2, b, d_E_1D, d_E_prev_1D, d_R_1D, WIDTH);
// cudaMemcpy(E_1D ,d_E_1D, Total_Bytes, cudaMemcpyDeviceToHost);
// cudaFree(d_E_1D);
// cudaFree(d_E_prev_1D);
// cudaFree(d_R_1D);
// =================================================
// Solve for the excitation, the PDE
for (row = 1; row <= m; row++){
for (col = 1; col <= n; col++){
E[row][col] = E_prev[row][col] + alpha * (E_prev[row][col + 1] + E_prev[row][col - 1] - 4 * E_prev[row][col] + E_prev[row + 1][col] + E_prev[row - 1][col]);
E_1D[row*WIDTH+col] = E_prev_1D[row*WIDTH+col] + alpha * (E_prev_1D[row*WIDTH+(col+1)] + E_prev_1D[row*WIDTH + (col-1)] - 4 * E_prev_1D[row*WIDTH+ col] + E_prev_1D[(row + 1)*WIDTH + col] + E_prev_1D[(row - 1) * WIDTH + col]);
}
}
/*
* Solve the ODE, advancing excitation and recovery to the
* next timtestep
*/
int index = -1;
for (row = 1; row <= m; row++){
for (col = 1; col <= n; col++) {
E[row][col] = E[row][col] - dt * (kk * E[row][col] * (E[row][col] - a) * (E[row][col] - 1) + E[row][col] * R[row][col]);
index = row * WIDTH + col;
E_1D[index] = E_1D[index] - dt * (kk * E_1D[index] * (E_1D[index] - a) * (E_1D[index] - 1) + E_1D[index] * R_1D[index]);
}
}
for (row = 1; row <= m; row++){
for (col = 1; col <= n; col++) {
R[row][col] = R[row][col] + dt * (epsilon + M1 * R[row][col] / (E[row][col] + M2)) * (-R[row][col] - kk * E[row][col] * (E[row][col] - b - 1));
index = row * WIDTH + col;
R_1D[index] = R_1D[index] + dt * (epsilon + M1 * R_1D[index] / (E_1D[index] + M2)) * (-R_1D[index] - kk * E_1D[index] * (E_1D[index] - b - 1));
}
}
}
// Main program
int main(int argc, char **argv){
/*
* Solution arrays
* E is the "Excitation" variable, a voltage
* R is the "Recovery" variable
* E_prev is the Excitation variable for the previous timestep,
* and is used in time integration
*/
cout<< "\n Hello I am waris"<<endl;
double **E, **R, **E_prev;
double * E_1D, *R_1D, *E_prev_1D;
// Various constants - these definitions shouldn't change
const double a = 0.1, b = 0.1, kk = 8.0, M1 = 0.07, M2 = 0.3, epsilon = 0.01, d = 5e-5;
double T = 1000.0;
int m = 200, n = 200;
int plot_freq = 0;
int px = 1, py = 1;
int no_comm = 0;
int num_threads = 1;
int WIDTH;
//int size;
cmdLine(argc, argv, T, n, px, py, plot_freq, no_comm, num_threads);
m = n;
// Allocate contiguous memory for solution arrays
// The computational box is defined on [1:m+1,1:n+1]
// We pad the arrays in order to facilitate differencing on the
// boundaries of the computation box
int Total_Bytes = (m+2) * (n+2) *sizeof(double);
WIDTH = m+2;
E = alloc2D(m + 2, n + 2);
E_prev = alloc2D(m + 2, n + 2);
R = alloc2D(m + 2, n + 2);
E_1D = (double *) malloc (Total_Bytes);
E_prev_1D = (double *) malloc (Total_Bytes);
R_1D = (double *) malloc (Total_Bytes);
int col, row;
// Initialization
for (row = 1; row <= m; row++) {
for (col = 1; col <= n; col++) {
E_prev[row][col] = 0;
R[row][col] = 0;
E_prev_1D[row*WIDTH + col] = 0;
R_1D[row*WIDTH + col] = 0;
}
}
for (row = 1; row <= m; row++) {
for (col = n / 2 + 1; col <= n; col++) {
E_prev[row][col] = 1.0;
E_prev_1D[row*WIDTH + col] = 1.0;
}
}
for (row = m / 2 + 1; row <= m; row++) {
for (col = 1; col <= n; col++) {
R[row][col] = 1.0;
R_1D[row*WIDTH + col] = 1.0;
}
}
//cout<< "check 1"<<endl;
double dx = 1.0 / n;
// For time integration, these values shouldn't change
double rp = kk * (b + 1) * (b + 1) / 4;
double dte = (dx * dx) / (d * 4 + ((dx * dx)) * (rp + kk));
double dtr = 1 / (epsilon + ((M1 / M2) * rp));
double dt = (dte < dtr) ? 0.95 * dte : 0.95 * dtr;
double alpha = d * dt / (dx * dx);
cout << "Grid Size : " << n << endl;
cout << "Duration of Sim : " << T << endl;
cout << "Time step dt : " << dt << endl;
cout << "Process geometry: " << px << " x " << py << endl;
if (no_comm) {
cout << "Communication : DISABLED" << endl;
}
cout << endl;
// Start the timer
double t0 = getTime();
// Simulated time is different from the integer timestep number
// Simulated time
double t = 0.0;
// Integer timestep number
int niter = 0;
while (t < T){
t += dt;
niter++;
simulate(E, E_prev, R, alpha, n, m, kk, dt, a, epsilon, M1, M2, b, E_1D, E_prev_1D, R_1D, WIDTH);
//swap current E with previous E
double **tmp = E;
E = E_prev;
E_prev = tmp;
double *tmp2 = E_1D;
E_1D = E_prev_1D;
E_prev_1D = tmp2;
// if (plot_freq){
// int k = (int)(t / plot_freq);
// if ((t - k * plot_freq) < dt){
// splot(E, t, niter, m + 2, n + 2);
// }
// }
} //end of while loop
double time_elapsed = getTime() - t0;
double Gflops = (double)(niter * (1E-9 * n * n) * 28.0) / time_elapsed;
double BW = (double)(niter * 1E-9 * (n * n * sizeof(double) * 4.0)) / time_elapsed;
cout << "Number of Iterations : " << niter << endl;
cout << "Elapsed Time (sec) : " << time_elapsed << endl;
cout << "Sustained Gflops Rate : " << Gflops << endl;
cout << "Sustained Bandwidth (GB/sec): " << BW << endl << endl;
double mx;
double l2norm = stats(E_prev, m, n, &mx);
cout << "Max: " << mx << " L2norm: " << l2norm << endl;
l2norm = stats1D(E_prev_1D, m, n, &mx, WIDTH);
cout << "1D Max : " << mx << " 1D L2norm: " << l2norm << endl;
// if (plot_freq){
// cout << "\n\nEnter any input to close the program and the plot..." << endl;
// getchar();
// }
free(E);
free(E_prev);
free(R);
free(E_1D);
free(E_prev_1D);
free(R_1D);
return 0;
}
/* **********************************************************
* Author : Urvashi R.V. [04/06/2004]
* Modified by Didem Unat [03/23/18]
*************************************************************/
//#include <stdio.h>
/* Function to plot the 2D array
* 'gnuplot' is instantiated via a pipe and
* the values to be plotted are passed through, along
* with gnuplot commands */
// FILE *gnu = NULL;
// void splot(double **U, double T, int niter, int m, int n){
// int col, row;
// if (gnu == NULL)
// gnu = popen("gnuplot", "w");
// double mx = -1, mn = 32768;
// for (row = 0; row < m; row++)
// for (col = 0; col < n; col++)
// {
// if (U[row][col] > mx)
// mx = U[row][col];
// if (U[row][col] < mn)
// mn = U[row][col];
// }
// fprintf(gnu, "set title \"T = %f [niter = %d]\"\n", T, niter);
// fprintf(gnu, "set size square\n");
// fprintf(gnu, "set key off\n");
// fprintf(gnu, "set pm3d map\n");
// // Various color schemes
// fprintf(gnu, "set palette defined (-3 \"blue\", 0 \"white\", 1 \"red\")\n");
// // fprintf(gnu,"set palette rgbformulae 22, 13, 31\n");
// // fprintf(gnu,"set palette rgbformulae 30, 31, 32\n");
// fprintf(gnu, "splot [0:%d] [0:%d][%f:%f] \"-\"\n", m - 1, n - 1, mn, mx);
// for (row = 0; row < m; row++)
// {
// for (col = 0; col < n; col++)
// {
// fprintf(gnu, "%d %d %f\n", col, row, U[col][row]);
// }
// fprintf(gnu, "\n");
// }
// fprintf(gnu, "e\n");
// fflush(gnu);
// return;
// } | .file "tmpxft_00064aba_00000000-6_vecAdd_UVM.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3958:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3958:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Usage: a.out [-n <domain size>] [-t <final time >]\n\t [-p <plot frequency>]\n\t[-px <x processor geometry> [-py <y proc. geometry] [-k turn off communication] [-o <Number of OpenMP threads>]\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "n:x:y:t:kp:o:"
.text
.globl _Z7cmdLineiPPcRdRiS2_S2_S2_S2_S2_
.type _Z7cmdLineiPPcRdRiS2_S2_S2_S2_S2_, @function
_Z7cmdLineiPPcRdRiS2_S2_S2_S2_S2_:
.LFB3949:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebp
movq %rsi, %r12
movq %rdx, %r15
movq %rcx, 16(%rsp)
movq %r8, 24(%rsp)
movq %r9, (%rsp)
movl $1, 12(%rsp)
leaq _ZZ7cmdLineiPPcRdRiS2_S2_S2_S2_S2_E12long_options(%rip), %r14
leaq .LC1(%rip), %r13
leaq .L8(%rip), %rbx
cmpl $1, %edi
jg .L17
jmp .L3
.L13:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movq 16(%rsp), %rcx
movl %eax, (%rcx)
jmp .L17
.L9:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movq 24(%rsp), %rdx
movl %eax, (%rdx)
.L7:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movq (%rsp), %rcx
movl %eax, (%rcx)
.L10:
movl $0, %esi
movq optarg(%rip), %rdi
call strtod@PLT
movsd %xmm0, (%r15)
.L17:
movl $0, %r8d
movq %r14, %rcx
movq %r13, %rdx
movq %r12, %rsi
movl %ebp, %edi
call getopt_long@PLT
cmpl $-1, %eax
je .L22
subl $107, %eax
cmpl $14, %eax
ja .L6
movl %eax, %eax
movslq (%rbx,%rax,4), %rax
addq %rbx, %rax
notrack jmp *%rax
.section .rodata
.align 4
.align 4
.L8:
.long .L14-.L8
.long .L6-.L8
.long .L6-.L8
.long .L13-.L8
.long .L12-.L8
.long .L11-.L8
.long .L6-.L8
.long .L6-.L8
.long .L6-.L8
.long .L10-.L8
.long .L6-.L8
.long .L6-.L8
.long .L6-.L8
.long .L9-.L8
.long .L7-.L8
.text
.L14:
movq 104(%rsp), %rax
movl $1, (%rax)
jmp .L17
.L11:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movq 96(%rsp), %rcx
movl %eax, (%rcx)
jmp .L17
.L12:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movq 112(%rsp), %rdx
movl %eax, (%rdx)
jmp .L17
.L6:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L22:
addl $1, 12(%rsp)
movl 12(%rsp), %eax
cmpl %eax, %ebp
jne .L17
.L3:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3949:
.size _Z7cmdLineiPPcRdRiS2_S2_S2_S2_S2_, .-_Z7cmdLineiPPcRdRiS2_S2_S2_S2_S2_
.section .rodata.str1.8
.align 8
.LC3:
.string "ERROR: Bad call to gettimeofday"
.text
.globl _Z7getTimev
.type _Z7getTimev, @function
_Z7getTimev:
.LFB3950:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rsi
leaq 16(%rsp), %rdi
call gettimeofday@PLT
cmpl $-1, %eax
je .L32
pxor %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
mulsd .LC4(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm1, %xmm0
.L23:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movl $31, %edx
leaq .LC3(%rip), %rsi
leaq _ZSt4cerr(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L34
cmpb $0, 56(%rbx)
je .L27
movzbl 67(%rbx), %esi
.L28:
movsbl %sil, %esi
leaq _ZSt4cerr(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movsd .LC2(%rip), %xmm0
jmp .L23
.L34:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L35
call _ZSt16__throw_bad_castv@PLT
.L35:
call __stack_chk_fail@PLT
.L27:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L28
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3950:
.size _Z7getTimev, .-_Z7getTimev
.globl _Z7alloc2Dii
.type _Z7alloc2Dii, @function
_Z7alloc2Dii:
.LFB3951:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl %edi, %r12d
movslq %esi, %rbp
movslq %edi, %rcx
leaq 0(,%rcx,8), %rbx
leaq 1(%rbp), %rdi
imulq %rbx, %rdi
call malloc@PLT
testl %r12d, %r12d
jle .L36
leaq 0(,%rbp,8), %rsi
leaq (%rax,%rbx), %rcx
movq %rax, %rdx
movq %rcx, %rdi
.L38:
movq %rcx, (%rdx)
addq %rsi, %rcx
addq $8, %rdx
cmpq %rdi, %rdx
jne .L38
.L36:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3951:
.size _Z7alloc2Dii, .-_Z7alloc2Dii
.globl _Z5statsPPdiiS_
.type _Z5statsPPdiiS_, @function
_Z5statsPPdiiS_:
.LFB3952:
.cfi_startproc
endbr64
movl %esi, %r10d
testl %esi, %esi
jle .L42
leaq 8(%rdi), %r8
leal -1(%rsi), %eax
leaq 16(%rdi,%rax,8), %rdi
leal -1(%rdx), %eax
pxor %xmm0, %xmm0
movsd .LC2(%rip), %xmm2
leaq 16(,%rax,8), %r9
jmp .L43
.L47:
movq (%r8), %rsi
leaq 8(%rsi), %rax
addq %r9, %rsi
.L45:
movsd (%rax), %xmm1
movapd %xmm1, %xmm3
mulsd %xmm1, %xmm3
addsd %xmm3, %xmm0
maxsd %xmm2, %xmm1
movapd %xmm1, %xmm2
addq $8, %rax
cmpq %rsi, %rax
jne .L45
.L48:
addq $8, %r8
cmpq %rdi, %r8
je .L46
.L43:
testl %edx, %edx
jg .L47
jmp .L48
.L46:
movsd %xmm2, (%rcx)
imull %r10d, %edx
pxor %xmm1, %xmm1
cvtsi2sdl %edx, %xmm1
divsd %xmm1, %xmm0
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
ja .L55
.L52:
sqrtsd %xmm0, %xmm0
ret
.L55:
subq $8, %rsp
.cfi_def_cfa_offset 16
call sqrt@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L42:
movq .LC2(%rip), %rax
movq %rax, (%rcx)
imull %edx, %r10d
pxor %xmm1, %xmm1
cvtsi2sdl %r10d, %xmm1
pxor %xmm0, %xmm0
divsd %xmm1, %xmm0
jmp .L52
.cfi_endproc
.LFE3952:
.size _Z5statsPPdiiS_, .-_Z5statsPPdiiS_
.globl _Z7stats1DPdiiS_i
.type _Z7stats1DPdiiS_i, @function
_Z7stats1DPdiiS_i:
.LFB3953:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r9
movl %esi, %r11d
movl %edx, %edi
movq %rcx, %rbp
testl %esi, %esi
jle .L60
leal 1(%rsi), %r10d
movl %r8d, %esi
movl $1, %ecx
pxor %xmm0, %xmm0
movsd .LC2(%rip), %xmm2
leal -1(%rdx), %r12d
leaq 8(%r9), %rbx
jmp .L61
.L65:
movslq %esi, %rdx
leaq (%r9,%rdx,8), %rax
addq %r12, %rdx
leaq (%rbx,%rdx,8), %rdx
.L63:
movsd 8(%rax), %xmm1
movapd %xmm1, %xmm3
mulsd %xmm1, %xmm3
addsd %xmm3, %xmm0
maxsd %xmm2, %xmm1
movapd %xmm1, %xmm2
addq $8, %rax
cmpq %rdx, %rax
jne .L63
.L66:
addl $1, %ecx
addl %r8d, %esi
cmpl %r10d, %ecx
je .L64
.L61:
testl %edi, %edi
jg .L65
jmp .L66
.L64:
movsd %xmm2, 0(%rbp)
imull %r11d, %edi
pxor %xmm1, %xmm1
cvtsi2sdl %edi, %xmm1
divsd %xmm1, %xmm0
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
ja .L73
.L70:
sqrtsd %xmm0, %xmm0
.L59:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L73:
.cfi_restore_state
call sqrt@PLT
jmp .L59
.L60:
movq .LC2(%rip), %rax
movq %rax, (%rcx)
imull %edx, %r11d
pxor %xmm1, %xmm1
cvtsi2sdl %r11d, %xmm1
pxor %xmm0, %xmm0
divsd %xmm1, %xmm0
jmp .L70
.cfi_endproc
.LFE3953:
.size _Z7stats1DPdiiS_i, .-_Z7stats1DPdiiS_i
.globl _Z8simulatePPdS0_S0_diidddddddS_S_S_i
.type _Z8simulatePPdS0_S0_diidddddddS_S_S_i, @function
_Z8simulatePPdS0_S0_diidddddddS_S_S_i:
.LFB3954:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rdi, %r11
movq %rsi, %r10
movq %rdx, -32(%rsp)
movapd %xmm0, %xmm9
movl %ecx, %ebp
movq %r9, %r14
movq 56(%rsp), %r12
movq 64(%rsp), %r15
movl 72(%rsp), %esi
testl %r8d, %r8d
jle .L76
leaq 8(%r10), %rax
movslq %esi, %rbx
leaq 0(,%rbx,8), %rdi
leaq (%r12,%rdi), %rcx
leal -1(%r8), %edx
leaq 16(%r10,%rdx,8), %r9
movq %rax, %rdx
.L77:
movq (%rdx), %r13
movsd 16(%r13), %xmm0
movsd %xmm0, 0(%r13)
movsd 16(%rcx), %xmm0
movsd %xmm0, (%rcx)
addq $8, %rdx
addq %rdi, %rcx
cmpq %r9, %rdx
jne .L77
movslq %ebp, %rdx
leaq -8(,%rdx,8), %r13
leaq 8(,%rdx,8), %rcx
leaq 1(%rdx,%rbx), %rdx
leaq (%r12,%rdx,8), %rdx
.L78:
movq (%rax), %rbx
movsd (%rbx,%r13), %xmm0
movsd %xmm0, (%rbx,%rcx)
movsd -16(%rdx), %xmm0
movsd %xmm0, (%rdx)
addq $8, %rax
addq %rdi, %rdx
cmpq %r9, %rax
jne .L78
testl %ebp, %ebp
jle .L98
.L97:
leal (%rsi,%rsi), %ecx
leal 1(%rbp), %edx
salq $3, %rdx
movslq %esi, %r9
salq $4, %r9
addq %r12, %r9
movl $8, %eax
.L80:
movq 16(%r10), %rdi
movsd (%rdi,%rax), %xmm0
movq (%r10), %rdi
movsd %xmm0, (%rdi,%rax)
movsd (%r9,%rax), %xmm0
movsd %xmm0, (%r12,%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L80
movslq %r8d, %rax
leaq -8(%r10,%rax,8), %r13
leaq 8(%r10,%rax,8), %rbx
leal -1(%r8), %eax
imull %esi, %eax
movslq %eax, %rdi
leaq (%r12,%rdi,8), %r9
addl %ecx, %eax
cltq
leaq (%r12,%rax,8), %rdi
movl $8, %eax
.L81:
movq 0(%r13), %rcx
movsd (%rcx,%rax), %xmm0
movq (%rbx), %rcx
movsd %xmm0, (%rcx,%rax)
movsd (%r9,%rax), %xmm0
movsd %xmm0, (%rdi,%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L81
testl %r8d, %r8d
jle .L75
.L98:
movq %r10, %rdi
leaq 8(%r11), %rax
leal -1(%r8), %edx
leaq 0(,%rdx,8), %rbx
movq %rbx, -24(%rsp)
leaq 8(%r10,%rbx), %r9
leal -1(%rbp), %edx
leaq 16(,%rdx,8), %r8
movq %rax, %r10
movl $0, %r13d
movsd .LC6(%rip), %xmm10
movq %rax, -16(%rsp)
movq %r11, -8(%rsp)
movq %r15, 64(%rsp)
jmp .L83
.L86:
leal 0(%r13,%rsi), %eax
movslq %eax, %r11
salq $3, %r11
leaq (%r12,%r11), %rcx
addl %esi, %eax
cltq
leaq (%r12,%rax,8), %r15
movslq %r13d, %rax
leaq (%r12,%rax,8), %rbx
addq %r14, %r11
movl $8, %edx
movl %r13d, -40(%rsp)
.L84:
movq 8(%rdi), %r13
movsd 0(%r13,%rdx), %xmm11
movq %rdx, %rax
addq $8, %rdx
movsd -8(%r13,%rax), %xmm8
movapd %xmm8, %xmm0
addsd 0(%r13,%rdx), %xmm0
movapd %xmm11, %xmm8
mulsd %xmm10, %xmm8
subsd %xmm8, %xmm0
movq 16(%rdi), %r13
addsd 0(%r13,%rax), %xmm0
movq (%rdi), %r13
addsd 0(%r13,%rax), %xmm0
mulsd %xmm9, %xmm0
addsd %xmm11, %xmm0
movq (%r10), %r13
movsd %xmm0, 0(%r13,%rax)
movsd 8(%rcx), %xmm11
movsd 16(%rcx), %xmm8
movapd %xmm8, %xmm0
addsd (%rcx), %xmm0
movapd %xmm11, %xmm8
mulsd %xmm10, %xmm8
subsd %xmm8, %xmm0
addsd (%r15,%rax), %xmm0
addsd (%rbx,%rax), %xmm0
mulsd %xmm9, %xmm0
addsd %xmm11, %xmm0
movsd %xmm0, (%r11,%rax)
addq $8, %rcx
cmpq %r8, %rdx
jne .L84
movl -40(%rsp), %r13d
.L87:
addq $8, %rdi
addq $8, %r10
addl %esi, %r13d
cmpq %r9, %rdi
je .L85
.L83:
testl %ebp, %ebp
jg .L86
jmp .L87
.L85:
movq -16(%rsp), %rax
movq -8(%rsp), %r11
movq 64(%rsp), %r15
movq -32(%rsp), %rdi
leaq 8(%rdi), %rcx
movq -24(%rsp), %rdi
leaq 16(%r11,%rdi), %r12
movl %esi, %r9d
movq %rcx, %rbx
movq %rax, %r11
movsd .LC7(%rip), %xmm8
movq %rcx, %r10
jmp .L88
.L91:
movslq %r9d, %r13
salq $3, %r13
leaq (%r14,%r13), %rdi
addq %r15, %r13
movl $8, %edx
movq %rax, -40(%rsp)
.L89:
movq %rdx, %rcx
addq (%r11), %rcx
movsd (%rcx), %xmm9
movapd %xmm9, %xmm0
mulsd %xmm1, %xmm0
movapd %xmm9, %xmm10
subsd %xmm3, %xmm10
mulsd %xmm10, %xmm0
movapd %xmm9, %xmm10
subsd %xmm8, %xmm10
mulsd %xmm10, %xmm0
movq (%rbx), %rax
movapd %xmm9, %xmm10
mulsd (%rax,%rdx), %xmm10
addsd %xmm10, %xmm0
mulsd %xmm2, %xmm0
subsd %xmm0, %xmm9
movsd %xmm9, (%rcx)
movsd (%rdi,%rdx), %xmm9
movapd %xmm9, %xmm0
mulsd %xmm1, %xmm0
movapd %xmm9, %xmm10
subsd %xmm3, %xmm10
mulsd %xmm10, %xmm0
movapd %xmm9, %xmm10
subsd %xmm8, %xmm10
mulsd %xmm10, %xmm0
movapd %xmm9, %xmm10
mulsd 0(%r13,%rdx), %xmm10
addsd %xmm10, %xmm0
mulsd %xmm2, %xmm0
subsd %xmm0, %xmm9
movsd %xmm9, (%rdi,%rdx)
addq $8, %rdx
cmpq %r8, %rdx
jne .L89
movq -40(%rsp), %rax
.L92:
addq $8, %r11
addq $8, %rbx
addl %esi, %r9d
cmpq %r12, %r11
je .L90
.L88:
testl %ebp, %ebp
jg .L91
jmp .L92
.L90:
movq %r10, %rcx
movq -32(%rsp), %rdi
movq -24(%rsp), %rbx
leaq 16(%rdi,%rbx), %r11
movl %esi, %r10d
movq .LC8(%rip), %xmm8
movsd .LC7(%rip), %xmm3
jmp .L93
.L95:
movslq %r10d, %r9
salq $3, %r9
leaq (%r15,%r9), %rdi
addq %r14, %r9
movl $8, %edx
.L94:
movq %rdx, %rbx
addq (%rcx), %rbx
movsd (%rbx), %xmm11
movq (%rax), %r12
movsd (%r12,%rdx), %xmm10
movapd %xmm11, %xmm0
xorpd %xmm8, %xmm0
movapd %xmm10, %xmm12
subsd %xmm7, %xmm12
subsd %xmm3, %xmm12
movapd %xmm10, %xmm9
mulsd %xmm1, %xmm9
mulsd %xmm9, %xmm12
subsd %xmm12, %xmm0
movapd %xmm0, %xmm9
movapd %xmm11, %xmm0
mulsd %xmm5, %xmm0
addsd %xmm6, %xmm10
divsd %xmm10, %xmm0
addsd %xmm4, %xmm0
mulsd %xmm2, %xmm0
mulsd %xmm9, %xmm0
addsd %xmm11, %xmm0
movsd %xmm0, (%rbx)
movsd (%rdi,%rdx), %xmm11
movsd (%r9,%rdx), %xmm10
movapd %xmm11, %xmm0
xorpd %xmm8, %xmm0
movapd %xmm10, %xmm12
subsd %xmm7, %xmm12
subsd %xmm3, %xmm12
movapd %xmm10, %xmm9
mulsd %xmm1, %xmm9
mulsd %xmm9, %xmm12
subsd %xmm12, %xmm0
movapd %xmm0, %xmm9
movapd %xmm11, %xmm0
mulsd %xmm5, %xmm0
addsd %xmm6, %xmm10
divsd %xmm10, %xmm0
addsd %xmm4, %xmm0
mulsd %xmm2, %xmm0
mulsd %xmm9, %xmm0
addsd %xmm11, %xmm0
movsd %xmm0, (%rdi,%rdx)
addq $8, %rdx
cmpq %r8, %rdx
jne .L94
.L96:
addq $8, %rcx
addq $8, %rax
addl %esi, %r10d
cmpq %r11, %rcx
je .L75
.L93:
testl %ebp, %ebp
jg .L95
jmp .L96
.L76:
testl %ecx, %ecx
jg .L97
.L75:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3954:
.size _Z8simulatePPdS0_S0_diidddddddS_S_S_i, .-_Z8simulatePPdS0_S0_diidddddddS_S_S_i
.section .rodata.str1.1
.LC10:
.string "\n Hello I am waris"
.LC17:
.string "Grid Size : "
.LC18:
.string "Duration of Sim : "
.LC19:
.string "Time step dt : "
.LC20:
.string "Process geometry: "
.LC21:
.string " x "
.LC22:
.string "Communication : DISABLED"
.section .rodata.str1.8
.align 8
.LC30:
.string "Number of Iterations : "
.align 8
.LC31:
.string "Elapsed Time (sec) : "
.align 8
.LC32:
.string "Sustained Gflops Rate : "
.align 8
.LC33:
.string "Sustained Bandwidth (GB/sec): "
.section .rodata.str1.1
.LC34:
.string "Max: "
.LC35:
.string " L2norm: "
.LC36:
.string "1D Max : "
.LC37:
.string " 1D L2norm: "
.text
.globl main
.type main, @function
main:
.LFB3955:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movl %edi, %ebx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq .LC10(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq .LC11(%rip), %rax
movq %rax, 104(%rsp)
movl $200, 80(%rsp)
movl $0, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $0, 96(%rsp)
movl $1, 100(%rsp)
leaq 80(%rsp), %rcx
leaq 104(%rsp), %rdx
subq $8, %rsp
.cfi_def_cfa_offset 200
leaq 108(%rsp), %rax
pushq %rax
.cfi_def_cfa_offset 208
leaq 112(%rsp), %rax
pushq %rax
.cfi_def_cfa_offset 216
leaq 108(%rsp), %rax
pushq %rax
.cfi_def_cfa_offset 224
leaq 124(%rsp), %r9
leaq 120(%rsp), %r8
movq %rbp, %rsi
movl %ebx, %edi
call _Z7cmdLineiPPcRdRiS2_S2_S2_S2_S2_
movl 112(%rsp), %ebx
leal 2(%rbx), %ebp
addq $32, %rsp
.cfi_def_cfa_offset 192
movl %ebp, %esi
movl %ebp, %edi
call _Z7alloc2Dii
movq %rax, 8(%rsp)
movl %ebp, %esi
movl %ebp, %edi
call _Z7alloc2Dii
movq %rax, %r14
movl %ebp, %esi
movl %ebp, %edi
call _Z7alloc2Dii
movq %rax, 32(%rsp)
movl %ebp, %r13d
imull %ebp, %r13d
sall $3, %r13d
movslq %r13d, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, 24(%rsp)
movq %r13, %rdi
call malloc@PLT
movq %rax, %r12
movq %r13, %rdi
call malloc@PLT
movq %rax, %r15
testl %ebx, %ebx
jle .L109
leaq 8(%r14), %rdx
movq 32(%rsp), %rax
leaq 8(%rax), %r8
movslq %ebp, %r10
salq $3, %r10
leaq (%r12,%r10), %rdi
leaq (%r15,%r10), %rsi
leal -1(%rbx), %r13d
movl %r13d, %eax
leaq 16(%r14,%rax,8), %r11
leaq 16(,%rax,8), %r9
movq %rdx, %rcx
movl %ebp, 16(%rsp)
.L110:
movl $8, %eax
.L111:
movq (%rcx), %rbp
movq $0x000000000, 0(%rbp,%rax)
movq (%r8), %rbp
movq $0x000000000, 0(%rbp,%rax)
movq $0x000000000, (%rdi,%rax)
movq $0x000000000, (%rsi,%rax)
addq $8, %rax
cmpq %r9, %rax
jne .L111
addq $8, %rcx
addq $8, %r8
addq %r10, %rdi
addq %r10, %rsi
cmpq %r11, %rcx
jne .L110
movl 16(%rsp), %ebp
movl %ebx, %r8d
shrl $31, %r8d
addl %ebx, %r8d
sarl %r8d
leal 1(%r8), %r9d
movslq %r9d, %r9
salq $3, %r9
leal 2(%r8), %edi
movslq %edi, %rdi
subl %r8d, %r13d
addq %r13, %rdi
salq $3, %rdi
movl %ebp, %r10d
movsd .LC7(%rip), %xmm0
.L115:
cmpl %ebx, %r8d
jge .L113
movslq %r10d, %rax
leaq (%r12,%rax,8), %rsi
movq %r9, %rax
.L114:
movq (%rdx), %rcx
movsd %xmm0, (%rcx,%rax)
movsd %xmm0, (%rsi,%rax)
addq $8, %rax
cmpq %rdi, %rax
jne .L114
.L113:
addq $8, %rdx
addl %ebp, %r10d
cmpq %r11, %rdx
jne .L115
.L109:
movl %ebx, %eax
shrl $31, %eax
addl %ebx, %eax
sarl %eax
leal 1(%rax), %r8d
cmpl %r8d, %ebx
jl .L116
movslq %r8d, %rdx
movq 32(%rsp), %rdi
leaq (%rdi,%rdx,8), %rcx
imull %ebp, %r8d
leal -1(%rbx), %edx
movl %edx, %esi
subl %eax, %esi
cltq
addq %rsi, %rax
leaq 16(%rdi,%rax,8), %r9
movl %edx, %edx
leaq 16(,%rdx,8), %rdi
movsd .LC7(%rip), %xmm0
jmp .L117
.L119:
movslq %r8d, %rax
leaq (%r15,%rax,8), %rsi
movl $8, %eax
.L118:
movq (%rcx), %rdx
movsd %xmm0, (%rdx,%rax)
movsd %xmm0, (%rsi,%rax)
addq $8, %rax
cmpq %rdi, %rax
jne .L118
.L120:
addq $8, %rcx
addl %ebp, %r8d
cmpq %r9, %rcx
je .L116
.L117:
testl %ebx, %ebx
jg .L119
jmp .L120
.L116:
pxor %xmm7, %xmm7
cvtsi2sdl %ebx, %xmm7
movsd %xmm7, 64(%rsp)
movsd .LC7(%rip), %xmm0
divsd %xmm7, %xmm0
mulsd %xmm0, %xmm0
movapd %xmm0, %xmm1
mulsd .LC12(%rip), %xmm1
addsd .LC13(%rip), %xmm1
movapd %xmm0, %xmm2
divsd %xmm1, %xmm2
movsd .LC14(%rip), %xmm1
comisd %xmm2, %xmm1
jbe .L140
mulsd .LC15(%rip), %xmm2
movsd %xmm2, 40(%rsp)
jmp .L121
.L140:
movsd .LC9(%rip), %xmm5
movsd %xmm5, 40(%rsp)
.L121:
movsd 40(%rsp), %xmm1
mulsd .LC16(%rip), %xmm1
movapd %xmm1, %xmm6
divsd %xmm0, %xmm6
movsd %xmm6, 56(%rsp)
leaq .LC17(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC18(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 104(%rsp), %xmm7
movsd %xmm7, 48(%rsp)
movapd %xmm7, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC19(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 40(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC20(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 88(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC21(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 92(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
cmpl $0, 96(%rsp)
jne .L144
.L123:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call _Z7getTimev
movsd %xmm0, 72(%rsp)
movl $0, %r13d
movq $0x000000000, 16(%rsp)
pxor %xmm0, %xmm0
movsd 48(%rsp), %xmm6
comisd %xmm0, %xmm6
ja .L126
movq %r12, %rax
movq 24(%rsp), %r12
movq %rax, 24(%rsp)
movq %r14, %rax
movq 8(%rsp), %r14
movq %rax, 8(%rsp)
movl $0, %r13d
jmp .L124
.L144:
leaq .LC22(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L123
.L132:
movq 24(%rsp), %rax
movq %r12, 24(%rsp)
movq %rax, %r12
movq 8(%rsp), %rax
movq %r14, 8(%rsp)
movq %rax, %r14
.L126:
movsd 16(%rsp), %xmm3
movsd 40(%rsp), %xmm2
addsd %xmm2, %xmm3
movsd %xmm3, 16(%rsp)
addl $1, %r13d
subq $8, %rsp
.cfi_def_cfa_offset 200
pushq %rbp
.cfi_def_cfa_offset 208
pushq %r15
.cfi_def_cfa_offset 216
pushq %r12
.cfi_def_cfa_offset 224
movq 56(%rsp), %r9
movsd .LC23(%rip), %xmm7
movsd .LC24(%rip), %xmm6
movsd .LC25(%rip), %xmm5
movsd .LC26(%rip), %xmm4
movapd %xmm7, %xmm3
movsd .LC27(%rip), %xmm1
movl %ebx, %r8d
movl %ebx, %ecx
movsd 88(%rsp), %xmm0
movq 64(%rsp), %rdx
movq %r14, %rsi
movq 40(%rsp), %rdi
call _Z8simulatePPdS0_S0_diidddddddS_S_S_i
addq $32, %rsp
.cfi_def_cfa_offset 192
movsd 48(%rsp), %xmm4
comisd 16(%rsp), %xmm4
ja .L132
.L124:
call _Z7getTimev
movapd %xmm0, %xmm5
subsd 72(%rsp), %xmm5
movsd %xmm5, 16(%rsp)
pxor %xmm1, %xmm1
cvtsi2sdl %r13d, %xmm1
movsd 64(%rsp), %xmm6
movapd %xmm6, %xmm0
mulsd .LC28(%rip), %xmm0
mulsd %xmm6, %xmm0
mulsd %xmm1, %xmm0
mulsd .LC29(%rip), %xmm0
divsd %xmm5, %xmm0
movsd %xmm0, 40(%rsp)
movl %ebx, %eax
imull %ebx, %eax
cltq
salq $3, %rax
js .L127
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
.L128:
mulsd .LC6(%rip), %xmm0
mulsd .LC28(%rip), %xmm1
mulsd %xmm1, %xmm0
movapd %xmm0, %xmm5
divsd 16(%rsp), %xmm5
movsd %xmm5, 48(%rsp)
leaq .LC30(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r13d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC31(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 16(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC32(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 40(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC33(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 48(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 112(%rsp), %r13
movq %r13, %rcx
movl %ebx, %edx
movl %ebx, %esi
movq 8(%rsp), %rdi
call _Z5statsPPdiiS_
movsd %xmm0, 16(%rsp)
leaq .LC34(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 112(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC35(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 16(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl %ebp, %r8d
movq %r13, %rcx
movl %ebx, %edx
movl %ebx, %esi
movq 24(%rsp), %rbx
movq %rbx, %rdi
call _Z7stats1DPdiiS_i
movsd %xmm0, 16(%rsp)
leaq .LC36(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 112(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC37(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 16(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r14, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 32(%rsp), %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L145
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L127:
.cfi_restore_state
shrq %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
jmp .L128
.L145:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3955:
.size main, .-main
.globl _Z52__device_stub__Z17simulate_version1diidddddddPdS_S_idiidddddddPdS_S_i
.type _Z52__device_stub__Z17simulate_version1diidddddddPdS_S_idiidddddddPdS_S_i, @function
_Z52__device_stub__Z17simulate_version1diidddddddPdS_S_idiidddddddPdS_S_i:
.LFB3980:
.cfi_startproc
endbr64
subq $312, %rsp
.cfi_def_cfa_offset 320
movsd %xmm0, 104(%rsp)
movl %edi, 100(%rsp)
movl %esi, 96(%rsp)
movsd %xmm1, 88(%rsp)
movsd %xmm2, 80(%rsp)
movsd %xmm3, 72(%rsp)
movsd %xmm4, 64(%rsp)
movsd %xmm5, 56(%rsp)
movsd %xmm6, 48(%rsp)
movsd %xmm7, 40(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 296(%rsp)
xorl %eax, %eax
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 100(%rsp), %rax
movq %rax, 184(%rsp)
leaq 96(%rsp), %rax
movq %rax, 192(%rsp)
leaq 88(%rsp), %rax
movq %rax, 200(%rsp)
leaq 80(%rsp), %rax
movq %rax, 208(%rsp)
leaq 72(%rsp), %rax
movq %rax, 216(%rsp)
leaq 64(%rsp), %rax
movq %rax, 224(%rsp)
leaq 56(%rsp), %rax
movq %rax, 232(%rsp)
leaq 48(%rsp), %rax
movq %rax, 240(%rsp)
leaq 40(%rsp), %rax
movq %rax, 248(%rsp)
leaq 32(%rsp), %rax
movq %rax, 256(%rsp)
leaq 24(%rsp), %rax
movq %rax, 264(%rsp)
leaq 16(%rsp), %rax
movq %rax, 272(%rsp)
leaq 12(%rsp), %rax
movq %rax, 280(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $1, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
leaq 120(%rsp), %rcx
leaq 112(%rsp), %rdx
leaq 140(%rsp), %rsi
leaq 128(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L150
.L146:
movq 296(%rsp), %rax
subq %fs:40, %rax
jne .L151
addq $312, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L150:
.cfi_restore_state
pushq 120(%rsp)
.cfi_def_cfa_offset 328
pushq 120(%rsp)
.cfi_def_cfa_offset 336
leaq 192(%rsp), %r9
movq 156(%rsp), %rcx
movl 164(%rsp), %r8d
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
leaq _Z17simulate_version1diidddddddPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 320
jmp .L146
.L151:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3980:
.size _Z52__device_stub__Z17simulate_version1diidddddddPdS_S_idiidddddddPdS_S_i, .-_Z52__device_stub__Z17simulate_version1diidddddddPdS_S_idiidddddddPdS_S_i
.globl _Z17simulate_version1diidddddddPdS_S_i
.type _Z17simulate_version1diidddddddPdS_S_i, @function
_Z17simulate_version1diidddddddPdS_S_i:
.LFB3981:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z17simulate_version1diidddddddPdS_S_idiidddddddPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3981:
.size _Z17simulate_version1diidddddddPdS_S_i, .-_Z17simulate_version1diidddddddPdS_S_i
.section .rodata.str1.8
.align 8
.LC38:
.string "_Z17simulate_version1diidddddddPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3983:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC38(%rip), %rdx
movq %rdx, %rcx
leaq _Z17simulate_version1diidddddddPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3983:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.str1.1
.LC39:
.string "n"
.LC40:
.string "px"
.LC41:
.string "py"
.LC42:
.string "tfinal"
.LC43:
.string "plot"
.LC44:
.string "nocomm"
.LC45:
.string "numthreads"
.section .data.rel.local,"aw"
.align 32
.type _ZZ7cmdLineiPPcRdRiS2_S2_S2_S2_S2_E12long_options, @object
.size _ZZ7cmdLineiPPcRdRiS2_S2_S2_S2_S2_E12long_options, 224
_ZZ7cmdLineiPPcRdRiS2_S2_S2_S2_S2_E12long_options:
.quad .LC39
.long 1
.zero 4
.quad 0
.long 110
.zero 4
.quad .LC40
.long 1
.zero 4
.quad 0
.long 120
.zero 4
.quad .LC41
.long 1
.zero 4
.quad 0
.long 121
.zero 4
.quad .LC42
.long 1
.zero 4
.quad 0
.long 116
.zero 4
.quad .LC43
.long 1
.zero 4
.quad 0
.long 112
.zero 4
.quad .LC44
.long 0
.zero 4
.quad 0
.long 107
.zero 4
.quad .LC45
.long 1
.zero 4
.quad 0
.long 111
.zero 4
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long -1074790400
.align 8
.LC4:
.long -1598689907
.long 1051772663
.align 8
.LC6:
.long 0
.long 1074790400
.align 8
.LC7:
.long 0
.long 1072693248
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC8:
.long 0
.long -2147483648
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC9:
.long -847035317
.long 1073378106
.align 8
.LC11:
.long 0
.long 1083129856
.align 8
.LC12:
.long 1030792151
.long 1076156170
.align 8
.LC13:
.long -350469331
.long 1059731170
.align 8
.LC14:
.long 916791160
.long 1073469340
.align 8
.LC15:
.long 1717986918
.long 1072588390
.align 8
.LC16:
.long -350469331
.long 1057634018
.align 8
.LC23:
.long -1717986918
.long 1069128089
.align 8
.LC24:
.long 858993459
.long 1070805811
.align 8
.LC25:
.long 515396076
.long 1068624773
.align 8
.LC26:
.long 1202590843
.long 1065646817
.align 8
.LC27:
.long 0
.long 1075838976
.align 8
.LC28:
.long -400107883
.long 1041313291
.align 8
.LC29:
.long 0
.long 1077673984
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
Implement your CUDA kernel in this file
*/
/*
* Solves the Panfilov model using an explicit numerical scheme.
* Based on code orginally provided by Xing Cai, Simula Research Laboratory
* and reimplementation by Scott B. Baden, UCSD
*
* Modified and restructured by Didem Unat, Koc University
*
* Refer to "Detailed Numerical Analyses of the Aliev-Panfilov Model on GPGPU"
* https://www.simula.no/publications/detailed-numerical-analyses-aliev-panfilov-model-gpgpu
* by Xing Cai, Didem Unat and Scott Baden
*
*/
#include <stdio.h>
#include <assert.h>
#include <stdlib.h>
#include <iostream>
#include <iomanip>
#include <string.h>
#include <math.h>
#include <sys/time.h>
#include <getopt.h>
using namespace std;
#define TILE_DIM 16
// External functions
//extern "C" void splot(double **E, double T, int niter, int m, int n);
void cmdLine(int argc, char *argv[], double &T, int &n, int &px, int &py, int &plot_freq, int &no_comm, int &num_threads){
/// Command line arguments
// Default value of the domain sizes
static struct option long_options[] = {
{"n", required_argument, 0, 'n'},
{"px", required_argument, 0, 'x'},
{"py", required_argument, 0, 'y'},
{"tfinal", required_argument, 0, 't'},
{"plot", required_argument, 0, 'p'},
{"nocomm", no_argument, 0, 'k'},
{"numthreads", required_argument, 0, 'o'},
};
// Process command line arguments
int ac;
for (ac = 1; ac < argc; ac++)
{
int c;
while ((c = getopt_long(argc, argv, "n:x:y:t:kp:o:", long_options, NULL)) != -1)
{
switch (c)
{
// Size of the computational box
case 'n':
n = atoi(optarg);
break;
// X processor geometry
case 'x':
px = atoi(optarg);
// Y processor geometry
case 'y':
py = atoi(optarg);
// Length of simulation, in simulated time units
case 't':
T = atof(optarg);
break;
// Turn off communication
case 'k':
no_comm = 1;
break;
// Plot the excitation variable
case 'p':
plot_freq = atoi(optarg);
break;
// Plot the excitation variable
case 'o':
num_threads = atoi(optarg);
break;
// Error
default:
printf("Usage: a.out [-n <domain size>] [-t <final time >]\n\t [-p <plot frequency>]\n\t[-px <x processor geometry> [-py <y proc. geometry] [-k turn off communication] [-o <Number of OpenMP threads>]\n");
exit(-1);
}
}
}
}
// Utilities
//
// Timer
// Make successive calls and take a difference to get the elapsed time.
static const double kMicro = 1.0e-6;
double getTime(){
struct timeval TV;
struct timezone TZ;
const int RC = gettimeofday(&TV, &TZ);
if (RC == -1)
{
cerr << "ERROR: Bad call to gettimeofday" << endl;
return (-1);
}
return (((double)TV.tv_sec) + kMicro * ((double)TV.tv_usec));
}
// end getTime()
// Allocate a 2D array
double **alloc2D(int m, int n){
double **E;
int nx = n, ny = m;
E = (double **)malloc(sizeof(double *) * ny + sizeof(double) * nx * ny);
assert(E);
int row;
for (row = 0; row < ny; row++)
E[row] = (double *)(E + ny) + row * nx;
return (E);
}
// Reports statistics about the computation
// These values should not vary (except to within roundoff)
// when we use different numbers of processes to solve the problem
double stats(double **E, int m, int n, double *_mx){
double mx = -1;
double l2norm = 0;
int col, row;
for (row = 1; row <= m; row++)
for (col = 1; col <= n; col++)
{
l2norm += E[row][col] * E[row][col];
if (E[row][col] > mx)
mx = E[row][col];
}
*_mx = mx;
l2norm /= (double)((m) * (n));
l2norm = sqrt(l2norm);
return l2norm;
}
double stats1D(double *E, int m, int n, double *_mx, int WIDTH){
double mx = -1;
double l2norm = 0;
int col, row;
int index = -1;
for (row = 1; row <= m; row++) {
for (col = 1; col <= n; col++){
index = row * WIDTH + col;
l2norm += E[index] * E[index];
if (E[index] > mx) {
mx = E[index];
}
}
}
*_mx = mx;
l2norm /= (double)((m) * (n));
l2norm = sqrt(l2norm);
return l2norm;
}
__global__ void simulate_version1(const double alpha, const int n, const int m, const double kk, const double dt, const double a, const double epsilon, const double M1, const double M2, const double b, double* E_1D, double* E_prev_1D, double* R_1D, int WIDTH){
int RADIUS = 1;
int row = blockIdx.y * blockDim.y + threadIdx.y + RADIUS;
int col = blockIdx.x * blockDim.x + threadIdx.x + RADIUS;
if (row < (WIDTH -1) && col < (WIDTH -1)) {
E_1D[row*WIDTH+col] = E_prev_1D[row*WIDTH+col] + alpha * (E_prev_1D[row*WIDTH+(col+1)] + E_prev_1D[row*WIDTH + (col-1)] - 4 * E_prev_1D[row*WIDTH+ col] + E_prev_1D[(row + 1)*WIDTH + col] + E_prev_1D[(row - 1) * WIDTH + col]);
}
}
void simulate(double **E, double **E_prev, double **R, const double alpha, const int n, const int m, const double kk, const double dt, const double a, const double epsilon, const double M1, const double M2, const double b, double* E_1D, double* E_prev_1D, double* R_1D, int WIDTH){
int col, row;
/*
* Copy data from boundary of the computational box
* to the padding region, set up for differencing
* on the boundary of the computational box
* Using mirror boundaries
*/
for (row = 1; row <= m; row++) {
E_prev[row][0] = E_prev[row][2];
E_prev_1D[row* WIDTH + 0] = E_prev_1D[row*WIDTH + 2];
}
for (row = 1; row <= m; row++) {
E_prev[row][n + 1] = E_prev[row][n - 1];
E_prev_1D[row*WIDTH+ (n+1)] = E_prev_1D[row*WIDTH + (n-1)];
}
for (col = 1; col <= n; col++) {
E_prev[0][col] = E_prev[2][col];
E_prev_1D[0*WIDTH+col] = E_prev_1D[2*WIDTH+ col];
}
for (col = 1; col <= n; col++) {
E_prev[m + 1][col] = E_prev[m - 1][col];
E_prev_1D[(m+1)*WIDTH+ col] = E_prev_1D[(m-1)*WIDTH+ col];
}
// ================ Kernel Setup ==============
// double *d_E_1D, *d_E_prev_1D, *d_R_1D;
// const dim3 block_size(TILE_DIM, TILE_DIM);
// const dim3 num_blocks(WIDTH / block_size.x, WIDTH / block_size.y);
// int Total_Bytes = WIDTH * WIDTH * sizeof(double);
// // Allocate space on the device
// cudaMalloc( &d_E_1D, Total_Bytes) ;
// cudaMalloc( &d_E_prev_1D,Total_Bytes) ;
// cudaMalloc(&d_R_1D, Total_Bytes);
// // Copy input data to device
// cudaMemcpy(d_E_1D, E_1D, Total_Bytes, cudaMemcpyHostToDevice) ;
// cudaMemcpy(d_E_prev_1D, E_prev_1D, Total_Bytes, cudaMemcpyHostToDevice) ;
// cudaMemcpy(d_R_1D, R_1D, Total_Bytes, cudaMemcpyHostToDevice) ;
// // simulate_version1<<<num_blocks, block_size>>>(alpha, n, m, kk, dt, a, epsilon, M1, M2, b, d_E_1D, d_E_prev_1D, d_R_1D, WIDTH);
// cudaMemcpy(E_1D ,d_E_1D, Total_Bytes, cudaMemcpyDeviceToHost);
// cudaFree(d_E_1D);
// cudaFree(d_E_prev_1D);
// cudaFree(d_R_1D);
// =================================================
// Solve for the excitation, the PDE
for (row = 1; row <= m; row++){
for (col = 1; col <= n; col++){
E[row][col] = E_prev[row][col] + alpha * (E_prev[row][col + 1] + E_prev[row][col - 1] - 4 * E_prev[row][col] + E_prev[row + 1][col] + E_prev[row - 1][col]);
E_1D[row*WIDTH+col] = E_prev_1D[row*WIDTH+col] + alpha * (E_prev_1D[row*WIDTH+(col+1)] + E_prev_1D[row*WIDTH + (col-1)] - 4 * E_prev_1D[row*WIDTH+ col] + E_prev_1D[(row + 1)*WIDTH + col] + E_prev_1D[(row - 1) * WIDTH + col]);
}
}
/*
* Solve the ODE, advancing excitation and recovery to the
* next timtestep
*/
int index = -1;
for (row = 1; row <= m; row++){
for (col = 1; col <= n; col++) {
E[row][col] = E[row][col] - dt * (kk * E[row][col] * (E[row][col] - a) * (E[row][col] - 1) + E[row][col] * R[row][col]);
index = row * WIDTH + col;
E_1D[index] = E_1D[index] - dt * (kk * E_1D[index] * (E_1D[index] - a) * (E_1D[index] - 1) + E_1D[index] * R_1D[index]);
}
}
for (row = 1; row <= m; row++){
for (col = 1; col <= n; col++) {
R[row][col] = R[row][col] + dt * (epsilon + M1 * R[row][col] / (E[row][col] + M2)) * (-R[row][col] - kk * E[row][col] * (E[row][col] - b - 1));
index = row * WIDTH + col;
R_1D[index] = R_1D[index] + dt * (epsilon + M1 * R_1D[index] / (E_1D[index] + M2)) * (-R_1D[index] - kk * E_1D[index] * (E_1D[index] - b - 1));
}
}
}
// Main program
int main(int argc, char **argv){
/*
* Solution arrays
* E is the "Excitation" variable, a voltage
* R is the "Recovery" variable
* E_prev is the Excitation variable for the previous timestep,
* and is used in time integration
*/
cout<< "\n Hello I am waris"<<endl;
double **E, **R, **E_prev;
double * E_1D, *R_1D, *E_prev_1D;
// Various constants - these definitions shouldn't change
const double a = 0.1, b = 0.1, kk = 8.0, M1 = 0.07, M2 = 0.3, epsilon = 0.01, d = 5e-5;
double T = 1000.0;
int m = 200, n = 200;
int plot_freq = 0;
int px = 1, py = 1;
int no_comm = 0;
int num_threads = 1;
int WIDTH;
//int size;
cmdLine(argc, argv, T, n, px, py, plot_freq, no_comm, num_threads);
m = n;
// Allocate contiguous memory for solution arrays
// The computational box is defined on [1:m+1,1:n+1]
// We pad the arrays in order to facilitate differencing on the
// boundaries of the computation box
int Total_Bytes = (m+2) * (n+2) *sizeof(double);
WIDTH = m+2;
E = alloc2D(m + 2, n + 2);
E_prev = alloc2D(m + 2, n + 2);
R = alloc2D(m + 2, n + 2);
E_1D = (double *) malloc (Total_Bytes);
E_prev_1D = (double *) malloc (Total_Bytes);
R_1D = (double *) malloc (Total_Bytes);
int col, row;
// Initialization
for (row = 1; row <= m; row++) {
for (col = 1; col <= n; col++) {
E_prev[row][col] = 0;
R[row][col] = 0;
E_prev_1D[row*WIDTH + col] = 0;
R_1D[row*WIDTH + col] = 0;
}
}
for (row = 1; row <= m; row++) {
for (col = n / 2 + 1; col <= n; col++) {
E_prev[row][col] = 1.0;
E_prev_1D[row*WIDTH + col] = 1.0;
}
}
for (row = m / 2 + 1; row <= m; row++) {
for (col = 1; col <= n; col++) {
R[row][col] = 1.0;
R_1D[row*WIDTH + col] = 1.0;
}
}
//cout<< "check 1"<<endl;
double dx = 1.0 / n;
// For time integration, these values shouldn't change
double rp = kk * (b + 1) * (b + 1) / 4;
double dte = (dx * dx) / (d * 4 + ((dx * dx)) * (rp + kk));
double dtr = 1 / (epsilon + ((M1 / M2) * rp));
double dt = (dte < dtr) ? 0.95 * dte : 0.95 * dtr;
double alpha = d * dt / (dx * dx);
cout << "Grid Size : " << n << endl;
cout << "Duration of Sim : " << T << endl;
cout << "Time step dt : " << dt << endl;
cout << "Process geometry: " << px << " x " << py << endl;
if (no_comm) {
cout << "Communication : DISABLED" << endl;
}
cout << endl;
// Start the timer
double t0 = getTime();
// Simulated time is different from the integer timestep number
// Simulated time
double t = 0.0;
// Integer timestep number
int niter = 0;
while (t < T){
t += dt;
niter++;
simulate(E, E_prev, R, alpha, n, m, kk, dt, a, epsilon, M1, M2, b, E_1D, E_prev_1D, R_1D, WIDTH);
//swap current E with previous E
double **tmp = E;
E = E_prev;
E_prev = tmp;
double *tmp2 = E_1D;
E_1D = E_prev_1D;
E_prev_1D = tmp2;
// if (plot_freq){
// int k = (int)(t / plot_freq);
// if ((t - k * plot_freq) < dt){
// splot(E, t, niter, m + 2, n + 2);
// }
// }
} //end of while loop
double time_elapsed = getTime() - t0;
double Gflops = (double)(niter * (1E-9 * n * n) * 28.0) / time_elapsed;
double BW = (double)(niter * 1E-9 * (n * n * sizeof(double) * 4.0)) / time_elapsed;
cout << "Number of Iterations : " << niter << endl;
cout << "Elapsed Time (sec) : " << time_elapsed << endl;
cout << "Sustained Gflops Rate : " << Gflops << endl;
cout << "Sustained Bandwidth (GB/sec): " << BW << endl << endl;
double mx;
double l2norm = stats(E_prev, m, n, &mx);
cout << "Max: " << mx << " L2norm: " << l2norm << endl;
l2norm = stats1D(E_prev_1D, m, n, &mx, WIDTH);
cout << "1D Max : " << mx << " 1D L2norm: " << l2norm << endl;
// if (plot_freq){
// cout << "\n\nEnter any input to close the program and the plot..." << endl;
// getchar();
// }
free(E);
free(E_prev);
free(R);
free(E_1D);
free(E_prev_1D);
free(R_1D);
return 0;
}
/* **********************************************************
* Author : Urvashi R.V. [04/06/2004]
* Modified by Didem Unat [03/23/18]
*************************************************************/
//#include <stdio.h>
/* Function to plot the 2D array
* 'gnuplot' is instantiated via a pipe and
* the values to be plotted are passed through, along
* with gnuplot commands */
// FILE *gnu = NULL;
// void splot(double **U, double T, int niter, int m, int n){
// int col, row;
// if (gnu == NULL)
// gnu = popen("gnuplot", "w");
// double mx = -1, mn = 32768;
// for (row = 0; row < m; row++)
// for (col = 0; col < n; col++)
// {
// if (U[row][col] > mx)
// mx = U[row][col];
// if (U[row][col] < mn)
// mn = U[row][col];
// }
// fprintf(gnu, "set title \"T = %f [niter = %d]\"\n", T, niter);
// fprintf(gnu, "set size square\n");
// fprintf(gnu, "set key off\n");
// fprintf(gnu, "set pm3d map\n");
// // Various color schemes
// fprintf(gnu, "set palette defined (-3 \"blue\", 0 \"white\", 1 \"red\")\n");
// // fprintf(gnu,"set palette rgbformulae 22, 13, 31\n");
// // fprintf(gnu,"set palette rgbformulae 30, 31, 32\n");
// fprintf(gnu, "splot [0:%d] [0:%d][%f:%f] \"-\"\n", m - 1, n - 1, mn, mx);
// for (row = 0; row < m; row++)
// {
// for (col = 0; col < n; col++)
// {
// fprintf(gnu, "%d %d %f\n", col, row, U[col][row]);
// }
// fprintf(gnu, "\n");
// }
// fprintf(gnu, "e\n");
// fflush(gnu);
// return;
// } | /*
Implement your CUDA kernel in this file
*/
/*
* Solves the Panfilov model using an explicit numerical scheme.
* Based on code orginally provided by Xing Cai, Simula Research Laboratory
* and reimplementation by Scott B. Baden, UCSD
*
* Modified and restructured by Didem Unat, Koc University
*
* Refer to "Detailed Numerical Analyses of the Aliev-Panfilov Model on GPGPU"
* https://www.simula.no/publications/detailed-numerical-analyses-aliev-panfilov-model-gpgpu
* by Xing Cai, Didem Unat and Scott Baden
*
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#include <stdlib.h>
#include <iostream>
#include <iomanip>
#include <string.h>
#include <math.h>
#include <sys/time.h>
#include <getopt.h>
using namespace std;
#define TILE_DIM 16
// External functions
//extern "C" void splot(double **E, double T, int niter, int m, int n);
void cmdLine(int argc, char *argv[], double &T, int &n, int &px, int &py, int &plot_freq, int &no_comm, int &num_threads){
/// Command line arguments
// Default value of the domain sizes
static struct option long_options[] = {
{"n", required_argument, 0, 'n'},
{"px", required_argument, 0, 'x'},
{"py", required_argument, 0, 'y'},
{"tfinal", required_argument, 0, 't'},
{"plot", required_argument, 0, 'p'},
{"nocomm", no_argument, 0, 'k'},
{"numthreads", required_argument, 0, 'o'},
};
// Process command line arguments
int ac;
for (ac = 1; ac < argc; ac++)
{
int c;
while ((c = getopt_long(argc, argv, "n:x:y:t:kp:o:", long_options, NULL)) != -1)
{
switch (c)
{
// Size of the computational box
case 'n':
n = atoi(optarg);
break;
// X processor geometry
case 'x':
px = atoi(optarg);
// Y processor geometry
case 'y':
py = atoi(optarg);
// Length of simulation, in simulated time units
case 't':
T = atof(optarg);
break;
// Turn off communication
case 'k':
no_comm = 1;
break;
// Plot the excitation variable
case 'p':
plot_freq = atoi(optarg);
break;
// Plot the excitation variable
case 'o':
num_threads = atoi(optarg);
break;
// Error
default:
printf("Usage: a.out [-n <domain size>] [-t <final time >]\n\t [-p <plot frequency>]\n\t[-px <x processor geometry> [-py <y proc. geometry] [-k turn off communication] [-o <Number of OpenMP threads>]\n");
exit(-1);
}
}
}
}
// Utilities
//
// Timer
// Make successive calls and take a difference to get the elapsed time.
static const double kMicro = 1.0e-6;
double getTime(){
struct timeval TV;
struct timezone TZ;
const int RC = gettimeofday(&TV, &TZ);
if (RC == -1)
{
cerr << "ERROR: Bad call to gettimeofday" << endl;
return (-1);
}
return (((double)TV.tv_sec) + kMicro * ((double)TV.tv_usec));
}
// end getTime()
// Allocate a 2D array
double **alloc2D(int m, int n){
double **E;
int nx = n, ny = m;
E = (double **)malloc(sizeof(double *) * ny + sizeof(double) * nx * ny);
assert(E);
int row;
for (row = 0; row < ny; row++)
E[row] = (double *)(E + ny) + row * nx;
return (E);
}
// Reports statistics about the computation
// These values should not vary (except to within roundoff)
// when we use different numbers of processes to solve the problem
double stats(double **E, int m, int n, double *_mx){
double mx = -1;
double l2norm = 0;
int col, row;
for (row = 1; row <= m; row++)
for (col = 1; col <= n; col++)
{
l2norm += E[row][col] * E[row][col];
if (E[row][col] > mx)
mx = E[row][col];
}
*_mx = mx;
l2norm /= (double)((m) * (n));
l2norm = sqrt(l2norm);
return l2norm;
}
double stats1D(double *E, int m, int n, double *_mx, int WIDTH){
double mx = -1;
double l2norm = 0;
int col, row;
int index = -1;
for (row = 1; row <= m; row++) {
for (col = 1; col <= n; col++){
index = row * WIDTH + col;
l2norm += E[index] * E[index];
if (E[index] > mx) {
mx = E[index];
}
}
}
*_mx = mx;
l2norm /= (double)((m) * (n));
l2norm = sqrt(l2norm);
return l2norm;
}
__global__ void simulate_version1(const double alpha, const int n, const int m, const double kk, const double dt, const double a, const double epsilon, const double M1, const double M2, const double b, double* E_1D, double* E_prev_1D, double* R_1D, int WIDTH){
int RADIUS = 1;
int row = blockIdx.y * blockDim.y + threadIdx.y + RADIUS;
int col = blockIdx.x * blockDim.x + threadIdx.x + RADIUS;
if (row < (WIDTH -1) && col < (WIDTH -1)) {
E_1D[row*WIDTH+col] = E_prev_1D[row*WIDTH+col] + alpha * (E_prev_1D[row*WIDTH+(col+1)] + E_prev_1D[row*WIDTH + (col-1)] - 4 * E_prev_1D[row*WIDTH+ col] + E_prev_1D[(row + 1)*WIDTH + col] + E_prev_1D[(row - 1) * WIDTH + col]);
}
}
void simulate(double **E, double **E_prev, double **R, const double alpha, const int n, const int m, const double kk, const double dt, const double a, const double epsilon, const double M1, const double M2, const double b, double* E_1D, double* E_prev_1D, double* R_1D, int WIDTH){
int col, row;
/*
* Copy data from boundary of the computational box
* to the padding region, set up for differencing
* on the boundary of the computational box
* Using mirror boundaries
*/
for (row = 1; row <= m; row++) {
E_prev[row][0] = E_prev[row][2];
E_prev_1D[row* WIDTH + 0] = E_prev_1D[row*WIDTH + 2];
}
for (row = 1; row <= m; row++) {
E_prev[row][n + 1] = E_prev[row][n - 1];
E_prev_1D[row*WIDTH+ (n+1)] = E_prev_1D[row*WIDTH + (n-1)];
}
for (col = 1; col <= n; col++) {
E_prev[0][col] = E_prev[2][col];
E_prev_1D[0*WIDTH+col] = E_prev_1D[2*WIDTH+ col];
}
for (col = 1; col <= n; col++) {
E_prev[m + 1][col] = E_prev[m - 1][col];
E_prev_1D[(m+1)*WIDTH+ col] = E_prev_1D[(m-1)*WIDTH+ col];
}
// ================ Kernel Setup ==============
// double *d_E_1D, *d_E_prev_1D, *d_R_1D;
// const dim3 block_size(TILE_DIM, TILE_DIM);
// const dim3 num_blocks(WIDTH / block_size.x, WIDTH / block_size.y);
// int Total_Bytes = WIDTH * WIDTH * sizeof(double);
// // Allocate space on the device
// cudaMalloc( &d_E_1D, Total_Bytes) ;
// cudaMalloc( &d_E_prev_1D,Total_Bytes) ;
// cudaMalloc(&d_R_1D, Total_Bytes);
// // Copy input data to device
// cudaMemcpy(d_E_1D, E_1D, Total_Bytes, cudaMemcpyHostToDevice) ;
// cudaMemcpy(d_E_prev_1D, E_prev_1D, Total_Bytes, cudaMemcpyHostToDevice) ;
// cudaMemcpy(d_R_1D, R_1D, Total_Bytes, cudaMemcpyHostToDevice) ;
// // simulate_version1<<<num_blocks, block_size>>>(alpha, n, m, kk, dt, a, epsilon, M1, M2, b, d_E_1D, d_E_prev_1D, d_R_1D, WIDTH);
// cudaMemcpy(E_1D ,d_E_1D, Total_Bytes, cudaMemcpyDeviceToHost);
// cudaFree(d_E_1D);
// cudaFree(d_E_prev_1D);
// cudaFree(d_R_1D);
// =================================================
// Solve for the excitation, the PDE
for (row = 1; row <= m; row++){
for (col = 1; col <= n; col++){
E[row][col] = E_prev[row][col] + alpha * (E_prev[row][col + 1] + E_prev[row][col - 1] - 4 * E_prev[row][col] + E_prev[row + 1][col] + E_prev[row - 1][col]);
E_1D[row*WIDTH+col] = E_prev_1D[row*WIDTH+col] + alpha * (E_prev_1D[row*WIDTH+(col+1)] + E_prev_1D[row*WIDTH + (col-1)] - 4 * E_prev_1D[row*WIDTH+ col] + E_prev_1D[(row + 1)*WIDTH + col] + E_prev_1D[(row - 1) * WIDTH + col]);
}
}
/*
* Solve the ODE, advancing excitation and recovery to the
* next timtestep
*/
int index = -1;
for (row = 1; row <= m; row++){
for (col = 1; col <= n; col++) {
E[row][col] = E[row][col] - dt * (kk * E[row][col] * (E[row][col] - a) * (E[row][col] - 1) + E[row][col] * R[row][col]);
index = row * WIDTH + col;
E_1D[index] = E_1D[index] - dt * (kk * E_1D[index] * (E_1D[index] - a) * (E_1D[index] - 1) + E_1D[index] * R_1D[index]);
}
}
for (row = 1; row <= m; row++){
for (col = 1; col <= n; col++) {
R[row][col] = R[row][col] + dt * (epsilon + M1 * R[row][col] / (E[row][col] + M2)) * (-R[row][col] - kk * E[row][col] * (E[row][col] - b - 1));
index = row * WIDTH + col;
R_1D[index] = R_1D[index] + dt * (epsilon + M1 * R_1D[index] / (E_1D[index] + M2)) * (-R_1D[index] - kk * E_1D[index] * (E_1D[index] - b - 1));
}
}
}
// Main program
int main(int argc, char **argv){
/*
* Solution arrays
* E is the "Excitation" variable, a voltage
* R is the "Recovery" variable
* E_prev is the Excitation variable for the previous timestep,
* and is used in time integration
*/
cout<< "\n Hello I am waris"<<endl;
double **E, **R, **E_prev;
double * E_1D, *R_1D, *E_prev_1D;
// Various constants - these definitions shouldn't change
const double a = 0.1, b = 0.1, kk = 8.0, M1 = 0.07, M2 = 0.3, epsilon = 0.01, d = 5e-5;
double T = 1000.0;
int m = 200, n = 200;
int plot_freq = 0;
int px = 1, py = 1;
int no_comm = 0;
int num_threads = 1;
int WIDTH;
//int size;
cmdLine(argc, argv, T, n, px, py, plot_freq, no_comm, num_threads);
m = n;
// Allocate contiguous memory for solution arrays
// The computational box is defined on [1:m+1,1:n+1]
// We pad the arrays in order to facilitate differencing on the
// boundaries of the computation box
int Total_Bytes = (m+2) * (n+2) *sizeof(double);
WIDTH = m+2;
E = alloc2D(m + 2, n + 2);
E_prev = alloc2D(m + 2, n + 2);
R = alloc2D(m + 2, n + 2);
E_1D = (double *) malloc (Total_Bytes);
E_prev_1D = (double *) malloc (Total_Bytes);
R_1D = (double *) malloc (Total_Bytes);
int col, row;
// Initialization
for (row = 1; row <= m; row++) {
for (col = 1; col <= n; col++) {
E_prev[row][col] = 0;
R[row][col] = 0;
E_prev_1D[row*WIDTH + col] = 0;
R_1D[row*WIDTH + col] = 0;
}
}
for (row = 1; row <= m; row++) {
for (col = n / 2 + 1; col <= n; col++) {
E_prev[row][col] = 1.0;
E_prev_1D[row*WIDTH + col] = 1.0;
}
}
for (row = m / 2 + 1; row <= m; row++) {
for (col = 1; col <= n; col++) {
R[row][col] = 1.0;
R_1D[row*WIDTH + col] = 1.0;
}
}
//cout<< "check 1"<<endl;
double dx = 1.0 / n;
// For time integration, these values shouldn't change
double rp = kk * (b + 1) * (b + 1) / 4;
double dte = (dx * dx) / (d * 4 + ((dx * dx)) * (rp + kk));
double dtr = 1 / (epsilon + ((M1 / M2) * rp));
double dt = (dte < dtr) ? 0.95 * dte : 0.95 * dtr;
double alpha = d * dt / (dx * dx);
cout << "Grid Size : " << n << endl;
cout << "Duration of Sim : " << T << endl;
cout << "Time step dt : " << dt << endl;
cout << "Process geometry: " << px << " x " << py << endl;
if (no_comm) {
cout << "Communication : DISABLED" << endl;
}
cout << endl;
// Start the timer
double t0 = getTime();
// Simulated time is different from the integer timestep number
// Simulated time
double t = 0.0;
// Integer timestep number
int niter = 0;
while (t < T){
t += dt;
niter++;
simulate(E, E_prev, R, alpha, n, m, kk, dt, a, epsilon, M1, M2, b, E_1D, E_prev_1D, R_1D, WIDTH);
//swap current E with previous E
double **tmp = E;
E = E_prev;
E_prev = tmp;
double *tmp2 = E_1D;
E_1D = E_prev_1D;
E_prev_1D = tmp2;
// if (plot_freq){
// int k = (int)(t / plot_freq);
// if ((t - k * plot_freq) < dt){
// splot(E, t, niter, m + 2, n + 2);
// }
// }
} //end of while loop
double time_elapsed = getTime() - t0;
double Gflops = (double)(niter * (1E-9 * n * n) * 28.0) / time_elapsed;
double BW = (double)(niter * 1E-9 * (n * n * sizeof(double) * 4.0)) / time_elapsed;
cout << "Number of Iterations : " << niter << endl;
cout << "Elapsed Time (sec) : " << time_elapsed << endl;
cout << "Sustained Gflops Rate : " << Gflops << endl;
cout << "Sustained Bandwidth (GB/sec): " << BW << endl << endl;
double mx;
double l2norm = stats(E_prev, m, n, &mx);
cout << "Max: " << mx << " L2norm: " << l2norm << endl;
l2norm = stats1D(E_prev_1D, m, n, &mx, WIDTH);
cout << "1D Max : " << mx << " 1D L2norm: " << l2norm << endl;
// if (plot_freq){
// cout << "\n\nEnter any input to close the program and the plot..." << endl;
// getchar();
// }
free(E);
free(E_prev);
free(R);
free(E_1D);
free(E_prev_1D);
free(R_1D);
return 0;
}
/* **********************************************************
* Author : Urvashi R.V. [04/06/2004]
* Modified by Didem Unat [03/23/18]
*************************************************************/
//#include <stdio.h>
/* Function to plot the 2D array
* 'gnuplot' is instantiated via a pipe and
* the values to be plotted are passed through, along
* with gnuplot commands */
// FILE *gnu = NULL;
// void splot(double **U, double T, int niter, int m, int n){
// int col, row;
// if (gnu == NULL)
// gnu = popen("gnuplot", "w");
// double mx = -1, mn = 32768;
// for (row = 0; row < m; row++)
// for (col = 0; col < n; col++)
// {
// if (U[row][col] > mx)
// mx = U[row][col];
// if (U[row][col] < mn)
// mn = U[row][col];
// }
// fprintf(gnu, "set title \"T = %f [niter = %d]\"\n", T, niter);
// fprintf(gnu, "set size square\n");
// fprintf(gnu, "set key off\n");
// fprintf(gnu, "set pm3d map\n");
// // Various color schemes
// fprintf(gnu, "set palette defined (-3 \"blue\", 0 \"white\", 1 \"red\")\n");
// // fprintf(gnu,"set palette rgbformulae 22, 13, 31\n");
// // fprintf(gnu,"set palette rgbformulae 30, 31, 32\n");
// fprintf(gnu, "splot [0:%d] [0:%d][%f:%f] \"-\"\n", m - 1, n - 1, mn, mx);
// for (row = 0; row < m; row++)
// {
// for (col = 0; col < n; col++)
// {
// fprintf(gnu, "%d %d %f\n", col, row, U[col][row]);
// }
// fprintf(gnu, "\n");
// }
// fprintf(gnu, "e\n");
// fflush(gnu);
// return;
// } |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
Implement your CUDA kernel in this file
*/
/*
* Solves the Panfilov model using an explicit numerical scheme.
* Based on code orginally provided by Xing Cai, Simula Research Laboratory
* and reimplementation by Scott B. Baden, UCSD
*
* Modified and restructured by Didem Unat, Koc University
*
* Refer to "Detailed Numerical Analyses of the Aliev-Panfilov Model on GPGPU"
* https://www.simula.no/publications/detailed-numerical-analyses-aliev-panfilov-model-gpgpu
* by Xing Cai, Didem Unat and Scott Baden
*
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#include <stdlib.h>
#include <iostream>
#include <iomanip>
#include <string.h>
#include <math.h>
#include <sys/time.h>
#include <getopt.h>
using namespace std;
#define TILE_DIM 16
// External functions
//extern "C" void splot(double **E, double T, int niter, int m, int n);
void cmdLine(int argc, char *argv[], double &T, int &n, int &px, int &py, int &plot_freq, int &no_comm, int &num_threads){
/// Command line arguments
// Default value of the domain sizes
static struct option long_options[] = {
{"n", required_argument, 0, 'n'},
{"px", required_argument, 0, 'x'},
{"py", required_argument, 0, 'y'},
{"tfinal", required_argument, 0, 't'},
{"plot", required_argument, 0, 'p'},
{"nocomm", no_argument, 0, 'k'},
{"numthreads", required_argument, 0, 'o'},
};
// Process command line arguments
int ac;
for (ac = 1; ac < argc; ac++)
{
int c;
while ((c = getopt_long(argc, argv, "n:x:y:t:kp:o:", long_options, NULL)) != -1)
{
switch (c)
{
// Size of the computational box
case 'n':
n = atoi(optarg);
break;
// X processor geometry
case 'x':
px = atoi(optarg);
// Y processor geometry
case 'y':
py = atoi(optarg);
// Length of simulation, in simulated time units
case 't':
T = atof(optarg);
break;
// Turn off communication
case 'k':
no_comm = 1;
break;
// Plot the excitation variable
case 'p':
plot_freq = atoi(optarg);
break;
// Plot the excitation variable
case 'o':
num_threads = atoi(optarg);
break;
// Error
default:
printf("Usage: a.out [-n <domain size>] [-t <final time >]\n\t [-p <plot frequency>]\n\t[-px <x processor geometry> [-py <y proc. geometry] [-k turn off communication] [-o <Number of OpenMP threads>]\n");
exit(-1);
}
}
}
}
// Utilities
//
// Timer
// Make successive calls and take a difference to get the elapsed time.
static const double kMicro = 1.0e-6;
double getTime(){
struct timeval TV;
struct timezone TZ;
const int RC = gettimeofday(&TV, &TZ);
if (RC == -1)
{
cerr << "ERROR: Bad call to gettimeofday" << endl;
return (-1);
}
return (((double)TV.tv_sec) + kMicro * ((double)TV.tv_usec));
}
// end getTime()
// Allocate a 2D array
double **alloc2D(int m, int n){
double **E;
int nx = n, ny = m;
E = (double **)malloc(sizeof(double *) * ny + sizeof(double) * nx * ny);
assert(E);
int row;
for (row = 0; row < ny; row++)
E[row] = (double *)(E + ny) + row * nx;
return (E);
}
// Reports statistics about the computation
// These values should not vary (except to within roundoff)
// when we use different numbers of processes to solve the problem
double stats(double **E, int m, int n, double *_mx){
double mx = -1;
double l2norm = 0;
int col, row;
for (row = 1; row <= m; row++)
for (col = 1; col <= n; col++)
{
l2norm += E[row][col] * E[row][col];
if (E[row][col] > mx)
mx = E[row][col];
}
*_mx = mx;
l2norm /= (double)((m) * (n));
l2norm = sqrt(l2norm);
return l2norm;
}
double stats1D(double *E, int m, int n, double *_mx, int WIDTH){
double mx = -1;
double l2norm = 0;
int col, row;
int index = -1;
for (row = 1; row <= m; row++) {
for (col = 1; col <= n; col++){
index = row * WIDTH + col;
l2norm += E[index] * E[index];
if (E[index] > mx) {
mx = E[index];
}
}
}
*_mx = mx;
l2norm /= (double)((m) * (n));
l2norm = sqrt(l2norm);
return l2norm;
}
__global__ void simulate_version1(const double alpha, const int n, const int m, const double kk, const double dt, const double a, const double epsilon, const double M1, const double M2, const double b, double* E_1D, double* E_prev_1D, double* R_1D, int WIDTH){
int RADIUS = 1;
int row = blockIdx.y * blockDim.y + threadIdx.y + RADIUS;
int col = blockIdx.x * blockDim.x + threadIdx.x + RADIUS;
if (row < (WIDTH -1) && col < (WIDTH -1)) {
E_1D[row*WIDTH+col] = E_prev_1D[row*WIDTH+col] + alpha * (E_prev_1D[row*WIDTH+(col+1)] + E_prev_1D[row*WIDTH + (col-1)] - 4 * E_prev_1D[row*WIDTH+ col] + E_prev_1D[(row + 1)*WIDTH + col] + E_prev_1D[(row - 1) * WIDTH + col]);
}
}
void simulate(double **E, double **E_prev, double **R, const double alpha, const int n, const int m, const double kk, const double dt, const double a, const double epsilon, const double M1, const double M2, const double b, double* E_1D, double* E_prev_1D, double* R_1D, int WIDTH){
int col, row;
/*
* Copy data from boundary of the computational box
* to the padding region, set up for differencing
* on the boundary of the computational box
* Using mirror boundaries
*/
for (row = 1; row <= m; row++) {
E_prev[row][0] = E_prev[row][2];
E_prev_1D[row* WIDTH + 0] = E_prev_1D[row*WIDTH + 2];
}
for (row = 1; row <= m; row++) {
E_prev[row][n + 1] = E_prev[row][n - 1];
E_prev_1D[row*WIDTH+ (n+1)] = E_prev_1D[row*WIDTH + (n-1)];
}
for (col = 1; col <= n; col++) {
E_prev[0][col] = E_prev[2][col];
E_prev_1D[0*WIDTH+col] = E_prev_1D[2*WIDTH+ col];
}
for (col = 1; col <= n; col++) {
E_prev[m + 1][col] = E_prev[m - 1][col];
E_prev_1D[(m+1)*WIDTH+ col] = E_prev_1D[(m-1)*WIDTH+ col];
}
// ================ Kernel Setup ==============
// double *d_E_1D, *d_E_prev_1D, *d_R_1D;
// const dim3 block_size(TILE_DIM, TILE_DIM);
// const dim3 num_blocks(WIDTH / block_size.x, WIDTH / block_size.y);
// int Total_Bytes = WIDTH * WIDTH * sizeof(double);
// // Allocate space on the device
// cudaMalloc( &d_E_1D, Total_Bytes) ;
// cudaMalloc( &d_E_prev_1D,Total_Bytes) ;
// cudaMalloc(&d_R_1D, Total_Bytes);
// // Copy input data to device
// cudaMemcpy(d_E_1D, E_1D, Total_Bytes, cudaMemcpyHostToDevice) ;
// cudaMemcpy(d_E_prev_1D, E_prev_1D, Total_Bytes, cudaMemcpyHostToDevice) ;
// cudaMemcpy(d_R_1D, R_1D, Total_Bytes, cudaMemcpyHostToDevice) ;
// // simulate_version1<<<num_blocks, block_size>>>(alpha, n, m, kk, dt, a, epsilon, M1, M2, b, d_E_1D, d_E_prev_1D, d_R_1D, WIDTH);
// cudaMemcpy(E_1D ,d_E_1D, Total_Bytes, cudaMemcpyDeviceToHost);
// cudaFree(d_E_1D);
// cudaFree(d_E_prev_1D);
// cudaFree(d_R_1D);
// =================================================
// Solve for the excitation, the PDE
for (row = 1; row <= m; row++){
for (col = 1; col <= n; col++){
E[row][col] = E_prev[row][col] + alpha * (E_prev[row][col + 1] + E_prev[row][col - 1] - 4 * E_prev[row][col] + E_prev[row + 1][col] + E_prev[row - 1][col]);
E_1D[row*WIDTH+col] = E_prev_1D[row*WIDTH+col] + alpha * (E_prev_1D[row*WIDTH+(col+1)] + E_prev_1D[row*WIDTH + (col-1)] - 4 * E_prev_1D[row*WIDTH+ col] + E_prev_1D[(row + 1)*WIDTH + col] + E_prev_1D[(row - 1) * WIDTH + col]);
}
}
/*
* Solve the ODE, advancing excitation and recovery to the
* next timtestep
*/
int index = -1;
for (row = 1; row <= m; row++){
for (col = 1; col <= n; col++) {
E[row][col] = E[row][col] - dt * (kk * E[row][col] * (E[row][col] - a) * (E[row][col] - 1) + E[row][col] * R[row][col]);
index = row * WIDTH + col;
E_1D[index] = E_1D[index] - dt * (kk * E_1D[index] * (E_1D[index] - a) * (E_1D[index] - 1) + E_1D[index] * R_1D[index]);
}
}
for (row = 1; row <= m; row++){
for (col = 1; col <= n; col++) {
R[row][col] = R[row][col] + dt * (epsilon + M1 * R[row][col] / (E[row][col] + M2)) * (-R[row][col] - kk * E[row][col] * (E[row][col] - b - 1));
index = row * WIDTH + col;
R_1D[index] = R_1D[index] + dt * (epsilon + M1 * R_1D[index] / (E_1D[index] + M2)) * (-R_1D[index] - kk * E_1D[index] * (E_1D[index] - b - 1));
}
}
}
// Main program
int main(int argc, char **argv){
/*
* Solution arrays
* E is the "Excitation" variable, a voltage
* R is the "Recovery" variable
* E_prev is the Excitation variable for the previous timestep,
* and is used in time integration
*/
cout<< "\n Hello I am waris"<<endl;
double **E, **R, **E_prev;
double * E_1D, *R_1D, *E_prev_1D;
// Various constants - these definitions shouldn't change
const double a = 0.1, b = 0.1, kk = 8.0, M1 = 0.07, M2 = 0.3, epsilon = 0.01, d = 5e-5;
double T = 1000.0;
int m = 200, n = 200;
int plot_freq = 0;
int px = 1, py = 1;
int no_comm = 0;
int num_threads = 1;
int WIDTH;
//int size;
cmdLine(argc, argv, T, n, px, py, plot_freq, no_comm, num_threads);
m = n;
// Allocate contiguous memory for solution arrays
// The computational box is defined on [1:m+1,1:n+1]
// We pad the arrays in order to facilitate differencing on the
// boundaries of the computation box
int Total_Bytes = (m+2) * (n+2) *sizeof(double);
WIDTH = m+2;
E = alloc2D(m + 2, n + 2);
E_prev = alloc2D(m + 2, n + 2);
R = alloc2D(m + 2, n + 2);
E_1D = (double *) malloc (Total_Bytes);
E_prev_1D = (double *) malloc (Total_Bytes);
R_1D = (double *) malloc (Total_Bytes);
int col, row;
// Initialization
for (row = 1; row <= m; row++) {
for (col = 1; col <= n; col++) {
E_prev[row][col] = 0;
R[row][col] = 0;
E_prev_1D[row*WIDTH + col] = 0;
R_1D[row*WIDTH + col] = 0;
}
}
for (row = 1; row <= m; row++) {
for (col = n / 2 + 1; col <= n; col++) {
E_prev[row][col] = 1.0;
E_prev_1D[row*WIDTH + col] = 1.0;
}
}
for (row = m / 2 + 1; row <= m; row++) {
for (col = 1; col <= n; col++) {
R[row][col] = 1.0;
R_1D[row*WIDTH + col] = 1.0;
}
}
//cout<< "check 1"<<endl;
double dx = 1.0 / n;
// For time integration, these values shouldn't change
double rp = kk * (b + 1) * (b + 1) / 4;
double dte = (dx * dx) / (d * 4 + ((dx * dx)) * (rp + kk));
double dtr = 1 / (epsilon + ((M1 / M2) * rp));
double dt = (dte < dtr) ? 0.95 * dte : 0.95 * dtr;
double alpha = d * dt / (dx * dx);
cout << "Grid Size : " << n << endl;
cout << "Duration of Sim : " << T << endl;
cout << "Time step dt : " << dt << endl;
cout << "Process geometry: " << px << " x " << py << endl;
if (no_comm) {
cout << "Communication : DISABLED" << endl;
}
cout << endl;
// Start the timer
double t0 = getTime();
// Simulated time is different from the integer timestep number
// Simulated time
double t = 0.0;
// Integer timestep number
int niter = 0;
while (t < T){
t += dt;
niter++;
simulate(E, E_prev, R, alpha, n, m, kk, dt, a, epsilon, M1, M2, b, E_1D, E_prev_1D, R_1D, WIDTH);
//swap current E with previous E
double **tmp = E;
E = E_prev;
E_prev = tmp;
double *tmp2 = E_1D;
E_1D = E_prev_1D;
E_prev_1D = tmp2;
// if (plot_freq){
// int k = (int)(t / plot_freq);
// if ((t - k * plot_freq) < dt){
// splot(E, t, niter, m + 2, n + 2);
// }
// }
} //end of while loop
double time_elapsed = getTime() - t0;
double Gflops = (double)(niter * (1E-9 * n * n) * 28.0) / time_elapsed;
double BW = (double)(niter * 1E-9 * (n * n * sizeof(double) * 4.0)) / time_elapsed;
cout << "Number of Iterations : " << niter << endl;
cout << "Elapsed Time (sec) : " << time_elapsed << endl;
cout << "Sustained Gflops Rate : " << Gflops << endl;
cout << "Sustained Bandwidth (GB/sec): " << BW << endl << endl;
double mx;
double l2norm = stats(E_prev, m, n, &mx);
cout << "Max: " << mx << " L2norm: " << l2norm << endl;
l2norm = stats1D(E_prev_1D, m, n, &mx, WIDTH);
cout << "1D Max : " << mx << " 1D L2norm: " << l2norm << endl;
// if (plot_freq){
// cout << "\n\nEnter any input to close the program and the plot..." << endl;
// getchar();
// }
free(E);
free(E_prev);
free(R);
free(E_1D);
free(E_prev_1D);
free(R_1D);
return 0;
}
/* **********************************************************
* Author : Urvashi R.V. [04/06/2004]
* Modified by Didem Unat [03/23/18]
*************************************************************/
//#include <stdio.h>
/* Function to plot the 2D array
* 'gnuplot' is instantiated via a pipe and
* the values to be plotted are passed through, along
* with gnuplot commands */
// FILE *gnu = NULL;
// void splot(double **U, double T, int niter, int m, int n){
// int col, row;
// if (gnu == NULL)
// gnu = popen("gnuplot", "w");
// double mx = -1, mn = 32768;
// for (row = 0; row < m; row++)
// for (col = 0; col < n; col++)
// {
// if (U[row][col] > mx)
// mx = U[row][col];
// if (U[row][col] < mn)
// mn = U[row][col];
// }
// fprintf(gnu, "set title \"T = %f [niter = %d]\"\n", T, niter);
// fprintf(gnu, "set size square\n");
// fprintf(gnu, "set key off\n");
// fprintf(gnu, "set pm3d map\n");
// // Various color schemes
// fprintf(gnu, "set palette defined (-3 \"blue\", 0 \"white\", 1 \"red\")\n");
// // fprintf(gnu,"set palette rgbformulae 22, 13, 31\n");
// // fprintf(gnu,"set palette rgbformulae 30, 31, 32\n");
// fprintf(gnu, "splot [0:%d] [0:%d][%f:%f] \"-\"\n", m - 1, n - 1, mn, mx);
// for (row = 0; row < m; row++)
// {
// for (col = 0; col < n; col++)
// {
// fprintf(gnu, "%d %d %f\n", col, row, U[col][row]);
// }
// fprintf(gnu, "\n");
// }
// fprintf(gnu, "e\n");
// fflush(gnu);
// return;
// } | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17simulate_version1diidddddddPdS_S_i
.globl _Z17simulate_version1diidddddddPdS_S_i
.p2align 8
.type _Z17simulate_version1diidddddddPdS_S_i,@function
_Z17simulate_version1diidddddddPdS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x74
s_load_b32 s2, s[0:1], 0x60
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[2:3], null, s14, s3, v[4:5]
s_add_i32 s3, s2, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, 1, v0
v_add_nc_u32_e32 v1, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v4, v3, v1
v_cmp_gt_i32_e32 vcc_lo, s3, v4
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_2
v_mul_lo_u32 v6, v3, s2
s_load_b128 s[4:7], s[0:1], 0x48
v_add_nc_u32_e32 v12, 2, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v6, v2
v_add_nc_u32_e32 v6, v6, v1
v_add_nc_u32_e32 v4, 2, v2
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v7, 31, v6
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 3, v[2:3]
v_lshlrev_b64 v[6:7], 3, v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 3, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v6
s_clause 0x1
global_load_b64 v[4:5], v[4:5], off
global_load_b64 v[2:3], v[2:3], off
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v7, vcc_lo
global_load_b64 v[8:9], v[8:9], off
s_waitcnt vmcnt(1)
v_mad_u64_u32 v[10:11], null, v12, s2, v[1:2]
v_mad_u64_u32 v[12:13], null, v0, s2, v[1:2]
v_add_f64 v[2:3], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v11, 31, v10
v_ashrrev_i32_e32 v13, 31, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[10:11], 3, v[10:11]
v_lshlrev_b64 v[0:1], 3, v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v10, vcc_lo, s6, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_clause 0x1
global_load_b64 v[10:11], v[10:11], off
global_load_b64 v[0:1], v[0:1], off
s_waitcnt vmcnt(2)
v_fma_f64 v[2:3], v[8:9], -4.0, v[2:3]
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[10:11], v[2:3]
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[0:1], v[2:3]
v_add_co_u32 v2, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_fma_f64 v[0:1], v[0:1], s[0:1], v[8:9]
global_store_b64 v[2:3], v[0:1], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17simulate_version1diidddddddPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 360
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17simulate_version1diidddddddPdS_S_i, .Lfunc_end0-_Z17simulate_version1diidddddddPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 8
.value_kind: by_value
- .offset: 56
.size: 8
.value_kind: by_value
- .offset: 64
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 80
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 88
.size: 8
.value_kind: global_buffer
- .offset: 96
.size: 4
.value_kind: by_value
- .offset: 104
.size: 4
.value_kind: hidden_block_count_x
- .offset: 108
.size: 4
.value_kind: hidden_block_count_y
- .offset: 112
.size: 4
.value_kind: hidden_block_count_z
- .offset: 116
.size: 2
.value_kind: hidden_group_size_x
- .offset: 118
.size: 2
.value_kind: hidden_group_size_y
- .offset: 120
.size: 2
.value_kind: hidden_group_size_z
- .offset: 122
.size: 2
.value_kind: hidden_remainder_x
- .offset: 124
.size: 2
.value_kind: hidden_remainder_y
- .offset: 126
.size: 2
.value_kind: hidden_remainder_z
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 152
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 160
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 168
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 360
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17simulate_version1diidddddddPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17simulate_version1diidddddddPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17simulate_version1diidddddddPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R14, SR_CTAID.X ; /* 0x00000000000e7919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x1c0] ; /* 0x0000700000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0050*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0060*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0070*/ IMAD R14, R14, c[0x0][0x0], R5 ; /* 0x000000000e0e7a24 */
/* 0x001fca00078e0205 */
/*0080*/ IADD3 R0, R14, 0x1, RZ ; /* 0x000000010e007810 */
/* 0x000fe20007ffe0ff */
/*0090*/ IMAD R2, R2, c[0x0][0x4], R3 ; /* 0x0000010002027a24 */
/* 0x002fc600078e0203 */
/*00a0*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fe4000bf06270 */
/*00b0*/ IADD3 R3, R2, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x000fc80007ffe0ff */
/*00c0*/ ISETP.GE.OR P0, PT, R3, UR4, P0 ; /* 0x0000000403007c0c */
/* 0x000fda0008706670 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ HFMA2.MMA R0, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff007435 */
/* 0x000fe200000001ff */
/*00f0*/ IMAD R3, R3, c[0x0][0x1c0], R14 ; /* 0x0000700003037a24 */
/* 0x000fe200078e020e */
/*0100*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0110*/ IMAD.WIDE R6, R3.reuse, R0, c[0x0][0x1b0] ; /* 0x00006c0003067625 */
/* 0x040fe200078e0200 */
/*0120*/ IADD3 R13, R3, c[0x0][0x1c0], RZ ; /* 0x00007000030d7a10 */
/* 0x000fc80007ffe0ff */
/*0130*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ea8000c1e1b00 */
/*0140*/ LDG.E.64 R10, [R6.64+0x10] ; /* 0x00001004060a7981 */
/* 0x000ea2000c1e1b00 */
/*0150*/ IMAD.WIDE R12, R13, R0, c[0x0][0x1b0] ; /* 0x00006c000d0c7625 */
/* 0x000fc600078e0200 */
/*0160*/ LDG.E.64 R4, [R6.64+0x8] ; /* 0x0000080406047981 */
/* 0x000ee2000c1e1b00 */
/*0170*/ IMAD R15, R2, c[0x0][0x1c0], R14 ; /* 0x00007000020f7a24 */
/* 0x000fc600078e020e */
/*0180*/ LDG.E.64 R12, [R12.64+0x8] ; /* 0x000008040c0c7981 */
/* 0x000f22000c1e1b00 */
/*0190*/ IMAD.WIDE R14, R15, R0, c[0x0][0x1b0] ; /* 0x00006c000f0e7625 */
/* 0x000fcc00078e0200 */
/*01a0*/ LDG.E.64 R14, [R14.64+0x8] ; /* 0x000008040e0e7981 */
/* 0x000f62000c1e1b00 */
/*01b0*/ IMAD.WIDE R2, R3, R0, c[0x0][0x1a8] ; /* 0x00006a0003027625 */
/* 0x000fe200078e0200 */
/*01c0*/ DADD R8, R8, R10 ; /* 0x0000000008087229 */
/* 0x004ecc000000000a */
/*01d0*/ DFMA R8, R4, -4, R8 ; /* 0xc01000000408782b */
/* 0x008f0c0000000008 */
/*01e0*/ DADD R8, R8, R12 ; /* 0x0000000008087229 */
/* 0x010f4c000000000c */
/*01f0*/ DADD R8, R8, R14 ; /* 0x0000000008087229 */
/* 0x020e0c000000000e */
/*0200*/ DFMA R8, R8, c[0x0][0x160], R4 ; /* 0x0000580008087a2b */
/* 0x001e0e0000000004 */
/*0210*/ STG.E.64 [R2.64+0x8], R8 ; /* 0x0000080802007986 */
/* 0x001fe2000c101b04 */
/*0220*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0230*/ BRA 0x230; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17simulate_version1diidddddddPdS_S_i
.globl _Z17simulate_version1diidddddddPdS_S_i
.p2align 8
.type _Z17simulate_version1diidddddddPdS_S_i,@function
_Z17simulate_version1diidddddddPdS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x74
s_load_b32 s2, s[0:1], 0x60
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[2:3], null, s14, s3, v[4:5]
s_add_i32 s3, s2, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, 1, v0
v_add_nc_u32_e32 v1, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v4, v3, v1
v_cmp_gt_i32_e32 vcc_lo, s3, v4
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_2
v_mul_lo_u32 v6, v3, s2
s_load_b128 s[4:7], s[0:1], 0x48
v_add_nc_u32_e32 v12, 2, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v6, v2
v_add_nc_u32_e32 v6, v6, v1
v_add_nc_u32_e32 v4, 2, v2
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v7, 31, v6
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 3, v[2:3]
v_lshlrev_b64 v[6:7], 3, v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 3, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v6
s_clause 0x1
global_load_b64 v[4:5], v[4:5], off
global_load_b64 v[2:3], v[2:3], off
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v7, vcc_lo
global_load_b64 v[8:9], v[8:9], off
s_waitcnt vmcnt(1)
v_mad_u64_u32 v[10:11], null, v12, s2, v[1:2]
v_mad_u64_u32 v[12:13], null, v0, s2, v[1:2]
v_add_f64 v[2:3], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v11, 31, v10
v_ashrrev_i32_e32 v13, 31, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[10:11], 3, v[10:11]
v_lshlrev_b64 v[0:1], 3, v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v10, vcc_lo, s6, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_clause 0x1
global_load_b64 v[10:11], v[10:11], off
global_load_b64 v[0:1], v[0:1], off
s_waitcnt vmcnt(2)
v_fma_f64 v[2:3], v[8:9], -4.0, v[2:3]
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[10:11], v[2:3]
s_waitcnt vmcnt(0)
v_add_f64 v[0:1], v[0:1], v[2:3]
v_add_co_u32 v2, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_fma_f64 v[0:1], v[0:1], s[0:1], v[8:9]
global_store_b64 v[2:3], v[0:1], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17simulate_version1diidddddddPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 360
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17simulate_version1diidddddddPdS_S_i, .Lfunc_end0-_Z17simulate_version1diidddddddPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 8
.value_kind: by_value
- .offset: 56
.size: 8
.value_kind: by_value
- .offset: 64
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 72
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 80
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 88
.size: 8
.value_kind: global_buffer
- .offset: 96
.size: 4
.value_kind: by_value
- .offset: 104
.size: 4
.value_kind: hidden_block_count_x
- .offset: 108
.size: 4
.value_kind: hidden_block_count_y
- .offset: 112
.size: 4
.value_kind: hidden_block_count_z
- .offset: 116
.size: 2
.value_kind: hidden_group_size_x
- .offset: 118
.size: 2
.value_kind: hidden_group_size_y
- .offset: 120
.size: 2
.value_kind: hidden_group_size_z
- .offset: 122
.size: 2
.value_kind: hidden_remainder_x
- .offset: 124
.size: 2
.value_kind: hidden_remainder_y
- .offset: 126
.size: 2
.value_kind: hidden_remainder_z
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 152
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 160
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 168
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 360
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17simulate_version1diidddddddPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17simulate_version1diidddddddPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
__global__ void compute_probs(double* alphas, double* rands, double* probs, int n, int K, int M) {
// assign overall id/index of the thread = id of row
int i = blockIdx.x * blockDim.x + threadIdx.x;
int threads_per_block = blockDim.x;
// set up shared memory: half for probs and half for w
extern __shared__ double shared[];
double* probs_shared = shared;
double* w = &shared[K*threads_per_block]; // shared mem is one big block, so need to index into latter portion of it to use for w
if(i < n) {
double maxval;
int m, k;
int maxind;
double M_d = (double) M;
// initialize shared memory probs
for(k = 0; k < K; ++k) {
probs_shared[k*threads_per_block + threadIdx.x] = 0.0;
}
// core computation
for(m = 0; m < M; ++m){ // loop over Monte Carlo iterations
for(k = 0; k < K; ++k){ // generate W ~ N(alpha, 1)
w[k*threads_per_block + threadIdx.x] = alphas[k*n + i] + rands[k*M + m];
}
maxind = K-1;
maxval = w[(K-1)*threads_per_block + threadIdx.x];
for(k = 0; k < (K-1); ++k){
if(w[k*threads_per_block + threadIdx.x] > maxval){
maxind = k;
maxval = w[k*threads_per_block + threadIdx.x];
}
}
probs_shared[maxind*threads_per_block + threadIdx.x] += 1.0;
}
for(k = 0; k < K; ++k) {
probs_shared[k*threads_per_block + threadIdx.x] /= M_d;
}
// copy to device memory so can be returned to CPU
for(k = 0; k < K; ++k) {
probs[k*n + i] = probs_shared[k*threads_per_block + threadIdx.x];
}
}
} | .file "tmpxft_000c0aa7_00000000-6_compute_probs_unitStrides_sharedMem.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z13compute_probsPdS_S_iiiPdS_S_iii
.type _Z40__device_stub__Z13compute_probsPdS_S_iiiPdS_S_iii, @function
_Z40__device_stub__Z13compute_probsPdS_S_iiiPdS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq compute_probs(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z13compute_probsPdS_S_iiiPdS_S_iii, .-_Z40__device_stub__Z13compute_probsPdS_S_iiiPdS_S_iii
.globl compute_probs
.type compute_probs, @function
compute_probs:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z13compute_probsPdS_S_iiiPdS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size compute_probs, .-compute_probs
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "compute_probs"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq compute_probs(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
__global__ void compute_probs(double* alphas, double* rands, double* probs, int n, int K, int M) {
// assign overall id/index of the thread = id of row
int i = blockIdx.x * blockDim.x + threadIdx.x;
int threads_per_block = blockDim.x;
// set up shared memory: half for probs and half for w
extern __shared__ double shared[];
double* probs_shared = shared;
double* w = &shared[K*threads_per_block]; // shared mem is one big block, so need to index into latter portion of it to use for w
if(i < n) {
double maxval;
int m, k;
int maxind;
double M_d = (double) M;
// initialize shared memory probs
for(k = 0; k < K; ++k) {
probs_shared[k*threads_per_block + threadIdx.x] = 0.0;
}
// core computation
for(m = 0; m < M; ++m){ // loop over Monte Carlo iterations
for(k = 0; k < K; ++k){ // generate W ~ N(alpha, 1)
w[k*threads_per_block + threadIdx.x] = alphas[k*n + i] + rands[k*M + m];
}
maxind = K-1;
maxval = w[(K-1)*threads_per_block + threadIdx.x];
for(k = 0; k < (K-1); ++k){
if(w[k*threads_per_block + threadIdx.x] > maxval){
maxind = k;
maxval = w[k*threads_per_block + threadIdx.x];
}
}
probs_shared[maxind*threads_per_block + threadIdx.x] += 1.0;
}
for(k = 0; k < K; ++k) {
probs_shared[k*threads_per_block + threadIdx.x] /= M_d;
}
// copy to device memory so can be returned to CPU
for(k = 0; k < K; ++k) {
probs[k*n + i] = probs_shared[k*threads_per_block + threadIdx.x];
}
}
} | #include <hip/hip_runtime.h>
extern "C"
__global__ void compute_probs(double* alphas, double* rands, double* probs, int n, int K, int M) {
// assign overall id/index of the thread = id of row
int i = blockIdx.x * blockDim.x + threadIdx.x;
int threads_per_block = blockDim.x;
// set up shared memory: half for probs and half for w
extern __shared__ double shared[];
double* probs_shared = shared;
double* w = &shared[K*threads_per_block]; // shared mem is one big block, so need to index into latter portion of it to use for w
if(i < n) {
double maxval;
int m, k;
int maxind;
double M_d = (double) M;
// initialize shared memory probs
for(k = 0; k < K; ++k) {
probs_shared[k*threads_per_block + threadIdx.x] = 0.0;
}
// core computation
for(m = 0; m < M; ++m){ // loop over Monte Carlo iterations
for(k = 0; k < K; ++k){ // generate W ~ N(alpha, 1)
w[k*threads_per_block + threadIdx.x] = alphas[k*n + i] + rands[k*M + m];
}
maxind = K-1;
maxval = w[(K-1)*threads_per_block + threadIdx.x];
for(k = 0; k < (K-1); ++k){
if(w[k*threads_per_block + threadIdx.x] > maxval){
maxind = k;
maxval = w[k*threads_per_block + threadIdx.x];
}
}
probs_shared[maxind*threads_per_block + threadIdx.x] += 1.0;
}
for(k = 0; k < K; ++k) {
probs_shared[k*threads_per_block + threadIdx.x] /= M_d;
}
// copy to device memory so can be returned to CPU
for(k = 0; k < K; ++k) {
probs[k*n + i] = probs_shared[k*threads_per_block + threadIdx.x];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__ void compute_probs(double* alphas, double* rands, double* probs, int n, int K, int M) {
// assign overall id/index of the thread = id of row
int i = blockIdx.x * blockDim.x + threadIdx.x;
int threads_per_block = blockDim.x;
// set up shared memory: half for probs and half for w
extern __shared__ double shared[];
double* probs_shared = shared;
double* w = &shared[K*threads_per_block]; // shared mem is one big block, so need to index into latter portion of it to use for w
if(i < n) {
double maxval;
int m, k;
int maxind;
double M_d = (double) M;
// initialize shared memory probs
for(k = 0; k < K; ++k) {
probs_shared[k*threads_per_block + threadIdx.x] = 0.0;
}
// core computation
for(m = 0; m < M; ++m){ // loop over Monte Carlo iterations
for(k = 0; k < K; ++k){ // generate W ~ N(alpha, 1)
w[k*threads_per_block + threadIdx.x] = alphas[k*n + i] + rands[k*M + m];
}
maxind = K-1;
maxval = w[(K-1)*threads_per_block + threadIdx.x];
for(k = 0; k < (K-1); ++k){
if(w[k*threads_per_block + threadIdx.x] > maxval){
maxind = k;
maxval = w[k*threads_per_block + threadIdx.x];
}
}
probs_shared[maxind*threads_per_block + threadIdx.x] += 1.0;
}
for(k = 0; k < K; ++k) {
probs_shared[k*threads_per_block + threadIdx.x] /= M_d;
}
// copy to device memory so can be returned to CPU
for(k = 0; k < K; ++k) {
probs[k*n + i] = probs_shared[k*threads_per_block + threadIdx.x];
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected compute_probs
.globl compute_probs
.p2align 8
.type compute_probs,@function
compute_probs:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s8, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s2, 0xffff
s_mov_b32 s2, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_18
s_load_b32 s9, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s9, 1
s_cbranch_scc1 .LBB0_4
v_lshl_add_u32 v4, v0, 3, 0
v_mov_b32_e32 v2, 0
s_lshl_b32 s2, s10, 3
s_mov_b32 s3, s9
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v3, v2
s_add_i32 s3, s3, -1
s_cmp_eq_u32 s3, 0
ds_store_b64 v4, v[2:3]
v_add_nc_u32_e32 v4, s2, v4
s_cbranch_scc0 .LBB0_3
.LBB0_4:
s_load_b32 s11, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s11, 1
s_cbranch_scc1 .LBB0_12
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 3, v0
s_mul_i32 s2, s10, s9
s_mov_b32 s3, 0
s_lshl_b32 s2, s2, 3
s_cmp_gt_i32 s9, 0
v_add3_u32 v4, 0, s2, v2
s_cselect_b32 s12, -1, 0
s_add_i32 s13, s9, -1
v_add_nc_u32_e32 v5, 0, v2
s_mul_i32 s2, s13, s10
s_cmp_gt_i32 s9, 1
v_lshl_add_u32 v6, s2, 3, v4
s_cselect_b32 s14, -1, 0
s_lshl_b32 s15, s10, 3
s_mov_b32 s16, 0
s_branch .LBB0_7
.LBB0_6:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v2, v7, s10
s_add_i32 s16, s16, 1
s_cmp_eq_u32 s16, s11
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v7, v2, 3, v5
ds_load_b64 v[2:3], v7
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[2:3], 1.0
ds_store_b64 v7, v[2:3]
s_cbranch_scc1 .LBB0_12
.LBB0_7:
v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v7, v4
s_and_not1_b32 vcc_lo, exec_lo, s12
s_mov_b32 s2, s16
s_mov_b32 s17, s9
s_cbranch_vccnz .LBB0_9
.p2align 6
.LBB0_8:
v_ashrrev_i32_e32 v3, 31, v2
s_lshl_b64 s[18:19], s[2:3], 3
s_waitcnt lgkmcnt(0)
s_add_u32 s18, s6, s18
s_addc_u32 s19, s7, s19
v_lshlrev_b64 v[8:9], 3, v[2:3]
s_load_b64 s[18:19], s[18:19], 0x0
v_add_nc_u32_e32 v2, s8, v2
s_add_i32 s17, s17, -1
s_add_i32 s2, s2, s11
s_cmp_lg_u32 s17, 0
v_add_co_u32 v8, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
global_load_b64 v[8:9], v[8:9], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f64 v[8:9], v[8:9], s[18:19]
ds_store_b64 v7, v[8:9]
v_add_nc_u32_e32 v7, s15, v7
s_cbranch_scc1 .LBB0_8
.LBB0_9:
v_mov_b32_e32 v7, s13
s_and_not1_b32 vcc_lo, exec_lo, s14
s_cbranch_vccnz .LBB0_6
ds_load_b64 v[2:3], v6
v_dual_mov_b32 v7, s13 :: v_dual_mov_b32 v8, v4
s_mov_b32 s2, 0
.LBB0_11:
ds_load_b64 v[9:10], v8
s_waitcnt lgkmcnt(0)
v_cmp_gt_f64_e32 vcc_lo, v[9:10], v[2:3]
v_dual_cndmask_b32 v3, v3, v10 :: v_dual_add_nc_u32 v8, s15, v8
v_cndmask_b32_e64 v7, v7, s2, vcc_lo
v_cndmask_b32_e32 v2, v2, v9, vcc_lo
s_add_i32 s2, s2, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s13, s2
s_cbranch_scc1 .LBB0_11
s_branch .LBB0_6
.LBB0_12:
s_cmp_lt_i32 s9, 1
s_cbranch_scc1 .LBB0_15
v_cvt_f64_i32_e32 v[2:3], s11
v_lshl_add_u32 v4, v0, 3, 0
s_lshl_b32 s2, s10, 3
s_mov_b32 s3, s9
.p2align 6
.LBB0_14:
ds_load_b64 v[5:6], v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s3, 0
s_waitcnt lgkmcnt(0)
v_div_scale_f64 v[7:8], null, v[2:3], v[2:3], v[5:6]
v_div_scale_f64 v[13:14], vcc_lo, v[5:6], v[2:3], v[5:6]
v_rcp_f64_e32 v[9:10], v[7:8]
s_waitcnt_depctr 0xfff
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
v_mul_f64 v[11:12], v[13:14], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], -v[7:8], v[11:12], v[13:14]
v_div_fmas_f64 v[7:8], v[7:8], v[9:10], v[11:12]
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f64 v[5:6], v[7:8], v[2:3], v[5:6]
ds_store_b64 v4, v[5:6]
v_add_nc_u32_e32 v4, s2, v4
s_cbranch_scc0 .LBB0_14
.LBB0_15:
s_cmp_lt_i32 s9, 1
s_cbranch_scc1 .LBB0_18
s_load_b64 s[0:1], s[0:1], 0x10
v_lshl_add_u32 v0, v0, 3, 0
s_lshl_b32 s2, s10, 3
.LBB0_17:
ds_load_b64 v[3:4], v0
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v0, s2, v0
s_add_i32 s9, s9, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_lg_u32 s9, 0
v_lshlrev_b64 v[5:6], 3, v[1:2]
v_add_nc_u32_e32 v1, s8, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
global_store_b64 v[5:6], v[3:4], off
s_cbranch_scc1 .LBB0_17
.LBB0_18:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel compute_probs
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size compute_probs, .Lfunc_end0-compute_probs
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
- .offset: 160
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: compute_probs
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: compute_probs.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__ void compute_probs(double* alphas, double* rands, double* probs, int n, int K, int M) {
// assign overall id/index of the thread = id of row
int i = blockIdx.x * blockDim.x + threadIdx.x;
int threads_per_block = blockDim.x;
// set up shared memory: half for probs and half for w
extern __shared__ double shared[];
double* probs_shared = shared;
double* w = &shared[K*threads_per_block]; // shared mem is one big block, so need to index into latter portion of it to use for w
if(i < n) {
double maxval;
int m, k;
int maxind;
double M_d = (double) M;
// initialize shared memory probs
for(k = 0; k < K; ++k) {
probs_shared[k*threads_per_block + threadIdx.x] = 0.0;
}
// core computation
for(m = 0; m < M; ++m){ // loop over Monte Carlo iterations
for(k = 0; k < K; ++k){ // generate W ~ N(alpha, 1)
w[k*threads_per_block + threadIdx.x] = alphas[k*n + i] + rands[k*M + m];
}
maxind = K-1;
maxval = w[(K-1)*threads_per_block + threadIdx.x];
for(k = 0; k < (K-1); ++k){
if(w[k*threads_per_block + threadIdx.x] > maxval){
maxind = k;
maxval = w[k*threads_per_block + threadIdx.x];
}
}
probs_shared[maxind*threads_per_block + threadIdx.x] += 1.0;
}
for(k = 0; k < K; ++k) {
probs_shared[k*threads_per_block + threadIdx.x] /= M_d;
}
// copy to device memory so can be returned to CPU
for(k = 0; k < K; ++k) {
probs[k*n + i] = probs_shared[k*threads_per_block + threadIdx.x];
}
}
} | .text
.file "compute_probs_unitStrides_sharedMem.hip"
.globl __device_stub__compute_probs # -- Begin function __device_stub__compute_probs
.p2align 4, 0x90
.type __device_stub__compute_probs,@function
__device_stub__compute_probs: # @__device_stub__compute_probs
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $compute_probs, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size __device_stub__compute_probs, .Lfunc_end0-__device_stub__compute_probs
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $compute_probs, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type compute_probs,@object # @compute_probs
.section .rodata,"a",@progbits
.globl compute_probs
.p2align 3, 0x0
compute_probs:
.quad __device_stub__compute_probs
.size compute_probs, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "compute_probs"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__compute_probs
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym compute_probs
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c0aa7_00000000-6_compute_probs_unitStrides_sharedMem.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z13compute_probsPdS_S_iiiPdS_S_iii
.type _Z40__device_stub__Z13compute_probsPdS_S_iiiPdS_S_iii, @function
_Z40__device_stub__Z13compute_probsPdS_S_iiiPdS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq compute_probs(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z13compute_probsPdS_S_iiiPdS_S_iii, .-_Z40__device_stub__Z13compute_probsPdS_S_iiiPdS_S_iii
.globl compute_probs
.type compute_probs, @function
compute_probs:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z13compute_probsPdS_S_iiiPdS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size compute_probs, .-compute_probs
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "compute_probs"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq compute_probs(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "compute_probs_unitStrides_sharedMem.hip"
.globl __device_stub__compute_probs # -- Begin function __device_stub__compute_probs
.p2align 4, 0x90
.type __device_stub__compute_probs,@function
__device_stub__compute_probs: # @__device_stub__compute_probs
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $compute_probs, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size __device_stub__compute_probs, .Lfunc_end0-__device_stub__compute_probs
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $compute_probs, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type compute_probs,@object # @compute_probs
.section .rodata,"a",@progbits
.globl compute_probs
.p2align 3, 0x0
compute_probs:
.quad __device_stub__compute_probs
.size compute_probs, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "compute_probs"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__compute_probs
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym compute_probs
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void CalcMass(double *Mass_d, double *GlobalMass_d, double *Rho_d, double A, double *Altitudeh_d, double *lonlat_d, double *areasT, int num, bool DeepModel) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
int nv = gridDim.y;
int lev = blockIdx.y;
if (id < num) {
//calculate control volume
double zup, zlow, Vol;
zup = Altitudeh_d[lev + 1] + A;
zlow = Altitudeh_d[lev] + A;
if (DeepModel) {
Vol = areasT[id] / pow(A, 2) * (pow(zup, 3) - pow(zlow, 3)) / 3;
}
else {
Vol = areasT[id] * (zup - zlow);
}
//mass in control volume = density*volume
Mass_d[id * nv + lev] = Rho_d[id * nv + lev] * Vol;
}
} | .file "tmpxft_000cf8f3_00000000-6_CalcMass.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z8CalcMassPdS_S_dS_S_S_ibPdS_S_dS_S_S_ib
.type _Z40__device_stub__Z8CalcMassPdS_S_dS_S_S_ibPdS_S_dS_S_S_ib, @function
_Z40__device_stub__Z8CalcMassPdS_S_dS_S_S_ibPdS_S_dS_S_S_ib:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movsd %xmm0, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movl 232(%rsp), %eax
movb %al, 4(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 224(%rsp), %rax
movq %rax, 184(%rsp)
leaq 4(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z8CalcMassPdS_S_dS_S_S_ib(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z8CalcMassPdS_S_dS_S_S_ibPdS_S_dS_S_S_ib, .-_Z40__device_stub__Z8CalcMassPdS_S_dS_S_S_ibPdS_S_dS_S_S_ib
.globl _Z8CalcMassPdS_S_dS_S_S_ib
.type _Z8CalcMassPdS_S_dS_S_S_ib, @function
_Z8CalcMassPdS_S_dS_S_S_ib:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z40__device_stub__Z8CalcMassPdS_S_dS_S_S_ibPdS_S_dS_S_S_ib
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8CalcMassPdS_S_dS_S_S_ib, .-_Z8CalcMassPdS_S_dS_S_S_ib
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8CalcMassPdS_S_dS_S_S_ib"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8CalcMassPdS_S_dS_S_S_ib(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void CalcMass(double *Mass_d, double *GlobalMass_d, double *Rho_d, double A, double *Altitudeh_d, double *lonlat_d, double *areasT, int num, bool DeepModel) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
int nv = gridDim.y;
int lev = blockIdx.y;
if (id < num) {
//calculate control volume
double zup, zlow, Vol;
zup = Altitudeh_d[lev + 1] + A;
zlow = Altitudeh_d[lev] + A;
if (DeepModel) {
Vol = areasT[id] / pow(A, 2) * (pow(zup, 3) - pow(zlow, 3)) / 3;
}
else {
Vol = areasT[id] * (zup - zlow);
}
//mass in control volume = density*volume
Mass_d[id * nv + lev] = Rho_d[id * nv + lev] * Vol;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void CalcMass(double *Mass_d, double *GlobalMass_d, double *Rho_d, double A, double *Altitudeh_d, double *lonlat_d, double *areasT, int num, bool DeepModel) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
int nv = gridDim.y;
int lev = blockIdx.y;
if (id < num) {
//calculate control volume
double zup, zlow, Vol;
zup = Altitudeh_d[lev + 1] + A;
zlow = Altitudeh_d[lev] + A;
if (DeepModel) {
Vol = areasT[id] / pow(A, 2) * (pow(zup, 3) - pow(zlow, 3)) / 3;
}
else {
Vol = areasT[id] * (zup - zlow);
}
//mass in control volume = density*volume
Mass_d[id * nv + lev] = Rho_d[id * nv + lev] * Vol;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void CalcMass(double *Mass_d, double *GlobalMass_d, double *Rho_d, double A, double *Altitudeh_d, double *lonlat_d, double *areasT, int num, bool DeepModel) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
int nv = gridDim.y;
int lev = blockIdx.y;
if (id < num) {
//calculate control volume
double zup, zlow, Vol;
zup = Altitudeh_d[lev + 1] + A;
zlow = Altitudeh_d[lev] + A;
if (DeepModel) {
Vol = areasT[id] / pow(A, 2) * (pow(zup, 3) - pow(zlow, 3)) / 3;
}
else {
Vol = areasT[id] * (zup - zlow);
}
//mass in control volume = density*volume
Mass_d[id * nv + lev] = Rho_d[id * nv + lev] * Vol;
}
} | .text
.file "CalcMass.hip"
.globl _Z23__device_stub__CalcMassPdS_S_dS_S_S_ib # -- Begin function _Z23__device_stub__CalcMassPdS_S_dS_S_S_ib
.p2align 4, 0x90
.type _Z23__device_stub__CalcMassPdS_S_dS_S_S_ib,@function
_Z23__device_stub__CalcMassPdS_S_dS_S_S_ib: # @_Z23__device_stub__CalcMassPdS_S_dS_S_S_ib
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movzbl 200(%rsp), %eax
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movsd %xmm0, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
movb %al, 7(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 192(%rsp), %rax
movq %rax, 168(%rsp)
leaq 7(%rsp), %rax
movq %rax, 176(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z8CalcMassPdS_S_dS_S_S_ib, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z23__device_stub__CalcMassPdS_S_dS_S_S_ib, .Lfunc_end0-_Z23__device_stub__CalcMassPdS_S_dS_S_S_ib
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8CalcMassPdS_S_dS_S_S_ib, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8CalcMassPdS_S_dS_S_S_ib,@object # @_Z8CalcMassPdS_S_dS_S_S_ib
.section .rodata,"a",@progbits
.globl _Z8CalcMassPdS_S_dS_S_S_ib
.p2align 3, 0x0
_Z8CalcMassPdS_S_dS_S_S_ib:
.quad _Z23__device_stub__CalcMassPdS_S_dS_S_S_ib
.size _Z8CalcMassPdS_S_dS_S_S_ib, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8CalcMassPdS_S_dS_S_S_ib"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__CalcMassPdS_S_dS_S_S_ib
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8CalcMassPdS_S_dS_S_S_ib
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000cf8f3_00000000-6_CalcMass.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z8CalcMassPdS_S_dS_S_S_ibPdS_S_dS_S_S_ib
.type _Z40__device_stub__Z8CalcMassPdS_S_dS_S_S_ibPdS_S_dS_S_S_ib, @function
_Z40__device_stub__Z8CalcMassPdS_S_dS_S_S_ibPdS_S_dS_S_S_ib:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movsd %xmm0, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movl 232(%rsp), %eax
movb %al, 4(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 224(%rsp), %rax
movq %rax, 184(%rsp)
leaq 4(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z8CalcMassPdS_S_dS_S_S_ib(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z8CalcMassPdS_S_dS_S_S_ibPdS_S_dS_S_S_ib, .-_Z40__device_stub__Z8CalcMassPdS_S_dS_S_S_ibPdS_S_dS_S_S_ib
.globl _Z8CalcMassPdS_S_dS_S_S_ib
.type _Z8CalcMassPdS_S_dS_S_S_ib, @function
_Z8CalcMassPdS_S_dS_S_S_ib:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z40__device_stub__Z8CalcMassPdS_S_dS_S_S_ibPdS_S_dS_S_S_ib
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8CalcMassPdS_S_dS_S_S_ib, .-_Z8CalcMassPdS_S_dS_S_S_ib
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8CalcMassPdS_S_dS_S_S_ib"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8CalcMassPdS_S_dS_S_S_ib(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CalcMass.hip"
.globl _Z23__device_stub__CalcMassPdS_S_dS_S_S_ib # -- Begin function _Z23__device_stub__CalcMassPdS_S_dS_S_S_ib
.p2align 4, 0x90
.type _Z23__device_stub__CalcMassPdS_S_dS_S_S_ib,@function
_Z23__device_stub__CalcMassPdS_S_dS_S_S_ib: # @_Z23__device_stub__CalcMassPdS_S_dS_S_S_ib
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movzbl 200(%rsp), %eax
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movsd %xmm0, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
movb %al, 7(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 192(%rsp), %rax
movq %rax, 168(%rsp)
leaq 7(%rsp), %rax
movq %rax, 176(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z8CalcMassPdS_S_dS_S_S_ib, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z23__device_stub__CalcMassPdS_S_dS_S_S_ib, .Lfunc_end0-_Z23__device_stub__CalcMassPdS_S_dS_S_S_ib
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8CalcMassPdS_S_dS_S_S_ib, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8CalcMassPdS_S_dS_S_S_ib,@object # @_Z8CalcMassPdS_S_dS_S_S_ib
.section .rodata,"a",@progbits
.globl _Z8CalcMassPdS_S_dS_S_S_ib
.p2align 3, 0x0
_Z8CalcMassPdS_S_dS_S_S_ib:
.quad _Z23__device_stub__CalcMassPdS_S_dS_S_S_ib
.size _Z8CalcMassPdS_S_dS_S_S_ib, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8CalcMassPdS_S_dS_S_S_ib"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__CalcMassPdS_S_dS_S_S_ib
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8CalcMassPdS_S_dS_S_S_ib
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //Alfred Shaker
//Octtober 30th 2015
//Matrix Multiply
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
//CUDA kernel function
__global__ void matrixMultiply(float* a, float* b, float* c, int n)
{
//use block dimentions to calculate column and row
int col = blockIdx.x*blockDim.x + threadIdx.x;
int row = blockIdx.y*blockDim.y + threadIdx.y;
for(int i = 0; i<n; i++)
{
c[row*n + col]+= a[row*n + i] + b[i*n + col];
}
}
//main function
int main(int argc, char* argv[])
{
//declare base values and 2d arrays
int width = 6;
float A_h[width][width], B_h[width][width], C_h[width][width];
float *A_d, *B_d, *C_d;
int tileWidth = 2;
int i, j;
//fill up arrays with random values between 0 and 9
for (i = 0; i < width; i++)
{
for( j = 0; j < width; j++)
{
A_h[i][j] = rand() % 10;
B_h[i][j] = rand() % 10;
}
}
//allocate memory for device variables
cudaMalloc((void**)&A_d, width*width*sizeof(int));
cudaMalloc((void**)&B_d, width*width*sizeof(int));
//copy values from host variables to device variables
cudaMemcpy(A_d, A_h, width*width*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(B_d, B_h, width*width*sizeof(int), cudaMemcpyHostToDevice);
//allocate memory for the device result array
cudaMalloc((void**)&C_d, width*width*sizeof(int));
//create variables for grid and block dimentions
dim3 dimGrid(width/tileWidth, width/tileWidth, 1);
dim3 dimBlock(tileWidth, tileWidth, 1);
//call the kernel function
matrixMultiply<<<dimGrid, dimBlock>>>(A_d, B_d, C_d, width);
//copy values from the device result array to the host result array
cudaMemcpy(C_h, C_d, width*width*sizeof(int), cudaMemcpyDeviceToHost);
//print the result of the matrix multiplication
for(i = 0; i<width; i++)
{
for(j = 0; j<width; j++)
{
printf("Index: [%d] [%d] Value:[%f] [%f]. Result: %f\n",i, j,A_h[i][j], B_h[i][j], C_h[i][j]);
}
}
//deallocate device variables memory
cudaFree(A_d);
cudaFree(B_d);
cudaFree(C_d);
return 0;
} | code for sm_80
Function : _Z14matrixMultiplyPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fc80000000f00 */
/*0030*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0040*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ LOP3.LUT R6, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300067812 */
/* 0x000fe200078ec0ff */
/*0090*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002600 */
/*00a0*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fc60000000f00 */
/*00b0*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*00c0*/ IMAD R5, R2, c[0x0][0x4], R5 ; /* 0x0000010002057a24 */
/* 0x002fe200078e0205 */
/*00d0*/ IADD3 R2, R0, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x000fe20007ffe0ff */
/*00e0*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x005fc600078e0203 */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0100*/ IMAD R5, R5, c[0x0][0x178], RZ ; /* 0x00005e0005057a24 */
/* 0x000fca00078e02ff */
/*0110*/ IADD3 R2, R4, R5, RZ ; /* 0x0000000504027210 */
/* 0x000fca0007ffe0ff */
/*0120*/ IMAD.WIDE R2, R2, R7, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fe400078e0207 */
/*0130*/ @!P0 BRA 0xe50 ; /* 0x00000d1000008947 */
/* 0x000fea0003800000 */
/*0140*/ IADD3 R8, -R6, c[0x0][0x178], RZ ; /* 0x00005e0006087a10 */
/* 0x000fe20007ffe1ff */
/*0150*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000162000c1e1900 */
/*0160*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0170*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD.WIDE R12, R4, R7, c[0x0][0x168] ; /* 0x00005a00040c7625 */
/* 0x000fe200078e0207 */
/*0190*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f04270 */
/*01a0*/ @!P0 BRA 0xc40 ; /* 0x00000a9000008947 */
/* 0x001fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x880 ; /* 0x000006a000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*0200*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea2000c1e1900 */
/*0210*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fca0008000f00 */
/*0220*/ IMAD.WIDE R10, R5, 0x4, R10 ; /* 0x00000004050a7825 */
/* 0x000fca00078e020a */
/*0230*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000ea4000c1e1900 */
/*0240*/ FADD R14, R14, R17 ; /* 0x000000110e0e7221 */
/* 0x004fc80000000000 */
/*0250*/ FADD R19, R14, R15 ; /* 0x0000000f0e137221 */
/* 0x020fe40000000000 */
/*0260*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x001fc600078e020c */
/*0270*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0280*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea8000c1e1900 */
/*0290*/ LDG.E R17, [R10.64+0x4] ; /* 0x000004040a117981 */
/* 0x000ea4000c1e1900 */
/*02a0*/ FADD R16, R16, R17 ; /* 0x0000001110107221 */
/* 0x004fc80000000000 */
/*02b0*/ FADD R21, R19, R16 ; /* 0x0000001013157221 */
/* 0x000fe40000000000 */
/*02c0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*02d0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*02e0*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ea8000c1e1900 */
/*02f0*/ LDG.E R13, [R10.64+0x8] ; /* 0x000008040a0d7981 */
/* 0x000ea4000c1e1900 */
/*0300*/ FADD R12, R12, R13 ; /* 0x0000000d0c0c7221 */
/* 0x004fc80000000000 */
/*0310*/ FADD R23, R21, R12 ; /* 0x0000000c15177221 */
/* 0x000fe40000000000 */
/*0320*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0210 */
/*0330*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0340*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ee8000c1e1900 */
/*0350*/ LDG.E R15, [R10.64+0xc] ; /* 0x00000c040a0f7981 */
/* 0x000ee4000c1e1900 */
/*0360*/ FADD R14, R14, R15 ; /* 0x0000000f0e0e7221 */
/* 0x008fc80000000000 */
/*0370*/ FADD R19, R23, R14 ; /* 0x0000000e17137221 */
/* 0x001fe40000000000 */
/*0380*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0390*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*03a0*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ee8000c1e1900 */
/*03b0*/ LDG.E R17, [R10.64+0x10] ; /* 0x000010040a117981 */
/* 0x000ee4000c1e1900 */
/*03c0*/ FADD R16, R16, R17 ; /* 0x0000001110107221 */
/* 0x008fc80000000000 */
/*03d0*/ FADD R21, R19, R16 ; /* 0x0000001013157221 */
/* 0x002fe40000000000 */
/*03e0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*03f0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0400*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ee8000c1e1900 */
/*0410*/ LDG.E R13, [R10.64+0x14] ; /* 0x000014040a0d7981 */
/* 0x000ee4000c1e1900 */
/*0420*/ FADD R12, R12, R13 ; /* 0x0000000d0c0c7221 */
/* 0x008fc80000000000 */
/*0430*/ FADD R23, R21, R12 ; /* 0x0000000c15177221 */
/* 0x004fe40000000000 */
/*0440*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0210 */
/*0450*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0460*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ee8000c1e1900 */
/*0470*/ LDG.E R15, [R10.64+0x18] ; /* 0x000018040a0f7981 */
/* 0x000ee4000c1e1900 */
/*0480*/ FADD R14, R14, R15 ; /* 0x0000000f0e0e7221 */
/* 0x008fc80000000000 */
/*0490*/ FADD R19, R23, R14 ; /* 0x0000000e17137221 */
/* 0x001fe40000000000 */
/*04a0*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*04b0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*04c0*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ee8000c1e1900 */
/*04d0*/ LDG.E R17, [R10.64+0x1c] ; /* 0x00001c040a117981 */
/* 0x000ee4000c1e1900 */
/*04e0*/ FADD R16, R16, R17 ; /* 0x0000001110107221 */
/* 0x008fc80000000000 */
/*04f0*/ FADD R21, R19, R16 ; /* 0x0000001013157221 */
/* 0x002fe40000000000 */
/*0500*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*0510*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0520*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ee8000c1e1900 */
/*0530*/ LDG.E R13, [R10.64+0x20] ; /* 0x000020040a0d7981 */
/* 0x000ee4000c1e1900 */
/*0540*/ FADD R12, R12, R13 ; /* 0x0000000d0c0c7221 */
/* 0x008fc80000000000 */
/*0550*/ FADD R23, R21, R12 ; /* 0x0000000c15177221 */
/* 0x004fe40000000000 */
/*0560*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0210 */
/*0570*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0580*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ee8000c1e1900 */
/*0590*/ LDG.E R15, [R10.64+0x24] ; /* 0x000024040a0f7981 */
/* 0x000ee4000c1e1900 */
/*05a0*/ FADD R14, R14, R15 ; /* 0x0000000f0e0e7221 */
/* 0x008fc80000000000 */
/*05b0*/ FADD R19, R23, R14 ; /* 0x0000000e17137221 */
/* 0x001fe40000000000 */
/*05c0*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*05d0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*05e0*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ee8000c1e1900 */
/*05f0*/ LDG.E R17, [R10.64+0x28] ; /* 0x000028040a117981 */
/* 0x000ee4000c1e1900 */
/*0600*/ FADD R16, R16, R17 ; /* 0x0000001110107221 */
/* 0x008fc80000000000 */
/*0610*/ FADD R21, R19, R16 ; /* 0x0000001013157221 */
/* 0x002fe40000000000 */
/*0620*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*0630*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0640*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ee8000c1e1900 */
/*0650*/ LDG.E R13, [R10.64+0x2c] ; /* 0x00002c040a0d7981 */
/* 0x000ee4000c1e1900 */
/*0660*/ FADD R12, R12, R13 ; /* 0x0000000d0c0c7221 */
/* 0x008fc80000000000 */
/*0670*/ FADD R23, R21, R12 ; /* 0x0000000c15177221 */
/* 0x004fe40000000000 */
/*0680*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0210 */
/*0690*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x000fe8000c101904 */
/*06a0*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea8000c1e1900 */
/*06b0*/ LDG.E R15, [R10.64+0x30] ; /* 0x000030040a0f7981 */
/* 0x000ea4000c1e1900 */
/*06c0*/ FADD R14, R14, R15 ; /* 0x0000000f0e0e7221 */
/* 0x004fc80000000000 */
/*06d0*/ FADD R19, R23, R14 ; /* 0x0000000e17137221 */
/* 0x001fe40000000000 */
/*06e0*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*06f0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0700*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea8000c1e1900 */
/*0710*/ LDG.E R17, [R10.64+0x34] ; /* 0x000034040a117981 */
/* 0x000ea4000c1e1900 */
/*0720*/ FADD R16, R16, R17 ; /* 0x0000001110107221 */
/* 0x004fc80000000000 */
/*0730*/ FADD R21, R19, R16 ; /* 0x0000001013157221 */
/* 0x002fe40000000000 */
/*0740*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*0750*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe8000c101904 */
/*0760*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ea8000c1e1900 */
/*0770*/ LDG.E R13, [R10.64+0x38] ; /* 0x000038040a0d7981 */
/* 0x000ea2000c1e1900 */
/*0780*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x001fc800078e0210 */
/*0790*/ FADD R12, R12, R13 ; /* 0x0000000d0c0c7221 */
/* 0x004fc80000000000 */
/*07a0*/ FADD R13, R21, R12 ; /* 0x0000000c150d7221 */
/* 0x000fca0000000000 */
/*07b0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*07c0*/ LDG.E R15, [R10.64+0x3c] ; /* 0x00003c040a0f7981 */
/* 0x000ea8000c1e1900 */
/*07d0*/ LDG.E R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000ea2000c1e1900 */
/*07e0*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fc80007ffe0ff */
/*07f0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe20003f24270 */
/*0800*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0810*/ IADD3 R9, R9, 0x10, RZ ; /* 0x0000001009097810 */
/* 0x000fc60007ffe0ff */
/*0820*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0830*/ FADD R12, R12, R15 ; /* 0x0000000f0c0c7221 */
/* 0x004fc80000000000 */
/*0840*/ FADD R15, R13, R12 ; /* 0x0000000c0d0f7221 */
/* 0x000fe40000000000 */
/*0850*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x001fc600078e0212 */
/*0860*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0001e2000c101904 */
/*0870*/ @P1 BRA 0x1f0 ; /* 0xfffff97000001947 */
/* 0x000fea000383ffff */
/*0880*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0890*/ @!P1 BRA 0xc20 ; /* 0x0000038000009947 */
/* 0x000fea0003800000 */
/*08a0*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*08b0*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea2000c1e1900 */
/*08c0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fca0008000f00 */
/*08d0*/ IMAD.WIDE R10, R5, 0x4, R10 ; /* 0x00000004050a7825 */
/* 0x000fca00078e020a */
/*08e0*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000ea4000c1e1900 */
/*08f0*/ FADD R14, R14, R17 ; /* 0x000000110e0e7221 */
/* 0x004fc80000000000 */
/*0900*/ FADD R19, R15, R14 ; /* 0x0000000e0f137221 */
/* 0x020fe40000000000 */
/*0910*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x001fc600078e020c */
/*0920*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0930*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea8000c1e1900 */
/*0940*/ LDG.E R17, [R10.64+0x4] ; /* 0x000004040a117981 */
/* 0x000ea4000c1e1900 */
/*0950*/ FADD R16, R16, R17 ; /* 0x0000001110107221 */
/* 0x004fc80000000000 */
/*0960*/ FADD R21, R19, R16 ; /* 0x0000001013157221 */
/* 0x000fe40000000000 */
/*0970*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*0980*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0990*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ LDG.E R13, [R10.64+0x8] ; /* 0x000008040a0d7981 */
/* 0x000ea4000c1e1900 */
/*09b0*/ FADD R12, R12, R13 ; /* 0x0000000d0c0c7221 */
/* 0x004fc80000000000 */
/*09c0*/ FADD R23, R21, R12 ; /* 0x0000000c15177221 */
/* 0x000fe40000000000 */
/*09d0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0210 */
/*09e0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*09f0*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ee8000c1e1900 */
/*0a00*/ LDG.E R15, [R10.64+0xc] ; /* 0x00000c040a0f7981 */
/* 0x000ee4000c1e1900 */
/*0a10*/ FADD R14, R14, R15 ; /* 0x0000000f0e0e7221 */
/* 0x008fc80000000000 */
/*0a20*/ FADD R19, R23, R14 ; /* 0x0000000e17137221 */
/* 0x001fe40000000000 */
/*0a30*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0a40*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0a50*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ee8000c1e1900 */
/*0a60*/ LDG.E R17, [R10.64+0x10] ; /* 0x000010040a117981 */
/* 0x000ee4000c1e1900 */
/*0a70*/ FADD R16, R16, R17 ; /* 0x0000001110107221 */
/* 0x008fc80000000000 */
/*0a80*/ FADD R21, R19, R16 ; /* 0x0000001013157221 */
/* 0x002fe40000000000 */
/*0a90*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*0aa0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0ab0*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ee8000c1e1900 */
/*0ac0*/ LDG.E R13, [R10.64+0x14] ; /* 0x000014040a0d7981 */
/* 0x000ee4000c1e1900 */
/*0ad0*/ FADD R12, R12, R13 ; /* 0x0000000d0c0c7221 */
/* 0x008fc80000000000 */
/*0ae0*/ FADD R23, R21, R12 ; /* 0x0000000c15177221 */
/* 0x004fe40000000000 */
/*0af0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0210 */
/*0b00*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*0b10*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea8000c1e1900 */
/*0b20*/ LDG.E R15, [R10.64+0x18] ; /* 0x000018040a0f7981 */
/* 0x000ea2000c1e1900 */
/*0b30*/ IMAD.WIDE R18, R0, 0x4, R12 ; /* 0x0000000400127825 */
/* 0x001fc800078e020c */
/*0b40*/ FADD R14, R14, R15 ; /* 0x0000000f0e0e7221 */
/* 0x004fc80000000000 */
/*0b50*/ FADD R25, R23, R14 ; /* 0x0000000e17197221 */
/* 0x000fca0000000000 */
/*0b60*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0b70*/ LDG.E R15, [R10.64+0x1c] ; /* 0x00001c040a0f7981 */
/* 0x000ea8000c1e1900 */
/*0b80*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000ea2000c1e1900 */
/*0b90*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0ba0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0bb0*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0212 */
/*0bc0*/ IADD3 R9, R9, 0x8, RZ ; /* 0x0000000809097810 */
/* 0x000fc40007ffe0ff */
/*0bd0*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*0be0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0bf0*/ FADD R14, R14, R15 ; /* 0x0000000f0e0e7221 */
/* 0x004fc80000000000 */
/*0c00*/ FADD R15, R25, R14 ; /* 0x0000000e190f7221 */
/* 0x000fca0000000000 */
/*0c10*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0003e4000c101904 */
/*0c20*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0c30*/ @!P0 BRA 0xe50 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*0c40*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*0c50*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea2000c1e1900 */
/*0c60*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fca0008000f00 */
/*0c70*/ IMAD.WIDE R10, R5, 0x4, R10 ; /* 0x00000004050a7825 */
/* 0x000fca00078e020a */
/*0c80*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000ea4000c1e1900 */
/*0c90*/ FADD R14, R14, R17 ; /* 0x000000110e0e7221 */
/* 0x004fc80000000000 */
/*0ca0*/ FADD R19, R14, R15 ; /* 0x0000000f0e137221 */
/* 0x020fe40000000000 */
/*0cb0*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x003fc600078e020c */
/*0cc0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0cd0*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea8000c1e1900 */
/*0ce0*/ LDG.E R17, [R10.64+0x4] ; /* 0x000004040a117981 */
/* 0x000ea4000c1e1900 */
/*0cf0*/ FADD R16, R16, R17 ; /* 0x0000001110107221 */
/* 0x004fc80000000000 */
/*0d00*/ FADD R21, R19, R16 ; /* 0x0000001013157221 */
/* 0x000fe40000000000 */
/*0d10*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*0d20*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe8000c101904 */
/*0d30*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ea8000c1e1900 */
/*0d40*/ LDG.E R13, [R10.64+0x8] ; /* 0x000008040a0d7981 */
/* 0x000ea2000c1e1900 */
/*0d50*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x001fc800078e0210 */
/*0d60*/ FADD R12, R12, R13 ; /* 0x0000000d0c0c7221 */
/* 0x004fc80000000000 */
/*0d70*/ FADD R13, R21, R12 ; /* 0x0000000c150d7221 */
/* 0x000fca0000000000 */
/*0d80*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0d90*/ LDG.E R15, [R10.64+0xc] ; /* 0x00000c040a0f7981 */
/* 0x000ea8000c1e1900 */
/*0da0*/ LDG.E R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000ea2000c1e1900 */
/*0db0*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fc80007ffe0ff */
/*0dc0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0dd0*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0de0*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fc60007ffe0ff */
/*0df0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0e00*/ FADD R12, R12, R15 ; /* 0x0000000f0c0c7221 */
/* 0x004fc80000000000 */
/*0e10*/ FADD R15, R13, R12 ; /* 0x0000000c0d0f7221 */
/* 0x000fe40000000000 */
/*0e20*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x001fc600078e0212 */
/*0e30*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0001e4000c101904 */
/*0e40*/ @P0 BRA 0xc40 ; /* 0xfffffdf000000947 */
/* 0x001fea000383ffff */
/*0e50*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0e60*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0e70*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000562000c1e1900 */
/*0e80*/ IADD3 R10, R5, R9, RZ ; /* 0x00000009050a7210 */
/* 0x000fe20007ffe0ff */
/*0e90*/ IMAD R4, R9, c[0x0][0x178], R4 ; /* 0x00005e0009047a24 */
/* 0x000fc800078e0204 */
/*0ea0*/ IMAD.WIDE R10, R10, R7, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fc800078e0207 */
/*0eb0*/ IMAD.WIDE R4, R4, R7, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0207 */
/*0ec0*/ MOV R12, R10 ; /* 0x0000000a000c7202 */
/* 0x004fc80000000f00 */
/*0ed0*/ MOV R8, R12 ; /* 0x0000000c00087202 */
/* 0x000fe20000000f00 */
/*0ee0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x0044e2000c1e1900 */
/*0ef0*/ MOV R9, R11 ; /* 0x0000000b00097202 */
/* 0x000fca0000000f00 */
/*0f00*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee2000c1e1900 */
/*0f10*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*0f20*/ IADD3 R12, P1, R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fe20007f3e0ff */
/*0f30*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x004fe200078e0204 */
/*0f40*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05270 */
/*0f50*/ IADD3.X R11, RZ, R11, RZ, P1, !PT ; /* 0x0000000bff0b7210 */
/* 0x000fe20000ffe4ff */
/*0f60*/ FADD R10, R7, R8 ; /* 0x00000008070a7221 */
/* 0x008fc80000000000 */
/*0f70*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x020fca0000000000 */
/*0f80*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e2000c101904 */
/*0f90*/ @P0 BRA 0xed0 ; /* 0xffffff3000000947 */
/* 0x000fea000383ffff */
/*0fa0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0fb0*/ BRA 0xfb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //Alfred Shaker
//Octtober 30th 2015
//Matrix Multiply
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
//CUDA kernel function
__global__ void matrixMultiply(float* a, float* b, float* c, int n)
{
//use block dimentions to calculate column and row
int col = blockIdx.x*blockDim.x + threadIdx.x;
int row = blockIdx.y*blockDim.y + threadIdx.y;
for(int i = 0; i<n; i++)
{
c[row*n + col]+= a[row*n + i] + b[i*n + col];
}
}
//main function
int main(int argc, char* argv[])
{
//declare base values and 2d arrays
int width = 6;
float A_h[width][width], B_h[width][width], C_h[width][width];
float *A_d, *B_d, *C_d;
int tileWidth = 2;
int i, j;
//fill up arrays with random values between 0 and 9
for (i = 0; i < width; i++)
{
for( j = 0; j < width; j++)
{
A_h[i][j] = rand() % 10;
B_h[i][j] = rand() % 10;
}
}
//allocate memory for device variables
cudaMalloc((void**)&A_d, width*width*sizeof(int));
cudaMalloc((void**)&B_d, width*width*sizeof(int));
//copy values from host variables to device variables
cudaMemcpy(A_d, A_h, width*width*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(B_d, B_h, width*width*sizeof(int), cudaMemcpyHostToDevice);
//allocate memory for the device result array
cudaMalloc((void**)&C_d, width*width*sizeof(int));
//create variables for grid and block dimentions
dim3 dimGrid(width/tileWidth, width/tileWidth, 1);
dim3 dimBlock(tileWidth, tileWidth, 1);
//call the kernel function
matrixMultiply<<<dimGrid, dimBlock>>>(A_d, B_d, C_d, width);
//copy values from the device result array to the host result array
cudaMemcpy(C_h, C_d, width*width*sizeof(int), cudaMemcpyDeviceToHost);
//print the result of the matrix multiplication
for(i = 0; i<width; i++)
{
for(j = 0; j<width; j++)
{
printf("Index: [%d] [%d] Value:[%f] [%f]. Result: %f\n",i, j,A_h[i][j], B_h[i][j], C_h[i][j]);
}
}
//deallocate device variables memory
cudaFree(A_d);
cudaFree(B_d);
cudaFree(C_d);
return 0;
} | .file "tmpxft_000e3633_00000000-6_matrixMultiply.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z14matrixMultiplyPfS_S_iPfS_S_i
.type _Z39__device_stub__Z14matrixMultiplyPfS_S_iPfS_S_i, @function
_Z39__device_stub__Z14matrixMultiplyPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14matrixMultiplyPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z39__device_stub__Z14matrixMultiplyPfS_S_iPfS_S_i, .-_Z39__device_stub__Z14matrixMultiplyPfS_S_iPfS_S_i
.globl _Z14matrixMultiplyPfS_S_i
.type _Z14matrixMultiplyPfS_S_i, @function
_Z14matrixMultiplyPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14matrixMultiplyPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14matrixMultiplyPfS_S_i, .-_Z14matrixMultiplyPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Index: [%d] [%d] Value:[%f] [%f]. Result: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $496, %rsp
.cfi_def_cfa_offset 544
movq %fs:40, %rax
movq %rax, 488(%rsp)
xorl %eax, %eax
movl $24, %ebp
jmp .L12
.L23:
addq $24, %rbp
cmpq $168, %rbp
je .L14
.L12:
leaq -24(%rbp), %rbx
.L13:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 48(%rsp,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 192(%rsp,%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L13
jmp .L23
.L14:
movq %rsp, %rdi
movl $144, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $144, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $144, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 192(%rsp), %rsi
movl $1, %ecx
movl $144, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movl $144, %esi
call cudaMalloc@PLT
movl $3, 24(%rsp)
movl $3, 28(%rsp)
movl $1, 32(%rsp)
movl $2, 36(%rsp)
movl $2, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L15:
leaq 336(%rsp), %rdi
movl $2, %ecx
movl $144, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %r14d
movl $0, %r12d
leaq .LC0(%rip), %r13
.L16:
movq %r14, %rbx
movl $0, %ebp
.L17:
pxor %xmm0, %xmm0
cvtss2sd 48(%rsp,%rbx), %xmm0
pxor %xmm2, %xmm2
cvtss2sd 336(%rsp,%rbx), %xmm2
pxor %xmm1, %xmm1
cvtss2sd 192(%rsp,%rbx), %xmm1
movl %ebp, %ecx
movl %r12d, %edx
movq %r13, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
addl $1, %ebp
addq $4, %rbx
cmpl $6, %ebp
jne .L17
addl $1, %r12d
addq $24, %r14
cmpl $6, %r12d
jne .L16
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 488(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $496, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl $6, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z39__device_stub__Z14matrixMultiplyPfS_S_iPfS_S_i
jmp .L15
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z14matrixMultiplyPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14matrixMultiplyPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //Alfred Shaker
//Octtober 30th 2015
//Matrix Multiply
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
//CUDA kernel function
__global__ void matrixMultiply(float* a, float* b, float* c, int n)
{
//use block dimentions to calculate column and row
int col = blockIdx.x*blockDim.x + threadIdx.x;
int row = blockIdx.y*blockDim.y + threadIdx.y;
for(int i = 0; i<n; i++)
{
c[row*n + col]+= a[row*n + i] + b[i*n + col];
}
}
//main function
int main(int argc, char* argv[])
{
//declare base values and 2d arrays
int width = 6;
float A_h[width][width], B_h[width][width], C_h[width][width];
float *A_d, *B_d, *C_d;
int tileWidth = 2;
int i, j;
//fill up arrays with random values between 0 and 9
for (i = 0; i < width; i++)
{
for( j = 0; j < width; j++)
{
A_h[i][j] = rand() % 10;
B_h[i][j] = rand() % 10;
}
}
//allocate memory for device variables
cudaMalloc((void**)&A_d, width*width*sizeof(int));
cudaMalloc((void**)&B_d, width*width*sizeof(int));
//copy values from host variables to device variables
cudaMemcpy(A_d, A_h, width*width*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(B_d, B_h, width*width*sizeof(int), cudaMemcpyHostToDevice);
//allocate memory for the device result array
cudaMalloc((void**)&C_d, width*width*sizeof(int));
//create variables for grid and block dimentions
dim3 dimGrid(width/tileWidth, width/tileWidth, 1);
dim3 dimBlock(tileWidth, tileWidth, 1);
//call the kernel function
matrixMultiply<<<dimGrid, dimBlock>>>(A_d, B_d, C_d, width);
//copy values from the device result array to the host result array
cudaMemcpy(C_h, C_d, width*width*sizeof(int), cudaMemcpyDeviceToHost);
//print the result of the matrix multiplication
for(i = 0; i<width; i++)
{
for(j = 0; j<width; j++)
{
printf("Index: [%d] [%d] Value:[%f] [%f]. Result: %f\n",i, j,A_h[i][j], B_h[i][j], C_h[i][j]);
}
}
//deallocate device variables memory
cudaFree(A_d);
cudaFree(B_d);
cudaFree(C_d);
return 0;
} | //Alfred Shaker
//Octtober 30th 2015
//Matrix Multiply
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
//CUDA kernel function
__global__ void matrixMultiply(float* a, float* b, float* c, int n)
{
//use block dimentions to calculate column and row
int col = blockIdx.x*blockDim.x + threadIdx.x;
int row = blockIdx.y*blockDim.y + threadIdx.y;
for(int i = 0; i<n; i++)
{
c[row*n + col]+= a[row*n + i] + b[i*n + col];
}
}
//main function
int main(int argc, char* argv[])
{
//declare base values and 2d arrays
int width = 6;
float A_h[width][width], B_h[width][width], C_h[width][width];
float *A_d, *B_d, *C_d;
int tileWidth = 2;
int i, j;
//fill up arrays with random values between 0 and 9
for (i = 0; i < width; i++)
{
for( j = 0; j < width; j++)
{
A_h[i][j] = rand() % 10;
B_h[i][j] = rand() % 10;
}
}
//allocate memory for device variables
hipMalloc((void**)&A_d, width*width*sizeof(int));
hipMalloc((void**)&B_d, width*width*sizeof(int));
//copy values from host variables to device variables
hipMemcpy(A_d, A_h, width*width*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(B_d, B_h, width*width*sizeof(int), hipMemcpyHostToDevice);
//allocate memory for the device result array
hipMalloc((void**)&C_d, width*width*sizeof(int));
//create variables for grid and block dimentions
dim3 dimGrid(width/tileWidth, width/tileWidth, 1);
dim3 dimBlock(tileWidth, tileWidth, 1);
//call the kernel function
matrixMultiply<<<dimGrid, dimBlock>>>(A_d, B_d, C_d, width);
//copy values from the device result array to the host result array
hipMemcpy(C_h, C_d, width*width*sizeof(int), hipMemcpyDeviceToHost);
//print the result of the matrix multiplication
for(i = 0; i<width; i++)
{
for(j = 0; j<width; j++)
{
printf("Index: [%d] [%d] Value:[%f] [%f]. Result: %f\n",i, j,A_h[i][j], B_h[i][j], C_h[i][j]);
}
}
//deallocate device variables memory
hipFree(A_d);
hipFree(B_d);
hipFree(C_d);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //Alfred Shaker
//Octtober 30th 2015
//Matrix Multiply
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
//CUDA kernel function
__global__ void matrixMultiply(float* a, float* b, float* c, int n)
{
//use block dimentions to calculate column and row
int col = blockIdx.x*blockDim.x + threadIdx.x;
int row = blockIdx.y*blockDim.y + threadIdx.y;
for(int i = 0; i<n; i++)
{
c[row*n + col]+= a[row*n + i] + b[i*n + col];
}
}
//main function
int main(int argc, char* argv[])
{
//declare base values and 2d arrays
int width = 6;
float A_h[width][width], B_h[width][width], C_h[width][width];
float *A_d, *B_d, *C_d;
int tileWidth = 2;
int i, j;
//fill up arrays with random values between 0 and 9
for (i = 0; i < width; i++)
{
for( j = 0; j < width; j++)
{
A_h[i][j] = rand() % 10;
B_h[i][j] = rand() % 10;
}
}
//allocate memory for device variables
hipMalloc((void**)&A_d, width*width*sizeof(int));
hipMalloc((void**)&B_d, width*width*sizeof(int));
//copy values from host variables to device variables
hipMemcpy(A_d, A_h, width*width*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(B_d, B_h, width*width*sizeof(int), hipMemcpyHostToDevice);
//allocate memory for the device result array
hipMalloc((void**)&C_d, width*width*sizeof(int));
//create variables for grid and block dimentions
dim3 dimGrid(width/tileWidth, width/tileWidth, 1);
dim3 dimBlock(tileWidth, tileWidth, 1);
//call the kernel function
matrixMultiply<<<dimGrid, dimBlock>>>(A_d, B_d, C_d, width);
//copy values from the device result array to the host result array
hipMemcpy(C_h, C_d, width*width*sizeof(int), hipMemcpyDeviceToHost);
//print the result of the matrix multiplication
for(i = 0; i<width; i++)
{
for(j = 0; j<width; j++)
{
printf("Index: [%d] [%d] Value:[%f] [%f]. Result: %f\n",i, j,A_h[i][j], B_h[i][j], C_h[i][j]);
}
}
//deallocate device variables memory
hipFree(A_d);
hipFree(B_d);
hipFree(C_d);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14matrixMultiplyPfS_S_i
.globl _Z14matrixMultiplyPfS_S_i
.p2align 8
.type _Z14matrixMultiplyPfS_S_i,@function
_Z14matrixMultiplyPfS_S_i:
s_load_b32 s4, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
s_load_b32 s2, s[0:1], 0x2c
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
v_and_b32_e32 v3, 0x3ff, v0
v_mad_u64_u32 v[0:1], null, s14, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v2, s4
s_load_b64 s[2:3], s[0:1], 0x10
v_add_nc_u32_e32 v1, v4, v0
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_load_b128 s[0:3], s[0:1], 0x0
global_load_b32 v6, v[2:3], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_mov_b32 s0, s4
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s0, 0
v_lshlrev_b64 v[7:8], 2, v[0:1]
v_add_nc_u32_e32 v0, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_load_b32 v1, v[4:5], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v7
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v6, v6, v1
global_store_b32 v[2:3], v6, off
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14matrixMultiplyPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14matrixMultiplyPfS_S_i, .Lfunc_end0-_Z14matrixMultiplyPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14matrixMultiplyPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14matrixMultiplyPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //Alfred Shaker
//Octtober 30th 2015
//Matrix Multiply
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
//CUDA kernel function
__global__ void matrixMultiply(float* a, float* b, float* c, int n)
{
//use block dimentions to calculate column and row
int col = blockIdx.x*blockDim.x + threadIdx.x;
int row = blockIdx.y*blockDim.y + threadIdx.y;
for(int i = 0; i<n; i++)
{
c[row*n + col]+= a[row*n + i] + b[i*n + col];
}
}
//main function
int main(int argc, char* argv[])
{
//declare base values and 2d arrays
int width = 6;
float A_h[width][width], B_h[width][width], C_h[width][width];
float *A_d, *B_d, *C_d;
int tileWidth = 2;
int i, j;
//fill up arrays with random values between 0 and 9
for (i = 0; i < width; i++)
{
for( j = 0; j < width; j++)
{
A_h[i][j] = rand() % 10;
B_h[i][j] = rand() % 10;
}
}
//allocate memory for device variables
hipMalloc((void**)&A_d, width*width*sizeof(int));
hipMalloc((void**)&B_d, width*width*sizeof(int));
//copy values from host variables to device variables
hipMemcpy(A_d, A_h, width*width*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(B_d, B_h, width*width*sizeof(int), hipMemcpyHostToDevice);
//allocate memory for the device result array
hipMalloc((void**)&C_d, width*width*sizeof(int));
//create variables for grid and block dimentions
dim3 dimGrid(width/tileWidth, width/tileWidth, 1);
dim3 dimBlock(tileWidth, tileWidth, 1);
//call the kernel function
matrixMultiply<<<dimGrid, dimBlock>>>(A_d, B_d, C_d, width);
//copy values from the device result array to the host result array
hipMemcpy(C_h, C_d, width*width*sizeof(int), hipMemcpyDeviceToHost);
//print the result of the matrix multiplication
for(i = 0; i<width; i++)
{
for(j = 0; j<width; j++)
{
printf("Index: [%d] [%d] Value:[%f] [%f]. Result: %f\n",i, j,A_h[i][j], B_h[i][j], C_h[i][j]);
}
}
//deallocate device variables memory
hipFree(A_d);
hipFree(B_d);
hipFree(C_d);
return 0;
} | .text
.file "matrixMultiply.hip"
.globl _Z29__device_stub__matrixMultiplyPfS_S_i # -- Begin function _Z29__device_stub__matrixMultiplyPfS_S_i
.p2align 4, 0x90
.type _Z29__device_stub__matrixMultiplyPfS_S_i,@function
_Z29__device_stub__matrixMultiplyPfS_S_i: # @_Z29__device_stub__matrixMultiplyPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14matrixMultiplyPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__matrixMultiplyPfS_S_i, .Lfunc_end0-_Z29__device_stub__matrixMultiplyPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $576, %rsp # imm = 0x240
.cfi_def_cfa_offset 624
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 144(%rsp), %rbx
leaq 288(%rsp), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_1: # %.preheader61
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%r12,4)
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r12,4)
incq %r12
cmpq $6, %r12
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %r15
addq $24, %rbx
addq $24, %r14
cmpq $6, %r15
jne .LBB1_1
# %bb.4:
leaq 24(%rsp), %rdi
movl $144, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $144, %esi
callq hipMalloc
movq 24(%rsp), %rdi
leaq 288(%rsp), %rbx
movl $144, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 144(%rsp), %r14
movl $144, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movl $144, %esi
callq hipMalloc
movabsq $12884901891, %rdi # imm = 0x300000003
movabsq $8589934594, %rdx # imm = 0x200000002
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $6, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z14matrixMultiplyPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 8(%rsp), %rsi
leaq 432(%rsp), %r15
movl $144, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss (%r14,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movss (%r15,%r13,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
movl $.L.str, %edi
movl %r12d, %esi
movl %r13d, %edx
movb $3, %al
callq printf
incq %r13
cmpq $6, %r13
jne .LBB1_8
# %bb.9: # in Loop: Header=BB1_7 Depth=1
incq %r12
addq $24, %r15
addq $24, %r14
addq $24, %rbx
cmpq $6, %r12
jne .LBB1_7
# %bb.10:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $576, %rsp # imm = 0x240
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14matrixMultiplyPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14matrixMultiplyPfS_S_i,@object # @_Z14matrixMultiplyPfS_S_i
.section .rodata,"a",@progbits
.globl _Z14matrixMultiplyPfS_S_i
.p2align 3, 0x0
_Z14matrixMultiplyPfS_S_i:
.quad _Z29__device_stub__matrixMultiplyPfS_S_i
.size _Z14matrixMultiplyPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Index: [%d] [%d] Value:[%f] [%f]. Result: %f\n"
.size .L.str, 46
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14matrixMultiplyPfS_S_i"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__matrixMultiplyPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14matrixMultiplyPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14matrixMultiplyPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fc80000000f00 */
/*0030*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*0040*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ LOP3.LUT R6, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300067812 */
/* 0x000fe200078ec0ff */
/*0090*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002600 */
/*00a0*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fc60000000f00 */
/*00b0*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*00c0*/ IMAD R5, R2, c[0x0][0x4], R5 ; /* 0x0000010002057a24 */
/* 0x002fe200078e0205 */
/*00d0*/ IADD3 R2, R0, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x000fe20007ffe0ff */
/*00e0*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x005fc600078e0203 */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0100*/ IMAD R5, R5, c[0x0][0x178], RZ ; /* 0x00005e0005057a24 */
/* 0x000fca00078e02ff */
/*0110*/ IADD3 R2, R4, R5, RZ ; /* 0x0000000504027210 */
/* 0x000fca0007ffe0ff */
/*0120*/ IMAD.WIDE R2, R2, R7, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fe400078e0207 */
/*0130*/ @!P0 BRA 0xe50 ; /* 0x00000d1000008947 */
/* 0x000fea0003800000 */
/*0140*/ IADD3 R8, -R6, c[0x0][0x178], RZ ; /* 0x00005e0006087a10 */
/* 0x000fe20007ffe1ff */
/*0150*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000162000c1e1900 */
/*0160*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0170*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD.WIDE R12, R4, R7, c[0x0][0x168] ; /* 0x00005a00040c7625 */
/* 0x000fe200078e0207 */
/*0190*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f04270 */
/*01a0*/ @!P0 BRA 0xc40 ; /* 0x00000a9000008947 */
/* 0x001fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x880 ; /* 0x000006a000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*0200*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea2000c1e1900 */
/*0210*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fca0008000f00 */
/*0220*/ IMAD.WIDE R10, R5, 0x4, R10 ; /* 0x00000004050a7825 */
/* 0x000fca00078e020a */
/*0230*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000ea4000c1e1900 */
/*0240*/ FADD R14, R14, R17 ; /* 0x000000110e0e7221 */
/* 0x004fc80000000000 */
/*0250*/ FADD R19, R14, R15 ; /* 0x0000000f0e137221 */
/* 0x020fe40000000000 */
/*0260*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x001fc600078e020c */
/*0270*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0280*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea8000c1e1900 */
/*0290*/ LDG.E R17, [R10.64+0x4] ; /* 0x000004040a117981 */
/* 0x000ea4000c1e1900 */
/*02a0*/ FADD R16, R16, R17 ; /* 0x0000001110107221 */
/* 0x004fc80000000000 */
/*02b0*/ FADD R21, R19, R16 ; /* 0x0000001013157221 */
/* 0x000fe40000000000 */
/*02c0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*02d0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*02e0*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ea8000c1e1900 */
/*02f0*/ LDG.E R13, [R10.64+0x8] ; /* 0x000008040a0d7981 */
/* 0x000ea4000c1e1900 */
/*0300*/ FADD R12, R12, R13 ; /* 0x0000000d0c0c7221 */
/* 0x004fc80000000000 */
/*0310*/ FADD R23, R21, R12 ; /* 0x0000000c15177221 */
/* 0x000fe40000000000 */
/*0320*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0210 */
/*0330*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0340*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ee8000c1e1900 */
/*0350*/ LDG.E R15, [R10.64+0xc] ; /* 0x00000c040a0f7981 */
/* 0x000ee4000c1e1900 */
/*0360*/ FADD R14, R14, R15 ; /* 0x0000000f0e0e7221 */
/* 0x008fc80000000000 */
/*0370*/ FADD R19, R23, R14 ; /* 0x0000000e17137221 */
/* 0x001fe40000000000 */
/*0380*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0390*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*03a0*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ee8000c1e1900 */
/*03b0*/ LDG.E R17, [R10.64+0x10] ; /* 0x000010040a117981 */
/* 0x000ee4000c1e1900 */
/*03c0*/ FADD R16, R16, R17 ; /* 0x0000001110107221 */
/* 0x008fc80000000000 */
/*03d0*/ FADD R21, R19, R16 ; /* 0x0000001013157221 */
/* 0x002fe40000000000 */
/*03e0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*03f0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0400*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ee8000c1e1900 */
/*0410*/ LDG.E R13, [R10.64+0x14] ; /* 0x000014040a0d7981 */
/* 0x000ee4000c1e1900 */
/*0420*/ FADD R12, R12, R13 ; /* 0x0000000d0c0c7221 */
/* 0x008fc80000000000 */
/*0430*/ FADD R23, R21, R12 ; /* 0x0000000c15177221 */
/* 0x004fe40000000000 */
/*0440*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0210 */
/*0450*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0460*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ee8000c1e1900 */
/*0470*/ LDG.E R15, [R10.64+0x18] ; /* 0x000018040a0f7981 */
/* 0x000ee4000c1e1900 */
/*0480*/ FADD R14, R14, R15 ; /* 0x0000000f0e0e7221 */
/* 0x008fc80000000000 */
/*0490*/ FADD R19, R23, R14 ; /* 0x0000000e17137221 */
/* 0x001fe40000000000 */
/*04a0*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*04b0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*04c0*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ee8000c1e1900 */
/*04d0*/ LDG.E R17, [R10.64+0x1c] ; /* 0x00001c040a117981 */
/* 0x000ee4000c1e1900 */
/*04e0*/ FADD R16, R16, R17 ; /* 0x0000001110107221 */
/* 0x008fc80000000000 */
/*04f0*/ FADD R21, R19, R16 ; /* 0x0000001013157221 */
/* 0x002fe40000000000 */
/*0500*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*0510*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0520*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ee8000c1e1900 */
/*0530*/ LDG.E R13, [R10.64+0x20] ; /* 0x000020040a0d7981 */
/* 0x000ee4000c1e1900 */
/*0540*/ FADD R12, R12, R13 ; /* 0x0000000d0c0c7221 */
/* 0x008fc80000000000 */
/*0550*/ FADD R23, R21, R12 ; /* 0x0000000c15177221 */
/* 0x004fe40000000000 */
/*0560*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0210 */
/*0570*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0580*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ee8000c1e1900 */
/*0590*/ LDG.E R15, [R10.64+0x24] ; /* 0x000024040a0f7981 */
/* 0x000ee4000c1e1900 */
/*05a0*/ FADD R14, R14, R15 ; /* 0x0000000f0e0e7221 */
/* 0x008fc80000000000 */
/*05b0*/ FADD R19, R23, R14 ; /* 0x0000000e17137221 */
/* 0x001fe40000000000 */
/*05c0*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*05d0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*05e0*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ee8000c1e1900 */
/*05f0*/ LDG.E R17, [R10.64+0x28] ; /* 0x000028040a117981 */
/* 0x000ee4000c1e1900 */
/*0600*/ FADD R16, R16, R17 ; /* 0x0000001110107221 */
/* 0x008fc80000000000 */
/*0610*/ FADD R21, R19, R16 ; /* 0x0000001013157221 */
/* 0x002fe40000000000 */
/*0620*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*0630*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0640*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ee8000c1e1900 */
/*0650*/ LDG.E R13, [R10.64+0x2c] ; /* 0x00002c040a0d7981 */
/* 0x000ee4000c1e1900 */
/*0660*/ FADD R12, R12, R13 ; /* 0x0000000d0c0c7221 */
/* 0x008fc80000000000 */
/*0670*/ FADD R23, R21, R12 ; /* 0x0000000c15177221 */
/* 0x004fe40000000000 */
/*0680*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0210 */
/*0690*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x000fe8000c101904 */
/*06a0*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea8000c1e1900 */
/*06b0*/ LDG.E R15, [R10.64+0x30] ; /* 0x000030040a0f7981 */
/* 0x000ea4000c1e1900 */
/*06c0*/ FADD R14, R14, R15 ; /* 0x0000000f0e0e7221 */
/* 0x004fc80000000000 */
/*06d0*/ FADD R19, R23, R14 ; /* 0x0000000e17137221 */
/* 0x001fe40000000000 */
/*06e0*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*06f0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0700*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea8000c1e1900 */
/*0710*/ LDG.E R17, [R10.64+0x34] ; /* 0x000034040a117981 */
/* 0x000ea4000c1e1900 */
/*0720*/ FADD R16, R16, R17 ; /* 0x0000001110107221 */
/* 0x004fc80000000000 */
/*0730*/ FADD R21, R19, R16 ; /* 0x0000001013157221 */
/* 0x002fe40000000000 */
/*0740*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*0750*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe8000c101904 */
/*0760*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ea8000c1e1900 */
/*0770*/ LDG.E R13, [R10.64+0x38] ; /* 0x000038040a0d7981 */
/* 0x000ea2000c1e1900 */
/*0780*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x001fc800078e0210 */
/*0790*/ FADD R12, R12, R13 ; /* 0x0000000d0c0c7221 */
/* 0x004fc80000000000 */
/*07a0*/ FADD R13, R21, R12 ; /* 0x0000000c150d7221 */
/* 0x000fca0000000000 */
/*07b0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*07c0*/ LDG.E R15, [R10.64+0x3c] ; /* 0x00003c040a0f7981 */
/* 0x000ea8000c1e1900 */
/*07d0*/ LDG.E R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000ea2000c1e1900 */
/*07e0*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fc80007ffe0ff */
/*07f0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe20003f24270 */
/*0800*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0810*/ IADD3 R9, R9, 0x10, RZ ; /* 0x0000001009097810 */
/* 0x000fc60007ffe0ff */
/*0820*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0830*/ FADD R12, R12, R15 ; /* 0x0000000f0c0c7221 */
/* 0x004fc80000000000 */
/*0840*/ FADD R15, R13, R12 ; /* 0x0000000c0d0f7221 */
/* 0x000fe40000000000 */
/*0850*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x001fc600078e0212 */
/*0860*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0001e2000c101904 */
/*0870*/ @P1 BRA 0x1f0 ; /* 0xfffff97000001947 */
/* 0x000fea000383ffff */
/*0880*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0890*/ @!P1 BRA 0xc20 ; /* 0x0000038000009947 */
/* 0x000fea0003800000 */
/*08a0*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*08b0*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea2000c1e1900 */
/*08c0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fca0008000f00 */
/*08d0*/ IMAD.WIDE R10, R5, 0x4, R10 ; /* 0x00000004050a7825 */
/* 0x000fca00078e020a */
/*08e0*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000ea4000c1e1900 */
/*08f0*/ FADD R14, R14, R17 ; /* 0x000000110e0e7221 */
/* 0x004fc80000000000 */
/*0900*/ FADD R19, R15, R14 ; /* 0x0000000e0f137221 */
/* 0x020fe40000000000 */
/*0910*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x001fc600078e020c */
/*0920*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0930*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea8000c1e1900 */
/*0940*/ LDG.E R17, [R10.64+0x4] ; /* 0x000004040a117981 */
/* 0x000ea4000c1e1900 */
/*0950*/ FADD R16, R16, R17 ; /* 0x0000001110107221 */
/* 0x004fc80000000000 */
/*0960*/ FADD R21, R19, R16 ; /* 0x0000001013157221 */
/* 0x000fe40000000000 */
/*0970*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*0980*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0990*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ LDG.E R13, [R10.64+0x8] ; /* 0x000008040a0d7981 */
/* 0x000ea4000c1e1900 */
/*09b0*/ FADD R12, R12, R13 ; /* 0x0000000d0c0c7221 */
/* 0x004fc80000000000 */
/*09c0*/ FADD R23, R21, R12 ; /* 0x0000000c15177221 */
/* 0x000fe40000000000 */
/*09d0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0210 */
/*09e0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*09f0*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ee8000c1e1900 */
/*0a00*/ LDG.E R15, [R10.64+0xc] ; /* 0x00000c040a0f7981 */
/* 0x000ee4000c1e1900 */
/*0a10*/ FADD R14, R14, R15 ; /* 0x0000000f0e0e7221 */
/* 0x008fc80000000000 */
/*0a20*/ FADD R19, R23, R14 ; /* 0x0000000e17137221 */
/* 0x001fe40000000000 */
/*0a30*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0a40*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0a50*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ee8000c1e1900 */
/*0a60*/ LDG.E R17, [R10.64+0x10] ; /* 0x000010040a117981 */
/* 0x000ee4000c1e1900 */
/*0a70*/ FADD R16, R16, R17 ; /* 0x0000001110107221 */
/* 0x008fc80000000000 */
/*0a80*/ FADD R21, R19, R16 ; /* 0x0000001013157221 */
/* 0x002fe40000000000 */
/*0a90*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*0aa0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0ab0*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ee8000c1e1900 */
/*0ac0*/ LDG.E R13, [R10.64+0x14] ; /* 0x000014040a0d7981 */
/* 0x000ee4000c1e1900 */
/*0ad0*/ FADD R12, R12, R13 ; /* 0x0000000d0c0c7221 */
/* 0x008fc80000000000 */
/*0ae0*/ FADD R23, R21, R12 ; /* 0x0000000c15177221 */
/* 0x004fe40000000000 */
/*0af0*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0210 */
/*0b00*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*0b10*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea8000c1e1900 */
/*0b20*/ LDG.E R15, [R10.64+0x18] ; /* 0x000018040a0f7981 */
/* 0x000ea2000c1e1900 */
/*0b30*/ IMAD.WIDE R18, R0, 0x4, R12 ; /* 0x0000000400127825 */
/* 0x001fc800078e020c */
/*0b40*/ FADD R14, R14, R15 ; /* 0x0000000f0e0e7221 */
/* 0x004fc80000000000 */
/*0b50*/ FADD R25, R23, R14 ; /* 0x0000000e17197221 */
/* 0x000fca0000000000 */
/*0b60*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0b70*/ LDG.E R15, [R10.64+0x1c] ; /* 0x00001c040a0f7981 */
/* 0x000ea8000c1e1900 */
/*0b80*/ LDG.E R14, [R18.64] ; /* 0x00000004120e7981 */
/* 0x000ea2000c1e1900 */
/*0b90*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0ba0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0bb0*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x000fe200078e0212 */
/*0bc0*/ IADD3 R9, R9, 0x8, RZ ; /* 0x0000000809097810 */
/* 0x000fc40007ffe0ff */
/*0bd0*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe20007ffe0ff */
/*0be0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0bf0*/ FADD R14, R14, R15 ; /* 0x0000000f0e0e7221 */
/* 0x004fc80000000000 */
/*0c00*/ FADD R15, R25, R14 ; /* 0x0000000e190f7221 */
/* 0x000fca0000000000 */
/*0c10*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0003e4000c101904 */
/*0c20*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0c30*/ @!P0 BRA 0xe50 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*0c40*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*0c50*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea2000c1e1900 */
/*0c60*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fca0008000f00 */
/*0c70*/ IMAD.WIDE R10, R5, 0x4, R10 ; /* 0x00000004050a7825 */
/* 0x000fca00078e020a */
/*0c80*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000ea4000c1e1900 */
/*0c90*/ FADD R14, R14, R17 ; /* 0x000000110e0e7221 */
/* 0x004fc80000000000 */
/*0ca0*/ FADD R19, R14, R15 ; /* 0x0000000f0e137221 */
/* 0x020fe40000000000 */
/*0cb0*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x003fc600078e020c */
/*0cc0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0001e8000c101904 */
/*0cd0*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea8000c1e1900 */
/*0ce0*/ LDG.E R17, [R10.64+0x4] ; /* 0x000004040a117981 */
/* 0x000ea4000c1e1900 */
/*0cf0*/ FADD R16, R16, R17 ; /* 0x0000001110107221 */
/* 0x004fc80000000000 */
/*0d00*/ FADD R21, R19, R16 ; /* 0x0000001013157221 */
/* 0x000fe40000000000 */
/*0d10*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*0d20*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe8000c101904 */
/*0d30*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ea8000c1e1900 */
/*0d40*/ LDG.E R13, [R10.64+0x8] ; /* 0x000008040a0d7981 */
/* 0x000ea2000c1e1900 */
/*0d50*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x001fc800078e0210 */
/*0d60*/ FADD R12, R12, R13 ; /* 0x0000000d0c0c7221 */
/* 0x004fc80000000000 */
/*0d70*/ FADD R13, R21, R12 ; /* 0x0000000c150d7221 */
/* 0x000fca0000000000 */
/*0d80*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0d90*/ LDG.E R15, [R10.64+0xc] ; /* 0x00000c040a0f7981 */
/* 0x000ea8000c1e1900 */
/*0da0*/ LDG.E R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000ea2000c1e1900 */
/*0db0*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fc80007ffe0ff */
/*0dc0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0dd0*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0de0*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fc60007ffe0ff */
/*0df0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0e00*/ FADD R12, R12, R15 ; /* 0x0000000f0c0c7221 */
/* 0x004fc80000000000 */
/*0e10*/ FADD R15, R13, R12 ; /* 0x0000000c0d0f7221 */
/* 0x000fe40000000000 */
/*0e20*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x001fc600078e0212 */
/*0e30*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0001e4000c101904 */
/*0e40*/ @P0 BRA 0xc40 ; /* 0xfffffdf000000947 */
/* 0x001fea000383ffff */
/*0e50*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0e60*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0e70*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000562000c1e1900 */
/*0e80*/ IADD3 R10, R5, R9, RZ ; /* 0x00000009050a7210 */
/* 0x000fe20007ffe0ff */
/*0e90*/ IMAD R4, R9, c[0x0][0x178], R4 ; /* 0x00005e0009047a24 */
/* 0x000fc800078e0204 */
/*0ea0*/ IMAD.WIDE R10, R10, R7, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fc800078e0207 */
/*0eb0*/ IMAD.WIDE R4, R4, R7, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0207 */
/*0ec0*/ MOV R12, R10 ; /* 0x0000000a000c7202 */
/* 0x004fc80000000f00 */
/*0ed0*/ MOV R8, R12 ; /* 0x0000000c00087202 */
/* 0x000fe20000000f00 */
/*0ee0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x0044e2000c1e1900 */
/*0ef0*/ MOV R9, R11 ; /* 0x0000000b00097202 */
/* 0x000fca0000000f00 */
/*0f00*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee2000c1e1900 */
/*0f10*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*0f20*/ IADD3 R12, P1, R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fe20007f3e0ff */
/*0f30*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x004fe200078e0204 */
/*0f40*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05270 */
/*0f50*/ IADD3.X R11, RZ, R11, RZ, P1, !PT ; /* 0x0000000bff0b7210 */
/* 0x000fe20000ffe4ff */
/*0f60*/ FADD R10, R7, R8 ; /* 0x00000008070a7221 */
/* 0x008fc80000000000 */
/*0f70*/ FADD R13, R10, R13 ; /* 0x0000000d0a0d7221 */
/* 0x020fca0000000000 */
/*0f80*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e2000c101904 */
/*0f90*/ @P0 BRA 0xed0 ; /* 0xffffff3000000947 */
/* 0x000fea000383ffff */
/*0fa0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0fb0*/ BRA 0xfb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0fc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14matrixMultiplyPfS_S_i
.globl _Z14matrixMultiplyPfS_S_i
.p2align 8
.type _Z14matrixMultiplyPfS_S_i,@function
_Z14matrixMultiplyPfS_S_i:
s_load_b32 s4, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
s_load_b32 s2, s[0:1], 0x2c
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
v_and_b32_e32 v3, 0x3ff, v0
v_mad_u64_u32 v[0:1], null, s14, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v2, s4
s_load_b64 s[2:3], s[0:1], 0x10
v_add_nc_u32_e32 v1, v4, v0
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_load_b128 s[0:3], s[0:1], 0x0
global_load_b32 v6, v[2:3], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_mov_b32 s0, s4
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s0, 0
v_lshlrev_b64 v[7:8], 2, v[0:1]
v_add_nc_u32_e32 v0, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_load_b32 v1, v[4:5], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v7
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v6, v6, v1
global_store_b32 v[2:3], v6, off
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14matrixMultiplyPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14matrixMultiplyPfS_S_i, .Lfunc_end0-_Z14matrixMultiplyPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14matrixMultiplyPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14matrixMultiplyPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e3633_00000000-6_matrixMultiply.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z14matrixMultiplyPfS_S_iPfS_S_i
.type _Z39__device_stub__Z14matrixMultiplyPfS_S_iPfS_S_i, @function
_Z39__device_stub__Z14matrixMultiplyPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14matrixMultiplyPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z39__device_stub__Z14matrixMultiplyPfS_S_iPfS_S_i, .-_Z39__device_stub__Z14matrixMultiplyPfS_S_iPfS_S_i
.globl _Z14matrixMultiplyPfS_S_i
.type _Z14matrixMultiplyPfS_S_i, @function
_Z14matrixMultiplyPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14matrixMultiplyPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14matrixMultiplyPfS_S_i, .-_Z14matrixMultiplyPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Index: [%d] [%d] Value:[%f] [%f]. Result: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $496, %rsp
.cfi_def_cfa_offset 544
movq %fs:40, %rax
movq %rax, 488(%rsp)
xorl %eax, %eax
movl $24, %ebp
jmp .L12
.L23:
addq $24, %rbp
cmpq $168, %rbp
je .L14
.L12:
leaq -24(%rbp), %rbx
.L13:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 48(%rsp,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 192(%rsp,%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L13
jmp .L23
.L14:
movq %rsp, %rdi
movl $144, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $144, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $144, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 192(%rsp), %rsi
movl $1, %ecx
movl $144, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movl $144, %esi
call cudaMalloc@PLT
movl $3, 24(%rsp)
movl $3, 28(%rsp)
movl $1, 32(%rsp)
movl $2, 36(%rsp)
movl $2, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L15:
leaq 336(%rsp), %rdi
movl $2, %ecx
movl $144, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %r14d
movl $0, %r12d
leaq .LC0(%rip), %r13
.L16:
movq %r14, %rbx
movl $0, %ebp
.L17:
pxor %xmm0, %xmm0
cvtss2sd 48(%rsp,%rbx), %xmm0
pxor %xmm2, %xmm2
cvtss2sd 336(%rsp,%rbx), %xmm2
pxor %xmm1, %xmm1
cvtss2sd 192(%rsp,%rbx), %xmm1
movl %ebp, %ecx
movl %r12d, %edx
movq %r13, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
addl $1, %ebp
addq $4, %rbx
cmpl $6, %ebp
jne .L17
addl $1, %r12d
addq $24, %r14
cmpl $6, %r12d
jne .L16
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 488(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $496, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl $6, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z39__device_stub__Z14matrixMultiplyPfS_S_iPfS_S_i
jmp .L15
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z14matrixMultiplyPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14matrixMultiplyPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixMultiply.hip"
.globl _Z29__device_stub__matrixMultiplyPfS_S_i # -- Begin function _Z29__device_stub__matrixMultiplyPfS_S_i
.p2align 4, 0x90
.type _Z29__device_stub__matrixMultiplyPfS_S_i,@function
_Z29__device_stub__matrixMultiplyPfS_S_i: # @_Z29__device_stub__matrixMultiplyPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14matrixMultiplyPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z29__device_stub__matrixMultiplyPfS_S_i, .Lfunc_end0-_Z29__device_stub__matrixMultiplyPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $576, %rsp # imm = 0x240
.cfi_def_cfa_offset 624
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 144(%rsp), %rbx
leaq 288(%rsp), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_1: # %.preheader61
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%r12,4)
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%r12,4)
incq %r12
cmpq $6, %r12
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %r15
addq $24, %rbx
addq $24, %r14
cmpq $6, %r15
jne .LBB1_1
# %bb.4:
leaq 24(%rsp), %rdi
movl $144, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $144, %esi
callq hipMalloc
movq 24(%rsp), %rdi
leaq 288(%rsp), %rbx
movl $144, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 144(%rsp), %r14
movl $144, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movl $144, %esi
callq hipMalloc
movabsq $12884901891, %rdi # imm = 0x300000003
movabsq $8589934594, %rdx # imm = 0x200000002
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $6, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z14matrixMultiplyPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 8(%rsp), %rsi
leaq 432(%rsp), %r15
movl $144, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss (%r14,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movss (%r15,%r13,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
movl $.L.str, %edi
movl %r12d, %esi
movl %r13d, %edx
movb $3, %al
callq printf
incq %r13
cmpq $6, %r13
jne .LBB1_8
# %bb.9: # in Loop: Header=BB1_7 Depth=1
incq %r12
addq $24, %r15
addq $24, %r14
addq $24, %rbx
cmpq $6, %r12
jne .LBB1_7
# %bb.10:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $576, %rsp # imm = 0x240
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14matrixMultiplyPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14matrixMultiplyPfS_S_i,@object # @_Z14matrixMultiplyPfS_S_i
.section .rodata,"a",@progbits
.globl _Z14matrixMultiplyPfS_S_i
.p2align 3, 0x0
_Z14matrixMultiplyPfS_S_i:
.quad _Z29__device_stub__matrixMultiplyPfS_S_i
.size _Z14matrixMultiplyPfS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Index: [%d] [%d] Value:[%f] [%f]. Result: %f\n"
.size .L.str, 46
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14matrixMultiplyPfS_S_i"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__matrixMultiplyPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14matrixMultiplyPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | void
init_bounds(int size, double *u) {
int i;
for (i = 0; i < size; i++) {
u[i * size + 0] = 0;
u[0 * size + i] = 20;
u[i * size + (size - 1)] = 20;
u[(size - 1) * size + i] = 20;
}
}
void init_interior(int size, double *u, double guess) {
int i, j;
for (i = 1; i < size - 1; i++) {
for (j = 1; j < size - 1; j++) {
u[i * size + j] = guess;
}
}
}
void
init_f(int N, double *f) {
int i,j, i_min, i_max, j_min, j_max;
i_min = (N + 1) / 2. * (0 + 1);
i_max = (N + 1) / 2. * (1. / 3 + 1);
j_max = (N + 1) / 2. * ( - 1. / 3 + 1);
j_min = (N + 1) / 2. * (- 2. / 3 + 1);
for (i = i_min; i <= i_max; i++) {
for (j = j_min; j <= j_max; j++) {
f[i * (N + 2) + j] = 200.;
}
}
}
void
init_u(int size, double *u, double guess) {
init_bounds(size, u);
init_interior(size, u, guess);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | void
init_bounds(int size, double *u) {
int i;
for (i = 0; i < size; i++) {
u[i * size + 0] = 0;
u[0 * size + i] = 20;
u[i * size + (size - 1)] = 20;
u[(size - 1) * size + i] = 20;
}
}
void init_interior(int size, double *u, double guess) {
int i, j;
for (i = 1; i < size - 1; i++) {
for (j = 1; j < size - 1; j++) {
u[i * size + j] = guess;
}
}
}
void
init_f(int N, double *f) {
int i,j, i_min, i_max, j_min, j_max;
i_min = (N + 1) / 2. * (0 + 1);
i_max = (N + 1) / 2. * (1. / 3 + 1);
j_max = (N + 1) / 2. * ( - 1. / 3 + 1);
j_min = (N + 1) / 2. * (- 2. / 3 + 1);
for (i = i_min; i <= i_max; i++) {
for (j = j_min; j <= j_max; j++) {
f[i * (N + 2) + j] = 200.;
}
}
}
void
init_u(int size, double *u, double guess) {
init_bounds(size, u);
init_interior(size, u, guess);
} | .file "tmpxft_00036056_00000000-6_init.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2033:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11init_boundsiPd
.type _Z11init_boundsiPd, @function
_Z11init_boundsiPd:
.LFB2027:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L3
leal -1(%rdi), %edx
imull %edi, %edx
movslq %edi, %rdi
leaq 0(,%rdi,8), %rcx
movq %rsi, %rax
leaq (%rsi,%rcx), %r8
movsd .LC1(%rip), %xmm0
movslq %edx, %rdx
.L5:
movq $0x000000000, (%rax)
movsd %xmm0, (%rsi)
movsd %xmm0, -8(%rax,%rdi,8)
movsd %xmm0, (%rsi,%rdx,8)
addq %rcx, %rax
addq $8, %rsi
cmpq %r8, %rsi
jne .L5
.L3:
ret
.cfi_endproc
.LFE2027:
.size _Z11init_boundsiPd, .-_Z11init_boundsiPd
.globl _Z13init_interioriPdd
.type _Z13init_interioriPdd, @function
_Z13init_interioriPdd:
.LFB2028:
.cfi_startproc
endbr64
cmpl $2, %edi
jle .L7
movslq %edi, %rdx
leaq 0(,%rdx,8), %r8
leal -3(%rdi), %eax
addq %rax, %rdx
leaq 8(%rsi,%rdx,8), %rdx
leal -1(%rdi), %esi
movl $1, %ecx
notq %rax
leaq 0(,%rax,8), %rdi
.L9:
leaq (%rdi,%rdx), %rax
.L10:
movsd %xmm0, 8(%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L10
addl $1, %ecx
addq %r8, %rdx
cmpl %esi, %ecx
jne .L9
.L7:
ret
.cfi_endproc
.LFE2028:
.size _Z13init_interioriPdd, .-_Z13init_interioriPdd
.globl _Z6init_fiPd
.type _Z6init_fiPd, @function
_Z6init_fiPd:
.LFB2029:
.cfi_startproc
endbr64
leal 1(%rdi), %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd .LC2(%rip), %xmm0
cvttsd2sil %xmm0, %ecx
movapd %xmm0, %xmm1
mulsd .LC3(%rip), %xmm1
cvttsd2sil %xmm1, %r8d
movapd %xmm0, %xmm1
mulsd .LC4(%rip), %xmm1
mulsd .LC5(%rip), %xmm0
cmpl %r8d, %ecx
jg .L20
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %r9
cvttsd2sil %xmm1, %r11d
cvttsd2sil %xmm0, %r10d
addl $2, %edi
movl %ecx, %esi
imull %edi, %esi
addl $1, %r8d
movslq %r10d, %rbp
movl %r11d, %ebx
subl %r10d, %ebx
addq %rbp, %rbx
leaq 8(%r9), %r12
movsd .LC6(%rip), %xmm0
jmp .L14
.L16:
movslq %esi, %rdx
leaq (%rdx,%rbp), %rax
leaq (%r9,%rax,8), %rax
addq %rbx, %rdx
leaq (%r12,%rdx,8), %rdx
.L15:
movsd %xmm0, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L15
.L17:
addl $1, %ecx
addl %edi, %esi
cmpl %r8d, %ecx
je .L12
.L14:
cmpl %r10d, %r11d
jge .L16
jmp .L17
.L12:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE2029:
.size _Z6init_fiPd, .-_Z6init_fiPd
.globl _Z6init_uiPdd
.type _Z6init_uiPdd, @function
_Z6init_uiPdd:
.LFB2030:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl %edi, %ebx
movq %rsi, %rbp
movsd %xmm0, (%rsp)
call _Z11init_boundsiPd
movsd (%rsp), %xmm0
movq %rbp, %rsi
movl %ebx, %edi
call _Z13init_interioriPdd
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _Z6init_uiPdd, .-_Z6init_uiPdd
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1077149696
.align 8
.LC2:
.long 0
.long 1071644672
.align 8
.LC3:
.long 1431655765
.long 1073042773
.align 8
.LC4:
.long 1431655766
.long 1071994197
.align 8
.LC5:
.long 1431655766
.long 1070945621
.align 8
.LC6:
.long 0
.long 1080623104
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | void
init_bounds(int size, double *u) {
int i;
for (i = 0; i < size; i++) {
u[i * size + 0] = 0;
u[0 * size + i] = 20;
u[i * size + (size - 1)] = 20;
u[(size - 1) * size + i] = 20;
}
}
void init_interior(int size, double *u, double guess) {
int i, j;
for (i = 1; i < size - 1; i++) {
for (j = 1; j < size - 1; j++) {
u[i * size + j] = guess;
}
}
}
void
init_f(int N, double *f) {
int i,j, i_min, i_max, j_min, j_max;
i_min = (N + 1) / 2. * (0 + 1);
i_max = (N + 1) / 2. * (1. / 3 + 1);
j_max = (N + 1) / 2. * ( - 1. / 3 + 1);
j_min = (N + 1) / 2. * (- 2. / 3 + 1);
for (i = i_min; i <= i_max; i++) {
for (j = j_min; j <= j_max; j++) {
f[i * (N + 2) + j] = 200.;
}
}
}
void
init_u(int size, double *u, double guess) {
init_bounds(size, u);
init_interior(size, u, guess);
} | #include <hip/hip_runtime.h>
void
init_bounds(int size, double *u) {
int i;
for (i = 0; i < size; i++) {
u[i * size + 0] = 0;
u[0 * size + i] = 20;
u[i * size + (size - 1)] = 20;
u[(size - 1) * size + i] = 20;
}
}
void init_interior(int size, double *u, double guess) {
int i, j;
for (i = 1; i < size - 1; i++) {
for (j = 1; j < size - 1; j++) {
u[i * size + j] = guess;
}
}
}
void
init_f(int N, double *f) {
int i,j, i_min, i_max, j_min, j_max;
i_min = (N + 1) / 2. * (0 + 1);
i_max = (N + 1) / 2. * (1. / 3 + 1);
j_max = (N + 1) / 2. * ( - 1. / 3 + 1);
j_min = (N + 1) / 2. * (- 2. / 3 + 1);
for (i = i_min; i <= i_max; i++) {
for (j = j_min; j <= j_max; j++) {
f[i * (N + 2) + j] = 200.;
}
}
}
void
init_u(int size, double *u, double guess) {
init_bounds(size, u);
init_interior(size, u, guess);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
void
init_bounds(int size, double *u) {
int i;
for (i = 0; i < size; i++) {
u[i * size + 0] = 0;
u[0 * size + i] = 20;
u[i * size + (size - 1)] = 20;
u[(size - 1) * size + i] = 20;
}
}
void init_interior(int size, double *u, double guess) {
int i, j;
for (i = 1; i < size - 1; i++) {
for (j = 1; j < size - 1; j++) {
u[i * size + j] = guess;
}
}
}
void
init_f(int N, double *f) {
int i,j, i_min, i_max, j_min, j_max;
i_min = (N + 1) / 2. * (0 + 1);
i_max = (N + 1) / 2. * (1. / 3 + 1);
j_max = (N + 1) / 2. * ( - 1. / 3 + 1);
j_min = (N + 1) / 2. * (- 2. / 3 + 1);
for (i = i_min; i <= i_max; i++) {
for (j = j_min; j <= j_max; j++) {
f[i * (N + 2) + j] = 200.;
}
}
}
void
init_u(int size, double *u, double guess) {
init_bounds(size, u);
init_interior(size, u, guess);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
void
init_bounds(int size, double *u) {
int i;
for (i = 0; i < size; i++) {
u[i * size + 0] = 0;
u[0 * size + i] = 20;
u[i * size + (size - 1)] = 20;
u[(size - 1) * size + i] = 20;
}
}
void init_interior(int size, double *u, double guess) {
int i, j;
for (i = 1; i < size - 1; i++) {
for (j = 1; j < size - 1; j++) {
u[i * size + j] = guess;
}
}
}
void
init_f(int N, double *f) {
int i,j, i_min, i_max, j_min, j_max;
i_min = (N + 1) / 2. * (0 + 1);
i_max = (N + 1) / 2. * (1. / 3 + 1);
j_max = (N + 1) / 2. * ( - 1. / 3 + 1);
j_min = (N + 1) / 2. * (- 2. / 3 + 1);
for (i = i_min; i <= i_max; i++) {
for (j = j_min; j <= j_max; j++) {
f[i * (N + 2) + j] = 200.;
}
}
}
void
init_u(int size, double *u, double guess) {
init_bounds(size, u);
init_interior(size, u, guess);
} | .text
.file "init.hip"
.globl _Z11init_boundsiPd # -- Begin function _Z11init_boundsiPd
.p2align 4, 0x90
.type _Z11init_boundsiPd,@function
_Z11init_boundsiPd: # @_Z11init_boundsiPd
.cfi_startproc
# %bb.0:
# kill: def $edi killed $edi def $rdi
testl %edi, %edi
jle .LBB0_3
# %bb.1: # %.lr.ph
leal -1(%rdi), %ecx
movslq %ecx, %rax
imull %edi, %ecx
movslq %ecx, %rdx
movl %edi, %ecx
leaq (%rsi,%rdx,8), %rdx
leaq (,%rcx,8), %rdi
xorl %r8d, %r8d
movabsq $4626322717216342016, %r9 # imm = 0x4034000000000000
movq %rsi, %r10
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq $0, (%r10)
movq %r9, (%rsi,%r8,8)
movq %r9, (%r10,%rax,8)
movq %r9, (%rdx,%r8,8)
incq %r8
addq %rdi, %r10
cmpq %r8, %rcx
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z11init_boundsiPd, .Lfunc_end0-_Z11init_boundsiPd
.cfi_endproc
# -- End function
.globl _Z13init_interioriPdd # -- Begin function _Z13init_interioriPdd
.p2align 4, 0x90
.type _Z13init_interioriPdd,@function
_Z13init_interioriPdd: # @_Z13init_interioriPdd
.cfi_startproc
# %bb.0:
# kill: def $edi killed $edi def $rdi
cmpl $3, %edi
jl .LBB1_5
# %bb.1: # %.preheader.lr.ph
leal -1(%rdi), %eax
movl %eax, %eax
movl $1, %ecx
movl %edi, %edx
.p2align 4, 0x90
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movl %edx, %r8d
leaq (%rsi,%r8,8), %r8
movl $1, %r9d
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movsd %xmm0, (%r8,%r9,8)
incq %r9
cmpq %r9, %rax
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %rcx
addl %edi, %edx
cmpq %rax, %rcx
jne .LBB1_2
.LBB1_5: # %._crit_edge14
retq
.Lfunc_end1:
.size _Z13init_interioriPdd, .Lfunc_end1-_Z13init_interioriPdd
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z6init_fiPd
.LCPI2_0:
.quad 0x3fe0000000000000 # double 0.5
.LCPI2_1:
.quad 0x3ff5555555555555 # double 1.3333333333333333
.LCPI2_2:
.quad 0x3fd5555555555556 # double 0.33333333333333337
.LCPI2_3:
.quad 0x3fe5555555555556 # double 0.66666666666666674
.text
.globl _Z6init_fiPd
.p2align 4, 0x90
.type _Z6init_fiPd,@function
_Z6init_fiPd: # @_Z6init_fiPd
.cfi_startproc
# %bb.0:
# kill: def $edi killed $edi def $rdi
leal 1(%rdi), %eax
cvtsi2sd %eax, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
cvttsd2si %xmm0, %r8d
movsd .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm0, %xmm1
cvttsd2si %xmm1, %eax
cmpl %eax, %r8d
jle .LBB2_1
.LBB2_6: # %._crit_edge21
retq
.LBB2_1: # %.preheader.lr.ph
movsd .LCPI2_2(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm0, %xmm1
cvttsd2si %xmm1, %ecx
mulsd .LCPI2_3(%rip), %xmm0
cvttsd2si %xmm0, %edx
addl $2, %edi
movslq %ecx, %r10
movslq %r8d, %r8
movslq %edi, %rdi
incl %eax
movq %r8, %r9
imulq %rdi, %r9
leaq (,%r10,8), %r11
leaq (%r11,%r9,8), %r9
addq %r9, %rsi
shlq $3, %rdi
movl %edx, %r9d
subl %r10d, %r9d
incl %r9d
movabsq $4641240890982006784, %r10 # imm = 0x4069000000000000
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %r8
addq %rdi, %rsi
cmpl %r8d, %eax
je .LBB2_6
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
cmpl %edx, %ecx
jg .LBB2_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movq %r10, (%rsi,%r11,8)
incq %r11
cmpl %r11d, %r9d
jne .LBB2_4
jmp .LBB2_5
.Lfunc_end2:
.size _Z6init_fiPd, .Lfunc_end2-_Z6init_fiPd
.cfi_endproc
# -- End function
.globl _Z6init_uiPdd # -- Begin function _Z6init_uiPdd
.p2align 4, 0x90
.type _Z6init_uiPdd,@function
_Z6init_uiPdd: # @_Z6init_uiPdd
.cfi_startproc
# %bb.0:
# kill: def $edi killed $edi def $rdi
testl %edi, %edi
jle .LBB3_3
# %bb.1: # %.lr.ph.i
leal -1(%rdi), %ecx
imull %edi, %ecx
movl %edi, %eax
movslq %edi, %rdx
movslq %ecx, %rcx
leaq (%rsi,%rcx,8), %rcx
leaq (%rsi,%rdx,8), %rdx
addq $-8, %rdx
xorl %r8d, %r8d
movabsq $4626322717216342016, %r9 # imm = 0x4034000000000000
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB3_2: # =>This Inner Loop Header: Depth=1
movq $0, (%rsi,%r8,8)
movq %r9, (%rsi,%r10,8)
movq %r9, (%rdx,%r8,8)
movq %r9, (%rcx,%r10,8)
incq %r10
addq %rax, %r8
cmpq %r10, %rax
jne .LBB3_2
.LBB3_3: # %_Z11init_boundsiPd.exit
cmpl $3, %edi
jl .LBB3_8
# %bb.4: # %.preheader.lr.ph.i
leal -1(%rdi), %eax
movl $1, %ecx
movl %edi, %edx
.p2align 4, 0x90
.LBB3_5: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
movl %edx, %r8d
leaq (%rsi,%r8,8), %r8
movl $1, %r9d
.p2align 4, 0x90
.LBB3_6: # Parent Loop BB3_5 Depth=1
# => This Inner Loop Header: Depth=2
movsd %xmm0, (%r8,%r9,8)
incq %r9
cmpq %r9, %rax
jne .LBB3_6
# %bb.7: # %._crit_edge.i
# in Loop: Header=BB3_5 Depth=1
incq %rcx
addl %edi, %edx
cmpq %rax, %rcx
jne .LBB3_5
.LBB3_8: # %_Z13init_interioriPdd.exit
retq
.Lfunc_end3:
.size _Z6init_uiPdd, .Lfunc_end3-_Z6init_uiPdd
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00036056_00000000-6_init.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2033:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11init_boundsiPd
.type _Z11init_boundsiPd, @function
_Z11init_boundsiPd:
.LFB2027:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L3
leal -1(%rdi), %edx
imull %edi, %edx
movslq %edi, %rdi
leaq 0(,%rdi,8), %rcx
movq %rsi, %rax
leaq (%rsi,%rcx), %r8
movsd .LC1(%rip), %xmm0
movslq %edx, %rdx
.L5:
movq $0x000000000, (%rax)
movsd %xmm0, (%rsi)
movsd %xmm0, -8(%rax,%rdi,8)
movsd %xmm0, (%rsi,%rdx,8)
addq %rcx, %rax
addq $8, %rsi
cmpq %r8, %rsi
jne .L5
.L3:
ret
.cfi_endproc
.LFE2027:
.size _Z11init_boundsiPd, .-_Z11init_boundsiPd
.globl _Z13init_interioriPdd
.type _Z13init_interioriPdd, @function
_Z13init_interioriPdd:
.LFB2028:
.cfi_startproc
endbr64
cmpl $2, %edi
jle .L7
movslq %edi, %rdx
leaq 0(,%rdx,8), %r8
leal -3(%rdi), %eax
addq %rax, %rdx
leaq 8(%rsi,%rdx,8), %rdx
leal -1(%rdi), %esi
movl $1, %ecx
notq %rax
leaq 0(,%rax,8), %rdi
.L9:
leaq (%rdi,%rdx), %rax
.L10:
movsd %xmm0, 8(%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L10
addl $1, %ecx
addq %r8, %rdx
cmpl %esi, %ecx
jne .L9
.L7:
ret
.cfi_endproc
.LFE2028:
.size _Z13init_interioriPdd, .-_Z13init_interioriPdd
.globl _Z6init_fiPd
.type _Z6init_fiPd, @function
_Z6init_fiPd:
.LFB2029:
.cfi_startproc
endbr64
leal 1(%rdi), %eax
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd .LC2(%rip), %xmm0
cvttsd2sil %xmm0, %ecx
movapd %xmm0, %xmm1
mulsd .LC3(%rip), %xmm1
cvttsd2sil %xmm1, %r8d
movapd %xmm0, %xmm1
mulsd .LC4(%rip), %xmm1
mulsd .LC5(%rip), %xmm0
cmpl %r8d, %ecx
jg .L20
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %r9
cvttsd2sil %xmm1, %r11d
cvttsd2sil %xmm0, %r10d
addl $2, %edi
movl %ecx, %esi
imull %edi, %esi
addl $1, %r8d
movslq %r10d, %rbp
movl %r11d, %ebx
subl %r10d, %ebx
addq %rbp, %rbx
leaq 8(%r9), %r12
movsd .LC6(%rip), %xmm0
jmp .L14
.L16:
movslq %esi, %rdx
leaq (%rdx,%rbp), %rax
leaq (%r9,%rax,8), %rax
addq %rbx, %rdx
leaq (%r12,%rdx,8), %rdx
.L15:
movsd %xmm0, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L15
.L17:
addl $1, %ecx
addl %edi, %esi
cmpl %r8d, %ecx
je .L12
.L14:
cmpl %r10d, %r11d
jge .L16
jmp .L17
.L12:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE2029:
.size _Z6init_fiPd, .-_Z6init_fiPd
.globl _Z6init_uiPdd
.type _Z6init_uiPdd, @function
_Z6init_uiPdd:
.LFB2030:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl %edi, %ebx
movq %rsi, %rbp
movsd %xmm0, (%rsp)
call _Z11init_boundsiPd
movsd (%rsp), %xmm0
movq %rbp, %rsi
movl %ebx, %edi
call _Z13init_interioriPdd
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _Z6init_uiPdd, .-_Z6init_uiPdd
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1077149696
.align 8
.LC2:
.long 0
.long 1071644672
.align 8
.LC3:
.long 1431655765
.long 1073042773
.align 8
.LC4:
.long 1431655766
.long 1071994197
.align 8
.LC5:
.long 1431655766
.long 1070945621
.align 8
.LC6:
.long 0
.long 1080623104
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "init.hip"
.globl _Z11init_boundsiPd # -- Begin function _Z11init_boundsiPd
.p2align 4, 0x90
.type _Z11init_boundsiPd,@function
_Z11init_boundsiPd: # @_Z11init_boundsiPd
.cfi_startproc
# %bb.0:
# kill: def $edi killed $edi def $rdi
testl %edi, %edi
jle .LBB0_3
# %bb.1: # %.lr.ph
leal -1(%rdi), %ecx
movslq %ecx, %rax
imull %edi, %ecx
movslq %ecx, %rdx
movl %edi, %ecx
leaq (%rsi,%rdx,8), %rdx
leaq (,%rcx,8), %rdi
xorl %r8d, %r8d
movabsq $4626322717216342016, %r9 # imm = 0x4034000000000000
movq %rsi, %r10
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq $0, (%r10)
movq %r9, (%rsi,%r8,8)
movq %r9, (%r10,%rax,8)
movq %r9, (%rdx,%r8,8)
incq %r8
addq %rdi, %r10
cmpq %r8, %rcx
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z11init_boundsiPd, .Lfunc_end0-_Z11init_boundsiPd
.cfi_endproc
# -- End function
.globl _Z13init_interioriPdd # -- Begin function _Z13init_interioriPdd
.p2align 4, 0x90
.type _Z13init_interioriPdd,@function
_Z13init_interioriPdd: # @_Z13init_interioriPdd
.cfi_startproc
# %bb.0:
# kill: def $edi killed $edi def $rdi
cmpl $3, %edi
jl .LBB1_5
# %bb.1: # %.preheader.lr.ph
leal -1(%rdi), %eax
movl %eax, %eax
movl $1, %ecx
movl %edi, %edx
.p2align 4, 0x90
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movl %edx, %r8d
leaq (%rsi,%r8,8), %r8
movl $1, %r9d
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movsd %xmm0, (%r8,%r9,8)
incq %r9
cmpq %r9, %rax
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %rcx
addl %edi, %edx
cmpq %rax, %rcx
jne .LBB1_2
.LBB1_5: # %._crit_edge14
retq
.Lfunc_end1:
.size _Z13init_interioriPdd, .Lfunc_end1-_Z13init_interioriPdd
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z6init_fiPd
.LCPI2_0:
.quad 0x3fe0000000000000 # double 0.5
.LCPI2_1:
.quad 0x3ff5555555555555 # double 1.3333333333333333
.LCPI2_2:
.quad 0x3fd5555555555556 # double 0.33333333333333337
.LCPI2_3:
.quad 0x3fe5555555555556 # double 0.66666666666666674
.text
.globl _Z6init_fiPd
.p2align 4, 0x90
.type _Z6init_fiPd,@function
_Z6init_fiPd: # @_Z6init_fiPd
.cfi_startproc
# %bb.0:
# kill: def $edi killed $edi def $rdi
leal 1(%rdi), %eax
cvtsi2sd %eax, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
cvttsd2si %xmm0, %r8d
movsd .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm0, %xmm1
cvttsd2si %xmm1, %eax
cmpl %eax, %r8d
jle .LBB2_1
.LBB2_6: # %._crit_edge21
retq
.LBB2_1: # %.preheader.lr.ph
movsd .LCPI2_2(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm0, %xmm1
cvttsd2si %xmm1, %ecx
mulsd .LCPI2_3(%rip), %xmm0
cvttsd2si %xmm0, %edx
addl $2, %edi
movslq %ecx, %r10
movslq %r8d, %r8
movslq %edi, %rdi
incl %eax
movq %r8, %r9
imulq %rdi, %r9
leaq (,%r10,8), %r11
leaq (%r11,%r9,8), %r9
addq %r9, %rsi
shlq $3, %rdi
movl %edx, %r9d
subl %r10d, %r9d
incl %r9d
movabsq $4641240890982006784, %r10 # imm = 0x4069000000000000
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %r8
addq %rdi, %rsi
cmpl %r8d, %eax
je .LBB2_6
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
cmpl %edx, %ecx
jg .LBB2_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movq %r10, (%rsi,%r11,8)
incq %r11
cmpl %r11d, %r9d
jne .LBB2_4
jmp .LBB2_5
.Lfunc_end2:
.size _Z6init_fiPd, .Lfunc_end2-_Z6init_fiPd
.cfi_endproc
# -- End function
.globl _Z6init_uiPdd # -- Begin function _Z6init_uiPdd
.p2align 4, 0x90
.type _Z6init_uiPdd,@function
_Z6init_uiPdd: # @_Z6init_uiPdd
.cfi_startproc
# %bb.0:
# kill: def $edi killed $edi def $rdi
testl %edi, %edi
jle .LBB3_3
# %bb.1: # %.lr.ph.i
leal -1(%rdi), %ecx
imull %edi, %ecx
movl %edi, %eax
movslq %edi, %rdx
movslq %ecx, %rcx
leaq (%rsi,%rcx,8), %rcx
leaq (%rsi,%rdx,8), %rdx
addq $-8, %rdx
xorl %r8d, %r8d
movabsq $4626322717216342016, %r9 # imm = 0x4034000000000000
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB3_2: # =>This Inner Loop Header: Depth=1
movq $0, (%rsi,%r8,8)
movq %r9, (%rsi,%r10,8)
movq %r9, (%rdx,%r8,8)
movq %r9, (%rcx,%r10,8)
incq %r10
addq %rax, %r8
cmpq %r10, %rax
jne .LBB3_2
.LBB3_3: # %_Z11init_boundsiPd.exit
cmpl $3, %edi
jl .LBB3_8
# %bb.4: # %.preheader.lr.ph.i
leal -1(%rdi), %eax
movl $1, %ecx
movl %edi, %edx
.p2align 4, 0x90
.LBB3_5: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
movl %edx, %r8d
leaq (%rsi,%r8,8), %r8
movl $1, %r9d
.p2align 4, 0x90
.LBB3_6: # Parent Loop BB3_5 Depth=1
# => This Inner Loop Header: Depth=2
movsd %xmm0, (%r8,%r9,8)
incq %r9
cmpq %r9, %rax
jne .LBB3_6
# %bb.7: # %._crit_edge.i
# in Loop: Header=BB3_5 Depth=1
incq %rcx
addl %edi, %edx
cmpq %rax, %rcx
jne .LBB3_5
.LBB3_8: # %_Z13init_interioriPdd.exit
retq
.Lfunc_end3:
.size _Z6init_uiPdd, .Lfunc_end3-_Z6init_uiPdd
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
// ïîäêëþ÷åíèå áèáëèîòåêè cuBLAS
#define IDX2C(i,j,ld) (((i)*(ld))+(j))
__global__ void matrixMultiplicationKernel(float* A, float* B, float* C, int N)
{
int ROW = blockIdx.y*blockDim.y + threadIdx.y;
int COL = blockIdx.x*blockDim.x + threadIdx.x;
float tmpSum = 0;
if (ROW < N && COL < N) {
// each thread computes one element of the block sub-matrix
for (int i = 0; i < N; i++) {
tmpSum += A[ROW * N + i] * B[i * N + COL];
}
C[ROW * N + COL] = tmpSum;
}
} | code for sm_80
Function : _Z26matrixMultiplicationKernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc00 ; /* 0x00000b0000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*01b0*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x000fcc00078e0219 */
/*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0280*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0290*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*02a0*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02b0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02c0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02e0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02f0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*0300*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0320*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0330*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0340*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0350*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0360*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0370*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0380*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0390*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*03a0*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*03b0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03d0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03e0*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*03f0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*0400*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0410*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*0420*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0430*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0440*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*0450*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0460*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0490*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*04a0*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*04b0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04c0*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*04d0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04e0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04f0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*0500*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*0510*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0520*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0530*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0540*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0550*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0560*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0570*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0580*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0590*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05b0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05c0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05e0*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*05f0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*0600*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*0610*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*0660*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0670*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0680*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0690*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06d0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06e0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06f0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0710*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0720*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0730*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0740*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0750*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0760*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0770*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0780*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0790*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*07a0*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07c0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07d0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07e0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07f0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*0800*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0810*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0830*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0840*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0850*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0860*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0870*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0880*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0890*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*08a0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08b0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08c0*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*08d0*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*08e0*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*08f0*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*0900*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*0910*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*0920*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*0930*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0940*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*0950*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0970*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0980*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0990*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*09a0*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09c0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09d0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09f0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*0a00*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a10*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a30*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a40*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a50*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0ab0*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0ac0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ad0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0ae0*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc00 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b20*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b30*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b40*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fd000078e0200 */
/*0b50*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b60*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b70*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b80*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0ba0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0bb0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bc0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bd0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0be0*/ FFMA R28, R11, R4, R28 ; /* 0x000000040b1c7223 */
/* 0x004fcc000000001c */
/*0bf0*/ @P0 BRA 0xb70 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0c00*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c10*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c20*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c30*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c50*/ BRA 0xc50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
// ïîäêëþ÷åíèå áèáëèîòåêè cuBLAS
#define IDX2C(i,j,ld) (((i)*(ld))+(j))
__global__ void matrixMultiplicationKernel(float* A, float* B, float* C, int N)
{
int ROW = blockIdx.y*blockDim.y + threadIdx.y;
int COL = blockIdx.x*blockDim.x + threadIdx.x;
float tmpSum = 0;
if (ROW < N && COL < N) {
// each thread computes one element of the block sub-matrix
for (int i = 0; i < N; i++) {
tmpSum += A[ROW * N + i] * B[i * N + COL];
}
C[ROW * N + COL] = tmpSum;
}
} | .file "tmpxft_000c83be_00000000-6_matrixMultiplicationKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z26matrixMultiplicationKernelPfS_S_iPfS_S_i
.type _Z51__device_stub__Z26matrixMultiplicationKernelPfS_S_iPfS_S_i, @function
_Z51__device_stub__Z26matrixMultiplicationKernelPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26matrixMultiplicationKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z51__device_stub__Z26matrixMultiplicationKernelPfS_S_iPfS_S_i, .-_Z51__device_stub__Z26matrixMultiplicationKernelPfS_S_iPfS_S_i
.globl _Z26matrixMultiplicationKernelPfS_S_i
.type _Z26matrixMultiplicationKernelPfS_S_i, @function
_Z26matrixMultiplicationKernelPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z26matrixMultiplicationKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26matrixMultiplicationKernelPfS_S_i, .-_Z26matrixMultiplicationKernelPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26matrixMultiplicationKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26matrixMultiplicationKernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
// ïîäêëþ÷åíèå áèáëèîòåêè cuBLAS
#define IDX2C(i,j,ld) (((i)*(ld))+(j))
__global__ void matrixMultiplicationKernel(float* A, float* B, float* C, int N)
{
int ROW = blockIdx.y*blockDim.y + threadIdx.y;
int COL = blockIdx.x*blockDim.x + threadIdx.x;
float tmpSum = 0;
if (ROW < N && COL < N) {
// each thread computes one element of the block sub-matrix
for (int i = 0; i < N; i++) {
tmpSum += A[ROW * N + i] * B[i * N + COL];
}
C[ROW * N + COL] = tmpSum;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
// ïîäêëþ÷åíèå áèáëèîòåêè cuBLAS
#define IDX2C(i,j,ld) (((i)*(ld))+(j))
__global__ void matrixMultiplicationKernel(float* A, float* B, float* C, int N)
{
int ROW = blockIdx.y*blockDim.y + threadIdx.y;
int COL = blockIdx.x*blockDim.x + threadIdx.x;
float tmpSum = 0;
if (ROW < N && COL < N) {
// each thread computes one element of the block sub-matrix
for (int i = 0; i < N; i++) {
tmpSum += A[ROW * N + i] * B[i * N + COL];
}
C[ROW * N + COL] = tmpSum;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// ïîäêëþ÷åíèå áèáëèîòåêè cuBLAS
#define IDX2C(i,j,ld) (((i)*(ld))+(j))
__global__ void matrixMultiplicationKernel(float* A, float* B, float* C, int N)
{
int ROW = blockIdx.y*blockDim.y + threadIdx.y;
int COL = blockIdx.x*blockDim.x + threadIdx.x;
float tmpSum = 0;
if (ROW < N && COL < N) {
// each thread computes one element of the block sub-matrix
for (int i = 0; i < N; i++) {
tmpSum += A[ROW * N + i] * B[i * N + COL];
}
C[ROW * N + COL] = tmpSum;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26matrixMultiplicationKernelPfS_S_i
.globl _Z26matrixMultiplicationKernelPfS_S_i
.p2align 8
.type _Z26matrixMultiplicationKernelPfS_S_i,@function
_Z26matrixMultiplicationKernelPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26matrixMultiplicationKernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26matrixMultiplicationKernelPfS_S_i, .Lfunc_end0-_Z26matrixMultiplicationKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26matrixMultiplicationKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26matrixMultiplicationKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// ïîäêëþ÷åíèå áèáëèîòåêè cuBLAS
#define IDX2C(i,j,ld) (((i)*(ld))+(j))
__global__ void matrixMultiplicationKernel(float* A, float* B, float* C, int N)
{
int ROW = blockIdx.y*blockDim.y + threadIdx.y;
int COL = blockIdx.x*blockDim.x + threadIdx.x;
float tmpSum = 0;
if (ROW < N && COL < N) {
// each thread computes one element of the block sub-matrix
for (int i = 0; i < N; i++) {
tmpSum += A[ROW * N + i] * B[i * N + COL];
}
C[ROW * N + COL] = tmpSum;
}
} | .text
.file "matrixMultiplicationKernel.hip"
.globl _Z41__device_stub__matrixMultiplicationKernelPfS_S_i # -- Begin function _Z41__device_stub__matrixMultiplicationKernelPfS_S_i
.p2align 4, 0x90
.type _Z41__device_stub__matrixMultiplicationKernelPfS_S_i,@function
_Z41__device_stub__matrixMultiplicationKernelPfS_S_i: # @_Z41__device_stub__matrixMultiplicationKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26matrixMultiplicationKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z41__device_stub__matrixMultiplicationKernelPfS_S_i, .Lfunc_end0-_Z41__device_stub__matrixMultiplicationKernelPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26matrixMultiplicationKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26matrixMultiplicationKernelPfS_S_i,@object # @_Z26matrixMultiplicationKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z26matrixMultiplicationKernelPfS_S_i
.p2align 3, 0x0
_Z26matrixMultiplicationKernelPfS_S_i:
.quad _Z41__device_stub__matrixMultiplicationKernelPfS_S_i
.size _Z26matrixMultiplicationKernelPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26matrixMultiplicationKernelPfS_S_i"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__matrixMultiplicationKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26matrixMultiplicationKernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z26matrixMultiplicationKernelPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc00 ; /* 0x00000b0000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fe200000001ff */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*01b0*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x000fcc00078e0219 */
/*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0280*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0290*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*02a0*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02b0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02c0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02d0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02e0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02f0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*0300*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0320*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0330*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0340*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0350*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0360*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0370*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0380*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0390*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*03a0*/ FFMA R29, R29, R27, R28 ; /* 0x0000001b1d1d7223 */
/* 0x004fc6000000001c */
/*03b0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03d0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03e0*/ FFMA R29, R16, R17, R29 ; /* 0x00000011101d7223 */
/* 0x008fe4000000001d */
/*03f0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*0400*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0410*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*0420*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0430*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0440*/ FFMA R26, R26, R7, R29 ; /* 0x000000071a1a7223 */
/* 0x000fc4000000001d */
/*0450*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0460*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0480*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0490*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*04a0*/ FFMA R9, R20, R9, R26 ; /* 0x0000000914097223 */
/* 0x020fc6000000001a */
/*04b0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04c0*/ FFMA R11, R8, R11, R9 ; /* 0x0000000b080b7223 */
/* 0x000fe40000000009 */
/*04d0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04e0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04f0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*0500*/ FFMA R21, R10, R21, R11 ; /* 0x000000150a157223 */
/* 0x000fc6000000000b */
/*0510*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0520*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0530*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0540*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0550*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0560*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0570*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0580*/ FFMA R9, R28, R27, R21 ; /* 0x0000001b1c097223 */
/* 0x004fc60000000015 */
/*0590*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05b0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05c0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05e0*/ FFMA R7, R14, R7, R9 ; /* 0x000000070e077223 */
/* 0x000fc80000000009 */
/*05f0*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x000fc80000000007 */
/*0600*/ FFMA R7, R18, R26, R7 ; /* 0x0000001a12077223 */
/* 0x020fc80000000007 */
/*0610*/ FFMA R7, R22, R17, R7 ; /* 0x0000001116077223 */
/* 0x010fe20000000007 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ FFMA R7, R15, R24, R7 ; /* 0x000000180f077223 */
/* 0x008fc80000000007 */
/*0660*/ FFMA R28, R19, R28, R7 ; /* 0x0000001c131c7223 */
/* 0x004fc80000000007 */
/*0670*/ FFMA R28, R23, R25, R28 ; /* 0x00000019171c7223 */
/* 0x000fe4000000001c */
/*0680*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0690*/ FFMA R28, R27, R8, R28 ; /* 0x000000081b1c7223 */
/* 0x000fe2000000001c */
/*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06d0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06e0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06f0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0710*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0720*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0730*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0740*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0750*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0760*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0770*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0780*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0790*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*07a0*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07c0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07d0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07e0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07f0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*0800*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0810*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0830*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0840*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0850*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0860*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0870*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0880*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0890*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*08a0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08b0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08c0*/ FFMA R7, R7, R20, R28 ; /* 0x0000001407077223 */
/* 0x004fc8000000001c */
/*08d0*/ FFMA R7, R21, R22, R7 ; /* 0x0000001615077223 */
/* 0x008fc80000000007 */
/*08e0*/ FFMA R7, R23, R26, R7 ; /* 0x0000001a17077223 */
/* 0x020fc80000000007 */
/*08f0*/ FFMA R7, R14, R27, R7 ; /* 0x0000001b0e077223 */
/* 0x000fc80000000007 */
/*0900*/ FFMA R7, R10, R25, R7 ; /* 0x000000190a077223 */
/* 0x000fc80000000007 */
/*0910*/ FFMA R7, R16, R29, R7 ; /* 0x0000001d10077223 */
/* 0x010fc80000000007 */
/*0920*/ FFMA R7, R24, R11, R7 ; /* 0x0000000b18077223 */
/* 0x000fe40000000007 */
/*0930*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0940*/ FFMA R28, R15, R18, R7 ; /* 0x000000120f1c7223 */
/* 0x000fe40000000007 */
/*0950*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0970*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0980*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0990*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*09a0*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09c0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09d0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09f0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*0a00*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a10*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a30*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a40*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a50*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ FFMA R7, R25, R7, R28 ; /* 0x0000000719077223 */
/* 0x004fc8000000001c */
/*0ab0*/ FFMA R7, R14, R16, R7 ; /* 0x000000100e077223 */
/* 0x008fe40000000007 */
/*0ac0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ad0*/ FFMA R7, R18, R17, R7 ; /* 0x0000001112077223 */
/* 0x010fc80000000007 */
/*0ae0*/ FFMA R28, R20, R19, R7 ; /* 0x00000013141c7223 */
/* 0x020fe20000000007 */
/*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc00 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b20*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b30*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b40*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fd000078e0200 */
/*0b50*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b60*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b70*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b80*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0ba0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0bb0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bc0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bd0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0be0*/ FFMA R28, R11, R4, R28 ; /* 0x000000040b1c7223 */
/* 0x004fcc000000001c */
/*0bf0*/ @P0 BRA 0xb70 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0c00*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c10*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c20*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c30*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c40*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c50*/ BRA 0xc50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26matrixMultiplicationKernelPfS_S_i
.globl _Z26matrixMultiplicationKernelPfS_S_i
.p2align 8
.type _Z26matrixMultiplicationKernelPfS_S_i,@function
_Z26matrixMultiplicationKernelPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26matrixMultiplicationKernelPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26matrixMultiplicationKernelPfS_S_i, .Lfunc_end0-_Z26matrixMultiplicationKernelPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26matrixMultiplicationKernelPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26matrixMultiplicationKernelPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c83be_00000000-6_matrixMultiplicationKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z26matrixMultiplicationKernelPfS_S_iPfS_S_i
.type _Z51__device_stub__Z26matrixMultiplicationKernelPfS_S_iPfS_S_i, @function
_Z51__device_stub__Z26matrixMultiplicationKernelPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26matrixMultiplicationKernelPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z51__device_stub__Z26matrixMultiplicationKernelPfS_S_iPfS_S_i, .-_Z51__device_stub__Z26matrixMultiplicationKernelPfS_S_iPfS_S_i
.globl _Z26matrixMultiplicationKernelPfS_S_i
.type _Z26matrixMultiplicationKernelPfS_S_i, @function
_Z26matrixMultiplicationKernelPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z26matrixMultiplicationKernelPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26matrixMultiplicationKernelPfS_S_i, .-_Z26matrixMultiplicationKernelPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26matrixMultiplicationKernelPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26matrixMultiplicationKernelPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixMultiplicationKernel.hip"
.globl _Z41__device_stub__matrixMultiplicationKernelPfS_S_i # -- Begin function _Z41__device_stub__matrixMultiplicationKernelPfS_S_i
.p2align 4, 0x90
.type _Z41__device_stub__matrixMultiplicationKernelPfS_S_i,@function
_Z41__device_stub__matrixMultiplicationKernelPfS_S_i: # @_Z41__device_stub__matrixMultiplicationKernelPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26matrixMultiplicationKernelPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z41__device_stub__matrixMultiplicationKernelPfS_S_i, .Lfunc_end0-_Z41__device_stub__matrixMultiplicationKernelPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26matrixMultiplicationKernelPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26matrixMultiplicationKernelPfS_S_i,@object # @_Z26matrixMultiplicationKernelPfS_S_i
.section .rodata,"a",@progbits
.globl _Z26matrixMultiplicationKernelPfS_S_i
.p2align 3, 0x0
_Z26matrixMultiplicationKernelPfS_S_i:
.quad _Z41__device_stub__matrixMultiplicationKernelPfS_S_i
.size _Z26matrixMultiplicationKernelPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26matrixMultiplicationKernelPfS_S_i"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__matrixMultiplicationKernelPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26matrixMultiplicationKernelPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Exhibits a bank conflict.
// Gklee and Gkleep both detect this.
#include <cstdio>
#define N 32
__global__ void bc(char* in, char* out)
{
__shared__ int smem[512];
int tid = threadIdx.x;
smem[tid*2]=in[tid];
__syncthreads();
smem[tid*4]=in[tid];
__syncthreads();
smem[tid*8]=in[tid];
__syncthreads();
int x = smem[tid * 2]; // 2-way bank conflicts
int y = smem[tid * 4]; // 4-way bank conflicts
int z = smem[tid * 8]; // 8-way bank conflicts
int m = max(max(x,y),z);
out[tid] = m;
}
int main()
{
char* in = (char*) malloc(N*sizeof(char));
for(int i = 0; i < N; i++)
in[i] = i;
char* din, * dout;
cudaMalloc((void**) &din, N*sizeof(char));
cudaMalloc((void**) &dout, N*sizeof(char));
cudaMemcpy(din, in, N*sizeof(char), cudaMemcpyHostToDevice);
bc<<<1,N>>>(din,dout);
cudaMemcpy(in, dout, N*sizeof(char), cudaMemcpyDeviceToHost);
for(int i = 0; i < N; i++)
printf("%d ", in[i]);
printf("\n");
free(in); cudaFree(din); cudaFree(dout);
} | code for sm_80
Function : _Z2bcPcS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ SHF.R.S32.HI R12, RZ, 0x1f, R11 ; /* 0x0000001fff0c7819 */
/* 0x001fe4000001140b */
/*0040*/ IADD3 R2, P0, R11, c[0x0][0x160], RZ ; /* 0x000058000b027a10 */
/* 0x000fc80007f1e0ff */
/*0050*/ IADD3.X R3, R12, c[0x0][0x164], RZ, P0, !PT ; /* 0x000059000c037a10 */
/* 0x000fca00007fe4ff */
/*0060*/ LDG.E.S8 R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1300 */
/*0070*/ STS [R11.X8], R0 ; /* 0x000000000b007388 */
/* 0x004fe80000008800 */
/*0080*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0090*/ LDG.E.S8 R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea8000c1e1300 */
/*00a0*/ STS [R11.X16], R6 ; /* 0x000000060b007388 */
/* 0x004fe8000000c800 */
/*00b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00c0*/ LDG.E.S8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea2000c1e1300 */
/*00d0*/ IMAD.SHL.U32 R8, R11.reuse, 0x20, RZ ; /* 0x000000200b087824 */
/* 0x040fe200078e00ff */
/*00e0*/ IADD3 R4, P0, R11, c[0x0][0x168], RZ ; /* 0x00005a000b047a10 */
/* 0x000fc80007f1e0ff */
/*00f0*/ STS [R8], R7 ; /* 0x0000000708007388 */
/* 0x004fe80000000800 */
/*0100*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0110*/ LDS R5, [R11.X8] ; /* 0x000000000b057984 */
/* 0x000fe80000008800 */
/*0120*/ LDS R10, [R11.X16] ; /* 0x000000000b0a7984 */
/* 0x000e28000000c800 */
/*0130*/ LDS R0, [R8] ; /* 0x0000000008007984 */
/* 0x000e620000000800 */
/*0140*/ IMNMX R9, R5, R10, !PT ; /* 0x0000000a05097217 */
/* 0x001fc40007800200 */
/*0150*/ IADD3.X R5, R12, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b000c057a10 */
/* 0x000fe400007fe4ff */
/*0160*/ IMNMX R9, R0, R9, !PT ; /* 0x0000000900097217 */
/* 0x002fca0007800200 */
/*0170*/ STG.E.U8 [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe2000c101104 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Exhibits a bank conflict.
// Gklee and Gkleep both detect this.
#include <cstdio>
#define N 32
__global__ void bc(char* in, char* out)
{
__shared__ int smem[512];
int tid = threadIdx.x;
smem[tid*2]=in[tid];
__syncthreads();
smem[tid*4]=in[tid];
__syncthreads();
smem[tid*8]=in[tid];
__syncthreads();
int x = smem[tid * 2]; // 2-way bank conflicts
int y = smem[tid * 4]; // 4-way bank conflicts
int z = smem[tid * 8]; // 8-way bank conflicts
int m = max(max(x,y),z);
out[tid] = m;
}
int main()
{
char* in = (char*) malloc(N*sizeof(char));
for(int i = 0; i < N; i++)
in[i] = i;
char* din, * dout;
cudaMalloc((void**) &din, N*sizeof(char));
cudaMalloc((void**) &dout, N*sizeof(char));
cudaMemcpy(din, in, N*sizeof(char), cudaMemcpyHostToDevice);
bc<<<1,N>>>(din,dout);
cudaMemcpy(in, dout, N*sizeof(char), cudaMemcpyDeviceToHost);
for(int i = 0; i < N; i++)
printf("%d ", in[i]);
printf("\n");
free(in); cudaFree(din); cudaFree(dout);
} | .file "tmpxft_00135087_00000000-6_bank_conflict.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z2bcPcS_PcS_
.type _Z23__device_stub__Z2bcPcS_PcS_, @function
_Z23__device_stub__Z2bcPcS_PcS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z2bcPcS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z23__device_stub__Z2bcPcS_PcS_, .-_Z23__device_stub__Z2bcPcS_PcS_
.globl _Z2bcPcS_
.type _Z2bcPcS_, @function
_Z2bcPcS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z2bcPcS_PcS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z2bcPcS_, .-_Z2bcPcS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $32, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %eax
.L12:
movb %al, 0(%rbp,%rax)
addq $1, %rax
cmpq $32, %rax
jne .L12
movq %rsp, %rdi
movl $32, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $32, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $32, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq %rbp, %rbx
leaq 32(%rbp), %r13
leaq .LC0(%rip), %r12
.L14:
movsbl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %r13, %rbx
jne .L14
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z23__device_stub__Z2bcPcS_PcS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z2bcPcS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z2bcPcS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Exhibits a bank conflict.
// Gklee and Gkleep both detect this.
#include <cstdio>
#define N 32
__global__ void bc(char* in, char* out)
{
__shared__ int smem[512];
int tid = threadIdx.x;
smem[tid*2]=in[tid];
__syncthreads();
smem[tid*4]=in[tid];
__syncthreads();
smem[tid*8]=in[tid];
__syncthreads();
int x = smem[tid * 2]; // 2-way bank conflicts
int y = smem[tid * 4]; // 4-way bank conflicts
int z = smem[tid * 8]; // 8-way bank conflicts
int m = max(max(x,y),z);
out[tid] = m;
}
int main()
{
char* in = (char*) malloc(N*sizeof(char));
for(int i = 0; i < N; i++)
in[i] = i;
char* din, * dout;
cudaMalloc((void**) &din, N*sizeof(char));
cudaMalloc((void**) &dout, N*sizeof(char));
cudaMemcpy(din, in, N*sizeof(char), cudaMemcpyHostToDevice);
bc<<<1,N>>>(din,dout);
cudaMemcpy(in, dout, N*sizeof(char), cudaMemcpyDeviceToHost);
for(int i = 0; i < N; i++)
printf("%d ", in[i]);
printf("\n");
free(in); cudaFree(din); cudaFree(dout);
} | // Exhibits a bank conflict.
// Gklee and Gkleep both detect this.
#include <hip/hip_runtime.h>
#include <cstdio>
#define N 32
__global__ void bc(char* in, char* out)
{
__shared__ int smem[512];
int tid = threadIdx.x;
smem[tid*2]=in[tid];
__syncthreads();
smem[tid*4]=in[tid];
__syncthreads();
smem[tid*8]=in[tid];
__syncthreads();
int x = smem[tid * 2]; // 2-way bank conflicts
int y = smem[tid * 4]; // 4-way bank conflicts
int z = smem[tid * 8]; // 8-way bank conflicts
int m = max(max(x,y),z);
out[tid] = m;
}
int main()
{
char* in = (char*) malloc(N*sizeof(char));
for(int i = 0; i < N; i++)
in[i] = i;
char* din, * dout;
hipMalloc((void**) &din, N*sizeof(char));
hipMalloc((void**) &dout, N*sizeof(char));
hipMemcpy(din, in, N*sizeof(char), hipMemcpyHostToDevice);
bc<<<1,N>>>(din,dout);
hipMemcpy(in, dout, N*sizeof(char), hipMemcpyDeviceToHost);
for(int i = 0; i < N; i++)
printf("%d ", in[i]);
printf("\n");
free(in); hipFree(din); hipFree(dout);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Exhibits a bank conflict.
// Gklee and Gkleep both detect this.
#include <hip/hip_runtime.h>
#include <cstdio>
#define N 32
__global__ void bc(char* in, char* out)
{
__shared__ int smem[512];
int tid = threadIdx.x;
smem[tid*2]=in[tid];
__syncthreads();
smem[tid*4]=in[tid];
__syncthreads();
smem[tid*8]=in[tid];
__syncthreads();
int x = smem[tid * 2]; // 2-way bank conflicts
int y = smem[tid * 4]; // 4-way bank conflicts
int z = smem[tid * 8]; // 8-way bank conflicts
int m = max(max(x,y),z);
out[tid] = m;
}
int main()
{
char* in = (char*) malloc(N*sizeof(char));
for(int i = 0; i < N; i++)
in[i] = i;
char* din, * dout;
hipMalloc((void**) &din, N*sizeof(char));
hipMalloc((void**) &dout, N*sizeof(char));
hipMemcpy(din, in, N*sizeof(char), hipMemcpyHostToDevice);
bc<<<1,N>>>(din,dout);
hipMemcpy(in, dout, N*sizeof(char), hipMemcpyDeviceToHost);
for(int i = 0; i < N; i++)
printf("%d ", in[i]);
printf("\n");
free(in); hipFree(din); hipFree(dout);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z2bcPcS_
.globl _Z2bcPcS_
.p2align 8
.type _Z2bcPcS_,@function
_Z2bcPcS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 3, v0
v_lshlrev_b32_e32 v3, 4, v0
v_lshlrev_b32_e32 v4, 5, v0
s_waitcnt lgkmcnt(0)
global_load_i8 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
ds_store_b32 v2, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
global_load_i8 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
ds_store_b32 v3, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
global_load_i8 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
ds_store_b32 v4, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v2
ds_load_b32 v2, v3
ds_load_b32 v3, v4
s_waitcnt lgkmcnt(0)
v_max3_i32 v1, v1, v2, v3
global_store_b8 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z2bcPcS_
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z2bcPcS_, .Lfunc_end0-_Z2bcPcS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z2bcPcS_
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z2bcPcS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Exhibits a bank conflict.
// Gklee and Gkleep both detect this.
#include <hip/hip_runtime.h>
#include <cstdio>
#define N 32
__global__ void bc(char* in, char* out)
{
__shared__ int smem[512];
int tid = threadIdx.x;
smem[tid*2]=in[tid];
__syncthreads();
smem[tid*4]=in[tid];
__syncthreads();
smem[tid*8]=in[tid];
__syncthreads();
int x = smem[tid * 2]; // 2-way bank conflicts
int y = smem[tid * 4]; // 4-way bank conflicts
int z = smem[tid * 8]; // 8-way bank conflicts
int m = max(max(x,y),z);
out[tid] = m;
}
int main()
{
char* in = (char*) malloc(N*sizeof(char));
for(int i = 0; i < N; i++)
in[i] = i;
char* din, * dout;
hipMalloc((void**) &din, N*sizeof(char));
hipMalloc((void**) &dout, N*sizeof(char));
hipMemcpy(din, in, N*sizeof(char), hipMemcpyHostToDevice);
bc<<<1,N>>>(din,dout);
hipMemcpy(in, dout, N*sizeof(char), hipMemcpyDeviceToHost);
for(int i = 0; i < N; i++)
printf("%d ", in[i]);
printf("\n");
free(in); hipFree(din); hipFree(dout);
} | .text
.file "bank_conflict.hip"
.globl _Z17__device_stub__bcPcS_ # -- Begin function _Z17__device_stub__bcPcS_
.p2align 4, 0x90
.type _Z17__device_stub__bcPcS_,@function
_Z17__device_stub__bcPcS_: # @_Z17__device_stub__bcPcS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z2bcPcS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z17__device_stub__bcPcS_, .Lfunc_end0-_Z17__device_stub__bcPcS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $32, %edi
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movb %al, (%rbx,%rax)
incq %rax
cmpq $32, %rax
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $32, %esi
callq hipMalloc
movq %rsp, %rdi
movl $32, %esi
callq hipMalloc
movq 8(%rsp), %rdi
movl $32, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z2bcPcS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
movl $32, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movsbl (%rbx,%r14), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $32, %r14
jne .LBB1_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2bcPcS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z2bcPcS_,@object # @_Z2bcPcS_
.section .rodata,"a",@progbits
.globl _Z2bcPcS_
.p2align 3, 0x0
_Z2bcPcS_:
.quad _Z17__device_stub__bcPcS_
.size _Z2bcPcS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z2bcPcS_"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z17__device_stub__bcPcS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z2bcPcS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z2bcPcS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ SHF.R.S32.HI R12, RZ, 0x1f, R11 ; /* 0x0000001fff0c7819 */
/* 0x001fe4000001140b */
/*0040*/ IADD3 R2, P0, R11, c[0x0][0x160], RZ ; /* 0x000058000b027a10 */
/* 0x000fc80007f1e0ff */
/*0050*/ IADD3.X R3, R12, c[0x0][0x164], RZ, P0, !PT ; /* 0x000059000c037a10 */
/* 0x000fca00007fe4ff */
/*0060*/ LDG.E.S8 R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1300 */
/*0070*/ STS [R11.X8], R0 ; /* 0x000000000b007388 */
/* 0x004fe80000008800 */
/*0080*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0090*/ LDG.E.S8 R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea8000c1e1300 */
/*00a0*/ STS [R11.X16], R6 ; /* 0x000000060b007388 */
/* 0x004fe8000000c800 */
/*00b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00c0*/ LDG.E.S8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea2000c1e1300 */
/*00d0*/ IMAD.SHL.U32 R8, R11.reuse, 0x20, RZ ; /* 0x000000200b087824 */
/* 0x040fe200078e00ff */
/*00e0*/ IADD3 R4, P0, R11, c[0x0][0x168], RZ ; /* 0x00005a000b047a10 */
/* 0x000fc80007f1e0ff */
/*00f0*/ STS [R8], R7 ; /* 0x0000000708007388 */
/* 0x004fe80000000800 */
/*0100*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0110*/ LDS R5, [R11.X8] ; /* 0x000000000b057984 */
/* 0x000fe80000008800 */
/*0120*/ LDS R10, [R11.X16] ; /* 0x000000000b0a7984 */
/* 0x000e28000000c800 */
/*0130*/ LDS R0, [R8] ; /* 0x0000000008007984 */
/* 0x000e620000000800 */
/*0140*/ IMNMX R9, R5, R10, !PT ; /* 0x0000000a05097217 */
/* 0x001fc40007800200 */
/*0150*/ IADD3.X R5, R12, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b000c057a10 */
/* 0x000fe400007fe4ff */
/*0160*/ IMNMX R9, R0, R9, !PT ; /* 0x0000000900097217 */
/* 0x002fca0007800200 */
/*0170*/ STG.E.U8 [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe2000c101104 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z2bcPcS_
.globl _Z2bcPcS_
.p2align 8
.type _Z2bcPcS_,@function
_Z2bcPcS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 3, v0
v_lshlrev_b32_e32 v3, 4, v0
v_lshlrev_b32_e32 v4, 5, v0
s_waitcnt lgkmcnt(0)
global_load_i8 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
ds_store_b32 v2, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
global_load_i8 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
ds_store_b32 v3, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
global_load_i8 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
ds_store_b32 v4, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v2
ds_load_b32 v2, v3
ds_load_b32 v3, v4
s_waitcnt lgkmcnt(0)
v_max3_i32 v1, v1, v2, v3
global_store_b8 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z2bcPcS_
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z2bcPcS_, .Lfunc_end0-_Z2bcPcS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z2bcPcS_
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z2bcPcS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00135087_00000000-6_bank_conflict.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z2bcPcS_PcS_
.type _Z23__device_stub__Z2bcPcS_PcS_, @function
_Z23__device_stub__Z2bcPcS_PcS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z2bcPcS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z23__device_stub__Z2bcPcS_PcS_, .-_Z23__device_stub__Z2bcPcS_PcS_
.globl _Z2bcPcS_
.type _Z2bcPcS_, @function
_Z2bcPcS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z2bcPcS_PcS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z2bcPcS_, .-_Z2bcPcS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $32, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %eax
.L12:
movb %al, 0(%rbp,%rax)
addq $1, %rax
cmpq $32, %rax
jne .L12
movq %rsp, %rdi
movl $32, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $32, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $32, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq %rbp, %rbx
leaq 32(%rbp), %r13
leaq .LC0(%rip), %r12
.L14:
movsbl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %r13, %rbx
jne .L14
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z23__device_stub__Z2bcPcS_PcS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z2bcPcS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z2bcPcS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "bank_conflict.hip"
.globl _Z17__device_stub__bcPcS_ # -- Begin function _Z17__device_stub__bcPcS_
.p2align 4, 0x90
.type _Z17__device_stub__bcPcS_,@function
_Z17__device_stub__bcPcS_: # @_Z17__device_stub__bcPcS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z2bcPcS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z17__device_stub__bcPcS_, .Lfunc_end0-_Z17__device_stub__bcPcS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $32, %edi
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movb %al, (%rbx,%rax)
incq %rax
cmpq $32, %rax
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $32, %esi
callq hipMalloc
movq %rsp, %rdi
movl $32, %esi
callq hipMalloc
movq 8(%rsp), %rdi
movl $32, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z2bcPcS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
movl $32, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movsbl (%rbx,%r14), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $32, %r14
jne .LBB1_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2bcPcS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z2bcPcS_,@object # @_Z2bcPcS_
.section .rodata,"a",@progbits
.globl _Z2bcPcS_
.p2align 3, 0x0
_Z2bcPcS_:
.quad _Z17__device_stub__bcPcS_
.size _Z2bcPcS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z2bcPcS_"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z17__device_stub__bcPcS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z2bcPcS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void blurKernel(uchar3 *in, uchar3 *out, int w, int h)
{
int Col = blockIdx.x*blockDim.x + threadIdx.x;
int Row = blockIdx.y*blockDim.y + threadIdx.y;
if(Col<w && Row<h)
{
int pixVal1 = 0;
// int pixVal2 = 0;
// int pixVal3 = 0;
int pixels1 = 0;
// int pixels2 = 0;
// int pixels3 = 0;
for(int blurRow=-BLUR_SIZE; blurRow<BLUR_SIZE+1;++blurRow){
for(int blurCol=-BLUR_SIZE; blurCol<BLUR_SIZE+1;++blurCol)
{
int curRow = Row + blurRow;
int curCol = Col + blurCol;
if(curRow>-1 && curRow<h && curCol>-1 && curCol<w){
pixVal1+=static_cast<int>(in[curRow*w + curCol].x);
pixels1++;
pixVal1+=static_cast<int>(in[curRow*w + curCol].y);
pixels1++;
pixVal1+=static_cast<int>(in[curRow*w + curCol].z);
pixels1++;
}
}
}
out[Row*w+Col].x= static_cast<unsigned char>(pixVal1/pixels1);
out[Row*w+Col].y= static_cast<unsigned char>(pixVal1/pixels1);
out[Row*w+Col].z= static_cast<unsigned char>(pixVal1/pixels1);
}
} | code for sm_80
Function : _Z10blurKernelP6uchar3S0_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R5, R5, c[0x0][0x0], R2 ; /* 0x0000000005057a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x170], P0 ; /* 0x00005c0005007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R24, R0, -0x7, RZ ; /* 0xfffffff900187810 */
/* 0x000fe20007ffe0ff */
/*00b0*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fe200078e00ff */
/*00c0*/ IADD3 R4, R5.reuse, -0x7, RZ ; /* 0xfffffff905047810 */
/* 0x040fe20007ffe0ff */
/*00d0*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ; /* 0x000000ffff157224 */
/* 0x000fe200078e00ff */
/*00e0*/ IADD3 R6, R5.reuse, -0x6, RZ ; /* 0xfffffffa05067810 */
/* 0x040fe20007ffe0ff */
/*00f0*/ IMAD.MOV.U32 R22, RZ, RZ, RZ ; /* 0x000000ffff167224 */
/* 0x000fe200078e00ff */
/*0100*/ IADD3 R7, R5.reuse, -0x5, RZ ; /* 0xfffffffb05077810 */
/* 0x040fe20007ffe0ff */
/*0110*/ IMAD R23, R24, c[0x0][0x170], R5 ; /* 0x00005c0018177a24 */
/* 0x000fe200078e0205 */
/*0120*/ IADD3 R8, R5.reuse, -0x4, RZ ; /* 0xfffffffc05087810 */
/* 0x040fe20007ffe0ff */
/*0130*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0140*/ IADD3 R9, R5, -0x3, RZ ; /* 0xfffffffd05097810 */
/* 0x000fc40007ffe0ff */
/*0150*/ IADD3 R10, R5.reuse, -0x2, RZ ; /* 0xfffffffe050a7810 */
/* 0x040fe40007ffe0ff */
/*0160*/ IADD3 R11, R5.reuse, -0x1, RZ ; /* 0xffffffff050b7810 */
/* 0x040fe40007ffe0ff */
/*0170*/ IADD3 R12, R5.reuse, 0x1, RZ ; /* 0x00000001050c7810 */
/* 0x040fe40007ffe0ff */
/*0180*/ IADD3 R13, R5.reuse, 0x2, RZ ; /* 0x00000002050d7810 */
/* 0x040fe40007ffe0ff */
/*0190*/ IADD3 R14, R5.reuse, 0x3, RZ ; /* 0x00000003050e7810 */
/* 0x040fe40007ffe0ff */
/*01a0*/ IADD3 R15, R5, 0x4, RZ ; /* 0x00000004050f7810 */
/* 0x000fc40007ffe0ff */
/*01b0*/ IADD3 R16, R5.reuse, 0x5, RZ ; /* 0x0000000505107810 */
/* 0x040fe40007ffe0ff */
/*01c0*/ IADD3 R17, R5.reuse, 0x6, RZ ; /* 0x0000000605117810 */
/* 0x040fe40007ffe0ff */
/*01d0*/ IADD3 R19, R5, 0x7, RZ ; /* 0x0000000705137810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.GE.AND P0, PT, R24, c[0x0][0x174], PT ; /* 0x00005d0018007a0c */
/* 0x000fe20003f06270 */
/*01f0*/ IMAD.MOV.U32 R20, RZ, RZ, 0x3 ; /* 0x00000003ff147424 */
/* 0x000fe200078e00ff */
/*0200*/ LOP3.LUT R2, R4, R24, RZ, 0xfc, !PT ; /* 0x0000001804027212 */
/* 0x000fe200078efcff */
/*0210*/ IMAD R3, R18, c[0x0][0x170], R23 ; /* 0x00005c0012037a24 */
/* 0x000fc600078e0217 */
/*0220*/ ISETP.LT.OR P2, PT, R2, RZ, P0 ; /* 0x000000ff0200720c */
/* 0x000fe20000741670 */
/*0230*/ IMAD.WIDE R2, R3, R20, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fc600078e0214 */
/*0240*/ ISETP.GE.OR P2, PT, R4, c[0x0][0x170], P2 ; /* 0x00005c0004007a0c */
/* 0x000fda0001746670 */
/*0250*/ @!P2 LDG.E.U8 R25, [R2.64+-0x15] ; /* 0xffffeb040219a981 */
/* 0x000ea8000c1e1100 */
/*0260*/ @!P2 LDG.E.U8 R26, [R2.64+-0x14] ; /* 0xffffec04021aa981 */
/* 0x000ea8000c1e1100 */
/*0270*/ @!P2 LDG.E.U8 R28, [R2.64+-0x13] ; /* 0xffffed04021ca981 */
/* 0x000ee2000c1e1100 */
/*0280*/ @!P2 IADD3 R25, R26, R22, R25 ; /* 0x000000161a19a210 */
/* 0x004fe40007ffe019 */
/*0290*/ LOP3.LUT R26, R6, R24, RZ, 0xfc, !PT ; /* 0x00000018061a7212 */
/* 0x000fc800078efcff */
/*02a0*/ ISETP.LT.OR P6, PT, R26, RZ, P0 ; /* 0x000000ff1a00720c */
/* 0x000fc800007c1670 */
/*02b0*/ ISETP.GE.OR P6, PT, R6, c[0x0][0x170], P6 ; /* 0x00005c0006007a0c */
/* 0x000fda00037c6670 */
/*02c0*/ @!P6 LDG.E.U8 R27, [R2.64+-0x12] ; /* 0xffffee04021be981 */
/* 0x000ea8000c1e1100 */
/*02d0*/ @!P6 LDG.E.U8 R29, [R2.64+-0x11] ; /* 0xffffef04021de981 */
/* 0x000ea8000c1e1100 */
/*02e0*/ @!P6 LDG.E.U8 R26, [R2.64+-0x10] ; /* 0xfffff004021ae981 */
/* 0x000f22000c1e1100 */
/*02f0*/ @!P2 IMAD.IADD R22, R25, 0x1, R28 ; /* 0x000000011916a824 */
/* 0x008fe200078e021c */
/*0300*/ LOP3.LUT R25, R7, R24, RZ, 0xfc, !PT ; /* 0x0000001807197212 */
/* 0x000fc800078efcff */
/*0310*/ ISETP.LT.OR P1, PT, R25, RZ, P0 ; /* 0x000000ff1900720c */
/* 0x000fe40000721670 */
/*0320*/ LOP3.LUT R25, R8, R24, RZ, 0xfc, !PT ; /* 0x0000001808197212 */
/* 0x000fe400078efcff */
/*0330*/ ISETP.GE.OR P1, PT, R7, c[0x0][0x170], P1 ; /* 0x00005c0007007a0c */
/* 0x000fe40000f26670 */
/*0340*/ ISETP.LT.OR P3, PT, R25, RZ, P0 ; /* 0x000000ff1900720c */
/* 0x000fc80000761670 */
/*0350*/ ISETP.GE.OR P3, PT, R8, c[0x0][0x170], P3 ; /* 0x00005c0008007a0c */
/* 0x000fce0001f66670 */
/*0360*/ @!P1 LDG.E.U8 R28, [R2.64+-0xe] ; /* 0xfffff204021c9981 */
/* 0x000eec000c1e1100 */
/*0370*/ @!P3 LDG.E.U8 R25, [R2.64+-0xb] ; /* 0xfffff5040219b981 */
/* 0x000f62000c1e1100 */
/*0380*/ @!P6 IADD3 R27, R29, R22, R27 ; /* 0x000000161d1be210 */
/* 0x004fc60007ffe01b */
/*0390*/ @!P1 LDG.E.U8 R29, [R2.64+-0xf] ; /* 0xfffff104021d9981 */
/* 0x000ee4000c1e1100 */
/*03a0*/ @!P6 IMAD.IADD R22, R27, 0x1, R26 ; /* 0x000000011b16e824 */
/* 0x010fe400078e021a */
/*03b0*/ @!P1 LDG.E.U8 R27, [R2.64+-0xd] ; /* 0xfffff304021b9981 */
/* 0x000ea8000c1e1100 */
/*03c0*/ @!P3 LDG.E.U8 R26, [R2.64+-0xc] ; /* 0xfffff404021ab981 */
/* 0x000f62000c1e1100 */
/*03d0*/ @!P1 IADD3 R28, R28, R22, R29 ; /* 0x000000161c1c9210 */
/* 0x008fca0007ffe01d */
/*03e0*/ @!P1 IMAD.IADD R22, R28, 0x1, R27 ; /* 0x000000011c169824 */
/* 0x004fe400078e021b */
/*03f0*/ @!P3 LDG.E.U8 R28, [R2.64+-0xa] ; /* 0xfffff604021cb981 */
/* 0x000ea6000c1e1100 */
/*0400*/ @!P3 IADD3 R25, R25, R22, R26 ; /* 0x000000161919b210 */
/* 0x020fe40007ffe01a */
/*0410*/ LOP3.LUT R26, R9, R24, RZ, 0xfc, !PT ; /* 0x00000018091a7212 */
/* 0x000fc800078efcff */
/*0420*/ ISETP.LT.OR P5, PT, R26, RZ, P0 ; /* 0x000000ff1a00720c */
/* 0x000fc800007a1670 */
/*0430*/ ISETP.GE.OR P5, PT, R9, c[0x0][0x170], P5 ; /* 0x00005c0009007a0c */
/* 0x000fda0002fa6670 */
/*0440*/ @!P5 LDG.E.U8 R27, [R2.64+-0x9] ; /* 0xfffff704021bd981 */
/* 0x000ee8000c1e1100 */
/*0450*/ @!P5 LDG.E.U8 R29, [R2.64+-0x8] ; /* 0xfffff804021dd981 */
/* 0x000ee8000c1e1100 */
/*0460*/ @!P5 LDG.E.U8 R26, [R2.64+-0x7] ; /* 0xfffff904021ad981 */
/* 0x000f22000c1e1100 */
/*0470*/ @!P2 IADD3 R21, R21, 0x3, RZ ; /* 0x000000031515a810 */
/* 0x000fe20007ffe0ff */
/*0480*/ @!P3 IMAD.IADD R22, R25, 0x1, R28 ; /* 0x000000011916b824 */
/* 0x004fe200078e021c */
/*0490*/ LOP3.LUT R25, R10, R24, RZ, 0xfc, !PT ; /* 0x000000180a197212 */
/* 0x000fc800078efcff */
/*04a0*/ ISETP.LT.OR P4, PT, R25, RZ, P0 ; /* 0x000000ff1900720c */
/* 0x000fe40000781670 */
/*04b0*/ LOP3.LUT R25, R11, R24, RZ, 0xfc, !PT ; /* 0x000000180b197212 */
/* 0x000fe400078efcff */
/*04c0*/ ISETP.GE.OR P4, PT, R10, c[0x0][0x170], P4 ; /* 0x00005c000a007a0c */
/* 0x000fe40002786670 */
/*04d0*/ ISETP.LT.OR P2, PT, R25, RZ, P0 ; /* 0x000000ff1900720c */
/* 0x000fc80000741670 */
/*04e0*/ ISETP.GT.OR P2, PT, R5, c[0x0][0x170], P2 ; /* 0x00005c0005007a0c */
/* 0x000fce0001744670 */
/*04f0*/ @!P4 LDG.E.U8 R28, [R2.64+-0x5] ; /* 0xfffffb04021cc981 */
/* 0x000eac000c1e1100 */
/*0500*/ @!P2 LDG.E.U8 R25, [R2.64+-0x2] ; /* 0xfffffe040219a981 */
/* 0x000f62000c1e1100 */
/*0510*/ @!P5 IADD3 R27, R29, R22, R27 ; /* 0x000000161d1bd210 */
/* 0x008fc60007ffe01b */
/*0520*/ @!P4 LDG.E.U8 R29, [R2.64+-0x6] ; /* 0xfffffa04021dc981 */
/* 0x000ea4000c1e1100 */
/*0530*/ @!P5 IMAD.IADD R22, R27, 0x1, R26 ; /* 0x000000011b16d824 */
/* 0x010fe400078e021a */
/*0540*/ @!P4 LDG.E.U8 R27, [R2.64+-0x4] ; /* 0xfffffc04021bc981 */
/* 0x000ee8000c1e1100 */
/*0550*/ @!P2 LDG.E.U8 R26, [R2.64+-0x3] ; /* 0xfffffd04021aa981 */
/* 0x000f62000c1e1100 */
/*0560*/ @!P6 IADD3 R21, R21, 0x3, RZ ; /* 0x000000031515e810 */
/* 0x000fe40007ffe0ff */
/*0570*/ @!P4 IADD3 R28, R28, R22, R29 ; /* 0x000000161c1cc210 */
/* 0x004fca0007ffe01d */
/*0580*/ @!P4 IMAD.IADD R22, R28, 0x1, R27 ; /* 0x000000011c16c824 */
/* 0x008fe400078e021b */
/*0590*/ @!P2 LDG.E.U8 R28, [R2.64+-0x1] ; /* 0xffffff04021ca981 */
/* 0x000ea6000c1e1100 */
/*05a0*/ @!P2 IADD3 R25, R25, R22, R26 ; /* 0x000000161919a210 */
/* 0x020fe40007ffe01a */
/*05b0*/ LOP3.LUT R26, R5, R24, RZ, 0xfc, !PT ; /* 0x00000018051a7212 */
/* 0x000fc800078efcff */
/*05c0*/ ISETP.LT.OR P6, PT, R26, RZ, P0 ; /* 0x000000ff1a00720c */
/* 0x000fda00007c1670 */
/*05d0*/ @!P6 LDG.E.U8 R27, [R2.64] ; /* 0x00000004021be981 */
/* 0x000ee8000c1e1100 */
/*05e0*/ @!P6 LDG.E.U8 R29, [R2.64+0x1] ; /* 0x00000104021de981 */
/* 0x000ee8000c1e1100 */
/*05f0*/ @!P6 LDG.E.U8 R26, [R2.64+0x2] ; /* 0x00000204021ae981 */
/* 0x000f22000c1e1100 */
/*0600*/ @!P1 IADD3 R21, R21, 0x3, RZ ; /* 0x0000000315159810 */
/* 0x000fc80007ffe0ff */
/*0610*/ @!P3 IADD3 R21, R21, 0x3, RZ ; /* 0x000000031515b810 */
/* 0x000fe20007ffe0ff */
/*0620*/ @!P2 IMAD.IADD R22, R25, 0x1, R28 ; /* 0x000000011916a824 */
/* 0x004fe200078e021c */
/*0630*/ LOP3.LUT R25, R12, R24, RZ, 0xfc, !PT ; /* 0x000000180c197212 */
/* 0x000fc800078efcff */
/*0640*/ ISETP.LT.OR P1, PT, R25, RZ, P0 ; /* 0x000000ff1900720c */
/* 0x000fe40000721670 */
/*0650*/ LOP3.LUT R25, R13, R24, RZ, 0xfc, !PT ; /* 0x000000180d197212 */
/* 0x000fe400078efcff */
/*0660*/ ISETP.GE.OR P1, PT, R12, c[0x0][0x170], P1 ; /* 0x00005c000c007a0c */
/* 0x000fe40000f26670 */
/*0670*/ ISETP.LT.OR P3, PT, R25, RZ, P0 ; /* 0x000000ff1900720c */
/* 0x000fc80000761670 */
/*0680*/ ISETP.GE.OR P3, PT, R13, c[0x0][0x170], P3 ; /* 0x00005c000d007a0c */
/* 0x000fce0001f66670 */
/*0690*/ @!P1 LDG.E.U8 R28, [R2.64+0x4] ; /* 0x00000404021c9981 */
/* 0x000ea2000c1e1100 */
/*06a0*/ @!P6 IADD3 R27, R29, R22, R27 ; /* 0x000000161d1be210 */
/* 0x008fc60007ffe01b */
/*06b0*/ @!P1 LDG.E.U8 R29, [R2.64+0x3] ; /* 0x00000304021d9981 */
/* 0x000ea4000c1e1100 */
/*06c0*/ @!P6 IMAD.IADD R22, R27, 0x1, R26 ; /* 0x000000011b16e824 */
/* 0x010fe400078e021a */
/*06d0*/ @!P3 LDG.E.U8 R25, [R2.64+0x7] ; /* 0x000007040219b981 */
/* 0x000ee8000c1e1100 */
/*06e0*/ @!P1 LDG.E.U8 R27, [R2.64+0x5] ; /* 0x00000504021b9981 */
/* 0x000f28000c1e1100 */
/*06f0*/ @!P3 LDG.E.U8 R26, [R2.64+0x6] ; /* 0x00000604021ab981 */
/* 0x000ee2000c1e1100 */
/*0700*/ @!P5 IADD3 R21, R21, 0x3, RZ ; /* 0x000000031515d810 */
/* 0x000fc40007ffe0ff */
/*0710*/ @!P1 IADD3 R28, R28, R22, R29 ; /* 0x000000161c1c9210 */
/* 0x004fca0007ffe01d */
/*0720*/ @!P1 IMAD.IADD R22, R28, 0x1, R27 ; /* 0x000000011c169824 */
/* 0x010fe400078e021b */
/*0730*/ @!P3 LDG.E.U8 R28, [R2.64+0x8] ; /* 0x00000804021cb981 */
/* 0x000ea6000c1e1100 */
/*0740*/ @!P3 IADD3 R25, R25, R22, R26 ; /* 0x000000161919b210 */
/* 0x008fe40007ffe01a */
/*0750*/ LOP3.LUT R26, R14, R24, RZ, 0xfc, !PT ; /* 0x000000180e1a7212 */
/* 0x000fc800078efcff */
/*0760*/ ISETP.LT.OR P5, PT, R26, RZ, P0 ; /* 0x000000ff1a00720c */
/* 0x000fc800007a1670 */
/*0770*/ ISETP.GE.OR P5, PT, R14, c[0x0][0x170], P5 ; /* 0x00005c000e007a0c */
/* 0x000fda0002fa6670 */
/*0780*/ @!P5 LDG.E.U8 R27, [R2.64+0x9] ; /* 0x00000904021bd981 */
/* 0x000ee8000c1e1100 */
/*0790*/ @!P5 LDG.E.U8 R29, [R2.64+0xa] ; /* 0x00000a04021dd981 */
/* 0x000ee8000c1e1100 */
/*07a0*/ @!P5 LDG.E.U8 R26, [R2.64+0xb] ; /* 0x00000b04021ad981 */
/* 0x000f22000c1e1100 */
/*07b0*/ @!P4 IADD3 R21, R21, 0x3, RZ ; /* 0x000000031515c810 */
/* 0x000fc80007ffe0ff */
/*07c0*/ @!P2 IADD3 R21, R21, 0x3, RZ ; /* 0x000000031515a810 */
/* 0x000fe20007ffe0ff */
/*07d0*/ @!P3 IMAD.IADD R22, R25, 0x1, R28 ; /* 0x000000011916b824 */
/* 0x004fe200078e021c */
/*07e0*/ LOP3.LUT R25, R15, R24, RZ, 0xfc, !PT ; /* 0x000000180f197212 */
/* 0x000fc800078efcff */
/*07f0*/ ISETP.LT.OR P4, PT, R25, RZ, P0 ; /* 0x000000ff1900720c */
/* 0x000fe40000781670 */
/*0800*/ LOP3.LUT R25, R16, R24, RZ, 0xfc, !PT ; /* 0x0000001810197212 */
/* 0x000fe400078efcff */
/*0810*/ ISETP.GE.OR P4, PT, R15, c[0x0][0x170], P4 ; /* 0x00005c000f007a0c */
/* 0x000fe40002786670 */
/*0820*/ ISETP.LT.OR P2, PT, R25, RZ, P0 ; /* 0x000000ff1900720c */
/* 0x000fc80000741670 */
/*0830*/ ISETP.GE.OR P2, PT, R16, c[0x0][0x170], P2 ; /* 0x00005c0010007a0c */
/* 0x000fce0001746670 */
/*0840*/ @!P4 LDG.E.U8 R28, [R2.64+0xd] ; /* 0x00000d04021cc981 */
/* 0x000eac000c1e1100 */
/*0850*/ @!P2 LDG.E.U8 R25, [R2.64+0x10] ; /* 0x000010040219a981 */
/* 0x000f62000c1e1100 */
/*0860*/ @!P5 IADD3 R27, R29, R22, R27 ; /* 0x000000161d1bd210 */
/* 0x008fc60007ffe01b */
/*0870*/ @!P4 LDG.E.U8 R29, [R2.64+0xc] ; /* 0x00000c04021dc981 */
/* 0x000ea4000c1e1100 */
/*0880*/ @!P5 IMAD.IADD R22, R27, 0x1, R26 ; /* 0x000000011b16d824 */
/* 0x010fe400078e021a */
/*0890*/ @!P4 LDG.E.U8 R27, [R2.64+0xe] ; /* 0x00000e04021bc981 */
/* 0x000ee8000c1e1100 */
/*08a0*/ @!P2 LDG.E.U8 R26, [R2.64+0xf] ; /* 0x00000f04021aa981 */
/* 0x000f62000c1e1100 */
/*08b0*/ @!P6 IADD3 R21, R21, 0x3, RZ ; /* 0x000000031515e810 */
/* 0x000fe40007ffe0ff */
/*08c0*/ @!P4 IADD3 R28, R28, R22, R29 ; /* 0x000000161c1cc210 */
/* 0x004fca0007ffe01d */
/*08d0*/ @!P4 IMAD.IADD R22, R28, 0x1, R27 ; /* 0x000000011c16c824 */
/* 0x008fe400078e021b */
/*08e0*/ @!P2 LDG.E.U8 R28, [R2.64+0x11] ; /* 0x00001104021ca981 */
/* 0x000ea6000c1e1100 */
/*08f0*/ @!P2 IADD3 R25, R25, R22, R26 ; /* 0x000000161919a210 */
/* 0x020fe40007ffe01a */
/*0900*/ LOP3.LUT R26, R17, R24, RZ, 0xfc, !PT ; /* 0x00000018111a7212 */
/* 0x000fc800078efcff */
/*0910*/ ISETP.LT.OR P6, PT, R26, RZ, P0 ; /* 0x000000ff1a00720c */
/* 0x000fc800007c1670 */
/*0920*/ ISETP.GE.OR P6, PT, R17, c[0x0][0x170], P6 ; /* 0x00005c0011007a0c */
/* 0x000fda00037c6670 */
/*0930*/ @!P6 LDG.E.U8 R27, [R2.64+0x12] ; /* 0x00001204021be981 */
/* 0x000ee8000c1e1100 */
/*0940*/ @!P6 LDG.E.U8 R29, [R2.64+0x13] ; /* 0x00001304021de981 */
/* 0x000ee8000c1e1100 */
/*0950*/ @!P6 LDG.E.U8 R26, [R2.64+0x14] ; /* 0x00001404021ae981 */
/* 0x000f22000c1e1100 */
/*0960*/ @!P2 IMAD.IADD R22, R25, 0x1, R28 ; /* 0x000000011916a824 */
/* 0x004fe200078e021c */
/*0970*/ LOP3.LUT R25, R19, R24, RZ, 0xfc, !PT ; /* 0x0000001813197212 */
/* 0x000fc800078efcff */
/*0980*/ ISETP.LT.OR P0, PT, R25, RZ, P0 ; /* 0x000000ff1900720c */
/* 0x000fc80000701670 */
/*0990*/ ISETP.GE.OR P0, PT, R19, c[0x0][0x170], P0 ; /* 0x00005c0013007a0c */
/* 0x000fda0000706670 */
/*09a0*/ @!P0 LDG.E.U8 R25, [R2.64+0x15] ; /* 0x0000150402198981 */
/* 0x000ea8000c1e1100 */
/*09b0*/ @!P0 LDG.E.U8 R28, [R2.64+0x17] ; /* 0x00001704021c8981 */
/* 0x000f62000c1e1100 */
/*09c0*/ @!P6 IADD3 R27, R29, R22, R27 ; /* 0x000000161d1be210 */
/* 0x008fca0007ffe01b */
/*09d0*/ @!P6 IMAD.IADD R22, R27, 0x1, R26 ; /* 0x000000011b16e824 */
/* 0x010fe400078e021a */
/*09e0*/ @!P0 LDG.E.U8 R26, [R2.64+0x16] ; /* 0x00001604021a8981 */
/* 0x000ea2000c1e1100 */
/*09f0*/ @!P1 IADD3 R21, R21, 0x3, RZ ; /* 0x0000000315159810 */
/* 0x000fc80007ffe0ff */
/*0a00*/ @!P3 IADD3 R21, R21, 0x3, RZ ; /* 0x000000031515b810 */
/* 0x000fe40007ffe0ff */
/*0a10*/ ISETP.NE.AND P1, PT, R18, 0xe, PT ; /* 0x0000000e1200780c */
/* 0x000fe40003f25270 */
/*0a20*/ @!P5 IADD3 R21, R21, 0x3, RZ ; /* 0x000000031515d810 */
/* 0x000fc80007ffe0ff */
/*0a30*/ @!P4 IADD3 R21, R21, 0x3, RZ ; /* 0x000000031515c810 */
/* 0x000fc80007ffe0ff */
/*0a40*/ @!P2 IADD3 R21, R21, 0x3, RZ ; /* 0x000000031515a810 */
/* 0x000fc80007ffe0ff */
/*0a50*/ @!P6 IADD3 R21, R21, 0x3, RZ ; /* 0x000000031515e810 */
/* 0x000fe40007ffe0ff */
/*0a60*/ IADD3 R24, R24, 0x1, RZ ; /* 0x0000000118187810 */
/* 0x000fe40007ffe0ff */
/*0a70*/ IADD3 R18, R18, 0x1, RZ ; /* 0x0000000112127810 */
/* 0x000fe40007ffe0ff */
/*0a80*/ @!P0 IADD3 R21, R21, 0x3, RZ ; /* 0x0000000315158810 */
/* 0x000fe40007ffe0ff */
/*0a90*/ @!P0 IADD3 R25, R26, R22, R25 ; /* 0x000000161a198210 */
/* 0x004fca0007ffe019 */
/*0aa0*/ @!P0 IMAD.IADD R22, R25, 0x1, R28 ; /* 0x0000000119168824 */
/* 0x020fe200078e021c */
/*0ab0*/ @P1 BRA 0x1e0 ; /* 0xfffff72000001947 */
/* 0x000fea000383ffff */
/*0ac0*/ IABS R7, R21.reuse ; /* 0x0000001500077213 */
/* 0x080fe40000000000 */
/*0ad0*/ IABS R8, R22 ; /* 0x0000001600087213 */
/* 0x000fe40000000000 */
/*0ae0*/ I2F.RP R4, R7 ; /* 0x0000000700047306 */
/* 0x000e220000209400 */
/*0af0*/ IABS R10, R21.reuse ; /* 0x00000015000a7213 */
/* 0x080fe40000000000 */
/*0b00*/ LOP3.LUT R22, R22, R21, RZ, 0x3c, !PT ; /* 0x0000001516167212 */
/* 0x000fc800078e3cff */
/*0b10*/ ISETP.GE.AND P2, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fe20003f46270 */
/*0b20*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0b30*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fe20007ffe0ff */
/*0b40*/ IMAD.MOV R4, RZ, RZ, -R10 ; /* 0x000000ffff047224 */
/* 0x000fca00078e0a0a */
/*0b50*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0b60*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0b70*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*0b80*/ IMAD R9, R6, R7, RZ ; /* 0x0000000706097224 */
/* 0x000fe400078e02ff */
/*0b90*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0008 */
/*0ba0*/ IMAD.HI.U32 R3, R3, R9, R2 ; /* 0x0000000903037227 */
/* 0x000fcc00078e0002 */
/*0bb0*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fc800078e00ff */
/*0bc0*/ IMAD R2, R3, R4, R6 ; /* 0x0000000403027224 */
/* 0x000fca00078e0206 */
/*0bd0*/ ISETP.GT.U32.AND P1, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fda0003f24070 */
/*0be0*/ @!P1 IMAD.IADD R2, R2, 0x1, -R7 ; /* 0x0000000102029824 */
/* 0x000fe200078e0a07 */
/*0bf0*/ @!P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103039810 */
/* 0x000fe40007ffe0ff */
/*0c00*/ ISETP.NE.AND P1, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fe40003f25270 */
/*0c10*/ ISETP.GE.U32.AND P0, PT, R2, R7, PT ; /* 0x000000070200720c */
/* 0x000fda0003f06070 */
/*0c20*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*0c30*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0003 */
/*0c40*/ IMAD R3, R0, c[0x0][0x170], R5 ; /* 0x00005c0000037a24 */
/* 0x000fe400078e0205 */
/*0c50*/ @!P2 IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff07a224 */
/* 0x000fe200078e0a07 */
/*0c60*/ @!P1 LOP3.LUT R7, RZ, R21, RZ, 0x33, !PT ; /* 0x00000015ff079212 */
/* 0x000fe200078e33ff */
/*0c70*/ IMAD.WIDE R2, R3, R20, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0214 */
/*0c80*/ STG.E.U8 [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101104 */
/*0c90*/ STG.E.U8 [R2.64+0x1], R7 ; /* 0x0000010702007986 */
/* 0x000fe8000c101104 */
/*0ca0*/ STG.E.U8 [R2.64+0x2], R7 ; /* 0x0000020702007986 */
/* 0x000fe2000c101104 */
/*0cb0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0cc0*/ BRA 0xcc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void blurKernel(uchar3 *in, uchar3 *out, int w, int h)
{
int Col = blockIdx.x*blockDim.x + threadIdx.x;
int Row = blockIdx.y*blockDim.y + threadIdx.y;
if(Col<w && Row<h)
{
int pixVal1 = 0;
// int pixVal2 = 0;
// int pixVal3 = 0;
int pixels1 = 0;
// int pixels2 = 0;
// int pixels3 = 0;
for(int blurRow=-BLUR_SIZE; blurRow<BLUR_SIZE+1;++blurRow){
for(int blurCol=-BLUR_SIZE; blurCol<BLUR_SIZE+1;++blurCol)
{
int curRow = Row + blurRow;
int curCol = Col + blurCol;
if(curRow>-1 && curRow<h && curCol>-1 && curCol<w){
pixVal1+=static_cast<int>(in[curRow*w + curCol].x);
pixels1++;
pixVal1+=static_cast<int>(in[curRow*w + curCol].y);
pixels1++;
pixVal1+=static_cast<int>(in[curRow*w + curCol].z);
pixels1++;
}
}
}
out[Row*w+Col].x= static_cast<unsigned char>(pixVal1/pixels1);
out[Row*w+Col].y= static_cast<unsigned char>(pixVal1/pixels1);
out[Row*w+Col].z= static_cast<unsigned char>(pixVal1/pixels1);
}
} | .file "tmpxft_000adf06_00000000-6_blurKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z10blurKernelP6uchar3S0_iiP6uchar3S0_ii
.type _Z41__device_stub__Z10blurKernelP6uchar3S0_iiP6uchar3S0_ii, @function
_Z41__device_stub__Z10blurKernelP6uchar3S0_iiP6uchar3S0_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10blurKernelP6uchar3S0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z10blurKernelP6uchar3S0_iiP6uchar3S0_ii, .-_Z41__device_stub__Z10blurKernelP6uchar3S0_iiP6uchar3S0_ii
.globl _Z10blurKernelP6uchar3S0_ii
.type _Z10blurKernelP6uchar3S0_ii, @function
_Z10blurKernelP6uchar3S0_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z10blurKernelP6uchar3S0_iiP6uchar3S0_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10blurKernelP6uchar3S0_ii, .-_Z10blurKernelP6uchar3S0_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10blurKernelP6uchar3S0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10blurKernelP6uchar3S0_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void blurKernel(uchar3 *in, uchar3 *out, int w, int h)
{
int Col = blockIdx.x*blockDim.x + threadIdx.x;
int Row = blockIdx.y*blockDim.y + threadIdx.y;
if(Col<w && Row<h)
{
int pixVal1 = 0;
// int pixVal2 = 0;
// int pixVal3 = 0;
int pixels1 = 0;
// int pixels2 = 0;
// int pixels3 = 0;
for(int blurRow=-BLUR_SIZE; blurRow<BLUR_SIZE+1;++blurRow){
for(int blurCol=-BLUR_SIZE; blurCol<BLUR_SIZE+1;++blurCol)
{
int curRow = Row + blurRow;
int curCol = Col + blurCol;
if(curRow>-1 && curRow<h && curCol>-1 && curCol<w){
pixVal1+=static_cast<int>(in[curRow*w + curCol].x);
pixels1++;
pixVal1+=static_cast<int>(in[curRow*w + curCol].y);
pixels1++;
pixVal1+=static_cast<int>(in[curRow*w + curCol].z);
pixels1++;
}
}
}
out[Row*w+Col].x= static_cast<unsigned char>(pixVal1/pixels1);
out[Row*w+Col].y= static_cast<unsigned char>(pixVal1/pixels1);
out[Row*w+Col].z= static_cast<unsigned char>(pixVal1/pixels1);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void blurKernel(uchar3 *in, uchar3 *out, int w, int h)
{
int Col = blockIdx.x*blockDim.x + threadIdx.x;
int Row = blockIdx.y*blockDim.y + threadIdx.y;
if(Col<w && Row<h)
{
int pixVal1 = 0;
// int pixVal2 = 0;
// int pixVal3 = 0;
int pixels1 = 0;
// int pixels2 = 0;
// int pixels3 = 0;
for(int blurRow=-BLUR_SIZE; blurRow<BLUR_SIZE+1;++blurRow){
for(int blurCol=-BLUR_SIZE; blurCol<BLUR_SIZE+1;++blurCol)
{
int curRow = Row + blurRow;
int curCol = Col + blurCol;
if(curRow>-1 && curRow<h && curCol>-1 && curCol<w){
pixVal1+=static_cast<int>(in[curRow*w + curCol].x);
pixels1++;
pixVal1+=static_cast<int>(in[curRow*w + curCol].y);
pixels1++;
pixVal1+=static_cast<int>(in[curRow*w + curCol].z);
pixels1++;
}
}
}
out[Row*w+Col].x= static_cast<unsigned char>(pixVal1/pixels1);
out[Row*w+Col].y= static_cast<unsigned char>(pixVal1/pixels1);
out[Row*w+Col].z= static_cast<unsigned char>(pixVal1/pixels1);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void blurKernel(uchar3 *in, uchar3 *out, int w, int h)
{
int Col = blockIdx.x*blockDim.x + threadIdx.x;
int Row = blockIdx.y*blockDim.y + threadIdx.y;
if(Col<w && Row<h)
{
int pixVal1 = 0;
// int pixVal2 = 0;
// int pixVal3 = 0;
int pixels1 = 0;
// int pixels2 = 0;
// int pixels3 = 0;
for(int blurRow=-BLUR_SIZE; blurRow<BLUR_SIZE+1;++blurRow){
for(int blurCol=-BLUR_SIZE; blurCol<BLUR_SIZE+1;++blurCol)
{
int curRow = Row + blurRow;
int curCol = Col + blurCol;
if(curRow>-1 && curRow<h && curCol>-1 && curCol<w){
pixVal1+=static_cast<int>(in[curRow*w + curCol].x);
pixels1++;
pixVal1+=static_cast<int>(in[curRow*w + curCol].y);
pixels1++;
pixVal1+=static_cast<int>(in[curRow*w + curCol].z);
pixels1++;
}
}
}
out[Row*w+Col].x= static_cast<unsigned char>(pixVal1/pixels1);
out[Row*w+Col].y= static_cast<unsigned char>(pixVal1/pixels1);
out[Row*w+Col].z= static_cast<unsigned char>(pixVal1/pixels1);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10blurKernelP15HIP_vector_typeIhLj3EES1_ii
.globl _Z10blurKernelP15HIP_vector_typeIhLj3EES1_ii
.p2align 8
.type _Z10blurKernelP15HIP_vector_typeIhLj3EES1_ii,@function
_Z10blurKernelP15HIP_vector_typeIhLj3EES1_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[6:7], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_mul_i32 s14, s14, s3
s_mul_i32 s15, s15, s2
v_add_nc_u32_e32 v0, s14, v2
v_add_nc_u32_e32 v1, s15, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s6, v0
v_cmp_gt_i32_e64 s2, s7, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_10
s_load_b64 s[8:9], s[0:1], 0x0
v_add3_u32 v3, v3, s15, -7
v_add3_u32 v5, v2, s14, -7
v_mov_b32_e32 v2, 0
s_mov_b32 s5, -7
s_delay_alu instid0(VALU_DEP_3)
v_mul_lo_u32 v4, s6, v3
v_mov_b32_e32 v3, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v4, s6, v4
s_add_i32 s5, s5, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s5, 8
s_cbranch_scc1 .LBB0_9
.LBB0_3:
v_add_nc_u32_e32 v6, s5, v1
s_mov_b32 s10, 15
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v6
v_cmp_gt_i32_e64 s2, s7, v6
v_mov_b32_e32 v6, v5
s_branch .LBB0_6
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s3
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s11
v_add_nc_u32_e32 v6, 1, v6
s_add_i32 s10, s10, -1
s_cmp_eq_u32 s10, 0
s_cbranch_scc1 .LBB0_2
.LBB0_6:
s_and_saveexec_b32 s11, vcc_lo
s_cbranch_execz .LBB0_5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_lt_i32_e64 s3, -1, v6
v_cmp_gt_i32_e64 s4, s6, v6
s_and_b32 s3, s2, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s4, s3, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s4
s_cbranch_execz .LBB0_4
v_add_nc_u32_e32 v9, v4, v6
v_add_nc_u32_e32 v3, 3, v3
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_mad_i64_i32 v[7:8], null, v9, 3, s[8:9]
s_clause 0x2
global_load_u8 v9, v[7:8], off
global_load_u8 v10, v[7:8], off offset:1
global_load_u8 v7, v[7:8], off offset:2
s_waitcnt vmcnt(2)
v_add_nc_u32_e32 v2, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v2, v2, v10, v7
s_branch .LBB0_4
.LBB0_9:
s_set_inst_prefetch_distance 0x2
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v7, 31, v2
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, v3, v4
v_add_nc_u32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v5, v3, v4
v_xor_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cvt_f32_u32_e32 v3, v5
v_sub_nc_u32_e32 v6, 0, v5
v_rcp_iflag_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v3, v3
v_mul_lo_u32 v6, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v6, v3, v6
v_add_nc_u32_e32 v3, v3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v2, v3
v_mul_lo_u32 v6, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v2, v6
v_add_nc_u32_e32 v6, 1, v3
v_sub_nc_u32_e32 v8, v2, v5
v_cmp_ge_u32_e32 vcc_lo, v2, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v8, v2, v8, vcc_lo
v_cndmask_b32_e32 v6, v3, v6, vcc_lo
v_mad_u64_u32 v[2:3], null, v1, s6, v[0:1]
v_xor_b32_e32 v3, v7, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_ge_u32_e32 vcc_lo, v8, v5
v_add_nc_u32_e32 v9, 1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v6, v9, vcc_lo
v_xor_b32_e32 v4, v0, v3
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[0:1], null, v2, 3, s[0:1]
s_delay_alu instid0(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v4, v3
s_clause 0x2
global_store_b8 v[0:1], v2, off
global_store_b8 v[0:1], v2, off offset:1
global_store_b8 v[0:1], v2, off offset:2
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10blurKernelP15HIP_vector_typeIhLj3EES1_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10blurKernelP15HIP_vector_typeIhLj3EES1_ii, .Lfunc_end0-_Z10blurKernelP15HIP_vector_typeIhLj3EES1_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10blurKernelP15HIP_vector_typeIhLj3EES1_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10blurKernelP15HIP_vector_typeIhLj3EES1_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void blurKernel(uchar3 *in, uchar3 *out, int w, int h)
{
int Col = blockIdx.x*blockDim.x + threadIdx.x;
int Row = blockIdx.y*blockDim.y + threadIdx.y;
if(Col<w && Row<h)
{
int pixVal1 = 0;
// int pixVal2 = 0;
// int pixVal3 = 0;
int pixels1 = 0;
// int pixels2 = 0;
// int pixels3 = 0;
for(int blurRow=-BLUR_SIZE; blurRow<BLUR_SIZE+1;++blurRow){
for(int blurCol=-BLUR_SIZE; blurCol<BLUR_SIZE+1;++blurCol)
{
int curRow = Row + blurRow;
int curCol = Col + blurCol;
if(curRow>-1 && curRow<h && curCol>-1 && curCol<w){
pixVal1+=static_cast<int>(in[curRow*w + curCol].x);
pixels1++;
pixVal1+=static_cast<int>(in[curRow*w + curCol].y);
pixels1++;
pixVal1+=static_cast<int>(in[curRow*w + curCol].z);
pixels1++;
}
}
}
out[Row*w+Col].x= static_cast<unsigned char>(pixVal1/pixels1);
out[Row*w+Col].y= static_cast<unsigned char>(pixVal1/pixels1);
out[Row*w+Col].z= static_cast<unsigned char>(pixVal1/pixels1);
}
} | .text
.file "blurKernel.hip"
.globl _Z25__device_stub__blurKernelP15HIP_vector_typeIhLj3EES1_ii # -- Begin function _Z25__device_stub__blurKernelP15HIP_vector_typeIhLj3EES1_ii
.p2align 4, 0x90
.type _Z25__device_stub__blurKernelP15HIP_vector_typeIhLj3EES1_ii,@function
_Z25__device_stub__blurKernelP15HIP_vector_typeIhLj3EES1_ii: # @_Z25__device_stub__blurKernelP15HIP_vector_typeIhLj3EES1_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10blurKernelP15HIP_vector_typeIhLj3EES1_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__blurKernelP15HIP_vector_typeIhLj3EES1_ii, .Lfunc_end0-_Z25__device_stub__blurKernelP15HIP_vector_typeIhLj3EES1_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10blurKernelP15HIP_vector_typeIhLj3EES1_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10blurKernelP15HIP_vector_typeIhLj3EES1_ii,@object # @_Z10blurKernelP15HIP_vector_typeIhLj3EES1_ii
.section .rodata,"a",@progbits
.globl _Z10blurKernelP15HIP_vector_typeIhLj3EES1_ii
.p2align 3, 0x0
_Z10blurKernelP15HIP_vector_typeIhLj3EES1_ii:
.quad _Z25__device_stub__blurKernelP15HIP_vector_typeIhLj3EES1_ii
.size _Z10blurKernelP15HIP_vector_typeIhLj3EES1_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10blurKernelP15HIP_vector_typeIhLj3EES1_ii"
.size .L__unnamed_1, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__blurKernelP15HIP_vector_typeIhLj3EES1_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10blurKernelP15HIP_vector_typeIhLj3EES1_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10blurKernelP6uchar3S0_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R5, R5, c[0x0][0x0], R2 ; /* 0x0000000005057a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x170], P0 ; /* 0x00005c0005007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R24, R0, -0x7, RZ ; /* 0xfffffff900187810 */
/* 0x000fe20007ffe0ff */
/*00b0*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fe200078e00ff */
/*00c0*/ IADD3 R4, R5.reuse, -0x7, RZ ; /* 0xfffffff905047810 */
/* 0x040fe20007ffe0ff */
/*00d0*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ; /* 0x000000ffff157224 */
/* 0x000fe200078e00ff */
/*00e0*/ IADD3 R6, R5.reuse, -0x6, RZ ; /* 0xfffffffa05067810 */
/* 0x040fe20007ffe0ff */
/*00f0*/ IMAD.MOV.U32 R22, RZ, RZ, RZ ; /* 0x000000ffff167224 */
/* 0x000fe200078e00ff */
/*0100*/ IADD3 R7, R5.reuse, -0x5, RZ ; /* 0xfffffffb05077810 */
/* 0x040fe20007ffe0ff */
/*0110*/ IMAD R23, R24, c[0x0][0x170], R5 ; /* 0x00005c0018177a24 */
/* 0x000fe200078e0205 */
/*0120*/ IADD3 R8, R5.reuse, -0x4, RZ ; /* 0xfffffffc05087810 */
/* 0x040fe20007ffe0ff */
/*0130*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0140*/ IADD3 R9, R5, -0x3, RZ ; /* 0xfffffffd05097810 */
/* 0x000fc40007ffe0ff */
/*0150*/ IADD3 R10, R5.reuse, -0x2, RZ ; /* 0xfffffffe050a7810 */
/* 0x040fe40007ffe0ff */
/*0160*/ IADD3 R11, R5.reuse, -0x1, RZ ; /* 0xffffffff050b7810 */
/* 0x040fe40007ffe0ff */
/*0170*/ IADD3 R12, R5.reuse, 0x1, RZ ; /* 0x00000001050c7810 */
/* 0x040fe40007ffe0ff */
/*0180*/ IADD3 R13, R5.reuse, 0x2, RZ ; /* 0x00000002050d7810 */
/* 0x040fe40007ffe0ff */
/*0190*/ IADD3 R14, R5.reuse, 0x3, RZ ; /* 0x00000003050e7810 */
/* 0x040fe40007ffe0ff */
/*01a0*/ IADD3 R15, R5, 0x4, RZ ; /* 0x00000004050f7810 */
/* 0x000fc40007ffe0ff */
/*01b0*/ IADD3 R16, R5.reuse, 0x5, RZ ; /* 0x0000000505107810 */
/* 0x040fe40007ffe0ff */
/*01c0*/ IADD3 R17, R5.reuse, 0x6, RZ ; /* 0x0000000605117810 */
/* 0x040fe40007ffe0ff */
/*01d0*/ IADD3 R19, R5, 0x7, RZ ; /* 0x0000000705137810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.GE.AND P0, PT, R24, c[0x0][0x174], PT ; /* 0x00005d0018007a0c */
/* 0x000fe20003f06270 */
/*01f0*/ IMAD.MOV.U32 R20, RZ, RZ, 0x3 ; /* 0x00000003ff147424 */
/* 0x000fe200078e00ff */
/*0200*/ LOP3.LUT R2, R4, R24, RZ, 0xfc, !PT ; /* 0x0000001804027212 */
/* 0x000fe200078efcff */
/*0210*/ IMAD R3, R18, c[0x0][0x170], R23 ; /* 0x00005c0012037a24 */
/* 0x000fc600078e0217 */
/*0220*/ ISETP.LT.OR P2, PT, R2, RZ, P0 ; /* 0x000000ff0200720c */
/* 0x000fe20000741670 */
/*0230*/ IMAD.WIDE R2, R3, R20, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fc600078e0214 */
/*0240*/ ISETP.GE.OR P2, PT, R4, c[0x0][0x170], P2 ; /* 0x00005c0004007a0c */
/* 0x000fda0001746670 */
/*0250*/ @!P2 LDG.E.U8 R25, [R2.64+-0x15] ; /* 0xffffeb040219a981 */
/* 0x000ea8000c1e1100 */
/*0260*/ @!P2 LDG.E.U8 R26, [R2.64+-0x14] ; /* 0xffffec04021aa981 */
/* 0x000ea8000c1e1100 */
/*0270*/ @!P2 LDG.E.U8 R28, [R2.64+-0x13] ; /* 0xffffed04021ca981 */
/* 0x000ee2000c1e1100 */
/*0280*/ @!P2 IADD3 R25, R26, R22, R25 ; /* 0x000000161a19a210 */
/* 0x004fe40007ffe019 */
/*0290*/ LOP3.LUT R26, R6, R24, RZ, 0xfc, !PT ; /* 0x00000018061a7212 */
/* 0x000fc800078efcff */
/*02a0*/ ISETP.LT.OR P6, PT, R26, RZ, P0 ; /* 0x000000ff1a00720c */
/* 0x000fc800007c1670 */
/*02b0*/ ISETP.GE.OR P6, PT, R6, c[0x0][0x170], P6 ; /* 0x00005c0006007a0c */
/* 0x000fda00037c6670 */
/*02c0*/ @!P6 LDG.E.U8 R27, [R2.64+-0x12] ; /* 0xffffee04021be981 */
/* 0x000ea8000c1e1100 */
/*02d0*/ @!P6 LDG.E.U8 R29, [R2.64+-0x11] ; /* 0xffffef04021de981 */
/* 0x000ea8000c1e1100 */
/*02e0*/ @!P6 LDG.E.U8 R26, [R2.64+-0x10] ; /* 0xfffff004021ae981 */
/* 0x000f22000c1e1100 */
/*02f0*/ @!P2 IMAD.IADD R22, R25, 0x1, R28 ; /* 0x000000011916a824 */
/* 0x008fe200078e021c */
/*0300*/ LOP3.LUT R25, R7, R24, RZ, 0xfc, !PT ; /* 0x0000001807197212 */
/* 0x000fc800078efcff */
/*0310*/ ISETP.LT.OR P1, PT, R25, RZ, P0 ; /* 0x000000ff1900720c */
/* 0x000fe40000721670 */
/*0320*/ LOP3.LUT R25, R8, R24, RZ, 0xfc, !PT ; /* 0x0000001808197212 */
/* 0x000fe400078efcff */
/*0330*/ ISETP.GE.OR P1, PT, R7, c[0x0][0x170], P1 ; /* 0x00005c0007007a0c */
/* 0x000fe40000f26670 */
/*0340*/ ISETP.LT.OR P3, PT, R25, RZ, P0 ; /* 0x000000ff1900720c */
/* 0x000fc80000761670 */
/*0350*/ ISETP.GE.OR P3, PT, R8, c[0x0][0x170], P3 ; /* 0x00005c0008007a0c */
/* 0x000fce0001f66670 */
/*0360*/ @!P1 LDG.E.U8 R28, [R2.64+-0xe] ; /* 0xfffff204021c9981 */
/* 0x000eec000c1e1100 */
/*0370*/ @!P3 LDG.E.U8 R25, [R2.64+-0xb] ; /* 0xfffff5040219b981 */
/* 0x000f62000c1e1100 */
/*0380*/ @!P6 IADD3 R27, R29, R22, R27 ; /* 0x000000161d1be210 */
/* 0x004fc60007ffe01b */
/*0390*/ @!P1 LDG.E.U8 R29, [R2.64+-0xf] ; /* 0xfffff104021d9981 */
/* 0x000ee4000c1e1100 */
/*03a0*/ @!P6 IMAD.IADD R22, R27, 0x1, R26 ; /* 0x000000011b16e824 */
/* 0x010fe400078e021a */
/*03b0*/ @!P1 LDG.E.U8 R27, [R2.64+-0xd] ; /* 0xfffff304021b9981 */
/* 0x000ea8000c1e1100 */
/*03c0*/ @!P3 LDG.E.U8 R26, [R2.64+-0xc] ; /* 0xfffff404021ab981 */
/* 0x000f62000c1e1100 */
/*03d0*/ @!P1 IADD3 R28, R28, R22, R29 ; /* 0x000000161c1c9210 */
/* 0x008fca0007ffe01d */
/*03e0*/ @!P1 IMAD.IADD R22, R28, 0x1, R27 ; /* 0x000000011c169824 */
/* 0x004fe400078e021b */
/*03f0*/ @!P3 LDG.E.U8 R28, [R2.64+-0xa] ; /* 0xfffff604021cb981 */
/* 0x000ea6000c1e1100 */
/*0400*/ @!P3 IADD3 R25, R25, R22, R26 ; /* 0x000000161919b210 */
/* 0x020fe40007ffe01a */
/*0410*/ LOP3.LUT R26, R9, R24, RZ, 0xfc, !PT ; /* 0x00000018091a7212 */
/* 0x000fc800078efcff */
/*0420*/ ISETP.LT.OR P5, PT, R26, RZ, P0 ; /* 0x000000ff1a00720c */
/* 0x000fc800007a1670 */
/*0430*/ ISETP.GE.OR P5, PT, R9, c[0x0][0x170], P5 ; /* 0x00005c0009007a0c */
/* 0x000fda0002fa6670 */
/*0440*/ @!P5 LDG.E.U8 R27, [R2.64+-0x9] ; /* 0xfffff704021bd981 */
/* 0x000ee8000c1e1100 */
/*0450*/ @!P5 LDG.E.U8 R29, [R2.64+-0x8] ; /* 0xfffff804021dd981 */
/* 0x000ee8000c1e1100 */
/*0460*/ @!P5 LDG.E.U8 R26, [R2.64+-0x7] ; /* 0xfffff904021ad981 */
/* 0x000f22000c1e1100 */
/*0470*/ @!P2 IADD3 R21, R21, 0x3, RZ ; /* 0x000000031515a810 */
/* 0x000fe20007ffe0ff */
/*0480*/ @!P3 IMAD.IADD R22, R25, 0x1, R28 ; /* 0x000000011916b824 */
/* 0x004fe200078e021c */
/*0490*/ LOP3.LUT R25, R10, R24, RZ, 0xfc, !PT ; /* 0x000000180a197212 */
/* 0x000fc800078efcff */
/*04a0*/ ISETP.LT.OR P4, PT, R25, RZ, P0 ; /* 0x000000ff1900720c */
/* 0x000fe40000781670 */
/*04b0*/ LOP3.LUT R25, R11, R24, RZ, 0xfc, !PT ; /* 0x000000180b197212 */
/* 0x000fe400078efcff */
/*04c0*/ ISETP.GE.OR P4, PT, R10, c[0x0][0x170], P4 ; /* 0x00005c000a007a0c */
/* 0x000fe40002786670 */
/*04d0*/ ISETP.LT.OR P2, PT, R25, RZ, P0 ; /* 0x000000ff1900720c */
/* 0x000fc80000741670 */
/*04e0*/ ISETP.GT.OR P2, PT, R5, c[0x0][0x170], P2 ; /* 0x00005c0005007a0c */
/* 0x000fce0001744670 */
/*04f0*/ @!P4 LDG.E.U8 R28, [R2.64+-0x5] ; /* 0xfffffb04021cc981 */
/* 0x000eac000c1e1100 */
/*0500*/ @!P2 LDG.E.U8 R25, [R2.64+-0x2] ; /* 0xfffffe040219a981 */
/* 0x000f62000c1e1100 */
/*0510*/ @!P5 IADD3 R27, R29, R22, R27 ; /* 0x000000161d1bd210 */
/* 0x008fc60007ffe01b */
/*0520*/ @!P4 LDG.E.U8 R29, [R2.64+-0x6] ; /* 0xfffffa04021dc981 */
/* 0x000ea4000c1e1100 */
/*0530*/ @!P5 IMAD.IADD R22, R27, 0x1, R26 ; /* 0x000000011b16d824 */
/* 0x010fe400078e021a */
/*0540*/ @!P4 LDG.E.U8 R27, [R2.64+-0x4] ; /* 0xfffffc04021bc981 */
/* 0x000ee8000c1e1100 */
/*0550*/ @!P2 LDG.E.U8 R26, [R2.64+-0x3] ; /* 0xfffffd04021aa981 */
/* 0x000f62000c1e1100 */
/*0560*/ @!P6 IADD3 R21, R21, 0x3, RZ ; /* 0x000000031515e810 */
/* 0x000fe40007ffe0ff */
/*0570*/ @!P4 IADD3 R28, R28, R22, R29 ; /* 0x000000161c1cc210 */
/* 0x004fca0007ffe01d */
/*0580*/ @!P4 IMAD.IADD R22, R28, 0x1, R27 ; /* 0x000000011c16c824 */
/* 0x008fe400078e021b */
/*0590*/ @!P2 LDG.E.U8 R28, [R2.64+-0x1] ; /* 0xffffff04021ca981 */
/* 0x000ea6000c1e1100 */
/*05a0*/ @!P2 IADD3 R25, R25, R22, R26 ; /* 0x000000161919a210 */
/* 0x020fe40007ffe01a */
/*05b0*/ LOP3.LUT R26, R5, R24, RZ, 0xfc, !PT ; /* 0x00000018051a7212 */
/* 0x000fc800078efcff */
/*05c0*/ ISETP.LT.OR P6, PT, R26, RZ, P0 ; /* 0x000000ff1a00720c */
/* 0x000fda00007c1670 */
/*05d0*/ @!P6 LDG.E.U8 R27, [R2.64] ; /* 0x00000004021be981 */
/* 0x000ee8000c1e1100 */
/*05e0*/ @!P6 LDG.E.U8 R29, [R2.64+0x1] ; /* 0x00000104021de981 */
/* 0x000ee8000c1e1100 */
/*05f0*/ @!P6 LDG.E.U8 R26, [R2.64+0x2] ; /* 0x00000204021ae981 */
/* 0x000f22000c1e1100 */
/*0600*/ @!P1 IADD3 R21, R21, 0x3, RZ ; /* 0x0000000315159810 */
/* 0x000fc80007ffe0ff */
/*0610*/ @!P3 IADD3 R21, R21, 0x3, RZ ; /* 0x000000031515b810 */
/* 0x000fe20007ffe0ff */
/*0620*/ @!P2 IMAD.IADD R22, R25, 0x1, R28 ; /* 0x000000011916a824 */
/* 0x004fe200078e021c */
/*0630*/ LOP3.LUT R25, R12, R24, RZ, 0xfc, !PT ; /* 0x000000180c197212 */
/* 0x000fc800078efcff */
/*0640*/ ISETP.LT.OR P1, PT, R25, RZ, P0 ; /* 0x000000ff1900720c */
/* 0x000fe40000721670 */
/*0650*/ LOP3.LUT R25, R13, R24, RZ, 0xfc, !PT ; /* 0x000000180d197212 */
/* 0x000fe400078efcff */
/*0660*/ ISETP.GE.OR P1, PT, R12, c[0x0][0x170], P1 ; /* 0x00005c000c007a0c */
/* 0x000fe40000f26670 */
/*0670*/ ISETP.LT.OR P3, PT, R25, RZ, P0 ; /* 0x000000ff1900720c */
/* 0x000fc80000761670 */
/*0680*/ ISETP.GE.OR P3, PT, R13, c[0x0][0x170], P3 ; /* 0x00005c000d007a0c */
/* 0x000fce0001f66670 */
/*0690*/ @!P1 LDG.E.U8 R28, [R2.64+0x4] ; /* 0x00000404021c9981 */
/* 0x000ea2000c1e1100 */
/*06a0*/ @!P6 IADD3 R27, R29, R22, R27 ; /* 0x000000161d1be210 */
/* 0x008fc60007ffe01b */
/*06b0*/ @!P1 LDG.E.U8 R29, [R2.64+0x3] ; /* 0x00000304021d9981 */
/* 0x000ea4000c1e1100 */
/*06c0*/ @!P6 IMAD.IADD R22, R27, 0x1, R26 ; /* 0x000000011b16e824 */
/* 0x010fe400078e021a */
/*06d0*/ @!P3 LDG.E.U8 R25, [R2.64+0x7] ; /* 0x000007040219b981 */
/* 0x000ee8000c1e1100 */
/*06e0*/ @!P1 LDG.E.U8 R27, [R2.64+0x5] ; /* 0x00000504021b9981 */
/* 0x000f28000c1e1100 */
/*06f0*/ @!P3 LDG.E.U8 R26, [R2.64+0x6] ; /* 0x00000604021ab981 */
/* 0x000ee2000c1e1100 */
/*0700*/ @!P5 IADD3 R21, R21, 0x3, RZ ; /* 0x000000031515d810 */
/* 0x000fc40007ffe0ff */
/*0710*/ @!P1 IADD3 R28, R28, R22, R29 ; /* 0x000000161c1c9210 */
/* 0x004fca0007ffe01d */
/*0720*/ @!P1 IMAD.IADD R22, R28, 0x1, R27 ; /* 0x000000011c169824 */
/* 0x010fe400078e021b */
/*0730*/ @!P3 LDG.E.U8 R28, [R2.64+0x8] ; /* 0x00000804021cb981 */
/* 0x000ea6000c1e1100 */
/*0740*/ @!P3 IADD3 R25, R25, R22, R26 ; /* 0x000000161919b210 */
/* 0x008fe40007ffe01a */
/*0750*/ LOP3.LUT R26, R14, R24, RZ, 0xfc, !PT ; /* 0x000000180e1a7212 */
/* 0x000fc800078efcff */
/*0760*/ ISETP.LT.OR P5, PT, R26, RZ, P0 ; /* 0x000000ff1a00720c */
/* 0x000fc800007a1670 */
/*0770*/ ISETP.GE.OR P5, PT, R14, c[0x0][0x170], P5 ; /* 0x00005c000e007a0c */
/* 0x000fda0002fa6670 */
/*0780*/ @!P5 LDG.E.U8 R27, [R2.64+0x9] ; /* 0x00000904021bd981 */
/* 0x000ee8000c1e1100 */
/*0790*/ @!P5 LDG.E.U8 R29, [R2.64+0xa] ; /* 0x00000a04021dd981 */
/* 0x000ee8000c1e1100 */
/*07a0*/ @!P5 LDG.E.U8 R26, [R2.64+0xb] ; /* 0x00000b04021ad981 */
/* 0x000f22000c1e1100 */
/*07b0*/ @!P4 IADD3 R21, R21, 0x3, RZ ; /* 0x000000031515c810 */
/* 0x000fc80007ffe0ff */
/*07c0*/ @!P2 IADD3 R21, R21, 0x3, RZ ; /* 0x000000031515a810 */
/* 0x000fe20007ffe0ff */
/*07d0*/ @!P3 IMAD.IADD R22, R25, 0x1, R28 ; /* 0x000000011916b824 */
/* 0x004fe200078e021c */
/*07e0*/ LOP3.LUT R25, R15, R24, RZ, 0xfc, !PT ; /* 0x000000180f197212 */
/* 0x000fc800078efcff */
/*07f0*/ ISETP.LT.OR P4, PT, R25, RZ, P0 ; /* 0x000000ff1900720c */
/* 0x000fe40000781670 */
/*0800*/ LOP3.LUT R25, R16, R24, RZ, 0xfc, !PT ; /* 0x0000001810197212 */
/* 0x000fe400078efcff */
/*0810*/ ISETP.GE.OR P4, PT, R15, c[0x0][0x170], P4 ; /* 0x00005c000f007a0c */
/* 0x000fe40002786670 */
/*0820*/ ISETP.LT.OR P2, PT, R25, RZ, P0 ; /* 0x000000ff1900720c */
/* 0x000fc80000741670 */
/*0830*/ ISETP.GE.OR P2, PT, R16, c[0x0][0x170], P2 ; /* 0x00005c0010007a0c */
/* 0x000fce0001746670 */
/*0840*/ @!P4 LDG.E.U8 R28, [R2.64+0xd] ; /* 0x00000d04021cc981 */
/* 0x000eac000c1e1100 */
/*0850*/ @!P2 LDG.E.U8 R25, [R2.64+0x10] ; /* 0x000010040219a981 */
/* 0x000f62000c1e1100 */
/*0860*/ @!P5 IADD3 R27, R29, R22, R27 ; /* 0x000000161d1bd210 */
/* 0x008fc60007ffe01b */
/*0870*/ @!P4 LDG.E.U8 R29, [R2.64+0xc] ; /* 0x00000c04021dc981 */
/* 0x000ea4000c1e1100 */
/*0880*/ @!P5 IMAD.IADD R22, R27, 0x1, R26 ; /* 0x000000011b16d824 */
/* 0x010fe400078e021a */
/*0890*/ @!P4 LDG.E.U8 R27, [R2.64+0xe] ; /* 0x00000e04021bc981 */
/* 0x000ee8000c1e1100 */
/*08a0*/ @!P2 LDG.E.U8 R26, [R2.64+0xf] ; /* 0x00000f04021aa981 */
/* 0x000f62000c1e1100 */
/*08b0*/ @!P6 IADD3 R21, R21, 0x3, RZ ; /* 0x000000031515e810 */
/* 0x000fe40007ffe0ff */
/*08c0*/ @!P4 IADD3 R28, R28, R22, R29 ; /* 0x000000161c1cc210 */
/* 0x004fca0007ffe01d */
/*08d0*/ @!P4 IMAD.IADD R22, R28, 0x1, R27 ; /* 0x000000011c16c824 */
/* 0x008fe400078e021b */
/*08e0*/ @!P2 LDG.E.U8 R28, [R2.64+0x11] ; /* 0x00001104021ca981 */
/* 0x000ea6000c1e1100 */
/*08f0*/ @!P2 IADD3 R25, R25, R22, R26 ; /* 0x000000161919a210 */
/* 0x020fe40007ffe01a */
/*0900*/ LOP3.LUT R26, R17, R24, RZ, 0xfc, !PT ; /* 0x00000018111a7212 */
/* 0x000fc800078efcff */
/*0910*/ ISETP.LT.OR P6, PT, R26, RZ, P0 ; /* 0x000000ff1a00720c */
/* 0x000fc800007c1670 */
/*0920*/ ISETP.GE.OR P6, PT, R17, c[0x0][0x170], P6 ; /* 0x00005c0011007a0c */
/* 0x000fda00037c6670 */
/*0930*/ @!P6 LDG.E.U8 R27, [R2.64+0x12] ; /* 0x00001204021be981 */
/* 0x000ee8000c1e1100 */
/*0940*/ @!P6 LDG.E.U8 R29, [R2.64+0x13] ; /* 0x00001304021de981 */
/* 0x000ee8000c1e1100 */
/*0950*/ @!P6 LDG.E.U8 R26, [R2.64+0x14] ; /* 0x00001404021ae981 */
/* 0x000f22000c1e1100 */
/*0960*/ @!P2 IMAD.IADD R22, R25, 0x1, R28 ; /* 0x000000011916a824 */
/* 0x004fe200078e021c */
/*0970*/ LOP3.LUT R25, R19, R24, RZ, 0xfc, !PT ; /* 0x0000001813197212 */
/* 0x000fc800078efcff */
/*0980*/ ISETP.LT.OR P0, PT, R25, RZ, P0 ; /* 0x000000ff1900720c */
/* 0x000fc80000701670 */
/*0990*/ ISETP.GE.OR P0, PT, R19, c[0x0][0x170], P0 ; /* 0x00005c0013007a0c */
/* 0x000fda0000706670 */
/*09a0*/ @!P0 LDG.E.U8 R25, [R2.64+0x15] ; /* 0x0000150402198981 */
/* 0x000ea8000c1e1100 */
/*09b0*/ @!P0 LDG.E.U8 R28, [R2.64+0x17] ; /* 0x00001704021c8981 */
/* 0x000f62000c1e1100 */
/*09c0*/ @!P6 IADD3 R27, R29, R22, R27 ; /* 0x000000161d1be210 */
/* 0x008fca0007ffe01b */
/*09d0*/ @!P6 IMAD.IADD R22, R27, 0x1, R26 ; /* 0x000000011b16e824 */
/* 0x010fe400078e021a */
/*09e0*/ @!P0 LDG.E.U8 R26, [R2.64+0x16] ; /* 0x00001604021a8981 */
/* 0x000ea2000c1e1100 */
/*09f0*/ @!P1 IADD3 R21, R21, 0x3, RZ ; /* 0x0000000315159810 */
/* 0x000fc80007ffe0ff */
/*0a00*/ @!P3 IADD3 R21, R21, 0x3, RZ ; /* 0x000000031515b810 */
/* 0x000fe40007ffe0ff */
/*0a10*/ ISETP.NE.AND P1, PT, R18, 0xe, PT ; /* 0x0000000e1200780c */
/* 0x000fe40003f25270 */
/*0a20*/ @!P5 IADD3 R21, R21, 0x3, RZ ; /* 0x000000031515d810 */
/* 0x000fc80007ffe0ff */
/*0a30*/ @!P4 IADD3 R21, R21, 0x3, RZ ; /* 0x000000031515c810 */
/* 0x000fc80007ffe0ff */
/*0a40*/ @!P2 IADD3 R21, R21, 0x3, RZ ; /* 0x000000031515a810 */
/* 0x000fc80007ffe0ff */
/*0a50*/ @!P6 IADD3 R21, R21, 0x3, RZ ; /* 0x000000031515e810 */
/* 0x000fe40007ffe0ff */
/*0a60*/ IADD3 R24, R24, 0x1, RZ ; /* 0x0000000118187810 */
/* 0x000fe40007ffe0ff */
/*0a70*/ IADD3 R18, R18, 0x1, RZ ; /* 0x0000000112127810 */
/* 0x000fe40007ffe0ff */
/*0a80*/ @!P0 IADD3 R21, R21, 0x3, RZ ; /* 0x0000000315158810 */
/* 0x000fe40007ffe0ff */
/*0a90*/ @!P0 IADD3 R25, R26, R22, R25 ; /* 0x000000161a198210 */
/* 0x004fca0007ffe019 */
/*0aa0*/ @!P0 IMAD.IADD R22, R25, 0x1, R28 ; /* 0x0000000119168824 */
/* 0x020fe200078e021c */
/*0ab0*/ @P1 BRA 0x1e0 ; /* 0xfffff72000001947 */
/* 0x000fea000383ffff */
/*0ac0*/ IABS R7, R21.reuse ; /* 0x0000001500077213 */
/* 0x080fe40000000000 */
/*0ad0*/ IABS R8, R22 ; /* 0x0000001600087213 */
/* 0x000fe40000000000 */
/*0ae0*/ I2F.RP R4, R7 ; /* 0x0000000700047306 */
/* 0x000e220000209400 */
/*0af0*/ IABS R10, R21.reuse ; /* 0x00000015000a7213 */
/* 0x080fe40000000000 */
/*0b00*/ LOP3.LUT R22, R22, R21, RZ, 0x3c, !PT ; /* 0x0000001516167212 */
/* 0x000fc800078e3cff */
/*0b10*/ ISETP.GE.AND P2, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fe20003f46270 */
/*0b20*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0b30*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fe20007ffe0ff */
/*0b40*/ IMAD.MOV R4, RZ, RZ, -R10 ; /* 0x000000ffff047224 */
/* 0x000fca00078e0a0a */
/*0b50*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0b60*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0b70*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*0b80*/ IMAD R9, R6, R7, RZ ; /* 0x0000000706097224 */
/* 0x000fe400078e02ff */
/*0b90*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0008 */
/*0ba0*/ IMAD.HI.U32 R3, R3, R9, R2 ; /* 0x0000000903037227 */
/* 0x000fcc00078e0002 */
/*0bb0*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fc800078e00ff */
/*0bc0*/ IMAD R2, R3, R4, R6 ; /* 0x0000000403027224 */
/* 0x000fca00078e0206 */
/*0bd0*/ ISETP.GT.U32.AND P1, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fda0003f24070 */
/*0be0*/ @!P1 IMAD.IADD R2, R2, 0x1, -R7 ; /* 0x0000000102029824 */
/* 0x000fe200078e0a07 */
/*0bf0*/ @!P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103039810 */
/* 0x000fe40007ffe0ff */
/*0c00*/ ISETP.NE.AND P1, PT, R21, RZ, PT ; /* 0x000000ff1500720c */
/* 0x000fe40003f25270 */
/*0c10*/ ISETP.GE.U32.AND P0, PT, R2, R7, PT ; /* 0x000000070200720c */
/* 0x000fda0003f06070 */
/*0c20*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*0c30*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0003 */
/*0c40*/ IMAD R3, R0, c[0x0][0x170], R5 ; /* 0x00005c0000037a24 */
/* 0x000fe400078e0205 */
/*0c50*/ @!P2 IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff07a224 */
/* 0x000fe200078e0a07 */
/*0c60*/ @!P1 LOP3.LUT R7, RZ, R21, RZ, 0x33, !PT ; /* 0x00000015ff079212 */
/* 0x000fe200078e33ff */
/*0c70*/ IMAD.WIDE R2, R3, R20, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0214 */
/*0c80*/ STG.E.U8 [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101104 */
/*0c90*/ STG.E.U8 [R2.64+0x1], R7 ; /* 0x0000010702007986 */
/* 0x000fe8000c101104 */
/*0ca0*/ STG.E.U8 [R2.64+0x2], R7 ; /* 0x0000020702007986 */
/* 0x000fe2000c101104 */
/*0cb0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0cc0*/ BRA 0xcc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10blurKernelP15HIP_vector_typeIhLj3EES1_ii
.globl _Z10blurKernelP15HIP_vector_typeIhLj3EES1_ii
.p2align 8
.type _Z10blurKernelP15HIP_vector_typeIhLj3EES1_ii,@function
_Z10blurKernelP15HIP_vector_typeIhLj3EES1_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[6:7], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_mul_i32 s14, s14, s3
s_mul_i32 s15, s15, s2
v_add_nc_u32_e32 v0, s14, v2
v_add_nc_u32_e32 v1, s15, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s6, v0
v_cmp_gt_i32_e64 s2, s7, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_10
s_load_b64 s[8:9], s[0:1], 0x0
v_add3_u32 v3, v3, s15, -7
v_add3_u32 v5, v2, s14, -7
v_mov_b32_e32 v2, 0
s_mov_b32 s5, -7
s_delay_alu instid0(VALU_DEP_3)
v_mul_lo_u32 v4, s6, v3
v_mov_b32_e32 v3, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
v_add_nc_u32_e32 v4, s6, v4
s_add_i32 s5, s5, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s5, 8
s_cbranch_scc1 .LBB0_9
.LBB0_3:
v_add_nc_u32_e32 v6, s5, v1
s_mov_b32 s10, 15
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v6
v_cmp_gt_i32_e64 s2, s7, v6
v_mov_b32_e32 v6, v5
s_branch .LBB0_6
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s3
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s11
v_add_nc_u32_e32 v6, 1, v6
s_add_i32 s10, s10, -1
s_cmp_eq_u32 s10, 0
s_cbranch_scc1 .LBB0_2
.LBB0_6:
s_and_saveexec_b32 s11, vcc_lo
s_cbranch_execz .LBB0_5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_lt_i32_e64 s3, -1, v6
v_cmp_gt_i32_e64 s4, s6, v6
s_and_b32 s3, s2, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s4, s3, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s4
s_cbranch_execz .LBB0_4
v_add_nc_u32_e32 v9, v4, v6
v_add_nc_u32_e32 v3, 3, v3
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_mad_i64_i32 v[7:8], null, v9, 3, s[8:9]
s_clause 0x2
global_load_u8 v9, v[7:8], off
global_load_u8 v10, v[7:8], off offset:1
global_load_u8 v7, v[7:8], off offset:2
s_waitcnt vmcnt(2)
v_add_nc_u32_e32 v2, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v2, v2, v10, v7
s_branch .LBB0_4
.LBB0_9:
s_set_inst_prefetch_distance 0x2
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v7, 31, v2
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, v3, v4
v_add_nc_u32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v5, v3, v4
v_xor_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cvt_f32_u32_e32 v3, v5
v_sub_nc_u32_e32 v6, 0, v5
v_rcp_iflag_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v3, v3
v_mul_lo_u32 v6, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v6, v3, v6
v_add_nc_u32_e32 v3, v3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v2, v3
v_mul_lo_u32 v6, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v2, v6
v_add_nc_u32_e32 v6, 1, v3
v_sub_nc_u32_e32 v8, v2, v5
v_cmp_ge_u32_e32 vcc_lo, v2, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v8, v2, v8, vcc_lo
v_cndmask_b32_e32 v6, v3, v6, vcc_lo
v_mad_u64_u32 v[2:3], null, v1, s6, v[0:1]
v_xor_b32_e32 v3, v7, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_ge_u32_e32 vcc_lo, v8, v5
v_add_nc_u32_e32 v9, 1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v6, v9, vcc_lo
v_xor_b32_e32 v4, v0, v3
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[0:1], null, v2, 3, s[0:1]
s_delay_alu instid0(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v4, v3
s_clause 0x2
global_store_b8 v[0:1], v2, off
global_store_b8 v[0:1], v2, off offset:1
global_store_b8 v[0:1], v2, off offset:2
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10blurKernelP15HIP_vector_typeIhLj3EES1_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10blurKernelP15HIP_vector_typeIhLj3EES1_ii, .Lfunc_end0-_Z10blurKernelP15HIP_vector_typeIhLj3EES1_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10blurKernelP15HIP_vector_typeIhLj3EES1_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10blurKernelP15HIP_vector_typeIhLj3EES1_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000adf06_00000000-6_blurKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z10blurKernelP6uchar3S0_iiP6uchar3S0_ii
.type _Z41__device_stub__Z10blurKernelP6uchar3S0_iiP6uchar3S0_ii, @function
_Z41__device_stub__Z10blurKernelP6uchar3S0_iiP6uchar3S0_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10blurKernelP6uchar3S0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z10blurKernelP6uchar3S0_iiP6uchar3S0_ii, .-_Z41__device_stub__Z10blurKernelP6uchar3S0_iiP6uchar3S0_ii
.globl _Z10blurKernelP6uchar3S0_ii
.type _Z10blurKernelP6uchar3S0_ii, @function
_Z10blurKernelP6uchar3S0_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z10blurKernelP6uchar3S0_iiP6uchar3S0_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10blurKernelP6uchar3S0_ii, .-_Z10blurKernelP6uchar3S0_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10blurKernelP6uchar3S0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10blurKernelP6uchar3S0_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "blurKernel.hip"
.globl _Z25__device_stub__blurKernelP15HIP_vector_typeIhLj3EES1_ii # -- Begin function _Z25__device_stub__blurKernelP15HIP_vector_typeIhLj3EES1_ii
.p2align 4, 0x90
.type _Z25__device_stub__blurKernelP15HIP_vector_typeIhLj3EES1_ii,@function
_Z25__device_stub__blurKernelP15HIP_vector_typeIhLj3EES1_ii: # @_Z25__device_stub__blurKernelP15HIP_vector_typeIhLj3EES1_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10blurKernelP15HIP_vector_typeIhLj3EES1_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__blurKernelP15HIP_vector_typeIhLj3EES1_ii, .Lfunc_end0-_Z25__device_stub__blurKernelP15HIP_vector_typeIhLj3EES1_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10blurKernelP15HIP_vector_typeIhLj3EES1_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10blurKernelP15HIP_vector_typeIhLj3EES1_ii,@object # @_Z10blurKernelP15HIP_vector_typeIhLj3EES1_ii
.section .rodata,"a",@progbits
.globl _Z10blurKernelP15HIP_vector_typeIhLj3EES1_ii
.p2align 3, 0x0
_Z10blurKernelP15HIP_vector_typeIhLj3EES1_ii:
.quad _Z25__device_stub__blurKernelP15HIP_vector_typeIhLj3EES1_ii
.size _Z10blurKernelP15HIP_vector_typeIhLj3EES1_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10blurKernelP15HIP_vector_typeIhLj3EES1_ii"
.size .L__unnamed_1, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__blurKernelP15HIP_vector_typeIhLj3EES1_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10blurKernelP15HIP_vector_typeIhLj3EES1_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <thrust/complex.h>
template <typename S, typename T, typename F, typename Fprime>
__device__
T root_finder_newton(F f, Fprime fprime, T x0, S tol, const int MAX_ITER = 100)
{
T x1;
for (auto i = 0; i < MAX_ITER; ++i)
{
x1 = x0 - f(x0) / fprime(x0);
if (abs(x1 - x0) < tol * abs(x1))
{
break;
}
x0 = x1;
}
return x1;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <thrust/complex.h>
template <typename S, typename T, typename F, typename Fprime>
__device__
T root_finder_newton(F f, Fprime fprime, T x0, S tol, const int MAX_ITER = 100)
{
T x1;
for (auto i = 0; i < MAX_ITER; ++i)
{
x1 = x0 - f(x0) / fprime(x0);
if (abs(x1 - x0) < tol * abs(x1))
{
break;
}
x0 = x1;
}
return x1;
} | .file "tmpxft_000a3168_00000000-6_newton_solver.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB5977:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5977:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_ZN54_INTERNAL_72778dc2_16_newton_solver_cu_cc78c704_6681554cuda3std3__45__cpo5beginE"
.align 8
.LC1:
.string "_ZN54_INTERNAL_72778dc2_16_newton_solver_cu_cc78c704_6681554cuda3std3__45__cpo3endE"
.align 8
.LC2:
.string "_ZN54_INTERNAL_72778dc2_16_newton_solver_cu_cc78c704_6681554cuda3std3__45__cpo6cbeginE"
.align 8
.LC3:
.string "_ZN54_INTERNAL_72778dc2_16_newton_solver_cu_cc78c704_6681554cuda3std3__45__cpo4cendE"
.align 8
.LC4:
.string "_ZN54_INTERNAL_72778dc2_16_newton_solver_cu_cc78c704_6681554cuda3std3__456_GLOBAL__N__72778dc2_16_newton_solver_cu_cc78c704_6681556ignoreE"
.align 8
.LC5:
.string "_ZN54_INTERNAL_72778dc2_16_newton_solver_cu_cc78c704_6681554cuda3std3__419piecewise_constructE"
.align 8
.LC6:
.string "_ZN54_INTERNAL_72778dc2_16_newton_solver_cu_cc78c704_6681554cuda3std3__48in_placeE"
.align 8
.LC7:
.string "_ZN54_INTERNAL_72778dc2_16_newton_solver_cu_cc78c704_6681554cuda3std6ranges3__45__cpo4swapE"
.align 8
.LC8:
.string "_ZN54_INTERNAL_72778dc2_16_newton_solver_cu_cc78c704_6681554cuda3std6ranges3__45__cpo9iter_moveE"
.align 8
.LC9:
.string "_ZN54_INTERNAL_72778dc2_16_newton_solver_cu_cc78c704_6681554cuda3std6ranges3__45__cpo7advanceE"
.align 8
.LC10:
.string "_ZN54_INTERNAL_72778dc2_16_newton_solver_cu_cc78c704_6681556thrust20THRUST_200700_800_NS6system6detail10sequential3seqE"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB6000:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__45__cpo5beginE(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__45__cpo3endE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__45__cpo6cbeginE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__45__cpo4cendE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__456_GLOBAL__N__72778dc2_16_newton_solver_cu_cc78c704_6681556ignoreE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__48in_placeE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo7advanceE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZN6thrust20THRUST_200700_800_NS6system6detail10sequentialL3seqE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6000:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata
.type _ZN6thrust20THRUST_200700_800_NS6system6detail10sequentialL3seqE, @object
.size _ZN6thrust20THRUST_200700_800_NS6system6detail10sequentialL3seqE, 1
_ZN6thrust20THRUST_200700_800_NS6system6detail10sequentialL3seqE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo7advanceE
.section .rodata._ZN4cuda3std6ranges3__45__cpo7advanceE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo7advanceE,comdat
.type _ZN4cuda3std6ranges3__45__cpo7advanceE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo7advanceE, 1
_ZN4cuda3std6ranges3__45__cpo7advanceE:
.zero 1
.hidden _ZN4cuda3std3__456_GLOBAL__N__72778dc2_16_newton_solver_cu_cc78c704_6681556ignoreE
.weak _ZN4cuda3std3__456_GLOBAL__N__72778dc2_16_newton_solver_cu_cc78c704_6681556ignoreE
.section .rodata._ZN4cuda3std3__456_GLOBAL__N__72778dc2_16_newton_solver_cu_cc78c704_6681556ignoreE,"aG",@progbits,_ZN4cuda3std3__456_GLOBAL__N__72778dc2_16_newton_solver_cu_cc78c704_6681556ignoreE,comdat
.type _ZN4cuda3std3__456_GLOBAL__N__72778dc2_16_newton_solver_cu_cc78c704_6681556ignoreE, @gnu_unique_object
.size _ZN4cuda3std3__456_GLOBAL__N__72778dc2_16_newton_solver_cu_cc78c704_6681556ignoreE, 1
_ZN4cuda3std3__456_GLOBAL__N__72778dc2_16_newton_solver_cu_cc78c704_6681556ignoreE:
.zero 1
.weak _ZN4cuda3std3__48in_placeE
.section .rodata._ZN4cuda3std3__48in_placeE,"aG",@progbits,_ZN4cuda3std3__48in_placeE,comdat
.type _ZN4cuda3std3__48in_placeE, @gnu_unique_object
.size _ZN4cuda3std3__48in_placeE, 1
_ZN4cuda3std3__48in_placeE:
.zero 1
.weak _ZN4cuda3std3__45__cpo4cendE
.section .rodata._ZN4cuda3std3__45__cpo4cendE,"aG",@progbits,_ZN4cuda3std3__45__cpo4cendE,comdat
.type _ZN4cuda3std3__45__cpo4cendE, @gnu_unique_object
.size _ZN4cuda3std3__45__cpo4cendE, 1
_ZN4cuda3std3__45__cpo4cendE:
.zero 1
.weak _ZN4cuda3std3__45__cpo6cbeginE
.section .rodata._ZN4cuda3std3__45__cpo6cbeginE,"aG",@progbits,_ZN4cuda3std3__45__cpo6cbeginE,comdat
.type _ZN4cuda3std3__45__cpo6cbeginE, @gnu_unique_object
.size _ZN4cuda3std3__45__cpo6cbeginE, 1
_ZN4cuda3std3__45__cpo6cbeginE:
.zero 1
.weak _ZN4cuda3std3__45__cpo3endE
.section .rodata._ZN4cuda3std3__45__cpo3endE,"aG",@progbits,_ZN4cuda3std3__45__cpo3endE,comdat
.type _ZN4cuda3std3__45__cpo3endE, @gnu_unique_object
.size _ZN4cuda3std3__45__cpo3endE, 1
_ZN4cuda3std3__45__cpo3endE:
.zero 1
.weak _ZN4cuda3std3__45__cpo5beginE
.section .rodata._ZN4cuda3std3__45__cpo5beginE,"aG",@progbits,_ZN4cuda3std3__45__cpo5beginE,comdat
.type _ZN4cuda3std3__45__cpo5beginE, @gnu_unique_object
.size _ZN4cuda3std3__45__cpo5beginE, 1
_ZN4cuda3std3__45__cpo5beginE:
.zero 1
.weak _ZN4cuda3std3__419piecewise_constructE
.section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
.type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
.size _ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE
.section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
.type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo4swapE
.section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
.type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
.zero 1
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/complex.h>
template <typename S, typename T, typename F, typename Fprime>
__device__
T root_finder_newton(F f, Fprime fprime, T x0, S tol, const int MAX_ITER = 100)
{
T x1;
for (auto i = 0; i < MAX_ITER; ++i)
{
x1 = x0 - f(x0) / fprime(x0);
if (abs(x1 - x0) < tol * abs(x1))
{
break;
}
x0 = x1;
}
return x1;
} | #include <hip/hip_runtime.h>
#include <thrust/complex.h>
template <typename S, typename T, typename F, typename Fprime>
__device__
T root_finder_newton(F f, Fprime fprime, T x0, S tol, const int MAX_ITER = 100)
{
T x1;
for (auto i = 0; i < MAX_ITER; ++i)
{
x1 = x0 - f(x0) / fprime(x0);
if (abs(x1 - x0) < tol * abs(x1))
{
break;
}
x0 = x1;
}
return x1;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <thrust/complex.h>
template <typename S, typename T, typename F, typename Fprime>
__device__
T root_finder_newton(F f, Fprime fprime, T x0, S tol, const int MAX_ITER = 100)
{
T x1;
for (auto i = 0; i < MAX_ITER; ++i)
{
x1 = x0 - f(x0) / fprime(x0);
if (abs(x1 - x0) < tol * abs(x1))
{
break;
}
x0 = x1;
}
return x1;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <thrust/complex.h>
template <typename S, typename T, typename F, typename Fprime>
__device__
T root_finder_newton(F f, Fprime fprime, T x0, S tol, const int MAX_ITER = 100)
{
T x1;
for (auto i = 0; i < MAX_ITER; ++i)
{
x1 = x0 - f(x0) / fprime(x0);
if (abs(x1 - x0) < tol * abs(x1))
{
break;
}
x0 = x1;
}
return x1;
} | .text
.file "newton_solver.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a3168_00000000-6_newton_solver.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB5977:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE5977:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_ZN54_INTERNAL_72778dc2_16_newton_solver_cu_cc78c704_6681554cuda3std3__45__cpo5beginE"
.align 8
.LC1:
.string "_ZN54_INTERNAL_72778dc2_16_newton_solver_cu_cc78c704_6681554cuda3std3__45__cpo3endE"
.align 8
.LC2:
.string "_ZN54_INTERNAL_72778dc2_16_newton_solver_cu_cc78c704_6681554cuda3std3__45__cpo6cbeginE"
.align 8
.LC3:
.string "_ZN54_INTERNAL_72778dc2_16_newton_solver_cu_cc78c704_6681554cuda3std3__45__cpo4cendE"
.align 8
.LC4:
.string "_ZN54_INTERNAL_72778dc2_16_newton_solver_cu_cc78c704_6681554cuda3std3__456_GLOBAL__N__72778dc2_16_newton_solver_cu_cc78c704_6681556ignoreE"
.align 8
.LC5:
.string "_ZN54_INTERNAL_72778dc2_16_newton_solver_cu_cc78c704_6681554cuda3std3__419piecewise_constructE"
.align 8
.LC6:
.string "_ZN54_INTERNAL_72778dc2_16_newton_solver_cu_cc78c704_6681554cuda3std3__48in_placeE"
.align 8
.LC7:
.string "_ZN54_INTERNAL_72778dc2_16_newton_solver_cu_cc78c704_6681554cuda3std6ranges3__45__cpo4swapE"
.align 8
.LC8:
.string "_ZN54_INTERNAL_72778dc2_16_newton_solver_cu_cc78c704_6681554cuda3std6ranges3__45__cpo9iter_moveE"
.align 8
.LC9:
.string "_ZN54_INTERNAL_72778dc2_16_newton_solver_cu_cc78c704_6681554cuda3std6ranges3__45__cpo7advanceE"
.align 8
.LC10:
.string "_ZN54_INTERNAL_72778dc2_16_newton_solver_cu_cc78c704_6681556thrust20THRUST_200700_800_NS6system6detail10sequential3seqE"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB6000:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__45__cpo5beginE(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__45__cpo3endE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__45__cpo6cbeginE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__45__cpo4cendE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__456_GLOBAL__N__72778dc2_16_newton_solver_cu_cc78c704_6681556ignoreE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std3__48in_placeE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZN4cuda3std6ranges3__45__cpo7advanceE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $1, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZN6thrust20THRUST_200700_800_NS6system6detail10sequentialL3seqE(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE6000:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata
.type _ZN6thrust20THRUST_200700_800_NS6system6detail10sequentialL3seqE, @object
.size _ZN6thrust20THRUST_200700_800_NS6system6detail10sequentialL3seqE, 1
_ZN6thrust20THRUST_200700_800_NS6system6detail10sequentialL3seqE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo7advanceE
.section .rodata._ZN4cuda3std6ranges3__45__cpo7advanceE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo7advanceE,comdat
.type _ZN4cuda3std6ranges3__45__cpo7advanceE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo7advanceE, 1
_ZN4cuda3std6ranges3__45__cpo7advanceE:
.zero 1
.hidden _ZN4cuda3std3__456_GLOBAL__N__72778dc2_16_newton_solver_cu_cc78c704_6681556ignoreE
.weak _ZN4cuda3std3__456_GLOBAL__N__72778dc2_16_newton_solver_cu_cc78c704_6681556ignoreE
.section .rodata._ZN4cuda3std3__456_GLOBAL__N__72778dc2_16_newton_solver_cu_cc78c704_6681556ignoreE,"aG",@progbits,_ZN4cuda3std3__456_GLOBAL__N__72778dc2_16_newton_solver_cu_cc78c704_6681556ignoreE,comdat
.type _ZN4cuda3std3__456_GLOBAL__N__72778dc2_16_newton_solver_cu_cc78c704_6681556ignoreE, @gnu_unique_object
.size _ZN4cuda3std3__456_GLOBAL__N__72778dc2_16_newton_solver_cu_cc78c704_6681556ignoreE, 1
_ZN4cuda3std3__456_GLOBAL__N__72778dc2_16_newton_solver_cu_cc78c704_6681556ignoreE:
.zero 1
.weak _ZN4cuda3std3__48in_placeE
.section .rodata._ZN4cuda3std3__48in_placeE,"aG",@progbits,_ZN4cuda3std3__48in_placeE,comdat
.type _ZN4cuda3std3__48in_placeE, @gnu_unique_object
.size _ZN4cuda3std3__48in_placeE, 1
_ZN4cuda3std3__48in_placeE:
.zero 1
.weak _ZN4cuda3std3__45__cpo4cendE
.section .rodata._ZN4cuda3std3__45__cpo4cendE,"aG",@progbits,_ZN4cuda3std3__45__cpo4cendE,comdat
.type _ZN4cuda3std3__45__cpo4cendE, @gnu_unique_object
.size _ZN4cuda3std3__45__cpo4cendE, 1
_ZN4cuda3std3__45__cpo4cendE:
.zero 1
.weak _ZN4cuda3std3__45__cpo6cbeginE
.section .rodata._ZN4cuda3std3__45__cpo6cbeginE,"aG",@progbits,_ZN4cuda3std3__45__cpo6cbeginE,comdat
.type _ZN4cuda3std3__45__cpo6cbeginE, @gnu_unique_object
.size _ZN4cuda3std3__45__cpo6cbeginE, 1
_ZN4cuda3std3__45__cpo6cbeginE:
.zero 1
.weak _ZN4cuda3std3__45__cpo3endE
.section .rodata._ZN4cuda3std3__45__cpo3endE,"aG",@progbits,_ZN4cuda3std3__45__cpo3endE,comdat
.type _ZN4cuda3std3__45__cpo3endE, @gnu_unique_object
.size _ZN4cuda3std3__45__cpo3endE, 1
_ZN4cuda3std3__45__cpo3endE:
.zero 1
.weak _ZN4cuda3std3__45__cpo5beginE
.section .rodata._ZN4cuda3std3__45__cpo5beginE,"aG",@progbits,_ZN4cuda3std3__45__cpo5beginE,comdat
.type _ZN4cuda3std3__45__cpo5beginE, @gnu_unique_object
.size _ZN4cuda3std3__45__cpo5beginE, 1
_ZN4cuda3std3__45__cpo5beginE:
.zero 1
.weak _ZN4cuda3std3__419piecewise_constructE
.section .rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
.type _ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
.size _ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo9iter_moveE
.section .rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
.type _ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
.zero 1
.weak _ZN4cuda3std6ranges3__45__cpo4swapE
.section .rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
.type _ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
.size _ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
.zero 1
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "newton_solver.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <math.h>
#define N 4096
#define BLOCK_DIM 32
__global__ void matAdd(float *a, float *b, float *c){
int i = threadIdx.x + blockIdx.x * blockDim.x;
int j = threadIdx.y + blockIdx.y * blockDim.y;
if(i < N && j < N){
c[i * N + j] = a[i * N + j] + b[i * N + j];
}
}
int main(void){
float *dev_x, *dev_y, *dev_z;
float *x, *y, *z;
long long size = N * N * sizeof(float);
cudaMalloc((void **)&dev_x, size);
cudaMalloc((void **)&dev_y, size);
cudaMalloc((void **)&dev_z, size);
x = (float *)malloc(size);
y = (float *)malloc(size);
z = (float *)malloc(size);
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
x[i*N + j] = 1;
y[i*N + j] = 1;
}
}
cudaMemcpy(dev_x, x, size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_y, y, size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_z, z, size, cudaMemcpyHostToDevice);
// FIGURE OUT BLOCK_DIM
dim3 block(BLOCK_DIM, BLOCK_DIM);
dim3 grid((int)(N/block.x), (int)(N/block.y));
matAdd<<<grid, block>>>(dev_x, dev_y, dev_z);
cudaMemcpy(z, dev_z, size, cudaMemcpyDeviceToHost);
printf("%f ", z[3]);
float maxError = 0;
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
maxError = fmax(maxError, fabs(z[i*N + j] - 2));
}
}
std::cout << "Error: " << maxError << std::endl;
cudaFree(dev_x);
cudaFree(dev_y);
cudaFree(dev_z);
free(x);
free(y);
free(z);
return 0;
} | code for sm_80
Function : _Z6matAddPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GT.AND P0, PT, R3, 0xfff, PT ; /* 0x00000fff0300780c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GT.OR P0, PT, R0, 0xfff, P0 ; /* 0x00000fff0000780c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ LEA R0, R0, R3, 0xc ; /* 0x0000000300007211 */
/* 0x000fe200078e60ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*0120*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <math.h>
#define N 4096
#define BLOCK_DIM 32
__global__ void matAdd(float *a, float *b, float *c){
int i = threadIdx.x + blockIdx.x * blockDim.x;
int j = threadIdx.y + blockIdx.y * blockDim.y;
if(i < N && j < N){
c[i * N + j] = a[i * N + j] + b[i * N + j];
}
}
int main(void){
float *dev_x, *dev_y, *dev_z;
float *x, *y, *z;
long long size = N * N * sizeof(float);
cudaMalloc((void **)&dev_x, size);
cudaMalloc((void **)&dev_y, size);
cudaMalloc((void **)&dev_z, size);
x = (float *)malloc(size);
y = (float *)malloc(size);
z = (float *)malloc(size);
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
x[i*N + j] = 1;
y[i*N + j] = 1;
}
}
cudaMemcpy(dev_x, x, size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_y, y, size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_z, z, size, cudaMemcpyHostToDevice);
// FIGURE OUT BLOCK_DIM
dim3 block(BLOCK_DIM, BLOCK_DIM);
dim3 grid((int)(N/block.x), (int)(N/block.y));
matAdd<<<grid, block>>>(dev_x, dev_y, dev_z);
cudaMemcpy(z, dev_z, size, cudaMemcpyDeviceToHost);
printf("%f ", z[3]);
float maxError = 0;
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
maxError = fmax(maxError, fabs(z[i*N + j] - 2));
}
}
std::cout << "Error: " << maxError << std::endl;
cudaFree(dev_x);
cudaFree(dev_y);
cudaFree(dev_z);
free(x);
free(y);
free(z);
return 0;
} | .file "tmpxft_001127ff_00000000-6_matrixAddGPU.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6matAddPfS_S_PfS_S_
.type _Z29__device_stub__Z6matAddPfS_S_PfS_S_, @function
_Z29__device_stub__Z6matAddPfS_S_PfS_S_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6matAddPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z29__device_stub__Z6matAddPfS_S_PfS_S_, .-_Z29__device_stub__Z6matAddPfS_S_PfS_S_
.globl _Z6matAddPfS_S_
.type _Z6matAddPfS_S_, @function
_Z6matAddPfS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6matAddPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z6matAddPfS_S_, .-_Z6matAddPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%f "
.LC5:
.string "Error: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl $67108864, %edi
call malloc@PLT
movq %rax, %r13
movl $67108864, %edi
call malloc@PLT
movq %rax, %r12
movl $67108864, %edi
call malloc@PLT
movq %rax, %r15
movl $16384, %edx
movss .LC1(%rip), %xmm0
.L12:
leaq -16384(%rdx), %rax
.L13:
movss %xmm0, 0(%r13,%rax)
movss %xmm0, (%r12,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L13
addq $16384, %rdx
cmpq $67125248, %rdx
jne .L12
movl $1, %ecx
movl $67108864, %edx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $67108864, %edx
movq %r12, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $67108864, %edx
movq %r15, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 60(%rsp)
movl $128, 64(%rsp)
movl $32, 48(%rsp)
movl $32, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L15:
movl $2, %ecx
movl $67108864, %edx
movq 40(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%r15), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 16384(%r15), %rbp
leaq 67125248(%r15), %r14
movl $0x00000000, 12(%rsp)
.L16:
leaq -16384(%rbp), %rbx
.L17:
movss (%rbx), %xmm0
subss .LC3(%rip), %xmm0
andps .LC4(%rip), %xmm0
movss 12(%rsp), %xmm1
call fmaxf@PLT
movss %xmm0, 12(%rsp)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L17
addq $16384, %rbp
cmpq %r14, %rbp
jne .L16
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z29__device_stub__Z6matAddPfS_S_PfS_S_
jmp .L15
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z6matAddPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z6matAddPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC3:
.long 1073741824
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <math.h>
#define N 4096
#define BLOCK_DIM 32
__global__ void matAdd(float *a, float *b, float *c){
int i = threadIdx.x + blockIdx.x * blockDim.x;
int j = threadIdx.y + blockIdx.y * blockDim.y;
if(i < N && j < N){
c[i * N + j] = a[i * N + j] + b[i * N + j];
}
}
int main(void){
float *dev_x, *dev_y, *dev_z;
float *x, *y, *z;
long long size = N * N * sizeof(float);
cudaMalloc((void **)&dev_x, size);
cudaMalloc((void **)&dev_y, size);
cudaMalloc((void **)&dev_z, size);
x = (float *)malloc(size);
y = (float *)malloc(size);
z = (float *)malloc(size);
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
x[i*N + j] = 1;
y[i*N + j] = 1;
}
}
cudaMemcpy(dev_x, x, size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_y, y, size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_z, z, size, cudaMemcpyHostToDevice);
// FIGURE OUT BLOCK_DIM
dim3 block(BLOCK_DIM, BLOCK_DIM);
dim3 grid((int)(N/block.x), (int)(N/block.y));
matAdd<<<grid, block>>>(dev_x, dev_y, dev_z);
cudaMemcpy(z, dev_z, size, cudaMemcpyDeviceToHost);
printf("%f ", z[3]);
float maxError = 0;
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
maxError = fmax(maxError, fabs(z[i*N + j] - 2));
}
}
std::cout << "Error: " << maxError << std::endl;
cudaFree(dev_x);
cudaFree(dev_y);
cudaFree(dev_z);
free(x);
free(y);
free(z);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#define N 4096
#define BLOCK_DIM 32
__global__ void matAdd(float *a, float *b, float *c){
int i = threadIdx.x + blockIdx.x * blockDim.x;
int j = threadIdx.y + blockIdx.y * blockDim.y;
if(i < N && j < N){
c[i * N + j] = a[i * N + j] + b[i * N + j];
}
}
int main(void){
float *dev_x, *dev_y, *dev_z;
float *x, *y, *z;
long long size = N * N * sizeof(float);
hipMalloc((void **)&dev_x, size);
hipMalloc((void **)&dev_y, size);
hipMalloc((void **)&dev_z, size);
x = (float *)malloc(size);
y = (float *)malloc(size);
z = (float *)malloc(size);
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
x[i*N + j] = 1;
y[i*N + j] = 1;
}
}
hipMemcpy(dev_x, x, size, hipMemcpyHostToDevice);
hipMemcpy(dev_y, y, size, hipMemcpyHostToDevice);
hipMemcpy(dev_z, z, size, hipMemcpyHostToDevice);
// FIGURE OUT BLOCK_DIM
dim3 block(BLOCK_DIM, BLOCK_DIM);
dim3 grid((int)(N/block.x), (int)(N/block.y));
matAdd<<<grid, block>>>(dev_x, dev_y, dev_z);
hipMemcpy(z, dev_z, size, hipMemcpyDeviceToHost);
printf("%f ", z[3]);
float maxError = 0;
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
maxError = fmax(maxError, fabs(z[i*N + j] - 2));
}
}
std::cout << "Error: " << maxError << std::endl;
hipFree(dev_x);
hipFree(dev_y);
hipFree(dev_z);
free(x);
free(y);
free(z);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#define N 4096
#define BLOCK_DIM 32
__global__ void matAdd(float *a, float *b, float *c){
int i = threadIdx.x + blockIdx.x * blockDim.x;
int j = threadIdx.y + blockIdx.y * blockDim.y;
if(i < N && j < N){
c[i * N + j] = a[i * N + j] + b[i * N + j];
}
}
int main(void){
float *dev_x, *dev_y, *dev_z;
float *x, *y, *z;
long long size = N * N * sizeof(float);
hipMalloc((void **)&dev_x, size);
hipMalloc((void **)&dev_y, size);
hipMalloc((void **)&dev_z, size);
x = (float *)malloc(size);
y = (float *)malloc(size);
z = (float *)malloc(size);
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
x[i*N + j] = 1;
y[i*N + j] = 1;
}
}
hipMemcpy(dev_x, x, size, hipMemcpyHostToDevice);
hipMemcpy(dev_y, y, size, hipMemcpyHostToDevice);
hipMemcpy(dev_z, z, size, hipMemcpyHostToDevice);
// FIGURE OUT BLOCK_DIM
dim3 block(BLOCK_DIM, BLOCK_DIM);
dim3 grid((int)(N/block.x), (int)(N/block.y));
matAdd<<<grid, block>>>(dev_x, dev_y, dev_z);
hipMemcpy(z, dev_z, size, hipMemcpyDeviceToHost);
printf("%f ", z[3]);
float maxError = 0;
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
maxError = fmax(maxError, fabs(z[i*N + j] - 2));
}
}
std::cout << "Error: " << maxError << std::endl;
hipFree(dev_x);
hipFree(dev_y);
hipFree(dev_z);
free(x);
free(y);
free(z);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6matAddPfS_S_
.globl _Z6matAddPfS_S_
.p2align 8
.type _Z6matAddPfS_S_,@function
_Z6matAddPfS_S_:
s_load_b32 s2, s[0:1], 0x24
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x1000, v2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshl_add_u32 v0, v0, 12, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6matAddPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6matAddPfS_S_, .Lfunc_end0-_Z6matAddPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6matAddPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6matAddPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#define N 4096
#define BLOCK_DIM 32
__global__ void matAdd(float *a, float *b, float *c){
int i = threadIdx.x + blockIdx.x * blockDim.x;
int j = threadIdx.y + blockIdx.y * blockDim.y;
if(i < N && j < N){
c[i * N + j] = a[i * N + j] + b[i * N + j];
}
}
int main(void){
float *dev_x, *dev_y, *dev_z;
float *x, *y, *z;
long long size = N * N * sizeof(float);
hipMalloc((void **)&dev_x, size);
hipMalloc((void **)&dev_y, size);
hipMalloc((void **)&dev_z, size);
x = (float *)malloc(size);
y = (float *)malloc(size);
z = (float *)malloc(size);
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
x[i*N + j] = 1;
y[i*N + j] = 1;
}
}
hipMemcpy(dev_x, x, size, hipMemcpyHostToDevice);
hipMemcpy(dev_y, y, size, hipMemcpyHostToDevice);
hipMemcpy(dev_z, z, size, hipMemcpyHostToDevice);
// FIGURE OUT BLOCK_DIM
dim3 block(BLOCK_DIM, BLOCK_DIM);
dim3 grid((int)(N/block.x), (int)(N/block.y));
matAdd<<<grid, block>>>(dev_x, dev_y, dev_z);
hipMemcpy(z, dev_z, size, hipMemcpyDeviceToHost);
printf("%f ", z[3]);
float maxError = 0;
for(int i = 0; i < N; i++){
for(int j = 0; j < N; j++){
maxError = fmax(maxError, fabs(z[i*N + j] - 2));
}
}
std::cout << "Error: " << maxError << std::endl;
hipFree(dev_x);
hipFree(dev_y);
hipFree(dev_z);
free(x);
free(y);
free(z);
return 0;
} | .text
.file "matrixAddGPU.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__matAddPfS_S_ # -- Begin function _Z21__device_stub__matAddPfS_S_
.p2align 4, 0x90
.type _Z21__device_stub__matAddPfS_S_,@function
_Z21__device_stub__matAddPfS_S_: # @_Z21__device_stub__matAddPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6matAddPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__matAddPfS_S_, .Lfunc_end0-_Z21__device_stub__matAddPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0xc0000000 # float -2
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %rbx
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r14
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r15
xorl %eax, %eax
movq %rbx, %rcx
movq %r14, %rdx
.p2align 4, 0x90
.LBB1_1: # %.preheader49
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $1065353216, (%rcx,%rsi,4) # imm = 0x3F800000
movl $1065353216, (%rdx,%rsi,4) # imm = 0x3F800000
incq %rsi
cmpq $4096, %rsi # imm = 0x1000
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rax
addq $16384, %rdx # imm = 0x4000
addq $16384, %rcx # imm = 0x4000
cmpq $4096, %rax # imm = 0x1000
jne .LBB1_1
# %bb.4:
movq 24(%rsp), %rdi
movl $67108864, %edx # imm = 0x4000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $67108864, %edx # imm = 0x4000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $67108864, %edx # imm = 0x4000000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $549755814016, %rdi # imm = 0x8000000080
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6matAddPfS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 8(%rsp), %rsi
movl $67108864, %edx # imm = 0x4000000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movss 12(%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
xorps %xmm5, %xmm5
xorl %eax, %eax
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI1_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movq %r15, %rcx
.p2align 4, 0x90
.LBB1_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
xorl %edx, %edx
movaps %xmm5, %xmm2
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rcx,%rdx,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm2, %xmm2
movaps %xmm2, %xmm4
andps %xmm3, %xmm4
maxss %xmm5, %xmm3
andnps %xmm3, %xmm2
orps %xmm4, %xmm2
movaps %xmm2, %xmm5
incq %rdx
cmpq $4096, %rdx # imm = 0x1000
jne .LBB1_8
# %bb.9: # in Loop: Header=BB1_7 Depth=1
incq %rax
addq $16384, %rcx # imm = 0x4000
cmpq $4096, %rax # imm = 0x1000
jne .LBB1_7
# %bb.10:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $7, %edx
movss %xmm5, 36(%rsp) # 4-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 36(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB1_15
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB1_13
# %bb.12:
movzbl 67(%r12), %ecx
jmp .LBB1_14
.LBB1_13:
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB1_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_15:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6matAddPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6matAddPfS_S_,@object # @_Z6matAddPfS_S_
.section .rodata,"a",@progbits
.globl _Z6matAddPfS_S_
.p2align 3, 0x0
_Z6matAddPfS_S_:
.quad _Z21__device_stub__matAddPfS_S_
.size _Z6matAddPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error: "
.size .L.str.1, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6matAddPfS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__matAddPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6matAddPfS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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