system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6matAddPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GT.AND P0, PT, R3, 0xfff, PT ; /* 0x00000fff0300780c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GT.OR P0, PT, R0, 0xfff, P0 ; /* 0x00000fff0000780c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ LEA R0, R0, R3, 0xc ; /* 0x0000000300007211 */
/* 0x000fe200078e60ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*0120*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6matAddPfS_S_
.globl _Z6matAddPfS_S_
.p2align 8
.type _Z6matAddPfS_S_,@function
_Z6matAddPfS_S_:
s_load_b32 s2, s[0:1], 0x24
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x1000, v2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_lshl_add_u32 v0, v0, 12, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6matAddPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6matAddPfS_S_, .Lfunc_end0-_Z6matAddPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6matAddPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6matAddPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001127ff_00000000-6_matrixAddGPU.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6matAddPfS_S_PfS_S_
.type _Z29__device_stub__Z6matAddPfS_S_PfS_S_, @function
_Z29__device_stub__Z6matAddPfS_S_PfS_S_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6matAddPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z29__device_stub__Z6matAddPfS_S_PfS_S_, .-_Z29__device_stub__Z6matAddPfS_S_PfS_S_
.globl _Z6matAddPfS_S_
.type _Z6matAddPfS_S_, @function
_Z6matAddPfS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6matAddPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z6matAddPfS_S_, .-_Z6matAddPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%f "
.LC5:
.string "Error: "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $67108864, %esi
call cudaMalloc@PLT
movl $67108864, %edi
call malloc@PLT
movq %rax, %r13
movl $67108864, %edi
call malloc@PLT
movq %rax, %r12
movl $67108864, %edi
call malloc@PLT
movq %rax, %r15
movl $16384, %edx
movss .LC1(%rip), %xmm0
.L12:
leaq -16384(%rdx), %rax
.L13:
movss %xmm0, 0(%r13,%rax)
movss %xmm0, (%r12,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L13
addq $16384, %rdx
cmpq $67125248, %rdx
jne .L12
movl $1, %ecx
movl $67108864, %edx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $67108864, %edx
movq %r12, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $67108864, %edx
movq %r15, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 60(%rsp)
movl $128, 64(%rsp)
movl $32, 48(%rsp)
movl $32, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L15:
movl $2, %ecx
movl $67108864, %edx
movq 40(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%r15), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 16384(%r15), %rbp
leaq 67125248(%r15), %r14
movl $0x00000000, 12(%rsp)
.L16:
leaq -16384(%rbp), %rbx
.L17:
movss (%rbx), %xmm0
subss .LC3(%rip), %xmm0
andps .LC4(%rip), %xmm0
movss 12(%rsp), %xmm1
call fmaxf@PLT
movss %xmm0, 12(%rsp)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L17
addq $16384, %rbp
cmpq %r14, %rbp
jne .L16
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z29__device_stub__Z6matAddPfS_S_PfS_S_
jmp .L15
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z6matAddPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z6matAddPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1065353216
.align 4
.LC3:
.long 1073741824
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixAddGPU.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__matAddPfS_S_ # -- Begin function _Z21__device_stub__matAddPfS_S_
.p2align 4, 0x90
.type _Z21__device_stub__matAddPfS_S_,@function
_Z21__device_stub__matAddPfS_S_: # @_Z21__device_stub__matAddPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6matAddPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__matAddPfS_S_, .Lfunc_end0-_Z21__device_stub__matAddPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0xc0000000 # float -2
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $67108864, %esi # imm = 0x4000000
callq hipMalloc
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %rbx
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r14
movl $67108864, %edi # imm = 0x4000000
callq malloc
movq %rax, %r15
xorl %eax, %eax
movq %rbx, %rcx
movq %r14, %rdx
.p2align 4, 0x90
.LBB1_1: # %.preheader49
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $1065353216, (%rcx,%rsi,4) # imm = 0x3F800000
movl $1065353216, (%rdx,%rsi,4) # imm = 0x3F800000
incq %rsi
cmpq $4096, %rsi # imm = 0x1000
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rax
addq $16384, %rdx # imm = 0x4000
addq $16384, %rcx # imm = 0x4000
cmpq $4096, %rax # imm = 0x1000
jne .LBB1_1
# %bb.4:
movq 24(%rsp), %rdi
movl $67108864, %edx # imm = 0x4000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $67108864, %edx # imm = 0x4000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $67108864, %edx # imm = 0x4000000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $549755814016, %rdi # imm = 0x8000000080
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6matAddPfS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 8(%rsp), %rsi
movl $67108864, %edx # imm = 0x4000000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movss 12(%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
xorps %xmm5, %xmm5
xorl %eax, %eax
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps .LCPI1_1(%rip), %xmm1 # xmm1 = [NaN,NaN,NaN,NaN]
movq %r15, %rcx
.p2align 4, 0x90
.LBB1_7: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_8 Depth 2
xorl %edx, %edx
movaps %xmm5, %xmm2
.p2align 4, 0x90
.LBB1_8: # Parent Loop BB1_7 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rcx,%rdx,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
addss %xmm0, %xmm3
andps %xmm1, %xmm3
cmpunordss %xmm2, %xmm2
movaps %xmm2, %xmm4
andps %xmm3, %xmm4
maxss %xmm5, %xmm3
andnps %xmm3, %xmm2
orps %xmm4, %xmm2
movaps %xmm2, %xmm5
incq %rdx
cmpq $4096, %rdx # imm = 0x1000
jne .LBB1_8
# %bb.9: # in Loop: Header=BB1_7 Depth=1
incq %rax
addq $16384, %rcx # imm = 0x4000
cmpq $4096, %rax # imm = 0x1000
jne .LBB1_7
# %bb.10:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $7, %edx
movss %xmm5, 36(%rsp) # 4-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 36(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB1_15
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB1_13
# %bb.12:
movzbl 67(%r12), %ecx
jmp .LBB1_14
.LBB1_13:
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB1_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_15:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6matAddPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6matAddPfS_S_,@object # @_Z6matAddPfS_S_
.section .rodata,"a",@progbits
.globl _Z6matAddPfS_S_
.p2align 3, 0x0
_Z6matAddPfS_S_:
.quad _Z21__device_stub__matAddPfS_S_
.size _Z6matAddPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error: "
.size .L.str.1, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6matAddPfS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__matAddPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6matAddPfS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
using namespace std;
__global__ void channelScaleKernel(float *ptr, int width, int height, float min_val, float scale, float new_min)
{
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if(x < width && y < height)
{
int idx = 3 * (width * y + x);
ptr[idx] = new_min + (ptr[idx] - min_val) * scale;
ptr[idx + 1] = new_min + (ptr[idx + 1] - min_val) * scale;
ptr[idx + 2] = new_min + (ptr[idx + 2] - min_val) * scale;
}
}
extern "C"
void scaleChannels(float *ptr, int width, int height, float min_val, float scale, float new_min)
{
int image_memory = width * height * 3 * sizeof(*ptr);
float *gpuPtr = NULL;
cudaMalloc((void**) &gpuPtr, image_memory);
cudaMemcpy(gpuPtr, ptr, image_memory, cudaMemcpyHostToDevice);
dim3 threads(16, 16);
dim3 blocks((width + threads.x - 1) / threads.x, (height + threads.y - 1) / threads.y);
channelScaleKernel<<<blocks, threads>>>(gpuPtr, width, height, min_val, scale, new_min);
cudaMemcpy(ptr, gpuPtr, image_memory, cudaMemcpyDeviceToHost);
cudaFree(gpuPtr);
} | code for sm_80
Function : _Z18channelScaleKernelPfiifff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x16c], PT ; /* 0x00005b0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x168], P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R0, R3, c[0x0][0x168], R0 ; /* 0x00005a0003007a24 */
/* 0x000fe200078e0200 */
/*00b0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00d0*/ LEA R0, R0, R0, 0x1 ; /* 0x0000000000007211 */
/* 0x000fcc00078e08ff */
/*00e0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00f0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R4, [R2.64+0x4] ; /* 0x0000040402047981 */
/* 0x000ee8000c1e1900 */
/*0110*/ LDG.E R5, [R2.64+0x8] ; /* 0x0000080402057981 */
/* 0x000f22000c1e1900 */
/*0120*/ MOV R9, c[0x0][0x174] ; /* 0x00005d0000097a02 */
/* 0x000fe20000000f00 */
/*0130*/ FADD R0, R0, -c[0x0][0x170] ; /* 0x80005c0000007621 */
/* 0x004fc40000000000 */
/*0140*/ FADD R4, R4, -c[0x0][0x170] ; /* 0x80005c0004047621 */
/* 0x008fe40000000000 */
/*0150*/ FADD R6, R5, -c[0x0][0x170] ; /* 0x80005c0005067621 */
/* 0x010fe40000000000 */
/*0160*/ FFMA R5, R0, R9.reuse, c[0x0][0x178] ; /* 0x00005e0000057623 */
/* 0x080fe40000000009 */
/*0170*/ FFMA R7, R4, R9.reuse, c[0x0][0x178] ; /* 0x00005e0004077623 */
/* 0x080fe40000000009 */
/*0180*/ FFMA R9, R6, R9, c[0x0][0x178] ; /* 0x00005e0006097623 */
/* 0x000fe20000000009 */
/*0190*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*01a0*/ STG.E [R2.64+0x4], R7 ; /* 0x0000040702007986 */
/* 0x000fe8000c101904 */
/*01b0*/ STG.E [R2.64+0x8], R9 ; /* 0x0000080902007986 */
/* 0x000fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
using namespace std;
__global__ void channelScaleKernel(float *ptr, int width, int height, float min_val, float scale, float new_min)
{
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if(x < width && y < height)
{
int idx = 3 * (width * y + x);
ptr[idx] = new_min + (ptr[idx] - min_val) * scale;
ptr[idx + 1] = new_min + (ptr[idx + 1] - min_val) * scale;
ptr[idx + 2] = new_min + (ptr[idx + 2] - min_val) * scale;
}
}
extern "C"
void scaleChannels(float *ptr, int width, int height, float min_val, float scale, float new_min)
{
int image_memory = width * height * 3 * sizeof(*ptr);
float *gpuPtr = NULL;
cudaMalloc((void**) &gpuPtr, image_memory);
cudaMemcpy(gpuPtr, ptr, image_memory, cudaMemcpyHostToDevice);
dim3 threads(16, 16);
dim3 blocks((width + threads.x - 1) / threads.x, (height + threads.y - 1) / threads.y);
channelScaleKernel<<<blocks, threads>>>(gpuPtr, width, height, min_val, scale, new_min);
cudaMemcpy(ptr, gpuPtr, image_memory, cudaMemcpyDeviceToHost);
cudaFree(gpuPtr);
} | .file "tmpxft_00174859_00000000-6_scale_channels.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z18channelScaleKernelPfiifffPfiifff
.type _Z43__device_stub__Z18channelScaleKernelPfiifffPfiifff, @function
_Z43__device_stub__Z18channelScaleKernelPfiifffPfiifff:
.LFB3694:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18channelScaleKernelPfiifff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z43__device_stub__Z18channelScaleKernelPfiifffPfiifff, .-_Z43__device_stub__Z18channelScaleKernelPfiifffPfiifff
.globl _Z18channelScaleKernelPfiifff
.type _Z18channelScaleKernelPfiifff, @function
_Z18channelScaleKernelPfiifff:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z18channelScaleKernelPfiifffPfiifff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z18channelScaleKernelPfiifff, .-_Z18channelScaleKernelPfiifff
.globl scaleChannels
.type scaleChannels, @function
scaleChannels:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r13
movl %esi, %ebp
movl %edx, %r12d
movss %xmm0, 4(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 12(%rsp)
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq $0, 24(%rsp)
movl %esi, %eax
imull %edx, %eax
leal (%rax,%rax,2), %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leal 15(%rbp), %eax
shrl $4, %eax
movl %eax, 44(%rsp)
leal 15(%r12), %eax
shrl $4, %eax
movl %eax, 48(%rsp)
movl $16, 32(%rsp)
movl $16, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movss 12(%rsp), %xmm2
movss 8(%rsp), %xmm1
movss 4(%rsp), %xmm0
movl %r12d, %edx
movl %ebp, %esi
movq 24(%rsp), %rdi
call _Z43__device_stub__Z18channelScaleKernelPfiifffPfiifff
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size scaleChannels, .-scaleChannels
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18channelScaleKernelPfiifff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18channelScaleKernelPfiifff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
using namespace std;
__global__ void channelScaleKernel(float *ptr, int width, int height, float min_val, float scale, float new_min)
{
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if(x < width && y < height)
{
int idx = 3 * (width * y + x);
ptr[idx] = new_min + (ptr[idx] - min_val) * scale;
ptr[idx + 1] = new_min + (ptr[idx + 1] - min_val) * scale;
ptr[idx + 2] = new_min + (ptr[idx + 2] - min_val) * scale;
}
}
extern "C"
void scaleChannels(float *ptr, int width, int height, float min_val, float scale, float new_min)
{
int image_memory = width * height * 3 * sizeof(*ptr);
float *gpuPtr = NULL;
cudaMalloc((void**) &gpuPtr, image_memory);
cudaMemcpy(gpuPtr, ptr, image_memory, cudaMemcpyHostToDevice);
dim3 threads(16, 16);
dim3 blocks((width + threads.x - 1) / threads.x, (height + threads.y - 1) / threads.y);
channelScaleKernel<<<blocks, threads>>>(gpuPtr, width, height, min_val, scale, new_min);
cudaMemcpy(ptr, gpuPtr, image_memory, cudaMemcpyDeviceToHost);
cudaFree(gpuPtr);
} | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
__global__ void channelScaleKernel(float *ptr, int width, int height, float min_val, float scale, float new_min)
{
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if(x < width && y < height)
{
int idx = 3 * (width * y + x);
ptr[idx] = new_min + (ptr[idx] - min_val) * scale;
ptr[idx + 1] = new_min + (ptr[idx + 1] - min_val) * scale;
ptr[idx + 2] = new_min + (ptr[idx + 2] - min_val) * scale;
}
}
extern "C"
void scaleChannels(float *ptr, int width, int height, float min_val, float scale, float new_min)
{
int image_memory = width * height * 3 * sizeof(*ptr);
float *gpuPtr = NULL;
hipMalloc((void**) &gpuPtr, image_memory);
hipMemcpy(gpuPtr, ptr, image_memory, hipMemcpyHostToDevice);
dim3 threads(16, 16);
dim3 blocks((width + threads.x - 1) / threads.x, (height + threads.y - 1) / threads.y);
channelScaleKernel<<<blocks, threads>>>(gpuPtr, width, height, min_val, scale, new_min);
hipMemcpy(ptr, gpuPtr, image_memory, hipMemcpyDeviceToHost);
hipFree(gpuPtr);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
__global__ void channelScaleKernel(float *ptr, int width, int height, float min_val, float scale, float new_min)
{
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if(x < width && y < height)
{
int idx = 3 * (width * y + x);
ptr[idx] = new_min + (ptr[idx] - min_val) * scale;
ptr[idx + 1] = new_min + (ptr[idx + 1] - min_val) * scale;
ptr[idx + 2] = new_min + (ptr[idx + 2] - min_val) * scale;
}
}
extern "C"
void scaleChannels(float *ptr, int width, int height, float min_val, float scale, float new_min)
{
int image_memory = width * height * 3 * sizeof(*ptr);
float *gpuPtr = NULL;
hipMalloc((void**) &gpuPtr, image_memory);
hipMemcpy(gpuPtr, ptr, image_memory, hipMemcpyHostToDevice);
dim3 threads(16, 16);
dim3 blocks((width + threads.x - 1) / threads.x, (height + threads.y - 1) / threads.y);
channelScaleKernel<<<blocks, threads>>>(gpuPtr, width, height, min_val, scale, new_min);
hipMemcpy(ptr, gpuPtr, image_memory, hipMemcpyDeviceToHost);
hipFree(gpuPtr);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18channelScaleKernelPfiifff
.globl _Z18channelScaleKernelPfiifff
.p2align 8
.type _Z18channelScaleKernelPfiifff,@function
_Z18channelScaleKernelPfiifff:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b32 s0, s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v0, v2, 1, v2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v1, vcc_lo
global_load_b96 v[0:2], v[3:4], off
s_waitcnt vmcnt(0)
v_dual_subrev_f32 v0, s4, v0 :: v_dual_subrev_f32 v1, s4, v1
v_subrev_f32_e32 v2, s4, v2
v_fma_f32 v0, v0, s5, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v1, v1, s5, s0
v_fma_f32 v2, v2, s5, s0
global_store_b96 v[3:4], v[0:2], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18channelScaleKernelPfiifff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18channelScaleKernelPfiifff, .Lfunc_end0-_Z18channelScaleKernelPfiifff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18channelScaleKernelPfiifff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18channelScaleKernelPfiifff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
__global__ void channelScaleKernel(float *ptr, int width, int height, float min_val, float scale, float new_min)
{
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
if(x < width && y < height)
{
int idx = 3 * (width * y + x);
ptr[idx] = new_min + (ptr[idx] - min_val) * scale;
ptr[idx + 1] = new_min + (ptr[idx + 1] - min_val) * scale;
ptr[idx + 2] = new_min + (ptr[idx + 2] - min_val) * scale;
}
}
extern "C"
void scaleChannels(float *ptr, int width, int height, float min_val, float scale, float new_min)
{
int image_memory = width * height * 3 * sizeof(*ptr);
float *gpuPtr = NULL;
hipMalloc((void**) &gpuPtr, image_memory);
hipMemcpy(gpuPtr, ptr, image_memory, hipMemcpyHostToDevice);
dim3 threads(16, 16);
dim3 blocks((width + threads.x - 1) / threads.x, (height + threads.y - 1) / threads.y);
channelScaleKernel<<<blocks, threads>>>(gpuPtr, width, height, min_val, scale, new_min);
hipMemcpy(ptr, gpuPtr, image_memory, hipMemcpyDeviceToHost);
hipFree(gpuPtr);
} | .text
.file "scale_channels.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z33__device_stub__channelScaleKernelPfiifff # -- Begin function _Z33__device_stub__channelScaleKernelPfiifff
.p2align 4, 0x90
.type _Z33__device_stub__channelScaleKernelPfiifff,@function
_Z33__device_stub__channelScaleKernelPfiifff: # @_Z33__device_stub__channelScaleKernelPfiifff
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18channelScaleKernelPfiifff, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z33__device_stub__channelScaleKernelPfiifff, .Lfunc_end0-_Z33__device_stub__channelScaleKernelPfiifff
.cfi_endproc
# -- End function
.globl scaleChannels # -- Begin function scaleChannels
.p2align 4, 0x90
.type scaleChannels,@function
scaleChannels: # @scaleChannels
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movss %xmm2, 16(%rsp) # 4-byte Spill
movss %xmm1, 12(%rsp) # 4-byte Spill
movss %xmm0, 8(%rsp) # 4-byte Spill
movl %edx, %r15d
movl %esi, %r12d
movq %rdi, %rbx
movl %esi, %eax
imull %edx, %eax
shll $2, %eax
leal (%rax,%rax,2), %eax
movq $0, (%rsp)
movslq %eax, %r14
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
movq (%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leal 15(%r12), %eax
shrl $4, %eax
leal 15(%r15), %edi
shrl $4, %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rax
movq %rax, 88(%rsp)
movl %r12d, 36(%rsp)
movl %r15d, 32(%rsp)
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 28(%rsp)
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 24(%rsp)
movss 16(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 20(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 36(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rax
movq %rax, 112(%rsp)
leaq 28(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18channelScaleKernelPfiifff, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipFree
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size scaleChannels, .Lfunc_end1-scaleChannels
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18channelScaleKernelPfiifff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18channelScaleKernelPfiifff,@object # @_Z18channelScaleKernelPfiifff
.section .rodata,"a",@progbits
.globl _Z18channelScaleKernelPfiifff
.p2align 3, 0x0
_Z18channelScaleKernelPfiifff:
.quad _Z33__device_stub__channelScaleKernelPfiifff
.size _Z18channelScaleKernelPfiifff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18channelScaleKernelPfiifff"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__channelScaleKernelPfiifff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18channelScaleKernelPfiifff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18channelScaleKernelPfiifff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x16c], PT ; /* 0x00005b0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x168], P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R0, R3, c[0x0][0x168], R0 ; /* 0x00005a0003007a24 */
/* 0x000fe200078e0200 */
/*00b0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00d0*/ LEA R0, R0, R0, 0x1 ; /* 0x0000000000007211 */
/* 0x000fcc00078e08ff */
/*00e0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*00f0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R4, [R2.64+0x4] ; /* 0x0000040402047981 */
/* 0x000ee8000c1e1900 */
/*0110*/ LDG.E R5, [R2.64+0x8] ; /* 0x0000080402057981 */
/* 0x000f22000c1e1900 */
/*0120*/ MOV R9, c[0x0][0x174] ; /* 0x00005d0000097a02 */
/* 0x000fe20000000f00 */
/*0130*/ FADD R0, R0, -c[0x0][0x170] ; /* 0x80005c0000007621 */
/* 0x004fc40000000000 */
/*0140*/ FADD R4, R4, -c[0x0][0x170] ; /* 0x80005c0004047621 */
/* 0x008fe40000000000 */
/*0150*/ FADD R6, R5, -c[0x0][0x170] ; /* 0x80005c0005067621 */
/* 0x010fe40000000000 */
/*0160*/ FFMA R5, R0, R9.reuse, c[0x0][0x178] ; /* 0x00005e0000057623 */
/* 0x080fe40000000009 */
/*0170*/ FFMA R7, R4, R9.reuse, c[0x0][0x178] ; /* 0x00005e0004077623 */
/* 0x080fe40000000009 */
/*0180*/ FFMA R9, R6, R9, c[0x0][0x178] ; /* 0x00005e0006097623 */
/* 0x000fe20000000009 */
/*0190*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*01a0*/ STG.E [R2.64+0x4], R7 ; /* 0x0000040702007986 */
/* 0x000fe8000c101904 */
/*01b0*/ STG.E [R2.64+0x8], R9 ; /* 0x0000080902007986 */
/* 0x000fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18channelScaleKernelPfiifff
.globl _Z18channelScaleKernelPfiifff
.p2align 8
.type _Z18channelScaleKernelPfiifff,@function
_Z18channelScaleKernelPfiifff:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b32 s0, s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v0, v2, 1, v2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v1, vcc_lo
global_load_b96 v[0:2], v[3:4], off
s_waitcnt vmcnt(0)
v_dual_subrev_f32 v0, s4, v0 :: v_dual_subrev_f32 v1, s4, v1
v_subrev_f32_e32 v2, s4, v2
v_fma_f32 v0, v0, s5, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v1, v1, s5, s0
v_fma_f32 v2, v2, s5, s0
global_store_b96 v[3:4], v[0:2], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18channelScaleKernelPfiifff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18channelScaleKernelPfiifff, .Lfunc_end0-_Z18channelScaleKernelPfiifff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18channelScaleKernelPfiifff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18channelScaleKernelPfiifff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00174859_00000000-6_scale_channels.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z18channelScaleKernelPfiifffPfiifff
.type _Z43__device_stub__Z18channelScaleKernelPfiifffPfiifff, @function
_Z43__device_stub__Z18channelScaleKernelPfiifffPfiifff:
.LFB3694:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18channelScaleKernelPfiifff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z43__device_stub__Z18channelScaleKernelPfiifffPfiifff, .-_Z43__device_stub__Z18channelScaleKernelPfiifffPfiifff
.globl _Z18channelScaleKernelPfiifff
.type _Z18channelScaleKernelPfiifff, @function
_Z18channelScaleKernelPfiifff:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z18channelScaleKernelPfiifffPfiifff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z18channelScaleKernelPfiifff, .-_Z18channelScaleKernelPfiifff
.globl scaleChannels
.type scaleChannels, @function
scaleChannels:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r13
movl %esi, %ebp
movl %edx, %r12d
movss %xmm0, 4(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 12(%rsp)
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq $0, 24(%rsp)
movl %esi, %eax
imull %edx, %eax
leal (%rax,%rax,2), %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leal 15(%rbp), %eax
shrl $4, %eax
movl %eax, 44(%rsp)
leal 15(%r12), %eax
shrl $4, %eax
movl %eax, 48(%rsp)
movl $16, 32(%rsp)
movl $16, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movss 12(%rsp), %xmm2
movss 8(%rsp), %xmm1
movss 4(%rsp), %xmm0
movl %r12d, %edx
movl %ebp, %esi
movq 24(%rsp), %rdi
call _Z43__device_stub__Z18channelScaleKernelPfiifffPfiifff
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size scaleChannels, .-scaleChannels
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18channelScaleKernelPfiifff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18channelScaleKernelPfiifff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "scale_channels.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z33__device_stub__channelScaleKernelPfiifff # -- Begin function _Z33__device_stub__channelScaleKernelPfiifff
.p2align 4, 0x90
.type _Z33__device_stub__channelScaleKernelPfiifff,@function
_Z33__device_stub__channelScaleKernelPfiifff: # @_Z33__device_stub__channelScaleKernelPfiifff
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18channelScaleKernelPfiifff, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z33__device_stub__channelScaleKernelPfiifff, .Lfunc_end0-_Z33__device_stub__channelScaleKernelPfiifff
.cfi_endproc
# -- End function
.globl scaleChannels # -- Begin function scaleChannels
.p2align 4, 0x90
.type scaleChannels,@function
scaleChannels: # @scaleChannels
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movss %xmm2, 16(%rsp) # 4-byte Spill
movss %xmm1, 12(%rsp) # 4-byte Spill
movss %xmm0, 8(%rsp) # 4-byte Spill
movl %edx, %r15d
movl %esi, %r12d
movq %rdi, %rbx
movl %esi, %eax
imull %edx, %eax
shll $2, %eax
leal (%rax,%rax,2), %eax
movq $0, (%rsp)
movslq %eax, %r14
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
movq (%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leal 15(%r12), %eax
shrl $4, %eax
leal 15(%r15), %edi
shrl $4, %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rax
movq %rax, 88(%rsp)
movl %r12d, 36(%rsp)
movl %r15d, 32(%rsp)
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 28(%rsp)
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 24(%rsp)
movss 16(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 20(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 36(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rax
movq %rax, 112(%rsp)
leaq 28(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18channelScaleKernelPfiifff, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rdi
callq hipFree
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size scaleChannels, .Lfunc_end1-scaleChannels
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18channelScaleKernelPfiifff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18channelScaleKernelPfiifff,@object # @_Z18channelScaleKernelPfiifff
.section .rodata,"a",@progbits
.globl _Z18channelScaleKernelPfiifff
.p2align 3, 0x0
_Z18channelScaleKernelPfiifff:
.quad _Z33__device_stub__channelScaleKernelPfiifff
.size _Z18channelScaleKernelPfiifff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18channelScaleKernelPfiifff"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__channelScaleKernelPfiifff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18channelScaleKernelPfiifff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #pragma once
#include "Vector3.cuh.cu"
#include "Ray.cuh.cu"
namespace RayTracing
{
class Camera
{
private:
Point3 m_lookAt;
Point3 m_lookFrom;
Vector3 m_viewportHorizontal;
Vector3 m_viewportVertical;
float m_viewportHeight;
float m_viewportWidth;
Point3 m_lowerLeftCorner;
public:
Camera(
const int width,
const int height,
const float horizontalViewDegrees,
const Point3 &lookAt=Point3(),
const Point3 &lookFrom=Point3()
);
void LookAt(
const Point3 &lookAt,
const Point3 &lookFrom
);
Ray GetRay(const float w, const float h) const;
};
} // namespace RayTracing | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #pragma once
#include "Vector3.cuh.cu"
#include "Ray.cuh.cu"
namespace RayTracing
{
class Camera
{
private:
Point3 m_lookAt;
Point3 m_lookFrom;
Vector3 m_viewportHorizontal;
Vector3 m_viewportVertical;
float m_viewportHeight;
float m_viewportWidth;
Point3 m_lowerLeftCorner;
public:
Camera(
const int width,
const int height,
const float horizontalViewDegrees,
const Point3 &lookAt=Point3(),
const Point3 &lookFrom=Point3()
);
void LookAt(
const Point3 &lookAt,
const Point3 &lookFrom
);
Ray GetRay(const float w, const float h) const;
};
} // namespace RayTracing | .file "tmpxft_0011f9dc_00000000-6_Camera.cuh.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3687:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3687:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3710:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3710:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #pragma once
#include "Vector3.cuh.cu"
#include "Ray.cuh.cu"
namespace RayTracing
{
class Camera
{
private:
Point3 m_lookAt;
Point3 m_lookFrom;
Vector3 m_viewportHorizontal;
Vector3 m_viewportVertical;
float m_viewportHeight;
float m_viewportWidth;
Point3 m_lowerLeftCorner;
public:
Camera(
const int width,
const int height,
const float horizontalViewDegrees,
const Point3 &lookAt=Point3(),
const Point3 &lookFrom=Point3()
);
void LookAt(
const Point3 &lookAt,
const Point3 &lookFrom
);
Ray GetRay(const float w, const float h) const;
};
} // namespace RayTracing | #pragma once
#include <hip/hip_runtime.h>
#include "Vector3.cuh.cu"
#include "Ray.cuh.cu"
namespace RayTracing
{
class Camera
{
private:
Point3 m_lookAt;
Point3 m_lookFrom;
Vector3 m_viewportHorizontal;
Vector3 m_viewportVertical;
float m_viewportHeight;
float m_viewportWidth;
Point3 m_lowerLeftCorner;
public:
Camera(
const int width,
const int height,
const float horizontalViewDegrees,
const Point3 &lookAt=Point3(),
const Point3 &lookFrom=Point3()
);
void LookAt(
const Point3 &lookAt,
const Point3 &lookFrom
);
Ray GetRay(const float w, const float h) const;
};
} // namespace RayTracing |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #pragma once
#include <hip/hip_runtime.h>
#include "Vector3.cuh.cu"
#include "Ray.cuh.cu"
namespace RayTracing
{
class Camera
{
private:
Point3 m_lookAt;
Point3 m_lookFrom;
Vector3 m_viewportHorizontal;
Vector3 m_viewportVertical;
float m_viewportHeight;
float m_viewportWidth;
Point3 m_lowerLeftCorner;
public:
Camera(
const int width,
const int height,
const float horizontalViewDegrees,
const Point3 &lookAt=Point3(),
const Point3 &lookFrom=Point3()
);
void LookAt(
const Point3 &lookAt,
const Point3 &lookFrom
);
Ray GetRay(const float w, const float h) const;
};
} // namespace RayTracing | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #pragma once
#include <hip/hip_runtime.h>
#include "Vector3.cuh.cu"
#include "Ray.cuh.cu"
namespace RayTracing
{
class Camera
{
private:
Point3 m_lookAt;
Point3 m_lookFrom;
Vector3 m_viewportHorizontal;
Vector3 m_viewportVertical;
float m_viewportHeight;
float m_viewportWidth;
Point3 m_lowerLeftCorner;
public:
Camera(
const int width,
const int height,
const float horizontalViewDegrees,
const Point3 &lookAt=Point3(),
const Point3 &lookFrom=Point3()
);
void LookAt(
const Point3 &lookAt,
const Point3 &lookFrom
);
Ray GetRay(const float w, const float h) const;
};
} // namespace RayTracing | .text
.file "Camera.cuh.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011f9dc_00000000-6_Camera.cuh.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3687:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3687:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3710:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3710:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Camera.cuh.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/resource.h>
#define NewArray(Type, N) ((Type *)(malloc(N*sizeof(Type))))
#define cudaTry(cudaStatus) _cudaTry(cudaStatus, __FILE__, __LINE__)
void _cudaTry(cudaError_t cudaStatus, const char *fileName, int lineNumber) {
if(cudaStatus != cudaSuccess) {
fprintf(stderr, "%s in %s line %d\n",
cudaGetErrorString(cudaStatus), fileName, lineNumber);
exit(1);
}
}
__global__ void f_kernel(uint n, uint m, float *x, float *xm) {
uint i = blockIdx.x*blockDim.x + threadIdx.x; // nvcc built-ins
if(i < n) {
float a = 5.0/2.0;
float y = x[i];
for(uint j = 0; j < m; j++) {
y = a*(y*y*y - y);
}
xm[i] = y;
}
}
void f(float *x, float *xm, uint n, uint m) {
int size = n*sizeof(float);
float *dev_x, *dev_xm;
cudaTry(cudaMalloc((void**)(&dev_x), size));
cudaTry(cudaMalloc((void**)(&dev_xm), size));
cudaTry(cudaMemcpy(dev_x, x, size, cudaMemcpyHostToDevice));
f_kernel<<<ceil(n/256.0),256>>>(n, m, dev_x, dev_xm);
cudaTry(cudaMemcpy(xm, dev_xm, size, cudaMemcpyDeviceToHost));
cudaTry(cudaFree(dev_x));
cudaTry(cudaFree(dev_xm));
}
void f_cpu(float *x, float *xm, uint n, uint m) {
float a = 5.0/2.0;
for(uint i = 0; i < n; i++) {
float y = x[i];
for(uint j = 0; j < m; j++)
y = a*(y*y*y - y);
x[i] = y;
}
}
void f_test(uint n, uint m, int gpu_flag) {
float *x, *xm;
struct rusage r0, r1;
x = NewArray(float, n);
xm = NewArray(float, n);
for(uint i = 0; i < n; i++)
x[i] = (1.0+i)/(n+1);
getrusage(RUSAGE_SELF, &r0);
if(gpu_flag) f(x, xm, n, m);
else f_cpu(x, xm, n, m);
getrusage(RUSAGE_SELF, &r1);
double t_elapsed = (r1.ru_utime.tv_sec - r0.ru_utime.tv_sec)
+ 1e-6*(r1.ru_utime.tv_usec - r0.ru_utime.tv_usec);
printf("f%s(n, ...): t_elapsed = %10.3e, throughput = %10.3e\n",
gpu_flag ? "" : "_cpu", t_elapsed, n*m/t_elapsed);
}
__global__ void saxpy_kernel(uint n, float a, float *x, float *y) {
uint i = blockIdx.x*blockDim.x + threadIdx.x; // nvcc built-ins
if(i < n) {
float yi = y[i];
float xi = x[i];
float out;
//for (int j=0; j<10; j++) {
out = a*xi + yi;
//}
y[i] = out;
}
}
void saxpy(uint n, float a, float *x, float *y) {
int size = n*sizeof(float);
float *dev_x, *dev_y; // will be allocated on the GPU.
cudaTry(cudaMalloc((void**)(&dev_x), size));
cudaTry(cudaMalloc((void**)(&dev_y), size));
cudaTry(cudaMemcpy(dev_x, x, size, cudaMemcpyHostToDevice));
cudaTry(cudaMemcpy(dev_y, y, size, cudaMemcpyHostToDevice));
saxpy_kernel<<<ceil(n/256.0),256>>>(n, a, dev_x, dev_y);
cudaTry(cudaMemcpy(y, dev_y, size, cudaMemcpyDeviceToHost));
cudaTry(cudaFree(dev_x));
cudaTry(cudaFree(dev_y));
}
void saxpy_cpu(uint n, float a, float *x, float *y) {
for (int i=0; i< n; i++) {
float yi = y[i];
float xi = x[i];
float out;
//for (int j = 0; j<10; j++) {
out = a*xi + yi;
//}
y[i] = out;
}
}
void saxpy_test(uint n, float a, int gpu_flag) {
float *x, *y;
struct rusage r0, r1;
x = NewArray(float, n);
y = NewArray(float, n);
for(uint i = 0; i < n; i++) {
x[i] = i;
y[i] = i*i;
}
getrusage(RUSAGE_SELF, &r0);
if(gpu_flag) saxpy(n, a, x, y);
else saxpy_cpu(n, a, x, y);
getrusage(RUSAGE_SELF, &r1);
double t_elapsed = (r1.ru_utime.tv_sec - r0.ru_utime.tv_sec)
+ 1e-6*(r1.ru_utime.tv_usec - r0.ru_utime.tv_usec);
printf("saxpy%s(n, ...): t_elapsed = %10.3e\n",
gpu_flag ? "" : "_cpu", t_elapsed);
}
// f_main: for command lines of the form
// hw4 f n m
// or
// hw4 f_cpu n m
void f_main(int argc, char **argv, int gpu_flag) {
uint n, m;
if(argc != 4) {
fprintf(stderr, "usage: hw4 %s n m\n", argv[1]);
exit(1);
}
n = strtoul(argv[2], NULL, 10);
m = strtoul(argv[3], NULL, 10);
f_test(n, m, gpu_flag);
}
// saxpy_main: for command lines of the form
// hw4 saxpy n [a]
// or
// hw4 saxpy n [a]
// The parameter 'a' is optional. If omitted, we set a=3.0.
void saxpy_main(int argc, char **argv, int gpu_flag) {
int n;
float a;
if((argc < 3) || (4 < argc)) {
fprintf(stderr, "usage: hw4 saxpy n [a]\n");
exit(1);
}
n = strtoul(argv[2], NULL, 10);
if(argc >= 4) a = atof(argv[3]);
else a = 3.0;
saxpy_test(n, a, gpu_flag);
}
int main(int argc, char **argv) {
if(argc < 2) {
fprintf(stderr, "usage: hw4 testName testArgs\n");
exit(1);
}
if(strcmp(argv[1], "f") == 0) f_main(argc, argv, true);
else if(strcmp(argv[1], "f_cpu") == 0) f_main(argc, argv, false);
else if(strcmp(argv[1], "saxpy") == 0) saxpy_main(argc, argv, true);
else if(strcmp(argv[1], "saxpy_cpu") == 0) saxpy_main(argc, argv, false);
else {
fprintf(stderr, "hw4, unrecognized test case: %s\n", argv[1]);
exit(1);
}
exit(0);
} | code for sm_80
Function : _Z12saxpy_kerneljfPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R4, R2, R3, c[0x0][0x168] ; /* 0x00005a0002047625 */
/* 0x000fc800078e0003 */
/*0090*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fe400078e0003 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FFMA R7, R4, c[0x0][0x164], R7 ; /* 0x0000590004077a23 */
/* 0x004fca0000000007 */
/*00d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8f_kerneljjPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x164], PT ; /* 0x00005900ff007a0c */
/* 0x000fe20003f05270 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0003 */
/*00a0*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000162000c1e1900 */
/*00b0*/ @!P0 BRA 0x800 ; /* 0x0000074000008947 */
/* 0x000fea0003800000 */
/*00c0*/ MOV R2, c[0x0][0x164] ; /* 0x0000590000027a02 */
/* 0x001fc80000000f00 */
/*00d0*/ IADD3 R3, R2.reuse, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fda0003f06070 */
/*0100*/ @!P0 BRA 0x780 ; /* 0x0000067000008947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R6, -R2, c[0x0][0x164], RZ ; /* 0x0000590002067a10 */
/* 0x000fc80007ffe1ff */
/*0120*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f04270 */
/*0130*/ @!P0 BRA 0x690 ; /* 0x0000055000008947 */
/* 0x000fea0003800000 */
/*0140*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0150*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0160*/ @!P1 BRA 0x4b0 ; /* 0x0000034000009947 */
/* 0x000fea0003800000 */
/*0170*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0180*/ FMUL R4, R5, R5 ; /* 0x0000000505047220 */
/* 0x020fe20000400000 */
/*0190*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc60007ffe0ff */
/*01a0*/ FFMA R4, R4, R5, -R5 ; /* 0x0000000504047223 */
/* 0x000fe20000000805 */
/*01b0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fc60003f24270 */
/*01c0*/ FMUL R4, R4, 2.5 ; /* 0x4020000004047820 */
/* 0x000fc80000400000 */
/*01d0*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fc80000400000 */
/*01e0*/ FFMA R3, R4, R3, -R4 ; /* 0x0000000304037223 */
/* 0x000fc80000000804 */
/*01f0*/ FMUL R3, R3, 2.5 ; /* 0x4020000003037820 */
/* 0x000fc80000400000 */
/*0200*/ FMUL R4, R3, R3 ; /* 0x0000000303047220 */
/* 0x000fc80000400000 */
/*0210*/ FFMA R4, R3, R4, -R3 ; /* 0x0000000403047223 */
/* 0x000fc80000000803 */
/*0220*/ FMUL R4, R4, 2.5 ; /* 0x4020000004047820 */
/* 0x000fc80000400000 */
/*0230*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fc80000400000 */
/*0240*/ FFMA R3, R4, R3, -R4 ; /* 0x0000000304037223 */
/* 0x000fc80000000804 */
/*0250*/ FMUL R3, R3, 2.5 ; /* 0x4020000003037820 */
/* 0x000fc80000400000 */
/*0260*/ FMUL R4, R3, R3 ; /* 0x0000000303047220 */
/* 0x000fc80000400000 */
/*0270*/ FFMA R4, R3, R4, -R3 ; /* 0x0000000403047223 */
/* 0x000fc80000000803 */
/*0280*/ FMUL R4, R4, 2.5 ; /* 0x4020000004047820 */
/* 0x000fc80000400000 */
/*0290*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fc80000400000 */
/*02a0*/ FFMA R3, R4, R3, -R4 ; /* 0x0000000304037223 */
/* 0x000fc80000000804 */
/*02b0*/ FMUL R3, R3, 2.5 ; /* 0x4020000003037820 */
/* 0x000fc80000400000 */
/*02c0*/ FMUL R4, R3, R3 ; /* 0x0000000303047220 */
/* 0x000fc80000400000 */
/*02d0*/ FFMA R4, R3, R4, -R3 ; /* 0x0000000403047223 */
/* 0x000fc80000000803 */
/*02e0*/ FMUL R4, R4, 2.5 ; /* 0x4020000004047820 */
/* 0x000fc80000400000 */
/*02f0*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fc80000400000 */
/*0300*/ FFMA R3, R4, R3, -R4 ; /* 0x0000000304037223 */
/* 0x000fc80000000804 */
/*0310*/ FMUL R3, R3, 2.5 ; /* 0x4020000003037820 */
/* 0x000fc80000400000 */
/*0320*/ FMUL R4, R3, R3 ; /* 0x0000000303047220 */
/* 0x000fc80000400000 */
/*0330*/ FFMA R4, R3, R4, -R3 ; /* 0x0000000403047223 */
/* 0x000fc80000000803 */
/*0340*/ FMUL R4, R4, 2.5 ; /* 0x4020000004047820 */
/* 0x000fc80000400000 */
/*0350*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fc80000400000 */
/*0360*/ FFMA R3, R4, R3, -R4 ; /* 0x0000000304037223 */
/* 0x000fc80000000804 */
/*0370*/ FMUL R3, R3, 2.5 ; /* 0x4020000003037820 */
/* 0x000fc80000400000 */
/*0380*/ FMUL R4, R3, R3 ; /* 0x0000000303047220 */
/* 0x000fc80000400000 */
/*0390*/ FFMA R4, R3, R4, -R3 ; /* 0x0000000403047223 */
/* 0x000fc80000000803 */
/*03a0*/ FMUL R4, R4, 2.5 ; /* 0x4020000004047820 */
/* 0x000fc80000400000 */
/*03b0*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fc80000400000 */
/*03c0*/ FFMA R3, R4, R3, -R4 ; /* 0x0000000304037223 */
/* 0x000fc80000000804 */
/*03d0*/ FMUL R3, R3, 2.5 ; /* 0x4020000003037820 */
/* 0x000fc80000400000 */
/*03e0*/ FMUL R4, R3, R3 ; /* 0x0000000303047220 */
/* 0x000fc80000400000 */
/*03f0*/ FFMA R4, R3, R4, -R3 ; /* 0x0000000403047223 */
/* 0x000fc80000000803 */
/*0400*/ FMUL R4, R4, 2.5 ; /* 0x4020000004047820 */
/* 0x000fc80000400000 */
/*0410*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fc80000400000 */
/*0420*/ FFMA R3, R4, R3, -R4 ; /* 0x0000000304037223 */
/* 0x000fc80000000804 */
/*0430*/ FMUL R3, R3, 2.5 ; /* 0x4020000003037820 */
/* 0x000fc80000400000 */
/*0440*/ FMUL R4, R3, R3 ; /* 0x0000000303047220 */
/* 0x000fc80000400000 */
/*0450*/ FFMA R4, R3, R4, -R3 ; /* 0x0000000403047223 */
/* 0x000fc80000000803 */
/*0460*/ FMUL R4, R4, 2.5 ; /* 0x4020000004047820 */
/* 0x000fc80000400000 */
/*0470*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fc80000400000 */
/*0480*/ FFMA R3, R4, R3, -R4 ; /* 0x0000000304037223 */
/* 0x000fc80000000804 */
/*0490*/ FMUL R5, R3, 2.5 ; /* 0x4020000003057820 */
/* 0x000fe20000400000 */
/*04a0*/ @P1 BRA 0x180 ; /* 0xfffffcd000001947 */
/* 0x000fea000383ffff */
/*04b0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*04c0*/ @!P1 BRA 0x670 ; /* 0x000001a000009947 */
/* 0x000fea0003800000 */
/*04d0*/ FMUL R4, R5.reuse, R5 ; /* 0x0000000505047220 */
/* 0x060fe20000400000 */
/*04e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*04f0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0500*/ FFMA R4, R5, R4, -R5 ; /* 0x0000000405047223 */
/* 0x000fc80000000805 */
/*0510*/ FMUL R4, R4, 2.5 ; /* 0x4020000004047820 */
/* 0x000fc80000400000 */
/*0520*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fc80000400000 */
/*0530*/ FFMA R3, R4, R3, -R4 ; /* 0x0000000304037223 */
/* 0x000fc80000000804 */
/*0540*/ FMUL R3, R3, 2.5 ; /* 0x4020000003037820 */
/* 0x000fc80000400000 */
/*0550*/ FMUL R4, R3, R3 ; /* 0x0000000303047220 */
/* 0x000fc80000400000 */
/*0560*/ FFMA R4, R3, R4, -R3 ; /* 0x0000000403047223 */
/* 0x000fc80000000803 */
/*0570*/ FMUL R4, R4, 2.5 ; /* 0x4020000004047820 */
/* 0x000fc80000400000 */
/*0580*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fc80000400000 */
/*0590*/ FFMA R3, R4, R3, -R4 ; /* 0x0000000304037223 */
/* 0x000fc80000000804 */
/*05a0*/ FMUL R3, R3, 2.5 ; /* 0x4020000003037820 */
/* 0x000fc80000400000 */
/*05b0*/ FMUL R4, R3, R3 ; /* 0x0000000303047220 */
/* 0x000fc80000400000 */
/*05c0*/ FFMA R4, R3, R4, -R3 ; /* 0x0000000403047223 */
/* 0x000fc80000000803 */
/*05d0*/ FMUL R4, R4, 2.5 ; /* 0x4020000004047820 */
/* 0x000fc80000400000 */
/*05e0*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fc80000400000 */
/*05f0*/ FFMA R3, R4, R3, -R4 ; /* 0x0000000304037223 */
/* 0x000fc80000000804 */
/*0600*/ FMUL R3, R3, 2.5 ; /* 0x4020000003037820 */
/* 0x000fc80000400000 */
/*0610*/ FMUL R4, R3, R3 ; /* 0x0000000303047220 */
/* 0x000fc80000400000 */
/*0620*/ FFMA R4, R3, R4, -R3 ; /* 0x0000000403047223 */
/* 0x000fc80000000803 */
/*0630*/ FMUL R4, R4, 2.5 ; /* 0x4020000004047820 */
/* 0x000fc80000400000 */
/*0640*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fc80000400000 */
/*0650*/ FFMA R3, R4, R3, -R4 ; /* 0x0000000304037223 */
/* 0x000fc80000000804 */
/*0660*/ FMUL R5, R3, 2.5 ; /* 0x4020000003057820 */
/* 0x000fe40000400000 */
/*0670*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0680*/ @!P0 BRA 0x780 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0690*/ FMUL R4, R5, R5 ; /* 0x0000000505047220 */
/* 0x020fe20000400000 */
/*06a0*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc60007ffe0ff */
/*06b0*/ FFMA R4, R4, R5, -R5 ; /* 0x0000000504047223 */
/* 0x000fe20000000805 */
/*06c0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc60003f05270 */
/*06d0*/ FMUL R4, R4, 2.5 ; /* 0x4020000004047820 */
/* 0x000fc80000400000 */
/*06e0*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fc80000400000 */
/*06f0*/ FFMA R3, R4, R3, -R4 ; /* 0x0000000304037223 */
/* 0x000fc80000000804 */
/*0700*/ FMUL R3, R3, 2.5 ; /* 0x4020000003037820 */
/* 0x000fc80000400000 */
/*0710*/ FMUL R4, R3, R3 ; /* 0x0000000303047220 */
/* 0x000fc80000400000 */
/*0720*/ FFMA R4, R3, R4, -R3 ; /* 0x0000000403047223 */
/* 0x000fc80000000803 */
/*0730*/ FMUL R4, R4, 2.5 ; /* 0x4020000004047820 */
/* 0x000fc80000400000 */
/*0740*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fc80000400000 */
/*0750*/ FFMA R3, R4, R3, -R4 ; /* 0x0000000304037223 */
/* 0x000fc80000000804 */
/*0760*/ FMUL R5, R3, 2.5 ; /* 0x4020000003057820 */
/* 0x000fe20000400000 */
/*0770*/ @P0 BRA 0x690 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*0780*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*0790*/ @!P0 BRA 0x800 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*07a0*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe20007ffe0ff */
/*07b0*/ FMUL R4, R5, R5 ; /* 0x0000000505047220 */
/* 0x020fc60000400000 */
/*07c0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*07d0*/ FFMA R4, R4, R5, -R5 ; /* 0x0000000504047223 */
/* 0x000fc80000000805 */
/*07e0*/ FMUL R5, R4, 2.5 ; /* 0x4020000004057820 */
/* 0x000fd00000400000 */
/*07f0*/ @P0 BRA 0x7a0 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*0800*/ LEA R2, P0, R0, c[0x0][0x170], 0x2 ; /* 0x00005c0000027a11 */
/* 0x001fc800078010ff */
/*0810*/ LEA.HI.X R3, R0, c[0x0][0x174], RZ, 0x2, P0 ; /* 0x00005d0000037a11 */
/* 0x000fca00000f14ff */
/*0820*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x020fe2000c101904 */
/*0830*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0840*/ BRA 0x840; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/resource.h>
#define NewArray(Type, N) ((Type *)(malloc(N*sizeof(Type))))
#define cudaTry(cudaStatus) _cudaTry(cudaStatus, __FILE__, __LINE__)
void _cudaTry(cudaError_t cudaStatus, const char *fileName, int lineNumber) {
if(cudaStatus != cudaSuccess) {
fprintf(stderr, "%s in %s line %d\n",
cudaGetErrorString(cudaStatus), fileName, lineNumber);
exit(1);
}
}
__global__ void f_kernel(uint n, uint m, float *x, float *xm) {
uint i = blockIdx.x*blockDim.x + threadIdx.x; // nvcc built-ins
if(i < n) {
float a = 5.0/2.0;
float y = x[i];
for(uint j = 0; j < m; j++) {
y = a*(y*y*y - y);
}
xm[i] = y;
}
}
void f(float *x, float *xm, uint n, uint m) {
int size = n*sizeof(float);
float *dev_x, *dev_xm;
cudaTry(cudaMalloc((void**)(&dev_x), size));
cudaTry(cudaMalloc((void**)(&dev_xm), size));
cudaTry(cudaMemcpy(dev_x, x, size, cudaMemcpyHostToDevice));
f_kernel<<<ceil(n/256.0),256>>>(n, m, dev_x, dev_xm);
cudaTry(cudaMemcpy(xm, dev_xm, size, cudaMemcpyDeviceToHost));
cudaTry(cudaFree(dev_x));
cudaTry(cudaFree(dev_xm));
}
void f_cpu(float *x, float *xm, uint n, uint m) {
float a = 5.0/2.0;
for(uint i = 0; i < n; i++) {
float y = x[i];
for(uint j = 0; j < m; j++)
y = a*(y*y*y - y);
x[i] = y;
}
}
void f_test(uint n, uint m, int gpu_flag) {
float *x, *xm;
struct rusage r0, r1;
x = NewArray(float, n);
xm = NewArray(float, n);
for(uint i = 0; i < n; i++)
x[i] = (1.0+i)/(n+1);
getrusage(RUSAGE_SELF, &r0);
if(gpu_flag) f(x, xm, n, m);
else f_cpu(x, xm, n, m);
getrusage(RUSAGE_SELF, &r1);
double t_elapsed = (r1.ru_utime.tv_sec - r0.ru_utime.tv_sec)
+ 1e-6*(r1.ru_utime.tv_usec - r0.ru_utime.tv_usec);
printf("f%s(n, ...): t_elapsed = %10.3e, throughput = %10.3e\n",
gpu_flag ? "" : "_cpu", t_elapsed, n*m/t_elapsed);
}
__global__ void saxpy_kernel(uint n, float a, float *x, float *y) {
uint i = blockIdx.x*blockDim.x + threadIdx.x; // nvcc built-ins
if(i < n) {
float yi = y[i];
float xi = x[i];
float out;
//for (int j=0; j<10; j++) {
out = a*xi + yi;
//}
y[i] = out;
}
}
void saxpy(uint n, float a, float *x, float *y) {
int size = n*sizeof(float);
float *dev_x, *dev_y; // will be allocated on the GPU.
cudaTry(cudaMalloc((void**)(&dev_x), size));
cudaTry(cudaMalloc((void**)(&dev_y), size));
cudaTry(cudaMemcpy(dev_x, x, size, cudaMemcpyHostToDevice));
cudaTry(cudaMemcpy(dev_y, y, size, cudaMemcpyHostToDevice));
saxpy_kernel<<<ceil(n/256.0),256>>>(n, a, dev_x, dev_y);
cudaTry(cudaMemcpy(y, dev_y, size, cudaMemcpyDeviceToHost));
cudaTry(cudaFree(dev_x));
cudaTry(cudaFree(dev_y));
}
void saxpy_cpu(uint n, float a, float *x, float *y) {
for (int i=0; i< n; i++) {
float yi = y[i];
float xi = x[i];
float out;
//for (int j = 0; j<10; j++) {
out = a*xi + yi;
//}
y[i] = out;
}
}
void saxpy_test(uint n, float a, int gpu_flag) {
float *x, *y;
struct rusage r0, r1;
x = NewArray(float, n);
y = NewArray(float, n);
for(uint i = 0; i < n; i++) {
x[i] = i;
y[i] = i*i;
}
getrusage(RUSAGE_SELF, &r0);
if(gpu_flag) saxpy(n, a, x, y);
else saxpy_cpu(n, a, x, y);
getrusage(RUSAGE_SELF, &r1);
double t_elapsed = (r1.ru_utime.tv_sec - r0.ru_utime.tv_sec)
+ 1e-6*(r1.ru_utime.tv_usec - r0.ru_utime.tv_usec);
printf("saxpy%s(n, ...): t_elapsed = %10.3e\n",
gpu_flag ? "" : "_cpu", t_elapsed);
}
// f_main: for command lines of the form
// hw4 f n m
// or
// hw4 f_cpu n m
void f_main(int argc, char **argv, int gpu_flag) {
uint n, m;
if(argc != 4) {
fprintf(stderr, "usage: hw4 %s n m\n", argv[1]);
exit(1);
}
n = strtoul(argv[2], NULL, 10);
m = strtoul(argv[3], NULL, 10);
f_test(n, m, gpu_flag);
}
// saxpy_main: for command lines of the form
// hw4 saxpy n [a]
// or
// hw4 saxpy n [a]
// The parameter 'a' is optional. If omitted, we set a=3.0.
void saxpy_main(int argc, char **argv, int gpu_flag) {
int n;
float a;
if((argc < 3) || (4 < argc)) {
fprintf(stderr, "usage: hw4 saxpy n [a]\n");
exit(1);
}
n = strtoul(argv[2], NULL, 10);
if(argc >= 4) a = atof(argv[3]);
else a = 3.0;
saxpy_test(n, a, gpu_flag);
}
int main(int argc, char **argv) {
if(argc < 2) {
fprintf(stderr, "usage: hw4 testName testArgs\n");
exit(1);
}
if(strcmp(argv[1], "f") == 0) f_main(argc, argv, true);
else if(strcmp(argv[1], "f_cpu") == 0) f_main(argc, argv, false);
else if(strcmp(argv[1], "saxpy") == 0) saxpy_main(argc, argv, true);
else if(strcmp(argv[1], "saxpy_cpu") == 0) saxpy_main(argc, argv, false);
else {
fprintf(stderr, "hw4, unrecognized test case: %s\n", argv[1]);
exit(1);
}
exit(0);
} | .file "tmpxft_001a74ec_00000000-6_hw4.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2069:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2069:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s in %s line %d\n"
.text
.globl _Z8_cudaTry9cudaErrorPKci
.type _Z8_cudaTry9cudaErrorPKci, @function
_Z8_cudaTry9cudaErrorPKci:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
ret
.L8:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movl %edx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebp, %r9d
movq %rbx, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z8_cudaTry9cudaErrorPKci, .-_Z8_cudaTry9cudaErrorPKci
.globl _Z5f_cpuPfS_jj
.type _Z5f_cpuPfS_jj, @function
_Z5f_cpuPfS_jj:
.LFB2059:
.cfi_startproc
endbr64
testl %edx, %edx
je .L9
movq %rdi, %rsi
movl %edx, %edx
leaq (%rdi,%rdx,4), %rdi
movss .LC1(%rip), %xmm2
.L13:
movq %rsi, %rdx
movss (%rsi), %xmm1
testl %ecx, %ecx
je .L11
movl $0, %eax
.L12:
movaps %xmm1, %xmm0
mulss %xmm1, %xmm0
mulss %xmm1, %xmm0
subss %xmm1, %xmm0
movaps %xmm0, %xmm1
mulss %xmm2, %xmm1
addl $1, %eax
cmpl %eax, %ecx
jne .L12
.L11:
movss %xmm1, (%rdx)
addq $4, %rsi
cmpq %rdi, %rsi
jne .L13
.L9:
ret
.cfi_endproc
.LFE2059:
.size _Z5f_cpuPfS_jj, .-_Z5f_cpuPfS_jj
.globl _Z9saxpy_cpujfPfS_
.type _Z9saxpy_cpujfPfS_, @function
_Z9saxpy_cpujfPfS_:
.LFB2062:
.cfi_startproc
endbr64
testl %edi, %edi
je .L16
movl %edi, %edi
leaq 0(,%rdi,4), %rcx
movl $0, %eax
.L18:
movaps %xmm0, %xmm1
mulss (%rsi,%rax), %xmm1
addss (%rdx,%rax), %xmm1
movss %xmm1, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L18
.L16:
ret
.cfi_endproc
.LFE2062:
.size _Z9saxpy_cpujfPfS_, .-_Z9saxpy_cpujfPfS_
.globl _Z31__device_stub__Z8f_kerneljjPfS_jjPfS_
.type _Z31__device_stub__Z8f_kerneljjPfS_jjPfS_, @function
_Z31__device_stub__Z8f_kerneljjPfS_jjPfS_:
.LFB2091:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8f_kerneljjPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2091:
.size _Z31__device_stub__Z8f_kerneljjPfS_jjPfS_, .-_Z31__device_stub__Z8f_kerneljjPfS_jjPfS_
.globl _Z8f_kerneljjPfS_
.type _Z8f_kerneljjPfS_, @function
_Z8f_kerneljjPfS_:
.LFB2092:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8f_kerneljjPfS_jjPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _Z8f_kerneljjPfS_, .-_Z8f_kerneljjPfS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "/home/ubuntu/Datasets/stackv2/train-structured/d4l3k/cs418/master/hw4/hw4.cu"
.text
.globl _Z1fPfS_jj
.type _Z1fPfS_jj, @function
_Z1fPfS_jj:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r15
movq %rsi, %r12
movl %edx, %ebp
movl %ecx, %r13d
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leal 0(,%rdx,4), %ebx
movslq %ebx, %rbx
movq %rsp, %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $35, %edx
leaq .LC2(%rip), %r14
movq %r14, %rsi
call _Z8_cudaTry9cudaErrorPKci
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $36, %edx
movq %r14, %rsi
call _Z8_cudaTry9cudaErrorPKci
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $37, %edx
movq %r14, %rsi
call _Z8_cudaTry9cudaErrorPKci
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %ebp, %eax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC3(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC7(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC4(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L31
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC6(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L31:
cvttsd2siq %xmm3, %rax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl 36(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L32:
movl $2, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $41, %edx
leaq .LC2(%rip), %rbx
movq %rbx, %rsi
call _Z8_cudaTry9cudaErrorPKci
movq (%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $42, %edx
movq %rbx, %rsi
call _Z8_cudaTry9cudaErrorPKci
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $43, %edx
movq %rbx, %rsi
call _Z8_cudaTry9cudaErrorPKci
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movl %r13d, %esi
movl %ebp, %edi
call _Z31__device_stub__Z8f_kerneljjPfS_jjPfS_
jmp .L32
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z1fPfS_jj, .-_Z1fPfS_jj
.section .rodata.str1.1
.LC8:
.string "_cpu"
.LC9:
.string ""
.section .rodata.str1.8
.align 8
.LC11:
.string "f%s(n, ...): t_elapsed = %10.3e, throughput = %10.3e\n"
.text
.globl _Z6f_testjji
.type _Z6f_testjji, @function
_Z6f_testjji:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $312, %rsp
.cfi_def_cfa_offset 368
movl %edi, %r12d
movl %esi, %r13d
movl %edx, %r15d
movq %fs:40, %rax
movq %rax, 296(%rsp)
xorl %eax, %eax
movl %edi, %ebp
leaq 0(,%rbp,4), %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r14, %rdi
call malloc@PLT
movq %rax, %r14
testl %r12d, %r12d
je .L38
movl $0, %eax
movsd .LC6(%rip), %xmm2
leal 1(%r12), %edx
pxor %xmm1, %xmm1
cvtsi2sdq %rdx, %xmm1
.L43:
movl %eax, %edx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm2, %xmm0
divsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq %rax, %rbp
jne .L43
.L38:
movq %rsp, %rsi
movl $0, %edi
call getrusage@PLT
testl %r15d, %r15d
je .L44
movl %r13d, %ecx
movl %r12d, %edx
movq %r14, %rsi
movq %rbx, %rdi
call _Z1fPfS_jj
leaq 144(%rsp), %rsi
movl $0, %edi
call getrusage@PLT
movq 152(%rsp), %rax
subq 8(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC10(%rip), %xmm0
movq 144(%rsp), %rax
subq (%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
imull %r12d, %r13d
pxor %xmm1, %xmm1
cvtsi2sdq %r13, %xmm1
divsd %xmm0, %xmm1
leaq .LC9(%rip), %rdx
.L47:
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq 296(%rsp), %rax
subq %fs:40, %rax
jne .L53
addq $312, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
movl %r13d, %ecx
movl %r12d, %edx
movq %r14, %rsi
movq %rbx, %rdi
call _Z5f_cpuPfS_jj
leaq 144(%rsp), %rsi
movl $0, %edi
call getrusage@PLT
movq 152(%rsp), %rax
subq 8(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC10(%rip), %xmm0
movq 144(%rsp), %rax
subq (%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
imull %r13d, %r12d
pxor %xmm1, %xmm1
cvtsi2sdq %r12, %xmm1
divsd %xmm0, %xmm1
leaq .LC8(%rip), %rdx
jmp .L47
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z6f_testjji, .-_Z6f_testjji
.section .rodata.str1.1
.LC12:
.string "usage: hw4 %s n m\n"
.text
.globl _Z6f_mainiPPci
.type _Z6f_mainiPPci, @function
_Z6f_mainiPPci:
.LFB2064:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %rbp
cmpl $4, %edi
jne .L57
movl %edx, %r12d
movq 16(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtoul@PLT
movq %rax, %rbx
movq 24(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtoul@PLT
movl %r12d, %edx
movl %eax, %esi
movl %ebx, %edi
call _Z6f_testjji
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L57:
.cfi_restore_state
movq 8(%rsi), %rcx
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2064:
.size _Z6f_mainiPPci, .-_Z6f_mainiPPci
.globl _Z36__device_stub__Z12saxpy_kerneljfPfS_jfPfS_
.type _Z36__device_stub__Z12saxpy_kerneljfPfS_jfPfS_, @function
_Z36__device_stub__Z12saxpy_kerneljfPfS_jfPfS_:
.LFB2093:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L62
.L58:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L63
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L62:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12saxpy_kerneljfPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L58
.L63:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2093:
.size _Z36__device_stub__Z12saxpy_kerneljfPfS_jfPfS_, .-_Z36__device_stub__Z12saxpy_kerneljfPfS_jfPfS_
.globl _Z12saxpy_kerneljfPfS_
.type _Z12saxpy_kerneljfPfS_, @function
_Z12saxpy_kerneljfPfS_:
.LFB2094:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12saxpy_kerneljfPfS_jfPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2094:
.size _Z12saxpy_kerneljfPfS_, .-_Z12saxpy_kerneljfPfS_
.globl _Z5saxpyjfPfS_
.type _Z5saxpyjfPfS_, @function
_Z5saxpyjfPfS_:
.LFB2061:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movl %edi, %ebp
movss %xmm0, 12(%rsp)
movq %rsi, %r14
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leal 0(,%rdi,4), %ebx
movslq %ebx, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $91, %edx
leaq .LC2(%rip), %r13
movq %r13, %rsi
call _Z8_cudaTry9cudaErrorPKci
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $92, %edx
movq %r13, %rsi
call _Z8_cudaTry9cudaErrorPKci
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $93, %edx
movq %r13, %rsi
call _Z8_cudaTry9cudaErrorPKci
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $94, %edx
movq %r13, %rsi
call _Z8_cudaTry9cudaErrorPKci
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %ebp, %eax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC3(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC7(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC4(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L69
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC6(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L69:
cvttsd2siq %xmm3, %rax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl 52(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L73
.L70:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $98, %edx
leaq .LC2(%rip), %rbx
movq %rbx, %rsi
call _Z8_cudaTry9cudaErrorPKci
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $99, %edx
movq %rbx, %rsi
call _Z8_cudaTry9cudaErrorPKci
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $100, %edx
movq %rbx, %rsi
call _Z8_cudaTry9cudaErrorPKci
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L74
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L73:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movss 12(%rsp), %xmm0
movl %ebp, %edi
call _Z36__device_stub__Z12saxpy_kerneljfPfS_jfPfS_
jmp .L70
.L74:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z5saxpyjfPfS_, .-_Z5saxpyjfPfS_
.section .rodata.str1.8
.align 8
.LC13:
.string "saxpy%s(n, ...): t_elapsed = %10.3e\n"
.text
.globl _Z10saxpy_testjfi
.type _Z10saxpy_testjfi, @function
_Z10saxpy_testjfi:
.LFB2063:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $320, %rsp
.cfi_def_cfa_offset 368
movl %edi, %r13d
movss %xmm0, 12(%rsp)
movl %esi, %r14d
movq %fs:40, %rax
movq %rax, 312(%rsp)
xorl %eax, %eax
movl %edi, %r12d
leaq 0(,%r12,4), %rbp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbp
testl %r13d, %r13d
je .L76
movl $0, %eax
.L81:
movl %eax, %edx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
movss %xmm0, (%rbx,%rax,4)
movl %eax, %edx
imull %eax, %edx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq %rax, %r12
jne .L81
.L76:
leaq 16(%rsp), %rsi
movl $0, %edi
call getrusage@PLT
testl %r14d, %r14d
je .L82
movq %rbp, %rdx
movq %rbx, %rsi
movss 12(%rsp), %xmm0
movl %r13d, %edi
call _Z5saxpyjfPfS_
leaq 160(%rsp), %rsi
movl $0, %edi
call getrusage@PLT
movq 168(%rsp), %rax
subq 24(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC10(%rip), %xmm0
movq 160(%rsp), %rax
subq 16(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
leaq .LC9(%rip), %rdx
.L83:
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 312(%rsp), %rax
subq %fs:40, %rax
jne .L87
addq $320, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L82:
.cfi_restore_state
movq %rbp, %rdx
movq %rbx, %rsi
movss 12(%rsp), %xmm0
movl %r13d, %edi
call _Z9saxpy_cpujfPfS_
leaq 160(%rsp), %rsi
movl $0, %edi
call getrusage@PLT
movq 168(%rsp), %rax
subq 24(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC10(%rip), %xmm0
movq 160(%rsp), %rax
subq 16(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
leaq .LC8(%rip), %rdx
jmp .L83
.L87:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size _Z10saxpy_testjfi, .-_Z10saxpy_testjfi
.section .rodata.str1.1
.LC15:
.string "usage: hw4 saxpy n [a]\n"
.text
.globl _Z10saxpy_mainiPPci
.type _Z10saxpy_mainiPPci, @function
_Z10saxpy_mainiPPci:
.LFB2065:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
leal -3(%rdi), %eax
cmpl $1, %eax
ja .L93
movl %edi, %ebp
movq %rsi, %r12
movl %edx, %r13d
movq 16(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtoul@PLT
movq %rax, %rbx
movss .LC14(%rip), %xmm0
cmpl $3, %ebp
jg .L94
.L90:
movl %r13d, %esi
movl %ebx, %edi
call _Z10saxpy_testjfi
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L93:
.cfi_restore_state
leaq .LC15(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L94:
movq 24(%r12), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
jmp .L90
.cfi_endproc
.LFE2065:
.size _Z10saxpy_mainiPPci, .-_Z10saxpy_mainiPPci
.section .rodata.str1.1
.LC16:
.string "usage: hw4 testName testArgs\n"
.LC17:
.string "f"
.LC18:
.string "f_cpu"
.LC19:
.string "saxpy"
.LC20:
.string "saxpy_cpu"
.section .rodata.str1.8
.align 8
.LC21:
.string "hw4, unrecognized test case: %s\n"
.text
.globl main
.type main, @function
main:
.LFB2066:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
cmpl $1, %edi
jle .L103
movl %edi, %ebx
movq %rsi, %rbp
movq 8(%rsi), %r12
leaq .LC17(%rip), %rsi
movq %r12, %rdi
call strcmp@PLT
testl %eax, %eax
je .L104
leaq .LC18(%rip), %rsi
movq %r12, %rdi
call strcmp@PLT
testl %eax, %eax
je .L105
leaq .LC19(%rip), %rsi
movq %r12, %rdi
call strcmp@PLT
testl %eax, %eax
je .L106
leaq .LC20(%rip), %rsi
movq %r12, %rdi
call strcmp@PLT
testl %eax, %eax
jne .L101
movl $0, %edx
movq %rbp, %rsi
movl %ebx, %edi
call _Z10saxpy_mainiPPci
jmp .L98
.L103:
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L104:
movl $1, %edx
movq %rbp, %rsi
movl %ebx, %edi
call _Z6f_mainiPPci
.L98:
movl $0, %edi
call exit@PLT
.L105:
movl $0, %edx
movq %rbp, %rsi
movl %ebx, %edi
call _Z6f_mainiPPci
jmp .L98
.L106:
movl $1, %edx
movq %rbp, %rsi
movl %ebx, %edi
call _Z10saxpy_mainiPPci
jmp .L98
.L101:
movq %r12, %rcx
leaq .LC21(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2066:
.size main, .-main
.section .rodata.str1.1
.LC22:
.string "_Z12saxpy_kerneljfPfS_"
.LC23:
.string "_Z8f_kerneljjPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2096:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC22(%rip), %rdx
movq %rdx, %rcx
leaq _Z12saxpy_kerneljfPfS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC23(%rip), %rdx
movq %rdx, %rcx
leaq _Z8f_kerneljjPfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1075838976
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1064304640
.align 8
.LC4:
.long 0
.long 1127219200
.align 8
.LC6:
.long 0
.long 1072693248
.align 8
.LC7:
.long -1
.long 2147483647
.align 8
.LC10:
.long -1598689907
.long 1051772663
.section .rodata.cst4
.align 4
.LC14:
.long 1077936128
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/resource.h>
#define NewArray(Type, N) ((Type *)(malloc(N*sizeof(Type))))
#define cudaTry(cudaStatus) _cudaTry(cudaStatus, __FILE__, __LINE__)
void _cudaTry(cudaError_t cudaStatus, const char *fileName, int lineNumber) {
if(cudaStatus != cudaSuccess) {
fprintf(stderr, "%s in %s line %d\n",
cudaGetErrorString(cudaStatus), fileName, lineNumber);
exit(1);
}
}
__global__ void f_kernel(uint n, uint m, float *x, float *xm) {
uint i = blockIdx.x*blockDim.x + threadIdx.x; // nvcc built-ins
if(i < n) {
float a = 5.0/2.0;
float y = x[i];
for(uint j = 0; j < m; j++) {
y = a*(y*y*y - y);
}
xm[i] = y;
}
}
void f(float *x, float *xm, uint n, uint m) {
int size = n*sizeof(float);
float *dev_x, *dev_xm;
cudaTry(cudaMalloc((void**)(&dev_x), size));
cudaTry(cudaMalloc((void**)(&dev_xm), size));
cudaTry(cudaMemcpy(dev_x, x, size, cudaMemcpyHostToDevice));
f_kernel<<<ceil(n/256.0),256>>>(n, m, dev_x, dev_xm);
cudaTry(cudaMemcpy(xm, dev_xm, size, cudaMemcpyDeviceToHost));
cudaTry(cudaFree(dev_x));
cudaTry(cudaFree(dev_xm));
}
void f_cpu(float *x, float *xm, uint n, uint m) {
float a = 5.0/2.0;
for(uint i = 0; i < n; i++) {
float y = x[i];
for(uint j = 0; j < m; j++)
y = a*(y*y*y - y);
x[i] = y;
}
}
void f_test(uint n, uint m, int gpu_flag) {
float *x, *xm;
struct rusage r0, r1;
x = NewArray(float, n);
xm = NewArray(float, n);
for(uint i = 0; i < n; i++)
x[i] = (1.0+i)/(n+1);
getrusage(RUSAGE_SELF, &r0);
if(gpu_flag) f(x, xm, n, m);
else f_cpu(x, xm, n, m);
getrusage(RUSAGE_SELF, &r1);
double t_elapsed = (r1.ru_utime.tv_sec - r0.ru_utime.tv_sec)
+ 1e-6*(r1.ru_utime.tv_usec - r0.ru_utime.tv_usec);
printf("f%s(n, ...): t_elapsed = %10.3e, throughput = %10.3e\n",
gpu_flag ? "" : "_cpu", t_elapsed, n*m/t_elapsed);
}
__global__ void saxpy_kernel(uint n, float a, float *x, float *y) {
uint i = blockIdx.x*blockDim.x + threadIdx.x; // nvcc built-ins
if(i < n) {
float yi = y[i];
float xi = x[i];
float out;
//for (int j=0; j<10; j++) {
out = a*xi + yi;
//}
y[i] = out;
}
}
void saxpy(uint n, float a, float *x, float *y) {
int size = n*sizeof(float);
float *dev_x, *dev_y; // will be allocated on the GPU.
cudaTry(cudaMalloc((void**)(&dev_x), size));
cudaTry(cudaMalloc((void**)(&dev_y), size));
cudaTry(cudaMemcpy(dev_x, x, size, cudaMemcpyHostToDevice));
cudaTry(cudaMemcpy(dev_y, y, size, cudaMemcpyHostToDevice));
saxpy_kernel<<<ceil(n/256.0),256>>>(n, a, dev_x, dev_y);
cudaTry(cudaMemcpy(y, dev_y, size, cudaMemcpyDeviceToHost));
cudaTry(cudaFree(dev_x));
cudaTry(cudaFree(dev_y));
}
void saxpy_cpu(uint n, float a, float *x, float *y) {
for (int i=0; i< n; i++) {
float yi = y[i];
float xi = x[i];
float out;
//for (int j = 0; j<10; j++) {
out = a*xi + yi;
//}
y[i] = out;
}
}
void saxpy_test(uint n, float a, int gpu_flag) {
float *x, *y;
struct rusage r0, r1;
x = NewArray(float, n);
y = NewArray(float, n);
for(uint i = 0; i < n; i++) {
x[i] = i;
y[i] = i*i;
}
getrusage(RUSAGE_SELF, &r0);
if(gpu_flag) saxpy(n, a, x, y);
else saxpy_cpu(n, a, x, y);
getrusage(RUSAGE_SELF, &r1);
double t_elapsed = (r1.ru_utime.tv_sec - r0.ru_utime.tv_sec)
+ 1e-6*(r1.ru_utime.tv_usec - r0.ru_utime.tv_usec);
printf("saxpy%s(n, ...): t_elapsed = %10.3e\n",
gpu_flag ? "" : "_cpu", t_elapsed);
}
// f_main: for command lines of the form
// hw4 f n m
// or
// hw4 f_cpu n m
void f_main(int argc, char **argv, int gpu_flag) {
uint n, m;
if(argc != 4) {
fprintf(stderr, "usage: hw4 %s n m\n", argv[1]);
exit(1);
}
n = strtoul(argv[2], NULL, 10);
m = strtoul(argv[3], NULL, 10);
f_test(n, m, gpu_flag);
}
// saxpy_main: for command lines of the form
// hw4 saxpy n [a]
// or
// hw4 saxpy n [a]
// The parameter 'a' is optional. If omitted, we set a=3.0.
void saxpy_main(int argc, char **argv, int gpu_flag) {
int n;
float a;
if((argc < 3) || (4 < argc)) {
fprintf(stderr, "usage: hw4 saxpy n [a]\n");
exit(1);
}
n = strtoul(argv[2], NULL, 10);
if(argc >= 4) a = atof(argv[3]);
else a = 3.0;
saxpy_test(n, a, gpu_flag);
}
int main(int argc, char **argv) {
if(argc < 2) {
fprintf(stderr, "usage: hw4 testName testArgs\n");
exit(1);
}
if(strcmp(argv[1], "f") == 0) f_main(argc, argv, true);
else if(strcmp(argv[1], "f_cpu") == 0) f_main(argc, argv, false);
else if(strcmp(argv[1], "saxpy") == 0) saxpy_main(argc, argv, true);
else if(strcmp(argv[1], "saxpy_cpu") == 0) saxpy_main(argc, argv, false);
else {
fprintf(stderr, "hw4, unrecognized test case: %s\n", argv[1]);
exit(1);
}
exit(0);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/resource.h>
#define NewArray(Type, N) ((Type *)(malloc(N*sizeof(Type))))
#define cudaTry(cudaStatus) _cudaTry(cudaStatus, __FILE__, __LINE__)
void _cudaTry(hipError_t cudaStatus, const char *fileName, int lineNumber) {
if(cudaStatus != hipSuccess) {
fprintf(stderr, "%s in %s line %d\n",
hipGetErrorString(cudaStatus), fileName, lineNumber);
exit(1);
}
}
__global__ void f_kernel(uint n, uint m, float *x, float *xm) {
uint i = blockIdx.x*blockDim.x + threadIdx.x; // nvcc built-ins
if(i < n) {
float a = 5.0/2.0;
float y = x[i];
for(uint j = 0; j < m; j++) {
y = a*(y*y*y - y);
}
xm[i] = y;
}
}
void f(float *x, float *xm, uint n, uint m) {
int size = n*sizeof(float);
float *dev_x, *dev_xm;
cudaTry(hipMalloc((void**)(&dev_x), size));
cudaTry(hipMalloc((void**)(&dev_xm), size));
cudaTry(hipMemcpy(dev_x, x, size, hipMemcpyHostToDevice));
f_kernel<<<ceil(n/256.0),256>>>(n, m, dev_x, dev_xm);
cudaTry(hipMemcpy(xm, dev_xm, size, hipMemcpyDeviceToHost));
cudaTry(hipFree(dev_x));
cudaTry(hipFree(dev_xm));
}
void f_cpu(float *x, float *xm, uint n, uint m) {
float a = 5.0/2.0;
for(uint i = 0; i < n; i++) {
float y = x[i];
for(uint j = 0; j < m; j++)
y = a*(y*y*y - y);
x[i] = y;
}
}
void f_test(uint n, uint m, int gpu_flag) {
float *x, *xm;
struct rusage r0, r1;
x = NewArray(float, n);
xm = NewArray(float, n);
for(uint i = 0; i < n; i++)
x[i] = (1.0+i)/(n+1);
getrusage(RUSAGE_SELF, &r0);
if(gpu_flag) f(x, xm, n, m);
else f_cpu(x, xm, n, m);
getrusage(RUSAGE_SELF, &r1);
double t_elapsed = (r1.ru_utime.tv_sec - r0.ru_utime.tv_sec)
+ 1e-6*(r1.ru_utime.tv_usec - r0.ru_utime.tv_usec);
printf("f%s(n, ...): t_elapsed = %10.3e, throughput = %10.3e\n",
gpu_flag ? "" : "_cpu", t_elapsed, n*m/t_elapsed);
}
__global__ void saxpy_kernel(uint n, float a, float *x, float *y) {
uint i = blockIdx.x*blockDim.x + threadIdx.x; // nvcc built-ins
if(i < n) {
float yi = y[i];
float xi = x[i];
float out;
//for (int j=0; j<10; j++) {
out = a*xi + yi;
//}
y[i] = out;
}
}
void saxpy(uint n, float a, float *x, float *y) {
int size = n*sizeof(float);
float *dev_x, *dev_y; // will be allocated on the GPU.
cudaTry(hipMalloc((void**)(&dev_x), size));
cudaTry(hipMalloc((void**)(&dev_y), size));
cudaTry(hipMemcpy(dev_x, x, size, hipMemcpyHostToDevice));
cudaTry(hipMemcpy(dev_y, y, size, hipMemcpyHostToDevice));
saxpy_kernel<<<ceil(n/256.0),256>>>(n, a, dev_x, dev_y);
cudaTry(hipMemcpy(y, dev_y, size, hipMemcpyDeviceToHost));
cudaTry(hipFree(dev_x));
cudaTry(hipFree(dev_y));
}
void saxpy_cpu(uint n, float a, float *x, float *y) {
for (int i=0; i< n; i++) {
float yi = y[i];
float xi = x[i];
float out;
//for (int j = 0; j<10; j++) {
out = a*xi + yi;
//}
y[i] = out;
}
}
void saxpy_test(uint n, float a, int gpu_flag) {
float *x, *y;
struct rusage r0, r1;
x = NewArray(float, n);
y = NewArray(float, n);
for(uint i = 0; i < n; i++) {
x[i] = i;
y[i] = i*i;
}
getrusage(RUSAGE_SELF, &r0);
if(gpu_flag) saxpy(n, a, x, y);
else saxpy_cpu(n, a, x, y);
getrusage(RUSAGE_SELF, &r1);
double t_elapsed = (r1.ru_utime.tv_sec - r0.ru_utime.tv_sec)
+ 1e-6*(r1.ru_utime.tv_usec - r0.ru_utime.tv_usec);
printf("saxpy%s(n, ...): t_elapsed = %10.3e\n",
gpu_flag ? "" : "_cpu", t_elapsed);
}
// f_main: for command lines of the form
// hw4 f n m
// or
// hw4 f_cpu n m
void f_main(int argc, char **argv, int gpu_flag) {
uint n, m;
if(argc != 4) {
fprintf(stderr, "usage: hw4 %s n m\n", argv[1]);
exit(1);
}
n = strtoul(argv[2], NULL, 10);
m = strtoul(argv[3], NULL, 10);
f_test(n, m, gpu_flag);
}
// saxpy_main: for command lines of the form
// hw4 saxpy n [a]
// or
// hw4 saxpy n [a]
// The parameter 'a' is optional. If omitted, we set a=3.0.
void saxpy_main(int argc, char **argv, int gpu_flag) {
int n;
float a;
if((argc < 3) || (4 < argc)) {
fprintf(stderr, "usage: hw4 saxpy n [a]\n");
exit(1);
}
n = strtoul(argv[2], NULL, 10);
if(argc >= 4) a = atof(argv[3]);
else a = 3.0;
saxpy_test(n, a, gpu_flag);
}
int main(int argc, char **argv) {
if(argc < 2) {
fprintf(stderr, "usage: hw4 testName testArgs\n");
exit(1);
}
if(strcmp(argv[1], "f") == 0) f_main(argc, argv, true);
else if(strcmp(argv[1], "f_cpu") == 0) f_main(argc, argv, false);
else if(strcmp(argv[1], "saxpy") == 0) saxpy_main(argc, argv, true);
else if(strcmp(argv[1], "saxpy_cpu") == 0) saxpy_main(argc, argv, false);
else {
fprintf(stderr, "hw4, unrecognized test case: %s\n", argv[1]);
exit(1);
}
exit(0);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/resource.h>
#define NewArray(Type, N) ((Type *)(malloc(N*sizeof(Type))))
#define cudaTry(cudaStatus) _cudaTry(cudaStatus, __FILE__, __LINE__)
void _cudaTry(hipError_t cudaStatus, const char *fileName, int lineNumber) {
if(cudaStatus != hipSuccess) {
fprintf(stderr, "%s in %s line %d\n",
hipGetErrorString(cudaStatus), fileName, lineNumber);
exit(1);
}
}
__global__ void f_kernel(uint n, uint m, float *x, float *xm) {
uint i = blockIdx.x*blockDim.x + threadIdx.x; // nvcc built-ins
if(i < n) {
float a = 5.0/2.0;
float y = x[i];
for(uint j = 0; j < m; j++) {
y = a*(y*y*y - y);
}
xm[i] = y;
}
}
void f(float *x, float *xm, uint n, uint m) {
int size = n*sizeof(float);
float *dev_x, *dev_xm;
cudaTry(hipMalloc((void**)(&dev_x), size));
cudaTry(hipMalloc((void**)(&dev_xm), size));
cudaTry(hipMemcpy(dev_x, x, size, hipMemcpyHostToDevice));
f_kernel<<<ceil(n/256.0),256>>>(n, m, dev_x, dev_xm);
cudaTry(hipMemcpy(xm, dev_xm, size, hipMemcpyDeviceToHost));
cudaTry(hipFree(dev_x));
cudaTry(hipFree(dev_xm));
}
void f_cpu(float *x, float *xm, uint n, uint m) {
float a = 5.0/2.0;
for(uint i = 0; i < n; i++) {
float y = x[i];
for(uint j = 0; j < m; j++)
y = a*(y*y*y - y);
x[i] = y;
}
}
void f_test(uint n, uint m, int gpu_flag) {
float *x, *xm;
struct rusage r0, r1;
x = NewArray(float, n);
xm = NewArray(float, n);
for(uint i = 0; i < n; i++)
x[i] = (1.0+i)/(n+1);
getrusage(RUSAGE_SELF, &r0);
if(gpu_flag) f(x, xm, n, m);
else f_cpu(x, xm, n, m);
getrusage(RUSAGE_SELF, &r1);
double t_elapsed = (r1.ru_utime.tv_sec - r0.ru_utime.tv_sec)
+ 1e-6*(r1.ru_utime.tv_usec - r0.ru_utime.tv_usec);
printf("f%s(n, ...): t_elapsed = %10.3e, throughput = %10.3e\n",
gpu_flag ? "" : "_cpu", t_elapsed, n*m/t_elapsed);
}
__global__ void saxpy_kernel(uint n, float a, float *x, float *y) {
uint i = blockIdx.x*blockDim.x + threadIdx.x; // nvcc built-ins
if(i < n) {
float yi = y[i];
float xi = x[i];
float out;
//for (int j=0; j<10; j++) {
out = a*xi + yi;
//}
y[i] = out;
}
}
void saxpy(uint n, float a, float *x, float *y) {
int size = n*sizeof(float);
float *dev_x, *dev_y; // will be allocated on the GPU.
cudaTry(hipMalloc((void**)(&dev_x), size));
cudaTry(hipMalloc((void**)(&dev_y), size));
cudaTry(hipMemcpy(dev_x, x, size, hipMemcpyHostToDevice));
cudaTry(hipMemcpy(dev_y, y, size, hipMemcpyHostToDevice));
saxpy_kernel<<<ceil(n/256.0),256>>>(n, a, dev_x, dev_y);
cudaTry(hipMemcpy(y, dev_y, size, hipMemcpyDeviceToHost));
cudaTry(hipFree(dev_x));
cudaTry(hipFree(dev_y));
}
void saxpy_cpu(uint n, float a, float *x, float *y) {
for (int i=0; i< n; i++) {
float yi = y[i];
float xi = x[i];
float out;
//for (int j = 0; j<10; j++) {
out = a*xi + yi;
//}
y[i] = out;
}
}
void saxpy_test(uint n, float a, int gpu_flag) {
float *x, *y;
struct rusage r0, r1;
x = NewArray(float, n);
y = NewArray(float, n);
for(uint i = 0; i < n; i++) {
x[i] = i;
y[i] = i*i;
}
getrusage(RUSAGE_SELF, &r0);
if(gpu_flag) saxpy(n, a, x, y);
else saxpy_cpu(n, a, x, y);
getrusage(RUSAGE_SELF, &r1);
double t_elapsed = (r1.ru_utime.tv_sec - r0.ru_utime.tv_sec)
+ 1e-6*(r1.ru_utime.tv_usec - r0.ru_utime.tv_usec);
printf("saxpy%s(n, ...): t_elapsed = %10.3e\n",
gpu_flag ? "" : "_cpu", t_elapsed);
}
// f_main: for command lines of the form
// hw4 f n m
// or
// hw4 f_cpu n m
void f_main(int argc, char **argv, int gpu_flag) {
uint n, m;
if(argc != 4) {
fprintf(stderr, "usage: hw4 %s n m\n", argv[1]);
exit(1);
}
n = strtoul(argv[2], NULL, 10);
m = strtoul(argv[3], NULL, 10);
f_test(n, m, gpu_flag);
}
// saxpy_main: for command lines of the form
// hw4 saxpy n [a]
// or
// hw4 saxpy n [a]
// The parameter 'a' is optional. If omitted, we set a=3.0.
void saxpy_main(int argc, char **argv, int gpu_flag) {
int n;
float a;
if((argc < 3) || (4 < argc)) {
fprintf(stderr, "usage: hw4 saxpy n [a]\n");
exit(1);
}
n = strtoul(argv[2], NULL, 10);
if(argc >= 4) a = atof(argv[3]);
else a = 3.0;
saxpy_test(n, a, gpu_flag);
}
int main(int argc, char **argv) {
if(argc < 2) {
fprintf(stderr, "usage: hw4 testName testArgs\n");
exit(1);
}
if(strcmp(argv[1], "f") == 0) f_main(argc, argv, true);
else if(strcmp(argv[1], "f_cpu") == 0) f_main(argc, argv, false);
else if(strcmp(argv[1], "saxpy") == 0) saxpy_main(argc, argv, true);
else if(strcmp(argv[1], "saxpy_cpu") == 0) saxpy_main(argc, argv, false);
else {
fprintf(stderr, "hw4, unrecognized test case: %s\n", argv[1]);
exit(1);
}
exit(0);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8f_kerneljjPfS_
.globl _Z8f_kerneljjPfS_
.p2align 8
.type _Z8f_kerneljjPfS_,@function
_Z8f_kerneljjPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x8
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_load_b32 s2, s[0:1], 0x4
global_load_b32 v0, v[3:4], off
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB0_3
.LBB0_2:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, v0, v0
s_add_i32 s2, s2, -1
v_fma_f32 v0, v0, v3, -v0
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v0, 0x40200000, v0
s_cmp_eq_u32 s2, 0
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v0, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8f_kerneljjPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8f_kerneljjPfS_, .Lfunc_end0-_Z8f_kerneljjPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12saxpy_kerneljfPfS_
.globl _Z12saxpy_kerneljfPfS_
.p2align 8
.type _Z12saxpy_kerneljfPfS_,@function
_Z12saxpy_kerneljfPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x8
v_mov_b32_e32 v2, 0
s_load_b32 s0, s[0:1], 0x4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v4, v[2:3], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, s0, v0
global_store_b32 v[2:3], v4, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12saxpy_kerneljfPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12saxpy_kerneljfPfS_, .Lfunc_end1-_Z12saxpy_kerneljfPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8f_kerneljjPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8f_kerneljjPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12saxpy_kerneljfPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12saxpy_kerneljfPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/resource.h>
#define NewArray(Type, N) ((Type *)(malloc(N*sizeof(Type))))
#define cudaTry(cudaStatus) _cudaTry(cudaStatus, __FILE__, __LINE__)
void _cudaTry(hipError_t cudaStatus, const char *fileName, int lineNumber) {
if(cudaStatus != hipSuccess) {
fprintf(stderr, "%s in %s line %d\n",
hipGetErrorString(cudaStatus), fileName, lineNumber);
exit(1);
}
}
__global__ void f_kernel(uint n, uint m, float *x, float *xm) {
uint i = blockIdx.x*blockDim.x + threadIdx.x; // nvcc built-ins
if(i < n) {
float a = 5.0/2.0;
float y = x[i];
for(uint j = 0; j < m; j++) {
y = a*(y*y*y - y);
}
xm[i] = y;
}
}
void f(float *x, float *xm, uint n, uint m) {
int size = n*sizeof(float);
float *dev_x, *dev_xm;
cudaTry(hipMalloc((void**)(&dev_x), size));
cudaTry(hipMalloc((void**)(&dev_xm), size));
cudaTry(hipMemcpy(dev_x, x, size, hipMemcpyHostToDevice));
f_kernel<<<ceil(n/256.0),256>>>(n, m, dev_x, dev_xm);
cudaTry(hipMemcpy(xm, dev_xm, size, hipMemcpyDeviceToHost));
cudaTry(hipFree(dev_x));
cudaTry(hipFree(dev_xm));
}
void f_cpu(float *x, float *xm, uint n, uint m) {
float a = 5.0/2.0;
for(uint i = 0; i < n; i++) {
float y = x[i];
for(uint j = 0; j < m; j++)
y = a*(y*y*y - y);
x[i] = y;
}
}
void f_test(uint n, uint m, int gpu_flag) {
float *x, *xm;
struct rusage r0, r1;
x = NewArray(float, n);
xm = NewArray(float, n);
for(uint i = 0; i < n; i++)
x[i] = (1.0+i)/(n+1);
getrusage(RUSAGE_SELF, &r0);
if(gpu_flag) f(x, xm, n, m);
else f_cpu(x, xm, n, m);
getrusage(RUSAGE_SELF, &r1);
double t_elapsed = (r1.ru_utime.tv_sec - r0.ru_utime.tv_sec)
+ 1e-6*(r1.ru_utime.tv_usec - r0.ru_utime.tv_usec);
printf("f%s(n, ...): t_elapsed = %10.3e, throughput = %10.3e\n",
gpu_flag ? "" : "_cpu", t_elapsed, n*m/t_elapsed);
}
__global__ void saxpy_kernel(uint n, float a, float *x, float *y) {
uint i = blockIdx.x*blockDim.x + threadIdx.x; // nvcc built-ins
if(i < n) {
float yi = y[i];
float xi = x[i];
float out;
//for (int j=0; j<10; j++) {
out = a*xi + yi;
//}
y[i] = out;
}
}
void saxpy(uint n, float a, float *x, float *y) {
int size = n*sizeof(float);
float *dev_x, *dev_y; // will be allocated on the GPU.
cudaTry(hipMalloc((void**)(&dev_x), size));
cudaTry(hipMalloc((void**)(&dev_y), size));
cudaTry(hipMemcpy(dev_x, x, size, hipMemcpyHostToDevice));
cudaTry(hipMemcpy(dev_y, y, size, hipMemcpyHostToDevice));
saxpy_kernel<<<ceil(n/256.0),256>>>(n, a, dev_x, dev_y);
cudaTry(hipMemcpy(y, dev_y, size, hipMemcpyDeviceToHost));
cudaTry(hipFree(dev_x));
cudaTry(hipFree(dev_y));
}
void saxpy_cpu(uint n, float a, float *x, float *y) {
for (int i=0; i< n; i++) {
float yi = y[i];
float xi = x[i];
float out;
//for (int j = 0; j<10; j++) {
out = a*xi + yi;
//}
y[i] = out;
}
}
void saxpy_test(uint n, float a, int gpu_flag) {
float *x, *y;
struct rusage r0, r1;
x = NewArray(float, n);
y = NewArray(float, n);
for(uint i = 0; i < n; i++) {
x[i] = i;
y[i] = i*i;
}
getrusage(RUSAGE_SELF, &r0);
if(gpu_flag) saxpy(n, a, x, y);
else saxpy_cpu(n, a, x, y);
getrusage(RUSAGE_SELF, &r1);
double t_elapsed = (r1.ru_utime.tv_sec - r0.ru_utime.tv_sec)
+ 1e-6*(r1.ru_utime.tv_usec - r0.ru_utime.tv_usec);
printf("saxpy%s(n, ...): t_elapsed = %10.3e\n",
gpu_flag ? "" : "_cpu", t_elapsed);
}
// f_main: for command lines of the form
// hw4 f n m
// or
// hw4 f_cpu n m
void f_main(int argc, char **argv, int gpu_flag) {
uint n, m;
if(argc != 4) {
fprintf(stderr, "usage: hw4 %s n m\n", argv[1]);
exit(1);
}
n = strtoul(argv[2], NULL, 10);
m = strtoul(argv[3], NULL, 10);
f_test(n, m, gpu_flag);
}
// saxpy_main: for command lines of the form
// hw4 saxpy n [a]
// or
// hw4 saxpy n [a]
// The parameter 'a' is optional. If omitted, we set a=3.0.
void saxpy_main(int argc, char **argv, int gpu_flag) {
int n;
float a;
if((argc < 3) || (4 < argc)) {
fprintf(stderr, "usage: hw4 saxpy n [a]\n");
exit(1);
}
n = strtoul(argv[2], NULL, 10);
if(argc >= 4) a = atof(argv[3]);
else a = 3.0;
saxpy_test(n, a, gpu_flag);
}
int main(int argc, char **argv) {
if(argc < 2) {
fprintf(stderr, "usage: hw4 testName testArgs\n");
exit(1);
}
if(strcmp(argv[1], "f") == 0) f_main(argc, argv, true);
else if(strcmp(argv[1], "f_cpu") == 0) f_main(argc, argv, false);
else if(strcmp(argv[1], "saxpy") == 0) saxpy_main(argc, argv, true);
else if(strcmp(argv[1], "saxpy_cpu") == 0) saxpy_main(argc, argv, false);
else {
fprintf(stderr, "hw4, unrecognized test case: %s\n", argv[1]);
exit(1);
}
exit(0);
} | .text
.file "hw4.hip"
.globl _Z8_cudaTry10hipError_tPKci # -- Begin function _Z8_cudaTry10hipError_tPKci
.p2align 4, 0x90
.type _Z8_cudaTry10hipError_tPKci,@function
_Z8_cudaTry10hipError_tPKci: # @_Z8_cudaTry10hipError_tPKci
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB0_2
# %bb.1:
retq
.LBB0_2:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq stderr(%rip), %rbx
movl %edx, %ebp
movq %rsi, %r14
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
movq %r14, %rcx
movl %ebp, %r8d
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z8_cudaTry10hipError_tPKci, .Lfunc_end0-_Z8_cudaTry10hipError_tPKci
.cfi_endproc
# -- End function
.globl _Z23__device_stub__f_kerneljjPfS_ # -- Begin function _Z23__device_stub__f_kerneljjPfS_
.p2align 4, 0x90
.type _Z23__device_stub__f_kerneljjPfS_,@function
_Z23__device_stub__f_kerneljjPfS_: # @_Z23__device_stub__f_kerneljjPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8f_kerneljjPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z23__device_stub__f_kerneljjPfS_, .Lfunc_end1-_Z23__device_stub__f_kerneljjPfS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z1fPfS_jj
.LCPI2_0:
.quad 0x3f70000000000000 # double 0.00390625
.text
.globl _Z1fPfS_jj
.p2align 4, 0x90
.type _Z1fPfS_jj,@function
_Z1fPfS_jj: # @_Z1fPfS_jj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %r15d
movq %rsi, %rbx
movq %rdi, %r12
leal (,%r15,4), %eax
movslq %eax, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_1
# %bb.3: # %_Z8_cudaTry10hipError_tPKci.exit
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_4
# %bb.5: # %_Z8_cudaTry10hipError_tPKci.exit12
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_6
# %bb.7: # %_Z8_cudaTry10hipError_tPKci.exit14
movl %r15d, %eax
cvtsi2sd %rax, %xmm0
mulsd .LCPI2_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_9
# %bb.8:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl %r15d, 28(%rsp)
movl %ebp, 24(%rsp)
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8f_kerneljjPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_9:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_10
# %bb.11: # %_Z8_cudaTry10hipError_tPKci.exit16
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_12
# %bb.13: # %_Z8_cudaTry10hipError_tPKci.exit18
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_14
# %bb.15: # %_Z8_cudaTry10hipError_tPKci.exit20
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 176
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $37, %r8d
jmp .LBB2_2
.LBB2_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $38, %r8d
jmp .LBB2_2
.LBB2_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $39, %r8d
jmp .LBB2_2
.LBB2_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $43, %r8d
jmp .LBB2_2
.LBB2_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $44, %r8d
jmp .LBB2_2
.LBB2_14:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $45, %r8d
.LBB2_2:
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size _Z1fPfS_jj, .Lfunc_end2-_Z1fPfS_jj
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z5f_cpuPfS_jj
.LCPI3_0:
.long 0x40200000 # float 2.5
.text
.globl _Z5f_cpuPfS_jj
.p2align 4, 0x90
.type _Z5f_cpuPfS_jj,@function
_Z5f_cpuPfS_jj: # @_Z5f_cpuPfS_jj
.cfi_startproc
# %bb.0:
testl %edx, %edx
je .LBB3_4
# %bb.1: # %.lr.ph21
movl %edx, %eax
xorl %edx, %edx
movss .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_3: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
movss %xmm1, (%rdi,%rdx,4)
incq %rdx
cmpq %rax, %rdx
je .LBB3_4
.LBB3_2: # =>This Loop Header: Depth=1
# Child Loop BB3_5 Depth 2
movss (%rdi,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movl %ecx, %esi
testl %ecx, %ecx
je .LBB3_3
.p2align 4, 0x90
.LBB3_5: # %.lr.ph
# Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movaps %xmm1, %xmm2
mulss %xmm1, %xmm2
mulss %xmm1, %xmm2
subss %xmm1, %xmm2
mulss %xmm0, %xmm2
movaps %xmm2, %xmm1
decl %esi
jne .LBB3_5
jmp .LBB3_3
.LBB3_4: # %._crit_edge22
retq
.Lfunc_end3:
.size _Z5f_cpuPfS_jj, .Lfunc_end3-_Z5f_cpuPfS_jj
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z6f_testjji
.LCPI4_0:
.quad 0x3ff0000000000000 # double 1
.LCPI4_2:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI4_1:
.long 0x40200000 # float 2.5
.text
.globl _Z6f_testjji
.p2align 4, 0x90
.type _Z6f_testjji,@function
_Z6f_testjji: # @_Z6f_testjji
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 352
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movl %esi, %ebx
movl %edi, %r14d
movl %edi, %r13d
leaq (,%r13,4), %r12
movq %r12, %rdi
callq malloc
movq %rax, %r15
movq %r12, %rdi
callq malloc
movq %rax, %r12
testl %r14d, %r14d
je .LBB4_3
# %bb.1: # %.lr.ph
leal 1(%r14), %eax
cvtsi2sd %rax, %xmm0
xorl %eax, %eax
movsd .LCPI4_0(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB4_2: # =>This Inner Loop Header: Depth=1
movl %eax, %ecx
xorps %xmm2, %xmm2
cvtsi2sd %rcx, %xmm2
addsd %xmm1, %xmm2
divsd %xmm0, %xmm2
cvtsd2ss %xmm2, %xmm2
movss %xmm2, (%r15,%rax,4)
incq %rax
cmpq %rax, %r13
jne .LBB4_2
.LBB4_3: # %._crit_edge
leaq 152(%rsp), %rsi
xorl %edi, %edi
callq getrusage
testl %ebp, %ebp
je .LBB4_5
# %bb.4:
movq %r15, %rdi
movq %r12, %rsi
movl %r14d, %edx
movl %ebx, %ecx
callq _Z1fPfS_jj
movl $.L.str.3, %r12d
.LBB4_9: # %_Z5f_cpuPfS_jj.exit
leaq 8(%rsp), %rsi
xorl %edi, %edi
callq getrusage
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
subq 152(%rsp), %rax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
subq 160(%rsp), %rcx
xorps %xmm0, %xmm0
cvtsi2sd %rcx, %xmm0
mulsd .LCPI4_2(%rip), %xmm0
addsd %xmm1, %xmm0
imull %r14d, %ebx
xorps %xmm1, %xmm1
cvtsi2sd %rbx, %xmm1
divsd %xmm0, %xmm1
movl $.L.str.2, %edi
movq %r12, %rsi
movb $2, %al
callq printf
addq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_5:
.cfi_def_cfa_offset 352
movl $.L.str.4, %r12d
testl %r14d, %r14d
je .LBB4_9
# %bb.6: # %.lr.ph21.i
xorl %eax, %eax
movss .LCPI4_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
jmp .LBB4_7
.p2align 4, 0x90
.LBB4_8: # %._crit_edge.i
# in Loop: Header=BB4_7 Depth=1
movss %xmm1, (%r15,%rax,4)
incq %rax
cmpq %r13, %rax
je .LBB4_9
.LBB4_7: # =>This Loop Header: Depth=1
# Child Loop BB4_10 Depth 2
movss (%r15,%rax,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movl %ebx, %ecx
testl %ebx, %ebx
je .LBB4_8
.p2align 4, 0x90
.LBB4_10: # %.lr.ph.i
# Parent Loop BB4_7 Depth=1
# => This Inner Loop Header: Depth=2
movaps %xmm1, %xmm2
mulss %xmm1, %xmm2
mulss %xmm1, %xmm2
subss %xmm1, %xmm2
mulss %xmm0, %xmm2
movaps %xmm2, %xmm1
decl %ecx
jne .LBB4_10
jmp .LBB4_8
.Lfunc_end4:
.size _Z6f_testjji, .Lfunc_end4-_Z6f_testjji
.cfi_endproc
# -- End function
.globl _Z27__device_stub__saxpy_kerneljfPfS_ # -- Begin function _Z27__device_stub__saxpy_kerneljfPfS_
.p2align 4, 0x90
.type _Z27__device_stub__saxpy_kerneljfPfS_,@function
_Z27__device_stub__saxpy_kerneljfPfS_: # @_Z27__device_stub__saxpy_kerneljfPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12saxpy_kerneljfPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end5:
.size _Z27__device_stub__saxpy_kerneljfPfS_, .Lfunc_end5-_Z27__device_stub__saxpy_kerneljfPfS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z5saxpyjfPfS_
.LCPI6_0:
.quad 0x3f70000000000000 # double 0.00390625
.text
.globl _Z5saxpyjfPfS_
.p2align 4, 0x90
.type _Z5saxpyjfPfS_,@function
_Z5saxpyjfPfS_: # @_Z5saxpyjfPfS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rsi, %r12
movss %xmm0, 20(%rsp) # 4-byte Spill
movl %edi, %r15d
leal (,%r15,4), %eax
movslq %eax, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB6_1
# %bb.3: # %_Z8_cudaTry10hipError_tPKci.exit
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB6_4
# %bb.5: # %_Z8_cudaTry10hipError_tPKci.exit14
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB6_6
# %bb.7: # %_Z8_cudaTry10hipError_tPKci.exit16
movq (%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB6_8
# %bb.9: # %_Z8_cudaTry10hipError_tPKci.exit18
movl %r15d, %eax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
mulsd .LCPI6_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_11
# %bb.10:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movl %r15d, 28(%rsp)
movss 20(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 24(%rsp)
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12saxpy_kerneljfPfS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_11:
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB6_12
# %bb.13: # %_Z8_cudaTry10hipError_tPKci.exit20
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB6_14
# %bb.15: # %_Z8_cudaTry10hipError_tPKci.exit22
movq (%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB6_16
# %bb.17: # %_Z8_cudaTry10hipError_tPKci.exit24
addq $136, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB6_1:
.cfi_def_cfa_offset 176
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $93, %r8d
jmp .LBB6_2
.LBB6_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $94, %r8d
jmp .LBB6_2
.LBB6_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $95, %r8d
jmp .LBB6_2
.LBB6_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $96, %r8d
jmp .LBB6_2
.LBB6_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $100, %r8d
jmp .LBB6_2
.LBB6_14:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $101, %r8d
jmp .LBB6_2
.LBB6_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $102, %r8d
.LBB6_2:
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end6:
.size _Z5saxpyjfPfS_, .Lfunc_end6-_Z5saxpyjfPfS_
.cfi_endproc
# -- End function
.globl _Z9saxpy_cpujfPfS_ # -- Begin function _Z9saxpy_cpujfPfS_
.p2align 4, 0x90
.type _Z9saxpy_cpujfPfS_,@function
_Z9saxpy_cpujfPfS_: # @_Z9saxpy_cpujfPfS_
.cfi_startproc
# %bb.0:
testl %edi, %edi
je .LBB7_3
# %bb.1: # %.lr.ph.preheader
movl %edi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB7_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rsi,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm0, %xmm1
addss (%rdx,%rcx,4), %xmm1
movss %xmm1, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB7_2
.LBB7_3: # %._crit_edge
retq
.Lfunc_end7:
.size _Z9saxpy_cpujfPfS_, .Lfunc_end7-_Z9saxpy_cpujfPfS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z10saxpy_testjfi
.LCPI8_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z10saxpy_testjfi
.p2align 4, 0x90
.type _Z10saxpy_testjfi,@function
_Z10saxpy_testjfi: # @_Z10saxpy_testjfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $304, %rsp # imm = 0x130
.cfi_def_cfa_offset 352
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %r15d
movss %xmm0, 12(%rsp) # 4-byte Spill
movl %edi, %ebp
movl %edi, %r12d
leaq (,%r12,4), %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movq %r14, %rdi
callq malloc
movq %rax, %r14
testl %ebp, %ebp
je .LBB8_3
# %bb.1: # %.lr.ph.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB8_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %eax, %ecx
xorps %xmm0, %xmm0
cvtsi2ss %rcx, %xmm0
movl %eax, %ecx
imull %ecx, %ecx
xorps %xmm1, %xmm1
cvtsi2ss %rcx, %xmm1
movss %xmm0, (%rbx,%rax,4)
movss %xmm1, (%r14,%rax,4)
incq %rax
cmpq %rax, %r12
jne .LBB8_2
.LBB8_3: # %._crit_edge
leaq 160(%rsp), %rsi
xorl %edi, %edi
callq getrusage
testl %r15d, %r15d
je .LBB8_5
# %bb.4:
movl %ebp, %edi
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rbx, %rsi
movq %r14, %rdx
callq _Z5saxpyjfPfS_
movl $.L.str.3, %r15d
jmp .LBB8_8
.LBB8_5:
movl $.L.str.4, %r15d
testl %ebp, %ebp
movss 12(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
je .LBB8_8
# %bb.6: # %.lr.ph.i.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB8_7: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
addss (%r14,%rax,4), %xmm0
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq %rax, %r12
jne .LBB8_7
.LBB8_8: # %_Z9saxpy_cpujfPfS_.exit
leaq 16(%rsp), %rsi
xorl %edi, %edi
callq getrusage
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
subq 160(%rsp), %rax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
subq 168(%rsp), %rcx
xorps %xmm0, %xmm0
cvtsi2sd %rcx, %xmm0
mulsd .LCPI8_0(%rip), %xmm0
addsd %xmm1, %xmm0
movl $.L.str.5, %edi
movq %r15, %rsi
movb $1, %al
callq printf
addq $304, %rsp # imm = 0x130
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size _Z10saxpy_testjfi, .Lfunc_end8-_Z10saxpy_testjfi
.cfi_endproc
# -- End function
.globl _Z6f_mainiPPci # -- Begin function _Z6f_mainiPPci
.p2align 4, 0x90
.type _Z6f_mainiPPci,@function
_Z6f_mainiPPci: # @_Z6f_mainiPPci
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %r14
cmpl $4, %edi
jne .LBB9_1
# %bb.2:
movl %edx, %ebx
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtoul
movq %rax, %r15
movq 24(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtoul
movl %r15d, %edi
movl %eax, %esi
movl %ebx, %edx
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp _Z6f_testjji # TAILCALL
.LBB9_1:
.cfi_def_cfa_offset 32
movq stderr(%rip), %rdi
movq 8(%r14), %rdx
movl $.L.str.6, %esi
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end9:
.size _Z6f_mainiPPci, .Lfunc_end9-_Z6f_mainiPPci
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10saxpy_mainiPPci
.LCPI10_0:
.long 0x40400000 # float 3
.text
.globl _Z10saxpy_mainiPPci
.p2align 4, 0x90
.type _Z10saxpy_mainiPPci,@function
_Z10saxpy_mainiPPci: # @_Z10saxpy_mainiPPci
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edi, %r12d
leal -5(%r12), %eax
cmpl $-3, %eax
jbe .LBB10_5
# %bb.1:
movl %edx, %ebx
movq %rsi, %r15
movq 16(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtoul
movq %rax, %r14
cmpl $4, %r12d
jl .LBB10_2
# %bb.3:
movq 24(%r15), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
jmp .LBB10_4
.LBB10_2:
movss .LCPI10_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.LBB10_4:
movl %r14d, %edi
movl %ebx, %esi
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp _Z10saxpy_testjfi # TAILCALL
.LBB10_5:
.cfi_def_cfa_offset 48
movq stderr(%rip), %rcx
movl $.L.str.7, %edi
movl $23, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end10:
.size _Z10saxpy_mainiPPci, .Lfunc_end10-_Z10saxpy_mainiPPci
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI11_0:
.long 0x40400000 # float 3
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
cmpl $1, %edi
jg .LBB11_3
# %bb.1:
movq stderr(%rip), %rcx
movl $.L.str.8, %edi
movl $29, %esi
.LBB11_2:
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.LBB11_3:
movq %rsi, %rbx
movl %edi, %r14d
movq 8(%rsi), %r15
movl $.L.str.9, %esi
movq %r15, %rdi
callq strcmp
testl %eax, %eax
jne .LBB11_6
# %bb.4:
cmpl $4, %r14d
jne .LBB11_10
# %bb.5: # %_Z6f_mainiPPci.exit
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtoul
movq %rax, %r14
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtoul
movl %r14d, %edi
movl %eax, %esi
movl $1, %edx
jmp .LBB11_9
.LBB11_6:
movl $.L.str.10, %esi
movq %r15, %rdi
callq strcmp
testl %eax, %eax
jne .LBB11_12
# %bb.7:
cmpl $4, %r14d
jne .LBB11_10
# %bb.8: # %_Z6f_mainiPPci.exit14
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtoul
movq %rax, %r14
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtoul
movl %r14d, %edi
movl %eax, %esi
xorl %edx, %edx
.LBB11_9:
callq _Z6f_testjji
xorl %edi, %edi
callq exit
.LBB11_10:
movq stderr(%rip), %rdi
movl $.L.str.6, %esi
.LBB11_11:
movq %r15, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB11_12:
movl $.L.str.11, %esi
movq %r15, %rdi
callq strcmp
testl %eax, %eax
jne .LBB11_16
# %bb.13:
leal -5(%r14), %eax
cmpl $-3, %eax
jbe .LBB11_18
# %bb.14:
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtoul
movq %rax, %r15
cmpl $4, %r14d
jl .LBB11_20
# %bb.15:
movq 24(%rbx), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
jmp .LBB11_21
.LBB11_16:
movl $.L.str.12, %esi
movq %r15, %rdi
callq strcmp
testl %eax, %eax
jne .LBB11_19
# %bb.17:
leal -5(%r14), %eax
cmpl $-3, %eax
ja .LBB11_23
.LBB11_18:
movq stderr(%rip), %rcx
movl $.L.str.7, %edi
movl $23, %esi
jmp .LBB11_2
.LBB11_19:
movq stderr(%rip), %rdi
movl $.L.str.13, %esi
jmp .LBB11_11
.LBB11_20:
movss .LCPI11_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.LBB11_21: # %_Z10saxpy_mainiPPci.exit
movl %r15d, %edi
movl $1, %esi
jmp .LBB11_22
.LBB11_23:
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtoul
movq %rax, %r15
cmpl $4, %r14d
jl .LBB11_25
# %bb.24:
movq 24(%rbx), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
jmp .LBB11_26
.LBB11_25:
movss .LCPI11_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.LBB11_26: # %_Z10saxpy_mainiPPci.exit17
movl %r15d, %edi
xorl %esi, %esi
.LBB11_22: # %_Z10saxpy_mainiPPci.exit
callq _Z10saxpy_testjfi
xorl %edi, %edi
callq exit
.Lfunc_end11:
.size main, .Lfunc_end11-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB12_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB12_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8f_kerneljjPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12saxpy_kerneljfPfS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end12:
.size __hip_module_ctor, .Lfunc_end12-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB13_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB13_2:
retq
.Lfunc_end13:
.size __hip_module_dtor, .Lfunc_end13-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%s in %s line %d\n"
.size .L.str, 18
.type _Z8f_kerneljjPfS_,@object # @_Z8f_kerneljjPfS_
.section .rodata,"a",@progbits
.globl _Z8f_kerneljjPfS_
.p2align 3, 0x0
_Z8f_kerneljjPfS_:
.quad _Z23__device_stub__f_kerneljjPfS_
.size _Z8f_kerneljjPfS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/d4l3k/cs418/master/hw4/hw4.hip"
.size .L.str.1, 88
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "f%s(n, ...): t_elapsed = %10.3e, throughput = %10.3e\n"
.size .L.str.2, 54
.type .L.str.3,@object # @.str.3
.L.str.3:
.zero 1
.size .L.str.3, 1
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "_cpu"
.size .L.str.4, 5
.type _Z12saxpy_kerneljfPfS_,@object # @_Z12saxpy_kerneljfPfS_
.section .rodata,"a",@progbits
.globl _Z12saxpy_kerneljfPfS_
.p2align 3, 0x0
_Z12saxpy_kerneljfPfS_:
.quad _Z27__device_stub__saxpy_kerneljfPfS_
.size _Z12saxpy_kerneljfPfS_, 8
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "saxpy%s(n, ...): t_elapsed = %10.3e\n"
.size .L.str.5, 37
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "usage: hw4 %s n m\n"
.size .L.str.6, 19
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "usage: hw4 saxpy n [a]\n"
.size .L.str.7, 24
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "usage: hw4 testName testArgs\n"
.size .L.str.8, 30
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "f"
.size .L.str.9, 2
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "f_cpu"
.size .L.str.10, 6
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "saxpy"
.size .L.str.11, 6
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "saxpy_cpu"
.size .L.str.12, 10
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "hw4, unrecognized test case: %s\n"
.size .L.str.13, 33
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8f_kerneljjPfS_"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12saxpy_kerneljfPfS_"
.size .L__unnamed_2, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__f_kerneljjPfS_
.addrsig_sym _Z27__device_stub__saxpy_kerneljfPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8f_kerneljjPfS_
.addrsig_sym _Z12saxpy_kerneljfPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12saxpy_kerneljfPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R4, R2, R3, c[0x0][0x168] ; /* 0x00005a0002047625 */
/* 0x000fc800078e0003 */
/*0090*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fe400078e0003 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FFMA R7, R4, c[0x0][0x164], R7 ; /* 0x0000590004077a23 */
/* 0x004fca0000000007 */
/*00d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8f_kerneljjPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x164], PT ; /* 0x00005900ff007a0c */
/* 0x000fe20003f05270 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0003 */
/*00a0*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000162000c1e1900 */
/*00b0*/ @!P0 BRA 0x800 ; /* 0x0000074000008947 */
/* 0x000fea0003800000 */
/*00c0*/ MOV R2, c[0x0][0x164] ; /* 0x0000590000027a02 */
/* 0x001fc80000000f00 */
/*00d0*/ IADD3 R3, R2.reuse, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fda0003f06070 */
/*0100*/ @!P0 BRA 0x780 ; /* 0x0000067000008947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R6, -R2, c[0x0][0x164], RZ ; /* 0x0000590002067a10 */
/* 0x000fc80007ffe1ff */
/*0120*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f04270 */
/*0130*/ @!P0 BRA 0x690 ; /* 0x0000055000008947 */
/* 0x000fea0003800000 */
/*0140*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*0150*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0160*/ @!P1 BRA 0x4b0 ; /* 0x0000034000009947 */
/* 0x000fea0003800000 */
/*0170*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0180*/ FMUL R4, R5, R5 ; /* 0x0000000505047220 */
/* 0x020fe20000400000 */
/*0190*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc60007ffe0ff */
/*01a0*/ FFMA R4, R4, R5, -R5 ; /* 0x0000000504047223 */
/* 0x000fe20000000805 */
/*01b0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fc60003f24270 */
/*01c0*/ FMUL R4, R4, 2.5 ; /* 0x4020000004047820 */
/* 0x000fc80000400000 */
/*01d0*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fc80000400000 */
/*01e0*/ FFMA R3, R4, R3, -R4 ; /* 0x0000000304037223 */
/* 0x000fc80000000804 */
/*01f0*/ FMUL R3, R3, 2.5 ; /* 0x4020000003037820 */
/* 0x000fc80000400000 */
/*0200*/ FMUL R4, R3, R3 ; /* 0x0000000303047220 */
/* 0x000fc80000400000 */
/*0210*/ FFMA R4, R3, R4, -R3 ; /* 0x0000000403047223 */
/* 0x000fc80000000803 */
/*0220*/ FMUL R4, R4, 2.5 ; /* 0x4020000004047820 */
/* 0x000fc80000400000 */
/*0230*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fc80000400000 */
/*0240*/ FFMA R3, R4, R3, -R4 ; /* 0x0000000304037223 */
/* 0x000fc80000000804 */
/*0250*/ FMUL R3, R3, 2.5 ; /* 0x4020000003037820 */
/* 0x000fc80000400000 */
/*0260*/ FMUL R4, R3, R3 ; /* 0x0000000303047220 */
/* 0x000fc80000400000 */
/*0270*/ FFMA R4, R3, R4, -R3 ; /* 0x0000000403047223 */
/* 0x000fc80000000803 */
/*0280*/ FMUL R4, R4, 2.5 ; /* 0x4020000004047820 */
/* 0x000fc80000400000 */
/*0290*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fc80000400000 */
/*02a0*/ FFMA R3, R4, R3, -R4 ; /* 0x0000000304037223 */
/* 0x000fc80000000804 */
/*02b0*/ FMUL R3, R3, 2.5 ; /* 0x4020000003037820 */
/* 0x000fc80000400000 */
/*02c0*/ FMUL R4, R3, R3 ; /* 0x0000000303047220 */
/* 0x000fc80000400000 */
/*02d0*/ FFMA R4, R3, R4, -R3 ; /* 0x0000000403047223 */
/* 0x000fc80000000803 */
/*02e0*/ FMUL R4, R4, 2.5 ; /* 0x4020000004047820 */
/* 0x000fc80000400000 */
/*02f0*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fc80000400000 */
/*0300*/ FFMA R3, R4, R3, -R4 ; /* 0x0000000304037223 */
/* 0x000fc80000000804 */
/*0310*/ FMUL R3, R3, 2.5 ; /* 0x4020000003037820 */
/* 0x000fc80000400000 */
/*0320*/ FMUL R4, R3, R3 ; /* 0x0000000303047220 */
/* 0x000fc80000400000 */
/*0330*/ FFMA R4, R3, R4, -R3 ; /* 0x0000000403047223 */
/* 0x000fc80000000803 */
/*0340*/ FMUL R4, R4, 2.5 ; /* 0x4020000004047820 */
/* 0x000fc80000400000 */
/*0350*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fc80000400000 */
/*0360*/ FFMA R3, R4, R3, -R4 ; /* 0x0000000304037223 */
/* 0x000fc80000000804 */
/*0370*/ FMUL R3, R3, 2.5 ; /* 0x4020000003037820 */
/* 0x000fc80000400000 */
/*0380*/ FMUL R4, R3, R3 ; /* 0x0000000303047220 */
/* 0x000fc80000400000 */
/*0390*/ FFMA R4, R3, R4, -R3 ; /* 0x0000000403047223 */
/* 0x000fc80000000803 */
/*03a0*/ FMUL R4, R4, 2.5 ; /* 0x4020000004047820 */
/* 0x000fc80000400000 */
/*03b0*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fc80000400000 */
/*03c0*/ FFMA R3, R4, R3, -R4 ; /* 0x0000000304037223 */
/* 0x000fc80000000804 */
/*03d0*/ FMUL R3, R3, 2.5 ; /* 0x4020000003037820 */
/* 0x000fc80000400000 */
/*03e0*/ FMUL R4, R3, R3 ; /* 0x0000000303047220 */
/* 0x000fc80000400000 */
/*03f0*/ FFMA R4, R3, R4, -R3 ; /* 0x0000000403047223 */
/* 0x000fc80000000803 */
/*0400*/ FMUL R4, R4, 2.5 ; /* 0x4020000004047820 */
/* 0x000fc80000400000 */
/*0410*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fc80000400000 */
/*0420*/ FFMA R3, R4, R3, -R4 ; /* 0x0000000304037223 */
/* 0x000fc80000000804 */
/*0430*/ FMUL R3, R3, 2.5 ; /* 0x4020000003037820 */
/* 0x000fc80000400000 */
/*0440*/ FMUL R4, R3, R3 ; /* 0x0000000303047220 */
/* 0x000fc80000400000 */
/*0450*/ FFMA R4, R3, R4, -R3 ; /* 0x0000000403047223 */
/* 0x000fc80000000803 */
/*0460*/ FMUL R4, R4, 2.5 ; /* 0x4020000004047820 */
/* 0x000fc80000400000 */
/*0470*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fc80000400000 */
/*0480*/ FFMA R3, R4, R3, -R4 ; /* 0x0000000304037223 */
/* 0x000fc80000000804 */
/*0490*/ FMUL R5, R3, 2.5 ; /* 0x4020000003057820 */
/* 0x000fe20000400000 */
/*04a0*/ @P1 BRA 0x180 ; /* 0xfffffcd000001947 */
/* 0x000fea000383ffff */
/*04b0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*04c0*/ @!P1 BRA 0x670 ; /* 0x000001a000009947 */
/* 0x000fea0003800000 */
/*04d0*/ FMUL R4, R5.reuse, R5 ; /* 0x0000000505047220 */
/* 0x060fe20000400000 */
/*04e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*04f0*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0500*/ FFMA R4, R5, R4, -R5 ; /* 0x0000000405047223 */
/* 0x000fc80000000805 */
/*0510*/ FMUL R4, R4, 2.5 ; /* 0x4020000004047820 */
/* 0x000fc80000400000 */
/*0520*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fc80000400000 */
/*0530*/ FFMA R3, R4, R3, -R4 ; /* 0x0000000304037223 */
/* 0x000fc80000000804 */
/*0540*/ FMUL R3, R3, 2.5 ; /* 0x4020000003037820 */
/* 0x000fc80000400000 */
/*0550*/ FMUL R4, R3, R3 ; /* 0x0000000303047220 */
/* 0x000fc80000400000 */
/*0560*/ FFMA R4, R3, R4, -R3 ; /* 0x0000000403047223 */
/* 0x000fc80000000803 */
/*0570*/ FMUL R4, R4, 2.5 ; /* 0x4020000004047820 */
/* 0x000fc80000400000 */
/*0580*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fc80000400000 */
/*0590*/ FFMA R3, R4, R3, -R4 ; /* 0x0000000304037223 */
/* 0x000fc80000000804 */
/*05a0*/ FMUL R3, R3, 2.5 ; /* 0x4020000003037820 */
/* 0x000fc80000400000 */
/*05b0*/ FMUL R4, R3, R3 ; /* 0x0000000303047220 */
/* 0x000fc80000400000 */
/*05c0*/ FFMA R4, R3, R4, -R3 ; /* 0x0000000403047223 */
/* 0x000fc80000000803 */
/*05d0*/ FMUL R4, R4, 2.5 ; /* 0x4020000004047820 */
/* 0x000fc80000400000 */
/*05e0*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fc80000400000 */
/*05f0*/ FFMA R3, R4, R3, -R4 ; /* 0x0000000304037223 */
/* 0x000fc80000000804 */
/*0600*/ FMUL R3, R3, 2.5 ; /* 0x4020000003037820 */
/* 0x000fc80000400000 */
/*0610*/ FMUL R4, R3, R3 ; /* 0x0000000303047220 */
/* 0x000fc80000400000 */
/*0620*/ FFMA R4, R3, R4, -R3 ; /* 0x0000000403047223 */
/* 0x000fc80000000803 */
/*0630*/ FMUL R4, R4, 2.5 ; /* 0x4020000004047820 */
/* 0x000fc80000400000 */
/*0640*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fc80000400000 */
/*0650*/ FFMA R3, R4, R3, -R4 ; /* 0x0000000304037223 */
/* 0x000fc80000000804 */
/*0660*/ FMUL R5, R3, 2.5 ; /* 0x4020000003057820 */
/* 0x000fe40000400000 */
/*0670*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0680*/ @!P0 BRA 0x780 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0690*/ FMUL R4, R5, R5 ; /* 0x0000000505047220 */
/* 0x020fe20000400000 */
/*06a0*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc60007ffe0ff */
/*06b0*/ FFMA R4, R4, R5, -R5 ; /* 0x0000000504047223 */
/* 0x000fe20000000805 */
/*06c0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc60003f05270 */
/*06d0*/ FMUL R4, R4, 2.5 ; /* 0x4020000004047820 */
/* 0x000fc80000400000 */
/*06e0*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fc80000400000 */
/*06f0*/ FFMA R3, R4, R3, -R4 ; /* 0x0000000304037223 */
/* 0x000fc80000000804 */
/*0700*/ FMUL R3, R3, 2.5 ; /* 0x4020000003037820 */
/* 0x000fc80000400000 */
/*0710*/ FMUL R4, R3, R3 ; /* 0x0000000303047220 */
/* 0x000fc80000400000 */
/*0720*/ FFMA R4, R3, R4, -R3 ; /* 0x0000000403047223 */
/* 0x000fc80000000803 */
/*0730*/ FMUL R4, R4, 2.5 ; /* 0x4020000004047820 */
/* 0x000fc80000400000 */
/*0740*/ FMUL R3, R4, R4 ; /* 0x0000000404037220 */
/* 0x000fc80000400000 */
/*0750*/ FFMA R3, R4, R3, -R4 ; /* 0x0000000304037223 */
/* 0x000fc80000000804 */
/*0760*/ FMUL R5, R3, 2.5 ; /* 0x4020000003057820 */
/* 0x000fe20000400000 */
/*0770*/ @P0 BRA 0x690 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*0780*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*0790*/ @!P0 BRA 0x800 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*07a0*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe20007ffe0ff */
/*07b0*/ FMUL R4, R5, R5 ; /* 0x0000000505047220 */
/* 0x020fc60000400000 */
/*07c0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*07d0*/ FFMA R4, R4, R5, -R5 ; /* 0x0000000504047223 */
/* 0x000fc80000000805 */
/*07e0*/ FMUL R5, R4, 2.5 ; /* 0x4020000004057820 */
/* 0x000fd00000400000 */
/*07f0*/ @P0 BRA 0x7a0 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*0800*/ LEA R2, P0, R0, c[0x0][0x170], 0x2 ; /* 0x00005c0000027a11 */
/* 0x001fc800078010ff */
/*0810*/ LEA.HI.X R3, R0, c[0x0][0x174], RZ, 0x2, P0 ; /* 0x00005d0000037a11 */
/* 0x000fca00000f14ff */
/*0820*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x020fe2000c101904 */
/*0830*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0840*/ BRA 0x840; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8f_kerneljjPfS_
.globl _Z8f_kerneljjPfS_
.p2align 8
.type _Z8f_kerneljjPfS_,@function
_Z8f_kerneljjPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x8
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_load_b32 s2, s[0:1], 0x4
global_load_b32 v0, v[3:4], off
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB0_3
.LBB0_2:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, v0, v0
s_add_i32 s2, s2, -1
v_fma_f32 v0, v0, v3, -v0
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v0, 0x40200000, v0
s_cmp_eq_u32 s2, 0
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v0, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8f_kerneljjPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8f_kerneljjPfS_, .Lfunc_end0-_Z8f_kerneljjPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12saxpy_kerneljfPfS_
.globl _Z12saxpy_kerneljfPfS_
.p2align 8
.type _Z12saxpy_kerneljfPfS_,@function
_Z12saxpy_kerneljfPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x8
v_mov_b32_e32 v2, 0
s_load_b32 s0, s[0:1], 0x4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b32 v4, v[2:3], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, s0, v0
global_store_b32 v[2:3], v4, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12saxpy_kerneljfPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12saxpy_kerneljfPfS_, .Lfunc_end1-_Z12saxpy_kerneljfPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8f_kerneljjPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8f_kerneljjPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12saxpy_kerneljfPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12saxpy_kerneljfPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cassert>
typedef void (* execute_task_t)(void *);
class CubeTask {
double* xi;
execute_task_t* cube_on_device;
public:
__host__ __device__ CubeTask();
__host__ __device__ CubeTask(execute_task_t* cube_fp, double* x) : cube_on_device(cube_fp), xi(x) {}
__device__ void execute() {
(*cube_on_device)(xi);
}
};
__device__
void cube(void* xv) {
double* xi = static_cast<double*>(xv);
*xi = (*xi) * (*xi) * (*xi);
}
__global__
void task_kernel(CubeTask* tasks, int size) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < size) {
tasks[tid].execute();
}
}
__global__
void get_cube_pointer(execute_task_t* device_pointer) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid == 0) *device_pointer = cube;
}
int main(int argc, char* argv[]) {
double* x = NULL;
int size = 100;
execute_task_t* device_cube_fun_p = NULL;
CubeTask* tasks = NULL;
cudaError_t cuda_status = cudaSuccess;
cuda_status = cudaMallocManaged(&x, sizeof(double) * size);
assert(cuda_status == cudaSuccess);
cuda_status = cudaMallocManaged(&device_cube_fun_p, sizeof(execute_task_t));
assert(cuda_status == cudaSuccess);
cuda_status = cudaMallocManaged(&tasks, sizeof(CubeTask)*size);
assert(cuda_status == cudaSuccess);
get_cube_pointer<<<1,1>>>(device_cube_fun_p);
for (int i = 0; i < size; i++) {
x[i] = 2.0;
}
for (int i = 0; i < size; i++) {
tasks[i] = CubeTask(device_cube_fun_p, &x[i]);
}
int numThreads = std::min(32, size);
int numBlocks = static_cast<int>(ceil(((double) size)/((double) numThreads)));
task_kernel<<<numBlocks, numThreads>>>(tasks, size);
cuda_status = cudaDeviceSynchronize();
assert(cuda_status == cudaSuccess);
double xsum = 0.0;
for (int i = 0; i < size; i++) {
xsum += x[i];
}
std::cout << "sum of elementwise cubed x is: " << xsum << std::endl;
if (xsum == 800.0) std::cout << "SUCCESS!" << std::endl;
else std::cout << "ERROR!" << std::endl;
return 0;
} | code for sm_80
Function : _Z16get_cube_pointerPPFvPvE
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0030*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe40000000800 */
/*0040*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x001fe2000f8e023f */
/*0050*/ IMAD.MOV R0, RZ, RZ, -R0 ; /* 0x000000ffff007224 */
/* 0x002fca00078e0a00 */
/*0060*/ ISETP.NE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf05270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R4, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff047435 */
/* 0x000fe200000001ff */
/*0090*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fca00078e00ff */
/*00d0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101b04 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fca0007ffe0ff */
/*0100*/ STL [R1], R2 ; /* 0x0000000201007387 */
/* 0x0001e40000100800 */
/*0110*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0120*/ LD.E.64 R2, [R4.64] ; /* 0x0000000404027980 */
/* 0x001ea4000c101b00 */
/*0130*/ DMUL R6, R2, R2 ; /* 0x0000000202067228 */
/* 0x004e0c0000000000 */
/*0140*/ DMUL R6, R2, R6 ; /* 0x0000000602067228 */
/* 0x001e0e0000000000 */
/*0150*/ ST.E.64 [R4.64], R6 ; /* 0x0000000604007985 */
/* 0x0011e8000c101b04 */
/*0160*/ LDL R2, [R1] ; /* 0x0000000001027983 */
/* 0x0001640000100800 */
/*0170*/ IADD3 R1, R1, 0x8, RZ ; /* 0x0000000801017810 */
/* 0x001fe20007ffe0ff */
/*0180*/ RET.REL.NODEC R20 0x0 ; /* 0xfffffe7014007950 */
/* 0x020fec0003c3ffff */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11task_kernelP8CubeTaski
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E.64 R6, [R2.64+0x8] ; /* 0x0000080402067981 */
/* 0x000ea8000c1e1b00 */
/*00a0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000168000c1e1b00 */
/*00b0*/ LD.E R6, [R6.64] ; /* 0x0000000406067980 */
/* 0x004ea4000c101900 */
/*00c0*/ LDC.64 R8, c[0x2][R6] ; /* 0x0080000006087b82 */
/* 0x0040640000000a00 */
/*00d0*/ BSSY B6, 0x120 ; /* 0x0000004000067945 */
/* 0x000fe20003800000 */
/*00e0*/ MOV R20, 0x110 ; /* 0x0000011000147802 */
/* 0x000fe20000000f00 */
/*00f0*/ IMAD.MOV.U32 R21, RZ, RZ, 0x0 ; /* 0x00000000ff157424 */
/* 0x000fc800078e00ff */
/*0100*/ CALL.REL.NOINC R8 0x0 ; /* 0xfffffef008007344 */
/* 0x023fea0003c3ffff */
/*0110*/ BSYNC B6 ; /* 0x0000000000067941 */
/* 0x000fea0003800000 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe40007ffe0ff */
/*0140*/ MOV R3, R5 ; /* 0x0000000500037202 */
/* 0x000fc60000000f00 */
/*0150*/ STL [R1], R2 ; /* 0x0000000201007387 */
/* 0x0001e40000100800 */
/*0160*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x001fc600078e0004 */
/*0170*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0180*/ LD.E.64 R4, [R2.64] ; /* 0x0000000402047980 */
/* 0x000ea4000c101b00 */
/*0190*/ DMUL R6, R4, R4 ; /* 0x0000000404067228 */
/* 0x004e0c0000000000 */
/*01a0*/ DMUL R6, R4, R6 ; /* 0x0000000604067228 */
/* 0x001e0e0000000000 */
/*01b0*/ ST.E.64 [R2.64], R6 ; /* 0x0000000602007985 */
/* 0x0011e8000c101b04 */
/*01c0*/ LDL R2, [R1] ; /* 0x0000000001027983 */
/* 0x0011640000100800 */
/*01d0*/ IADD3 R1, R1, 0x8, RZ ; /* 0x0000000801017810 */
/* 0x001fe20007ffe0ff */
/*01e0*/ RET.REL.NODEC R20 0x0 ; /* 0xfffffe1014007950 */
/* 0x020fec0003c3ffff */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cassert>
typedef void (* execute_task_t)(void *);
class CubeTask {
double* xi;
execute_task_t* cube_on_device;
public:
__host__ __device__ CubeTask();
__host__ __device__ CubeTask(execute_task_t* cube_fp, double* x) : cube_on_device(cube_fp), xi(x) {}
__device__ void execute() {
(*cube_on_device)(xi);
}
};
__device__
void cube(void* xv) {
double* xi = static_cast<double*>(xv);
*xi = (*xi) * (*xi) * (*xi);
}
__global__
void task_kernel(CubeTask* tasks, int size) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < size) {
tasks[tid].execute();
}
}
__global__
void get_cube_pointer(execute_task_t* device_pointer) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid == 0) *device_pointer = cube;
}
int main(int argc, char* argv[]) {
double* x = NULL;
int size = 100;
execute_task_t* device_cube_fun_p = NULL;
CubeTask* tasks = NULL;
cudaError_t cuda_status = cudaSuccess;
cuda_status = cudaMallocManaged(&x, sizeof(double) * size);
assert(cuda_status == cudaSuccess);
cuda_status = cudaMallocManaged(&device_cube_fun_p, sizeof(execute_task_t));
assert(cuda_status == cudaSuccess);
cuda_status = cudaMallocManaged(&tasks, sizeof(CubeTask)*size);
assert(cuda_status == cudaSuccess);
get_cube_pointer<<<1,1>>>(device_cube_fun_p);
for (int i = 0; i < size; i++) {
x[i] = 2.0;
}
for (int i = 0; i < size; i++) {
tasks[i] = CubeTask(device_cube_fun_p, &x[i]);
}
int numThreads = std::min(32, size);
int numBlocks = static_cast<int>(ceil(((double) size)/((double) numThreads)));
task_kernel<<<numBlocks, numThreads>>>(tasks, size);
cuda_status = cudaDeviceSynchronize();
assert(cuda_status == cudaSuccess);
double xsum = 0.0;
for (int i = 0; i < size; i++) {
xsum += x[i];
}
std::cout << "sum of elementwise cubed x is: " << xsum << std::endl;
if (xsum == 800.0) std::cout << "SUCCESS!" << std::endl;
else std::cout << "ERROR!" << std::endl;
return 0;
} | .file "tmpxft_0006342c_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3678:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3678:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4cubePv
.type _Z4cubePv, @function
_Z4cubePv:
.LFB3673:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3673:
.size _Z4cubePv, .-_Z4cubePv
.globl _Z40__device_stub__Z11task_kernelP8CubeTaskiP8CubeTaski
.type _Z40__device_stub__Z11task_kernelP8CubeTaskiP8CubeTaski, @function
_Z40__device_stub__Z11task_kernelP8CubeTaskiP8CubeTaski:
.LFB3700:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11task_kernelP8CubeTaski(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3700:
.size _Z40__device_stub__Z11task_kernelP8CubeTaskiP8CubeTaski, .-_Z40__device_stub__Z11task_kernelP8CubeTaskiP8CubeTaski
.globl _Z11task_kernelP8CubeTaski
.type _Z11task_kernelP8CubeTaski, @function
_Z11task_kernelP8CubeTaski:
.LFB3701:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z11task_kernelP8CubeTaskiP8CubeTaski
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _Z11task_kernelP8CubeTaski, .-_Z11task_kernelP8CubeTaski
.globl _Z41__device_stub__Z16get_cube_pointerPPFvPvEPPFvPvE
.type _Z41__device_stub__Z16get_cube_pointerPPFvPvEPPFvPvE, @function
_Z41__device_stub__Z16get_cube_pointerPPFvPvEPPFvPvE:
.LFB3702:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16get_cube_pointerPPFvPvE(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3702:
.size _Z41__device_stub__Z16get_cube_pointerPPFvPvEPPFvPvE, .-_Z41__device_stub__Z16get_cube_pointerPPFvPvEPPFvPvE
.globl _Z16get_cube_pointerPPFvPvE
.type _Z16get_cube_pointerPPFvPvE, @function
_Z16get_cube_pointerPPFvPvE:
.LFB3703:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z16get_cube_pointerPPFvPvEPPFvPvE
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3703:
.size _Z16get_cube_pointerPPFvPvE, .-_Z16get_cube_pointerPPFvPvE
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "sum of elementwise cubed x is: "
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "SUCCESS!"
.LC5:
.string "ERROR!"
.text
.globl main
.type main, @function
main:
.LFB3674:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
leaq 8(%rsp), %rdi
movl $1, %edx
movl $800, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $8, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $1600, %esi
call cudaMallocManaged@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L22:
movl $0, %eax
movsd .LC1(%rip), %xmm0
.L23:
movq 8(%rsp), %rdx
movsd %xmm0, (%rdx,%rax)
addq $8, %rax
cmpq $800, %rax
jne .L23
movl $0, %eax
.L24:
movq 16(%rsp), %rcx
movq 24(%rsp), %rdx
leaq (%rdx,%rax,2), %rdx
movq %rax, %rsi
addq 8(%rsp), %rsi
movq %rsi, (%rdx)
movq %rcx, 8(%rdx)
addq $8, %rax
cmpq $800, %rax
jne .L24
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $4, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L25:
call cudaDeviceSynchronize@PLT
movq 8(%rsp), %rax
leaq 800(%rax), %rdx
movl $0x000000000, %ebx
.L26:
movq %rbx, %xmm1
addsd (%rax), %xmm1
movq %xmm1, %rbx
addq $8, %rax
cmpq %rdx, %rax
jne .L26
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbx, %xmm2
ucomisd .LC3(%rip), %xmm2
jp .L27
jne .L27
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L29:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L38
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movq 16(%rsp), %rdi
call _Z41__device_stub__Z16get_cube_pointerPPFvPvEPPFvPvE
jmp .L22
.L37:
movl $100, %esi
movq 24(%rsp), %rdi
call _Z40__device_stub__Z11task_kernelP8CubeTaskiP8CubeTaski
jmp .L25
.L27:
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L29
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3674:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z16get_cube_pointerPPFvPvE"
.LC7:
.string "_Z11task_kernelP8CubeTaski"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3705:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z16get_cube_pointerPPFvPvE(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z11task_kernelP8CubeTaski(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3705:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1073741824
.align 8
.LC3:
.long 0
.long 1082720256
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cassert>
typedef void (* execute_task_t)(void *);
class CubeTask {
double* xi;
execute_task_t* cube_on_device;
public:
__host__ __device__ CubeTask();
__host__ __device__ CubeTask(execute_task_t* cube_fp, double* x) : cube_on_device(cube_fp), xi(x) {}
__device__ void execute() {
(*cube_on_device)(xi);
}
};
__device__
void cube(void* xv) {
double* xi = static_cast<double*>(xv);
*xi = (*xi) * (*xi) * (*xi);
}
__global__
void task_kernel(CubeTask* tasks, int size) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < size) {
tasks[tid].execute();
}
}
__global__
void get_cube_pointer(execute_task_t* device_pointer) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid == 0) *device_pointer = cube;
}
int main(int argc, char* argv[]) {
double* x = NULL;
int size = 100;
execute_task_t* device_cube_fun_p = NULL;
CubeTask* tasks = NULL;
cudaError_t cuda_status = cudaSuccess;
cuda_status = cudaMallocManaged(&x, sizeof(double) * size);
assert(cuda_status == cudaSuccess);
cuda_status = cudaMallocManaged(&device_cube_fun_p, sizeof(execute_task_t));
assert(cuda_status == cudaSuccess);
cuda_status = cudaMallocManaged(&tasks, sizeof(CubeTask)*size);
assert(cuda_status == cudaSuccess);
get_cube_pointer<<<1,1>>>(device_cube_fun_p);
for (int i = 0; i < size; i++) {
x[i] = 2.0;
}
for (int i = 0; i < size; i++) {
tasks[i] = CubeTask(device_cube_fun_p, &x[i]);
}
int numThreads = std::min(32, size);
int numBlocks = static_cast<int>(ceil(((double) size)/((double) numThreads)));
task_kernel<<<numBlocks, numThreads>>>(tasks, size);
cuda_status = cudaDeviceSynchronize();
assert(cuda_status == cudaSuccess);
double xsum = 0.0;
for (int i = 0; i < size; i++) {
xsum += x[i];
}
std::cout << "sum of elementwise cubed x is: " << xsum << std::endl;
if (xsum == 800.0) std::cout << "SUCCESS!" << std::endl;
else std::cout << "ERROR!" << std::endl;
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <cassert>
typedef void (* execute_task_t)(void *);
class CubeTask {
double* xi;
execute_task_t* cube_on_device;
public:
__host__ __device__ CubeTask();
__host__ __device__ CubeTask(execute_task_t* cube_fp, double* x) : cube_on_device(cube_fp), xi(x) {}
__device__ void execute() {
(*cube_on_device)(xi);
}
};
__device__
void cube(void* xv) {
double* xi = static_cast<double*>(xv);
*xi = (*xi) * (*xi) * (*xi);
}
__global__
void task_kernel(CubeTask* tasks, int size) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < size) {
tasks[tid].execute();
}
}
__global__
void get_cube_pointer(execute_task_t* device_pointer) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid == 0) *device_pointer = cube;
}
int main(int argc, char* argv[]) {
double* x = NULL;
int size = 100;
execute_task_t* device_cube_fun_p = NULL;
CubeTask* tasks = NULL;
hipError_t cuda_status = hipSuccess;
cuda_status = hipMallocManaged(&x, sizeof(double) * size);
assert(cuda_status == hipSuccess);
cuda_status = hipMallocManaged(&device_cube_fun_p, sizeof(execute_task_t));
assert(cuda_status == hipSuccess);
cuda_status = hipMallocManaged(&tasks, sizeof(CubeTask)*size);
assert(cuda_status == hipSuccess);
get_cube_pointer<<<1,1>>>(device_cube_fun_p);
for (int i = 0; i < size; i++) {
x[i] = 2.0;
}
for (int i = 0; i < size; i++) {
tasks[i] = CubeTask(device_cube_fun_p, &x[i]);
}
int numThreads = std::min(32, size);
int numBlocks = static_cast<int>(ceil(((double) size)/((double) numThreads)));
task_kernel<<<numBlocks, numThreads>>>(tasks, size);
cuda_status = hipDeviceSynchronize();
assert(cuda_status == hipSuccess);
double xsum = 0.0;
for (int i = 0; i < size; i++) {
xsum += x[i];
}
std::cout << "sum of elementwise cubed x is: " << xsum << std::endl;
if (xsum == 800.0) std::cout << "SUCCESS!" << std::endl;
else std::cout << "ERROR!" << std::endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cassert>
typedef void (* execute_task_t)(void *);
class CubeTask {
double* xi;
execute_task_t* cube_on_device;
public:
__host__ __device__ CubeTask();
__host__ __device__ CubeTask(execute_task_t* cube_fp, double* x) : cube_on_device(cube_fp), xi(x) {}
__device__ void execute() {
(*cube_on_device)(xi);
}
};
__device__
void cube(void* xv) {
double* xi = static_cast<double*>(xv);
*xi = (*xi) * (*xi) * (*xi);
}
__global__
void task_kernel(CubeTask* tasks, int size) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < size) {
tasks[tid].execute();
}
}
__global__
void get_cube_pointer(execute_task_t* device_pointer) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid == 0) *device_pointer = cube;
}
int main(int argc, char* argv[]) {
double* x = NULL;
int size = 100;
execute_task_t* device_cube_fun_p = NULL;
CubeTask* tasks = NULL;
hipError_t cuda_status = hipSuccess;
cuda_status = hipMallocManaged(&x, sizeof(double) * size);
assert(cuda_status == hipSuccess);
cuda_status = hipMallocManaged(&device_cube_fun_p, sizeof(execute_task_t));
assert(cuda_status == hipSuccess);
cuda_status = hipMallocManaged(&tasks, sizeof(CubeTask)*size);
assert(cuda_status == hipSuccess);
get_cube_pointer<<<1,1>>>(device_cube_fun_p);
for (int i = 0; i < size; i++) {
x[i] = 2.0;
}
for (int i = 0; i < size; i++) {
tasks[i] = CubeTask(device_cube_fun_p, &x[i]);
}
int numThreads = std::min(32, size);
int numBlocks = static_cast<int>(ceil(((double) size)/((double) numThreads)));
task_kernel<<<numBlocks, numThreads>>>(tasks, size);
cuda_status = hipDeviceSynchronize();
assert(cuda_status == hipSuccess);
double xsum = 0.0;
for (int i = 0; i < size; i++) {
xsum += x[i];
}
std::cout << "sum of elementwise cubed x is: " << xsum << std::endl;
if (xsum == 800.0) std::cout << "SUCCESS!" << std::endl;
else std::cout << "ERROR!" << std::endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.p2align 2
.type _Z4cubePv,@function
_Z4cubePv:
s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
flat_load_b64 v[2:3], v[0:1]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mul_f64 v[4:5], v[2:3], v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[2:3], v[2:3], v[4:5]
flat_store_b64 v[0:1], v[2:3]
s_waitcnt lgkmcnt(0)
s_setpc_b64 s[30:31]
.Lfunc_end0:
.size _Z4cubePv, .Lfunc_end0-_Z4cubePv
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11task_kernelP8CubeTaski
.globl _Z11task_kernelP8CubeTaski
.p2align 8
.type _Z11task_kernelP8CubeTaski,@function
_Z11task_kernelP8CubeTaski:
s_mov_b64 s[36:37], s[0:1]
s_clause 0x1
s_load_b32 s0, s[2:3], 0x1c
s_load_b32 s1, s[2:3], 0x8
v_mov_b32_e32 v31, v0
s_mov_b32 s40, s13
s_mov_b32 s32, 0
s_delay_alu instid0(VALU_DEP_1)
v_and_b32_e32 v2, 0x3ff, v31
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s0, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s40, s0, v[2:3]
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s1, v0
s_cbranch_execz .LBB1_3
s_load_b64 s[0:1], s[2:3], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_add_u32 s38, s2, 16
s_mov_b32 s33, s15
s_mov_b32 s41, s14
s_mov_b64 s[34:35], s[4:5]
v_lshlrev_b64 v[0:1], 4, v[0:1]
s_addc_u32 s39, s3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s0, exec_lo
global_load_b128 v[0:3], v[0:1], off
s_waitcnt vmcnt(0)
flat_load_b64 v[2:3], v[2:3]
.LBB1_2:
s_waitcnt vmcnt(0) lgkmcnt(0)
v_readfirstlane_b32 s0, v2
v_readfirstlane_b32 s1, v3
s_mov_b32 s42, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u64_e64 s[0:1], v[2:3]
s_mov_b64 s[4:5], s[36:37]
s_mov_b64 s[8:9], s[38:39]
s_mov_b64 s[10:11], s[34:35]
s_mov_b32 s12, s40
s_mov_b32 s13, s41
s_mov_b32 s14, s33
s_swappc_b64 s[30:31], s[0:1]
s_xor_b32 exec_lo, exec_lo, s42
s_cbranch_execnz .LBB1_2
.LBB1_3:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11task_kernelP8CubeTaski
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 1
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 1
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 1
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 43
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z11task_kernelP8CubeTaski, .Lfunc_end1-_Z11task_kernelP8CubeTaski
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16get_cube_pointerPPFvPvE
.globl _Z16get_cube_pointerPPFvPvE
.p2align 8
.type _Z16get_cube_pointerPPFvPvE,@function
_Z16get_cube_pointerPPFvPvE:
s_load_b32 s2, s[0:1], 0x14
v_sub_nc_u32_e32 v0, 0, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s15, s15, s2
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e64 s15, v0
s_cbranch_execz .LBB2_2
s_load_b64 s[0:1], s[0:1], 0x0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, _Z4cubePv@rel32@lo+4
s_addc_u32 s3, s3, _Z4cubePv@rel32@hi+12
v_mov_b32_e32 v2, 0
v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
s_waitcnt lgkmcnt(0)
global_store_b64 v2, v[0:1], s[0:1]
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16get_cube_pointerPPFvPvE
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z16get_cube_pointerPPFvPvE, .Lfunc_end2-_Z16get_cube_pointerPPFvPvE
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z4cubePv
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 96
.size: 8
.value_kind: hidden_hostcall_buffer
- .offset: 104
.size: 8
.value_kind: hidden_multigrid_sync_arg
- .offset: 112
.size: 8
.value_kind: hidden_heap_v1
- .offset: 120
.size: 8
.value_kind: hidden_default_queue
- .offset: 216
.size: 8
.value_kind: hidden_queue_ptr
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11task_kernelP8CubeTaski
.private_segment_fixed_size: 0
.sgpr_count: 45
.sgpr_spill_count: 0
.symbol: _Z11task_kernelP8CubeTaski.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: true
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16get_cube_pointerPPFvPvE
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z16get_cube_pointerPPFvPvE.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cassert>
typedef void (* execute_task_t)(void *);
class CubeTask {
double* xi;
execute_task_t* cube_on_device;
public:
__host__ __device__ CubeTask();
__host__ __device__ CubeTask(execute_task_t* cube_fp, double* x) : cube_on_device(cube_fp), xi(x) {}
__device__ void execute() {
(*cube_on_device)(xi);
}
};
__device__
void cube(void* xv) {
double* xi = static_cast<double*>(xv);
*xi = (*xi) * (*xi) * (*xi);
}
__global__
void task_kernel(CubeTask* tasks, int size) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid < size) {
tasks[tid].execute();
}
}
__global__
void get_cube_pointer(execute_task_t* device_pointer) {
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if (tid == 0) *device_pointer = cube;
}
int main(int argc, char* argv[]) {
double* x = NULL;
int size = 100;
execute_task_t* device_cube_fun_p = NULL;
CubeTask* tasks = NULL;
hipError_t cuda_status = hipSuccess;
cuda_status = hipMallocManaged(&x, sizeof(double) * size);
assert(cuda_status == hipSuccess);
cuda_status = hipMallocManaged(&device_cube_fun_p, sizeof(execute_task_t));
assert(cuda_status == hipSuccess);
cuda_status = hipMallocManaged(&tasks, sizeof(CubeTask)*size);
assert(cuda_status == hipSuccess);
get_cube_pointer<<<1,1>>>(device_cube_fun_p);
for (int i = 0; i < size; i++) {
x[i] = 2.0;
}
for (int i = 0; i < size; i++) {
tasks[i] = CubeTask(device_cube_fun_p, &x[i]);
}
int numThreads = std::min(32, size);
int numBlocks = static_cast<int>(ceil(((double) size)/((double) numThreads)));
task_kernel<<<numBlocks, numThreads>>>(tasks, size);
cuda_status = hipDeviceSynchronize();
assert(cuda_status == hipSuccess);
double xsum = 0.0;
for (int i = 0; i < size; i++) {
xsum += x[i];
}
std::cout << "sum of elementwise cubed x is: " << xsum << std::endl;
if (xsum == 800.0) std::cout << "SUCCESS!" << std::endl;
else std::cout << "ERROR!" << std::endl;
return 0;
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z26__device_stub__task_kernelP8CubeTaski # -- Begin function _Z26__device_stub__task_kernelP8CubeTaski
.p2align 4, 0x90
.type _Z26__device_stub__task_kernelP8CubeTaski,@function
_Z26__device_stub__task_kernelP8CubeTaski: # @_Z26__device_stub__task_kernelP8CubeTaski
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11task_kernelP8CubeTaski, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__task_kernelP8CubeTaski, .Lfunc_end0-_Z26__device_stub__task_kernelP8CubeTaski
.cfi_endproc
# -- End function
.globl _Z31__device_stub__get_cube_pointerPPFvPvE # -- Begin function _Z31__device_stub__get_cube_pointerPPFvPvE
.p2align 4, 0x90
.type _Z31__device_stub__get_cube_pointerPPFvPvE,@function
_Z31__device_stub__get_cube_pointerPPFvPvE: # @_Z31__device_stub__get_cube_pointerPPFvPvE
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z16get_cube_pointerPPFvPvE, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z31__device_stub__get_cube_pointerPPFvPvE, .Lfunc_end1-_Z31__device_stub__get_cube_pointerPPFvPvE
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x4089000000000000 # double 800
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $120, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movabsq $4294967297, %rbx # imm = 0x100000001
movq $0, 8(%rsp)
movq $0, 32(%rsp)
movq $0, 24(%rsp)
leaq 8(%rsp), %rdi
movl $800, %esi # imm = 0x320
movl $1, %edx
callq hipMallocManaged
leaq 32(%rsp), %rdi
movl $8, %esi
movl $1, %edx
callq hipMallocManaged
leaq 24(%rsp), %rdi
movl $1600, %esi # imm = 0x640
movl $1, %edx
callq hipMallocManaged
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 32(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 96(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z16get_cube_pointerPPFvPvE, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 8(%rsp), %rax
xorl %ecx, %ecx
movabsq $4611686018427387904, %rdx # imm = 0x4000000000000000
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movq %rdx, (%rax,%rcx,8)
incq %rcx
cmpq $100, %rcx
jne .LBB2_3
# %bb.4: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_5: # %.preheader
# =>This Inner Loop Header: Depth=1
movq 32(%rsp), %rcx
movq 8(%rsp), %rdx
addq %rax, %rdx
movq 24(%rsp), %rsi
movq %rdx, (%rsi,%rax,2)
movq %rcx, 8(%rsi,%rax,2)
addq $8, %rax
cmpq $800, %rax # imm = 0x320
jne .LBB2_5
# %bb.6:
leaq 3(%rbx), %rdi
addq $31, %rbx
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq 24(%rsp), %rax
movq %rax, 64(%rsp)
movl $100, 76(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 76(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11task_kernelP8CubeTaski, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
callq hipDeviceSynchronize
xorpd %xmm0, %xmm0
xorl %eax, %eax
movq 8(%rsp), %rcx
.p2align 4, 0x90
.LBB2_9: # =>This Inner Loop Header: Depth=1
addsd (%rcx,%rax,8), %xmm0
incq %rax
cmpq $100, %rax
jne .LBB2_9
# %bb.10:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $31, %edx
movsd %xmm0, 112(%rsp) # 8-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 112(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_23
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB2_13
# %bb.12:
movzbl 67(%rbx), %ecx
jmp .LBB2_14
.LBB2_13:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movsd 112(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
ucomisd .LCPI2_0(%rip), %xmm0
jne .LBB2_18
jp .LBB2_18
# %bb.15:
movl $.L.str.1, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_23
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i32
cmpb $0, 56(%rbx)
je .LBB2_21
.LBB2_17:
movzbl 67(%rbx), %eax
jmp .LBB2_22
.LBB2_18:
movl $.L.str.2, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_23
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i37
cmpb $0, 56(%rbx)
jne .LBB2_17
.LBB2_21:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit35
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_23:
.cfi_def_cfa_offset 144
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11task_kernelP8CubeTaski, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16get_cube_pointerPPFvPvE, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11task_kernelP8CubeTaski,@object # @_Z11task_kernelP8CubeTaski
.section .rodata,"a",@progbits
.globl _Z11task_kernelP8CubeTaski
.p2align 3, 0x0
_Z11task_kernelP8CubeTaski:
.quad _Z26__device_stub__task_kernelP8CubeTaski
.size _Z11task_kernelP8CubeTaski, 8
.type _Z16get_cube_pointerPPFvPvE,@object # @_Z16get_cube_pointerPPFvPvE
.globl _Z16get_cube_pointerPPFvPvE
.p2align 3, 0x0
_Z16get_cube_pointerPPFvPvE:
.quad _Z31__device_stub__get_cube_pointerPPFvPvE
.size _Z16get_cube_pointerPPFvPvE, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "sum of elementwise cubed x is: "
.size .L.str, 32
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "SUCCESS!"
.size .L.str.1, 9
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ERROR!"
.size .L.str.2, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11task_kernelP8CubeTaski"
.size .L__unnamed_1, 27
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16get_cube_pointerPPFvPvE"
.size .L__unnamed_2, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__task_kernelP8CubeTaski
.addrsig_sym _Z31__device_stub__get_cube_pointerPPFvPvE
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11task_kernelP8CubeTaski
.addrsig_sym _Z16get_cube_pointerPPFvPvE
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16get_cube_pointerPPFvPvE
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0030*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe40000000800 */
/*0040*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x001fe2000f8e023f */
/*0050*/ IMAD.MOV R0, RZ, RZ, -R0 ; /* 0x000000ffff007224 */
/* 0x002fca00078e0a00 */
/*0060*/ ISETP.NE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf05270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R4, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff047435 */
/* 0x000fe200000001ff */
/*0090*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fca00078e00ff */
/*00d0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101b04 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fca0007ffe0ff */
/*0100*/ STL [R1], R2 ; /* 0x0000000201007387 */
/* 0x0001e40000100800 */
/*0110*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0120*/ LD.E.64 R2, [R4.64] ; /* 0x0000000404027980 */
/* 0x001ea4000c101b00 */
/*0130*/ DMUL R6, R2, R2 ; /* 0x0000000202067228 */
/* 0x004e0c0000000000 */
/*0140*/ DMUL R6, R2, R6 ; /* 0x0000000602067228 */
/* 0x001e0e0000000000 */
/*0150*/ ST.E.64 [R4.64], R6 ; /* 0x0000000604007985 */
/* 0x0011e8000c101b04 */
/*0160*/ LDL R2, [R1] ; /* 0x0000000001027983 */
/* 0x0001640000100800 */
/*0170*/ IADD3 R1, R1, 0x8, RZ ; /* 0x0000000801017810 */
/* 0x001fe20007ffe0ff */
/*0180*/ RET.REL.NODEC R20 0x0 ; /* 0xfffffe7014007950 */
/* 0x020fec0003c3ffff */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11task_kernelP8CubeTaski
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E.64 R6, [R2.64+0x8] ; /* 0x0000080402067981 */
/* 0x000ea8000c1e1b00 */
/*00a0*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000168000c1e1b00 */
/*00b0*/ LD.E R6, [R6.64] ; /* 0x0000000406067980 */
/* 0x004ea4000c101900 */
/*00c0*/ LDC.64 R8, c[0x2][R6] ; /* 0x0080000006087b82 */
/* 0x0040640000000a00 */
/*00d0*/ BSSY B6, 0x120 ; /* 0x0000004000067945 */
/* 0x000fe20003800000 */
/*00e0*/ MOV R20, 0x110 ; /* 0x0000011000147802 */
/* 0x000fe20000000f00 */
/*00f0*/ IMAD.MOV.U32 R21, RZ, RZ, 0x0 ; /* 0x00000000ff157424 */
/* 0x000fc800078e00ff */
/*0100*/ CALL.REL.NOINC R8 0x0 ; /* 0xfffffef008007344 */
/* 0x023fea0003c3ffff */
/*0110*/ BSYNC B6 ; /* 0x0000000000067941 */
/* 0x000fea0003800000 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe40007ffe0ff */
/*0140*/ MOV R3, R5 ; /* 0x0000000500037202 */
/* 0x000fc60000000f00 */
/*0150*/ STL [R1], R2 ; /* 0x0000000201007387 */
/* 0x0001e40000100800 */
/*0160*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x001fc600078e0004 */
/*0170*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0180*/ LD.E.64 R4, [R2.64] ; /* 0x0000000402047980 */
/* 0x000ea4000c101b00 */
/*0190*/ DMUL R6, R4, R4 ; /* 0x0000000404067228 */
/* 0x004e0c0000000000 */
/*01a0*/ DMUL R6, R4, R6 ; /* 0x0000000604067228 */
/* 0x001e0e0000000000 */
/*01b0*/ ST.E.64 [R2.64], R6 ; /* 0x0000000602007985 */
/* 0x0011e8000c101b04 */
/*01c0*/ LDL R2, [R1] ; /* 0x0000000001027983 */
/* 0x0011640000100800 */
/*01d0*/ IADD3 R1, R1, 0x8, RZ ; /* 0x0000000801017810 */
/* 0x001fe20007ffe0ff */
/*01e0*/ RET.REL.NODEC R20 0x0 ; /* 0xfffffe1014007950 */
/* 0x020fec0003c3ffff */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.p2align 2
.type _Z4cubePv,@function
_Z4cubePv:
s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
flat_load_b64 v[2:3], v[0:1]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mul_f64 v[4:5], v[2:3], v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[2:3], v[2:3], v[4:5]
flat_store_b64 v[0:1], v[2:3]
s_waitcnt lgkmcnt(0)
s_setpc_b64 s[30:31]
.Lfunc_end0:
.size _Z4cubePv, .Lfunc_end0-_Z4cubePv
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11task_kernelP8CubeTaski
.globl _Z11task_kernelP8CubeTaski
.p2align 8
.type _Z11task_kernelP8CubeTaski,@function
_Z11task_kernelP8CubeTaski:
s_mov_b64 s[36:37], s[0:1]
s_clause 0x1
s_load_b32 s0, s[2:3], 0x1c
s_load_b32 s1, s[2:3], 0x8
v_mov_b32_e32 v31, v0
s_mov_b32 s40, s13
s_mov_b32 s32, 0
s_delay_alu instid0(VALU_DEP_1)
v_and_b32_e32 v2, 0x3ff, v31
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s0, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s40, s0, v[2:3]
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s1, v0
s_cbranch_execz .LBB1_3
s_load_b64 s[0:1], s[2:3], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_add_u32 s38, s2, 16
s_mov_b32 s33, s15
s_mov_b32 s41, s14
s_mov_b64 s[34:35], s[4:5]
v_lshlrev_b64 v[0:1], 4, v[0:1]
s_addc_u32 s39, s3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s0, exec_lo
global_load_b128 v[0:3], v[0:1], off
s_waitcnt vmcnt(0)
flat_load_b64 v[2:3], v[2:3]
.LBB1_2:
s_waitcnt vmcnt(0) lgkmcnt(0)
v_readfirstlane_b32 s0, v2
v_readfirstlane_b32 s1, v3
s_mov_b32 s42, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u64_e64 s[0:1], v[2:3]
s_mov_b64 s[4:5], s[36:37]
s_mov_b64 s[8:9], s[38:39]
s_mov_b64 s[10:11], s[34:35]
s_mov_b32 s12, s40
s_mov_b32 s13, s41
s_mov_b32 s14, s33
s_swappc_b64 s[30:31], s[0:1]
s_xor_b32 exec_lo, exec_lo, s42
s_cbranch_execnz .LBB1_2
.LBB1_3:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11task_kernelP8CubeTaski
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 1
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 1
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 1
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 43
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z11task_kernelP8CubeTaski, .Lfunc_end1-_Z11task_kernelP8CubeTaski
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16get_cube_pointerPPFvPvE
.globl _Z16get_cube_pointerPPFvPvE
.p2align 8
.type _Z16get_cube_pointerPPFvPvE,@function
_Z16get_cube_pointerPPFvPvE:
s_load_b32 s2, s[0:1], 0x14
v_sub_nc_u32_e32 v0, 0, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s15, s15, s2
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e64 s15, v0
s_cbranch_execz .LBB2_2
s_load_b64 s[0:1], s[0:1], 0x0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, _Z4cubePv@rel32@lo+4
s_addc_u32 s3, s3, _Z4cubePv@rel32@hi+12
v_mov_b32_e32 v2, 0
v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
s_waitcnt lgkmcnt(0)
global_store_b64 v2, v[0:1], s[0:1]
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16get_cube_pointerPPFvPvE
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z16get_cube_pointerPPFvPvE, .Lfunc_end2-_Z16get_cube_pointerPPFvPvE
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z4cubePv
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 96
.size: 8
.value_kind: hidden_hostcall_buffer
- .offset: 104
.size: 8
.value_kind: hidden_multigrid_sync_arg
- .offset: 112
.size: 8
.value_kind: hidden_heap_v1
- .offset: 120
.size: 8
.value_kind: hidden_default_queue
- .offset: 216
.size: 8
.value_kind: hidden_queue_ptr
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11task_kernelP8CubeTaski
.private_segment_fixed_size: 0
.sgpr_count: 45
.sgpr_spill_count: 0
.symbol: _Z11task_kernelP8CubeTaski.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: true
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16get_cube_pointerPPFvPvE
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z16get_cube_pointerPPFvPvE.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006342c_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3678:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3678:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4cubePv
.type _Z4cubePv, @function
_Z4cubePv:
.LFB3673:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3673:
.size _Z4cubePv, .-_Z4cubePv
.globl _Z40__device_stub__Z11task_kernelP8CubeTaskiP8CubeTaski
.type _Z40__device_stub__Z11task_kernelP8CubeTaskiP8CubeTaski, @function
_Z40__device_stub__Z11task_kernelP8CubeTaskiP8CubeTaski:
.LFB3700:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11task_kernelP8CubeTaski(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3700:
.size _Z40__device_stub__Z11task_kernelP8CubeTaskiP8CubeTaski, .-_Z40__device_stub__Z11task_kernelP8CubeTaskiP8CubeTaski
.globl _Z11task_kernelP8CubeTaski
.type _Z11task_kernelP8CubeTaski, @function
_Z11task_kernelP8CubeTaski:
.LFB3701:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z11task_kernelP8CubeTaskiP8CubeTaski
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _Z11task_kernelP8CubeTaski, .-_Z11task_kernelP8CubeTaski
.globl _Z41__device_stub__Z16get_cube_pointerPPFvPvEPPFvPvE
.type _Z41__device_stub__Z16get_cube_pointerPPFvPvEPPFvPvE, @function
_Z41__device_stub__Z16get_cube_pointerPPFvPvEPPFvPvE:
.LFB3702:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16get_cube_pointerPPFvPvE(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3702:
.size _Z41__device_stub__Z16get_cube_pointerPPFvPvEPPFvPvE, .-_Z41__device_stub__Z16get_cube_pointerPPFvPvEPPFvPvE
.globl _Z16get_cube_pointerPPFvPvE
.type _Z16get_cube_pointerPPFvPvE, @function
_Z16get_cube_pointerPPFvPvE:
.LFB3703:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z16get_cube_pointerPPFvPvEPPFvPvE
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3703:
.size _Z16get_cube_pointerPPFvPvE, .-_Z16get_cube_pointerPPFvPvE
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "sum of elementwise cubed x is: "
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "SUCCESS!"
.LC5:
.string "ERROR!"
.text
.globl main
.type main, @function
main:
.LFB3674:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movq $0, 16(%rsp)
movq $0, 24(%rsp)
leaq 8(%rsp), %rdi
movl $1, %edx
movl $800, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $8, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $1600, %esi
call cudaMallocManaged@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L36
.L22:
movl $0, %eax
movsd .LC1(%rip), %xmm0
.L23:
movq 8(%rsp), %rdx
movsd %xmm0, (%rdx,%rax)
addq $8, %rax
cmpq $800, %rax
jne .L23
movl $0, %eax
.L24:
movq 16(%rsp), %rcx
movq 24(%rsp), %rdx
leaq (%rdx,%rax,2), %rdx
movq %rax, %rsi
addq 8(%rsp), %rsi
movq %rsi, (%rdx)
movq %rcx, 8(%rdx)
addq $8, %rax
cmpq $800, %rax
jne .L24
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $4, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L25:
call cudaDeviceSynchronize@PLT
movq 8(%rsp), %rax
leaq 800(%rax), %rdx
movl $0x000000000, %ebx
.L26:
movq %rbx, %xmm1
addsd (%rax), %xmm1
movq %xmm1, %rbx
addq $8, %rax
cmpq %rdx, %rax
jne .L26
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbx, %xmm2
ucomisd .LC3(%rip), %xmm2
jp .L27
jne .L27
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L29:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L38
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movq 16(%rsp), %rdi
call _Z41__device_stub__Z16get_cube_pointerPPFvPvEPPFvPvE
jmp .L22
.L37:
movl $100, %esi
movq 24(%rsp), %rdi
call _Z40__device_stub__Z11task_kernelP8CubeTaskiP8CubeTaski
jmp .L25
.L27:
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L29
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3674:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z16get_cube_pointerPPFvPvE"
.LC7:
.string "_Z11task_kernelP8CubeTaski"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3705:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z16get_cube_pointerPPFvPvE(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z11task_kernelP8CubeTaski(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3705:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1073741824
.align 8
.LC3:
.long 0
.long 1082720256
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z26__device_stub__task_kernelP8CubeTaski # -- Begin function _Z26__device_stub__task_kernelP8CubeTaski
.p2align 4, 0x90
.type _Z26__device_stub__task_kernelP8CubeTaski,@function
_Z26__device_stub__task_kernelP8CubeTaski: # @_Z26__device_stub__task_kernelP8CubeTaski
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11task_kernelP8CubeTaski, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__task_kernelP8CubeTaski, .Lfunc_end0-_Z26__device_stub__task_kernelP8CubeTaski
.cfi_endproc
# -- End function
.globl _Z31__device_stub__get_cube_pointerPPFvPvE # -- Begin function _Z31__device_stub__get_cube_pointerPPFvPvE
.p2align 4, 0x90
.type _Z31__device_stub__get_cube_pointerPPFvPvE,@function
_Z31__device_stub__get_cube_pointerPPFvPvE: # @_Z31__device_stub__get_cube_pointerPPFvPvE
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z16get_cube_pointerPPFvPvE, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z31__device_stub__get_cube_pointerPPFvPvE, .Lfunc_end1-_Z31__device_stub__get_cube_pointerPPFvPvE
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x4089000000000000 # double 800
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $120, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movabsq $4294967297, %rbx # imm = 0x100000001
movq $0, 8(%rsp)
movq $0, 32(%rsp)
movq $0, 24(%rsp)
leaq 8(%rsp), %rdi
movl $800, %esi # imm = 0x320
movl $1, %edx
callq hipMallocManaged
leaq 32(%rsp), %rdi
movl $8, %esi
movl $1, %edx
callq hipMallocManaged
leaq 24(%rsp), %rdi
movl $1600, %esi # imm = 0x640
movl $1, %edx
callq hipMallocManaged
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 32(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 96(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z16get_cube_pointerPPFvPvE, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 8(%rsp), %rax
xorl %ecx, %ecx
movabsq $4611686018427387904, %rdx # imm = 0x4000000000000000
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movq %rdx, (%rax,%rcx,8)
incq %rcx
cmpq $100, %rcx
jne .LBB2_3
# %bb.4: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_5: # %.preheader
# =>This Inner Loop Header: Depth=1
movq 32(%rsp), %rcx
movq 8(%rsp), %rdx
addq %rax, %rdx
movq 24(%rsp), %rsi
movq %rdx, (%rsi,%rax,2)
movq %rcx, 8(%rsi,%rax,2)
addq $8, %rax
cmpq $800, %rax # imm = 0x320
jne .LBB2_5
# %bb.6:
leaq 3(%rbx), %rdi
addq $31, %rbx
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_8
# %bb.7:
movq 24(%rsp), %rax
movq %rax, 64(%rsp)
movl $100, 76(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 76(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11task_kernelP8CubeTaski, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_8:
callq hipDeviceSynchronize
xorpd %xmm0, %xmm0
xorl %eax, %eax
movq 8(%rsp), %rcx
.p2align 4, 0x90
.LBB2_9: # =>This Inner Loop Header: Depth=1
addsd (%rcx,%rax,8), %xmm0
incq %rax
cmpq $100, %rax
jne .LBB2_9
# %bb.10:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $31, %edx
movsd %xmm0, 112(%rsp) # 8-byte Spill
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 112(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_23
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB2_13
# %bb.12:
movzbl 67(%rbx), %ecx
jmp .LBB2_14
.LBB2_13:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movsd 112(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
ucomisd .LCPI2_0(%rip), %xmm0
jne .LBB2_18
jp .LBB2_18
# %bb.15:
movl $.L.str.1, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_23
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i32
cmpb $0, 56(%rbx)
je .LBB2_21
.LBB2_17:
movzbl 67(%rbx), %eax
jmp .LBB2_22
.LBB2_18:
movl $.L.str.2, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_23
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i37
cmpb $0, 56(%rbx)
jne .LBB2_17
.LBB2_21:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit35
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_23:
.cfi_def_cfa_offset 144
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11task_kernelP8CubeTaski, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16get_cube_pointerPPFvPvE, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11task_kernelP8CubeTaski,@object # @_Z11task_kernelP8CubeTaski
.section .rodata,"a",@progbits
.globl _Z11task_kernelP8CubeTaski
.p2align 3, 0x0
_Z11task_kernelP8CubeTaski:
.quad _Z26__device_stub__task_kernelP8CubeTaski
.size _Z11task_kernelP8CubeTaski, 8
.type _Z16get_cube_pointerPPFvPvE,@object # @_Z16get_cube_pointerPPFvPvE
.globl _Z16get_cube_pointerPPFvPvE
.p2align 3, 0x0
_Z16get_cube_pointerPPFvPvE:
.quad _Z31__device_stub__get_cube_pointerPPFvPvE
.size _Z16get_cube_pointerPPFvPvE, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "sum of elementwise cubed x is: "
.size .L.str, 32
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "SUCCESS!"
.size .L.str.1, 9
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ERROR!"
.size .L.str.2, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11task_kernelP8CubeTaski"
.size .L__unnamed_1, 27
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16get_cube_pointerPPFvPvE"
.size .L__unnamed_2, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__task_kernelP8CubeTaski
.addrsig_sym _Z31__device_stub__get_cube_pointerPPFvPvE
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11task_kernelP8CubeTaski
.addrsig_sym _Z16get_cube_pointerPPFvPvE
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void AddIntsCUDA(int* a, int* b) {
for (int i = 0; i < 1000005; i++) {
a[0] += b[0];
}
} | code for sm_80
Function : _Z11AddIntsCUDAPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0060*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*0080*/ IADD3 R7, R0, R7, RZ ; /* 0x0000000700077210 */
/* 0x004fca0007ffe0ff */
/*0090*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*00a0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*00b0*/ IMAD.IADD R9, R7, 0x1, R0 ; /* 0x0000000107097824 */
/* 0x004fca00078e0200 */
/*00c0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*00d0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*00e0*/ IADD3 R11, R9, R0, RZ ; /* 0x00000000090b7210 */
/* 0x004fca0007ffe0ff */
/*00f0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*0100*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*0110*/ IMAD.IADD R13, R11, 0x1, R0 ; /* 0x000000010b0d7824 */
/* 0x004fca00078e0200 */
/*0120*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e8000c101904 */
/*0130*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000e24000c1e1900 */
/*0140*/ IADD3 R7, R13, R0, RZ ; /* 0x000000000d077210 */
/* 0x001fe20007ffe0ff */
/*0150*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fc800078e00ff */
/*0160*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0003e6000c101904 */
/*0170*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*0180*/ IADD3 R7, R6, R7, RZ ; /* 0x0000000706077210 */
/* 0x016fca0007ffe0ff */
/*0190*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*01a0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*01b0*/ IMAD.IADD R9, R7, 0x1, R6 ; /* 0x0000000107097824 */
/* 0x004fca00078e0206 */
/*01c0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*01d0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*01e0*/ IADD3 R11, R9, R6, RZ ; /* 0x00000006090b7210 */
/* 0x004fca0007ffe0ff */
/*01f0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0200*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee4000c1e1900 */
/*0210*/ IMAD.IADD R13, R11, 0x1, R6 ; /* 0x000000010b0d7824 */
/* 0x008fca00078e0206 */
/*0220*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*0230*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e24000c1e1900 */
/*0240*/ IADD3 R7, R13, R6, RZ ; /* 0x000000060d077210 */
/* 0x001fca0007ffe0ff */
/*0250*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*0260*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e64000c1e1900 */
/*0270*/ IMAD.IADD R9, R7, 0x1, R6 ; /* 0x0000000107097824 */
/* 0x002fca00078e0206 */
/*0280*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0290*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*02a0*/ IADD3 R11, R9, R6, RZ ; /* 0x00000006090b7210 */
/* 0x004fca0007ffe0ff */
/*02b0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*02c0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee4000c1e1900 */
/*02d0*/ IMAD.IADD R13, R11, 0x1, R6 ; /* 0x000000010b0d7824 */
/* 0x008fca00078e0206 */
/*02e0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*02f0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e24000c1e1900 */
/*0300*/ IADD3 R7, R13, R6, RZ ; /* 0x000000060d077210 */
/* 0x001fca0007ffe0ff */
/*0310*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*0320*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e64000c1e1900 */
/*0330*/ IMAD.IADD R9, R7, 0x1, R6 ; /* 0x0000000107097824 */
/* 0x002fca00078e0206 */
/*0340*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0350*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*0360*/ IADD3 R11, R9, R6, RZ ; /* 0x00000006090b7210 */
/* 0x004fca0007ffe0ff */
/*0370*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0380*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee4000c1e1900 */
/*0390*/ IMAD.IADD R13, R11, 0x1, R6 ; /* 0x000000010b0d7824 */
/* 0x008fca00078e0206 */
/*03a0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*03b0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e24000c1e1900 */
/*03c0*/ IADD3 R7, R13, R6, RZ ; /* 0x000000060d077210 */
/* 0x001fca0007ffe0ff */
/*03d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*03e0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e64000c1e1900 */
/*03f0*/ IMAD.IADD R9, R7, 0x1, R6 ; /* 0x0000000107097824 */
/* 0x002fca00078e0206 */
/*0400*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0410*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*0420*/ IADD3 R11, R9, R6, RZ ; /* 0x00000006090b7210 */
/* 0x004fca0007ffe0ff */
/*0430*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0440*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee4000c1e1900 */
/*0450*/ IMAD.IADD R13, R11, 0x1, R6 ; /* 0x000000010b0d7824 */
/* 0x008fca00078e0206 */
/*0460*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*0470*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e24000c1e1900 */
/*0480*/ IADD3 R7, R13, R6, RZ ; /* 0x000000060d077210 */
/* 0x001fca0007ffe0ff */
/*0490*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*04a0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e64000c1e1900 */
/*04b0*/ IMAD.IADD R9, R7, 0x1, R6 ; /* 0x0000000107097824 */
/* 0x002fca00078e0206 */
/*04c0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*04d0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*04e0*/ IADD3 R11, R9, R6, RZ ; /* 0x00000006090b7210 */
/* 0x004fca0007ffe0ff */
/*04f0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0500*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee4000c1e1900 */
/*0510*/ IMAD.IADD R13, R11, 0x1, R6 ; /* 0x000000010b0d7824 */
/* 0x008fca00078e0206 */
/*0520*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*0530*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e24000c1e1900 */
/*0540*/ IADD3 R7, R13, R6, RZ ; /* 0x000000060d077210 */
/* 0x001fca0007ffe0ff */
/*0550*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*0560*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e64000c1e1900 */
/*0570*/ IMAD.IADD R9, R7, 0x1, R6 ; /* 0x0000000107097824 */
/* 0x002fca00078e0206 */
/*0580*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0590*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*05a0*/ IADD3 R11, R9, R6, RZ ; /* 0x00000006090b7210 */
/* 0x004fca0007ffe0ff */
/*05b0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*05c0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee4000c1e1900 */
/*05d0*/ IMAD.IADD R13, R11, 0x1, R6 ; /* 0x000000010b0d7824 */
/* 0x008fca00078e0206 */
/*05e0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*05f0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e24000c1e1900 */
/*0600*/ IADD3 R7, R13, R6, RZ ; /* 0x000000060d077210 */
/* 0x001fca0007ffe0ff */
/*0610*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*0620*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e64000c1e1900 */
/*0630*/ IMAD.IADD R9, R7, 0x1, R6 ; /* 0x0000000107097824 */
/* 0x002fca00078e0206 */
/*0640*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0650*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*0660*/ IADD3 R11, R9, R6, RZ ; /* 0x00000006090b7210 */
/* 0x004fca0007ffe0ff */
/*0670*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0680*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee4000c1e1900 */
/*0690*/ IMAD.IADD R13, R11, 0x1, R6 ; /* 0x000000010b0d7824 */
/* 0x008fca00078e0206 */
/*06a0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*06b0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e24000c1e1900 */
/*06c0*/ IADD3 R7, R13, R6, RZ ; /* 0x000000060d077210 */
/* 0x001fca0007ffe0ff */
/*06d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*06e0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e64000c1e1900 */
/*06f0*/ IMAD.IADD R9, R7, 0x1, R6 ; /* 0x0000000107097824 */
/* 0x002fca00078e0206 */
/*0700*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0710*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*0720*/ IADD3 R11, R9, R6, RZ ; /* 0x00000006090b7210 */
/* 0x004fca0007ffe0ff */
/*0730*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0740*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee4000c1e1900 */
/*0750*/ IMAD.IADD R13, R11, 0x1, R6 ; /* 0x000000010b0d7824 */
/* 0x008fca00078e0206 */
/*0760*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*0770*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e24000c1e1900 */
/*0780*/ IADD3 R7, R13, R6, RZ ; /* 0x000000060d077210 */
/* 0x001fca0007ffe0ff */
/*0790*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*07a0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e64000c1e1900 */
/*07b0*/ IMAD.IADD R9, R7, 0x1, R6 ; /* 0x0000000107097824 */
/* 0x002fca00078e0206 */
/*07c0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*07d0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*07e0*/ IADD3 R11, R9, R6, RZ ; /* 0x00000006090b7210 */
/* 0x004fca0007ffe0ff */
/*07f0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0800*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee4000c1e1900 */
/*0810*/ IMAD.IADD R13, R11, 0x1, R6 ; /* 0x000000010b0d7824 */
/* 0x008fca00078e0206 */
/*0820*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*0830*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e24000c1e1900 */
/*0840*/ IADD3 R7, R13, R6, RZ ; /* 0x000000060d077210 */
/* 0x001fca0007ffe0ff */
/*0850*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*0860*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e64000c1e1900 */
/*0870*/ IMAD.IADD R9, R7, 0x1, R6 ; /* 0x0000000107097824 */
/* 0x002fca00078e0206 */
/*0880*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0890*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*08a0*/ IADD3 R11, R9, R6, RZ ; /* 0x00000006090b7210 */
/* 0x004fca0007ffe0ff */
/*08b0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*08c0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee4000c1e1900 */
/*08d0*/ IMAD.IADD R13, R11, 0x1, R6 ; /* 0x000000010b0d7824 */
/* 0x008fca00078e0206 */
/*08e0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*08f0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e24000c1e1900 */
/*0900*/ IADD3 R7, R13, R6, RZ ; /* 0x000000060d077210 */
/* 0x001fca0007ffe0ff */
/*0910*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*0920*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e64000c1e1900 */
/*0930*/ IMAD.IADD R9, R7, 0x1, R6 ; /* 0x0000000107097824 */
/* 0x002fca00078e0206 */
/*0940*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0950*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*0960*/ IADD3 R11, R9, R6, RZ ; /* 0x00000006090b7210 */
/* 0x004fca0007ffe0ff */
/*0970*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0980*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee4000c1e1900 */
/*0990*/ IMAD.IADD R13, R11, 0x1, R6 ; /* 0x000000010b0d7824 */
/* 0x008fca00078e0206 */
/*09a0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*09b0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e24000c1e1900 */
/*09c0*/ IADD3 R7, R13, R6, RZ ; /* 0x000000060d077210 */
/* 0x001fca0007ffe0ff */
/*09d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*09e0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e64000c1e1900 */
/*09f0*/ IMAD.IADD R9, R7, 0x1, R6 ; /* 0x0000000107097824 */
/* 0x002fca00078e0206 */
/*0a00*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0a10*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*0a20*/ IADD3 R11, R9, R6, RZ ; /* 0x00000006090b7210 */
/* 0x004fca0007ffe0ff */
/*0a30*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0a40*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee4000c1e1900 */
/*0a50*/ IMAD.IADD R13, R11, 0x1, R6 ; /* 0x000000010b0d7824 */
/* 0x008fca00078e0206 */
/*0a60*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*0a70*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e24000c1e1900 */
/*0a80*/ IADD3 R7, R13, R6, RZ ; /* 0x000000060d077210 */
/* 0x001fca0007ffe0ff */
/*0a90*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*0aa0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e64000c1e1900 */
/*0ab0*/ IMAD.IADD R9, R7, 0x1, R6 ; /* 0x0000000107097824 */
/* 0x002fca00078e0206 */
/*0ac0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0ad0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*0ae0*/ IADD3 R11, R9, R6, RZ ; /* 0x00000006090b7210 */
/* 0x004fca0007ffe0ff */
/*0af0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0b00*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee4000c1e1900 */
/*0b10*/ IMAD.IADD R13, R11, 0x1, R6 ; /* 0x000000010b0d7824 */
/* 0x008fca00078e0206 */
/*0b20*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*0b30*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e24000c1e1900 */
/*0b40*/ IADD3 R7, R13, R6, RZ ; /* 0x000000060d077210 */
/* 0x001fca0007ffe0ff */
/*0b50*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*0b60*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e64000c1e1900 */
/*0b70*/ IMAD.IADD R9, R7, 0x1, R6 ; /* 0x0000000107097824 */
/* 0x002fca00078e0206 */
/*0b80*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0b90*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*0ba0*/ IADD3 R11, R9, R6, RZ ; /* 0x00000006090b7210 */
/* 0x004fca0007ffe0ff */
/*0bb0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0bc0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee4000c1e1900 */
/*0bd0*/ IMAD.IADD R13, R11, 0x1, R6 ; /* 0x000000010b0d7824 */
/* 0x008fca00078e0206 */
/*0be0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*0bf0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e24000c1e1900 */
/*0c00*/ IADD3 R7, R13, R6, RZ ; /* 0x000000060d077210 */
/* 0x001fca0007ffe0ff */
/*0c10*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*0c20*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000f24000c1e1900 */
/*0c30*/ IMAD.IADD R15, R7, 0x1, R6 ; /* 0x00000001070f7824 */
/* 0x010fca00078e0206 */
/*0c40*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0009e8000c101904 */
/*0c50*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000f64000c1e1900 */
/*0c60*/ IADD3 R17, R15, R6, RZ ; /* 0x000000060f117210 */
/* 0x020fca0007ffe0ff */
/*0c70*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0009e8000c101904 */
/*0c80*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000f64000c1e1900 */
/*0c90*/ IMAD.IADD R19, R17, 0x1, R6 ; /* 0x0000000111137824 */
/* 0x020fca00078e0206 */
/*0ca0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0009e8000c101904 */
/*0cb0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e64000c1e1900 */
/*0cc0*/ IADD3 R9, R6, R19, RZ ; /* 0x0000001306097210 */
/* 0x002fca0007ffe0ff */
/*0cd0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0009e8000c101904 */
/*0ce0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*0cf0*/ IMAD.IADD R11, R9, 0x1, R6 ; /* 0x00000001090b7824 */
/* 0x004fca00078e0206 */
/*0d00*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0009e8000c101904 */
/*0d10*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee2000c1e1900 */
/*0d20*/ IADD3 R0, R0, 0x40, RZ ; /* 0x0000004000007810 */
/* 0x000fe40007ffe0ff */
/*0d30*/ IADD3 R13, R11, R6, RZ ; /* 0x000000060b0d7210 */
/* 0x008fca0007ffe0ff */
/*0d40*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0009e8000c101904 */
/*0d50*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e22000c1e1900 */
/*0d60*/ ISETP.NE.AND P0, PT, R0, 0xf4244, PT ; /* 0x000f42440000780c */
/* 0x000fe20003f05270 */
/*0d70*/ IMAD.IADD R7, R13, 0x1, R6 ; /* 0x000000010d077824 */
/* 0x001fca00078e0206 */
/*0d80*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0009ee000c101904 */
/*0d90*/ @P0 BRA 0x170 ; /* 0xfffff3d000000947 */
/* 0x000fea000383ffff */
/*0da0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0db0*/ BRA 0xdb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void AddIntsCUDA(int* a, int* b) {
for (int i = 0; i < 1000005; i++) {
a[0] += b[0];
}
} | .file "tmpxft_00184895_00000000-6_AddIntsCUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z11AddIntsCUDAPiS_PiS_
.type _Z33__device_stub__Z11AddIntsCUDAPiS_PiS_, @function
_Z33__device_stub__Z11AddIntsCUDAPiS_PiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11AddIntsCUDAPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z11AddIntsCUDAPiS_PiS_, .-_Z33__device_stub__Z11AddIntsCUDAPiS_PiS_
.globl _Z11AddIntsCUDAPiS_
.type _Z11AddIntsCUDAPiS_, @function
_Z11AddIntsCUDAPiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z11AddIntsCUDAPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11AddIntsCUDAPiS_, .-_Z11AddIntsCUDAPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11AddIntsCUDAPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11AddIntsCUDAPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void AddIntsCUDA(int* a, int* b) {
for (int i = 0; i < 1000005; i++) {
a[0] += b[0];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void AddIntsCUDA(int* a, int* b) {
for (int i = 0; i < 1000005; i++) {
a[0] += b[0];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void AddIntsCUDA(int* a, int* b) {
for (int i = 0; i < 1000005; i++) {
a[0] += b[0];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11AddIntsCUDAPiS_
.globl _Z11AddIntsCUDAPiS_
.p2align 8
.type _Z11AddIntsCUDAPiS_,@function
_Z11AddIntsCUDAPiS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_mov_b32 s4, 0xf4245
.LBB0_1:
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[2:3]
global_load_b32 v2, v0, s[0:1]
s_add_i32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s4, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_cbranch_scc0 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11AddIntsCUDAPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 5
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11AddIntsCUDAPiS_, .Lfunc_end0-_Z11AddIntsCUDAPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11AddIntsCUDAPiS_
.private_segment_fixed_size: 0
.sgpr_count: 5
.sgpr_spill_count: 0
.symbol: _Z11AddIntsCUDAPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void AddIntsCUDA(int* a, int* b) {
for (int i = 0; i < 1000005; i++) {
a[0] += b[0];
}
} | .text
.file "AddIntsCUDA.hip"
.globl _Z26__device_stub__AddIntsCUDAPiS_ # -- Begin function _Z26__device_stub__AddIntsCUDAPiS_
.p2align 4, 0x90
.type _Z26__device_stub__AddIntsCUDAPiS_,@function
_Z26__device_stub__AddIntsCUDAPiS_: # @_Z26__device_stub__AddIntsCUDAPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11AddIntsCUDAPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__AddIntsCUDAPiS_, .Lfunc_end0-_Z26__device_stub__AddIntsCUDAPiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11AddIntsCUDAPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11AddIntsCUDAPiS_,@object # @_Z11AddIntsCUDAPiS_
.section .rodata,"a",@progbits
.globl _Z11AddIntsCUDAPiS_
.p2align 3, 0x0
_Z11AddIntsCUDAPiS_:
.quad _Z26__device_stub__AddIntsCUDAPiS_
.size _Z11AddIntsCUDAPiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11AddIntsCUDAPiS_"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__AddIntsCUDAPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11AddIntsCUDAPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11AddIntsCUDAPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0060*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*0080*/ IADD3 R7, R0, R7, RZ ; /* 0x0000000700077210 */
/* 0x004fca0007ffe0ff */
/*0090*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*00a0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*00b0*/ IMAD.IADD R9, R7, 0x1, R0 ; /* 0x0000000107097824 */
/* 0x004fca00078e0200 */
/*00c0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*00d0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*00e0*/ IADD3 R11, R9, R0, RZ ; /* 0x00000000090b7210 */
/* 0x004fca0007ffe0ff */
/*00f0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0003e8000c101904 */
/*0100*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*0110*/ IMAD.IADD R13, R11, 0x1, R0 ; /* 0x000000010b0d7824 */
/* 0x004fca00078e0200 */
/*0120*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e8000c101904 */
/*0130*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000e24000c1e1900 */
/*0140*/ IADD3 R7, R13, R0, RZ ; /* 0x000000000d077210 */
/* 0x001fe20007ffe0ff */
/*0150*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fc800078e00ff */
/*0160*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0003e6000c101904 */
/*0170*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*0180*/ IADD3 R7, R6, R7, RZ ; /* 0x0000000706077210 */
/* 0x016fca0007ffe0ff */
/*0190*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*01a0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*01b0*/ IMAD.IADD R9, R7, 0x1, R6 ; /* 0x0000000107097824 */
/* 0x004fca00078e0206 */
/*01c0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*01d0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*01e0*/ IADD3 R11, R9, R6, RZ ; /* 0x00000006090b7210 */
/* 0x004fca0007ffe0ff */
/*01f0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0200*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee4000c1e1900 */
/*0210*/ IMAD.IADD R13, R11, 0x1, R6 ; /* 0x000000010b0d7824 */
/* 0x008fca00078e0206 */
/*0220*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*0230*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e24000c1e1900 */
/*0240*/ IADD3 R7, R13, R6, RZ ; /* 0x000000060d077210 */
/* 0x001fca0007ffe0ff */
/*0250*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*0260*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e64000c1e1900 */
/*0270*/ IMAD.IADD R9, R7, 0x1, R6 ; /* 0x0000000107097824 */
/* 0x002fca00078e0206 */
/*0280*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0290*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*02a0*/ IADD3 R11, R9, R6, RZ ; /* 0x00000006090b7210 */
/* 0x004fca0007ffe0ff */
/*02b0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*02c0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee4000c1e1900 */
/*02d0*/ IMAD.IADD R13, R11, 0x1, R6 ; /* 0x000000010b0d7824 */
/* 0x008fca00078e0206 */
/*02e0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*02f0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e24000c1e1900 */
/*0300*/ IADD3 R7, R13, R6, RZ ; /* 0x000000060d077210 */
/* 0x001fca0007ffe0ff */
/*0310*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*0320*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e64000c1e1900 */
/*0330*/ IMAD.IADD R9, R7, 0x1, R6 ; /* 0x0000000107097824 */
/* 0x002fca00078e0206 */
/*0340*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0350*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*0360*/ IADD3 R11, R9, R6, RZ ; /* 0x00000006090b7210 */
/* 0x004fca0007ffe0ff */
/*0370*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0380*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee4000c1e1900 */
/*0390*/ IMAD.IADD R13, R11, 0x1, R6 ; /* 0x000000010b0d7824 */
/* 0x008fca00078e0206 */
/*03a0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*03b0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e24000c1e1900 */
/*03c0*/ IADD3 R7, R13, R6, RZ ; /* 0x000000060d077210 */
/* 0x001fca0007ffe0ff */
/*03d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*03e0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e64000c1e1900 */
/*03f0*/ IMAD.IADD R9, R7, 0x1, R6 ; /* 0x0000000107097824 */
/* 0x002fca00078e0206 */
/*0400*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0410*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*0420*/ IADD3 R11, R9, R6, RZ ; /* 0x00000006090b7210 */
/* 0x004fca0007ffe0ff */
/*0430*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0440*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee4000c1e1900 */
/*0450*/ IMAD.IADD R13, R11, 0x1, R6 ; /* 0x000000010b0d7824 */
/* 0x008fca00078e0206 */
/*0460*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*0470*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e24000c1e1900 */
/*0480*/ IADD3 R7, R13, R6, RZ ; /* 0x000000060d077210 */
/* 0x001fca0007ffe0ff */
/*0490*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*04a0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e64000c1e1900 */
/*04b0*/ IMAD.IADD R9, R7, 0x1, R6 ; /* 0x0000000107097824 */
/* 0x002fca00078e0206 */
/*04c0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*04d0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*04e0*/ IADD3 R11, R9, R6, RZ ; /* 0x00000006090b7210 */
/* 0x004fca0007ffe0ff */
/*04f0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0500*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee4000c1e1900 */
/*0510*/ IMAD.IADD R13, R11, 0x1, R6 ; /* 0x000000010b0d7824 */
/* 0x008fca00078e0206 */
/*0520*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*0530*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e24000c1e1900 */
/*0540*/ IADD3 R7, R13, R6, RZ ; /* 0x000000060d077210 */
/* 0x001fca0007ffe0ff */
/*0550*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*0560*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e64000c1e1900 */
/*0570*/ IMAD.IADD R9, R7, 0x1, R6 ; /* 0x0000000107097824 */
/* 0x002fca00078e0206 */
/*0580*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0590*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*05a0*/ IADD3 R11, R9, R6, RZ ; /* 0x00000006090b7210 */
/* 0x004fca0007ffe0ff */
/*05b0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*05c0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee4000c1e1900 */
/*05d0*/ IMAD.IADD R13, R11, 0x1, R6 ; /* 0x000000010b0d7824 */
/* 0x008fca00078e0206 */
/*05e0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*05f0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e24000c1e1900 */
/*0600*/ IADD3 R7, R13, R6, RZ ; /* 0x000000060d077210 */
/* 0x001fca0007ffe0ff */
/*0610*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*0620*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e64000c1e1900 */
/*0630*/ IMAD.IADD R9, R7, 0x1, R6 ; /* 0x0000000107097824 */
/* 0x002fca00078e0206 */
/*0640*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0650*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*0660*/ IADD3 R11, R9, R6, RZ ; /* 0x00000006090b7210 */
/* 0x004fca0007ffe0ff */
/*0670*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0680*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee4000c1e1900 */
/*0690*/ IMAD.IADD R13, R11, 0x1, R6 ; /* 0x000000010b0d7824 */
/* 0x008fca00078e0206 */
/*06a0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*06b0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e24000c1e1900 */
/*06c0*/ IADD3 R7, R13, R6, RZ ; /* 0x000000060d077210 */
/* 0x001fca0007ffe0ff */
/*06d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*06e0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e64000c1e1900 */
/*06f0*/ IMAD.IADD R9, R7, 0x1, R6 ; /* 0x0000000107097824 */
/* 0x002fca00078e0206 */
/*0700*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0710*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*0720*/ IADD3 R11, R9, R6, RZ ; /* 0x00000006090b7210 */
/* 0x004fca0007ffe0ff */
/*0730*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0740*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee4000c1e1900 */
/*0750*/ IMAD.IADD R13, R11, 0x1, R6 ; /* 0x000000010b0d7824 */
/* 0x008fca00078e0206 */
/*0760*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*0770*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e24000c1e1900 */
/*0780*/ IADD3 R7, R13, R6, RZ ; /* 0x000000060d077210 */
/* 0x001fca0007ffe0ff */
/*0790*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*07a0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e64000c1e1900 */
/*07b0*/ IMAD.IADD R9, R7, 0x1, R6 ; /* 0x0000000107097824 */
/* 0x002fca00078e0206 */
/*07c0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*07d0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*07e0*/ IADD3 R11, R9, R6, RZ ; /* 0x00000006090b7210 */
/* 0x004fca0007ffe0ff */
/*07f0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0800*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee4000c1e1900 */
/*0810*/ IMAD.IADD R13, R11, 0x1, R6 ; /* 0x000000010b0d7824 */
/* 0x008fca00078e0206 */
/*0820*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*0830*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e24000c1e1900 */
/*0840*/ IADD3 R7, R13, R6, RZ ; /* 0x000000060d077210 */
/* 0x001fca0007ffe0ff */
/*0850*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*0860*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e64000c1e1900 */
/*0870*/ IMAD.IADD R9, R7, 0x1, R6 ; /* 0x0000000107097824 */
/* 0x002fca00078e0206 */
/*0880*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0890*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*08a0*/ IADD3 R11, R9, R6, RZ ; /* 0x00000006090b7210 */
/* 0x004fca0007ffe0ff */
/*08b0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*08c0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee4000c1e1900 */
/*08d0*/ IMAD.IADD R13, R11, 0x1, R6 ; /* 0x000000010b0d7824 */
/* 0x008fca00078e0206 */
/*08e0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*08f0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e24000c1e1900 */
/*0900*/ IADD3 R7, R13, R6, RZ ; /* 0x000000060d077210 */
/* 0x001fca0007ffe0ff */
/*0910*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*0920*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e64000c1e1900 */
/*0930*/ IMAD.IADD R9, R7, 0x1, R6 ; /* 0x0000000107097824 */
/* 0x002fca00078e0206 */
/*0940*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0950*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*0960*/ IADD3 R11, R9, R6, RZ ; /* 0x00000006090b7210 */
/* 0x004fca0007ffe0ff */
/*0970*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0980*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee4000c1e1900 */
/*0990*/ IMAD.IADD R13, R11, 0x1, R6 ; /* 0x000000010b0d7824 */
/* 0x008fca00078e0206 */
/*09a0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*09b0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e24000c1e1900 */
/*09c0*/ IADD3 R7, R13, R6, RZ ; /* 0x000000060d077210 */
/* 0x001fca0007ffe0ff */
/*09d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*09e0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e64000c1e1900 */
/*09f0*/ IMAD.IADD R9, R7, 0x1, R6 ; /* 0x0000000107097824 */
/* 0x002fca00078e0206 */
/*0a00*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0a10*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*0a20*/ IADD3 R11, R9, R6, RZ ; /* 0x00000006090b7210 */
/* 0x004fca0007ffe0ff */
/*0a30*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0a40*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee4000c1e1900 */
/*0a50*/ IMAD.IADD R13, R11, 0x1, R6 ; /* 0x000000010b0d7824 */
/* 0x008fca00078e0206 */
/*0a60*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*0a70*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e24000c1e1900 */
/*0a80*/ IADD3 R7, R13, R6, RZ ; /* 0x000000060d077210 */
/* 0x001fca0007ffe0ff */
/*0a90*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*0aa0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e64000c1e1900 */
/*0ab0*/ IMAD.IADD R9, R7, 0x1, R6 ; /* 0x0000000107097824 */
/* 0x002fca00078e0206 */
/*0ac0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0ad0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*0ae0*/ IADD3 R11, R9, R6, RZ ; /* 0x00000006090b7210 */
/* 0x004fca0007ffe0ff */
/*0af0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0b00*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee4000c1e1900 */
/*0b10*/ IMAD.IADD R13, R11, 0x1, R6 ; /* 0x000000010b0d7824 */
/* 0x008fca00078e0206 */
/*0b20*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*0b30*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e24000c1e1900 */
/*0b40*/ IADD3 R7, R13, R6, RZ ; /* 0x000000060d077210 */
/* 0x001fca0007ffe0ff */
/*0b50*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*0b60*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e64000c1e1900 */
/*0b70*/ IMAD.IADD R9, R7, 0x1, R6 ; /* 0x0000000107097824 */
/* 0x002fca00078e0206 */
/*0b80*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101904 */
/*0b90*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*0ba0*/ IADD3 R11, R9, R6, RZ ; /* 0x00000006090b7210 */
/* 0x004fca0007ffe0ff */
/*0bb0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101904 */
/*0bc0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee4000c1e1900 */
/*0bd0*/ IMAD.IADD R13, R11, 0x1, R6 ; /* 0x000000010b0d7824 */
/* 0x008fca00078e0206 */
/*0be0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e8000c101904 */
/*0bf0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e24000c1e1900 */
/*0c00*/ IADD3 R7, R13, R6, RZ ; /* 0x000000060d077210 */
/* 0x001fca0007ffe0ff */
/*0c10*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*0c20*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000f24000c1e1900 */
/*0c30*/ IMAD.IADD R15, R7, 0x1, R6 ; /* 0x00000001070f7824 */
/* 0x010fca00078e0206 */
/*0c40*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0009e8000c101904 */
/*0c50*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000f64000c1e1900 */
/*0c60*/ IADD3 R17, R15, R6, RZ ; /* 0x000000060f117210 */
/* 0x020fca0007ffe0ff */
/*0c70*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x0009e8000c101904 */
/*0c80*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000f64000c1e1900 */
/*0c90*/ IMAD.IADD R19, R17, 0x1, R6 ; /* 0x0000000111137824 */
/* 0x020fca00078e0206 */
/*0ca0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0009e8000c101904 */
/*0cb0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e64000c1e1900 */
/*0cc0*/ IADD3 R9, R6, R19, RZ ; /* 0x0000001306097210 */
/* 0x002fca0007ffe0ff */
/*0cd0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0009e8000c101904 */
/*0ce0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*0cf0*/ IMAD.IADD R11, R9, 0x1, R6 ; /* 0x00000001090b7824 */
/* 0x004fca00078e0206 */
/*0d00*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0009e8000c101904 */
/*0d10*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee2000c1e1900 */
/*0d20*/ IADD3 R0, R0, 0x40, RZ ; /* 0x0000004000007810 */
/* 0x000fe40007ffe0ff */
/*0d30*/ IADD3 R13, R11, R6, RZ ; /* 0x000000060b0d7210 */
/* 0x008fca0007ffe0ff */
/*0d40*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0009e8000c101904 */
/*0d50*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000e22000c1e1900 */
/*0d60*/ ISETP.NE.AND P0, PT, R0, 0xf4244, PT ; /* 0x000f42440000780c */
/* 0x000fe20003f05270 */
/*0d70*/ IMAD.IADD R7, R13, 0x1, R6 ; /* 0x000000010d077824 */
/* 0x001fca00078e0206 */
/*0d80*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0009ee000c101904 */
/*0d90*/ @P0 BRA 0x170 ; /* 0xfffff3d000000947 */
/* 0x000fea000383ffff */
/*0da0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0db0*/ BRA 0xdb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11AddIntsCUDAPiS_
.globl _Z11AddIntsCUDAPiS_
.p2align 8
.type _Z11AddIntsCUDAPiS_,@function
_Z11AddIntsCUDAPiS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v0, 0
s_mov_b32 s4, 0xf4245
.LBB0_1:
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[2:3]
global_load_b32 v2, v0, s[0:1]
s_add_i32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s4, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_cbranch_scc0 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11AddIntsCUDAPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 5
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11AddIntsCUDAPiS_, .Lfunc_end0-_Z11AddIntsCUDAPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11AddIntsCUDAPiS_
.private_segment_fixed_size: 0
.sgpr_count: 5
.sgpr_spill_count: 0
.symbol: _Z11AddIntsCUDAPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00184895_00000000-6_AddIntsCUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z11AddIntsCUDAPiS_PiS_
.type _Z33__device_stub__Z11AddIntsCUDAPiS_PiS_, @function
_Z33__device_stub__Z11AddIntsCUDAPiS_PiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11AddIntsCUDAPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z11AddIntsCUDAPiS_PiS_, .-_Z33__device_stub__Z11AddIntsCUDAPiS_PiS_
.globl _Z11AddIntsCUDAPiS_
.type _Z11AddIntsCUDAPiS_, @function
_Z11AddIntsCUDAPiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z11AddIntsCUDAPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11AddIntsCUDAPiS_, .-_Z11AddIntsCUDAPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11AddIntsCUDAPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11AddIntsCUDAPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "AddIntsCUDA.hip"
.globl _Z26__device_stub__AddIntsCUDAPiS_ # -- Begin function _Z26__device_stub__AddIntsCUDAPiS_
.p2align 4, 0x90
.type _Z26__device_stub__AddIntsCUDAPiS_,@function
_Z26__device_stub__AddIntsCUDAPiS_: # @_Z26__device_stub__AddIntsCUDAPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11AddIntsCUDAPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__AddIntsCUDAPiS_, .Lfunc_end0-_Z26__device_stub__AddIntsCUDAPiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11AddIntsCUDAPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11AddIntsCUDAPiS_,@object # @_Z11AddIntsCUDAPiS_
.section .rodata,"a",@progbits
.globl _Z11AddIntsCUDAPiS_
.p2align 3, 0x0
_Z11AddIntsCUDAPiS_:
.quad _Z26__device_stub__AddIntsCUDAPiS_
.size _Z11AddIntsCUDAPiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11AddIntsCUDAPiS_"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__AddIntsCUDAPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11AddIntsCUDAPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void __embedmat2d(double *a, long long *b, int nrows, int ncols, int sortdown) {
int tid = threadIdx.x + blockDim.x * (blockIdx.x + gridDim.x * blockIdx.y);
const int signbit = 0x80000000;
const int mag = 0x7fffffff;
int icol;
for (int i = tid; i < nrows*ncols; i += blockDim.x*gridDim.x*gridDim.y) {
double v = a[i];
int vi = *((int *)&v);
if (vi & signbit) {
vi = -(vi & mag);
}
icol = (i/nrows+1);
if (sortdown) icol = ncols - icol + 1;
b[i] = (long long)vi + (((long long)icol)<<32);
}
} | code for sm_80
Function : _Z12__embedmat2dPdPxiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0070*/ IMAD R3, R0, c[0x0][0x0], R5 ; /* 0x0000000000037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.AND P0, PT, R3, UR4, PT ; /* 0x0000000403007c0c */
/* 0x000fda000bf06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f05270 */
/*00b0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*00c0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*00d0*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fd000078e02ff */
/*00e0*/ @!P0 BRA 0x370 ; /* 0x0000028000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IABS R2, c[0x0][0x170] ; /* 0x00005c0000027a13 */
/* 0x000fe40000000000 */
/*0100*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fe40003f05270 */
/*0110*/ I2F.RP R6, R2 ; /* 0x0000000200067306 */
/* 0x000e220000209400 */
/*0120*/ LOP3.LUT R9, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff097a12 */
/* 0x000fce00078e33ff */
/*0130*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0140*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0150*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0160*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0170*/ IMAD.MOV R7, RZ, RZ, -R5 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a05 */
/*0180*/ IMAD R7, R7, R2, RZ ; /* 0x0000000207077224 */
/* 0x000fc800078e02ff */
/*0190*/ IMAD.HI.U32 R8, R5, R7, R4 ; /* 0x0000000705087227 */
/* 0x000fc800078e0004 */
/*01a0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x8 ; /* 0x00000008ff0a7424 */
/* 0x000fc800078e00ff */
/*01b0*/ IMAD.WIDE R4, R3, R10, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fcc00078e020a */
/*01c0*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x0000a2000c1e1900 */
/*01d0*/ IABS R7, R3 ; /* 0x0000000300077213 */
/* 0x000fe40000000000 */
/*01e0*/ IABS R14, c[0x0][0x170] ; /* 0x00005c00000e7a13 */
/* 0x000fc60000000000 */
/*01f0*/ IMAD.HI.U32 R6, R8, R7, RZ ; /* 0x0000000708067227 */
/* 0x000fc800078e00ff */
/*0200*/ IMAD.MOV R12, RZ, RZ, -R6 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0a06 */
/*0210*/ LOP3.LUT R5, R3, c[0x0][0x170], RZ, 0x3c, !PT ; /* 0x00005c0003057a12 */
/* 0x001fc600078e3cff */
/*0220*/ IMAD R7, R14, R12, R7 ; /* 0x0000000c0e077224 */
/* 0x000fe200078e0207 */
/*0230*/ ISETP.GE.AND P3, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc80003f66270 */
/*0240*/ ISETP.GT.U32.AND P2, PT, R2, R7, PT ; /* 0x000000070200720c */
/* 0x000fda0003f44070 */
/*0250*/ @!P2 IMAD.IADD R7, R7, 0x1, -R14 ; /* 0x000000010707a824 */
/* 0x000fe200078e0a0e */
/*0260*/ @!P2 IADD3 R6, R6, 0x1, RZ ; /* 0x000000010606a810 */
/* 0x000fc80007ffe0ff */
/*0270*/ ISETP.GE.U32.AND P1, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fda0003f26070 */
/*0280*/ @P1 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106061810 */
/* 0x000fca0007ffe0ff */
/*0290*/ @!P3 IMAD.MOV R6, RZ, RZ, -R6 ; /* 0x000000ffff06b224 */
/* 0x000fe200078e0a06 */
/*02a0*/ ISETP.GE.AND P2, PT, R4.reuse, RZ, PT ; /* 0x000000ff0400720c */
/* 0x044fe40003f46270 */
/*02b0*/ LOP3.LUT R5, R4, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff04057812 */
/* 0x000fd600078ec0ff */
/*02c0*/ @!P2 IMAD.MOV R4, RZ, RZ, -R5 ; /* 0x000000ffff04a224 */
/* 0x000fe200078e0a05 */
/*02d0*/ SEL R5, R9, R6, !P0 ; /* 0x0000000609057207 */
/* 0x000fc80004000000 */
/*02e0*/ IADD3 R6, P1, RZ, R4, RZ ; /* 0x00000004ff067210 */
/* 0x000fe40007f3e0ff */
/*02f0*/ IADD3 R5, -R5, c[0x0][0x174], RZ ; /* 0x00005d0005057a10 */
/* 0x000fc80007ffe1ff */
/*0300*/ LEA.HI.X.SX32 R7, R4, R5, 0x1, P1 ; /* 0x0000000504077211 */
/* 0x000fe200008f0eff */
/*0310*/ IMAD.WIDE R4, R3, R10, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e020a */
/*0320*/ IMAD R3, R0, c[0x0][0x10], R3 ; /* 0x0000040000037a24 */
/* 0x000fe200078e0203 */
/*0330*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x0001e8000c101b06 */
/*0340*/ ISETP.GE.AND P1, PT, R3, UR4, PT ; /* 0x0000000403007c0c */
/* 0x000fda000bf26270 */
/*0350*/ @!P1 BRA 0x1a0 ; /* 0xfffffe4000009947 */
/* 0x001fea000383ffff */
/*0360*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0370*/ IABS R2, c[0x0][0x170] ; /* 0x00005c0000027a13 */
/* 0x000fe40000000000 */
/*0380*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fe40003f05270 */
/*0390*/ I2F.RP R6, R2 ; /* 0x0000000200067306 */
/* 0x000e220000209400 */
/*03a0*/ LOP3.LUT R12, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff0c7a12 */
/* 0x000fce00078e33ff */
/*03b0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*03c0*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*03d0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*03e0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*03f0*/ IMAD.MOV R7, RZ, RZ, -R5 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a05 */
/*0400*/ IMAD R7, R7, R2, RZ ; /* 0x0000000207077224 */
/* 0x000fc800078e02ff */
/*0410*/ IMAD.HI.U32 R10, R5, R7, R4 ; /* 0x00000007050a7227 */
/* 0x000fc800078e0004 */
/*0420*/ IMAD.MOV.U32 R14, RZ, RZ, 0x8 ; /* 0x00000008ff0e7424 */
/* 0x000fc800078e00ff */
/*0430*/ IMAD.WIDE R4, R3, R14, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fcc00078e020e */
/*0440*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x0000a2000c1e1900 */
/*0450*/ IABS R7, R3 ; /* 0x0000000300077213 */
/* 0x000fe40000000000 */
/*0460*/ IABS R16, c[0x0][0x170] ; /* 0x00005c0000107a13 */
/* 0x000fc60000000000 */
/*0470*/ IMAD.HI.U32 R6, R10, R7, RZ ; /* 0x000000070a067227 */
/* 0x000fc800078e00ff */
/*0480*/ IMAD.MOV R8, RZ, RZ, -R6 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0a06 */
/*0490*/ LOP3.LUT R5, R3, c[0x0][0x170], RZ, 0x3c, !PT ; /* 0x00005c0003057a12 */
/* 0x001fc600078e3cff */
/*04a0*/ IMAD R7, R16, R8, R7 ; /* 0x0000000810077224 */
/* 0x000fe200078e0207 */
/*04b0*/ ISETP.GE.AND P4, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc80003f86270 */
/*04c0*/ ISETP.GT.U32.AND P3, PT, R2, R7, PT ; /* 0x000000070200720c */
/* 0x000fda0003f64070 */
/*04d0*/ @!P3 IMAD.IADD R7, R7, 0x1, -R16 ; /* 0x000000010707b824 */
/* 0x000fe200078e0a10 */
/*04e0*/ @!P3 IADD3 R6, R6, 0x1, RZ ; /* 0x000000010606b810 */
/* 0x000fc80007ffe0ff */
/*04f0*/ ISETP.GE.U32.AND P1, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fda0003f26070 */
/*0500*/ @P1 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106061810 */
/* 0x000fca0007ffe0ff */
/*0510*/ IMAD.MOV.U32 R5, RZ, RZ, R6 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0006 */
/*0520*/ @!P4 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff05c224 */
/* 0x000fca00078e0a05 */
/*0530*/ SEL R5, R12, R5, !P0 ; /* 0x000000050c057207 */
/* 0x000fe40004000000 */
/*0540*/ ISETP.GE.AND P2, PT, R4.reuse, RZ, PT ; /* 0x000000ff0400720c */
/* 0x044fe40003f46270 */
/*0550*/ LOP3.LUT R7, R4, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff04077812 */
/* 0x000fd600078ec0ff */
/*0560*/ @!P2 IMAD.MOV R4, RZ, RZ, -R7 ; /* 0x000000ffff04a224 */
/* 0x000fca00078e0a07 */
/*0570*/ SHF.R.S32.HI R8, RZ, 0x1f, R4 ; /* 0x0000001fff087819 */
/* 0x000fe40000011404 */
/*0580*/ IADD3 R6, P1, RZ, R4, RZ ; /* 0x00000004ff067210 */
/* 0x000fc80007f3e0ff */
/*0590*/ IADD3.X R7, R8, 0x1, R5, P1, !PT ; /* 0x0000000108077810 */
/* 0x000fe20000ffe405 */
/*05a0*/ IMAD.WIDE R4, R3, R14, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e020e */
/*05b0*/ IMAD R3, R0, c[0x0][0x10], R3 ; /* 0x0000040000037a24 */
/* 0x000fe200078e0203 */
/*05c0*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x0001e8000c101b06 */
/*05d0*/ ISETP.GE.AND P1, PT, R3, UR4, PT ; /* 0x0000000403007c0c */
/* 0x000fda000bf26270 */
/*05e0*/ @!P1 BRA 0x420 ; /* 0xfffffe3000009947 */
/* 0x001fea000383ffff */
/*05f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0600*/ BRA 0x600; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void __embedmat2d(double *a, long long *b, int nrows, int ncols, int sortdown) {
int tid = threadIdx.x + blockDim.x * (blockIdx.x + gridDim.x * blockIdx.y);
const int signbit = 0x80000000;
const int mag = 0x7fffffff;
int icol;
for (int i = tid; i < nrows*ncols; i += blockDim.x*gridDim.x*gridDim.y) {
double v = a[i];
int vi = *((int *)&v);
if (vi & signbit) {
vi = -(vi & mag);
}
icol = (i/nrows+1);
if (sortdown) icol = ncols - icol + 1;
b[i] = (long long)vi + (((long long)icol)<<32);
}
} | .file "tmpxft_00097d31_00000000-6___embedmat2d.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z12__embedmat2dPdPxiiiPdPxiii
.type _Z37__device_stub__Z12__embedmat2dPdPxiiiPdPxiii, @function
_Z37__device_stub__Z12__embedmat2dPdPxiiiPdPxiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12__embedmat2dPdPxiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z12__embedmat2dPdPxiiiPdPxiii, .-_Z37__device_stub__Z12__embedmat2dPdPxiiiPdPxiii
.globl _Z12__embedmat2dPdPxiii
.type _Z12__embedmat2dPdPxiii, @function
_Z12__embedmat2dPdPxiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12__embedmat2dPdPxiiiPdPxiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12__embedmat2dPdPxiii, .-_Z12__embedmat2dPdPxiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12__embedmat2dPdPxiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12__embedmat2dPdPxiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void __embedmat2d(double *a, long long *b, int nrows, int ncols, int sortdown) {
int tid = threadIdx.x + blockDim.x * (blockIdx.x + gridDim.x * blockIdx.y);
const int signbit = 0x80000000;
const int mag = 0x7fffffff;
int icol;
for (int i = tid; i < nrows*ncols; i += blockDim.x*gridDim.x*gridDim.y) {
double v = a[i];
int vi = *((int *)&v);
if (vi & signbit) {
vi = -(vi & mag);
}
icol = (i/nrows+1);
if (sortdown) icol = ncols - icol + 1;
b[i] = (long long)vi + (((long long)icol)<<32);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void __embedmat2d(double *a, long long *b, int nrows, int ncols, int sortdown) {
int tid = threadIdx.x + blockDim.x * (blockIdx.x + gridDim.x * blockIdx.y);
const int signbit = 0x80000000;
const int mag = 0x7fffffff;
int icol;
for (int i = tid; i < nrows*ncols; i += blockDim.x*gridDim.x*gridDim.y) {
double v = a[i];
int vi = *((int *)&v);
if (vi & signbit) {
vi = -(vi & mag);
}
icol = (i/nrows+1);
if (sortdown) icol = ncols - icol + 1;
b[i] = (long long)vi + (((long long)icol)<<32);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void __embedmat2d(double *a, long long *b, int nrows, int ncols, int sortdown) {
int tid = threadIdx.x + blockDim.x * (blockIdx.x + gridDim.x * blockIdx.y);
const int signbit = 0x80000000;
const int mag = 0x7fffffff;
int icol;
for (int i = tid; i < nrows*ncols; i += blockDim.x*gridDim.x*gridDim.y) {
double v = a[i];
int vi = *((int *)&v);
if (vi & signbit) {
vi = -(vi & mag);
}
icol = (i/nrows+1);
if (sortdown) icol = ncols - icol + 1;
b[i] = (long long)vi + (((long long)icol)<<32);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12__embedmat2dPdPxiii
.globl _Z12__embedmat2dPdPxiii
.p2align 8
.type _Z12__embedmat2dPdPxiii,@function
_Z12__embedmat2dPdPxiii:
s_clause 0x2
s_load_b32 s10, s[0:1], 0x20
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s7, s10, s15
s_and_b32 s11, s6, 0xffff
s_add_i32 s7, s7, s14
s_mul_i32 s8, s3, s2
v_mad_u64_u32 v[1:2], null, s7, s11, v[0:1]
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_3
s_load_b32 s6, s[0:1], 0x18
s_load_b32 s12, s[4:5], 0x4
s_mul_i32 s11, s10, s11
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s6, 0
s_mul_i32 s11, s11, s12
s_cselect_b32 vcc_lo, -1, 0
s_ashr_i32 s9, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s9
s_xor_b32 s2, s2, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v0, s2
s_sub_i32 s6, 0, s2
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s6, v0
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, s0, s4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s0, s5, v3, s0
global_load_b32 v4, v[4:5], off
v_ashrrev_i32_e32 v5, 31, v1
v_add_nc_u32_e32 v6, v1, v5
v_add_nc_u32_e32 v1, s11, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v6, v6, v5
v_xor_b32_e32 v5, s9, v5
v_mul_hi_u32 v7, v6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v8, v7, s2
v_sub_nc_u32_e32 v6, v6, v8
v_add_nc_u32_e32 v8, 1, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v9, s2, v6
v_cmp_le_u32_e64 s0, s2, v6
v_cndmask_b32_e64 v7, v7, v8, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v6, v6, v9, s0
v_add_nc_u32_e32 v8, 1, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_u32_e64 s0, s2, v6
v_cndmask_b32_e64 v6, v7, v8, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v6, v6, v5
v_sub_nc_u32_e32 v5, v6, v5
s_waitcnt vmcnt(0)
v_and_b32_e32 v7, 0x7fffffff, v4
v_cmp_lt_i32_e64 s0, -1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v6, 0, v7
v_add_nc_u32_e32 v7, 1, v5
v_sub_nc_u32_e32 v5, s3, v5
v_cndmask_b32_e64 v4, v6, v4, s0
v_cmp_le_i32_e64 s0, s8, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v5, v5, v7, vcc_lo
v_ashrrev_i32_e32 v6, 31, v4
v_add_co_u32 v4, s1, 0, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
s_or_b32 s10, s0, s10
v_add_co_ci_u32_e64 v5, s1, v5, v6, s1
v_add_co_u32 v2, s1, s6, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s1, s7, v3, s1
global_store_b64 v[2:3], v[4:5], off
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12__embedmat2dPdPxiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12__embedmat2dPdPxiii, .Lfunc_end0-_Z12__embedmat2dPdPxiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12__embedmat2dPdPxiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12__embedmat2dPdPxiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void __embedmat2d(double *a, long long *b, int nrows, int ncols, int sortdown) {
int tid = threadIdx.x + blockDim.x * (blockIdx.x + gridDim.x * blockIdx.y);
const int signbit = 0x80000000;
const int mag = 0x7fffffff;
int icol;
for (int i = tid; i < nrows*ncols; i += blockDim.x*gridDim.x*gridDim.y) {
double v = a[i];
int vi = *((int *)&v);
if (vi & signbit) {
vi = -(vi & mag);
}
icol = (i/nrows+1);
if (sortdown) icol = ncols - icol + 1;
b[i] = (long long)vi + (((long long)icol)<<32);
}
} | .text
.file "__embedmat2d.hip"
.globl _Z27__device_stub____embedmat2dPdPxiii # -- Begin function _Z27__device_stub____embedmat2dPdPxiii
.p2align 4, 0x90
.type _Z27__device_stub____embedmat2dPdPxiii,@function
_Z27__device_stub____embedmat2dPdPxiii: # @_Z27__device_stub____embedmat2dPdPxiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12__embedmat2dPdPxiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub____embedmat2dPdPxiii, .Lfunc_end0-_Z27__device_stub____embedmat2dPdPxiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12__embedmat2dPdPxiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12__embedmat2dPdPxiii,@object # @_Z12__embedmat2dPdPxiii
.section .rodata,"a",@progbits
.globl _Z12__embedmat2dPdPxiii
.p2align 3, 0x0
_Z12__embedmat2dPdPxiii:
.quad _Z27__device_stub____embedmat2dPdPxiii
.size _Z12__embedmat2dPdPxiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12__embedmat2dPdPxiii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub____embedmat2dPdPxiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12__embedmat2dPdPxiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12__embedmat2dPdPxiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0070*/ IMAD R3, R0, c[0x0][0x0], R5 ; /* 0x0000000000037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.AND P0, PT, R3, UR4, PT ; /* 0x0000000403007c0c */
/* 0x000fda000bf06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f05270 */
/*00b0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x000fe200078e00ff */
/*00c0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*00d0*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fd000078e02ff */
/*00e0*/ @!P0 BRA 0x370 ; /* 0x0000028000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IABS R2, c[0x0][0x170] ; /* 0x00005c0000027a13 */
/* 0x000fe40000000000 */
/*0100*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fe40003f05270 */
/*0110*/ I2F.RP R6, R2 ; /* 0x0000000200067306 */
/* 0x000e220000209400 */
/*0120*/ LOP3.LUT R9, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff097a12 */
/* 0x000fce00078e33ff */
/*0130*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0140*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0150*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0160*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0170*/ IMAD.MOV R7, RZ, RZ, -R5 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a05 */
/*0180*/ IMAD R7, R7, R2, RZ ; /* 0x0000000207077224 */
/* 0x000fc800078e02ff */
/*0190*/ IMAD.HI.U32 R8, R5, R7, R4 ; /* 0x0000000705087227 */
/* 0x000fc800078e0004 */
/*01a0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x8 ; /* 0x00000008ff0a7424 */
/* 0x000fc800078e00ff */
/*01b0*/ IMAD.WIDE R4, R3, R10, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fcc00078e020a */
/*01c0*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x0000a2000c1e1900 */
/*01d0*/ IABS R7, R3 ; /* 0x0000000300077213 */
/* 0x000fe40000000000 */
/*01e0*/ IABS R14, c[0x0][0x170] ; /* 0x00005c00000e7a13 */
/* 0x000fc60000000000 */
/*01f0*/ IMAD.HI.U32 R6, R8, R7, RZ ; /* 0x0000000708067227 */
/* 0x000fc800078e00ff */
/*0200*/ IMAD.MOV R12, RZ, RZ, -R6 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0a06 */
/*0210*/ LOP3.LUT R5, R3, c[0x0][0x170], RZ, 0x3c, !PT ; /* 0x00005c0003057a12 */
/* 0x001fc600078e3cff */
/*0220*/ IMAD R7, R14, R12, R7 ; /* 0x0000000c0e077224 */
/* 0x000fe200078e0207 */
/*0230*/ ISETP.GE.AND P3, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc80003f66270 */
/*0240*/ ISETP.GT.U32.AND P2, PT, R2, R7, PT ; /* 0x000000070200720c */
/* 0x000fda0003f44070 */
/*0250*/ @!P2 IMAD.IADD R7, R7, 0x1, -R14 ; /* 0x000000010707a824 */
/* 0x000fe200078e0a0e */
/*0260*/ @!P2 IADD3 R6, R6, 0x1, RZ ; /* 0x000000010606a810 */
/* 0x000fc80007ffe0ff */
/*0270*/ ISETP.GE.U32.AND P1, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fda0003f26070 */
/*0280*/ @P1 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106061810 */
/* 0x000fca0007ffe0ff */
/*0290*/ @!P3 IMAD.MOV R6, RZ, RZ, -R6 ; /* 0x000000ffff06b224 */
/* 0x000fe200078e0a06 */
/*02a0*/ ISETP.GE.AND P2, PT, R4.reuse, RZ, PT ; /* 0x000000ff0400720c */
/* 0x044fe40003f46270 */
/*02b0*/ LOP3.LUT R5, R4, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff04057812 */
/* 0x000fd600078ec0ff */
/*02c0*/ @!P2 IMAD.MOV R4, RZ, RZ, -R5 ; /* 0x000000ffff04a224 */
/* 0x000fe200078e0a05 */
/*02d0*/ SEL R5, R9, R6, !P0 ; /* 0x0000000609057207 */
/* 0x000fc80004000000 */
/*02e0*/ IADD3 R6, P1, RZ, R4, RZ ; /* 0x00000004ff067210 */
/* 0x000fe40007f3e0ff */
/*02f0*/ IADD3 R5, -R5, c[0x0][0x174], RZ ; /* 0x00005d0005057a10 */
/* 0x000fc80007ffe1ff */
/*0300*/ LEA.HI.X.SX32 R7, R4, R5, 0x1, P1 ; /* 0x0000000504077211 */
/* 0x000fe200008f0eff */
/*0310*/ IMAD.WIDE R4, R3, R10, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e020a */
/*0320*/ IMAD R3, R0, c[0x0][0x10], R3 ; /* 0x0000040000037a24 */
/* 0x000fe200078e0203 */
/*0330*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x0001e8000c101b06 */
/*0340*/ ISETP.GE.AND P1, PT, R3, UR4, PT ; /* 0x0000000403007c0c */
/* 0x000fda000bf26270 */
/*0350*/ @!P1 BRA 0x1a0 ; /* 0xfffffe4000009947 */
/* 0x001fea000383ffff */
/*0360*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0370*/ IABS R2, c[0x0][0x170] ; /* 0x00005c0000027a13 */
/* 0x000fe40000000000 */
/*0380*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fe40003f05270 */
/*0390*/ I2F.RP R6, R2 ; /* 0x0000000200067306 */
/* 0x000e220000209400 */
/*03a0*/ LOP3.LUT R12, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff0c7a12 */
/* 0x000fce00078e33ff */
/*03b0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*03c0*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*03d0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*03e0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*03f0*/ IMAD.MOV R7, RZ, RZ, -R5 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a05 */
/*0400*/ IMAD R7, R7, R2, RZ ; /* 0x0000000207077224 */
/* 0x000fc800078e02ff */
/*0410*/ IMAD.HI.U32 R10, R5, R7, R4 ; /* 0x00000007050a7227 */
/* 0x000fc800078e0004 */
/*0420*/ IMAD.MOV.U32 R14, RZ, RZ, 0x8 ; /* 0x00000008ff0e7424 */
/* 0x000fc800078e00ff */
/*0430*/ IMAD.WIDE R4, R3, R14, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fcc00078e020e */
/*0440*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x0000a2000c1e1900 */
/*0450*/ IABS R7, R3 ; /* 0x0000000300077213 */
/* 0x000fe40000000000 */
/*0460*/ IABS R16, c[0x0][0x170] ; /* 0x00005c0000107a13 */
/* 0x000fc60000000000 */
/*0470*/ IMAD.HI.U32 R6, R10, R7, RZ ; /* 0x000000070a067227 */
/* 0x000fc800078e00ff */
/*0480*/ IMAD.MOV R8, RZ, RZ, -R6 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0a06 */
/*0490*/ LOP3.LUT R5, R3, c[0x0][0x170], RZ, 0x3c, !PT ; /* 0x00005c0003057a12 */
/* 0x001fc600078e3cff */
/*04a0*/ IMAD R7, R16, R8, R7 ; /* 0x0000000810077224 */
/* 0x000fe200078e0207 */
/*04b0*/ ISETP.GE.AND P4, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc80003f86270 */
/*04c0*/ ISETP.GT.U32.AND P3, PT, R2, R7, PT ; /* 0x000000070200720c */
/* 0x000fda0003f64070 */
/*04d0*/ @!P3 IMAD.IADD R7, R7, 0x1, -R16 ; /* 0x000000010707b824 */
/* 0x000fe200078e0a10 */
/*04e0*/ @!P3 IADD3 R6, R6, 0x1, RZ ; /* 0x000000010606b810 */
/* 0x000fc80007ffe0ff */
/*04f0*/ ISETP.GE.U32.AND P1, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fda0003f26070 */
/*0500*/ @P1 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106061810 */
/* 0x000fca0007ffe0ff */
/*0510*/ IMAD.MOV.U32 R5, RZ, RZ, R6 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0006 */
/*0520*/ @!P4 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff05c224 */
/* 0x000fca00078e0a05 */
/*0530*/ SEL R5, R12, R5, !P0 ; /* 0x000000050c057207 */
/* 0x000fe40004000000 */
/*0540*/ ISETP.GE.AND P2, PT, R4.reuse, RZ, PT ; /* 0x000000ff0400720c */
/* 0x044fe40003f46270 */
/*0550*/ LOP3.LUT R7, R4, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff04077812 */
/* 0x000fd600078ec0ff */
/*0560*/ @!P2 IMAD.MOV R4, RZ, RZ, -R7 ; /* 0x000000ffff04a224 */
/* 0x000fca00078e0a07 */
/*0570*/ SHF.R.S32.HI R8, RZ, 0x1f, R4 ; /* 0x0000001fff087819 */
/* 0x000fe40000011404 */
/*0580*/ IADD3 R6, P1, RZ, R4, RZ ; /* 0x00000004ff067210 */
/* 0x000fc80007f3e0ff */
/*0590*/ IADD3.X R7, R8, 0x1, R5, P1, !PT ; /* 0x0000000108077810 */
/* 0x000fe20000ffe405 */
/*05a0*/ IMAD.WIDE R4, R3, R14, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e020e */
/*05b0*/ IMAD R3, R0, c[0x0][0x10], R3 ; /* 0x0000040000037a24 */
/* 0x000fe200078e0203 */
/*05c0*/ STG.E.64 [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x0001e8000c101b06 */
/*05d0*/ ISETP.GE.AND P1, PT, R3, UR4, PT ; /* 0x0000000403007c0c */
/* 0x000fda000bf26270 */
/*05e0*/ @!P1 BRA 0x420 ; /* 0xfffffe3000009947 */
/* 0x001fea000383ffff */
/*05f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0600*/ BRA 0x600; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12__embedmat2dPdPxiii
.globl _Z12__embedmat2dPdPxiii
.p2align 8
.type _Z12__embedmat2dPdPxiii,@function
_Z12__embedmat2dPdPxiii:
s_clause 0x2
s_load_b32 s10, s[0:1], 0x20
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_add_u32 s4, s0, 32
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s7, s10, s15
s_and_b32 s11, s6, 0xffff
s_add_i32 s7, s7, s14
s_mul_i32 s8, s3, s2
v_mad_u64_u32 v[1:2], null, s7, s11, v[0:1]
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_3
s_load_b32 s6, s[0:1], 0x18
s_load_b32 s12, s[4:5], 0x4
s_mul_i32 s11, s10, s11
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s6, 0
s_mul_i32 s11, s11, s12
s_cselect_b32 vcc_lo, -1, 0
s_ashr_i32 s9, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s9
s_xor_b32 s2, s2, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v0, s2
s_sub_i32 s6, 0, s2
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s6, v0
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v2
v_add_nc_u32_e32 v0, v0, v2
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, s0, s4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s0, s5, v3, s0
global_load_b32 v4, v[4:5], off
v_ashrrev_i32_e32 v5, 31, v1
v_add_nc_u32_e32 v6, v1, v5
v_add_nc_u32_e32 v1, s11, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v6, v6, v5
v_xor_b32_e32 v5, s9, v5
v_mul_hi_u32 v7, v6, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v8, v7, s2
v_sub_nc_u32_e32 v6, v6, v8
v_add_nc_u32_e32 v8, 1, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v9, s2, v6
v_cmp_le_u32_e64 s0, s2, v6
v_cndmask_b32_e64 v7, v7, v8, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v6, v6, v9, s0
v_add_nc_u32_e32 v8, 1, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_u32_e64 s0, s2, v6
v_cndmask_b32_e64 v6, v7, v8, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v6, v6, v5
v_sub_nc_u32_e32 v5, v6, v5
s_waitcnt vmcnt(0)
v_and_b32_e32 v7, 0x7fffffff, v4
v_cmp_lt_i32_e64 s0, -1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v6, 0, v7
v_add_nc_u32_e32 v7, 1, v5
v_sub_nc_u32_e32 v5, s3, v5
v_cndmask_b32_e64 v4, v6, v4, s0
v_cmp_le_i32_e64 s0, s8, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v5, v5, v7, vcc_lo
v_ashrrev_i32_e32 v6, 31, v4
v_add_co_u32 v4, s1, 0, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
s_or_b32 s10, s0, s10
v_add_co_ci_u32_e64 v5, s1, v5, v6, s1
v_add_co_u32 v2, s1, s6, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s1, s7, v3, s1
global_store_b64 v[2:3], v[4:5], off
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12__embedmat2dPdPxiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12__embedmat2dPdPxiii, .Lfunc_end0-_Z12__embedmat2dPdPxiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12__embedmat2dPdPxiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12__embedmat2dPdPxiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00097d31_00000000-6___embedmat2d.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z12__embedmat2dPdPxiiiPdPxiii
.type _Z37__device_stub__Z12__embedmat2dPdPxiiiPdPxiii, @function
_Z37__device_stub__Z12__embedmat2dPdPxiiiPdPxiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12__embedmat2dPdPxiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z12__embedmat2dPdPxiiiPdPxiii, .-_Z37__device_stub__Z12__embedmat2dPdPxiiiPdPxiii
.globl _Z12__embedmat2dPdPxiii
.type _Z12__embedmat2dPdPxiii, @function
_Z12__embedmat2dPdPxiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12__embedmat2dPdPxiiiPdPxiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12__embedmat2dPdPxiii, .-_Z12__embedmat2dPdPxiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12__embedmat2dPdPxiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12__embedmat2dPdPxiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "__embedmat2d.hip"
.globl _Z27__device_stub____embedmat2dPdPxiii # -- Begin function _Z27__device_stub____embedmat2dPdPxiii
.p2align 4, 0x90
.type _Z27__device_stub____embedmat2dPdPxiii,@function
_Z27__device_stub____embedmat2dPdPxiii: # @_Z27__device_stub____embedmat2dPdPxiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12__embedmat2dPdPxiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub____embedmat2dPdPxiii, .Lfunc_end0-_Z27__device_stub____embedmat2dPdPxiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12__embedmat2dPdPxiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12__embedmat2dPdPxiii,@object # @_Z12__embedmat2dPdPxiii
.section .rodata,"a",@progbits
.globl _Z12__embedmat2dPdPxiii
.p2align 3, 0x0
_Z12__embedmat2dPdPxiii:
.quad _Z27__device_stub____embedmat2dPdPxiii
.size _Z12__embedmat2dPdPxiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12__embedmat2dPdPxiii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub____embedmat2dPdPxiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12__embedmat2dPdPxiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void square(float *d_out,float *d_in)
{
int idx = threadIdx.x;
float f = d_in[idx];
d_out[idx] = f * f *f;
}
int main(int argc, char **argv)
{
const int ARRAY_SIZE = 96;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
float h_in[ARRAY_SIZE];
for(int i = 0; i < ARRAY_SIZE; ++i)
{
h_in[i] = float(i);
}
float h_out[ARRAY_SIZE];
//declare GPU memory pointers
float *d_in;
float *d_out;
//allocate GPU memory
cudaMalloc((void **) &d_in, ARRAY_BYTES);
cudaMalloc((void **) &d_out, ARRAY_BYTES);
//cuda memcpy to GPU
cudaMemcpy(d_in,h_in,ARRAY_BYTES,cudaMemcpyHostToDevice);
//kernel launch
square<<<1,ARRAY_SIZE>>> (d_out,d_in);
cudaMemcpy(h_out,d_out,ARRAY_BYTES,cudaMemcpyDeviceToHost);
for(int i =0 ; i < ARRAY_SIZE; ++i)
{
printf("%.2f \n",h_out[i]);
}
cudaFree(d_in);
cudaFree(d_out);
} | code for sm_80
Function : _Z6squarePfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x001fcc00078e0205 */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0205 */
/*0070*/ FMUL R7, R2, R2 ; /* 0x0000000202077220 */
/* 0x004fc80000400000 */
/*0080*/ FMUL R7, R2, R7 ; /* 0x0000000702077220 */
/* 0x000fca0000400000 */
/*0090*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void square(float *d_out,float *d_in)
{
int idx = threadIdx.x;
float f = d_in[idx];
d_out[idx] = f * f *f;
}
int main(int argc, char **argv)
{
const int ARRAY_SIZE = 96;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
float h_in[ARRAY_SIZE];
for(int i = 0; i < ARRAY_SIZE; ++i)
{
h_in[i] = float(i);
}
float h_out[ARRAY_SIZE];
//declare GPU memory pointers
float *d_in;
float *d_out;
//allocate GPU memory
cudaMalloc((void **) &d_in, ARRAY_BYTES);
cudaMalloc((void **) &d_out, ARRAY_BYTES);
//cuda memcpy to GPU
cudaMemcpy(d_in,h_in,ARRAY_BYTES,cudaMemcpyHostToDevice);
//kernel launch
square<<<1,ARRAY_SIZE>>> (d_out,d_in);
cudaMemcpy(h_out,d_out,ARRAY_BYTES,cudaMemcpyDeviceToHost);
for(int i =0 ; i < ARRAY_SIZE; ++i)
{
printf("%.2f \n",h_out[i]);
}
cudaFree(d_in);
cudaFree(d_out);
} | .file "tmpxft_0010c244_00000000-6_gpu_pract.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6squarePfS_PfS_
.type _Z27__device_stub__Z6squarePfS_PfS_, @function
_Z27__device_stub__Z6squarePfS_PfS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6squarePfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z6squarePfS_PfS_, .-_Z27__device_stub__Z6squarePfS_PfS_
.globl _Z6squarePfS_
.type _Z6squarePfS_, @function
_Z6squarePfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6squarePfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6squarePfS_, .-_Z6squarePfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%.2f \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $832, %rsp
.cfi_def_cfa_offset 864
movq %fs:40, %rax
movq %rax, 824(%rsp)
xorl %eax, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 48(%rsp,%rax,4)
addq $1, %rax
cmpq $96, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $384, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $384, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $384, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $96, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 432(%rsp), %rbx
movl $2, %ecx
movl $384, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 816(%rsp), %r12
leaq .LC0(%rip), %rbp
.L14:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L14
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 824(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $832, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z27__device_stub__Z6squarePfS_PfS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6squarePfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6squarePfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void square(float *d_out,float *d_in)
{
int idx = threadIdx.x;
float f = d_in[idx];
d_out[idx] = f * f *f;
}
int main(int argc, char **argv)
{
const int ARRAY_SIZE = 96;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
float h_in[ARRAY_SIZE];
for(int i = 0; i < ARRAY_SIZE; ++i)
{
h_in[i] = float(i);
}
float h_out[ARRAY_SIZE];
//declare GPU memory pointers
float *d_in;
float *d_out;
//allocate GPU memory
cudaMalloc((void **) &d_in, ARRAY_BYTES);
cudaMalloc((void **) &d_out, ARRAY_BYTES);
//cuda memcpy to GPU
cudaMemcpy(d_in,h_in,ARRAY_BYTES,cudaMemcpyHostToDevice);
//kernel launch
square<<<1,ARRAY_SIZE>>> (d_out,d_in);
cudaMemcpy(h_out,d_out,ARRAY_BYTES,cudaMemcpyDeviceToHost);
for(int i =0 ; i < ARRAY_SIZE; ++i)
{
printf("%.2f \n",h_out[i]);
}
cudaFree(d_in);
cudaFree(d_out);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void square(float *d_out,float *d_in)
{
int idx = threadIdx.x;
float f = d_in[idx];
d_out[idx] = f * f *f;
}
int main(int argc, char **argv)
{
const int ARRAY_SIZE = 96;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
float h_in[ARRAY_SIZE];
for(int i = 0; i < ARRAY_SIZE; ++i)
{
h_in[i] = float(i);
}
float h_out[ARRAY_SIZE];
//declare GPU memory pointers
float *d_in;
float *d_out;
//allocate GPU memory
hipMalloc((void **) &d_in, ARRAY_BYTES);
hipMalloc((void **) &d_out, ARRAY_BYTES);
//cuda memcpy to GPU
hipMemcpy(d_in,h_in,ARRAY_BYTES,hipMemcpyHostToDevice);
//kernel launch
square<<<1,ARRAY_SIZE>>> (d_out,d_in);
hipMemcpy(h_out,d_out,ARRAY_BYTES,hipMemcpyDeviceToHost);
for(int i =0 ; i < ARRAY_SIZE; ++i)
{
printf("%.2f \n",h_out[i]);
}
hipFree(d_in);
hipFree(d_out);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void square(float *d_out,float *d_in)
{
int idx = threadIdx.x;
float f = d_in[idx];
d_out[idx] = f * f *f;
}
int main(int argc, char **argv)
{
const int ARRAY_SIZE = 96;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
float h_in[ARRAY_SIZE];
for(int i = 0; i < ARRAY_SIZE; ++i)
{
h_in[i] = float(i);
}
float h_out[ARRAY_SIZE];
//declare GPU memory pointers
float *d_in;
float *d_out;
//allocate GPU memory
hipMalloc((void **) &d_in, ARRAY_BYTES);
hipMalloc((void **) &d_out, ARRAY_BYTES);
//cuda memcpy to GPU
hipMemcpy(d_in,h_in,ARRAY_BYTES,hipMemcpyHostToDevice);
//kernel launch
square<<<1,ARRAY_SIZE>>> (d_out,d_in);
hipMemcpy(h_out,d_out,ARRAY_BYTES,hipMemcpyDeviceToHost);
for(int i =0 ; i < ARRAY_SIZE; ++i)
{
printf("%.2f \n",h_out[i]);
}
hipFree(d_in);
hipFree(d_out);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6squarePfS_
.globl _Z6squarePfS_
.p2align 8
.type _Z6squarePfS_,@function
_Z6squarePfS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[2:3]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v1, v1
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6squarePfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6squarePfS_, .Lfunc_end0-_Z6squarePfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6squarePfS_
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z6squarePfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void square(float *d_out,float *d_in)
{
int idx = threadIdx.x;
float f = d_in[idx];
d_out[idx] = f * f *f;
}
int main(int argc, char **argv)
{
const int ARRAY_SIZE = 96;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(float);
float h_in[ARRAY_SIZE];
for(int i = 0; i < ARRAY_SIZE; ++i)
{
h_in[i] = float(i);
}
float h_out[ARRAY_SIZE];
//declare GPU memory pointers
float *d_in;
float *d_out;
//allocate GPU memory
hipMalloc((void **) &d_in, ARRAY_BYTES);
hipMalloc((void **) &d_out, ARRAY_BYTES);
//cuda memcpy to GPU
hipMemcpy(d_in,h_in,ARRAY_BYTES,hipMemcpyHostToDevice);
//kernel launch
square<<<1,ARRAY_SIZE>>> (d_out,d_in);
hipMemcpy(h_out,d_out,ARRAY_BYTES,hipMemcpyDeviceToHost);
for(int i =0 ; i < ARRAY_SIZE; ++i)
{
printf("%.2f \n",h_out[i]);
}
hipFree(d_in);
hipFree(d_out);
} | .text
.file "gpu_pract.hip"
.globl _Z21__device_stub__squarePfS_ # -- Begin function _Z21__device_stub__squarePfS_
.p2align 4, 0x90
.type _Z21__device_stub__squarePfS_,@function
_Z21__device_stub__squarePfS_: # @_Z21__device_stub__squarePfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6squarePfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__squarePfS_, .Lfunc_end0-_Z21__device_stub__squarePfS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $848, %rsp # imm = 0x350
.cfi_def_cfa_offset 864
.cfi_offset %rbx, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, 464(%rsp,%rax,4)
incq %rax
cmpq $96, %rax
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $384, %esi # imm = 0x180
callq hipMalloc
movq %rsp, %rdi
movl $384, %esi # imm = 0x180
callq hipMalloc
movq 8(%rsp), %rdi
leaq 464(%rsp), %rsi
movl $384, %edx # imm = 0x180
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 95(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6squarePfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 80(%rsp), %rdi
movl $384, %edx # imm = 0x180
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss 80(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %rbx
cmpq $96, %rbx
jne .LBB1_5
# %bb.6:
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $848, %rsp # imm = 0x350
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6squarePfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6squarePfS_,@object # @_Z6squarePfS_
.section .rodata,"a",@progbits
.globl _Z6squarePfS_
.p2align 3, 0x0
_Z6squarePfS_:
.quad _Z21__device_stub__squarePfS_
.size _Z6squarePfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%.2f \n"
.size .L.str, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6squarePfS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__squarePfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6squarePfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6squarePfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x001fcc00078e0205 */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0205 */
/*0070*/ FMUL R7, R2, R2 ; /* 0x0000000202077220 */
/* 0x004fc80000400000 */
/*0080*/ FMUL R7, R2, R7 ; /* 0x0000000702077220 */
/* 0x000fca0000400000 */
/*0090*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6squarePfS_
.globl _Z6squarePfS_
.p2align 8
.type _Z6squarePfS_,@function
_Z6squarePfS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[2:3]
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v1, v1
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6squarePfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6squarePfS_, .Lfunc_end0-_Z6squarePfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6squarePfS_
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z6squarePfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010c244_00000000-6_gpu_pract.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z6squarePfS_PfS_
.type _Z27__device_stub__Z6squarePfS_PfS_, @function
_Z27__device_stub__Z6squarePfS_PfS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6squarePfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z6squarePfS_PfS_, .-_Z27__device_stub__Z6squarePfS_PfS_
.globl _Z6squarePfS_
.type _Z6squarePfS_, @function
_Z6squarePfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6squarePfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6squarePfS_, .-_Z6squarePfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%.2f \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $832, %rsp
.cfi_def_cfa_offset 864
movq %fs:40, %rax
movq %rax, 824(%rsp)
xorl %eax, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 48(%rsp,%rax,4)
addq $1, %rax
cmpq $96, %rax
jne .L12
leaq 8(%rsp), %rdi
movl $384, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $384, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $384, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $96, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 432(%rsp), %rbx
movl $2, %ecx
movl $384, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 816(%rsp), %r12
leaq .LC0(%rip), %rbp
.L14:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L14
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 824(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $832, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z27__device_stub__Z6squarePfS_PfS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6squarePfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6squarePfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpu_pract.hip"
.globl _Z21__device_stub__squarePfS_ # -- Begin function _Z21__device_stub__squarePfS_
.p2align 4, 0x90
.type _Z21__device_stub__squarePfS_,@function
_Z21__device_stub__squarePfS_: # @_Z21__device_stub__squarePfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6squarePfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__squarePfS_, .Lfunc_end0-_Z21__device_stub__squarePfS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $848, %rsp # imm = 0x350
.cfi_def_cfa_offset 864
.cfi_offset %rbx, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, 464(%rsp,%rax,4)
incq %rax
cmpq $96, %rax
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $384, %esi # imm = 0x180
callq hipMalloc
movq %rsp, %rdi
movl $384, %esi # imm = 0x180
callq hipMalloc
movq 8(%rsp), %rdi
leaq 464(%rsp), %rsi
movl $384, %edx # imm = 0x180
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 95(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6squarePfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 80(%rsp), %rdi
movl $384, %edx # imm = 0x180
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss 80(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %rbx
cmpq $96, %rbx
jne .LBB1_5
# %bb.6:
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $848, %rsp # imm = 0x350
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6squarePfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6squarePfS_,@object # @_Z6squarePfS_
.section .rodata,"a",@progbits
.globl _Z6squarePfS_
.p2align 3, 0x0
_Z6squarePfS_:
.quad _Z21__device_stub__squarePfS_
.size _Z6squarePfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%.2f \n"
.size .L.str, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6squarePfS_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__squarePfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6squarePfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kernel_test5_init(char* _ptr, char* end_ptr)
{
unsigned int i;
unsigned int* ptr = (unsigned int*) (_ptr + blockIdx.x*BLOCKSIZE);
if (ptr >= (unsigned int*) end_ptr) {
return;
}
unsigned int p1 = 1;
for (i = 0;i < BLOCKSIZE/sizeof(unsigned int); i+=16){
unsigned int p2 = ~p1;
ptr[i] = p1;
ptr[i+1] = p1;
ptr[i+2] = p2;
ptr[i+3] = p2;
ptr[i+4] = p1;
ptr[i+5] = p1;
ptr[i+6] = p2;
ptr[i+7] = p2;
ptr[i+8] = p1;
ptr[i+9] = p1;
ptr[i+10] = p2;
ptr[i+11] = p2;
ptr[i+12] = p1;
ptr[i+13] = p1;
ptr[i+14] = p2;
ptr[i+15] = p2;
p1 = p1<<1;
if (p1 == 0){
p1 = 1;
}
}
return;
} | code for sm_80
Function : _Z17kernel_test5_initPcS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e240000002500 */
/*0020*/ LEA R0, P1, R0, c[0x0][0x160], 0x14 ; /* 0x0000580000007a11 */
/* 0x001fc8000782a0ff */
/*0030*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe20003f06070 */
/*0040*/ IMAD.X R9, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff097624 */
/* 0x000fca00008e06ff */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, R9, c[0x0][0x16c], PT, P0 ; /* 0x00005b0009007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IADD3 R4, P0, R0, 0x40, RZ ; /* 0x0000004000047810 */
/* 0x000fe20007f1e0ff */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD.X R9, RZ, RZ, R9, P0 ; /* 0x000000ffff097224 */
/* 0x000fe400000e0609 */
/*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x002fe200078e0004 */
/*00d0*/ LOP3.LUT R7, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff077212 */
/* 0x000fe200078e33ff */
/*00e0*/ IMAD.SHL.U32 R4, R5, 0x2, RZ ; /* 0x0000000205047824 */
/* 0x000fe200078e00ff */
/*00f0*/ IADD3 R0, R0, 0x80, RZ ; /* 0x0000008000007810 */
/* 0x000fe20007ffe0ff */
/*0100*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fc600078e0009 */
/*0110*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*0120*/ STG.E [R2.64+-0x38], R7 ; /* 0xffffc80702007986 */
/* 0x000fe2000c101904 */
/*0130*/ ISETP.GE.U32.AND P1, PT, R0, 0x40000, PT ; /* 0x000400000000780c */
/* 0x000fe40003f26070 */
/*0140*/ SEL R9, R4, 0x1, P0 ; /* 0x0000000104097807 */
/* 0x000fe20000000000 */
/*0150*/ STG.E [R2.64+-0x34], R7 ; /* 0xffffcc0702007986 */
/* 0x000fe8000c101904 */
/*0160*/ IMAD.SHL.U32 R4, R9, 0x2, RZ ; /* 0x0000000209047824 */
/* 0x000fe200078e00ff */
/*0170*/ STG.E [R2.64+-0x28], R7 ; /* 0xffffd80702007986 */
/* 0x000fe8000c101904 */
/*0180*/ ISETP.NE.AND P0, PT, R4.reuse, RZ, PT ; /* 0x000000ff0400720c */
/* 0x040fe20003f05270 */
/*0190*/ STG.E [R2.64+-0x24], R7 ; /* 0xffffdc0702007986 */
/* 0x000fe8000c101904 */
/*01a0*/ STG.E [R2.64+-0x18], R7 ; /* 0xffffe80702007986 */
/* 0x000fe8000c101904 */
/*01b0*/ STG.E [R2.64+-0x14], R7 ; /* 0xffffec0702007986 */
/* 0x000fe8000c101904 */
/*01c0*/ STG.E [R2.64+-0x8], R7 ; /* 0xfffff80702007986 */
/* 0x000fe8000c101904 */
/*01d0*/ STG.E [R2.64+-0x4], R7 ; /* 0xfffffc0702007986 */
/* 0x0001e8000c101904 */
/*01e0*/ STG.E [R2.64+-0x40], R5 ; /* 0xffffc00502007986 */
/* 0x000fe8000c101904 */
/*01f0*/ STG.E [R2.64+-0x3c], R5 ; /* 0xffffc40502007986 */
/* 0x000fe2000c101904 */
/*0200*/ SEL R7, R4, 0x1, P0 ; /* 0x0000000104077807 */
/* 0x001fc60000000000 */
/*0210*/ STG.E [R2.64+-0x30], R5 ; /* 0xffffd00502007986 */
/* 0x000fe4000c101904 */
/*0220*/ IMAD.SHL.U32 R4, R7, 0x2, RZ ; /* 0x0000000207047824 */
/* 0x000fe400078e00ff */
/*0230*/ STG.E [R2.64+-0x2c], R5 ; /* 0xffffd40502007986 */
/* 0x000fe8000c101904 */
/*0240*/ STG.E [R2.64+-0x20], R5 ; /* 0xffffe00502007986 */
/* 0x000fe2000c101904 */
/*0250*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0260*/ STG.E [R2.64+-0x1c], R5 ; /* 0xffffe40502007986 */
/* 0x000fe8000c101904 */
/*0270*/ STG.E [R2.64+-0x10], R5 ; /* 0xfffff00502007986 */
/* 0x000fe8000c101904 */
/*0280*/ STG.E [R2.64+-0xc], R5 ; /* 0xfffff40502007986 */
/* 0x0001e8000c101904 */
/*0290*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*02a0*/ STG.E [R2.64+0x4], R9 ; /* 0x0000040902007986 */
/* 0x000fe2000c101904 */
/*02b0*/ LOP3.LUT R5, RZ, R9, RZ, 0x33, !PT ; /* 0x00000009ff057212 */
/* 0x001fc600078e33ff */
/*02c0*/ STG.E [R2.64+0x10], R9 ; /* 0x0000100902007986 */
/* 0x000fe8000c101904 */
/*02d0*/ STG.E [R2.64+0x8], R5 ; /* 0x0000080502007986 */
/* 0x000fe8000c101904 */
/*02e0*/ STG.E [R2.64+0xc], R5 ; /* 0x00000c0502007986 */
/* 0x000fe8000c101904 */
/*02f0*/ STG.E [R2.64+0x18], R5 ; /* 0x0000180502007986 */
/* 0x000fe8000c101904 */
/*0300*/ STG.E [R2.64+0x1c], R5 ; /* 0x00001c0502007986 */
/* 0x000fe8000c101904 */
/*0310*/ STG.E [R2.64+0x28], R5 ; /* 0x0000280502007986 */
/* 0x000fe8000c101904 */
/*0320*/ STG.E [R2.64+0x2c], R5 ; /* 0x00002c0502007986 */
/* 0x000fe8000c101904 */
/*0330*/ STG.E [R2.64+0x38], R5 ; /* 0x0000380502007986 */
/* 0x000fe8000c101904 */
/*0340*/ STG.E [R2.64+0x3c], R5 ; /* 0x00003c0502007986 */
/* 0x0001e8000c101904 */
/*0350*/ STG.E [R2.64+0x14], R9 ; /* 0x0000140902007986 */
/* 0x000fe8000c101904 */
/*0360*/ STG.E [R2.64+0x20], R9 ; /* 0x0000200902007986 */
/* 0x000fe2000c101904 */
/*0370*/ SEL R5, R4, 0x1, P0 ; /* 0x0000000104057807 */
/* 0x001fc60000000000 */
/*0380*/ STG.E [R2.64+0x24], R9 ; /* 0x0000240902007986 */
/* 0x000fe4000c101904 */
/*0390*/ IMAD.SHL.U32 R4, R5, 0x2, RZ ; /* 0x0000000205047824 */
/* 0x000fe400078e00ff */
/*03a0*/ STG.E [R2.64+0x30], R9 ; /* 0x0000300902007986 */
/* 0x000fe8000c101904 */
/*03b0*/ STG.E [R2.64+0x34], R9 ; /* 0x0000340902007986 */
/* 0x0001e2000c101904 */
/*03c0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*03d0*/ STG.E [R2.64+0x40], R7 ; /* 0x0000400702007986 */
/* 0x000fe8000c101904 */
/*03e0*/ STG.E [R2.64+0x44], R7 ; /* 0x0000440702007986 */
/* 0x000fe2000c101904 */
/*03f0*/ LOP3.LUT R9, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff097212 */
/* 0x001fc600078e33ff */
/*0400*/ STG.E [R2.64+0x50], R7 ; /* 0x0000500702007986 */
/* 0x000fe8000c101904 */
/*0410*/ STG.E [R2.64+0x48], R9 ; /* 0x0000480902007986 */
/* 0x000fe8000c101904 */
/*0420*/ STG.E [R2.64+0x4c], R9 ; /* 0x00004c0902007986 */
/* 0x000fe8000c101904 */
/*0430*/ STG.E [R2.64+0x58], R9 ; /* 0x0000580902007986 */
/* 0x000fe8000c101904 */
/*0440*/ STG.E [R2.64+0x5c], R9 ; /* 0x00005c0902007986 */
/* 0x000fe8000c101904 */
/*0450*/ STG.E [R2.64+0x68], R9 ; /* 0x0000680902007986 */
/* 0x000fe8000c101904 */
/*0460*/ STG.E [R2.64+0x6c], R9 ; /* 0x00006c0902007986 */
/* 0x000fe8000c101904 */
/*0470*/ STG.E [R2.64+0x78], R9 ; /* 0x0000780902007986 */
/* 0x000fe8000c101904 */
/*0480*/ STG.E [R2.64+0x7c], R9 ; /* 0x00007c0902007986 */
/* 0x0001e8000c101904 */
/*0490*/ STG.E [R2.64+0x54], R7 ; /* 0x0000540702007986 */
/* 0x000fe8000c101904 */
/*04a0*/ STG.E [R2.64+0x60], R7 ; /* 0x0000600702007986 */
/* 0x000fe2000c101904 */
/*04b0*/ SEL R9, R4, 0x1, P0 ; /* 0x0000000104097807 */
/* 0x001fc60000000000 */
/*04c0*/ STG.E [R2.64+0x64], R7 ; /* 0x0000640702007986 */
/* 0x000fe4000c101904 */
/*04d0*/ IMAD.SHL.U32 R4, R9, 0x2, RZ ; /* 0x0000000209047824 */
/* 0x000fe400078e00ff */
/*04e0*/ STG.E [R2.64+0x70], R7 ; /* 0x0000700702007986 */
/* 0x000fe8000c101904 */
/*04f0*/ STG.E [R2.64+0x74], R7 ; /* 0x0000740702007986 */
/* 0x0001e2000c101904 */
/*0500*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0510*/ STG.E [R2.64+0x80], R5 ; /* 0x0000800502007986 */
/* 0x000fe8000c101904 */
/*0520*/ STG.E [R2.64+0x84], R5 ; /* 0x0000840502007986 */
/* 0x000fe2000c101904 */
/*0530*/ LOP3.LUT R7, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff077212 */
/* 0x001fc600078e33ff */
/*0540*/ STG.E [R2.64+0x90], R5 ; /* 0x0000900502007986 */
/* 0x000fe8000c101904 */
/*0550*/ STG.E [R2.64+0x88], R7 ; /* 0x0000880702007986 */
/* 0x000fe8000c101904 */
/*0560*/ STG.E [R2.64+0x8c], R7 ; /* 0x00008c0702007986 */
/* 0x000fe8000c101904 */
/*0570*/ STG.E [R2.64+0x98], R7 ; /* 0x0000980702007986 */
/* 0x000fe8000c101904 */
/*0580*/ STG.E [R2.64+0x9c], R7 ; /* 0x00009c0702007986 */
/* 0x000fe8000c101904 */
/*0590*/ STG.E [R2.64+0xa8], R7 ; /* 0x0000a80702007986 */
/* 0x000fe8000c101904 */
/*05a0*/ STG.E [R2.64+0xac], R7 ; /* 0x0000ac0702007986 */
/* 0x000fe8000c101904 */
/*05b0*/ STG.E [R2.64+0xb8], R7 ; /* 0x0000b80702007986 */
/* 0x000fe8000c101904 */
/*05c0*/ STG.E [R2.64+0xbc], R7 ; /* 0x0000bc0702007986 */
/* 0x0001e8000c101904 */
/*05d0*/ STG.E [R2.64+0x94], R5 ; /* 0x0000940502007986 */
/* 0x000fe8000c101904 */
/*05e0*/ STG.E [R2.64+0xa0], R5 ; /* 0x0000a00502007986 */
/* 0x000fe2000c101904 */
/*05f0*/ SEL R7, R4, 0x1, P0 ; /* 0x0000000104077807 */
/* 0x001fc60000000000 */
/*0600*/ STG.E [R2.64+0xa4], R5 ; /* 0x0000a40502007986 */
/* 0x000fe4000c101904 */
/*0610*/ IMAD.SHL.U32 R4, R7, 0x2, RZ ; /* 0x0000000207047824 */
/* 0x000fe400078e00ff */
/*0620*/ STG.E [R2.64+0xb0], R5 ; /* 0x0000b00502007986 */
/* 0x000fe6000c101904 */
/*0630*/ ISETP.NE.AND P0, PT, R4.reuse, RZ, PT ; /* 0x000000ff0400720c */
/* 0x040fe20003f05270 */
/*0640*/ STG.E [R2.64+0xb4], R5 ; /* 0x0000b40502007986 */
/* 0x0001e6000c101904 */
/*0650*/ SEL R11, R4, 0x1, P0 ; /* 0x00000001040b7807 */
/* 0x000fe20000000000 */
/*0660*/ STG.E [R2.64+0xc0], R9 ; /* 0x0000c00902007986 */
/* 0x000fe8000c101904 */
/*0670*/ IMAD.SHL.U32 R4, R11, 0x2, RZ ; /* 0x000000020b047824 */
/* 0x000fe200078e00ff */
/*0680*/ STG.E [R2.64+0xc4], R9 ; /* 0x0000c40902007986 */
/* 0x000fe2000c101904 */
/*0690*/ LOP3.LUT R5, RZ, R9, RZ, 0x33, !PT ; /* 0x00000009ff057212 */
/* 0x001fc600078e33ff */
/*06a0*/ STG.E [R2.64+0xd0], R9 ; /* 0x0000d00902007986 */
/* 0x000fe2000c101904 */
/*06b0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*06c0*/ STG.E [R2.64+0xd4], R9 ; /* 0x0000d40902007986 */
/* 0x000fe8000c101904 */
/*06d0*/ STG.E [R2.64+0xe0], R9 ; /* 0x0000e00902007986 */
/* 0x000fe8000c101904 */
/*06e0*/ STG.E [R2.64+0xe4], R9 ; /* 0x0000e40902007986 */
/* 0x000fe8000c101904 */
/*06f0*/ STG.E [R2.64+0xf0], R9 ; /* 0x0000f00902007986 */
/* 0x000fe8000c101904 */
/*0700*/ STG.E [R2.64+0xf4], R9 ; /* 0x0000f40902007986 */
/* 0x0001e8000c101904 */
/*0710*/ STG.E [R2.64+0xc8], R5 ; /* 0x0000c80502007986 */
/* 0x000fe8000c101904 */
/*0720*/ STG.E [R2.64+0xcc], R5 ; /* 0x0000cc0502007986 */
/* 0x000fe8000c101904 */
/*0730*/ STG.E [R2.64+0xd8], R5 ; /* 0x0000d80502007986 */
/* 0x000fe2000c101904 */
/*0740*/ LOP3.LUT R9, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff097212 */
/* 0x001fc600078e33ff */
/*0750*/ STG.E [R2.64+0xdc], R5 ; /* 0x0000dc0502007986 */
/* 0x000fe8000c101904 */
/*0760*/ STG.E [R2.64+0xe8], R5 ; /* 0x0000e80502007986 */
/* 0x000fe8000c101904 */
/*0770*/ STG.E [R2.64+0xec], R5 ; /* 0x0000ec0502007986 */
/* 0x000fe8000c101904 */
/*0780*/ STG.E [R2.64+0xf8], R5 ; /* 0x0000f80502007986 */
/* 0x000fe8000c101904 */
/*0790*/ STG.E [R2.64+0xfc], R5 ; /* 0x0000fc0502007986 */
/* 0x0001e8000c101904 */
/*07a0*/ STG.E [R2.64+0x100], R7 ; /* 0x0001000702007986 */
/* 0x000fe8000c101904 */
/*07b0*/ STG.E [R2.64+0x104], R7 ; /* 0x0001040702007986 */
/* 0x000fe8000c101904 */
/*07c0*/ STG.E [R2.64+0x110], R7 ; /* 0x0001100702007986 */
/* 0x000fe2000c101904 */
/*07d0*/ LOP3.LUT R5, RZ, R11, RZ, 0x33, !PT ; /* 0x0000000bff057212 */
/* 0x001fc600078e33ff */
/*07e0*/ STG.E [R2.64+0x114], R7 ; /* 0x0001140702007986 */
/* 0x000fe8000c101904 */
/*07f0*/ STG.E [R2.64+0x120], R7 ; /* 0x0001200702007986 */
/* 0x000fe8000c101904 */
/*0800*/ STG.E [R2.64+0x124], R7 ; /* 0x0001240702007986 */
/* 0x000fe8000c101904 */
/*0810*/ STG.E [R2.64+0x130], R7 ; /* 0x0001300702007986 */
/* 0x000fe8000c101904 */
/*0820*/ STG.E [R2.64+0x134], R7 ; /* 0x0001340702007986 */
/* 0x0001e8000c101904 */
/*0830*/ STG.E [R2.64+0x148], R5 ; /* 0x0001480502007986 */
/* 0x000fe8000c101904 */
/*0840*/ STG.E [R2.64+0x14c], R5 ; /* 0x00014c0502007986 */
/* 0x000fe2000c101904 */
/*0850*/ SEL R7, R4, 0x1, P0 ; /* 0x0000000104077807 */
/* 0x001fc60000000000 */
/*0860*/ STG.E [R2.64+0x158], R5 ; /* 0x0001580502007986 */
/* 0x000fe2000c101904 */
/*0870*/ IADD3 R4, P2, R2, 0x200, RZ ; /* 0x0000020002047810 */
/* 0x000fc60007f5e0ff */
/*0880*/ STG.E [R2.64+0x15c], R5 ; /* 0x00015c0502007986 */
/* 0x000fe8000c101904 */
/*0890*/ STG.E [R2.64+0x168], R5 ; /* 0x0001680502007986 */
/* 0x000fe8000c101904 */
/*08a0*/ STG.E [R2.64+0x16c], R5 ; /* 0x00016c0502007986 */
/* 0x000fe8000c101904 */
/*08b0*/ STG.E [R2.64+0x178], R5 ; /* 0x0001780502007986 */
/* 0x000fe8000c101904 */
/*08c0*/ STG.E [R2.64+0x17c], R5 ; /* 0x00017c0502007986 */
/* 0x0001e8000c101904 */
/*08d0*/ STG.E [R2.64+0x108], R9 ; /* 0x0001080902007986 */
/* 0x000fe8000c101904 */
/*08e0*/ STG.E [R2.64+0x10c], R9 ; /* 0x00010c0902007986 */
/* 0x000fe8000c101904 */
/*08f0*/ STG.E [R2.64+0x118], R9 ; /* 0x0001180902007986 */
/* 0x000fe2000c101904 */
/*0900*/ IMAD.SHL.U32 R5, R7, 0x2, RZ ; /* 0x0000000207057824 */
/* 0x001fc600078e00ff */
/*0910*/ STG.E [R2.64+0x11c], R9 ; /* 0x00011c0902007986 */
/* 0x000fe4000c101904 */
/*0920*/ ISETP.NE.AND P0, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720c */
/* 0x040fe40003f05270 */
/*0930*/ STG.E [R2.64+0x128], R9 ; /* 0x0001280902007986 */
/* 0x000fe4000c101904 */
/*0940*/ SEL R5, R5, 0x1, P0 ; /* 0x0000000105057807 */
/* 0x000fe40000000000 */
/*0950*/ STG.E [R2.64+0x12c], R9 ; /* 0x00012c0902007986 */
/* 0x000fe8000c101904 */
/*0960*/ STG.E [R2.64+0x138], R9 ; /* 0x0001380902007986 */
/* 0x000fe8000c101904 */
/*0970*/ STG.E [R2.64+0x13c], R9 ; /* 0x00013c0902007986 */
/* 0x0001e8000c101904 */
/*0980*/ STG.E [R2.64+0x140], R11 ; /* 0x0001400b02007986 */
/* 0x000fe8000c101904 */
/*0990*/ STG.E [R2.64+0x144], R11 ; /* 0x0001440b02007986 */
/* 0x000fe2000c101904 */
/*09a0*/ LOP3.LUT R9, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff097212 */
/* 0x001fc600078e33ff */
/*09b0*/ STG.E [R2.64+0x150], R11 ; /* 0x0001500b02007986 */
/* 0x000fe8000c101904 */
/*09c0*/ STG.E [R2.64+0x154], R11 ; /* 0x0001540b02007986 */
/* 0x000fe8000c101904 */
/*09d0*/ STG.E [R2.64+0x160], R11 ; /* 0x0001600b02007986 */
/* 0x000fe8000c101904 */
/*09e0*/ STG.E [R2.64+0x164], R11 ; /* 0x0001640b02007986 */
/* 0x000fe8000c101904 */
/*09f0*/ STG.E [R2.64+0x170], R11 ; /* 0x0001700b02007986 */
/* 0x000fe8000c101904 */
/*0a00*/ STG.E [R2.64+0x174], R11 ; /* 0x0001740b02007986 */
/* 0x000fe8000c101904 */
/*0a10*/ STG.E [R2.64+0x188], R9 ; /* 0x0001880902007986 */
/* 0x000fe8000c101904 */
/*0a20*/ STG.E [R2.64+0x18c], R9 ; /* 0x00018c0902007986 */
/* 0x000fe8000c101904 */
/*0a30*/ STG.E [R2.64+0x198], R9 ; /* 0x0001980902007986 */
/* 0x000fe8000c101904 */
/*0a40*/ STG.E [R2.64+0x19c], R9 ; /* 0x00019c0902007986 */
/* 0x000fe8000c101904 */
/*0a50*/ STG.E [R2.64+0x1a8], R9 ; /* 0x0001a80902007986 */
/* 0x000fe8000c101904 */
/*0a60*/ STG.E [R2.64+0x1ac], R9 ; /* 0x0001ac0902007986 */
/* 0x000fe8000c101904 */
/*0a70*/ STG.E [R2.64+0x1b8], R9 ; /* 0x0001b80902007986 */
/* 0x000fe8000c101904 */
/*0a80*/ STG.E [R2.64+0x1bc], R9 ; /* 0x0001bc0902007986 */
/* 0x0001e8000c101904 */
/*0a90*/ STG.E [R2.64+0x180], R7 ; /* 0x0001800702007986 */
/* 0x0003e8000c101904 */
/*0aa0*/ STG.E [R2.64+0x184], R7 ; /* 0x0001840702007986 */
/* 0x0003e8000c101904 */
/*0ab0*/ STG.E [R2.64+0x190], R7 ; /* 0x0001900702007986 */
/* 0x0003e2000c101904 */
/*0ac0*/ IMAD.X R9, RZ, RZ, R3, P2 ; /* 0x000000ffff097224 */
/* 0x001fc600010e0603 */
/*0ad0*/ STG.E [R2.64+0x194], R7 ; /* 0x0001940702007986 */
/* 0x0003e8000c101904 */
/*0ae0*/ STG.E [R2.64+0x1a0], R7 ; /* 0x0001a00702007986 */
/* 0x0003e8000c101904 */
/*0af0*/ STG.E [R2.64+0x1a4], R7 ; /* 0x0001a40702007986 */
/* 0x0003e8000c101904 */
/*0b00*/ STG.E [R2.64+0x1b0], R7 ; /* 0x0001b00702007986 */
/* 0x0003e8000c101904 */
/*0b10*/ STG.E [R2.64+0x1b4], R7 ; /* 0x0001b40702007986 */
/* 0x0003e2000c101904 */
/*0b20*/ @!P1 BRA 0xc0 ; /* 0xfffff59000009947 */
/* 0x000fea000383ffff */
/*0b30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b40*/ BRA 0xb40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kernel_test5_init(char* _ptr, char* end_ptr)
{
unsigned int i;
unsigned int* ptr = (unsigned int*) (_ptr + blockIdx.x*BLOCKSIZE);
if (ptr >= (unsigned int*) end_ptr) {
return;
}
unsigned int p1 = 1;
for (i = 0;i < BLOCKSIZE/sizeof(unsigned int); i+=16){
unsigned int p2 = ~p1;
ptr[i] = p1;
ptr[i+1] = p1;
ptr[i+2] = p2;
ptr[i+3] = p2;
ptr[i+4] = p1;
ptr[i+5] = p1;
ptr[i+6] = p2;
ptr[i+7] = p2;
ptr[i+8] = p1;
ptr[i+9] = p1;
ptr[i+10] = p2;
ptr[i+11] = p2;
ptr[i+12] = p1;
ptr[i+13] = p1;
ptr[i+14] = p2;
ptr[i+15] = p2;
p1 = p1<<1;
if (p1 == 0){
p1 = 1;
}
}
return;
} | .file "tmpxft_00107af8_00000000-6_kernel_test5_init.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z17kernel_test5_initPcS_PcS_
.type _Z39__device_stub__Z17kernel_test5_initPcS_PcS_, @function
_Z39__device_stub__Z17kernel_test5_initPcS_PcS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17kernel_test5_initPcS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z17kernel_test5_initPcS_PcS_, .-_Z39__device_stub__Z17kernel_test5_initPcS_PcS_
.globl _Z17kernel_test5_initPcS_
.type _Z17kernel_test5_initPcS_, @function
_Z17kernel_test5_initPcS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z17kernel_test5_initPcS_PcS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17kernel_test5_initPcS_, .-_Z17kernel_test5_initPcS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17kernel_test5_initPcS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17kernel_test5_initPcS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kernel_test5_init(char* _ptr, char* end_ptr)
{
unsigned int i;
unsigned int* ptr = (unsigned int*) (_ptr + blockIdx.x*BLOCKSIZE);
if (ptr >= (unsigned int*) end_ptr) {
return;
}
unsigned int p1 = 1;
for (i = 0;i < BLOCKSIZE/sizeof(unsigned int); i+=16){
unsigned int p2 = ~p1;
ptr[i] = p1;
ptr[i+1] = p1;
ptr[i+2] = p2;
ptr[i+3] = p2;
ptr[i+4] = p1;
ptr[i+5] = p1;
ptr[i+6] = p2;
ptr[i+7] = p2;
ptr[i+8] = p1;
ptr[i+9] = p1;
ptr[i+10] = p2;
ptr[i+11] = p2;
ptr[i+12] = p1;
ptr[i+13] = p1;
ptr[i+14] = p2;
ptr[i+15] = p2;
p1 = p1<<1;
if (p1 == 0){
p1 = 1;
}
}
return;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_test5_init(char* _ptr, char* end_ptr)
{
unsigned int i;
unsigned int* ptr = (unsigned int*) (_ptr + blockIdx.x*BLOCKSIZE);
if (ptr >= (unsigned int*) end_ptr) {
return;
}
unsigned int p1 = 1;
for (i = 0;i < BLOCKSIZE/sizeof(unsigned int); i+=16){
unsigned int p2 = ~p1;
ptr[i] = p1;
ptr[i+1] = p1;
ptr[i+2] = p2;
ptr[i+3] = p2;
ptr[i+4] = p1;
ptr[i+5] = p1;
ptr[i+6] = p2;
ptr[i+7] = p2;
ptr[i+8] = p1;
ptr[i+9] = p1;
ptr[i+10] = p2;
ptr[i+11] = p2;
ptr[i+12] = p1;
ptr[i+13] = p1;
ptr[i+14] = p2;
ptr[i+15] = p2;
p1 = p1<<1;
if (p1 == 0){
p1 = 1;
}
}
return;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_test5_init(char* _ptr, char* end_ptr)
{
unsigned int i;
unsigned int* ptr = (unsigned int*) (_ptr + blockIdx.x*BLOCKSIZE);
if (ptr >= (unsigned int*) end_ptr) {
return;
}
unsigned int p1 = 1;
for (i = 0;i < BLOCKSIZE/sizeof(unsigned int); i+=16){
unsigned int p2 = ~p1;
ptr[i] = p1;
ptr[i+1] = p1;
ptr[i+2] = p2;
ptr[i+3] = p2;
ptr[i+4] = p1;
ptr[i+5] = p1;
ptr[i+6] = p2;
ptr[i+7] = p2;
ptr[i+8] = p1;
ptr[i+9] = p1;
ptr[i+10] = p2;
ptr[i+11] = p2;
ptr[i+12] = p1;
ptr[i+13] = p1;
ptr[i+14] = p2;
ptr[i+15] = p2;
p1 = p1<<1;
if (p1 == 0){
p1 = 1;
}
}
return;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17kernel_test5_initPcS_
.globl _Z17kernel_test5_initPcS_
.p2align 8
.type _Z17kernel_test5_initPcS_,@function
_Z17kernel_test5_initPcS_:
s_load_b128 s[0:3], s[0:1], 0x0
s_lshl_b32 s4, s15, 20
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s4
s_addc_u32 s1, s1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_u64_e64 s2, s[0:1], s[2:3]
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_3
v_mov_b32_e32 v0, 0
s_mov_b32 s3, 1
s_mov_b32 s2, -16
.p2align 6
.LBB0_2:
s_not_b32 s4, s3
v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v2, s3
v_dual_mov_b32 v3, s4 :: v_dual_mov_b32 v4, s4
s_lshl_b32 s3, s3, 1
s_add_i32 s2, s2, 16
s_max_u32 s3, s3, 1
s_clause 0x3
global_store_b128 v0, v[1:4], s[0:1]
global_store_b128 v0, v[1:4], s[0:1] offset:16
global_store_b128 v0, v[1:4], s[0:1] offset:32
global_store_b128 v0, v[1:4], s[0:1] offset:48
s_add_u32 s0, s0, 64
s_addc_u32 s1, s1, 0
s_cmp_lt_u32 s2, 0x3fff0
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17kernel_test5_initPcS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17kernel_test5_initPcS_, .Lfunc_end0-_Z17kernel_test5_initPcS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17kernel_test5_initPcS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17kernel_test5_initPcS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_test5_init(char* _ptr, char* end_ptr)
{
unsigned int i;
unsigned int* ptr = (unsigned int*) (_ptr + blockIdx.x*BLOCKSIZE);
if (ptr >= (unsigned int*) end_ptr) {
return;
}
unsigned int p1 = 1;
for (i = 0;i < BLOCKSIZE/sizeof(unsigned int); i+=16){
unsigned int p2 = ~p1;
ptr[i] = p1;
ptr[i+1] = p1;
ptr[i+2] = p2;
ptr[i+3] = p2;
ptr[i+4] = p1;
ptr[i+5] = p1;
ptr[i+6] = p2;
ptr[i+7] = p2;
ptr[i+8] = p1;
ptr[i+9] = p1;
ptr[i+10] = p2;
ptr[i+11] = p2;
ptr[i+12] = p1;
ptr[i+13] = p1;
ptr[i+14] = p2;
ptr[i+15] = p2;
p1 = p1<<1;
if (p1 == 0){
p1 = 1;
}
}
return;
} | .text
.file "kernel_test5_init.hip"
.globl _Z32__device_stub__kernel_test5_initPcS_ # -- Begin function _Z32__device_stub__kernel_test5_initPcS_
.p2align 4, 0x90
.type _Z32__device_stub__kernel_test5_initPcS_,@function
_Z32__device_stub__kernel_test5_initPcS_: # @_Z32__device_stub__kernel_test5_initPcS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z17kernel_test5_initPcS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z32__device_stub__kernel_test5_initPcS_, .Lfunc_end0-_Z32__device_stub__kernel_test5_initPcS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17kernel_test5_initPcS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17kernel_test5_initPcS_,@object # @_Z17kernel_test5_initPcS_
.section .rodata,"a",@progbits
.globl _Z17kernel_test5_initPcS_
.p2align 3, 0x0
_Z17kernel_test5_initPcS_:
.quad _Z32__device_stub__kernel_test5_initPcS_
.size _Z17kernel_test5_initPcS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17kernel_test5_initPcS_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__kernel_test5_initPcS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17kernel_test5_initPcS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17kernel_test5_initPcS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e240000002500 */
/*0020*/ LEA R0, P1, R0, c[0x0][0x160], 0x14 ; /* 0x0000580000007a11 */
/* 0x001fc8000782a0ff */
/*0030*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe20003f06070 */
/*0040*/ IMAD.X R9, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff097624 */
/* 0x000fca00008e06ff */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, R9, c[0x0][0x16c], PT, P0 ; /* 0x00005b0009007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IADD3 R4, P0, R0, 0x40, RZ ; /* 0x0000004000047810 */
/* 0x000fe20007f1e0ff */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD.X R9, RZ, RZ, R9, P0 ; /* 0x000000ffff097224 */
/* 0x000fe400000e0609 */
/*00c0*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x002fe200078e0004 */
/*00d0*/ LOP3.LUT R7, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff077212 */
/* 0x000fe200078e33ff */
/*00e0*/ IMAD.SHL.U32 R4, R5, 0x2, RZ ; /* 0x0000000205047824 */
/* 0x000fe200078e00ff */
/*00f0*/ IADD3 R0, R0, 0x80, RZ ; /* 0x0000008000007810 */
/* 0x000fe20007ffe0ff */
/*0100*/ IMAD.MOV.U32 R3, RZ, RZ, R9 ; /* 0x000000ffff037224 */
/* 0x000fc600078e0009 */
/*0110*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*0120*/ STG.E [R2.64+-0x38], R7 ; /* 0xffffc80702007986 */
/* 0x000fe2000c101904 */
/*0130*/ ISETP.GE.U32.AND P1, PT, R0, 0x40000, PT ; /* 0x000400000000780c */
/* 0x000fe40003f26070 */
/*0140*/ SEL R9, R4, 0x1, P0 ; /* 0x0000000104097807 */
/* 0x000fe20000000000 */
/*0150*/ STG.E [R2.64+-0x34], R7 ; /* 0xffffcc0702007986 */
/* 0x000fe8000c101904 */
/*0160*/ IMAD.SHL.U32 R4, R9, 0x2, RZ ; /* 0x0000000209047824 */
/* 0x000fe200078e00ff */
/*0170*/ STG.E [R2.64+-0x28], R7 ; /* 0xffffd80702007986 */
/* 0x000fe8000c101904 */
/*0180*/ ISETP.NE.AND P0, PT, R4.reuse, RZ, PT ; /* 0x000000ff0400720c */
/* 0x040fe20003f05270 */
/*0190*/ STG.E [R2.64+-0x24], R7 ; /* 0xffffdc0702007986 */
/* 0x000fe8000c101904 */
/*01a0*/ STG.E [R2.64+-0x18], R7 ; /* 0xffffe80702007986 */
/* 0x000fe8000c101904 */
/*01b0*/ STG.E [R2.64+-0x14], R7 ; /* 0xffffec0702007986 */
/* 0x000fe8000c101904 */
/*01c0*/ STG.E [R2.64+-0x8], R7 ; /* 0xfffff80702007986 */
/* 0x000fe8000c101904 */
/*01d0*/ STG.E [R2.64+-0x4], R7 ; /* 0xfffffc0702007986 */
/* 0x0001e8000c101904 */
/*01e0*/ STG.E [R2.64+-0x40], R5 ; /* 0xffffc00502007986 */
/* 0x000fe8000c101904 */
/*01f0*/ STG.E [R2.64+-0x3c], R5 ; /* 0xffffc40502007986 */
/* 0x000fe2000c101904 */
/*0200*/ SEL R7, R4, 0x1, P0 ; /* 0x0000000104077807 */
/* 0x001fc60000000000 */
/*0210*/ STG.E [R2.64+-0x30], R5 ; /* 0xffffd00502007986 */
/* 0x000fe4000c101904 */
/*0220*/ IMAD.SHL.U32 R4, R7, 0x2, RZ ; /* 0x0000000207047824 */
/* 0x000fe400078e00ff */
/*0230*/ STG.E [R2.64+-0x2c], R5 ; /* 0xffffd40502007986 */
/* 0x000fe8000c101904 */
/*0240*/ STG.E [R2.64+-0x20], R5 ; /* 0xffffe00502007986 */
/* 0x000fe2000c101904 */
/*0250*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0260*/ STG.E [R2.64+-0x1c], R5 ; /* 0xffffe40502007986 */
/* 0x000fe8000c101904 */
/*0270*/ STG.E [R2.64+-0x10], R5 ; /* 0xfffff00502007986 */
/* 0x000fe8000c101904 */
/*0280*/ STG.E [R2.64+-0xc], R5 ; /* 0xfffff40502007986 */
/* 0x0001e8000c101904 */
/*0290*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*02a0*/ STG.E [R2.64+0x4], R9 ; /* 0x0000040902007986 */
/* 0x000fe2000c101904 */
/*02b0*/ LOP3.LUT R5, RZ, R9, RZ, 0x33, !PT ; /* 0x00000009ff057212 */
/* 0x001fc600078e33ff */
/*02c0*/ STG.E [R2.64+0x10], R9 ; /* 0x0000100902007986 */
/* 0x000fe8000c101904 */
/*02d0*/ STG.E [R2.64+0x8], R5 ; /* 0x0000080502007986 */
/* 0x000fe8000c101904 */
/*02e0*/ STG.E [R2.64+0xc], R5 ; /* 0x00000c0502007986 */
/* 0x000fe8000c101904 */
/*02f0*/ STG.E [R2.64+0x18], R5 ; /* 0x0000180502007986 */
/* 0x000fe8000c101904 */
/*0300*/ STG.E [R2.64+0x1c], R5 ; /* 0x00001c0502007986 */
/* 0x000fe8000c101904 */
/*0310*/ STG.E [R2.64+0x28], R5 ; /* 0x0000280502007986 */
/* 0x000fe8000c101904 */
/*0320*/ STG.E [R2.64+0x2c], R5 ; /* 0x00002c0502007986 */
/* 0x000fe8000c101904 */
/*0330*/ STG.E [R2.64+0x38], R5 ; /* 0x0000380502007986 */
/* 0x000fe8000c101904 */
/*0340*/ STG.E [R2.64+0x3c], R5 ; /* 0x00003c0502007986 */
/* 0x0001e8000c101904 */
/*0350*/ STG.E [R2.64+0x14], R9 ; /* 0x0000140902007986 */
/* 0x000fe8000c101904 */
/*0360*/ STG.E [R2.64+0x20], R9 ; /* 0x0000200902007986 */
/* 0x000fe2000c101904 */
/*0370*/ SEL R5, R4, 0x1, P0 ; /* 0x0000000104057807 */
/* 0x001fc60000000000 */
/*0380*/ STG.E [R2.64+0x24], R9 ; /* 0x0000240902007986 */
/* 0x000fe4000c101904 */
/*0390*/ IMAD.SHL.U32 R4, R5, 0x2, RZ ; /* 0x0000000205047824 */
/* 0x000fe400078e00ff */
/*03a0*/ STG.E [R2.64+0x30], R9 ; /* 0x0000300902007986 */
/* 0x000fe8000c101904 */
/*03b0*/ STG.E [R2.64+0x34], R9 ; /* 0x0000340902007986 */
/* 0x0001e2000c101904 */
/*03c0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*03d0*/ STG.E [R2.64+0x40], R7 ; /* 0x0000400702007986 */
/* 0x000fe8000c101904 */
/*03e0*/ STG.E [R2.64+0x44], R7 ; /* 0x0000440702007986 */
/* 0x000fe2000c101904 */
/*03f0*/ LOP3.LUT R9, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff097212 */
/* 0x001fc600078e33ff */
/*0400*/ STG.E [R2.64+0x50], R7 ; /* 0x0000500702007986 */
/* 0x000fe8000c101904 */
/*0410*/ STG.E [R2.64+0x48], R9 ; /* 0x0000480902007986 */
/* 0x000fe8000c101904 */
/*0420*/ STG.E [R2.64+0x4c], R9 ; /* 0x00004c0902007986 */
/* 0x000fe8000c101904 */
/*0430*/ STG.E [R2.64+0x58], R9 ; /* 0x0000580902007986 */
/* 0x000fe8000c101904 */
/*0440*/ STG.E [R2.64+0x5c], R9 ; /* 0x00005c0902007986 */
/* 0x000fe8000c101904 */
/*0450*/ STG.E [R2.64+0x68], R9 ; /* 0x0000680902007986 */
/* 0x000fe8000c101904 */
/*0460*/ STG.E [R2.64+0x6c], R9 ; /* 0x00006c0902007986 */
/* 0x000fe8000c101904 */
/*0470*/ STG.E [R2.64+0x78], R9 ; /* 0x0000780902007986 */
/* 0x000fe8000c101904 */
/*0480*/ STG.E [R2.64+0x7c], R9 ; /* 0x00007c0902007986 */
/* 0x0001e8000c101904 */
/*0490*/ STG.E [R2.64+0x54], R7 ; /* 0x0000540702007986 */
/* 0x000fe8000c101904 */
/*04a0*/ STG.E [R2.64+0x60], R7 ; /* 0x0000600702007986 */
/* 0x000fe2000c101904 */
/*04b0*/ SEL R9, R4, 0x1, P0 ; /* 0x0000000104097807 */
/* 0x001fc60000000000 */
/*04c0*/ STG.E [R2.64+0x64], R7 ; /* 0x0000640702007986 */
/* 0x000fe4000c101904 */
/*04d0*/ IMAD.SHL.U32 R4, R9, 0x2, RZ ; /* 0x0000000209047824 */
/* 0x000fe400078e00ff */
/*04e0*/ STG.E [R2.64+0x70], R7 ; /* 0x0000700702007986 */
/* 0x000fe8000c101904 */
/*04f0*/ STG.E [R2.64+0x74], R7 ; /* 0x0000740702007986 */
/* 0x0001e2000c101904 */
/*0500*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0510*/ STG.E [R2.64+0x80], R5 ; /* 0x0000800502007986 */
/* 0x000fe8000c101904 */
/*0520*/ STG.E [R2.64+0x84], R5 ; /* 0x0000840502007986 */
/* 0x000fe2000c101904 */
/*0530*/ LOP3.LUT R7, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff077212 */
/* 0x001fc600078e33ff */
/*0540*/ STG.E [R2.64+0x90], R5 ; /* 0x0000900502007986 */
/* 0x000fe8000c101904 */
/*0550*/ STG.E [R2.64+0x88], R7 ; /* 0x0000880702007986 */
/* 0x000fe8000c101904 */
/*0560*/ STG.E [R2.64+0x8c], R7 ; /* 0x00008c0702007986 */
/* 0x000fe8000c101904 */
/*0570*/ STG.E [R2.64+0x98], R7 ; /* 0x0000980702007986 */
/* 0x000fe8000c101904 */
/*0580*/ STG.E [R2.64+0x9c], R7 ; /* 0x00009c0702007986 */
/* 0x000fe8000c101904 */
/*0590*/ STG.E [R2.64+0xa8], R7 ; /* 0x0000a80702007986 */
/* 0x000fe8000c101904 */
/*05a0*/ STG.E [R2.64+0xac], R7 ; /* 0x0000ac0702007986 */
/* 0x000fe8000c101904 */
/*05b0*/ STG.E [R2.64+0xb8], R7 ; /* 0x0000b80702007986 */
/* 0x000fe8000c101904 */
/*05c0*/ STG.E [R2.64+0xbc], R7 ; /* 0x0000bc0702007986 */
/* 0x0001e8000c101904 */
/*05d0*/ STG.E [R2.64+0x94], R5 ; /* 0x0000940502007986 */
/* 0x000fe8000c101904 */
/*05e0*/ STG.E [R2.64+0xa0], R5 ; /* 0x0000a00502007986 */
/* 0x000fe2000c101904 */
/*05f0*/ SEL R7, R4, 0x1, P0 ; /* 0x0000000104077807 */
/* 0x001fc60000000000 */
/*0600*/ STG.E [R2.64+0xa4], R5 ; /* 0x0000a40502007986 */
/* 0x000fe4000c101904 */
/*0610*/ IMAD.SHL.U32 R4, R7, 0x2, RZ ; /* 0x0000000207047824 */
/* 0x000fe400078e00ff */
/*0620*/ STG.E [R2.64+0xb0], R5 ; /* 0x0000b00502007986 */
/* 0x000fe6000c101904 */
/*0630*/ ISETP.NE.AND P0, PT, R4.reuse, RZ, PT ; /* 0x000000ff0400720c */
/* 0x040fe20003f05270 */
/*0640*/ STG.E [R2.64+0xb4], R5 ; /* 0x0000b40502007986 */
/* 0x0001e6000c101904 */
/*0650*/ SEL R11, R4, 0x1, P0 ; /* 0x00000001040b7807 */
/* 0x000fe20000000000 */
/*0660*/ STG.E [R2.64+0xc0], R9 ; /* 0x0000c00902007986 */
/* 0x000fe8000c101904 */
/*0670*/ IMAD.SHL.U32 R4, R11, 0x2, RZ ; /* 0x000000020b047824 */
/* 0x000fe200078e00ff */
/*0680*/ STG.E [R2.64+0xc4], R9 ; /* 0x0000c40902007986 */
/* 0x000fe2000c101904 */
/*0690*/ LOP3.LUT R5, RZ, R9, RZ, 0x33, !PT ; /* 0x00000009ff057212 */
/* 0x001fc600078e33ff */
/*06a0*/ STG.E [R2.64+0xd0], R9 ; /* 0x0000d00902007986 */
/* 0x000fe2000c101904 */
/*06b0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*06c0*/ STG.E [R2.64+0xd4], R9 ; /* 0x0000d40902007986 */
/* 0x000fe8000c101904 */
/*06d0*/ STG.E [R2.64+0xe0], R9 ; /* 0x0000e00902007986 */
/* 0x000fe8000c101904 */
/*06e0*/ STG.E [R2.64+0xe4], R9 ; /* 0x0000e40902007986 */
/* 0x000fe8000c101904 */
/*06f0*/ STG.E [R2.64+0xf0], R9 ; /* 0x0000f00902007986 */
/* 0x000fe8000c101904 */
/*0700*/ STG.E [R2.64+0xf4], R9 ; /* 0x0000f40902007986 */
/* 0x0001e8000c101904 */
/*0710*/ STG.E [R2.64+0xc8], R5 ; /* 0x0000c80502007986 */
/* 0x000fe8000c101904 */
/*0720*/ STG.E [R2.64+0xcc], R5 ; /* 0x0000cc0502007986 */
/* 0x000fe8000c101904 */
/*0730*/ STG.E [R2.64+0xd8], R5 ; /* 0x0000d80502007986 */
/* 0x000fe2000c101904 */
/*0740*/ LOP3.LUT R9, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff097212 */
/* 0x001fc600078e33ff */
/*0750*/ STG.E [R2.64+0xdc], R5 ; /* 0x0000dc0502007986 */
/* 0x000fe8000c101904 */
/*0760*/ STG.E [R2.64+0xe8], R5 ; /* 0x0000e80502007986 */
/* 0x000fe8000c101904 */
/*0770*/ STG.E [R2.64+0xec], R5 ; /* 0x0000ec0502007986 */
/* 0x000fe8000c101904 */
/*0780*/ STG.E [R2.64+0xf8], R5 ; /* 0x0000f80502007986 */
/* 0x000fe8000c101904 */
/*0790*/ STG.E [R2.64+0xfc], R5 ; /* 0x0000fc0502007986 */
/* 0x0001e8000c101904 */
/*07a0*/ STG.E [R2.64+0x100], R7 ; /* 0x0001000702007986 */
/* 0x000fe8000c101904 */
/*07b0*/ STG.E [R2.64+0x104], R7 ; /* 0x0001040702007986 */
/* 0x000fe8000c101904 */
/*07c0*/ STG.E [R2.64+0x110], R7 ; /* 0x0001100702007986 */
/* 0x000fe2000c101904 */
/*07d0*/ LOP3.LUT R5, RZ, R11, RZ, 0x33, !PT ; /* 0x0000000bff057212 */
/* 0x001fc600078e33ff */
/*07e0*/ STG.E [R2.64+0x114], R7 ; /* 0x0001140702007986 */
/* 0x000fe8000c101904 */
/*07f0*/ STG.E [R2.64+0x120], R7 ; /* 0x0001200702007986 */
/* 0x000fe8000c101904 */
/*0800*/ STG.E [R2.64+0x124], R7 ; /* 0x0001240702007986 */
/* 0x000fe8000c101904 */
/*0810*/ STG.E [R2.64+0x130], R7 ; /* 0x0001300702007986 */
/* 0x000fe8000c101904 */
/*0820*/ STG.E [R2.64+0x134], R7 ; /* 0x0001340702007986 */
/* 0x0001e8000c101904 */
/*0830*/ STG.E [R2.64+0x148], R5 ; /* 0x0001480502007986 */
/* 0x000fe8000c101904 */
/*0840*/ STG.E [R2.64+0x14c], R5 ; /* 0x00014c0502007986 */
/* 0x000fe2000c101904 */
/*0850*/ SEL R7, R4, 0x1, P0 ; /* 0x0000000104077807 */
/* 0x001fc60000000000 */
/*0860*/ STG.E [R2.64+0x158], R5 ; /* 0x0001580502007986 */
/* 0x000fe2000c101904 */
/*0870*/ IADD3 R4, P2, R2, 0x200, RZ ; /* 0x0000020002047810 */
/* 0x000fc60007f5e0ff */
/*0880*/ STG.E [R2.64+0x15c], R5 ; /* 0x00015c0502007986 */
/* 0x000fe8000c101904 */
/*0890*/ STG.E [R2.64+0x168], R5 ; /* 0x0001680502007986 */
/* 0x000fe8000c101904 */
/*08a0*/ STG.E [R2.64+0x16c], R5 ; /* 0x00016c0502007986 */
/* 0x000fe8000c101904 */
/*08b0*/ STG.E [R2.64+0x178], R5 ; /* 0x0001780502007986 */
/* 0x000fe8000c101904 */
/*08c0*/ STG.E [R2.64+0x17c], R5 ; /* 0x00017c0502007986 */
/* 0x0001e8000c101904 */
/*08d0*/ STG.E [R2.64+0x108], R9 ; /* 0x0001080902007986 */
/* 0x000fe8000c101904 */
/*08e0*/ STG.E [R2.64+0x10c], R9 ; /* 0x00010c0902007986 */
/* 0x000fe8000c101904 */
/*08f0*/ STG.E [R2.64+0x118], R9 ; /* 0x0001180902007986 */
/* 0x000fe2000c101904 */
/*0900*/ IMAD.SHL.U32 R5, R7, 0x2, RZ ; /* 0x0000000207057824 */
/* 0x001fc600078e00ff */
/*0910*/ STG.E [R2.64+0x11c], R9 ; /* 0x00011c0902007986 */
/* 0x000fe4000c101904 */
/*0920*/ ISETP.NE.AND P0, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720c */
/* 0x040fe40003f05270 */
/*0930*/ STG.E [R2.64+0x128], R9 ; /* 0x0001280902007986 */
/* 0x000fe4000c101904 */
/*0940*/ SEL R5, R5, 0x1, P0 ; /* 0x0000000105057807 */
/* 0x000fe40000000000 */
/*0950*/ STG.E [R2.64+0x12c], R9 ; /* 0x00012c0902007986 */
/* 0x000fe8000c101904 */
/*0960*/ STG.E [R2.64+0x138], R9 ; /* 0x0001380902007986 */
/* 0x000fe8000c101904 */
/*0970*/ STG.E [R2.64+0x13c], R9 ; /* 0x00013c0902007986 */
/* 0x0001e8000c101904 */
/*0980*/ STG.E [R2.64+0x140], R11 ; /* 0x0001400b02007986 */
/* 0x000fe8000c101904 */
/*0990*/ STG.E [R2.64+0x144], R11 ; /* 0x0001440b02007986 */
/* 0x000fe2000c101904 */
/*09a0*/ LOP3.LUT R9, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff097212 */
/* 0x001fc600078e33ff */
/*09b0*/ STG.E [R2.64+0x150], R11 ; /* 0x0001500b02007986 */
/* 0x000fe8000c101904 */
/*09c0*/ STG.E [R2.64+0x154], R11 ; /* 0x0001540b02007986 */
/* 0x000fe8000c101904 */
/*09d0*/ STG.E [R2.64+0x160], R11 ; /* 0x0001600b02007986 */
/* 0x000fe8000c101904 */
/*09e0*/ STG.E [R2.64+0x164], R11 ; /* 0x0001640b02007986 */
/* 0x000fe8000c101904 */
/*09f0*/ STG.E [R2.64+0x170], R11 ; /* 0x0001700b02007986 */
/* 0x000fe8000c101904 */
/*0a00*/ STG.E [R2.64+0x174], R11 ; /* 0x0001740b02007986 */
/* 0x000fe8000c101904 */
/*0a10*/ STG.E [R2.64+0x188], R9 ; /* 0x0001880902007986 */
/* 0x000fe8000c101904 */
/*0a20*/ STG.E [R2.64+0x18c], R9 ; /* 0x00018c0902007986 */
/* 0x000fe8000c101904 */
/*0a30*/ STG.E [R2.64+0x198], R9 ; /* 0x0001980902007986 */
/* 0x000fe8000c101904 */
/*0a40*/ STG.E [R2.64+0x19c], R9 ; /* 0x00019c0902007986 */
/* 0x000fe8000c101904 */
/*0a50*/ STG.E [R2.64+0x1a8], R9 ; /* 0x0001a80902007986 */
/* 0x000fe8000c101904 */
/*0a60*/ STG.E [R2.64+0x1ac], R9 ; /* 0x0001ac0902007986 */
/* 0x000fe8000c101904 */
/*0a70*/ STG.E [R2.64+0x1b8], R9 ; /* 0x0001b80902007986 */
/* 0x000fe8000c101904 */
/*0a80*/ STG.E [R2.64+0x1bc], R9 ; /* 0x0001bc0902007986 */
/* 0x0001e8000c101904 */
/*0a90*/ STG.E [R2.64+0x180], R7 ; /* 0x0001800702007986 */
/* 0x0003e8000c101904 */
/*0aa0*/ STG.E [R2.64+0x184], R7 ; /* 0x0001840702007986 */
/* 0x0003e8000c101904 */
/*0ab0*/ STG.E [R2.64+0x190], R7 ; /* 0x0001900702007986 */
/* 0x0003e2000c101904 */
/*0ac0*/ IMAD.X R9, RZ, RZ, R3, P2 ; /* 0x000000ffff097224 */
/* 0x001fc600010e0603 */
/*0ad0*/ STG.E [R2.64+0x194], R7 ; /* 0x0001940702007986 */
/* 0x0003e8000c101904 */
/*0ae0*/ STG.E [R2.64+0x1a0], R7 ; /* 0x0001a00702007986 */
/* 0x0003e8000c101904 */
/*0af0*/ STG.E [R2.64+0x1a4], R7 ; /* 0x0001a40702007986 */
/* 0x0003e8000c101904 */
/*0b00*/ STG.E [R2.64+0x1b0], R7 ; /* 0x0001b00702007986 */
/* 0x0003e8000c101904 */
/*0b10*/ STG.E [R2.64+0x1b4], R7 ; /* 0x0001b40702007986 */
/* 0x0003e2000c101904 */
/*0b20*/ @!P1 BRA 0xc0 ; /* 0xfffff59000009947 */
/* 0x000fea000383ffff */
/*0b30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b40*/ BRA 0xb40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17kernel_test5_initPcS_
.globl _Z17kernel_test5_initPcS_
.p2align 8
.type _Z17kernel_test5_initPcS_,@function
_Z17kernel_test5_initPcS_:
s_load_b128 s[0:3], s[0:1], 0x0
s_lshl_b32 s4, s15, 20
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s4
s_addc_u32 s1, s1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_u64_e64 s2, s[0:1], s[2:3]
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_3
v_mov_b32_e32 v0, 0
s_mov_b32 s3, 1
s_mov_b32 s2, -16
.p2align 6
.LBB0_2:
s_not_b32 s4, s3
v_dual_mov_b32 v1, s3 :: v_dual_mov_b32 v2, s3
v_dual_mov_b32 v3, s4 :: v_dual_mov_b32 v4, s4
s_lshl_b32 s3, s3, 1
s_add_i32 s2, s2, 16
s_max_u32 s3, s3, 1
s_clause 0x3
global_store_b128 v0, v[1:4], s[0:1]
global_store_b128 v0, v[1:4], s[0:1] offset:16
global_store_b128 v0, v[1:4], s[0:1] offset:32
global_store_b128 v0, v[1:4], s[0:1] offset:48
s_add_u32 s0, s0, 64
s_addc_u32 s1, s1, 0
s_cmp_lt_u32 s2, 0x3fff0
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17kernel_test5_initPcS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17kernel_test5_initPcS_, .Lfunc_end0-_Z17kernel_test5_initPcS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17kernel_test5_initPcS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17kernel_test5_initPcS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00107af8_00000000-6_kernel_test5_init.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z17kernel_test5_initPcS_PcS_
.type _Z39__device_stub__Z17kernel_test5_initPcS_PcS_, @function
_Z39__device_stub__Z17kernel_test5_initPcS_PcS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17kernel_test5_initPcS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z17kernel_test5_initPcS_PcS_, .-_Z39__device_stub__Z17kernel_test5_initPcS_PcS_
.globl _Z17kernel_test5_initPcS_
.type _Z17kernel_test5_initPcS_, @function
_Z17kernel_test5_initPcS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z17kernel_test5_initPcS_PcS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17kernel_test5_initPcS_, .-_Z17kernel_test5_initPcS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17kernel_test5_initPcS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17kernel_test5_initPcS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel_test5_init.hip"
.globl _Z32__device_stub__kernel_test5_initPcS_ # -- Begin function _Z32__device_stub__kernel_test5_initPcS_
.p2align 4, 0x90
.type _Z32__device_stub__kernel_test5_initPcS_,@function
_Z32__device_stub__kernel_test5_initPcS_: # @_Z32__device_stub__kernel_test5_initPcS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z17kernel_test5_initPcS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z32__device_stub__kernel_test5_initPcS_, .Lfunc_end0-_Z32__device_stub__kernel_test5_initPcS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17kernel_test5_initPcS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17kernel_test5_initPcS_,@object # @_Z17kernel_test5_initPcS_
.section .rodata,"a",@progbits
.globl _Z17kernel_test5_initPcS_
.p2align 3, 0x0
_Z17kernel_test5_initPcS_:
.quad _Z32__device_stub__kernel_test5_initPcS_
.size _Z17kernel_test5_initPcS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17kernel_test5_initPcS_"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__kernel_test5_initPcS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17kernel_test5_initPcS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void ExtQtyKernel (double *ExtLabel, double *Dens, double *Label, int nsec, int nrad)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
if (i<nrad && j<nsec)
ExtLabel[i*nsec + j] = Dens[i*nsec + j]*Label[i*nsec + j];
} | code for sm_80
Function : _Z12ExtQtyKernelPdS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R3, c[0x0][0x178], R0 ; /* 0x00005e0003007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R9, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0209 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R9.reuse, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x0c0fe400078e0209 */
/*00f0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*0100*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*0110*/ IMAD.WIDE R8, R0, R9, c[0x0][0x160] ; /* 0x0000580000087625 */
/* 0x000fe200078e0209 */
/*0120*/ DMUL R6, R4, R2 ; /* 0x0000000204067228 */
/* 0x004e0e0000000000 */
/*0130*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void ExtQtyKernel (double *ExtLabel, double *Dens, double *Label, int nsec, int nrad)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
if (i<nrad && j<nsec)
ExtLabel[i*nsec + j] = Dens[i*nsec + j]*Label[i*nsec + j];
} | .file "tmpxft_00189bcf_00000000-6_ExtQtyKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z12ExtQtyKernelPdS_S_iiPdS_S_ii
.type _Z38__device_stub__Z12ExtQtyKernelPdS_S_iiPdS_S_ii, @function
_Z38__device_stub__Z12ExtQtyKernelPdS_S_iiPdS_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12ExtQtyKernelPdS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z12ExtQtyKernelPdS_S_iiPdS_S_ii, .-_Z38__device_stub__Z12ExtQtyKernelPdS_S_iiPdS_S_ii
.globl _Z12ExtQtyKernelPdS_S_ii
.type _Z12ExtQtyKernelPdS_S_ii, @function
_Z12ExtQtyKernelPdS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z12ExtQtyKernelPdS_S_iiPdS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12ExtQtyKernelPdS_S_ii, .-_Z12ExtQtyKernelPdS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12ExtQtyKernelPdS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12ExtQtyKernelPdS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void ExtQtyKernel (double *ExtLabel, double *Dens, double *Label, int nsec, int nrad)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
if (i<nrad && j<nsec)
ExtLabel[i*nsec + j] = Dens[i*nsec + j]*Label[i*nsec + j];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ExtQtyKernel (double *ExtLabel, double *Dens, double *Label, int nsec, int nrad)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
if (i<nrad && j<nsec)
ExtLabel[i*nsec + j] = Dens[i*nsec + j]*Label[i*nsec + j];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ExtQtyKernel (double *ExtLabel, double *Dens, double *Label, int nsec, int nrad)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
if (i<nrad && j<nsec)
ExtLabel[i*nsec + j] = Dens[i*nsec + j]*Label[i*nsec + j];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12ExtQtyKernelPdS_S_ii
.globl _Z12ExtQtyKernelPdS_S_ii
.p2align 8
.type _Z12ExtQtyKernelPdS_S_ii,@function
_Z12ExtQtyKernelPdS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s5, v0
v_cmp_gt_i32_e64 s2, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[8:11], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s4, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s10, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s8, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12ExtQtyKernelPdS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12ExtQtyKernelPdS_S_ii, .Lfunc_end0-_Z12ExtQtyKernelPdS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12ExtQtyKernelPdS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12ExtQtyKernelPdS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ExtQtyKernel (double *ExtLabel, double *Dens, double *Label, int nsec, int nrad)
{
int j = threadIdx.x + blockDim.x*blockIdx.x;
int i = threadIdx.y + blockDim.y*blockIdx.y;
if (i<nrad && j<nsec)
ExtLabel[i*nsec + j] = Dens[i*nsec + j]*Label[i*nsec + j];
} | .text
.file "ExtQtyKernel.hip"
.globl _Z27__device_stub__ExtQtyKernelPdS_S_ii # -- Begin function _Z27__device_stub__ExtQtyKernelPdS_S_ii
.p2align 4, 0x90
.type _Z27__device_stub__ExtQtyKernelPdS_S_ii,@function
_Z27__device_stub__ExtQtyKernelPdS_S_ii: # @_Z27__device_stub__ExtQtyKernelPdS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12ExtQtyKernelPdS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__ExtQtyKernelPdS_S_ii, .Lfunc_end0-_Z27__device_stub__ExtQtyKernelPdS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12ExtQtyKernelPdS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12ExtQtyKernelPdS_S_ii,@object # @_Z12ExtQtyKernelPdS_S_ii
.section .rodata,"a",@progbits
.globl _Z12ExtQtyKernelPdS_S_ii
.p2align 3, 0x0
_Z12ExtQtyKernelPdS_S_ii:
.quad _Z27__device_stub__ExtQtyKernelPdS_S_ii
.size _Z12ExtQtyKernelPdS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12ExtQtyKernelPdS_S_ii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__ExtQtyKernelPdS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12ExtQtyKernelPdS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12ExtQtyKernelPdS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R3, c[0x0][0x178], R0 ; /* 0x00005e0003007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R9, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0209 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R9.reuse, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x0c0fe400078e0209 */
/*00f0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*0100*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*0110*/ IMAD.WIDE R8, R0, R9, c[0x0][0x160] ; /* 0x0000580000087625 */
/* 0x000fe200078e0209 */
/*0120*/ DMUL R6, R4, R2 ; /* 0x0000000204067228 */
/* 0x004e0e0000000000 */
/*0130*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12ExtQtyKernelPdS_S_ii
.globl _Z12ExtQtyKernelPdS_S_ii
.p2align 8
.type _Z12ExtQtyKernelPdS_S_ii,@function
_Z12ExtQtyKernelPdS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s15, s2, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s5, v0
v_cmp_gt_i32_e64 s2, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[8:11], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s4, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s10, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s8, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12ExtQtyKernelPdS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12ExtQtyKernelPdS_S_ii, .Lfunc_end0-_Z12ExtQtyKernelPdS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12ExtQtyKernelPdS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12ExtQtyKernelPdS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00189bcf_00000000-6_ExtQtyKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z12ExtQtyKernelPdS_S_iiPdS_S_ii
.type _Z38__device_stub__Z12ExtQtyKernelPdS_S_iiPdS_S_ii, @function
_Z38__device_stub__Z12ExtQtyKernelPdS_S_iiPdS_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12ExtQtyKernelPdS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z12ExtQtyKernelPdS_S_iiPdS_S_ii, .-_Z38__device_stub__Z12ExtQtyKernelPdS_S_iiPdS_S_ii
.globl _Z12ExtQtyKernelPdS_S_ii
.type _Z12ExtQtyKernelPdS_S_ii, @function
_Z12ExtQtyKernelPdS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z12ExtQtyKernelPdS_S_iiPdS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12ExtQtyKernelPdS_S_ii, .-_Z12ExtQtyKernelPdS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12ExtQtyKernelPdS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12ExtQtyKernelPdS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ExtQtyKernel.hip"
.globl _Z27__device_stub__ExtQtyKernelPdS_S_ii # -- Begin function _Z27__device_stub__ExtQtyKernelPdS_S_ii
.p2align 4, 0x90
.type _Z27__device_stub__ExtQtyKernelPdS_S_ii,@function
_Z27__device_stub__ExtQtyKernelPdS_S_ii: # @_Z27__device_stub__ExtQtyKernelPdS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12ExtQtyKernelPdS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__ExtQtyKernelPdS_S_ii, .Lfunc_end0-_Z27__device_stub__ExtQtyKernelPdS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12ExtQtyKernelPdS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12ExtQtyKernelPdS_S_ii,@object # @_Z12ExtQtyKernelPdS_S_ii
.section .rodata,"a",@progbits
.globl _Z12ExtQtyKernelPdS_S_ii
.p2align 3, 0x0
_Z12ExtQtyKernelPdS_S_ii:
.quad _Z27__device_stub__ExtQtyKernelPdS_S_ii
.size _Z12ExtQtyKernelPdS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12ExtQtyKernelPdS_S_ii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__ExtQtyKernelPdS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12ExtQtyKernelPdS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
//device
__global__ void primer_kernel(){}
//host
int main(int argc, char *argv[]){
int DeviceCount = 0;
//inicializamos CUDA
if(cuInit(0) != 0){
printf("ERROR en la inicializacion\n");
exit(0);
}
//obtenemos el numero de dispositivos compatibles con CUDA
cuDeviceGetCount(&DeviceCount);
if(DeviceCount == 0){
printf("ERROR, ningun dispositivo soporta CUDA\n");
return EXIT_FAILURE;
}
//llamamos al codigo del kernel
primer_kernel<<<1,1,0,0>>>();
printf("Se dispone de %d unidad(es) GPU\n", DeviceCount);
} | code for sm_80
Function : _Z13primer_kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
//device
__global__ void primer_kernel(){}
//host
int main(int argc, char *argv[]){
int DeviceCount = 0;
//inicializamos CUDA
if(cuInit(0) != 0){
printf("ERROR en la inicializacion\n");
exit(0);
}
//obtenemos el numero de dispositivos compatibles con CUDA
cuDeviceGetCount(&DeviceCount);
if(DeviceCount == 0){
printf("ERROR, ningun dispositivo soporta CUDA\n");
return EXIT_FAILURE;
}
//llamamos al codigo del kernel
primer_kernel<<<1,1,0,0>>>();
printf("Se dispone de %d unidad(es) GPU\n", DeviceCount);
} | .file "tmpxft_0010eed5_00000000-6_cuda3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z13primer_kernelvv
.type _Z32__device_stub__Z13primer_kernelvv, @function
_Z32__device_stub__Z13primer_kernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z13primer_kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z13primer_kernelvv, .-_Z32__device_stub__Z13primer_kernelvv
.globl _Z13primer_kernelv
.type _Z13primer_kernelv, @function
_Z13primer_kernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z13primer_kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z13primer_kernelv, .-_Z13primer_kernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "ERROR en la inicializacion\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "ERROR, ningun dispositivo soporta CUDA\n"
.align 8
.LC2:
.string "Se dispone de %d unidad(es) GPU\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0, 12(%rsp)
movl $0, %edi
call cuInit@PLT
testl %eax, %eax
je .L12
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L12:
leaq 12(%rsp), %rdi
call cuDeviceGetCount@PLT
cmpl $0, 12(%rsp)
je .L18
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movl 12(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
.L11:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L20
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L11
.L19:
call _Z32__device_stub__Z13primer_kernelvv
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z13primer_kernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z13primer_kernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
//device
__global__ void primer_kernel(){}
//host
int main(int argc, char *argv[]){
int DeviceCount = 0;
//inicializamos CUDA
if(cuInit(0) != 0){
printf("ERROR en la inicializacion\n");
exit(0);
}
//obtenemos el numero de dispositivos compatibles con CUDA
cuDeviceGetCount(&DeviceCount);
if(DeviceCount == 0){
printf("ERROR, ningun dispositivo soporta CUDA\n");
return EXIT_FAILURE;
}
//llamamos al codigo del kernel
primer_kernel<<<1,1,0,0>>>();
printf("Se dispone de %d unidad(es) GPU\n", DeviceCount);
} | #include <stdio.h>
#include <hip/hip_runtime.h>
//device
__global__ void primer_kernel(){}
//host
int main(int argc, char *argv[]){
int DeviceCount = 0;
//inicializamos CUDA
if(hipInit(0) != 0){
printf("ERROR en la inicializacion\n");
exit(0);
}
//obtenemos el numero de dispositivos compatibles con CUDA
hipGetDeviceCount(&DeviceCount);
if(DeviceCount == 0){
printf("ERROR, ningun dispositivo soporta CUDA\n");
return EXIT_FAILURE;
}
//llamamos al codigo del kernel
primer_kernel<<<1,1,0,0>>>();
printf("Se dispone de %d unidad(es) GPU\n", DeviceCount);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
//device
__global__ void primer_kernel(){}
//host
int main(int argc, char *argv[]){
int DeviceCount = 0;
//inicializamos CUDA
if(hipInit(0) != 0){
printf("ERROR en la inicializacion\n");
exit(0);
}
//obtenemos el numero de dispositivos compatibles con CUDA
hipGetDeviceCount(&DeviceCount);
if(DeviceCount == 0){
printf("ERROR, ningun dispositivo soporta CUDA\n");
return EXIT_FAILURE;
}
//llamamos al codigo del kernel
primer_kernel<<<1,1,0,0>>>();
printf("Se dispone de %d unidad(es) GPU\n", DeviceCount);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13primer_kernelv
.globl _Z13primer_kernelv
.p2align 8
.type _Z13primer_kernelv,@function
_Z13primer_kernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13primer_kernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13primer_kernelv, .Lfunc_end0-_Z13primer_kernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13primer_kernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z13primer_kernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
//device
__global__ void primer_kernel(){}
//host
int main(int argc, char *argv[]){
int DeviceCount = 0;
//inicializamos CUDA
if(hipInit(0) != 0){
printf("ERROR en la inicializacion\n");
exit(0);
}
//obtenemos el numero de dispositivos compatibles con CUDA
hipGetDeviceCount(&DeviceCount);
if(DeviceCount == 0){
printf("ERROR, ningun dispositivo soporta CUDA\n");
return EXIT_FAILURE;
}
//llamamos al codigo del kernel
primer_kernel<<<1,1,0,0>>>();
printf("Se dispone de %d unidad(es) GPU\n", DeviceCount);
} | .text
.file "cuda3.hip"
.globl _Z28__device_stub__primer_kernelv # -- Begin function _Z28__device_stub__primer_kernelv
.p2align 4, 0x90
.type _Z28__device_stub__primer_kernelv,@function
_Z28__device_stub__primer_kernelv: # @_Z28__device_stub__primer_kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z13primer_kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z28__device_stub__primer_kernelv, .Lfunc_end0-_Z28__device_stub__primer_kernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
movl $0, 12(%rsp)
xorl %edi, %edi
callq hipInit
testl %eax, %eax
jne .LBB1_7
# %bb.1:
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 12(%rsp)
je .LBB1_2
# %bb.3:
xorl %ebx, %ebx
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13primer_kernelv, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movl 12(%rsp), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
jmp .LBB1_6
.LBB1_2:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %ebx
.LBB1_6:
movl %ebx, %eax
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_7:
.cfi_def_cfa_offset 96
movl $.Lstr.1, %edi
callq puts@PLT
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13primer_kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13primer_kernelv,@object # @_Z13primer_kernelv
.section .rodata,"a",@progbits
.globl _Z13primer_kernelv
.p2align 3, 0x0
_Z13primer_kernelv:
.quad _Z28__device_stub__primer_kernelv
.size _Z13primer_kernelv, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Se dispone de %d unidad(es) GPU\n"
.size .L.str.2, 33
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13primer_kernelv"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "ERROR, ningun dispositivo soporta CUDA"
.size .Lstr, 39
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "ERROR en la inicializacion"
.size .Lstr.1, 27
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__primer_kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13primer_kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13primer_kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13primer_kernelv
.globl _Z13primer_kernelv
.p2align 8
.type _Z13primer_kernelv,@function
_Z13primer_kernelv:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13primer_kernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13primer_kernelv, .Lfunc_end0-_Z13primer_kernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13primer_kernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z13primer_kernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010eed5_00000000-6_cuda3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z13primer_kernelvv
.type _Z32__device_stub__Z13primer_kernelvv, @function
_Z32__device_stub__Z13primer_kernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z13primer_kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z13primer_kernelvv, .-_Z32__device_stub__Z13primer_kernelvv
.globl _Z13primer_kernelv
.type _Z13primer_kernelv, @function
_Z13primer_kernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z13primer_kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z13primer_kernelv, .-_Z13primer_kernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "ERROR en la inicializacion\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "ERROR, ningun dispositivo soporta CUDA\n"
.align 8
.LC2:
.string "Se dispone de %d unidad(es) GPU\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0, 12(%rsp)
movl $0, %edi
call cuInit@PLT
testl %eax, %eax
je .L12
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L12:
leaq 12(%rsp), %rdi
call cuDeviceGetCount@PLT
cmpl $0, 12(%rsp)
je .L18
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movl 12(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
.L11:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L20
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L11
.L19:
call _Z32__device_stub__Z13primer_kernelvv
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z13primer_kernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z13primer_kernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda3.hip"
.globl _Z28__device_stub__primer_kernelv # -- Begin function _Z28__device_stub__primer_kernelv
.p2align 4, 0x90
.type _Z28__device_stub__primer_kernelv,@function
_Z28__device_stub__primer_kernelv: # @_Z28__device_stub__primer_kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z13primer_kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z28__device_stub__primer_kernelv, .Lfunc_end0-_Z28__device_stub__primer_kernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
movl $0, 12(%rsp)
xorl %edi, %edi
callq hipInit
testl %eax, %eax
jne .LBB1_7
# %bb.1:
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 12(%rsp)
je .LBB1_2
# %bb.3:
xorl %ebx, %ebx
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13primer_kernelv, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movl 12(%rsp), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
jmp .LBB1_6
.LBB1_2:
movl $.Lstr, %edi
callq puts@PLT
movl $1, %ebx
.LBB1_6:
movl %ebx, %eax
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_7:
.cfi_def_cfa_offset 96
movl $.Lstr.1, %edi
callq puts@PLT
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13primer_kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13primer_kernelv,@object # @_Z13primer_kernelv
.section .rodata,"a",@progbits
.globl _Z13primer_kernelv
.p2align 3, 0x0
_Z13primer_kernelv:
.quad _Z28__device_stub__primer_kernelv
.size _Z13primer_kernelv, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Se dispone de %d unidad(es) GPU\n"
.size .L.str.2, 33
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13primer_kernelv"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "ERROR, ningun dispositivo soporta CUDA"
.size .Lstr, 39
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "ERROR en la inicializacion"
.size .Lstr.1, 27
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__primer_kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13primer_kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#define DataSize 1024
// ¨C®æ¬Û¼:(2^8)*(2^8)=2^16,¤@¦C¼¤@¦æ:¦³(2^9)Ó,·s¯x°}¨C®æ:(2^16)*(2^9)=2^25,¦@¦³(2^25)*(2^9)*(2^9)=2^43 < 2^32
__global__ void Add(unsigned long *Da,unsigned long *Db,int high,int width)
{
int tx = threadIdx.x;
int bx = blockIdx.x;
int bn = blockDim.x;
//int gn = gridDim.x;
int id = bx*bn+tx;
//for(int i=id;i<(high*width);i+=(bn*gn))
//Da[i] = 255 - Da[i];
unsigned long tmp = 0;
for (int i = 0; i < 512; i++) { // 512*512ªº¯x°}
tmp += Da[bx*512+i] * Da[i*512+tx];
}
Db[bx*512+tx] = tmp;
__syncthreads();
int i = bn/2; // ¨CÓblock¤ºªºthreads¨Ó°µ
while (i != 0) {
if (tx < i) {
Db[id] += Db[id + i];
}
__syncthreads();
i /= 2;
}
}
int main()
{
FILE *fp = NULL;
unsigned int high, width, offset;
unsigned char *head;
unsigned char *img; // ¥iªí¦ì¤¸¡A1 byte = 8 bits
high = 0;
width = 0;
offset = 0;
fp = fopen("lena.bmp","rb");
fseek(fp, 10, SEEK_SET);
fread(&offset, sizeof(unsigned int), 1, fp);
fseek(fp, 18, SEEK_SET);
fread(&width, sizeof(unsigned int), 1, fp);
fseek(fp, 22, SEEK_SET);
fread(&high, sizeof(unsigned int), 1, fp);
img = (unsigned char*)malloc(sizeof(unsigned char)*(width*high));
fseek(fp, offset, SEEK_SET);
fread(img, sizeof(char), (width*high), fp);
head =(unsigned char*)malloc(sizeof(unsigned char)*(offset));
fseek(fp, 0, SEEK_SET);
fread(head, sizeof(unsigned char), offset, fp);
unsigned int nthread, nblock;
if(width > 1024) { // ¬Û¼nµ¥©ówidth*high¡A¦ýthreadºû«×¤£¯à¶W¹L1024
nthread = 1024;
nblock = width * high / 1024;
} else {
nthread = width;
nblock = high;
}
dim3 block(nthread, 1, 1); // ¤@Óblock¦³1024Óthreads
dim3 grid(nblock, 1, 1); // ¤@Ógrid¦³256Óblock
unsigned long Dimg[512*512]; // CPU
for (int j = 0; j < 512*512; j++) { // °t¸mCPU¯x°}ªÅ¶¡
Dimg[j] = img[j]; // ½T«O¤@Ópixel¤§¹ïÀ³¡A¤Ó¤p´N«e±¸É0¡A¤£·|¦Y¨ì«e±ªºÈ¡A¯u¬O^©ú
}
unsigned long *Da; // GPU¡A4ytes
cudaMalloc((void**)&Da, (sizeof(unsigned long)*(width*high))); // °t¸mGPU¯x°}ªÅ¶¡
cudaMemcpy(Da, Dimg, (sizeof(unsigned long)*(width*high)), cudaMemcpyHostToDevice); //½Æ»s¸ê®Æ¨ìGPU
unsigned long *Db; // GPU¡A4ytes
cudaMalloc((void**)&Db, (sizeof(unsigned long)*(width*high))); // °t¸mGPU¯x°}ªÅ¶¡
Add <<< grid, block >>> (Da,Db,high,width); // ©I¥skernel
cudaThreadSynchronize();
cudaMemcpy(Dimg, Db, (sizeof(unsigned long)*(width*high)), cudaMemcpyDeviceToHost); // ½Æ»s¸ê®Æ(µ²ªG)¦^CPU
fclose(fp);
unsigned long sum = 0;
/*for (int i = 0; i < 512*512; i++) {
sum += Dimg[i];
}*/
for (int i = 0; i < nthread*nblock; i += nthread) {
sum += Dimg[i];
}
sum /= (512*512);
printf("\n%3lu\n", sum);
} | code for sm_80
Function : _Z3AddPmS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R26, c[0x0][0x160] ; /* 0x00005800001a7a02 */
/* 0x000fe20000000f00 */
/*0040*/ CS2R R14, SRZ ; /* 0x00000000000e7805 */
/* 0x000fe2000001ff00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0060*/ MOV R7, c[0x0][0x164] ; /* 0x0000590000077a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ MOV R5, c[0x0][0x0] ; /* 0x0000000000057a02 */
/* 0x000fe20000000f00 */
/*0090*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ MOV R6, c[0x0][0x0] ; /* 0x0000000000067a02 */
/* 0x000fe40000000f00 */
/*00b0*/ SHF.L.U32 R4, R0, 0x9, RZ ; /* 0x0000000900047819 */
/* 0x001fc400000006ff */
/*00c0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe40008000f00 */
/*00d0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc40008000f00 */
/*00e0*/ MOV R27, R7 ; /* 0x00000007001b7202 */
/* 0x000fc60000000f00 */
/*00f0*/ IMAD.WIDE R8, R3, 0x8, R8 ; /* 0x0000000803087825 */
/* 0x002fc800078e0208 */
/*0100*/ IMAD.WIDE R22, R4, 0x8, R26 ; /* 0x0000000804167825 */
/* 0x000fe200078e021a */
/*0110*/ LDG.E.64 R18, [R8.64] ; /* 0x0000000408127981 */
/* 0x000ea8000c1e1b00 */
/*0120*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000ea8000c1e1b00 */
/*0130*/ LDG.E.64 R10, [R22.64+0x8] ; /* 0x00000804160a7981 */
/* 0x000ee8000c1e1b00 */
/*0140*/ LDG.E.64 R16, [R8.64+0x1000] ; /* 0x0010000408107981 */
/* 0x000ee8000c1e1b00 */
/*0150*/ LDG.E.64 R24, [R8.64+0xf000] ; /* 0x00f0000408187981 */
/* 0x000f22000c1e1b00 */
/*0160*/ IMAD R19, R19, R12, RZ ; /* 0x0000000c13137224 */
/* 0x004fc400078e02ff */
/*0170*/ IMAD.WIDE.U32 R14, R18, R12, R14 ; /* 0x0000000c120e7225 */
/* 0x000fc800078e000e */
/*0180*/ IMAD R21, R18, R13, R19 ; /* 0x0000000d12157224 */
/* 0x000fe400078e0213 */
/*0190*/ LDG.E.64 R12, [R22.64+0x10] ; /* 0x00001004160c7981 */
/* 0x000ea8000c1e1b00 */
/*01a0*/ LDG.E.64 R18, [R8.64+0x2000] ; /* 0x0020000408127981 */
/* 0x000ea2000c1e1b00 */
/*01b0*/ IADD3 R15, R15, R21, RZ ; /* 0x000000150f0f7210 */
/* 0x000fe20007ffe0ff */
/*01c0*/ IMAD R17, R17, R10, RZ ; /* 0x0000000a11117224 */
/* 0x008fc800078e02ff */
/*01d0*/ IMAD R21, R16.reuse, R11, R17 ; /* 0x0000000b10157224 */
/* 0x040fe400078e0211 */
/*01e0*/ IMAD.WIDE.U32 R10, R16, R10, R14 ; /* 0x0000000a100a7225 */
/* 0x000fe400078e000e */
/*01f0*/ LDG.E.64 R14, [R22.64+0x18] ; /* 0x00001804160e7981 */
/* 0x000ee8000c1e1b00 */
/*0200*/ LDG.E.64 R16, [R8.64+0x3000] ; /* 0x0030000408107981 */
/* 0x000ee2000c1e1b00 */
/*0210*/ IADD3 R11, R11, R21, RZ ; /* 0x000000150b0b7210 */
/* 0x000fe20007ffe0ff */
/*0220*/ IMAD R19, R19, R12, RZ ; /* 0x0000000c13137224 */
/* 0x004fc800078e02ff */
/*0230*/ IMAD R21, R18.reuse, R13, R19 ; /* 0x0000000d12157224 */
/* 0x040fe400078e0213 */
/*0240*/ IMAD.WIDE.U32 R12, R18, R12, R10 ; /* 0x0000000c120c7225 */
/* 0x000fe400078e000a */
/*0250*/ LDG.E.64 R10, [R22.64+0x20] ; /* 0x00002004160a7981 */
/* 0x000ea8000c1e1b00 */
/*0260*/ LDG.E.64 R18, [R8.64+0x4000] ; /* 0x0040000408127981 */
/* 0x000ea2000c1e1b00 */
/*0270*/ IADD3 R13, R13, R21, RZ ; /* 0x000000150d0d7210 */
/* 0x000fe20007ffe0ff */
/*0280*/ IMAD R17, R17, R14, RZ ; /* 0x0000000e11117224 */
/* 0x008fc800078e02ff */
/*0290*/ IMAD R21, R16.reuse, R15, R17 ; /* 0x0000000f10157224 */
/* 0x040fe400078e0211 */
/*02a0*/ IMAD.WIDE.U32 R14, R16, R14, R12 ; /* 0x0000000e100e7225 */
/* 0x000fe400078e000c */
/*02b0*/ LDG.E.64 R12, [R22.64+0x28] ; /* 0x00002804160c7981 */
/* 0x000ee8000c1e1b00 */
/*02c0*/ LDG.E.64 R16, [R8.64+0x5000] ; /* 0x0050000408107981 */
/* 0x000ee2000c1e1b00 */
/*02d0*/ IADD3 R15, R15, R21, RZ ; /* 0x000000150f0f7210 */
/* 0x000fe20007ffe0ff */
/*02e0*/ IMAD R19, R19, R10, RZ ; /* 0x0000000a13137224 */
/* 0x004fc800078e02ff */
/*02f0*/ IMAD R21, R18.reuse, R11, R19 ; /* 0x0000000b12157224 */
/* 0x040fe400078e0213 */
/*0300*/ IMAD.WIDE.U32 R10, R18, R10, R14 ; /* 0x0000000a120a7225 */
/* 0x000fe400078e000e */
/*0310*/ LDG.E.64 R14, [R22.64+0x30] ; /* 0x00003004160e7981 */
/* 0x000ea8000c1e1b00 */
/*0320*/ LDG.E.64 R18, [R8.64+0x6000] ; /* 0x0060000408127981 */
/* 0x000ea2000c1e1b00 */
/*0330*/ IADD3 R11, R11, R21, RZ ; /* 0x000000150b0b7210 */
/* 0x000fe20007ffe0ff */
/*0340*/ IMAD R17, R17, R12, RZ ; /* 0x0000000c11117224 */
/* 0x008fc800078e02ff */
/*0350*/ IMAD R21, R16.reuse, R13, R17 ; /* 0x0000000d10157224 */
/* 0x040fe400078e0211 */
/*0360*/ IMAD.WIDE.U32 R12, R16, R12, R10 ; /* 0x0000000c100c7225 */
/* 0x000fe400078e000a */
/*0370*/ LDG.E.64 R10, [R22.64+0x38] ; /* 0x00003804160a7981 */
/* 0x000ee8000c1e1b00 */
/*0380*/ LDG.E.64 R16, [R8.64+0x7000] ; /* 0x0070000408107981 */
/* 0x000ee2000c1e1b00 */
/*0390*/ IADD3 R13, R13, R21, RZ ; /* 0x000000150d0d7210 */
/* 0x000fe20007ffe0ff */
/*03a0*/ IMAD R19, R19, R14, RZ ; /* 0x0000000e13137224 */
/* 0x004fc800078e02ff */
/*03b0*/ IMAD R21, R18.reuse, R15, R19 ; /* 0x0000000f12157224 */
/* 0x040fe400078e0213 */
/*03c0*/ IMAD.WIDE.U32 R14, R18, R14, R12 ; /* 0x0000000e120e7225 */
/* 0x000fe400078e000c */
/*03d0*/ LDG.E.64 R12, [R22.64+0x40] ; /* 0x00004004160c7981 */
/* 0x000ea8000c1e1b00 */
/*03e0*/ LDG.E.64 R18, [R8.64+0x8000] ; /* 0x0080000408127981 */
/* 0x000ea2000c1e1b00 */
/*03f0*/ IADD3 R15, R15, R21, RZ ; /* 0x000000150f0f7210 */
/* 0x000fe20007ffe0ff */
/*0400*/ IMAD R17, R17, R10, RZ ; /* 0x0000000a11117224 */
/* 0x008fc800078e02ff */
/*0410*/ IMAD R21, R16.reuse, R11, R17 ; /* 0x0000000b10157224 */
/* 0x040fe400078e0211 */
/*0420*/ IMAD.WIDE.U32 R10, R16, R10, R14 ; /* 0x0000000a100a7225 */
/* 0x000fe400078e000e */
/*0430*/ LDG.E.64 R16, [R22.64+0x48] ; /* 0x0000480416107981 */
/* 0x000ee8000c1e1b00 */
/*0440*/ LDG.E.64 R14, [R8.64+0x9000] ; /* 0x00900004080e7981 */
/* 0x000ee2000c1e1b00 */
/*0450*/ IADD3 R11, R11, R21, RZ ; /* 0x000000150b0b7210 */
/* 0x000fe20007ffe0ff */
/*0460*/ IMAD R19, R19, R12, RZ ; /* 0x0000000c13137224 */
/* 0x004fc800078e02ff */
/*0470*/ IMAD R21, R18.reuse, R13, R19 ; /* 0x0000000d12157224 */
/* 0x040fe400078e0213 */
/*0480*/ IMAD.WIDE.U32 R12, R18, R12, R10 ; /* 0x0000000c120c7225 */
/* 0x000fe400078e000a */
/*0490*/ LDG.E.64 R10, [R22.64+0x50] ; /* 0x00005004160a7981 */
/* 0x000ea8000c1e1b00 */
/*04a0*/ LDG.E.64 R18, [R8.64+0xa000] ; /* 0x00a0000408127981 */
/* 0x000ea2000c1e1b00 */
/*04b0*/ IADD3 R13, R13, R21, RZ ; /* 0x000000150d0d7210 */
/* 0x000fe20007ffe0ff */
/*04c0*/ IMAD R15, R15, R16, RZ ; /* 0x000000100f0f7224 */
/* 0x008fc800078e02ff */
/*04d0*/ IMAD R21, R14.reuse, R17, R15 ; /* 0x000000110e157224 */
/* 0x040fe400078e020f */
/*04e0*/ IMAD.WIDE.U32 R16, R14, R16, R12 ; /* 0x000000100e107225 */
/* 0x000fe400078e000c */
/*04f0*/ LDG.E.64 R14, [R22.64+0x58] ; /* 0x00005804160e7981 */
/* 0x000ee8000c1e1b00 */
/*0500*/ LDG.E.64 R12, [R8.64+0xb000] ; /* 0x00b00004080c7981 */
/* 0x000ee2000c1e1b00 */
/*0510*/ IADD3 R17, R17, R21, RZ ; /* 0x0000001511117210 */
/* 0x000fe20007ffe0ff */
/*0520*/ IMAD R19, R19, R10, RZ ; /* 0x0000000a13137224 */
/* 0x004fc800078e02ff */
/*0530*/ IMAD R21, R18.reuse, R11, R19 ; /* 0x0000000b12157224 */
/* 0x040fe400078e0213 */
/*0540*/ IMAD.WIDE.U32 R10, R18, R10, R16 ; /* 0x0000000a120a7225 */
/* 0x000fe400078e0010 */
/*0550*/ LDG.E.64 R16, [R22.64+0x60] ; /* 0x0000600416107981 */
/* 0x000ea8000c1e1b00 */
/*0560*/ LDG.E.64 R18, [R8.64+0xc000] ; /* 0x00c0000408127981 */
/* 0x000ea2000c1e1b00 */
/*0570*/ IADD3 R11, R11, R21, RZ ; /* 0x000000150b0b7210 */
/* 0x000fe20007ffe0ff */
/*0580*/ IMAD R13, R13, R14, RZ ; /* 0x0000000e0d0d7224 */
/* 0x008fc800078e02ff */
/*0590*/ IMAD R21, R12.reuse, R15, R13 ; /* 0x0000000f0c157224 */
/* 0x040fe400078e020d */
/*05a0*/ IMAD.WIDE.U32 R14, R12, R14, R10 ; /* 0x0000000e0c0e7225 */
/* 0x000fe400078e000a */
/*05b0*/ LDG.E.64 R10, [R22.64+0x68] ; /* 0x00006804160a7981 */
/* 0x000ee8000c1e1b00 */
/*05c0*/ LDG.E.64 R12, [R8.64+0xd000] ; /* 0x00d00004080c7981 */
/* 0x000ee2000c1e1b00 */
/*05d0*/ IADD3 R15, R15, R21, RZ ; /* 0x000000150f0f7210 */
/* 0x000fc60007ffe0ff */
/*05e0*/ LDG.E.64 R20, [R22.64+0x78] ; /* 0x0000780416147981 */
/* 0x000f22000c1e1b00 */
/*05f0*/ IMAD R27, R19, R16.reuse, RZ ; /* 0x00000010131b7224 */
/* 0x084fe400078e02ff */
/*0600*/ IMAD.WIDE.U32 R14, R18, R16, R14 ; /* 0x00000010120e7225 */
/* 0x000fc800078e000e */
/*0610*/ IMAD R27, R18, R17, R27 ; /* 0x00000011121b7224 */
/* 0x000fe400078e021b */
/*0620*/ LDG.E.64 R16, [R22.64+0x70] ; /* 0x0000700416107981 */
/* 0x000ea8000c1e1b00 */
/*0630*/ LDG.E.64 R18, [R8.64+0xe000] ; /* 0x00e0000408127981 */
/* 0x0008a2000c1e1b00 */
/*0640*/ IADD3 R15, R15, R27, RZ ; /* 0x0000001b0f0f7210 */
/* 0x000fe20007ffe0ff */
/*0650*/ IMAD R13, R13, R10, RZ ; /* 0x0000000a0d0d7224 */
/* 0x008fc800078e02ff */
/*0660*/ IMAD R13, R12.reuse, R11, R13 ; /* 0x0000000b0c0d7224 */
/* 0x040fe400078e020d */
/*0670*/ IMAD.WIDE.U32 R10, R12, R10, R14 ; /* 0x0000000a0c0a7225 */
/* 0x000fe200078e000e */
/*0680*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fc80007ffe0ff */
/*0690*/ IADD3 R11, R11, R13, RZ ; /* 0x0000000d0b0b7210 */
/* 0x000fe40007ffe0ff */
/*06a0*/ ISETP.NE.AND P0, PT, R2, 0x200, PT ; /* 0x000002000200780c */
/* 0x000fe20003f05270 */
/*06b0*/ IMAD R9, R25, R20, RZ ; /* 0x0000001419097224 */
/* 0x010fe200078e02ff */
/*06c0*/ UIADD3 UR6, UP0, UR6, 0x10000, URZ ; /* 0x0001000006067890 */
/* 0x000fe2000ff1e03f */
/*06d0*/ IADD3 R26, P1, R26, 0x80, RZ ; /* 0x000000801a1a7810 */
/* 0x000fe40007f3e0ff */
/*06e0*/ IMAD R9, R24, R21, R9 ; /* 0x0000001518097224 */
/* 0x000fe200078e0209 */
/*06f0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0700*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0710*/ IMAD R13, R19, R16, RZ ; /* 0x00000010130d7224 */
/* 0x004fc400078e02ff */
/*0720*/ IMAD.WIDE.U32 R10, R18, R16, R10 ; /* 0x00000010120a7225 */
/* 0x000fc800078e000a */
/*0730*/ IMAD R13, R18, R17, R13 ; /* 0x00000011120d7224 */
/* 0x000fca00078e020d */
/*0740*/ IADD3 R11, R11, R13, RZ ; /* 0x0000000d0b0b7210 */
/* 0x000fca0007ffe0ff */
/*0750*/ IMAD.WIDE.U32 R14, R24, R20, R10 ; /* 0x00000014180e7225 */
/* 0x000fca00078e000a */
/*0760*/ IADD3 R15, R15, R9, RZ ; /* 0x000000090f0f7210 */
/* 0x000fe20007ffe0ff */
/*0770*/ @P0 BRA 0xc0 ; /* 0xfffff94000000947 */
/* 0x000fea000383ffff */
/*0780*/ IADD3 R4, R4, R3, RZ ; /* 0x0000000304047210 */
/* 0x000fe40007ffe0ff */
/*0790*/ MOV R7, 0x8 ; /* 0x0000000800077802 */
/* 0x000fe40000000f00 */
/*07a0*/ IADD3 R2, R5, 0x1, RZ ; /* 0x0000000105027810 */
/* 0x000fc60007ffe0ff */
/*07b0*/ IMAD.WIDE R4, R4, R7, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0207 */
/*07c0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fc80003f06070 */
/*07d0*/ STG.E.64 [R4.64], R14 ; /* 0x0000000e04007986 */
/* 0x0001e8000c101b04 */
/*07e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*07f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0800*/ IMAD R4, R0, c[0x0][0x0], R3 ; /* 0x0000000000047a24 */
/* 0x001fc800078e0203 */
/*0810*/ IMAD.WIDE R4, R4, R7, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0207 */
/*0820*/ LEA.HI R6, R6, R6, RZ, 0x1 ; /* 0x0000000606067211 */
/* 0x000fe200078f08ff */
/*0830*/ BSSY B0, 0x8e0 ; /* 0x000000a000007945 */
/* 0x000fe60003800000 */
/*0840*/ SHF.R.S32.HI R6, RZ, 0x1, R6 ; /* 0x00000001ff067819 */
/* 0x000fc80000011406 */
/*0850*/ ISETP.GE.AND P0, PT, R3, R6, PT ; /* 0x000000060300720c */
/* 0x000fda0003f06270 */
/*0860*/ @P0 BRA 0x8d0 ; /* 0x0000006000000947 */
/* 0x001fea0003800000 */
/*0870*/ IMAD.WIDE R8, R6, 0x8, R4 ; /* 0x0000000806087825 */
/* 0x000fe200078e0204 */
/*0880*/ LDG.E.64 R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000eaa000c1e1b00 */
/*0890*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea4000c1e1b00 */
/*08a0*/ IADD3 R10, P0, R10, R8, RZ ; /* 0x000000080a0a7210 */
/* 0x004fc80007f1e0ff */
/*08b0*/ IADD3.X R11, R11, R9, RZ, P0, !PT ; /* 0x000000090b0b7210 */
/* 0x000fca00007fe4ff */
/*08c0*/ STG.E.64 [R4.64], R10 ; /* 0x0000000a04007986 */
/* 0x0001e8000c101b04 */
/*08d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08e0*/ IADD3 R0, R6, 0x1, RZ ; /* 0x0000000106007810 */
/* 0x000fe20007ffe0ff */
/*08f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0900*/ ISETP.GT.U32.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fda0003f04070 */
/*0910*/ @P0 BRA 0x820 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*0920*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0930*/ BRA 0x930; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#define DataSize 1024
// ¨C®æ¬Û¼:(2^8)*(2^8)=2^16,¤@¦C¼¤@¦æ:¦³(2^9)Ó,·s¯x°}¨C®æ:(2^16)*(2^9)=2^25,¦@¦³(2^25)*(2^9)*(2^9)=2^43 < 2^32
__global__ void Add(unsigned long *Da,unsigned long *Db,int high,int width)
{
int tx = threadIdx.x;
int bx = blockIdx.x;
int bn = blockDim.x;
//int gn = gridDim.x;
int id = bx*bn+tx;
//for(int i=id;i<(high*width);i+=(bn*gn))
//Da[i] = 255 - Da[i];
unsigned long tmp = 0;
for (int i = 0; i < 512; i++) { // 512*512ªº¯x°}
tmp += Da[bx*512+i] * Da[i*512+tx];
}
Db[bx*512+tx] = tmp;
__syncthreads();
int i = bn/2; // ¨CÓblock¤ºªºthreads¨Ó°µ
while (i != 0) {
if (tx < i) {
Db[id] += Db[id + i];
}
__syncthreads();
i /= 2;
}
}
int main()
{
FILE *fp = NULL;
unsigned int high, width, offset;
unsigned char *head;
unsigned char *img; // ¥iªí¦ì¤¸¡A1 byte = 8 bits
high = 0;
width = 0;
offset = 0;
fp = fopen("lena.bmp","rb");
fseek(fp, 10, SEEK_SET);
fread(&offset, sizeof(unsigned int), 1, fp);
fseek(fp, 18, SEEK_SET);
fread(&width, sizeof(unsigned int), 1, fp);
fseek(fp, 22, SEEK_SET);
fread(&high, sizeof(unsigned int), 1, fp);
img = (unsigned char*)malloc(sizeof(unsigned char)*(width*high));
fseek(fp, offset, SEEK_SET);
fread(img, sizeof(char), (width*high), fp);
head =(unsigned char*)malloc(sizeof(unsigned char)*(offset));
fseek(fp, 0, SEEK_SET);
fread(head, sizeof(unsigned char), offset, fp);
unsigned int nthread, nblock;
if(width > 1024) { // ¬Û¼nµ¥©ówidth*high¡A¦ýthreadºû«×¤£¯à¶W¹L1024
nthread = 1024;
nblock = width * high / 1024;
} else {
nthread = width;
nblock = high;
}
dim3 block(nthread, 1, 1); // ¤@Óblock¦³1024Óthreads
dim3 grid(nblock, 1, 1); // ¤@Ógrid¦³256Óblock
unsigned long Dimg[512*512]; // CPU
for (int j = 0; j < 512*512; j++) { // °t¸mCPU¯x°}ªÅ¶¡
Dimg[j] = img[j]; // ½T«O¤@Ópixel¤§¹ïÀ³¡A¤Ó¤p´N«e±¸É0¡A¤£·|¦Y¨ì«e±ªºÈ¡A¯u¬O^©ú
}
unsigned long *Da; // GPU¡A4ytes
cudaMalloc((void**)&Da, (sizeof(unsigned long)*(width*high))); // °t¸mGPU¯x°}ªÅ¶¡
cudaMemcpy(Da, Dimg, (sizeof(unsigned long)*(width*high)), cudaMemcpyHostToDevice); //½Æ»s¸ê®Æ¨ìGPU
unsigned long *Db; // GPU¡A4ytes
cudaMalloc((void**)&Db, (sizeof(unsigned long)*(width*high))); // °t¸mGPU¯x°}ªÅ¶¡
Add <<< grid, block >>> (Da,Db,high,width); // ©I¥skernel
cudaThreadSynchronize();
cudaMemcpy(Dimg, Db, (sizeof(unsigned long)*(width*high)), cudaMemcpyDeviceToHost); // ½Æ»s¸ê®Æ(µ²ªG)¦^CPU
fclose(fp);
unsigned long sum = 0;
/*for (int i = 0; i < 512*512; i++) {
sum += Dimg[i];
}*/
for (int i = 0; i < nthread*nblock; i += nthread) {
sum += Dimg[i];
}
sum /= (512*512);
printf("\n%3lu\n", sum);
} | .file "tmpxft_0009af96_00000000-6_hw5.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3AddPmS_iiPmS_ii
.type _Z26__device_stub__Z3AddPmS_iiPmS_ii, @function
_Z26__device_stub__Z3AddPmS_iiPmS_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3AddPmS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3AddPmS_iiPmS_ii, .-_Z26__device_stub__Z3AddPmS_iiPmS_ii
.globl _Z3AddPmS_ii
.type _Z3AddPmS_ii, @function
_Z3AddPmS_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3AddPmS_iiPmS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3AddPmS_ii, .-_Z3AddPmS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "rb"
.LC1:
.string "lena.bmp"
.LC2:
.string "\n%3lu\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
leaq -2097152(%rsp), %r11
.cfi_def_cfa 11, 2097192
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $88, %rsp
.cfi_def_cfa_offset 2097280
movq %fs:40, %rax
movq %rax, 2097224(%rsp)
xorl %eax, %eax
movl $0, 12(%rsp)
movl $0, 16(%rsp)
movl $0, 20(%rsp)
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %r13
movl $0, %edx
movl $10, %esi
movq %rax, %rdi
call fseek@PLT
leaq 20(%rsp), %rdi
movq %r13, %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
movl $0, %edx
movl $18, %esi
movq %r13, %rdi
call fseek@PLT
leaq 16(%rsp), %rdi
movq %r13, %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
movl $0, %edx
movl $22, %esi
movq %r13, %rdi
call fseek@PLT
leaq 12(%rsp), %rdi
movq %r13, %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
movl 16(%rsp), %ebp
imull 12(%rsp), %ebp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
movl 20(%rsp), %esi
movl $0, %edx
movq %r13, %rdi
call fseek@PLT
movl 16(%rsp), %ecx
imull 12(%rsp), %ecx
movq %r13, %r8
movl $1, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call __fread_chk@PLT
movl 20(%rsp), %r12d
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movl $0, %edx
movl $0, %esi
movq %r13, %rdi
call fseek@PLT
movl 20(%rsp), %ecx
movq %r13, %r8
movl $1, %edx
movq %r12, %rsi
movq %rbp, %rdi
call __fread_chk@PLT
movl 16(%rsp), %ecx
cmpl $1024, %ecx
jbe .L12
movl %ecx, %esi
imull 12(%rsp), %esi
shrl $10, %esi
movl %esi, %r12d
movl $1024, %ebp
.L13:
movl %ebp, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl %r12d, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %eax
.L14:
movzbl (%rbx,%rax), %edx
movq %rdx, 64(%rsp,%rax,8)
addq $1, %rax
cmpq $262144, %rax
jne .L14
imull 12(%rsp), %ecx
leaq 0(,%rcx,8), %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movl 16(%rsp), %edx
imull 12(%rsp), %edx
salq $3, %rdx
leaq 64(%rsp), %rsi
movl $1, %ecx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl 16(%rsp), %esi
imull 12(%rsp), %esi
salq $3, %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
movl 48(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movq 52(%rsp), %rdi
movl 60(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L15:
call cudaThreadSynchronize@PLT
movl 16(%rsp), %edx
imull 12(%rsp), %edx
salq $3, %rdx
leaq 64(%rsp), %rdi
movl $2, %ecx
movq 32(%rsp), %rsi
call cudaMemcpy@PLT
movq %r13, %rdi
call fclose@PLT
movl %r12d, %esi
imull %ebp, %esi
testl %esi, %esi
je .L19
movl $0, %ecx
movl $0, %edx
movl $0, %eax
.L17:
movslq %ecx, %rcx
addq 64(%rsp,%rcx,8), %rdx
addl %ebp, %eax
movl %eax, %ecx
cmpl %esi, %eax
jb .L17
.L16:
shrq $18, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 2097224(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $2097240, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movl 12(%rsp), %r12d
movl %ecx, %ebp
jmp .L13
.L23:
movl 16(%rsp), %ecx
movl 12(%rsp), %edx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z26__device_stub__Z3AddPmS_iiPmS_ii
jmp .L15
.L19:
movl $0, %edx
jmp .L16
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z3AddPmS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z3AddPmS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#define DataSize 1024
// ¨C®æ¬Û¼:(2^8)*(2^8)=2^16,¤@¦C¼¤@¦æ:¦³(2^9)Ó,·s¯x°}¨C®æ:(2^16)*(2^9)=2^25,¦@¦³(2^25)*(2^9)*(2^9)=2^43 < 2^32
__global__ void Add(unsigned long *Da,unsigned long *Db,int high,int width)
{
int tx = threadIdx.x;
int bx = blockIdx.x;
int bn = blockDim.x;
//int gn = gridDim.x;
int id = bx*bn+tx;
//for(int i=id;i<(high*width);i+=(bn*gn))
//Da[i] = 255 - Da[i];
unsigned long tmp = 0;
for (int i = 0; i < 512; i++) { // 512*512ªº¯x°}
tmp += Da[bx*512+i] * Da[i*512+tx];
}
Db[bx*512+tx] = tmp;
__syncthreads();
int i = bn/2; // ¨CÓblock¤ºªºthreads¨Ó°µ
while (i != 0) {
if (tx < i) {
Db[id] += Db[id + i];
}
__syncthreads();
i /= 2;
}
}
int main()
{
FILE *fp = NULL;
unsigned int high, width, offset;
unsigned char *head;
unsigned char *img; // ¥iªí¦ì¤¸¡A1 byte = 8 bits
high = 0;
width = 0;
offset = 0;
fp = fopen("lena.bmp","rb");
fseek(fp, 10, SEEK_SET);
fread(&offset, sizeof(unsigned int), 1, fp);
fseek(fp, 18, SEEK_SET);
fread(&width, sizeof(unsigned int), 1, fp);
fseek(fp, 22, SEEK_SET);
fread(&high, sizeof(unsigned int), 1, fp);
img = (unsigned char*)malloc(sizeof(unsigned char)*(width*high));
fseek(fp, offset, SEEK_SET);
fread(img, sizeof(char), (width*high), fp);
head =(unsigned char*)malloc(sizeof(unsigned char)*(offset));
fseek(fp, 0, SEEK_SET);
fread(head, sizeof(unsigned char), offset, fp);
unsigned int nthread, nblock;
if(width > 1024) { // ¬Û¼nµ¥©ówidth*high¡A¦ýthreadºû«×¤£¯à¶W¹L1024
nthread = 1024;
nblock = width * high / 1024;
} else {
nthread = width;
nblock = high;
}
dim3 block(nthread, 1, 1); // ¤@Óblock¦³1024Óthreads
dim3 grid(nblock, 1, 1); // ¤@Ógrid¦³256Óblock
unsigned long Dimg[512*512]; // CPU
for (int j = 0; j < 512*512; j++) { // °t¸mCPU¯x°}ªÅ¶¡
Dimg[j] = img[j]; // ½T«O¤@Ópixel¤§¹ïÀ³¡A¤Ó¤p´N«e±¸É0¡A¤£·|¦Y¨ì«e±ªºÈ¡A¯u¬O^©ú
}
unsigned long *Da; // GPU¡A4ytes
cudaMalloc((void**)&Da, (sizeof(unsigned long)*(width*high))); // °t¸mGPU¯x°}ªÅ¶¡
cudaMemcpy(Da, Dimg, (sizeof(unsigned long)*(width*high)), cudaMemcpyHostToDevice); //½Æ»s¸ê®Æ¨ìGPU
unsigned long *Db; // GPU¡A4ytes
cudaMalloc((void**)&Db, (sizeof(unsigned long)*(width*high))); // °t¸mGPU¯x°}ªÅ¶¡
Add <<< grid, block >>> (Da,Db,high,width); // ©I¥skernel
cudaThreadSynchronize();
cudaMemcpy(Dimg, Db, (sizeof(unsigned long)*(width*high)), cudaMemcpyDeviceToHost); // ½Æ»s¸ê®Æ(µ²ªG)¦^CPU
fclose(fp);
unsigned long sum = 0;
/*for (int i = 0; i < 512*512; i++) {
sum += Dimg[i];
}*/
for (int i = 0; i < nthread*nblock; i += nthread) {
sum += Dimg[i];
}
sum /= (512*512);
printf("\n%3lu\n", sum);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define DataSize 1024
// ¨C®æ¬Û¼:(2^8)*(2^8)=2^16,¤@¦C¼¤@¦æ:¦³(2^9)Ó,·s¯x°}¨C®æ:(2^16)*(2^9)=2^25,¦@¦³(2^25)*(2^9)*(2^9)=2^43 < 2^32
__global__ void Add(unsigned long *Da,unsigned long *Db,int high,int width)
{
int tx = threadIdx.x;
int bx = blockIdx.x;
int bn = blockDim.x;
//int gn = gridDim.x;
int id = bx*bn+tx;
//for(int i=id;i<(high*width);i+=(bn*gn))
//Da[i] = 255 - Da[i];
unsigned long tmp = 0;
for (int i = 0; i < 512; i++) { // 512*512ªº¯x°}
tmp += Da[bx*512+i] * Da[i*512+tx];
}
Db[bx*512+tx] = tmp;
__syncthreads();
int i = bn/2; // ¨CÓblock¤ºªºthreads¨Ó°µ
while (i != 0) {
if (tx < i) {
Db[id] += Db[id + i];
}
__syncthreads();
i /= 2;
}
}
int main()
{
FILE *fp = NULL;
unsigned int high, width, offset;
unsigned char *head;
unsigned char *img; // ¥iªí¦ì¤¸¡A1 byte = 8 bits
high = 0;
width = 0;
offset = 0;
fp = fopen("lena.bmp","rb");
fseek(fp, 10, SEEK_SET);
fread(&offset, sizeof(unsigned int), 1, fp);
fseek(fp, 18, SEEK_SET);
fread(&width, sizeof(unsigned int), 1, fp);
fseek(fp, 22, SEEK_SET);
fread(&high, sizeof(unsigned int), 1, fp);
img = (unsigned char*)malloc(sizeof(unsigned char)*(width*high));
fseek(fp, offset, SEEK_SET);
fread(img, sizeof(char), (width*high), fp);
head =(unsigned char*)malloc(sizeof(unsigned char)*(offset));
fseek(fp, 0, SEEK_SET);
fread(head, sizeof(unsigned char), offset, fp);
unsigned int nthread, nblock;
if(width > 1024) { // ¬Û¼nµ¥©ówidth*high¡A¦ýthreadºû«×¤£¯à¶W¹L1024
nthread = 1024;
nblock = width * high / 1024;
} else {
nthread = width;
nblock = high;
}
dim3 block(nthread, 1, 1); // ¤@Óblock¦³1024Óthreads
dim3 grid(nblock, 1, 1); // ¤@Ógrid¦³256Óblock
unsigned long Dimg[512*512]; // CPU
for (int j = 0; j < 512*512; j++) { // °t¸mCPU¯x°}ªÅ¶¡
Dimg[j] = img[j]; // ½T«O¤@Ópixel¤§¹ïÀ³¡A¤Ó¤p´N«e±¸É0¡A¤£·|¦Y¨ì«e±ªºÈ¡A¯u¬O^©ú
}
unsigned long *Da; // GPU¡A4ytes
hipMalloc((void**)&Da, (sizeof(unsigned long)*(width*high))); // °t¸mGPU¯x°}ªÅ¶¡
hipMemcpy(Da, Dimg, (sizeof(unsigned long)*(width*high)), hipMemcpyHostToDevice); //½Æ»s¸ê®Æ¨ìGPU
unsigned long *Db; // GPU¡A4ytes
hipMalloc((void**)&Db, (sizeof(unsigned long)*(width*high))); // °t¸mGPU¯x°}ªÅ¶¡
Add <<< grid, block >>> (Da,Db,high,width); // ©I¥skernel
hipDeviceSynchronize();
hipMemcpy(Dimg, Db, (sizeof(unsigned long)*(width*high)), hipMemcpyDeviceToHost); // ½Æ»s¸ê®Æ(µ²ªG)¦^CPU
fclose(fp);
unsigned long sum = 0;
/*for (int i = 0; i < 512*512; i++) {
sum += Dimg[i];
}*/
for (int i = 0; i < nthread*nblock; i += nthread) {
sum += Dimg[i];
}
sum /= (512*512);
printf("\n%3lu\n", sum);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define DataSize 1024
// ¨C®æ¬Û¼:(2^8)*(2^8)=2^16,¤@¦C¼¤@¦æ:¦³(2^9)Ó,·s¯x°}¨C®æ:(2^16)*(2^9)=2^25,¦@¦³(2^25)*(2^9)*(2^9)=2^43 < 2^32
__global__ void Add(unsigned long *Da,unsigned long *Db,int high,int width)
{
int tx = threadIdx.x;
int bx = blockIdx.x;
int bn = blockDim.x;
//int gn = gridDim.x;
int id = bx*bn+tx;
//for(int i=id;i<(high*width);i+=(bn*gn))
//Da[i] = 255 - Da[i];
unsigned long tmp = 0;
for (int i = 0; i < 512; i++) { // 512*512ªº¯x°}
tmp += Da[bx*512+i] * Da[i*512+tx];
}
Db[bx*512+tx] = tmp;
__syncthreads();
int i = bn/2; // ¨CÓblock¤ºªºthreads¨Ó°µ
while (i != 0) {
if (tx < i) {
Db[id] += Db[id + i];
}
__syncthreads();
i /= 2;
}
}
int main()
{
FILE *fp = NULL;
unsigned int high, width, offset;
unsigned char *head;
unsigned char *img; // ¥iªí¦ì¤¸¡A1 byte = 8 bits
high = 0;
width = 0;
offset = 0;
fp = fopen("lena.bmp","rb");
fseek(fp, 10, SEEK_SET);
fread(&offset, sizeof(unsigned int), 1, fp);
fseek(fp, 18, SEEK_SET);
fread(&width, sizeof(unsigned int), 1, fp);
fseek(fp, 22, SEEK_SET);
fread(&high, sizeof(unsigned int), 1, fp);
img = (unsigned char*)malloc(sizeof(unsigned char)*(width*high));
fseek(fp, offset, SEEK_SET);
fread(img, sizeof(char), (width*high), fp);
head =(unsigned char*)malloc(sizeof(unsigned char)*(offset));
fseek(fp, 0, SEEK_SET);
fread(head, sizeof(unsigned char), offset, fp);
unsigned int nthread, nblock;
if(width > 1024) { // ¬Û¼nµ¥©ówidth*high¡A¦ýthreadºû«×¤£¯à¶W¹L1024
nthread = 1024;
nblock = width * high / 1024;
} else {
nthread = width;
nblock = high;
}
dim3 block(nthread, 1, 1); // ¤@Óblock¦³1024Óthreads
dim3 grid(nblock, 1, 1); // ¤@Ógrid¦³256Óblock
unsigned long Dimg[512*512]; // CPU
for (int j = 0; j < 512*512; j++) { // °t¸mCPU¯x°}ªÅ¶¡
Dimg[j] = img[j]; // ½T«O¤@Ópixel¤§¹ïÀ³¡A¤Ó¤p´N«e±¸É0¡A¤£·|¦Y¨ì«e±ªºÈ¡A¯u¬O^©ú
}
unsigned long *Da; // GPU¡A4ytes
hipMalloc((void**)&Da, (sizeof(unsigned long)*(width*high))); // °t¸mGPU¯x°}ªÅ¶¡
hipMemcpy(Da, Dimg, (sizeof(unsigned long)*(width*high)), hipMemcpyHostToDevice); //½Æ»s¸ê®Æ¨ìGPU
unsigned long *Db; // GPU¡A4ytes
hipMalloc((void**)&Db, (sizeof(unsigned long)*(width*high))); // °t¸mGPU¯x°}ªÅ¶¡
Add <<< grid, block >>> (Da,Db,high,width); // ©I¥skernel
hipDeviceSynchronize();
hipMemcpy(Dimg, Db, (sizeof(unsigned long)*(width*high)), hipMemcpyDeviceToHost); // ½Æ»s¸ê®Æ(µ²ªG)¦^CPU
fclose(fp);
unsigned long sum = 0;
/*for (int i = 0; i < 512*512; i++) {
sum += Dimg[i];
}*/
for (int i = 0; i < nthread*nblock; i += nthread) {
sum += Dimg[i];
}
sum /= (512*512);
printf("\n%3lu\n", sum);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3AddPmS_ii
.globl _Z3AddPmS_ii
.p2align 8
.type _Z3AddPmS_ii,@function
_Z3AddPmS_ii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s4, s[0:1], 0x24
v_lshlrev_b32_e32 v1, 3, v0
s_lshl_b32 s6, s15, 9
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v6, 0
s_ashr_i32 s7, s6, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_lshl_b64 s[6:7], s[6:7], 3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, s5, s2, v1
v_add_co_ci_u32_e64 v2, null, s3, 0, s5
s_add_u32 s5, s2, s6
s_addc_u32 s6, s3, s7
s_mov_b64 s[2:3], 0
.p2align 6
.LBB0_1:
global_load_b64 v[7:8], v[1:2], off
s_add_u32 s8, s5, s2
s_addc_u32 s9, s6, s3
v_add_co_u32 v1, vcc_lo, v1, 0x1000
s_load_b64 s[8:9], s[8:9], 0x0
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_add_u32 s2, s2, 8
s_addc_u32 s3, s3, 0
s_cmpk_eq_i32 s2, 0x1000
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mul_lo_u32 v9, v7, s9
v_mul_lo_u32 v8, v8, s8
v_mad_u64_u32 v[3:4], null, v7, s8, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v4, v8, v4, v9
v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
s_cbranch_scc0 .LBB0_1
s_load_b64 s[0:1], s[0:1], 0x8
v_lshl_add_u32 v1, s15, 9, v0
v_cmp_lt_u16_e64 s2, s4, 2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_and_b32 vcc_lo, exec_lo, s2
global_store_b64 v[1:2], v[3:4], off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB0_7
s_and_b32 s2, 0xffff, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s4
s_cmp_gt_u32 s2, 3
s_mov_b32 s2, s3
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_7
.LBB0_5:
s_lshr_b32 s3, s2, 1
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB0_4
v_add_nc_u32_e32 v4, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 3, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_clause 0x1
global_load_b64 v[4:5], v[4:5], off
global_load_b64 v[6:7], v[2:3], off
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, v7, v5, vcc_lo
global_store_b64 v[2:3], v[4:5], off
s_branch .LBB0_4
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3AddPmS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3AddPmS_ii, .Lfunc_end0-_Z3AddPmS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3AddPmS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3AddPmS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define DataSize 1024
// ¨C®æ¬Û¼:(2^8)*(2^8)=2^16,¤@¦C¼¤@¦æ:¦³(2^9)Ó,·s¯x°}¨C®æ:(2^16)*(2^9)=2^25,¦@¦³(2^25)*(2^9)*(2^9)=2^43 < 2^32
__global__ void Add(unsigned long *Da,unsigned long *Db,int high,int width)
{
int tx = threadIdx.x;
int bx = blockIdx.x;
int bn = blockDim.x;
//int gn = gridDim.x;
int id = bx*bn+tx;
//for(int i=id;i<(high*width);i+=(bn*gn))
//Da[i] = 255 - Da[i];
unsigned long tmp = 0;
for (int i = 0; i < 512; i++) { // 512*512ªº¯x°}
tmp += Da[bx*512+i] * Da[i*512+tx];
}
Db[bx*512+tx] = tmp;
__syncthreads();
int i = bn/2; // ¨CÓblock¤ºªºthreads¨Ó°µ
while (i != 0) {
if (tx < i) {
Db[id] += Db[id + i];
}
__syncthreads();
i /= 2;
}
}
int main()
{
FILE *fp = NULL;
unsigned int high, width, offset;
unsigned char *head;
unsigned char *img; // ¥iªí¦ì¤¸¡A1 byte = 8 bits
high = 0;
width = 0;
offset = 0;
fp = fopen("lena.bmp","rb");
fseek(fp, 10, SEEK_SET);
fread(&offset, sizeof(unsigned int), 1, fp);
fseek(fp, 18, SEEK_SET);
fread(&width, sizeof(unsigned int), 1, fp);
fseek(fp, 22, SEEK_SET);
fread(&high, sizeof(unsigned int), 1, fp);
img = (unsigned char*)malloc(sizeof(unsigned char)*(width*high));
fseek(fp, offset, SEEK_SET);
fread(img, sizeof(char), (width*high), fp);
head =(unsigned char*)malloc(sizeof(unsigned char)*(offset));
fseek(fp, 0, SEEK_SET);
fread(head, sizeof(unsigned char), offset, fp);
unsigned int nthread, nblock;
if(width > 1024) { // ¬Û¼nµ¥©ówidth*high¡A¦ýthreadºû«×¤£¯à¶W¹L1024
nthread = 1024;
nblock = width * high / 1024;
} else {
nthread = width;
nblock = high;
}
dim3 block(nthread, 1, 1); // ¤@Óblock¦³1024Óthreads
dim3 grid(nblock, 1, 1); // ¤@Ógrid¦³256Óblock
unsigned long Dimg[512*512]; // CPU
for (int j = 0; j < 512*512; j++) { // °t¸mCPU¯x°}ªÅ¶¡
Dimg[j] = img[j]; // ½T«O¤@Ópixel¤§¹ïÀ³¡A¤Ó¤p´N«e±¸É0¡A¤£·|¦Y¨ì«e±ªºÈ¡A¯u¬O^©ú
}
unsigned long *Da; // GPU¡A4ytes
hipMalloc((void**)&Da, (sizeof(unsigned long)*(width*high))); // °t¸mGPU¯x°}ªÅ¶¡
hipMemcpy(Da, Dimg, (sizeof(unsigned long)*(width*high)), hipMemcpyHostToDevice); //½Æ»s¸ê®Æ¨ìGPU
unsigned long *Db; // GPU¡A4ytes
hipMalloc((void**)&Db, (sizeof(unsigned long)*(width*high))); // °t¸mGPU¯x°}ªÅ¶¡
Add <<< grid, block >>> (Da,Db,high,width); // ©I¥skernel
hipDeviceSynchronize();
hipMemcpy(Dimg, Db, (sizeof(unsigned long)*(width*high)), hipMemcpyDeviceToHost); // ½Æ»s¸ê®Æ(µ²ªG)¦^CPU
fclose(fp);
unsigned long sum = 0;
/*for (int i = 0; i < 512*512; i++) {
sum += Dimg[i];
}*/
for (int i = 0; i < nthread*nblock; i += nthread) {
sum += Dimg[i];
}
sum /= (512*512);
printf("\n%3lu\n", sum);
} | .text
.file "hw5.hip"
.globl _Z18__device_stub__AddPmS_ii # -- Begin function _Z18__device_stub__AddPmS_ii
.p2align 4, 0x90
.type _Z18__device_stub__AddPmS_ii,@function
_Z18__device_stub__AddPmS_ii: # @_Z18__device_stub__AddPmS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3AddPmS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__AddPmS_ii, .Lfunc_end0-_Z18__device_stub__AddPmS_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $2097320, %rsp # imm = 0x2000A8
.cfi_def_cfa_offset 2097376
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $0, 20(%rsp)
movl $0, 16(%rsp)
movl $0, 12(%rsp)
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbp
xorl %ebx, %ebx
movl $10, %esi
movq %rax, %rdi
xorl %edx, %edx
callq fseek
leaq 12(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %rbp, %rcx
callq fread
movl $18, %esi
movq %rbp, %rdi
xorl %edx, %edx
callq fseek
leaq 16(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %rbp, %rcx
callq fread
movl $22, %esi
movq %rbp, %rdi
xorl %edx, %edx
callq fseek
leaq 20(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %rbp, %rcx
callq fread
movl 16(%rsp), %r12d
movl 20(%rsp), %eax
movl %eax, 8(%rsp) # 4-byte Spill
movl %eax, %r14d
imull %r12d, %r14d
movq %r14, %rdi
callq malloc
movq %rax, %r15
movl 12(%rsp), %r13d
movq %rbp, %rdi
movq %r13, %rsi
xorl %edx, %edx
callq fseek
movl $1, %esi
movq %r15, %rdi
movq %r14, %rdx
movq %rbp, %rcx
callq fread
movq %r13, %rdi
callq malloc
movq %rax, 24(%rsp) # 8-byte Spill
movq %rbp, %rdi
xorl %esi, %esi
xorl %edx, %edx
callq fseek
movl $1, %esi
movq 24(%rsp), %rdi # 8-byte Reload
movq %r13, %rdx
movq %rbp, 24(%rsp) # 8-byte Spill
movq %rbp, %rcx
callq fread
movl %r14d, %r13d
shrl $10, %r13d
cmpl $1025, %r12d # imm = 0x401
cmovbl 8(%rsp), %r13d # 4-byte Folded Reload
cmpl $1024, %r12d # imm = 0x400
movl $1024, %ebp # imm = 0x400
movl %r12d, 36(%rsp) # 4-byte Spill
cmovbl %r12d, %ebp
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movzbl (%r15,%rbx), %eax
movq %rax, 160(%rsp,%rbx,8)
incq %rbx
cmpq $262144, %rbx # imm = 0x40000
jne .LBB1_1
# %bb.2:
movabsq $4294967296, %r15 # imm = 0x100000000
leaq (%r15,%rbp), %r12
orq %r13, %r15
leaq (,%r14,8), %r14
leaq 56(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 56(%rsp), %rdi
leaq 160(%rsp), %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 48(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movl 8(%rsp), %eax # 4-byte Reload
movl %eax, 44(%rsp)
movl 36(%rsp), %eax # 4-byte Reload
movl %eax, 40(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z3AddPmS_ii, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
movq 48(%rsp), %rsi
leaq 160(%rsp), %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi # 8-byte Reload
callq fclose
imull %ebp, %r13d
xorl %esi, %esi
testl %r13d, %r13d
je .LBB1_8
# %bb.5: # %.lr.ph.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_6: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movslq %esi, %rsi
addq 160(%rsp,%rsi,8), %rax
addl %ebp, %esi
cmpl %r13d, %esi
jb .LBB1_6
# %bb.7: # %._crit_edge.loopexit
shrq $18, %rax
movq %rax, %rsi
.LBB1_8: # %._crit_edge
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $2097320, %rsp # imm = 0x2000A8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3AddPmS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3AddPmS_ii,@object # @_Z3AddPmS_ii
.section .rodata,"a",@progbits
.globl _Z3AddPmS_ii
.p2align 3, 0x0
_Z3AddPmS_ii:
.quad _Z18__device_stub__AddPmS_ii
.size _Z3AddPmS_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "lena.bmp"
.size .L.str, 9
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "rb"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n%3lu\n"
.size .L.str.2, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3AddPmS_ii"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__AddPmS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3AddPmS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3AddPmS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R26, c[0x0][0x160] ; /* 0x00005800001a7a02 */
/* 0x000fe20000000f00 */
/*0040*/ CS2R R14, SRZ ; /* 0x00000000000e7805 */
/* 0x000fe2000001ff00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0060*/ MOV R7, c[0x0][0x164] ; /* 0x0000590000077a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ MOV R5, c[0x0][0x0] ; /* 0x0000000000057a02 */
/* 0x000fe20000000f00 */
/*0090*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ MOV R6, c[0x0][0x0] ; /* 0x0000000000067a02 */
/* 0x000fe40000000f00 */
/*00b0*/ SHF.L.U32 R4, R0, 0x9, RZ ; /* 0x0000000900047819 */
/* 0x001fc400000006ff */
/*00c0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe40008000f00 */
/*00d0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc40008000f00 */
/*00e0*/ MOV R27, R7 ; /* 0x00000007001b7202 */
/* 0x000fc60000000f00 */
/*00f0*/ IMAD.WIDE R8, R3, 0x8, R8 ; /* 0x0000000803087825 */
/* 0x002fc800078e0208 */
/*0100*/ IMAD.WIDE R22, R4, 0x8, R26 ; /* 0x0000000804167825 */
/* 0x000fe200078e021a */
/*0110*/ LDG.E.64 R18, [R8.64] ; /* 0x0000000408127981 */
/* 0x000ea8000c1e1b00 */
/*0120*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000ea8000c1e1b00 */
/*0130*/ LDG.E.64 R10, [R22.64+0x8] ; /* 0x00000804160a7981 */
/* 0x000ee8000c1e1b00 */
/*0140*/ LDG.E.64 R16, [R8.64+0x1000] ; /* 0x0010000408107981 */
/* 0x000ee8000c1e1b00 */
/*0150*/ LDG.E.64 R24, [R8.64+0xf000] ; /* 0x00f0000408187981 */
/* 0x000f22000c1e1b00 */
/*0160*/ IMAD R19, R19, R12, RZ ; /* 0x0000000c13137224 */
/* 0x004fc400078e02ff */
/*0170*/ IMAD.WIDE.U32 R14, R18, R12, R14 ; /* 0x0000000c120e7225 */
/* 0x000fc800078e000e */
/*0180*/ IMAD R21, R18, R13, R19 ; /* 0x0000000d12157224 */
/* 0x000fe400078e0213 */
/*0190*/ LDG.E.64 R12, [R22.64+0x10] ; /* 0x00001004160c7981 */
/* 0x000ea8000c1e1b00 */
/*01a0*/ LDG.E.64 R18, [R8.64+0x2000] ; /* 0x0020000408127981 */
/* 0x000ea2000c1e1b00 */
/*01b0*/ IADD3 R15, R15, R21, RZ ; /* 0x000000150f0f7210 */
/* 0x000fe20007ffe0ff */
/*01c0*/ IMAD R17, R17, R10, RZ ; /* 0x0000000a11117224 */
/* 0x008fc800078e02ff */
/*01d0*/ IMAD R21, R16.reuse, R11, R17 ; /* 0x0000000b10157224 */
/* 0x040fe400078e0211 */
/*01e0*/ IMAD.WIDE.U32 R10, R16, R10, R14 ; /* 0x0000000a100a7225 */
/* 0x000fe400078e000e */
/*01f0*/ LDG.E.64 R14, [R22.64+0x18] ; /* 0x00001804160e7981 */
/* 0x000ee8000c1e1b00 */
/*0200*/ LDG.E.64 R16, [R8.64+0x3000] ; /* 0x0030000408107981 */
/* 0x000ee2000c1e1b00 */
/*0210*/ IADD3 R11, R11, R21, RZ ; /* 0x000000150b0b7210 */
/* 0x000fe20007ffe0ff */
/*0220*/ IMAD R19, R19, R12, RZ ; /* 0x0000000c13137224 */
/* 0x004fc800078e02ff */
/*0230*/ IMAD R21, R18.reuse, R13, R19 ; /* 0x0000000d12157224 */
/* 0x040fe400078e0213 */
/*0240*/ IMAD.WIDE.U32 R12, R18, R12, R10 ; /* 0x0000000c120c7225 */
/* 0x000fe400078e000a */
/*0250*/ LDG.E.64 R10, [R22.64+0x20] ; /* 0x00002004160a7981 */
/* 0x000ea8000c1e1b00 */
/*0260*/ LDG.E.64 R18, [R8.64+0x4000] ; /* 0x0040000408127981 */
/* 0x000ea2000c1e1b00 */
/*0270*/ IADD3 R13, R13, R21, RZ ; /* 0x000000150d0d7210 */
/* 0x000fe20007ffe0ff */
/*0280*/ IMAD R17, R17, R14, RZ ; /* 0x0000000e11117224 */
/* 0x008fc800078e02ff */
/*0290*/ IMAD R21, R16.reuse, R15, R17 ; /* 0x0000000f10157224 */
/* 0x040fe400078e0211 */
/*02a0*/ IMAD.WIDE.U32 R14, R16, R14, R12 ; /* 0x0000000e100e7225 */
/* 0x000fe400078e000c */
/*02b0*/ LDG.E.64 R12, [R22.64+0x28] ; /* 0x00002804160c7981 */
/* 0x000ee8000c1e1b00 */
/*02c0*/ LDG.E.64 R16, [R8.64+0x5000] ; /* 0x0050000408107981 */
/* 0x000ee2000c1e1b00 */
/*02d0*/ IADD3 R15, R15, R21, RZ ; /* 0x000000150f0f7210 */
/* 0x000fe20007ffe0ff */
/*02e0*/ IMAD R19, R19, R10, RZ ; /* 0x0000000a13137224 */
/* 0x004fc800078e02ff */
/*02f0*/ IMAD R21, R18.reuse, R11, R19 ; /* 0x0000000b12157224 */
/* 0x040fe400078e0213 */
/*0300*/ IMAD.WIDE.U32 R10, R18, R10, R14 ; /* 0x0000000a120a7225 */
/* 0x000fe400078e000e */
/*0310*/ LDG.E.64 R14, [R22.64+0x30] ; /* 0x00003004160e7981 */
/* 0x000ea8000c1e1b00 */
/*0320*/ LDG.E.64 R18, [R8.64+0x6000] ; /* 0x0060000408127981 */
/* 0x000ea2000c1e1b00 */
/*0330*/ IADD3 R11, R11, R21, RZ ; /* 0x000000150b0b7210 */
/* 0x000fe20007ffe0ff */
/*0340*/ IMAD R17, R17, R12, RZ ; /* 0x0000000c11117224 */
/* 0x008fc800078e02ff */
/*0350*/ IMAD R21, R16.reuse, R13, R17 ; /* 0x0000000d10157224 */
/* 0x040fe400078e0211 */
/*0360*/ IMAD.WIDE.U32 R12, R16, R12, R10 ; /* 0x0000000c100c7225 */
/* 0x000fe400078e000a */
/*0370*/ LDG.E.64 R10, [R22.64+0x38] ; /* 0x00003804160a7981 */
/* 0x000ee8000c1e1b00 */
/*0380*/ LDG.E.64 R16, [R8.64+0x7000] ; /* 0x0070000408107981 */
/* 0x000ee2000c1e1b00 */
/*0390*/ IADD3 R13, R13, R21, RZ ; /* 0x000000150d0d7210 */
/* 0x000fe20007ffe0ff */
/*03a0*/ IMAD R19, R19, R14, RZ ; /* 0x0000000e13137224 */
/* 0x004fc800078e02ff */
/*03b0*/ IMAD R21, R18.reuse, R15, R19 ; /* 0x0000000f12157224 */
/* 0x040fe400078e0213 */
/*03c0*/ IMAD.WIDE.U32 R14, R18, R14, R12 ; /* 0x0000000e120e7225 */
/* 0x000fe400078e000c */
/*03d0*/ LDG.E.64 R12, [R22.64+0x40] ; /* 0x00004004160c7981 */
/* 0x000ea8000c1e1b00 */
/*03e0*/ LDG.E.64 R18, [R8.64+0x8000] ; /* 0x0080000408127981 */
/* 0x000ea2000c1e1b00 */
/*03f0*/ IADD3 R15, R15, R21, RZ ; /* 0x000000150f0f7210 */
/* 0x000fe20007ffe0ff */
/*0400*/ IMAD R17, R17, R10, RZ ; /* 0x0000000a11117224 */
/* 0x008fc800078e02ff */
/*0410*/ IMAD R21, R16.reuse, R11, R17 ; /* 0x0000000b10157224 */
/* 0x040fe400078e0211 */
/*0420*/ IMAD.WIDE.U32 R10, R16, R10, R14 ; /* 0x0000000a100a7225 */
/* 0x000fe400078e000e */
/*0430*/ LDG.E.64 R16, [R22.64+0x48] ; /* 0x0000480416107981 */
/* 0x000ee8000c1e1b00 */
/*0440*/ LDG.E.64 R14, [R8.64+0x9000] ; /* 0x00900004080e7981 */
/* 0x000ee2000c1e1b00 */
/*0450*/ IADD3 R11, R11, R21, RZ ; /* 0x000000150b0b7210 */
/* 0x000fe20007ffe0ff */
/*0460*/ IMAD R19, R19, R12, RZ ; /* 0x0000000c13137224 */
/* 0x004fc800078e02ff */
/*0470*/ IMAD R21, R18.reuse, R13, R19 ; /* 0x0000000d12157224 */
/* 0x040fe400078e0213 */
/*0480*/ IMAD.WIDE.U32 R12, R18, R12, R10 ; /* 0x0000000c120c7225 */
/* 0x000fe400078e000a */
/*0490*/ LDG.E.64 R10, [R22.64+0x50] ; /* 0x00005004160a7981 */
/* 0x000ea8000c1e1b00 */
/*04a0*/ LDG.E.64 R18, [R8.64+0xa000] ; /* 0x00a0000408127981 */
/* 0x000ea2000c1e1b00 */
/*04b0*/ IADD3 R13, R13, R21, RZ ; /* 0x000000150d0d7210 */
/* 0x000fe20007ffe0ff */
/*04c0*/ IMAD R15, R15, R16, RZ ; /* 0x000000100f0f7224 */
/* 0x008fc800078e02ff */
/*04d0*/ IMAD R21, R14.reuse, R17, R15 ; /* 0x000000110e157224 */
/* 0x040fe400078e020f */
/*04e0*/ IMAD.WIDE.U32 R16, R14, R16, R12 ; /* 0x000000100e107225 */
/* 0x000fe400078e000c */
/*04f0*/ LDG.E.64 R14, [R22.64+0x58] ; /* 0x00005804160e7981 */
/* 0x000ee8000c1e1b00 */
/*0500*/ LDG.E.64 R12, [R8.64+0xb000] ; /* 0x00b00004080c7981 */
/* 0x000ee2000c1e1b00 */
/*0510*/ IADD3 R17, R17, R21, RZ ; /* 0x0000001511117210 */
/* 0x000fe20007ffe0ff */
/*0520*/ IMAD R19, R19, R10, RZ ; /* 0x0000000a13137224 */
/* 0x004fc800078e02ff */
/*0530*/ IMAD R21, R18.reuse, R11, R19 ; /* 0x0000000b12157224 */
/* 0x040fe400078e0213 */
/*0540*/ IMAD.WIDE.U32 R10, R18, R10, R16 ; /* 0x0000000a120a7225 */
/* 0x000fe400078e0010 */
/*0550*/ LDG.E.64 R16, [R22.64+0x60] ; /* 0x0000600416107981 */
/* 0x000ea8000c1e1b00 */
/*0560*/ LDG.E.64 R18, [R8.64+0xc000] ; /* 0x00c0000408127981 */
/* 0x000ea2000c1e1b00 */
/*0570*/ IADD3 R11, R11, R21, RZ ; /* 0x000000150b0b7210 */
/* 0x000fe20007ffe0ff */
/*0580*/ IMAD R13, R13, R14, RZ ; /* 0x0000000e0d0d7224 */
/* 0x008fc800078e02ff */
/*0590*/ IMAD R21, R12.reuse, R15, R13 ; /* 0x0000000f0c157224 */
/* 0x040fe400078e020d */
/*05a0*/ IMAD.WIDE.U32 R14, R12, R14, R10 ; /* 0x0000000e0c0e7225 */
/* 0x000fe400078e000a */
/*05b0*/ LDG.E.64 R10, [R22.64+0x68] ; /* 0x00006804160a7981 */
/* 0x000ee8000c1e1b00 */
/*05c0*/ LDG.E.64 R12, [R8.64+0xd000] ; /* 0x00d00004080c7981 */
/* 0x000ee2000c1e1b00 */
/*05d0*/ IADD3 R15, R15, R21, RZ ; /* 0x000000150f0f7210 */
/* 0x000fc60007ffe0ff */
/*05e0*/ LDG.E.64 R20, [R22.64+0x78] ; /* 0x0000780416147981 */
/* 0x000f22000c1e1b00 */
/*05f0*/ IMAD R27, R19, R16.reuse, RZ ; /* 0x00000010131b7224 */
/* 0x084fe400078e02ff */
/*0600*/ IMAD.WIDE.U32 R14, R18, R16, R14 ; /* 0x00000010120e7225 */
/* 0x000fc800078e000e */
/*0610*/ IMAD R27, R18, R17, R27 ; /* 0x00000011121b7224 */
/* 0x000fe400078e021b */
/*0620*/ LDG.E.64 R16, [R22.64+0x70] ; /* 0x0000700416107981 */
/* 0x000ea8000c1e1b00 */
/*0630*/ LDG.E.64 R18, [R8.64+0xe000] ; /* 0x00e0000408127981 */
/* 0x0008a2000c1e1b00 */
/*0640*/ IADD3 R15, R15, R27, RZ ; /* 0x0000001b0f0f7210 */
/* 0x000fe20007ffe0ff */
/*0650*/ IMAD R13, R13, R10, RZ ; /* 0x0000000a0d0d7224 */
/* 0x008fc800078e02ff */
/*0660*/ IMAD R13, R12.reuse, R11, R13 ; /* 0x0000000b0c0d7224 */
/* 0x040fe400078e020d */
/*0670*/ IMAD.WIDE.U32 R10, R12, R10, R14 ; /* 0x0000000a0c0a7225 */
/* 0x000fe200078e000e */
/*0680*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fc80007ffe0ff */
/*0690*/ IADD3 R11, R11, R13, RZ ; /* 0x0000000d0b0b7210 */
/* 0x000fe40007ffe0ff */
/*06a0*/ ISETP.NE.AND P0, PT, R2, 0x200, PT ; /* 0x000002000200780c */
/* 0x000fe20003f05270 */
/*06b0*/ IMAD R9, R25, R20, RZ ; /* 0x0000001419097224 */
/* 0x010fe200078e02ff */
/*06c0*/ UIADD3 UR6, UP0, UR6, 0x10000, URZ ; /* 0x0001000006067890 */
/* 0x000fe2000ff1e03f */
/*06d0*/ IADD3 R26, P1, R26, 0x80, RZ ; /* 0x000000801a1a7810 */
/* 0x000fe40007f3e0ff */
/*06e0*/ IMAD R9, R24, R21, R9 ; /* 0x0000001518097224 */
/* 0x000fe200078e0209 */
/*06f0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0700*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0710*/ IMAD R13, R19, R16, RZ ; /* 0x00000010130d7224 */
/* 0x004fc400078e02ff */
/*0720*/ IMAD.WIDE.U32 R10, R18, R16, R10 ; /* 0x00000010120a7225 */
/* 0x000fc800078e000a */
/*0730*/ IMAD R13, R18, R17, R13 ; /* 0x00000011120d7224 */
/* 0x000fca00078e020d */
/*0740*/ IADD3 R11, R11, R13, RZ ; /* 0x0000000d0b0b7210 */
/* 0x000fca0007ffe0ff */
/*0750*/ IMAD.WIDE.U32 R14, R24, R20, R10 ; /* 0x00000014180e7225 */
/* 0x000fca00078e000a */
/*0760*/ IADD3 R15, R15, R9, RZ ; /* 0x000000090f0f7210 */
/* 0x000fe20007ffe0ff */
/*0770*/ @P0 BRA 0xc0 ; /* 0xfffff94000000947 */
/* 0x000fea000383ffff */
/*0780*/ IADD3 R4, R4, R3, RZ ; /* 0x0000000304047210 */
/* 0x000fe40007ffe0ff */
/*0790*/ MOV R7, 0x8 ; /* 0x0000000800077802 */
/* 0x000fe40000000f00 */
/*07a0*/ IADD3 R2, R5, 0x1, RZ ; /* 0x0000000105027810 */
/* 0x000fc60007ffe0ff */
/*07b0*/ IMAD.WIDE R4, R4, R7, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0207 */
/*07c0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fc80003f06070 */
/*07d0*/ STG.E.64 [R4.64], R14 ; /* 0x0000000e04007986 */
/* 0x0001e8000c101b04 */
/*07e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*07f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0800*/ IMAD R4, R0, c[0x0][0x0], R3 ; /* 0x0000000000047a24 */
/* 0x001fc800078e0203 */
/*0810*/ IMAD.WIDE R4, R4, R7, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0207 */
/*0820*/ LEA.HI R6, R6, R6, RZ, 0x1 ; /* 0x0000000606067211 */
/* 0x000fe200078f08ff */
/*0830*/ BSSY B0, 0x8e0 ; /* 0x000000a000007945 */
/* 0x000fe60003800000 */
/*0840*/ SHF.R.S32.HI R6, RZ, 0x1, R6 ; /* 0x00000001ff067819 */
/* 0x000fc80000011406 */
/*0850*/ ISETP.GE.AND P0, PT, R3, R6, PT ; /* 0x000000060300720c */
/* 0x000fda0003f06270 */
/*0860*/ @P0 BRA 0x8d0 ; /* 0x0000006000000947 */
/* 0x001fea0003800000 */
/*0870*/ IMAD.WIDE R8, R6, 0x8, R4 ; /* 0x0000000806087825 */
/* 0x000fe200078e0204 */
/*0880*/ LDG.E.64 R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000eaa000c1e1b00 */
/*0890*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea4000c1e1b00 */
/*08a0*/ IADD3 R10, P0, R10, R8, RZ ; /* 0x000000080a0a7210 */
/* 0x004fc80007f1e0ff */
/*08b0*/ IADD3.X R11, R11, R9, RZ, P0, !PT ; /* 0x000000090b0b7210 */
/* 0x000fca00007fe4ff */
/*08c0*/ STG.E.64 [R4.64], R10 ; /* 0x0000000a04007986 */
/* 0x0001e8000c101b04 */
/*08d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08e0*/ IADD3 R0, R6, 0x1, RZ ; /* 0x0000000106007810 */
/* 0x000fe20007ffe0ff */
/*08f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0900*/ ISETP.GT.U32.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fda0003f04070 */
/*0910*/ @P0 BRA 0x820 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*0920*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0930*/ BRA 0x930; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3AddPmS_ii
.globl _Z3AddPmS_ii
.p2align 8
.type _Z3AddPmS_ii,@function
_Z3AddPmS_ii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s4, s[0:1], 0x24
v_lshlrev_b32_e32 v1, 3, v0
s_lshl_b32 s6, s15, 9
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v6, 0
s_ashr_i32 s7, s6, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_lshl_b64 s[6:7], s[6:7], 3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, s5, s2, v1
v_add_co_ci_u32_e64 v2, null, s3, 0, s5
s_add_u32 s5, s2, s6
s_addc_u32 s6, s3, s7
s_mov_b64 s[2:3], 0
.p2align 6
.LBB0_1:
global_load_b64 v[7:8], v[1:2], off
s_add_u32 s8, s5, s2
s_addc_u32 s9, s6, s3
v_add_co_u32 v1, vcc_lo, v1, 0x1000
s_load_b64 s[8:9], s[8:9], 0x0
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_add_u32 s2, s2, 8
s_addc_u32 s3, s3, 0
s_cmpk_eq_i32 s2, 0x1000
s_waitcnt vmcnt(0) lgkmcnt(0)
v_mul_lo_u32 v9, v7, s9
v_mul_lo_u32 v8, v8, s8
v_mad_u64_u32 v[3:4], null, v7, s8, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v4, v8, v4, v9
v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
s_cbranch_scc0 .LBB0_1
s_load_b64 s[0:1], s[0:1], 0x8
v_lshl_add_u32 v1, s15, 9, v0
v_cmp_lt_u16_e64 s2, s4, 2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 3, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_and_b32 vcc_lo, exec_lo, s2
global_store_b64 v[1:2], v[3:4], off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB0_7
s_and_b32 s2, 0xffff, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s4
s_cmp_gt_u32 s2, 3
s_mov_b32 s2, s3
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_7
.LBB0_5:
s_lshr_b32 s3, s2, 1
s_mov_b32 s4, exec_lo
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB0_4
v_add_nc_u32_e32 v4, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 3, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_clause 0x1
global_load_b64 v[4:5], v[4:5], off
global_load_b64 v[6:7], v[2:3], off
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, v7, v5, vcc_lo
global_store_b64 v[2:3], v[4:5], off
s_branch .LBB0_4
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3AddPmS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3AddPmS_ii, .Lfunc_end0-_Z3AddPmS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3AddPmS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3AddPmS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009af96_00000000-6_hw5.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3AddPmS_iiPmS_ii
.type _Z26__device_stub__Z3AddPmS_iiPmS_ii, @function
_Z26__device_stub__Z3AddPmS_iiPmS_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3AddPmS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3AddPmS_iiPmS_ii, .-_Z26__device_stub__Z3AddPmS_iiPmS_ii
.globl _Z3AddPmS_ii
.type _Z3AddPmS_ii, @function
_Z3AddPmS_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3AddPmS_iiPmS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3AddPmS_ii, .-_Z3AddPmS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "rb"
.LC1:
.string "lena.bmp"
.LC2:
.string "\n%3lu\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
leaq -2097152(%rsp), %r11
.cfi_def_cfa 11, 2097192
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $88, %rsp
.cfi_def_cfa_offset 2097280
movq %fs:40, %rax
movq %rax, 2097224(%rsp)
xorl %eax, %eax
movl $0, 12(%rsp)
movl $0, 16(%rsp)
movl $0, 20(%rsp)
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %r13
movl $0, %edx
movl $10, %esi
movq %rax, %rdi
call fseek@PLT
leaq 20(%rsp), %rdi
movq %r13, %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
movl $0, %edx
movl $18, %esi
movq %r13, %rdi
call fseek@PLT
leaq 16(%rsp), %rdi
movq %r13, %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
movl $0, %edx
movl $22, %esi
movq %r13, %rdi
call fseek@PLT
leaq 12(%rsp), %rdi
movq %r13, %r8
movl $1, %ecx
movl $4, %edx
movl $4, %esi
call __fread_chk@PLT
movl 16(%rsp), %ebp
imull 12(%rsp), %ebp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
movl 20(%rsp), %esi
movl $0, %edx
movq %r13, %rdi
call fseek@PLT
movl 16(%rsp), %ecx
imull 12(%rsp), %ecx
movq %r13, %r8
movl $1, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call __fread_chk@PLT
movl 20(%rsp), %r12d
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movl $0, %edx
movl $0, %esi
movq %r13, %rdi
call fseek@PLT
movl 20(%rsp), %ecx
movq %r13, %r8
movl $1, %edx
movq %r12, %rsi
movq %rbp, %rdi
call __fread_chk@PLT
movl 16(%rsp), %ecx
cmpl $1024, %ecx
jbe .L12
movl %ecx, %esi
imull 12(%rsp), %esi
shrl $10, %esi
movl %esi, %r12d
movl $1024, %ebp
.L13:
movl %ebp, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl %r12d, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %eax
.L14:
movzbl (%rbx,%rax), %edx
movq %rdx, 64(%rsp,%rax,8)
addq $1, %rax
cmpq $262144, %rax
jne .L14
imull 12(%rsp), %ecx
leaq 0(,%rcx,8), %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movl 16(%rsp), %edx
imull 12(%rsp), %edx
salq $3, %rdx
leaq 64(%rsp), %rsi
movl $1, %ecx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl 16(%rsp), %esi
imull 12(%rsp), %esi
salq $3, %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
movl 48(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movq 52(%rsp), %rdi
movl 60(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L15:
call cudaThreadSynchronize@PLT
movl 16(%rsp), %edx
imull 12(%rsp), %edx
salq $3, %rdx
leaq 64(%rsp), %rdi
movl $2, %ecx
movq 32(%rsp), %rsi
call cudaMemcpy@PLT
movq %r13, %rdi
call fclose@PLT
movl %r12d, %esi
imull %ebp, %esi
testl %esi, %esi
je .L19
movl $0, %ecx
movl $0, %edx
movl $0, %eax
.L17:
movslq %ecx, %rcx
addq 64(%rsp,%rcx,8), %rdx
addl %ebp, %eax
movl %eax, %ecx
cmpl %esi, %eax
jb .L17
.L16:
shrq $18, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 2097224(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $2097240, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movl 12(%rsp), %r12d
movl %ecx, %ebp
jmp .L13
.L23:
movl 16(%rsp), %ecx
movl 12(%rsp), %edx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z26__device_stub__Z3AddPmS_iiPmS_ii
jmp .L15
.L19:
movl $0, %edx
jmp .L16
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z3AddPmS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z3AddPmS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hw5.hip"
.globl _Z18__device_stub__AddPmS_ii # -- Begin function _Z18__device_stub__AddPmS_ii
.p2align 4, 0x90
.type _Z18__device_stub__AddPmS_ii,@function
_Z18__device_stub__AddPmS_ii: # @_Z18__device_stub__AddPmS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3AddPmS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__AddPmS_ii, .Lfunc_end0-_Z18__device_stub__AddPmS_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $2097320, %rsp # imm = 0x2000A8
.cfi_def_cfa_offset 2097376
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $0, 20(%rsp)
movl $0, 16(%rsp)
movl $0, 12(%rsp)
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %rbp
xorl %ebx, %ebx
movl $10, %esi
movq %rax, %rdi
xorl %edx, %edx
callq fseek
leaq 12(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %rbp, %rcx
callq fread
movl $18, %esi
movq %rbp, %rdi
xorl %edx, %edx
callq fseek
leaq 16(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %rbp, %rcx
callq fread
movl $22, %esi
movq %rbp, %rdi
xorl %edx, %edx
callq fseek
leaq 20(%rsp), %rdi
movl $4, %esi
movl $1, %edx
movq %rbp, %rcx
callq fread
movl 16(%rsp), %r12d
movl 20(%rsp), %eax
movl %eax, 8(%rsp) # 4-byte Spill
movl %eax, %r14d
imull %r12d, %r14d
movq %r14, %rdi
callq malloc
movq %rax, %r15
movl 12(%rsp), %r13d
movq %rbp, %rdi
movq %r13, %rsi
xorl %edx, %edx
callq fseek
movl $1, %esi
movq %r15, %rdi
movq %r14, %rdx
movq %rbp, %rcx
callq fread
movq %r13, %rdi
callq malloc
movq %rax, 24(%rsp) # 8-byte Spill
movq %rbp, %rdi
xorl %esi, %esi
xorl %edx, %edx
callq fseek
movl $1, %esi
movq 24(%rsp), %rdi # 8-byte Reload
movq %r13, %rdx
movq %rbp, 24(%rsp) # 8-byte Spill
movq %rbp, %rcx
callq fread
movl %r14d, %r13d
shrl $10, %r13d
cmpl $1025, %r12d # imm = 0x401
cmovbl 8(%rsp), %r13d # 4-byte Folded Reload
cmpl $1024, %r12d # imm = 0x400
movl $1024, %ebp # imm = 0x400
movl %r12d, 36(%rsp) # 4-byte Spill
cmovbl %r12d, %ebp
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movzbl (%r15,%rbx), %eax
movq %rax, 160(%rsp,%rbx,8)
incq %rbx
cmpq $262144, %rbx # imm = 0x40000
jne .LBB1_1
# %bb.2:
movabsq $4294967296, %r15 # imm = 0x100000000
leaq (%r15,%rbp), %r12
orq %r13, %r15
leaq (,%r14,8), %r14
leaq 56(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 56(%rsp), %rdi
leaq 160(%rsp), %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 48(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movl 8(%rsp), %eax # 4-byte Reload
movl %eax, 44(%rsp)
movl 36(%rsp), %eax # 4-byte Reload
movl %eax, 40(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z3AddPmS_ii, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
movq 48(%rsp), %rsi
leaq 160(%rsp), %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi # 8-byte Reload
callq fclose
imull %ebp, %r13d
xorl %esi, %esi
testl %r13d, %r13d
je .LBB1_8
# %bb.5: # %.lr.ph.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_6: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movslq %esi, %rsi
addq 160(%rsp,%rsi,8), %rax
addl %ebp, %esi
cmpl %r13d, %esi
jb .LBB1_6
# %bb.7: # %._crit_edge.loopexit
shrq $18, %rax
movq %rax, %rsi
.LBB1_8: # %._crit_edge
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $2097320, %rsp # imm = 0x2000A8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3AddPmS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3AddPmS_ii,@object # @_Z3AddPmS_ii
.section .rodata,"a",@progbits
.globl _Z3AddPmS_ii
.p2align 3, 0x0
_Z3AddPmS_ii:
.quad _Z18__device_stub__AddPmS_ii
.size _Z3AddPmS_ii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "lena.bmp"
.size .L.str, 9
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "rb"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n%3lu\n"
.size .L.str.2, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3AddPmS_ii"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__AddPmS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3AddPmS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void Sign( float * x, size_t idx, size_t N)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
float res = x[(idx-1)*N+i];
if (res > 0 )
x[(idx-1)*N+i] = 1.0 ;
else if (res == 0)
x[(idx-1)*N+i] = 0.0;
else
x[(idx-1)*N+i] = -1.0 ;
}
return;
} | code for sm_80
Function : _Z4SignPfmm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R2, c[0x0][0x174], PT, P0 ; /* 0x00005d0002007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fc600078e00ff */
/*00b0*/ IADD3 R7, P0, -R7, c[0x0][0x168], RZ ; /* 0x00005a0007077a10 */
/* 0x000fc80007f1e1ff */
/*00c0*/ IADD3.X R3, R3, -0x1, RZ, P0, !PT ; /* 0xffffffff03037810 */
/* 0x000fca00007fe4ff */
/*00d0*/ IMAD R4, R3, c[0x0][0x170], RZ ; /* 0x00005c0003047a24 */
/* 0x000fe200078e02ff */
/*00e0*/ MOV R3, R2 ; /* 0x0000000200037202 */
/* 0x000fe20000000f00 */
/*00f0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*0100*/ IMAD R9, R7, c[0x0][0x174], R4 ; /* 0x00005d0007097a24 */
/* 0x000fe400078e0204 */
/*0110*/ IMAD.WIDE.U32 R2, R7, c[0x0][0x170], R2 ; /* 0x00005c0007027a25 */
/* 0x000fc800078e0002 */
/*0120*/ IMAD.IADD R3, R3, 0x1, R9 ; /* 0x0000000103037824 */
/* 0x000fe200078e0209 */
/*0130*/ LEA R4, P0, R2, c[0x0][0x160], 0x2 ; /* 0x0000580002047a11 */
/* 0x000fc800078010ff */
/*0140*/ LEA.HI.X R5, R2, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590002057a11 */
/* 0x000fca00000f1403 */
/*0150*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea2000c1e1900 */
/*0160*/ BSSY B0, 0x210 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*0170*/ FSETP.GT.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x004fda0003f04000 */
/*0180*/ @P0 BRA 0x1e0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0190*/ FSETP.NEU.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x000fda0003f0d000 */
/*01a0*/ @P0 MOV R3, 0xbf800000 ; /* 0xbf80000000030802 */
/* 0x000fca0000000f00 */
/*01b0*/ @P0 STG.E [R4.64], R3 ; /* 0x0000000304000986 */
/* 0x0001e8000c101904 */
/*01c0*/ @!P0 STG.E [R4.64], RZ ; /* 0x000000ff04008986 */
/* 0x0001e2000c101904 */
/*01d0*/ BRA 0x200 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*01e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff037424 */
/* 0x000fca00078e00ff */
/*01f0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0001e4000c101904 */
/*0200*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0210*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff037624 */
/* 0x001fc800078e00ff */
/*0220*/ IMAD R2, R3, c[0x0][0xc], R0 ; /* 0x0000030003027a24 */
/* 0x000fca00078e0200 */
/*0230*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fe40003f06070 */
/*0240*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fe40000011402 */
/*0250*/ MOV R0, R2 ; /* 0x0000000200007202 */
/* 0x000fe40000000f00 */
/*0260*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x174], PT, P0 ; /* 0x00005d0003007a0c */
/* 0x000fda0003f06100 */
/*0270*/ @!P0 BRA 0x110 ; /* 0xfffffe9000008947 */
/* 0x000fea000383ffff */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ BRA 0x290; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void Sign( float * x, size_t idx, size_t N)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
float res = x[(idx-1)*N+i];
if (res > 0 )
x[(idx-1)*N+i] = 1.0 ;
else if (res == 0)
x[(idx-1)*N+i] = 0.0;
else
x[(idx-1)*N+i] = -1.0 ;
}
return;
} | .file "tmpxft_0015033e_00000000-6_Sign.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z4SignPfmmPfmm
.type _Z25__device_stub__Z4SignPfmmPfmm, @function
_Z25__device_stub__Z4SignPfmmPfmm:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4SignPfmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z25__device_stub__Z4SignPfmmPfmm, .-_Z25__device_stub__Z4SignPfmmPfmm
.globl _Z4SignPfmm
.type _Z4SignPfmm, @function
_Z4SignPfmm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z4SignPfmmPfmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4SignPfmm, .-_Z4SignPfmm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4SignPfmm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4SignPfmm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void Sign( float * x, size_t idx, size_t N)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
float res = x[(idx-1)*N+i];
if (res > 0 )
x[(idx-1)*N+i] = 1.0 ;
else if (res == 0)
x[(idx-1)*N+i] = 0.0;
else
x[(idx-1)*N+i] = -1.0 ;
}
return;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Sign( float * x, size_t idx, size_t N)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
float res = x[(idx-1)*N+i];
if (res > 0 )
x[(idx-1)*N+i] = 1.0 ;
else if (res == 0)
x[(idx-1)*N+i] = 0.0;
else
x[(idx-1)*N+i] = -1.0 ;
}
return;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Sign( float * x, size_t idx, size_t N)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
float res = x[(idx-1)*N+i];
if (res > 0 )
x[(idx-1)*N+i] = 1.0 ;
else if (res == 0)
x[(idx-1)*N+i] = 0.0;
else
x[(idx-1)*N+i] = -1.0 ;
}
return;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4SignPfmm
.globl _Z4SignPfmm
.p2align 8
.type _Z4SignPfmm,@function
_Z4SignPfmm:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b32 s7, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s10, -1
s_addc_u32 s1, s11, -1
s_mul_i32 s4, s0, s3
s_mul_hi_u32 s5, s0, s2
s_mul_i32 s1, s1, s2
s_add_i32 s4, s5, s4
s_mul_i32 s0, s0, s2
s_add_i32 s1, s4, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[0:1], 2
s_add_u32 s1, s8, s4
s_addc_u32 s4, s9, s5
s_add_i32 s15, s15, s7
s_mul_i32 s5, s7, s6
v_mad_u64_u32 v[3:4], null, s15, s6, v[0:1]
s_mov_b32 s6, 0
.p2align 6
.LBB0_2:
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v5, vcc_lo, s1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s4, v1, vcc_lo
v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
global_load_b32 v0, v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_eq_f32_e32 vcc_lo, 0, v0
v_cmp_nlt_f32_e64 s0, 0, v0
v_cndmask_b32_e64 v7, -1.0, 0, vcc_lo
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[3:4]
v_add_nc_u32_e32 v3, s5, v3
s_delay_alu instid0(VALU_DEP_3)
v_cndmask_b32_e64 v0, 1.0, v7, s0
s_or_b32 s6, vcc_lo, s6
global_store_b32 v[5:6], v0, off
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4SignPfmm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4SignPfmm, .Lfunc_end0-_Z4SignPfmm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4SignPfmm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4SignPfmm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Sign( float * x, size_t idx, size_t N)
{
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < N; i += blockDim.x * gridDim.x)
{
float res = x[(idx-1)*N+i];
if (res > 0 )
x[(idx-1)*N+i] = 1.0 ;
else if (res == 0)
x[(idx-1)*N+i] = 0.0;
else
x[(idx-1)*N+i] = -1.0 ;
}
return;
} | .text
.file "Sign.hip"
.globl _Z19__device_stub__SignPfmm # -- Begin function _Z19__device_stub__SignPfmm
.p2align 4, 0x90
.type _Z19__device_stub__SignPfmm,@function
_Z19__device_stub__SignPfmm: # @_Z19__device_stub__SignPfmm
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4SignPfmm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z19__device_stub__SignPfmm, .Lfunc_end0-_Z19__device_stub__SignPfmm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4SignPfmm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4SignPfmm,@object # @_Z4SignPfmm
.section .rodata,"a",@progbits
.globl _Z4SignPfmm
.p2align 3, 0x0
_Z4SignPfmm:
.quad _Z19__device_stub__SignPfmm
.size _Z4SignPfmm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4SignPfmm"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__SignPfmm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4SignPfmm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4SignPfmm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe40003f06070 */
/*0050*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fc80000011400 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R2, c[0x0][0x174], PT, P0 ; /* 0x00005d0002007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fc600078e00ff */
/*00b0*/ IADD3 R7, P0, -R7, c[0x0][0x168], RZ ; /* 0x00005a0007077a10 */
/* 0x000fc80007f1e1ff */
/*00c0*/ IADD3.X R3, R3, -0x1, RZ, P0, !PT ; /* 0xffffffff03037810 */
/* 0x000fca00007fe4ff */
/*00d0*/ IMAD R4, R3, c[0x0][0x170], RZ ; /* 0x00005c0003047a24 */
/* 0x000fe200078e02ff */
/*00e0*/ MOV R3, R2 ; /* 0x0000000200037202 */
/* 0x000fe20000000f00 */
/*00f0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*0100*/ IMAD R9, R7, c[0x0][0x174], R4 ; /* 0x00005d0007097a24 */
/* 0x000fe400078e0204 */
/*0110*/ IMAD.WIDE.U32 R2, R7, c[0x0][0x170], R2 ; /* 0x00005c0007027a25 */
/* 0x000fc800078e0002 */
/*0120*/ IMAD.IADD R3, R3, 0x1, R9 ; /* 0x0000000103037824 */
/* 0x000fe200078e0209 */
/*0130*/ LEA R4, P0, R2, c[0x0][0x160], 0x2 ; /* 0x0000580002047a11 */
/* 0x000fc800078010ff */
/*0140*/ LEA.HI.X R5, R2, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590002057a11 */
/* 0x000fca00000f1403 */
/*0150*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea2000c1e1900 */
/*0160*/ BSSY B0, 0x210 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*0170*/ FSETP.GT.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x004fda0003f04000 */
/*0180*/ @P0 BRA 0x1e0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0190*/ FSETP.NEU.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x000fda0003f0d000 */
/*01a0*/ @P0 MOV R3, 0xbf800000 ; /* 0xbf80000000030802 */
/* 0x000fca0000000f00 */
/*01b0*/ @P0 STG.E [R4.64], R3 ; /* 0x0000000304000986 */
/* 0x0001e8000c101904 */
/*01c0*/ @!P0 STG.E [R4.64], RZ ; /* 0x000000ff04008986 */
/* 0x0001e2000c101904 */
/*01d0*/ BRA 0x200 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*01e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff037424 */
/* 0x000fca00078e00ff */
/*01f0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0001e4000c101904 */
/*0200*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0210*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff037624 */
/* 0x001fc800078e00ff */
/*0220*/ IMAD R2, R3, c[0x0][0xc], R0 ; /* 0x0000030003027a24 */
/* 0x000fca00078e0200 */
/*0230*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fe40003f06070 */
/*0240*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fe40000011402 */
/*0250*/ MOV R0, R2 ; /* 0x0000000200007202 */
/* 0x000fe40000000f00 */
/*0260*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x174], PT, P0 ; /* 0x00005d0003007a0c */
/* 0x000fda0003f06100 */
/*0270*/ @!P0 BRA 0x110 ; /* 0xfffffe9000008947 */
/* 0x000fea000383ffff */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ BRA 0x290; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4SignPfmm
.globl _Z4SignPfmm
.p2align 8
.type _Z4SignPfmm,@function
_Z4SignPfmm:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_mov_b32 s7, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s6, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b32 s7, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s10, -1
s_addc_u32 s1, s11, -1
s_mul_i32 s4, s0, s3
s_mul_hi_u32 s5, s0, s2
s_mul_i32 s1, s1, s2
s_add_i32 s4, s5, s4
s_mul_i32 s0, s0, s2
s_add_i32 s1, s4, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[0:1], 2
s_add_u32 s1, s8, s4
s_addc_u32 s4, s9, s5
s_add_i32 s15, s15, s7
s_mul_i32 s5, s7, s6
v_mad_u64_u32 v[3:4], null, s15, s6, v[0:1]
s_mov_b32 s6, 0
.p2align 6
.LBB0_2:
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_add_co_u32 v5, vcc_lo, s1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s4, v1, vcc_lo
v_dual_mov_b32 v1, v3 :: v_dual_mov_b32 v2, v4
global_load_b32 v0, v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_eq_f32_e32 vcc_lo, 0, v0
v_cmp_nlt_f32_e64 s0, 0, v0
v_cndmask_b32_e64 v7, -1.0, 0, vcc_lo
v_cmp_le_u64_e32 vcc_lo, s[2:3], v[3:4]
v_add_nc_u32_e32 v3, s5, v3
s_delay_alu instid0(VALU_DEP_3)
v_cndmask_b32_e64 v0, 1.0, v7, s0
s_or_b32 s6, vcc_lo, s6
global_store_b32 v[5:6], v0, off
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4SignPfmm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4SignPfmm, .Lfunc_end0-_Z4SignPfmm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4SignPfmm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4SignPfmm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015033e_00000000-6_Sign.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z4SignPfmmPfmm
.type _Z25__device_stub__Z4SignPfmmPfmm, @function
_Z25__device_stub__Z4SignPfmmPfmm:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4SignPfmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z25__device_stub__Z4SignPfmmPfmm, .-_Z25__device_stub__Z4SignPfmmPfmm
.globl _Z4SignPfmm
.type _Z4SignPfmm, @function
_Z4SignPfmm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z4SignPfmmPfmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4SignPfmm, .-_Z4SignPfmm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4SignPfmm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4SignPfmm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Sign.hip"
.globl _Z19__device_stub__SignPfmm # -- Begin function _Z19__device_stub__SignPfmm
.p2align 4, 0x90
.type _Z19__device_stub__SignPfmm,@function
_Z19__device_stub__SignPfmm: # @_Z19__device_stub__SignPfmm
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4SignPfmm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z19__device_stub__SignPfmm, .Lfunc_end0-_Z19__device_stub__SignPfmm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4SignPfmm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4SignPfmm,@object # @_Z4SignPfmm
.section .rodata,"a",@progbits
.globl _Z4SignPfmm
.p2align 3, 0x0
_Z4SignPfmm:
.quad _Z19__device_stub__SignPfmm
.size _Z4SignPfmm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4SignPfmm"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__SignPfmm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4SignPfmm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void unmarshalling(int *input_itemsets, int *tmp, int max_rows, int max_cols)
{
int i, j;
i = blockIdx.y*blockDim.y+threadIdx.y;
j = blockIdx.x*blockDim.x+threadIdx.x;
if( i >= max_rows || j >= max_cols) return;
if( (i+j) < max_rows) {
input_itemsets[i*max_cols+j] = tmp[(i+j)*max_cols+j];
}
else {
input_itemsets[i*max_cols+j] = tmp[(i+j)*max_cols+j-(i+j-max_rows+1)];
}
} | code for sm_80
Function : _Z13unmarshallingPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R4, R0.reuse, R3, RZ ; /* 0x0000000300047210 */
/* 0x040fe20007ffe0ff */
/*00b0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00c0*/ IMAD R2, R0, c[0x0][0x174], R3.reuse ; /* 0x00005d0000027a24 */
/* 0x100fe200078e0203 */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00e0*/ ISETP.GE.AND P0, PT, R4.reuse, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x040fe20003f06270 */
/*00f0*/ IMAD R5, R4, c[0x0][0x174], R3 ; /* 0x00005d0004057a24 */
/* 0x000fcc00078e0203 */
/*0100*/ IMAD.WIDE R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0207 */
/*0110*/ @!P0 BRA 0x180 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*0120*/ LOP3.LUT R4, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff047212 */
/* 0x000fc800078e33ff */
/*0130*/ IADD3 R4, R5, c[0x0][0x170], R4 ; /* 0x00005c0005047a10 */
/* 0x000fca0007ffe004 */
/*0140*/ IMAD.WIDE R4, R4, R7, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fcc00078e0207 */
/*0150*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0160*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ IMAD.WIDE R4, R5, R7, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fcc00078e0207 */
/*0190*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void unmarshalling(int *input_itemsets, int *tmp, int max_rows, int max_cols)
{
int i, j;
i = blockIdx.y*blockDim.y+threadIdx.y;
j = blockIdx.x*blockDim.x+threadIdx.x;
if( i >= max_rows || j >= max_cols) return;
if( (i+j) < max_rows) {
input_itemsets[i*max_cols+j] = tmp[(i+j)*max_cols+j];
}
else {
input_itemsets[i*max_cols+j] = tmp[(i+j)*max_cols+j-(i+j-max_rows+1)];
}
} | .file "tmpxft_000e7025_00000000-6_unmarshalling.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z13unmarshallingPiS_iiPiS_ii
.type _Z37__device_stub__Z13unmarshallingPiS_iiPiS_ii, @function
_Z37__device_stub__Z13unmarshallingPiS_iiPiS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13unmarshallingPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z13unmarshallingPiS_iiPiS_ii, .-_Z37__device_stub__Z13unmarshallingPiS_iiPiS_ii
.globl _Z13unmarshallingPiS_ii
.type _Z13unmarshallingPiS_ii, @function
_Z13unmarshallingPiS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13unmarshallingPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13unmarshallingPiS_ii, .-_Z13unmarshallingPiS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13unmarshallingPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13unmarshallingPiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void unmarshalling(int *input_itemsets, int *tmp, int max_rows, int max_cols)
{
int i, j;
i = blockIdx.y*blockDim.y+threadIdx.y;
j = blockIdx.x*blockDim.x+threadIdx.x;
if( i >= max_rows || j >= max_cols) return;
if( (i+j) < max_rows) {
input_itemsets[i*max_cols+j] = tmp[(i+j)*max_cols+j];
}
else {
input_itemsets[i*max_cols+j] = tmp[(i+j)*max_cols+j-(i+j-max_rows+1)];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void unmarshalling(int *input_itemsets, int *tmp, int max_rows, int max_cols)
{
int i, j;
i = blockIdx.y*blockDim.y+threadIdx.y;
j = blockIdx.x*blockDim.x+threadIdx.x;
if( i >= max_rows || j >= max_cols) return;
if( (i+j) < max_rows) {
input_itemsets[i*max_cols+j] = tmp[(i+j)*max_cols+j];
}
else {
input_itemsets[i*max_cols+j] = tmp[(i+j)*max_cols+j-(i+j-max_rows+1)];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void unmarshalling(int *input_itemsets, int *tmp, int max_rows, int max_cols)
{
int i, j;
i = blockIdx.y*blockDim.y+threadIdx.y;
j = blockIdx.x*blockDim.x+threadIdx.x;
if( i >= max_rows || j >= max_cols) return;
if( (i+j) < max_rows) {
input_itemsets[i*max_cols+j] = tmp[(i+j)*max_cols+j];
}
else {
input_itemsets[i*max_cols+j] = tmp[(i+j)*max_cols+j-(i+j-max_rows+1)];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13unmarshallingPiS_ii
.globl _Z13unmarshallingPiS_ii
.p2align 8
.type _Z13unmarshallingPiS_ii,@function
_Z13unmarshallingPiS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
v_add_nc_u32_e32 v4, v1, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v3, v4, s5
v_cmpx_le_i32_e64 s4, v4
s_xor_b32 s2, exec_lo, s2
v_not_b32_e32 v2, v4
v_add_nc_u32_e32 v4, s4, v1
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v2, v4, v2, v3
s_and_not1_saveexec_b32 s2, s2
v_add_nc_u32_e32 v2, v3, v1
s_or_b32 exec_lo, exec_lo, s2
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v4, v[2:3], off
v_mad_u64_u32 v[2:3], null, v0, s5, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13unmarshallingPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13unmarshallingPiS_ii, .Lfunc_end0-_Z13unmarshallingPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13unmarshallingPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13unmarshallingPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void unmarshalling(int *input_itemsets, int *tmp, int max_rows, int max_cols)
{
int i, j;
i = blockIdx.y*blockDim.y+threadIdx.y;
j = blockIdx.x*blockDim.x+threadIdx.x;
if( i >= max_rows || j >= max_cols) return;
if( (i+j) < max_rows) {
input_itemsets[i*max_cols+j] = tmp[(i+j)*max_cols+j];
}
else {
input_itemsets[i*max_cols+j] = tmp[(i+j)*max_cols+j-(i+j-max_rows+1)];
}
} | .text
.file "unmarshalling.hip"
.globl _Z28__device_stub__unmarshallingPiS_ii # -- Begin function _Z28__device_stub__unmarshallingPiS_ii
.p2align 4, 0x90
.type _Z28__device_stub__unmarshallingPiS_ii,@function
_Z28__device_stub__unmarshallingPiS_ii: # @_Z28__device_stub__unmarshallingPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13unmarshallingPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__unmarshallingPiS_ii, .Lfunc_end0-_Z28__device_stub__unmarshallingPiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13unmarshallingPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13unmarshallingPiS_ii,@object # @_Z13unmarshallingPiS_ii
.section .rodata,"a",@progbits
.globl _Z13unmarshallingPiS_ii
.p2align 3, 0x0
_Z13unmarshallingPiS_ii:
.quad _Z28__device_stub__unmarshallingPiS_ii
.size _Z13unmarshallingPiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13unmarshallingPiS_ii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__unmarshallingPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13unmarshallingPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13unmarshallingPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x174], PT ; /* 0x00005d0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x170], P0 ; /* 0x00005c0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IADD3 R4, R0.reuse, R3, RZ ; /* 0x0000000300047210 */
/* 0x040fe20007ffe0ff */
/*00b0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00c0*/ IMAD R2, R0, c[0x0][0x174], R3.reuse ; /* 0x00005d0000027a24 */
/* 0x100fe200078e0203 */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00e0*/ ISETP.GE.AND P0, PT, R4.reuse, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x040fe20003f06270 */
/*00f0*/ IMAD R5, R4, c[0x0][0x174], R3 ; /* 0x00005d0004057a24 */
/* 0x000fcc00078e0203 */
/*0100*/ IMAD.WIDE R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0207 */
/*0110*/ @!P0 BRA 0x180 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*0120*/ LOP3.LUT R4, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff047212 */
/* 0x000fc800078e33ff */
/*0130*/ IADD3 R4, R5, c[0x0][0x170], R4 ; /* 0x00005c0005047a10 */
/* 0x000fca0007ffe004 */
/*0140*/ IMAD.WIDE R4, R4, R7, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fcc00078e0207 */
/*0150*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0160*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ IMAD.WIDE R4, R5, R7, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fcc00078e0207 */
/*0190*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13unmarshallingPiS_ii
.globl _Z13unmarshallingPiS_ii
.p2align 8
.type _Z13unmarshallingPiS_ii,@function
_Z13unmarshallingPiS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
v_add_nc_u32_e32 v4, v1, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_mul_lo_u32 v3, v4, s5
v_cmpx_le_i32_e64 s4, v4
s_xor_b32 s2, exec_lo, s2
v_not_b32_e32 v2, v4
v_add_nc_u32_e32 v4, s4, v1
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v2, v4, v2, v3
s_and_not1_saveexec_b32 s2, s2
v_add_nc_u32_e32 v2, v3, v1
s_or_b32 exec_lo, exec_lo, s2
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v4, v[2:3], off
v_mad_u64_u32 v[2:3], null, v0, s5, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13unmarshallingPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13unmarshallingPiS_ii, .Lfunc_end0-_Z13unmarshallingPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13unmarshallingPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13unmarshallingPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e7025_00000000-6_unmarshalling.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z13unmarshallingPiS_iiPiS_ii
.type _Z37__device_stub__Z13unmarshallingPiS_iiPiS_ii, @function
_Z37__device_stub__Z13unmarshallingPiS_iiPiS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13unmarshallingPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z13unmarshallingPiS_iiPiS_ii, .-_Z37__device_stub__Z13unmarshallingPiS_iiPiS_ii
.globl _Z13unmarshallingPiS_ii
.type _Z13unmarshallingPiS_ii, @function
_Z13unmarshallingPiS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13unmarshallingPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13unmarshallingPiS_ii, .-_Z13unmarshallingPiS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13unmarshallingPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13unmarshallingPiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "unmarshalling.hip"
.globl _Z28__device_stub__unmarshallingPiS_ii # -- Begin function _Z28__device_stub__unmarshallingPiS_ii
.p2align 4, 0x90
.type _Z28__device_stub__unmarshallingPiS_ii,@function
_Z28__device_stub__unmarshallingPiS_ii: # @_Z28__device_stub__unmarshallingPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13unmarshallingPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__unmarshallingPiS_ii, .Lfunc_end0-_Z28__device_stub__unmarshallingPiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13unmarshallingPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13unmarshallingPiS_ii,@object # @_Z13unmarshallingPiS_ii
.section .rodata,"a",@progbits
.globl _Z13unmarshallingPiS_ii
.p2align 3, 0x0
_Z13unmarshallingPiS_ii:
.quad _Z28__device_stub__unmarshallingPiS_ii
.size _Z13unmarshallingPiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13unmarshallingPiS_ii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__unmarshallingPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13unmarshallingPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<iostream>
#include<stdio.h>
#include<stdlib.h>
#include <cuda.h>
#include <math.h>
#define BLOCK_SIZE 1024
// Kernel for the first iteration of parallel scan
__global__ void parallelScan(float *d_out, float *d_in, int length) {
volatile extern __shared__ double sharedData[];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int threadx = threadIdx.x;
// load the data into the shared memory
sharedData[threadx] = d_in[tid];
__syncthreads();
int pout = 0; int pin = 1;
if (tid < length) {
for (int offset = 1; offset < blockDim.x; offset <<= 1) {
pout = 1 - pout;
pin = 1 - pin;
if (threadx >= offset) {
sharedData[pout * blockDim.x + threadx] = sharedData[pin * blockDim.x + threadx] + sharedData[pin * blockDim.x + threadx - offset];
} else {
sharedData[pout * blockDim.x + threadx] = sharedData[pin * blockDim.x + threadx];
}
__syncthreads();
}
d_out[tid] = sharedData[pout * blockDim.x + threadx];
//save the sum of the block back to d_in
if (threadx == blockDim.x - 1) d_in[tid] = sharedData[pout * blockDim.x + threadx];
}
}
__global__ void addPreSums(float *d_out, float *d_in)
{
volatile extern __shared__ double sharedData[];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int bid = blockIdx.x + 1;
int threadx = threadIdx.x;
int bDim = blockDim.x;
//load seperatedly scanned blocks (with one block offset)
sharedData[threadx] = d_out[tid + bDim];
//each thread adds the previous sums stored in the d_in
for (int i=0; i<bid; i++) {
sharedData[threadx] += d_in[i*bDim + bDim - 1];
}
__syncthreads();
//store the sums back to the correct position
d_out[tid + bDim] = sharedData[threadx];
}
// The function starts the prefix scan on values from d_in
void prefixScan(float * d_in, float *d_out, int num)
{
int blockx = (num + BLOCK_SIZE - 1)/BLOCK_SIZE; //blockx < 2^14, not exceeding the maximum
dim3 dimGrid(blockx, 1, 1);
dim3 dimBlock(BLOCK_SIZE, 1, 1);
parallelScan<<<dimGrid, dimBlock, sizeof(double)*BLOCK_SIZE*2>>>(d_out, d_in, num);
//when there is one more block
if (blockx > 1) {
//launch with one less block since we do not need to add previous sum for the very first block
addPreSums<<<blockx - 1, BLOCK_SIZE, sizeof(double)*(BLOCK_SIZE)>>>(d_out,d_in);
}
}
int checkResults(float*res, float* cudaRes,int length)
{
int nDiffs=0;
const float smallVal = 0.3f; // Keeping this extra high as we have repetitive addition and sequence matters
for(int i=0; i<length; i++)
if(fabs(cudaRes[i]-res[i])>smallVal){
nDiffs++;
}
return nDiffs;
}
void initializeArray(FILE* fp,float* arr, int nElements)
{
for( int i=0; i<nElements; i++){
int r=fscanf(fp,"%f",&arr[i]);
if(r == EOF){
rewind(fp);
}
arr[i]-=5; // This is to make the data zero mean. Otherwise we reach large numbers and lose precision
}
}
void inclusiveScan_SEQ(float *in, float *out,int length) {
float sum=0.f;
for (int i =0; i < length; i++) {
sum+=in[i];
out[i]=sum;
}
}
int main(int argc, char* argv[]) {
if(argc!=2){
printf("Usage %s N\n",argv[0]);
return 1;
}
int N=atoi(argv[1]);
FILE *fp = fopen("problem1.inp","r");
int size = N * sizeof(float);
//allocate resources
float *in = (float *)malloc(size);
float *out = (float *)malloc(size);
float *cuda_out= (float *)malloc(size);
float time = 0.f;
initializeArray(fp,in, N);
//start inclusive timing
cudaEvent_t startIn,stopIn;
cudaEventCreate(&startIn);
cudaEventCreate(&stopIn);
cudaEventRecord(startIn, 0);
float *d_in;
float *d_out;
cudaMalloc(&d_in, size);
cudaMalloc(&d_out, size);
cudaMemcpy(d_in, in, size, cudaMemcpyHostToDevice);
prefixScan(d_in, d_out, N);
cudaMemcpy(cuda_out, d_out, size, cudaMemcpyDeviceToHost);
//stop inclusive timing
cudaEventRecord(stopIn, 0);
cudaEventSynchronize(stopIn);
cudaEventElapsedTime(&time, startIn, stopIn);
cudaEventDestroy(startIn);
cudaEventDestroy(stopIn);
inclusiveScan_SEQ(in, out,N);
int nDiffs = checkResults(out, cuda_out,N);
if(nDiffs)printf("Test Failed\n"); // This should never print
printf("%d\n%f\n%f\n",N,cuda_out[N-1],time);
//printf("%f\n", time);
//free resources
cudaFree(d_in);cudaFree(d_out);free(in); free(out); free(cuda_out);
return 0;
} | code for sm_80
Function : _Z10addPreSumsPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R12, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0c7435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R16, SR_CTAID.X ; /* 0x0000000000107919 */
/* 0x000e620000002500 */
/*0050*/ IADD3 R2, R0, c[0x0][0x0], RZ ; /* 0x0000000000027a10 */
/* 0x001fca0007ffe0ff */
/*0060*/ IMAD R3, R16, c[0x0][0x0], R2 ; /* 0x0000000010037a24 */
/* 0x002fc800078e0202 */
/*0070*/ IMAD.WIDE R2, R3, R12, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e020c */
/*0080*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1900 */
/*0090*/ IADD3 R13, R16, 0x1, RZ ; /* 0x00000001100d7810 */
/* 0x000fc80007ffe0ff */
/*00a0*/ ISETP.GE.AND P0, PT, R13, 0x1, PT ; /* 0x000000010d00780c */
/* 0x000fe20003f06270 */
/*00b0*/ F2F.F64.F32 R4, R4 ; /* 0x0000000400047310 */
/* 0x004e240000201800 */
/*00c0*/ STS.64 [R0.X8], R4 ; /* 0x0000000400007388 */
/* 0x0011f40000008a00 */
/*00d0*/ @!P0 BRA 0xe50 ; /* 0x00000d7000008947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R16, 0x3, PT ; /* 0x000000031000780c */
/* 0x000fe40003f06070 */
/*00f0*/ LOP3.LUT R13, R13, 0x3, RZ, 0xc0, !PT ; /* 0x000000030d0d7812 */
/* 0x000fc400078ec0ff */
/*0100*/ MOV R14, RZ ; /* 0x000000ff000e7202 */
/* 0x000fd20000000f00 */
/*0110*/ @!P0 BRA 0xd60 ; /* 0x00000c4000008947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R16, -R13, R16, RZ ; /* 0x000000100d107210 */
/* 0x000fe20007ffe1ff */
/*0130*/ HFMA2.MMA R14, -RZ, RZ, 0, 0 ; /* 0x00000000ff0e7435 */
/* 0x000fe200000001ff */
/*0140*/ MOV R15, c[0x0][0x0] ; /* 0x00000000000f7a02 */
/* 0x000fe40000000f00 */
/*0150*/ ISETP.GT.AND P0, PT, R16, -0x1, PT ; /* 0xffffffff1000780c */
/* 0x000fe40003f04270 */
/*0160*/ IADD3 R9, R15, -0x1, RZ ; /* 0xffffffff0f097810 */
/* 0x000fca0007ffe0ff */
/*0170*/ IMAD.WIDE R8, R9, R12, c[0x0][0x168] ; /* 0x00005a0009087625 */
/* 0x000fcc00078e020c */
/*0180*/ @!P0 BRA 0xba0 ; /* 0x00000a1000008947 */
/* 0x000fea0003800000 */
/*0190*/ IADD3 R4, R16, 0x1, RZ ; /* 0x0000000110047810 */
/* 0x001fe40007ffe0ff */
/*01a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*01b0*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fda0003f24270 */
/*01c0*/ @!P1 BRA 0x820 ; /* 0x0000065000009947 */
/* 0x000fea0003800000 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01e0*/ LDG.E R25, [R8.64] ; /* 0x0000000408197981 */
/* 0x000ea2000c1e1900 */
/*01f0*/ IMAD.WIDE R10, R15, 0x4, R8 ; /* 0x000000040f0a7825 */
/* 0x000fc600078e0208 */
/*0200*/ LDS.64 R6, [R0.X8] ; /* 0x0000000000067984 */
/* 0x001e280000008a00 */
/*0210*/ LDG.E R28, [R10.64] ; /* 0x000000040a1c7981 */
/* 0x000ee2000c1e1900 */
/*0220*/ IMAD.WIDE R26, R15, 0x4, R10 ; /* 0x000000040f1a7825 */
/* 0x000fca00078e020a */
/*0230*/ LDG.E R18, [R26.64] ; /* 0x000000041a127981 */
/* 0x000122000c1e1900 */
/*0240*/ IMAD.WIDE R4, R15, 0x4, R26 ; /* 0x000000040f047825 */
/* 0x000fca00078e021a */
/*0250*/ LDG.E R17, [R4.64] ; /* 0x0000000404117981 */
/* 0x0002a2000c1e1900 */
/*0260*/ IMAD.WIDE R22, R15, 0x4, R4 ; /* 0x000000040f167825 */
/* 0x000fca00078e0204 */
/*0270*/ LDG.E R21, [R22.64] ; /* 0x0000000416157981 */
/* 0x0002e4000c1e1900 */
/*0280*/ IMAD.WIDE R22, R15, 0x4, R22 ; /* 0x000000040f167825 */
/* 0x002fca00078e0216 */
/*0290*/ LDG.E R20, [R22.64] ; /* 0x0000000416147981 */
/* 0x000922000c1e1900 */
/*02a0*/ IMAD.WIDE R4, R15, 0x4, R22 ; /* 0x000000040f047825 */
/* 0x000fca00078e0216 */
/*02b0*/ LDG.E R19, [R4.64] ; /* 0x0000000404137981 */
/* 0x000322000c1e1900 */
/*02c0*/ F2F.F64.F32 R8, R25 ; /* 0x0000001900087310 */
/* 0x004e240000201800 */
/*02d0*/ DADD R26, R8, R6 ; /* 0x00000000081a7229 */
/* 0x0010a40000000006 */
/*02e0*/ IMAD.WIDE R8, R15, 0x4, R4 ; /* 0x000000040f087825 */
/* 0x001fca00078e0204 */
/*02f0*/ STS.64 [R0.X8], R26 ; /* 0x0000001a00007388 */
/* 0x004fe80000008a00 */
/*0300*/ LDS.64 R6, [R0.X8] ; /* 0x0000000000067984 */
/* 0x000e280000008a00 */
/*0310*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000562000c1e1900 */
/*0320*/ F2F.F64.F32 R10, R28 ; /* 0x0000001c000a7310 */
/* 0x008e220000201800 */
/*0330*/ IMAD.WIDE R4, R15, 0x4, R8 ; /* 0x000000040f047825 */
/* 0x002fca00078e0208 */
/*0340*/ LDG.E R25, [R4.64] ; /* 0x0000000404197981 */
/* 0x0002e2000c1e1900 */
/*0350*/ DADD R10, R10, R6 ; /* 0x000000000a0a7229 */
/* 0x001e0e0000000006 */
/*0360*/ STS.64 [R0.X8], R10 ; /* 0x0000000a00007388 */
/* 0x001fe80000008a00 */
/*0370*/ LDS.64 R6, [R0.X8] ; /* 0x0000000000067984 */
/* 0x000e220000008a00 */
/*0380*/ F2F.F64.F32 R22, R18 ; /* 0x0000001200167310 */
/* 0x010e220000201800 */
/*0390*/ IMAD.WIDE R8, R15, 0x4, R4 ; /* 0x000000040f087825 */
/* 0x004fca00078e0204 */
/*03a0*/ LDG.E R28, [R8.64] ; /* 0x00000004081c7981 */
/* 0x000522000c1e1900 */
/*03b0*/ DADD R22, R22, R6 ; /* 0x0000000016167229 */
/* 0x001e0e0000000006 */
/*03c0*/ STS.64 [R0.X8], R22 ; /* 0x0000001600007388 */
/* 0x001fe80000008a00 */
/*03d0*/ LDS.64 R6, [R0.X8] ; /* 0x0000000000067984 */
/* 0x000e220000008a00 */
/*03e0*/ F2F.F64.F32 R26, R17 ; /* 0x00000011001a7310 */
/* 0x000e220000201800 */
/*03f0*/ IMAD.WIDE R4, R15, 0x4, R8 ; /* 0x000000040f047825 */
/* 0x002fca00078e0208 */
/*0400*/ LDG.E R18, [R4.64] ; /* 0x0000000404127981 */
/* 0x000322000c1e1900 */
/*0410*/ DADD R26, R26, R6 ; /* 0x000000001a1a7229 */
/* 0x001e0e0000000006 */
/*0420*/ STS.64 [R0.X8], R26 ; /* 0x0000001a00007388 */
/* 0x001fe80000008a00 */
/*0430*/ LDS.64 R6, [R0.X8] ; /* 0x0000000000067984 */
/* 0x000e220000008a00 */
/*0440*/ F2F.F64.F32 R10, R21 ; /* 0x00000015000a7310 */
/* 0x000e220000201800 */
/*0450*/ IMAD.WIDE R8, R15, 0x4, R4 ; /* 0x000000040f087825 */
/* 0x004fca00078e0204 */
/*0460*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000522000c1e1900 */
/*0470*/ DADD R10, R10, R6 ; /* 0x000000000a0a7229 */
/* 0x001e0e0000000006 */
/*0480*/ STS.64 [R0.X8], R10 ; /* 0x0000000a00007388 */
/* 0x001fe80000008a00 */
/*0490*/ LDS.64 R6, [R0.X8] ; /* 0x0000000000067984 */
/* 0x000e220000008a00 */
/*04a0*/ F2F.F64.F32 R22, R20 ; /* 0x0000001400167310 */
/* 0x000e220000201800 */
/*04b0*/ IMAD.WIDE R4, R15, 0x4, R8 ; /* 0x000000040f047825 */
/* 0x002fca00078e0208 */
/*04c0*/ LDG.E R21, [R4.64] ; /* 0x0000000404157981 */
/* 0x000322000c1e1900 */
/*04d0*/ DADD R22, R22, R6 ; /* 0x0000000016167229 */
/* 0x001e0e0000000006 */
/*04e0*/ STS.64 [R0.X8], R22 ; /* 0x0000001600007388 */
/* 0x001fe80000008a00 */
/*04f0*/ LDS.64 R6, [R0.X8] ; /* 0x0000000000067984 */
/* 0x000e220000008a00 */
/*0500*/ F2F.F64.F32 R26, R19 ; /* 0x00000013001a7310 */
/* 0x000e220000201800 */
/*0510*/ IMAD.WIDE R8, R15, 0x4, R4 ; /* 0x000000040f087825 */
/* 0x004fca00078e0204 */
/*0520*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000522000c1e1900 */
/*0530*/ DADD R26, R26, R6 ; /* 0x000000001a1a7229 */
/* 0x001e0e0000000006 */
/*0540*/ STS.64 [R0.X8], R26 ; /* 0x0000001a00007388 */
/* 0x001fe80000008a00 */
/*0550*/ LDS.64 R6, [R0.X8] ; /* 0x0000000000067984 */
/* 0x000e220000008a00 */
/*0560*/ F2F.F64.F32 R10, R24 ; /* 0x00000018000a7310 */
/* 0x020e220000201800 */
/*0570*/ IMAD.WIDE R4, R15, 0x4, R8 ; /* 0x000000040f047825 */
/* 0x002fca00078e0208 */
/*0580*/ LDG.E R19, [R4.64] ; /* 0x0000000404137981 */
/* 0x000362000c1e1900 */
/*0590*/ DADD R10, R10, R6 ; /* 0x000000000a0a7229 */
/* 0x001e0e0000000006 */
/*05a0*/ STS.64 [R0.X8], R10 ; /* 0x0000000a00007388 */
/* 0x001fe80000008a00 */
/*05b0*/ LDS.64 R6, [R0.X8] ; /* 0x0000000000067984 */
/* 0x000e220000008a00 */
/*05c0*/ F2F.F64.F32 R22, R25 ; /* 0x0000001900167310 */
/* 0x008e220000201800 */
/*05d0*/ IMAD.WIDE R8, R15, 0x4, R4 ; /* 0x000000040f087825 */
/* 0x004fca00078e0204 */
/*05e0*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000ea2000c1e1900 */
/*05f0*/ DADD R22, R22, R6 ; /* 0x0000000016167229 */
/* 0x001e0e0000000006 */
/*0600*/ STS.64 [R0.X8], R22 ; /* 0x0000001600007388 */
/* 0x001fe80000008a00 */
/*0610*/ LDS.64 R6, [R0.X8] ; /* 0x0000000000067984 */
/* 0x000e220000008a00 */
/*0620*/ F2F.F64.F32 R28, R28 ; /* 0x0000001c001c7310 */
/* 0x010e240000201800 */
/*0630*/ DADD R10, R28, R6 ; /* 0x000000001c0a7229 */
/* 0x001e0e0000000006 */
/*0640*/ STS.64 [R0.X8], R10 ; /* 0x0000000a00007388 */
/* 0x001fe80000008a00 */
/*0650*/ LDS.64 R6, [R0.X8] ; /* 0x0000000000067984 */
/* 0x000e220000008a00 */
/*0660*/ F2F.F64.F32 R4, R18 ; /* 0x0000001200047310 */
/* 0x002e240000201800 */
/*0670*/ DADD R6, R4, R6 ; /* 0x0000000004067229 */
/* 0x001e0e0000000006 */
/*0680*/ STS.64 [R0.X8], R6 ; /* 0x0000000600007388 */
/* 0x001fe80000008a00 */
/*0690*/ LDS.64 R4, [R0.X8] ; /* 0x0000000000047984 */
/* 0x000e220000008a00 */
/*06a0*/ F2F.F64.F32 R22, R17 ; /* 0x0000001100167310 */
/* 0x000e240000201800 */
/*06b0*/ DADD R4, R22, R4 ; /* 0x0000000016047229 */
/* 0x001e0e0000000004 */
/*06c0*/ STS.64 [R0.X8], R4 ; /* 0x0000000400007388 */
/* 0x001fe80000008a00 */
/*06d0*/ LDS.64 R26, [R0.X8] ; /* 0x00000000001a7984 */
/* 0x000e220000008a00 */
/*06e0*/ F2F.F64.F32 R22, R21 ; /* 0x0000001500167310 */
/* 0x000e240000201800 */
/*06f0*/ DADD R22, R22, R26 ; /* 0x0000000016167229 */
/* 0x001e0e000000001a */
/*0700*/ STS.64 [R0.X8], R22 ; /* 0x0000001600007388 */
/* 0x001fe80000008a00 */
/*0710*/ LDS.64 R26, [R0.X8] ; /* 0x00000000001a7984 */
/* 0x000e220000008a00 */
/*0720*/ F2F.F64.F32 R10, R20 ; /* 0x00000014000a7310 */
/* 0x000e240000201800 */
/*0730*/ DADD R10, R10, R26 ; /* 0x000000000a0a7229 */
/* 0x001e0e000000001a */
/*0740*/ STS.64 [R0.X8], R10 ; /* 0x0000000a00007388 */
/* 0x001fe80000008a00 */
/*0750*/ LDS.64 R26, [R0.X8] ; /* 0x00000000001a7984 */
/* 0x000e220000008a00 */
/*0760*/ F2F.F64.F32 R6, R19 ; /* 0x0000001300067310 */
/* 0x020e240000201800 */
/*0770*/ DADD R6, R6, R26 ; /* 0x0000000006067229 */
/* 0x001e0e000000001a */
/*0780*/ STS.64 [R0.X8], R6 ; /* 0x0000000600007388 */
/* 0x001fe80000008a00 */
/*0790*/ LDS.64 R4, [R0.X8] ; /* 0x0000000000047984 */
/* 0x000e220000008a00 */
/*07a0*/ F2F.F64.F32 R24, R24 ; /* 0x0000001800187310 */
/* 0x004e220000201800 */
/*07b0*/ IADD3 R16, R16, -0x10, RZ ; /* 0xfffffff010107810 */
/* 0x000fc80007ffe0ff */
/*07c0*/ ISETP.GT.AND P1, PT, R16, 0xb, PT ; /* 0x0000000b1000780c */
/* 0x000fe20003f24270 */
/*07d0*/ IMAD.WIDE R8, R15, 0x4, R8 ; /* 0x000000040f087825 */
/* 0x000fe200078e0208 */
/*07e0*/ IADD3 R14, R14, 0x10, RZ ; /* 0x000000100e0e7810 */
/* 0x000fe20007ffe0ff */
/*07f0*/ DADD R4, R24, R4 ; /* 0x0000000018047229 */
/* 0x001e0e0000000004 */
/*0800*/ STS.64 [R0.X8], R4 ; /* 0x0000000400007388 */
/* 0x0011e60000008a00 */
/*0810*/ @P1 BRA 0x1e0 ; /* 0xfffff9c000001947 */
/* 0x000fea000383ffff */
/*0820*/ IADD3 R4, R16, 0x1, RZ ; /* 0x0000000110047810 */
/* 0x001fc80007ffe0ff */
/*0830*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*0840*/ @!P1 BRA 0xb80 ; /* 0x0000033000009947 */
/* 0x000fea0003800000 */
/*0850*/ LDG.E R28, [R8.64] ; /* 0x00000004081c7981 */
/* 0x000ea2000c1e1900 */
/*0860*/ IMAD.WIDE R10, R15, 0x4, R8 ; /* 0x000000040f0a7825 */
/* 0x000fc600078e0208 */
/*0870*/ LDS.64 R6, [R0.X8] ; /* 0x0000000000067984 */
/* 0x000e280000008a00 */
/*0880*/ LDG.E R24, [R10.64] ; /* 0x000000040a187981 */
/* 0x000ee2000c1e1900 */
/*0890*/ IMAD.WIDE R22, R15, 0x4, R10 ; /* 0x000000040f167825 */
/* 0x000fca00078e020a */
/*08a0*/ LDG.E R21, [R22.64] ; /* 0x0000000416157981 */
/* 0x000122000c1e1900 */
/*08b0*/ IMAD.WIDE R4, R15, 0x4, R22 ; /* 0x000000040f047825 */
/* 0x000fca00078e0216 */
/*08c0*/ LDG.E R20, [R4.64] ; /* 0x0000000404147981 */
/* 0x000362000c1e1900 */
/*08d0*/ IMAD.WIDE R26, R15, 0x4, R4 ; /* 0x000000040f1a7825 */
/* 0x000fca00078e0204 */
/*08e0*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x0002e4000c1e1900 */
/*08f0*/ IMAD.WIDE R26, R15, 0x4, R26 ; /* 0x000000040f1a7825 */
/* 0x002fca00078e021a */
/*0900*/ LDG.E R18, [R26.64] ; /* 0x000000041a127981 */
/* 0x000f62000c1e1900 */
/*0910*/ IMAD.WIDE R4, R15, 0x4, R26 ; /* 0x000000040f047825 */
/* 0x000fca00078e021a */
/*0920*/ LDG.E R17, [R4.64] ; /* 0x0000000404117981 */
/* 0x000962000c1e1900 */
/*0930*/ F2F.F64.F32 R8, R28 ; /* 0x0000001c00087310 */
/* 0x004e240000201800 */
/*0940*/ DADD R22, R8, R6 ; /* 0x0000000008167229 */
/* 0x0010640000000006 */
/*0950*/ IMAD.WIDE R8, R15, 0x4, R4 ; /* 0x000000040f087825 */
/* 0x001fca00078e0204 */
/*0960*/ STS.64 [R0.X8], R22 ; /* 0x0000001600007388 */
/* 0x002be80000008a00 */
/*0970*/ LDS.64 R6, [R0.X8] ; /* 0x0000000000067984 */
/* 0x000e280000008a00 */
/*0980*/ LDG.E R25, [R8.64] ; /* 0x0000000408197981 */
/* 0x0002a2000c1e1900 */
/*0990*/ F2F.F64.F32 R10, R24 ; /* 0x00000018000a7310 */
/* 0x008e220000201800 */
/*09a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*09b0*/ IADD3 R14, R14, 0x8, RZ ; /* 0x000000080e0e7810 */
/* 0x000fe40007ffe0ff */
/*09c0*/ IADD3 R16, R16, -0x8, RZ ; /* 0xfffffff810107810 */
/* 0x000fc60007ffe0ff */
/*09d0*/ F2F.F64.F32 R4, R21 ; /* 0x0000001500047310 */
/* 0x010ee20000201800 */
/*09e0*/ IMAD.WIDE R8, R15, 0x4, R8 ; /* 0x000000040f087825 */
/* 0x002fce00078e0208 */
/*09f0*/ F2F.F64.F32 R22, R20 ; /* 0x0000001400167310 */
/* 0x020e620000201800 */
/*0a00*/ DADD R10, R10, R6 ; /* 0x000000000a0a7229 */
/* 0x001e0e0000000006 */
/*0a10*/ STS.64 [R0.X8], R10 ; /* 0x0000000a00007388 */
/* 0x0011e80000008a00 */
/*0a20*/ LDS.64 R6, [R0.X8] ; /* 0x0000000000067984 */
/* 0x000ee20000008a00 */
/*0a30*/ F2F.F64.F32 R10, R18 ; /* 0x00000012000a7310 */
/* 0x001fe20000201800 */
/*0a40*/ DADD R6, R4, R6 ; /* 0x0000000004067229 */
/* 0x008e0e0000000006 */
/*0a50*/ STS.64 [R0.X8], R6 ; /* 0x0000000600007388 */
/* 0x0011e80000008a00 */
/*0a60*/ LDS.64 R4, [R0.X8] ; /* 0x0000000000047984 */
/* 0x000e620000008a00 */
/*0a70*/ F2F.F64.F32 R6, R17 ; /* 0x0000001100067310 */
/* 0x001fe20000201800 */
/*0a80*/ DADD R4, R22, R4 ; /* 0x0000000016047229 */
/* 0x00204e0000000004 */
/*0a90*/ F2F.F64.F32 R22, R19 ; /* 0x0000001300167310 */
/* 0x001e220000201800 */
/*0aa0*/ STS.64 [R0.X8], R4 ; /* 0x0000000400007388 */
/* 0x002fe80000008a00 */
/*0ab0*/ LDS.64 R26, [R0.X8] ; /* 0x00000000001a7984 */
/* 0x000e240000008a00 */
/*0ac0*/ DADD R22, R22, R26 ; /* 0x0000000016167229 */
/* 0x001e0e000000001a */
/*0ad0*/ STS.64 [R0.X8], R22 ; /* 0x0000001600007388 */
/* 0x001fe80000008a00 */
/*0ae0*/ LDS.64 R26, [R0.X8] ; /* 0x00000000001a7984 */
/* 0x000e240000008a00 */
/*0af0*/ DADD R10, R10, R26 ; /* 0x000000000a0a7229 */
/* 0x001e0e000000001a */
/*0b00*/ STS.64 [R0.X8], R10 ; /* 0x0000000a00007388 */
/* 0x001fe80000008a00 */
/*0b10*/ LDS.64 R20, [R0.X8] ; /* 0x0000000000147984 */
/* 0x000e240000008a00 */
/*0b20*/ DADD R6, R6, R20 ; /* 0x0000000006067229 */
/* 0x001e0e0000000014 */
/*0b30*/ STS.64 [R0.X8], R6 ; /* 0x0000000600007388 */
/* 0x001fe20000008a00 */
/*0b40*/ F2F.F64.F32 R4, R25 ; /* 0x0000001900047310 */
/* 0x004e260000201800 */
/*0b50*/ LDS.64 R20, [R0.X8] ; /* 0x0000000000147984 */
/* 0x000e240000008a00 */
/*0b60*/ DADD R4, R4, R20 ; /* 0x0000000004047229 */
/* 0x001e0e0000000014 */
/*0b70*/ STS.64 [R0.X8], R4 ; /* 0x0000000400007388 */
/* 0x0011e80000008a00 */
/*0b80*/ ISETP.NE.OR P0, PT, R16, -0x1, P0 ; /* 0xffffffff1000780c */
/* 0x000fda0000705670 */
/*0b90*/ @!P0 BRA 0xd60 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0ba0*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000ea2000c1e1900 */
/*0bb0*/ IMAD.WIDE R20, R15, 0x4, R8 ; /* 0x000000040f147825 */
/* 0x000fc600078e0208 */
/*0bc0*/ LDS.64 R18, [R0.X8] ; /* 0x0000000000127984 */
/* 0x000e680000008a00 */
/*0bd0*/ LDG.E R24, [R20.64] ; /* 0x0000000414187981 */
/* 0x000ee2000c1e1900 */
/*0be0*/ IMAD.WIDE R22, R15, 0x4, R20 ; /* 0x000000040f167825 */
/* 0x000fca00078e0214 */
/*0bf0*/ LDG.E R7, [R22.64] ; /* 0x0000000416077981 */
/* 0x000f22000c1e1900 */
/*0c00*/ IMAD.WIDE R4, R15, 0x4, R22 ; /* 0x000000040f047825 */
/* 0x001fca00078e0216 */
/*0c10*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000f62000c1e1900 */
/*0c20*/ IADD3 R16, R16, -0x4, RZ ; /* 0xfffffffc10107810 */
/* 0x000fe40007ffe0ff */
/*0c30*/ IADD3 R14, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fe40007ffe0ff */
/*0c40*/ ISETP.NE.AND P0, PT, R16, -0x1, PT ; /* 0xffffffff1000780c */
/* 0x000fe20003f05270 */
/*0c50*/ F2F.F64.F32 R10, R17 ; /* 0x00000011000a7310 */
/* 0x004e700000201800 */
/*0c60*/ F2F.F64.F32 R8, R24 ; /* 0x0000001800087310 */
/* 0x008e220000201800 */
/*0c70*/ DADD R10, R10, R18 ; /* 0x000000000a0a7229 */
/* 0x002e4e0000000012 */
/*0c80*/ STS.64 [R0.X8], R10 ; /* 0x0000000a00007388 */
/* 0x002fe80000008a00 */
/*0c90*/ LDS.64 R18, [R0.X8] ; /* 0x0000000000127984 */
/* 0x000e240000008a00 */
/*0ca0*/ DADD R8, R8, R18 ; /* 0x0000000008087229 */
/* 0x0018240000000012 */
/*0cb0*/ F2F.F64.F32 R18, R7 ; /* 0x0000000700127310 */
/* 0x010e6a0000201800 */
/*0cc0*/ STS.64 [R0.X8], R8 ; /* 0x0000000800007388 */
/* 0x0011e80000008a00 */
/*0cd0*/ LDS.64 R20, [R0.X8] ; /* 0x0000000000147984 */
/* 0x000e620000008a00 */
/*0ce0*/ IMAD.WIDE R8, R15, 0x4, R4 ; /* 0x000000040f087825 */
/* 0x001fe200078e0204 */
/*0cf0*/ DADD R18, R18, R20 ; /* 0x0000000012127229 */
/* 0x002a040000000014 */
/*0d00*/ F2F.F64.F32 R20, R6 ; /* 0x0000000600147310 */
/* 0x020e6a0000201800 */
/*0d10*/ STS.64 [R0.X8], R18 ; /* 0x0000001200007388 */
/* 0x001fe80000008a00 */
/*0d20*/ LDS.64 R22, [R0.X8] ; /* 0x0000000000167984 */
/* 0x000e640000008a00 */
/*0d30*/ DADD R20, R20, R22 ; /* 0x0000000014147229 */
/* 0x002e0e0000000016 */
/*0d40*/ STS.64 [R0.X8], R20 ; /* 0x0000001400007388 */
/* 0x0011e40000008a00 */
/*0d50*/ @P0 BRA 0xba0 ; /* 0xfffffe4000000947 */
/* 0x001fea000383ffff */
/*0d60*/ ISETP.NE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fda0003f05270 */
/*0d70*/ @!P0 BRA 0xe50 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0d80*/ IADD3 R14, R14, 0x1, RZ ; /* 0x000000010e0e7810 */
/* 0x000fe40007ffe0ff */
/*0d90*/ MOV R11, c[0x0][0x0] ; /* 0x00000000000b7a02 */
/* 0x000fca0000000f00 */
/*0da0*/ IMAD R5, R14, R11, -0x1 ; /* 0xffffffff0e057424 */
/* 0x001fc800078e020b */
/*0db0*/ IMAD.WIDE R4, R5, R12, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e020c */
/*0dc0*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x0010a2000c1e1900 */
/*0dd0*/ IADD3 R13, R13, -0x1, RZ ; /* 0xffffffff0d0d7810 */
/* 0x000fc60007ffe0ff */
/*0de0*/ LDS.64 R8, [R0.X8] ; /* 0x0000000000087984 */
/* 0x000e620000008a00 */
/*0df0*/ ISETP.NE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe20003f05270 */
/*0e00*/ IMAD.WIDE R4, R11, 0x4, R4 ; /* 0x000000040b047825 */
/* 0x001fe200078e0204 */
/*0e10*/ F2F.F64.F32 R6, R10 ; /* 0x0000000a00067310 */
/* 0x004e640000201800 */
/*0e20*/ DADD R6, R6, R8 ; /* 0x0000000006067229 */
/* 0x002e0e0000000008 */
/*0e30*/ STS.64 [R0.X8], R6 ; /* 0x0000000600007388 */
/* 0x0011e40000008a00 */
/*0e40*/ @P0 BRA 0xdc0 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0e50*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0e60*/ LDS.64 R4, [R0.X8] ; /* 0x0000000000047984 */
/* 0x001e240000008a00 */
/*0e70*/ F2F.F32.F64 R5, R4 ; /* 0x0000000400057310 */
/* 0x001e240000301000 */
/*0e80*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0e90*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ea0*/ BRA 0xea0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z12parallelScanPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R3, c[0x0][0x0], R0 ; /* 0x0000000003047a24 */
/* 0x001fc800078e0200 */
/*0060*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R6, [R2.64] ; /* 0x0000000602067981 */
/* 0x000ea2000c1e1900 */
/*0080*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fe20003f06270 */
/*0090*/ F2F.F64.F32 R6, R6 ; /* 0x0000000600067310 */
/* 0x004e240000201800 */
/*00a0*/ STS.64 [R0.X8], R6 ; /* 0x0000000600007388 */
/* 0x0011e80000008a00 */
/*00b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff057624 */
/* 0x001fe400078e00ff */
/*00e0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fc600078e00ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R5, 0x2, PT ; /* 0x000000020500780c */
/* 0x000fe40003f06070 */
/*0100*/ SHF.L.U32 R5, R0, 0x3, RZ ; /* 0x0000000300057819 */
/* 0x000fd600000006ff */
/*0110*/ @!P0 BRA 0x260 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0120*/ HFMA2.MMA R11, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff0b7435 */
/* 0x000fe200000001ff */
/*0130*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e00ff */
/*0140*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1 ; /* 0x00000001ff0e7424 */
/* 0x000fce00078e00ff */
/*0150*/ ISETP.GE.AND P0, PT, R0, R11, PT ; /* 0x0000000b0000720c */
/* 0x000fe40003f06270 */
/*0160*/ IADD3 R14, -R14, 0x1, RZ ; /* 0x000000010e0e7810 */
/* 0x000fe40007ffe1ff */
/*0170*/ IADD3 R10, -R10, 0x1, RZ ; /* 0x000000010a0a7810 */
/* 0x000fc60007ffe1ff */
/*0180*/ IMAD R8, R14, c[0x0][0x0], RZ ; /* 0x000000000e087a24 */
/* 0x000fe400078e02ff */
/*0190*/ IMAD R12, R10, c[0x0][0x0], RZ ; /* 0x000000000a0c7a24 */
/* 0x000fe400078e02ff */
/*01a0*/ IMAD R6, R8, 0x8, R5 ; /* 0x0000000808067824 */
/* 0x000fe400078e0205 */
/*01b0*/ @P0 IADD3 R13, -R11.reuse, R8, R0 ; /* 0x000000080b0d0210 */
/* 0x040fe20007ffe100 */
/*01c0*/ IMAD.SHL.U32 R11, R11, 0x2, RZ ; /* 0x000000020b0b7824 */
/* 0x000fe200078e00ff */
/*01d0*/ LEA R15, R12, R5, 0x3 ; /* 0x000000050c0f7211 */
/* 0x000fe400078e18ff */
/*01e0*/ LDS.64 R6, [R6] ; /* 0x0000000006067984 */
/* 0x000fe80000000a00 */
/*01f0*/ @P0 LDS.64 R8, [R13.X8] ; /* 0x000000000d080984 */
/* 0x000e240000008a00 */
/*0200*/ @P0 DADD R8, R6, R8 ; /* 0x0000000006080229 */
/* 0x001e0e0000000008 */
/*0210*/ @P0 STS.64 [R15], R8 ; /* 0x000000080f000388 */
/* 0x0011e80000000a00 */
/*0220*/ @!P0 STS.64 [R15], R6 ; /* 0x000000060f008388 */
/* 0x0001e80000000a00 */
/*0230*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0240*/ ISETP.GE.U32.AND P0, PT, R11, c[0x0][0x0], PT ; /* 0x000000000b007a0c */
/* 0x000fda0003f06070 */
/*0250*/ @!P0 BRA 0x150 ; /* 0xfffffef000008947 */
/* 0x001fea000383ffff */
/*0260*/ IMAD R10, R10, c[0x0][0x0], RZ ; /* 0x000000000a0a7a24 */
/* 0x000fe200078e02ff */
/*0270*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0280*/ LEA R8, P1, R4, c[0x0][0x160], 0x2 ; /* 0x0000580004087a11 */
/* 0x000fe200078210ff */
/*0290*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe4000fffe03f */
/*02a0*/ LEA R10, R10, R5, 0x3 ; /* 0x000000050a0a7211 */
/* 0x000fe400078e18ff */
/*02b0*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fe40000011404 */
/*02c0*/ ISETP.NE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fe2000bf05270 */
/*02d0*/ LDS.64 R6, [R10] ; /* 0x000000000a067984 */
/* 0x000e220000000a00 */
/*02e0*/ LEA.HI.X R9, R4, c[0x0][0x164], R5, 0x2, P1 ; /* 0x0000590004097a11 */
/* 0x000fe200008f1405 */
/*02f0*/ F2F.F32.F64 R7, R6 ; /* 0x0000000600077310 */
/* 0x001e280000301000 */
/*0300*/ STG.E [R8.64], R7 ; /* 0x0000000708007986 */
/* 0x0011ec000c101906 */
/*0310*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0320*/ LDS.64 R4, [R10] ; /* 0x000000000a047984 */
/* 0x000e640000000a00 */
/*0330*/ F2F.F32.F64 R5, R4 ; /* 0x0000000400057310 */
/* 0x002e640000301000 */
/*0340*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101906 */
/*0350*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0360*/ BRA 0x360; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<iostream>
#include<stdio.h>
#include<stdlib.h>
#include <cuda.h>
#include <math.h>
#define BLOCK_SIZE 1024
// Kernel for the first iteration of parallel scan
__global__ void parallelScan(float *d_out, float *d_in, int length) {
volatile extern __shared__ double sharedData[];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int threadx = threadIdx.x;
// load the data into the shared memory
sharedData[threadx] = d_in[tid];
__syncthreads();
int pout = 0; int pin = 1;
if (tid < length) {
for (int offset = 1; offset < blockDim.x; offset <<= 1) {
pout = 1 - pout;
pin = 1 - pin;
if (threadx >= offset) {
sharedData[pout * blockDim.x + threadx] = sharedData[pin * blockDim.x + threadx] + sharedData[pin * blockDim.x + threadx - offset];
} else {
sharedData[pout * blockDim.x + threadx] = sharedData[pin * blockDim.x + threadx];
}
__syncthreads();
}
d_out[tid] = sharedData[pout * blockDim.x + threadx];
//save the sum of the block back to d_in
if (threadx == blockDim.x - 1) d_in[tid] = sharedData[pout * blockDim.x + threadx];
}
}
__global__ void addPreSums(float *d_out, float *d_in)
{
volatile extern __shared__ double sharedData[];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int bid = blockIdx.x + 1;
int threadx = threadIdx.x;
int bDim = blockDim.x;
//load seperatedly scanned blocks (with one block offset)
sharedData[threadx] = d_out[tid + bDim];
//each thread adds the previous sums stored in the d_in
for (int i=0; i<bid; i++) {
sharedData[threadx] += d_in[i*bDim + bDim - 1];
}
__syncthreads();
//store the sums back to the correct position
d_out[tid + bDim] = sharedData[threadx];
}
// The function starts the prefix scan on values from d_in
void prefixScan(float * d_in, float *d_out, int num)
{
int blockx = (num + BLOCK_SIZE - 1)/BLOCK_SIZE; //blockx < 2^14, not exceeding the maximum
dim3 dimGrid(blockx, 1, 1);
dim3 dimBlock(BLOCK_SIZE, 1, 1);
parallelScan<<<dimGrid, dimBlock, sizeof(double)*BLOCK_SIZE*2>>>(d_out, d_in, num);
//when there is one more block
if (blockx > 1) {
//launch with one less block since we do not need to add previous sum for the very first block
addPreSums<<<blockx - 1, BLOCK_SIZE, sizeof(double)*(BLOCK_SIZE)>>>(d_out,d_in);
}
}
int checkResults(float*res, float* cudaRes,int length)
{
int nDiffs=0;
const float smallVal = 0.3f; // Keeping this extra high as we have repetitive addition and sequence matters
for(int i=0; i<length; i++)
if(fabs(cudaRes[i]-res[i])>smallVal){
nDiffs++;
}
return nDiffs;
}
void initializeArray(FILE* fp,float* arr, int nElements)
{
for( int i=0; i<nElements; i++){
int r=fscanf(fp,"%f",&arr[i]);
if(r == EOF){
rewind(fp);
}
arr[i]-=5; // This is to make the data zero mean. Otherwise we reach large numbers and lose precision
}
}
void inclusiveScan_SEQ(float *in, float *out,int length) {
float sum=0.f;
for (int i =0; i < length; i++) {
sum+=in[i];
out[i]=sum;
}
}
int main(int argc, char* argv[]) {
if(argc!=2){
printf("Usage %s N\n",argv[0]);
return 1;
}
int N=atoi(argv[1]);
FILE *fp = fopen("problem1.inp","r");
int size = N * sizeof(float);
//allocate resources
float *in = (float *)malloc(size);
float *out = (float *)malloc(size);
float *cuda_out= (float *)malloc(size);
float time = 0.f;
initializeArray(fp,in, N);
//start inclusive timing
cudaEvent_t startIn,stopIn;
cudaEventCreate(&startIn);
cudaEventCreate(&stopIn);
cudaEventRecord(startIn, 0);
float *d_in;
float *d_out;
cudaMalloc(&d_in, size);
cudaMalloc(&d_out, size);
cudaMemcpy(d_in, in, size, cudaMemcpyHostToDevice);
prefixScan(d_in, d_out, N);
cudaMemcpy(cuda_out, d_out, size, cudaMemcpyDeviceToHost);
//stop inclusive timing
cudaEventRecord(stopIn, 0);
cudaEventSynchronize(stopIn);
cudaEventElapsedTime(&time, startIn, stopIn);
cudaEventDestroy(startIn);
cudaEventDestroy(stopIn);
inclusiveScan_SEQ(in, out,N);
int nDiffs = checkResults(out, cuda_out,N);
if(nDiffs)printf("Test Failed\n"); // This should never print
printf("%d\n%f\n%f\n",N,cuda_out[N-1],time);
//printf("%f\n", time);
//free resources
cudaFree(d_in);cudaFree(d_out);free(in); free(out); free(cuda_out);
return 0;
} | .file "tmpxft_0017eef5_00000000-6_problem1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3676:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3676:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12checkResultsPfS_i
.type _Z12checkResultsPfS_i, @function
_Z12checkResultsPfS_i:
.LFB3670:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L8
movslq %edx, %rdx
leaq 0(,%rdx,4), %r8
movl $0, %eax
movl $0, %edx
movss .LC0(%rip), %xmm1
.L7:
movss (%rsi,%rax), %xmm0
subss (%rdi,%rax), %xmm0
andps %xmm1, %xmm0
comiss .LC1(%rip), %xmm0
seta %cl
movzbl %cl, %ecx
addl %ecx, %edx
addq $4, %rax
cmpq %rax, %r8
jne .L7
.L3:
movl %edx, %eax
ret
.L8:
movl $0, %edx
jmp .L3
.cfi_endproc
.LFE3670:
.size _Z12checkResultsPfS_i, .-_Z12checkResultsPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%f"
.text
.globl _Z15initializeArrayP8_IO_FILEPfi
.type _Z15initializeArrayP8_IO_FILEPfi, @function
_Z15initializeArrayP8_IO_FILEPfi:
.LFB3671:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L17
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r12
movq %rsi, %rbx
movslq %edx, %rdx
leaq (%rsi,%rdx,4), %r14
leaq .LC2(%rip), %r13
jmp .L14
.L13:
movss 0(%rbp), %xmm0
subss .LC3(%rip), %xmm0
movss %xmm0, 0(%rbp)
addq $4, %rbx
cmpq %r14, %rbx
je .L20
.L14:
movq %rbx, %rbp
movq %rbx, %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $-1, %eax
jne .L13
movq %r12, %rdi
call rewind@PLT
jmp .L13
.L20:
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
ret
.cfi_endproc
.LFE3671:
.size _Z15initializeArrayP8_IO_FILEPfi, .-_Z15initializeArrayP8_IO_FILEPfi
.globl _Z17inclusiveScan_SEQPfS_i
.type _Z17inclusiveScan_SEQPfS_i, @function
_Z17inclusiveScan_SEQPfS_i:
.LFB3672:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L21
movslq %edx, %rdx
salq $2, %rdx
movl $0, %eax
pxor %xmm0, %xmm0
.L23:
addss (%rdi,%rax), %xmm0
movss %xmm0, (%rsi,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L23
.L21:
ret
.cfi_endproc
.LFE3672:
.size _Z17inclusiveScan_SEQPfS_i, .-_Z17inclusiveScan_SEQPfS_i
.globl _Z35__device_stub__Z12parallelScanPfS_iPfS_i
.type _Z35__device_stub__Z12parallelScanPfS_iPfS_i, @function
_Z35__device_stub__Z12parallelScanPfS_iPfS_i:
.LFB3698:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12parallelScanPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z35__device_stub__Z12parallelScanPfS_iPfS_i, .-_Z35__device_stub__Z12parallelScanPfS_iPfS_i
.globl _Z12parallelScanPfS_i
.type _Z12parallelScanPfS_i, @function
_Z12parallelScanPfS_i:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12parallelScanPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z12parallelScanPfS_i, .-_Z12parallelScanPfS_i
.globl _Z32__device_stub__Z10addPreSumsPfS_PfS_
.type _Z32__device_stub__Z10addPreSumsPfS_PfS_, @function
_Z32__device_stub__Z10addPreSumsPfS_PfS_:
.LFB3700:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10addPreSumsPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3700:
.size _Z32__device_stub__Z10addPreSumsPfS_PfS_, .-_Z32__device_stub__Z10addPreSumsPfS_PfS_
.globl _Z10addPreSumsPfS_
.type _Z10addPreSumsPfS_, @function
_Z10addPreSumsPfS_:
.LFB3701:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10addPreSumsPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _Z10addPreSumsPfS_, .-_Z10addPreSumsPfS_
.globl _Z10prefixScanPfS_i
.type _Z10prefixScanPfS_i, @function
_Z10prefixScanPfS_i:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r13
movq %rsi, %r12
movl %edx, %ebx
leal 2046(%rdx), %ebp
movl %edx, %eax
addl $1023, %eax
cmovns %eax, %ebp
sarl $10, %ebp
movl %ebp, (%rsp)
movl $1, 4(%rsp)
movl $1024, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $16384, %r8d
movq 12(%rsp), %rdx
movl $1, %ecx
movq (%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L46
.L42:
cmpl $1024, %ebx
jg .L47
.L41:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
movl %ebx, %edx
movq %r13, %rsi
movq %r12, %rdi
call _Z35__device_stub__Z12parallelScanPfS_iPfS_i
jmp .L42
.L47:
movl $1024, 36(%rsp)
movl $1, 40(%rsp)
subl $1, %ebp
movl %ebp, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $8192, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L41
movq %r13, %rsi
movq %r12, %rdi
call _Z32__device_stub__Z10addPreSumsPfS_PfS_
jmp .L41
.cfi_endproc
.LFE3669:
.size _Z10prefixScanPfS_i, .-_Z10prefixScanPfS_i
.section .rodata.str1.1
.LC5:
.string "Usage %s N\n"
.LC6:
.string "r"
.LC7:
.string "problem1.inp"
.LC8:
.string "Test Failed\n"
.LC9:
.string "%d\n%f\n%f\n"
.text
.globl main
.type main, @function
main:
.LFB3673:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
cmpl $2, %edi
je .L49
movq (%rsi), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %eax
.L48:
movq 56(%rsp), %rdx
subq %fs:40, %rdx
jne .L54
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %r14d
leaq .LC6(%rip), %rsi
leaq .LC7(%rip), %rdi
call fopen@PLT
movq %rax, 8(%rsp)
movslq %ebx, %r15
leal 0(,%rbx,4), %ebx
movslq %ebx, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movl $0x00000000, 20(%rsp)
movl %r14d, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call _Z15initializeArrayP8_IO_FILEPfi
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %r14d, %edx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z10prefixScanPfS_i
movl $2, %ecx
movq %rbx, %rdx
movq 48(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movl %r14d, %edx
movq %r13, %rsi
movq %r12, %rdi
call _Z17inclusiveScan_SEQPfS_i
movl %r14d, %edx
movq %rbp, %rsi
movq %r13, %rdi
call _Z12checkResultsPfS_i
testl %eax, %eax
jne .L55
.L51:
pxor %xmm0, %xmm0
cvtss2sd -4(%rbp,%r15,4), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 20(%rsp), %xmm1
movl %r14d, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movl $0, %eax
jmp .L48
.L55:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L51
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3673:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z10addPreSumsPfS_"
.LC11:
.string "_Z12parallelScanPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3703:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z10addPreSumsPfS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z12parallelScanPfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3703:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC0:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1050253722
.align 4
.LC3:
.long 1084227584
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<iostream>
#include<stdio.h>
#include<stdlib.h>
#include <cuda.h>
#include <math.h>
#define BLOCK_SIZE 1024
// Kernel for the first iteration of parallel scan
__global__ void parallelScan(float *d_out, float *d_in, int length) {
volatile extern __shared__ double sharedData[];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int threadx = threadIdx.x;
// load the data into the shared memory
sharedData[threadx] = d_in[tid];
__syncthreads();
int pout = 0; int pin = 1;
if (tid < length) {
for (int offset = 1; offset < blockDim.x; offset <<= 1) {
pout = 1 - pout;
pin = 1 - pin;
if (threadx >= offset) {
sharedData[pout * blockDim.x + threadx] = sharedData[pin * blockDim.x + threadx] + sharedData[pin * blockDim.x + threadx - offset];
} else {
sharedData[pout * blockDim.x + threadx] = sharedData[pin * blockDim.x + threadx];
}
__syncthreads();
}
d_out[tid] = sharedData[pout * blockDim.x + threadx];
//save the sum of the block back to d_in
if (threadx == blockDim.x - 1) d_in[tid] = sharedData[pout * blockDim.x + threadx];
}
}
__global__ void addPreSums(float *d_out, float *d_in)
{
volatile extern __shared__ double sharedData[];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int bid = blockIdx.x + 1;
int threadx = threadIdx.x;
int bDim = blockDim.x;
//load seperatedly scanned blocks (with one block offset)
sharedData[threadx] = d_out[tid + bDim];
//each thread adds the previous sums stored in the d_in
for (int i=0; i<bid; i++) {
sharedData[threadx] += d_in[i*bDim + bDim - 1];
}
__syncthreads();
//store the sums back to the correct position
d_out[tid + bDim] = sharedData[threadx];
}
// The function starts the prefix scan on values from d_in
void prefixScan(float * d_in, float *d_out, int num)
{
int blockx = (num + BLOCK_SIZE - 1)/BLOCK_SIZE; //blockx < 2^14, not exceeding the maximum
dim3 dimGrid(blockx, 1, 1);
dim3 dimBlock(BLOCK_SIZE, 1, 1);
parallelScan<<<dimGrid, dimBlock, sizeof(double)*BLOCK_SIZE*2>>>(d_out, d_in, num);
//when there is one more block
if (blockx > 1) {
//launch with one less block since we do not need to add previous sum for the very first block
addPreSums<<<blockx - 1, BLOCK_SIZE, sizeof(double)*(BLOCK_SIZE)>>>(d_out,d_in);
}
}
int checkResults(float*res, float* cudaRes,int length)
{
int nDiffs=0;
const float smallVal = 0.3f; // Keeping this extra high as we have repetitive addition and sequence matters
for(int i=0; i<length; i++)
if(fabs(cudaRes[i]-res[i])>smallVal){
nDiffs++;
}
return nDiffs;
}
void initializeArray(FILE* fp,float* arr, int nElements)
{
for( int i=0; i<nElements; i++){
int r=fscanf(fp,"%f",&arr[i]);
if(r == EOF){
rewind(fp);
}
arr[i]-=5; // This is to make the data zero mean. Otherwise we reach large numbers and lose precision
}
}
void inclusiveScan_SEQ(float *in, float *out,int length) {
float sum=0.f;
for (int i =0; i < length; i++) {
sum+=in[i];
out[i]=sum;
}
}
int main(int argc, char* argv[]) {
if(argc!=2){
printf("Usage %s N\n",argv[0]);
return 1;
}
int N=atoi(argv[1]);
FILE *fp = fopen("problem1.inp","r");
int size = N * sizeof(float);
//allocate resources
float *in = (float *)malloc(size);
float *out = (float *)malloc(size);
float *cuda_out= (float *)malloc(size);
float time = 0.f;
initializeArray(fp,in, N);
//start inclusive timing
cudaEvent_t startIn,stopIn;
cudaEventCreate(&startIn);
cudaEventCreate(&stopIn);
cudaEventRecord(startIn, 0);
float *d_in;
float *d_out;
cudaMalloc(&d_in, size);
cudaMalloc(&d_out, size);
cudaMemcpy(d_in, in, size, cudaMemcpyHostToDevice);
prefixScan(d_in, d_out, N);
cudaMemcpy(cuda_out, d_out, size, cudaMemcpyDeviceToHost);
//stop inclusive timing
cudaEventRecord(stopIn, 0);
cudaEventSynchronize(stopIn);
cudaEventElapsedTime(&time, startIn, stopIn);
cudaEventDestroy(startIn);
cudaEventDestroy(stopIn);
inclusiveScan_SEQ(in, out,N);
int nDiffs = checkResults(out, cuda_out,N);
if(nDiffs)printf("Test Failed\n"); // This should never print
printf("%d\n%f\n%f\n",N,cuda_out[N-1],time);
//printf("%f\n", time);
//free resources
cudaFree(d_in);cudaFree(d_out);free(in); free(out); free(cuda_out);
return 0;
} | #include<iostream>
#include<stdio.h>
#include<stdlib.h>
#include <hip/hip_runtime.h>
#include <math.h>
#define BLOCK_SIZE 1024
// Kernel for the first iteration of parallel scan
__global__ void parallelScan(float *d_out, float *d_in, int length) {
volatile extern __shared__ double sharedData[];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int threadx = threadIdx.x;
// load the data into the shared memory
sharedData[threadx] = d_in[tid];
__syncthreads();
int pout = 0; int pin = 1;
if (tid < length) {
for (int offset = 1; offset < blockDim.x; offset <<= 1) {
pout = 1 - pout;
pin = 1 - pin;
if (threadx >= offset) {
sharedData[pout * blockDim.x + threadx] = sharedData[pin * blockDim.x + threadx] + sharedData[pin * blockDim.x + threadx - offset];
} else {
sharedData[pout * blockDim.x + threadx] = sharedData[pin * blockDim.x + threadx];
}
__syncthreads();
}
d_out[tid] = sharedData[pout * blockDim.x + threadx];
//save the sum of the block back to d_in
if (threadx == blockDim.x - 1) d_in[tid] = sharedData[pout * blockDim.x + threadx];
}
}
__global__ void addPreSums(float *d_out, float *d_in)
{
volatile extern __shared__ double sharedData[];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int bid = blockIdx.x + 1;
int threadx = threadIdx.x;
int bDim = blockDim.x;
//load seperatedly scanned blocks (with one block offset)
sharedData[threadx] = d_out[tid + bDim];
//each thread adds the previous sums stored in the d_in
for (int i=0; i<bid; i++) {
sharedData[threadx] += d_in[i*bDim + bDim - 1];
}
__syncthreads();
//store the sums back to the correct position
d_out[tid + bDim] = sharedData[threadx];
}
// The function starts the prefix scan on values from d_in
void prefixScan(float * d_in, float *d_out, int num)
{
int blockx = (num + BLOCK_SIZE - 1)/BLOCK_SIZE; //blockx < 2^14, not exceeding the maximum
dim3 dimGrid(blockx, 1, 1);
dim3 dimBlock(BLOCK_SIZE, 1, 1);
parallelScan<<<dimGrid, dimBlock, sizeof(double)*BLOCK_SIZE*2>>>(d_out, d_in, num);
//when there is one more block
if (blockx > 1) {
//launch with one less block since we do not need to add previous sum for the very first block
addPreSums<<<blockx - 1, BLOCK_SIZE, sizeof(double)*(BLOCK_SIZE)>>>(d_out,d_in);
}
}
int checkResults(float*res, float* cudaRes,int length)
{
int nDiffs=0;
const float smallVal = 0.3f; // Keeping this extra high as we have repetitive addition and sequence matters
for(int i=0; i<length; i++)
if(fabs(cudaRes[i]-res[i])>smallVal){
nDiffs++;
}
return nDiffs;
}
void initializeArray(FILE* fp,float* arr, int nElements)
{
for( int i=0; i<nElements; i++){
int r=fscanf(fp,"%f",&arr[i]);
if(r == EOF){
rewind(fp);
}
arr[i]-=5; // This is to make the data zero mean. Otherwise we reach large numbers and lose precision
}
}
void inclusiveScan_SEQ(float *in, float *out,int length) {
float sum=0.f;
for (int i =0; i < length; i++) {
sum+=in[i];
out[i]=sum;
}
}
int main(int argc, char* argv[]) {
if(argc!=2){
printf("Usage %s N\n",argv[0]);
return 1;
}
int N=atoi(argv[1]);
FILE *fp = fopen("problem1.inp","r");
int size = N * sizeof(float);
//allocate resources
float *in = (float *)malloc(size);
float *out = (float *)malloc(size);
float *cuda_out= (float *)malloc(size);
float time = 0.f;
initializeArray(fp,in, N);
//start inclusive timing
hipEvent_t startIn,stopIn;
hipEventCreate(&startIn);
hipEventCreate(&stopIn);
hipEventRecord(startIn, 0);
float *d_in;
float *d_out;
hipMalloc(&d_in, size);
hipMalloc(&d_out, size);
hipMemcpy(d_in, in, size, hipMemcpyHostToDevice);
prefixScan(d_in, d_out, N);
hipMemcpy(cuda_out, d_out, size, hipMemcpyDeviceToHost);
//stop inclusive timing
hipEventRecord(stopIn, 0);
hipEventSynchronize(stopIn);
hipEventElapsedTime(&time, startIn, stopIn);
hipEventDestroy(startIn);
hipEventDestroy(stopIn);
inclusiveScan_SEQ(in, out,N);
int nDiffs = checkResults(out, cuda_out,N);
if(nDiffs)printf("Test Failed\n"); // This should never print
printf("%d\n%f\n%f\n",N,cuda_out[N-1],time);
//printf("%f\n", time);
//free resources
hipFree(d_in);hipFree(d_out);free(in); free(out); free(cuda_out);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<iostream>
#include<stdio.h>
#include<stdlib.h>
#include <hip/hip_runtime.h>
#include <math.h>
#define BLOCK_SIZE 1024
// Kernel for the first iteration of parallel scan
__global__ void parallelScan(float *d_out, float *d_in, int length) {
volatile extern __shared__ double sharedData[];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int threadx = threadIdx.x;
// load the data into the shared memory
sharedData[threadx] = d_in[tid];
__syncthreads();
int pout = 0; int pin = 1;
if (tid < length) {
for (int offset = 1; offset < blockDim.x; offset <<= 1) {
pout = 1 - pout;
pin = 1 - pin;
if (threadx >= offset) {
sharedData[pout * blockDim.x + threadx] = sharedData[pin * blockDim.x + threadx] + sharedData[pin * blockDim.x + threadx - offset];
} else {
sharedData[pout * blockDim.x + threadx] = sharedData[pin * blockDim.x + threadx];
}
__syncthreads();
}
d_out[tid] = sharedData[pout * blockDim.x + threadx];
//save the sum of the block back to d_in
if (threadx == blockDim.x - 1) d_in[tid] = sharedData[pout * blockDim.x + threadx];
}
}
__global__ void addPreSums(float *d_out, float *d_in)
{
volatile extern __shared__ double sharedData[];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int bid = blockIdx.x + 1;
int threadx = threadIdx.x;
int bDim = blockDim.x;
//load seperatedly scanned blocks (with one block offset)
sharedData[threadx] = d_out[tid + bDim];
//each thread adds the previous sums stored in the d_in
for (int i=0; i<bid; i++) {
sharedData[threadx] += d_in[i*bDim + bDim - 1];
}
__syncthreads();
//store the sums back to the correct position
d_out[tid + bDim] = sharedData[threadx];
}
// The function starts the prefix scan on values from d_in
void prefixScan(float * d_in, float *d_out, int num)
{
int blockx = (num + BLOCK_SIZE - 1)/BLOCK_SIZE; //blockx < 2^14, not exceeding the maximum
dim3 dimGrid(blockx, 1, 1);
dim3 dimBlock(BLOCK_SIZE, 1, 1);
parallelScan<<<dimGrid, dimBlock, sizeof(double)*BLOCK_SIZE*2>>>(d_out, d_in, num);
//when there is one more block
if (blockx > 1) {
//launch with one less block since we do not need to add previous sum for the very first block
addPreSums<<<blockx - 1, BLOCK_SIZE, sizeof(double)*(BLOCK_SIZE)>>>(d_out,d_in);
}
}
int checkResults(float*res, float* cudaRes,int length)
{
int nDiffs=0;
const float smallVal = 0.3f; // Keeping this extra high as we have repetitive addition and sequence matters
for(int i=0; i<length; i++)
if(fabs(cudaRes[i]-res[i])>smallVal){
nDiffs++;
}
return nDiffs;
}
void initializeArray(FILE* fp,float* arr, int nElements)
{
for( int i=0; i<nElements; i++){
int r=fscanf(fp,"%f",&arr[i]);
if(r == EOF){
rewind(fp);
}
arr[i]-=5; // This is to make the data zero mean. Otherwise we reach large numbers and lose precision
}
}
void inclusiveScan_SEQ(float *in, float *out,int length) {
float sum=0.f;
for (int i =0; i < length; i++) {
sum+=in[i];
out[i]=sum;
}
}
int main(int argc, char* argv[]) {
if(argc!=2){
printf("Usage %s N\n",argv[0]);
return 1;
}
int N=atoi(argv[1]);
FILE *fp = fopen("problem1.inp","r");
int size = N * sizeof(float);
//allocate resources
float *in = (float *)malloc(size);
float *out = (float *)malloc(size);
float *cuda_out= (float *)malloc(size);
float time = 0.f;
initializeArray(fp,in, N);
//start inclusive timing
hipEvent_t startIn,stopIn;
hipEventCreate(&startIn);
hipEventCreate(&stopIn);
hipEventRecord(startIn, 0);
float *d_in;
float *d_out;
hipMalloc(&d_in, size);
hipMalloc(&d_out, size);
hipMemcpy(d_in, in, size, hipMemcpyHostToDevice);
prefixScan(d_in, d_out, N);
hipMemcpy(cuda_out, d_out, size, hipMemcpyDeviceToHost);
//stop inclusive timing
hipEventRecord(stopIn, 0);
hipEventSynchronize(stopIn);
hipEventElapsedTime(&time, startIn, stopIn);
hipEventDestroy(startIn);
hipEventDestroy(stopIn);
inclusiveScan_SEQ(in, out,N);
int nDiffs = checkResults(out, cuda_out,N);
if(nDiffs)printf("Test Failed\n"); // This should never print
printf("%d\n%f\n%f\n",N,cuda_out[N-1],time);
//printf("%f\n", time);
//free resources
hipFree(d_in);hipFree(d_out);free(in); free(out); free(cuda_out);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12parallelScanPfS_i
.globl _Z12parallelScanPfS_i
.p2align 8
.type _Z12parallelScanPfS_i,@function
_Z12parallelScanPfS_i:
s_load_b32 s2, s[0:1], 0x24
v_lshl_add_u32 v7, v0, 3, 0
s_mov_b32 s5, 0
s_load_b32 s6, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_load_b64 s[2:3], s[0:1], 0x8
v_mad_u64_u32 v[3:4], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[1:2], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v7
s_mov_b64 s[2:3], src_shared_base
s_mov_b32 s2, exec_lo
global_load_b32 v5, v[1:2], off
v_cndmask_b32_e32 v7, 0, v7, vcc_lo
v_cndmask_b32_e64 v8, 0, s3, vcc_lo
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[5:6], v5
flat_store_b64 v[7:8], v[5:6] dlc
s_waitcnt_vscnt null, 0x0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_i32_e64 s6, v3
s_cbranch_execz .LBB0_8
s_cmp_lt_u32 s4, 2
s_cbranch_scc1 .LBB0_6
s_mov_b64 s[2:3], src_shared_base
s_mov_b32 s6, 1
s_mov_b32 s2, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s7
s_sub_i32 s5, 1, s5
s_lshl_b32 s6, s6, 1
v_mad_u64_u32 v[7:8], null, s5, s4, v[0:1]
s_cmp_ge_u32 s6, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v7, v7, 3, 0
v_cmp_ne_u32_e32 vcc_lo, -1, v7
v_cndmask_b32_e32 v7, 0, v7, vcc_lo
v_cndmask_b32_e64 v8, 0, s3, vcc_lo
s_waitcnt lgkmcnt(0)
flat_store_b64 v[7:8], v[5:6] dlc
s_waitcnt_vscnt null, 0x0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_6
.LBB0_4:
s_sub_i32 s2, 1, s2
s_mov_b32 s7, exec_lo
v_mad_u64_u32 v[7:8], null, s2, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v5, v7, 3, 0
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cndmask_b32_e64 v6, 0, s3, vcc_lo
flat_load_b64 v[5:6], v[5:6] glc dlc
s_waitcnt vmcnt(0)
v_cmpx_le_u32_e64 s6, v0
s_cbranch_execz .LBB0_3
v_subrev_nc_u32_e32 v7, s6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v7, v7, 3, 0
v_cmp_ne_u32_e32 vcc_lo, -1, v7
v_cndmask_b32_e32 v7, 0, v7, vcc_lo
v_cndmask_b32_e64 v8, 0, s3, vcc_lo
flat_load_b64 v[7:8], v[7:8] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f64 v[5:6], v[5:6], v[7:8]
s_branch .LBB0_3
.LBB0_6:
s_set_inst_prefetch_distance 0x2
v_mad_u64_u32 v[5:6], null, s5, s4, v[0:1]
s_mov_b64 s[2:3], src_shared_base
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_add_i32 s4, s4, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v5, v5, 3, 0
v_cmp_ne_u32_e32 vcc_lo, -1, v5
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cndmask_b32_e64 v6, 0, s3, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
flat_load_b64 v[7:8], v[5:6] glc dlc
s_waitcnt vmcnt(0)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, s4, v0
s_waitcnt lgkmcnt(0)
v_cvt_f32_f64_e32 v7, v[7:8]
global_store_b32 v[3:4], v7, off
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_8
flat_load_b64 v[3:4], v[5:6] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cvt_f32_f64_e32 v0, v[3:4]
global_store_b32 v[1:2], v0, off
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12parallelScanPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12parallelScanPfS_i, .Lfunc_end0-_Z12parallelScanPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10addPreSumsPfS_
.globl _Z10addPreSumsPfS_
.p2align 8
.type _Z10addPreSumsPfS_,@function
_Z10addPreSumsPfS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_cmp_gt_u32 s15, 0x7ffffffe
s_mul_i32 s3, s15, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add3_u32 v1, s3, s2, v0
v_lshl_add_u32 v0, v0, 3, 0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, -1, v0
s_mov_b64 s[4:5], src_shared_base
global_load_b32 v3, v[1:2], off
v_cndmask_b32_e64 v4, 0, s5, vcc_lo
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[5:6], v3
v_cndmask_b32_e32 v3, 0, v0, vcc_lo
flat_store_b64 v[3:4], v[5:6] dlc
s_waitcnt_vscnt null, 0x0
s_cbranch_scc1 .LBB1_3
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_add_u32 s3, s0, -4
s_addc_u32 s4, s1, -1
s_add_i32 s5, s15, 1
s_mov_b32 s0, s2
.p2align 6
.LBB1_2:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s1, s0, 31
s_lshl_b64 s[6:7], s[0:1], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s6, s3, s6
s_addc_u32 s7, s4, s7
s_add_i32 s5, s5, -1
s_load_b32 s1, s[6:7], 0x0
flat_load_b64 v[5:6], v[3:4] glc dlc
s_waitcnt vmcnt(0)
s_add_i32 s0, s0, s2
s_cmp_eq_u32 s5, 0
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[7:8], s1
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[5:6], v[5:6], v[7:8]
flat_store_b64 v[3:4], v[5:6] dlc
s_waitcnt_vscnt null, 0x0
s_cbranch_scc0 .LBB1_2
.LBB1_3:
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
flat_load_b64 v[3:4], v[3:4] glc dlc
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cvt_f32_f64_e32 v0, v[3:4]
global_store_b32 v[1:2], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10addPreSumsPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10addPreSumsPfS_, .Lfunc_end1-_Z10addPreSumsPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym sharedData
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12parallelScanPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12parallelScanPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10addPreSumsPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10addPreSumsPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<iostream>
#include<stdio.h>
#include<stdlib.h>
#include <hip/hip_runtime.h>
#include <math.h>
#define BLOCK_SIZE 1024
// Kernel for the first iteration of parallel scan
__global__ void parallelScan(float *d_out, float *d_in, int length) {
volatile extern __shared__ double sharedData[];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int threadx = threadIdx.x;
// load the data into the shared memory
sharedData[threadx] = d_in[tid];
__syncthreads();
int pout = 0; int pin = 1;
if (tid < length) {
for (int offset = 1; offset < blockDim.x; offset <<= 1) {
pout = 1 - pout;
pin = 1 - pin;
if (threadx >= offset) {
sharedData[pout * blockDim.x + threadx] = sharedData[pin * blockDim.x + threadx] + sharedData[pin * blockDim.x + threadx - offset];
} else {
sharedData[pout * blockDim.x + threadx] = sharedData[pin * blockDim.x + threadx];
}
__syncthreads();
}
d_out[tid] = sharedData[pout * blockDim.x + threadx];
//save the sum of the block back to d_in
if (threadx == blockDim.x - 1) d_in[tid] = sharedData[pout * blockDim.x + threadx];
}
}
__global__ void addPreSums(float *d_out, float *d_in)
{
volatile extern __shared__ double sharedData[];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int bid = blockIdx.x + 1;
int threadx = threadIdx.x;
int bDim = blockDim.x;
//load seperatedly scanned blocks (with one block offset)
sharedData[threadx] = d_out[tid + bDim];
//each thread adds the previous sums stored in the d_in
for (int i=0; i<bid; i++) {
sharedData[threadx] += d_in[i*bDim + bDim - 1];
}
__syncthreads();
//store the sums back to the correct position
d_out[tid + bDim] = sharedData[threadx];
}
// The function starts the prefix scan on values from d_in
void prefixScan(float * d_in, float *d_out, int num)
{
int blockx = (num + BLOCK_SIZE - 1)/BLOCK_SIZE; //blockx < 2^14, not exceeding the maximum
dim3 dimGrid(blockx, 1, 1);
dim3 dimBlock(BLOCK_SIZE, 1, 1);
parallelScan<<<dimGrid, dimBlock, sizeof(double)*BLOCK_SIZE*2>>>(d_out, d_in, num);
//when there is one more block
if (blockx > 1) {
//launch with one less block since we do not need to add previous sum for the very first block
addPreSums<<<blockx - 1, BLOCK_SIZE, sizeof(double)*(BLOCK_SIZE)>>>(d_out,d_in);
}
}
int checkResults(float*res, float* cudaRes,int length)
{
int nDiffs=0;
const float smallVal = 0.3f; // Keeping this extra high as we have repetitive addition and sequence matters
for(int i=0; i<length; i++)
if(fabs(cudaRes[i]-res[i])>smallVal){
nDiffs++;
}
return nDiffs;
}
void initializeArray(FILE* fp,float* arr, int nElements)
{
for( int i=0; i<nElements; i++){
int r=fscanf(fp,"%f",&arr[i]);
if(r == EOF){
rewind(fp);
}
arr[i]-=5; // This is to make the data zero mean. Otherwise we reach large numbers and lose precision
}
}
void inclusiveScan_SEQ(float *in, float *out,int length) {
float sum=0.f;
for (int i =0; i < length; i++) {
sum+=in[i];
out[i]=sum;
}
}
int main(int argc, char* argv[]) {
if(argc!=2){
printf("Usage %s N\n",argv[0]);
return 1;
}
int N=atoi(argv[1]);
FILE *fp = fopen("problem1.inp","r");
int size = N * sizeof(float);
//allocate resources
float *in = (float *)malloc(size);
float *out = (float *)malloc(size);
float *cuda_out= (float *)malloc(size);
float time = 0.f;
initializeArray(fp,in, N);
//start inclusive timing
hipEvent_t startIn,stopIn;
hipEventCreate(&startIn);
hipEventCreate(&stopIn);
hipEventRecord(startIn, 0);
float *d_in;
float *d_out;
hipMalloc(&d_in, size);
hipMalloc(&d_out, size);
hipMemcpy(d_in, in, size, hipMemcpyHostToDevice);
prefixScan(d_in, d_out, N);
hipMemcpy(cuda_out, d_out, size, hipMemcpyDeviceToHost);
//stop inclusive timing
hipEventRecord(stopIn, 0);
hipEventSynchronize(stopIn);
hipEventElapsedTime(&time, startIn, stopIn);
hipEventDestroy(startIn);
hipEventDestroy(stopIn);
inclusiveScan_SEQ(in, out,N);
int nDiffs = checkResults(out, cuda_out,N);
if(nDiffs)printf("Test Failed\n"); // This should never print
printf("%d\n%f\n%f\n",N,cuda_out[N-1],time);
//printf("%f\n", time);
//free resources
hipFree(d_in);hipFree(d_out);free(in); free(out); free(cuda_out);
return 0;
} | .text
.file "problem1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__parallelScanPfS_i # -- Begin function _Z27__device_stub__parallelScanPfS_i
.p2align 4, 0x90
.type _Z27__device_stub__parallelScanPfS_i,@function
_Z27__device_stub__parallelScanPfS_i: # @_Z27__device_stub__parallelScanPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12parallelScanPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__parallelScanPfS_i, .Lfunc_end0-_Z27__device_stub__parallelScanPfS_i
.cfi_endproc
# -- End function
.globl _Z25__device_stub__addPreSumsPfS_ # -- Begin function _Z25__device_stub__addPreSumsPfS_
.p2align 4, 0x90
.type _Z25__device_stub__addPreSumsPfS_,@function
_Z25__device_stub__addPreSumsPfS_: # @_Z25__device_stub__addPreSumsPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10addPreSumsPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z25__device_stub__addPreSumsPfS_, .Lfunc_end1-_Z25__device_stub__addPreSumsPfS_
.cfi_endproc
# -- End function
.globl _Z10prefixScanPfS_i # -- Begin function _Z10prefixScanPfS_i
.p2align 4, 0x90
.type _Z10prefixScanPfS_i,@function
_Z10prefixScanPfS_i: # @_Z10prefixScanPfS_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edx, %r13d
movq %rsi, %r14
movq %rdi, %rbx
leal 1023(%r13), %eax
leal 2046(%r13), %r15d
testl %eax, %eax
cmovnsl %eax, %r15d
movabsq $4294967296, %r12 # imm = 0x100000000
sarl $10, %r15d
leaq (%r15,%r12), %rdi
leaq 1024(%r12), %rdx
movl $16384, %r8d # imm = 0x4000
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB2_1
# %bb.2:
cmpl $1025, %r13d # imm = 0x401
jge .LBB2_3
jmp .LBB2_5
.LBB2_1:
movq %r14, 64(%rsp)
movq %rbx, 56(%rsp)
movl %r13d, 76(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 76(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12parallelScanPfS_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
cmpl $1025, %r13d # imm = 0x401
jl .LBB2_5
.LBB2_3:
decl %r15d
orq %r12, %r15
addq $1024, %r12 # imm = 0x400
movl $8192, %r8d # imm = 0x2000
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
movq %r14, 64(%rsp)
movq %rbx, 56(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10addPreSumsPfS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_5:
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10prefixScanPfS_i, .Lfunc_end2-_Z10prefixScanPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z12checkResultsPfS_i
.LCPI3_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI3_1:
.long 0x3e99999a # float 0.300000012
.text
.globl _Z12checkResultsPfS_i
.p2align 4, 0x90
.type _Z12checkResultsPfS_i,@function
_Z12checkResultsPfS_i: # @_Z12checkResultsPfS_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB3_1
# %bb.3: # %.lr.ph.preheader
movl %edx, %ecx
xorl %edx, %edx
movaps .LCPI3_0(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movss .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rsi,%rdx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss (%rdi,%rdx,4), %xmm2
andps %xmm0, %xmm2
xorl %r8d, %r8d
ucomiss %xmm1, %xmm2
seta %r8b
addl %r8d, %eax
incq %rdx
cmpq %rdx, %rcx
jne .LBB3_4
# %bb.2: # %._crit_edge
retq
.LBB3_1:
xorl %eax, %eax
retq
.Lfunc_end3:
.size _Z12checkResultsPfS_i, .Lfunc_end3-_Z12checkResultsPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z15initializeArrayP8_IO_FILEPfi
.LCPI4_0:
.long 0xc0a00000 # float -5
.text
.globl _Z15initializeArrayP8_IO_FILEPfi
.p2align 4, 0x90
.type _Z15initializeArrayP8_IO_FILEPfi,@function
_Z15initializeArrayP8_IO_FILEPfi: # @_Z15initializeArrayP8_IO_FILEPfi
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB4_6
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
movl %edx, %r15d
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_4: # in Loop: Header=BB4_2 Depth=1
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss .LCPI4_0(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
decq %r15
je .LBB4_5
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str, %esi
movq %r14, %rdi
movq %rbx, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
jne .LBB4_4
# %bb.3: # in Loop: Header=BB4_2 Depth=1
movq %r14, %rdi
callq rewind
jmp .LBB4_4
.LBB4_5:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB4_6: # %._crit_edge
retq
.Lfunc_end4:
.size _Z15initializeArrayP8_IO_FILEPfi, .Lfunc_end4-_Z15initializeArrayP8_IO_FILEPfi
.cfi_endproc
# -- End function
.globl _Z17inclusiveScan_SEQPfS_i # -- Begin function _Z17inclusiveScan_SEQPfS_i
.p2align 4, 0x90
.type _Z17inclusiveScan_SEQPfS_i,@function
_Z17inclusiveScan_SEQPfS_i: # @_Z17inclusiveScan_SEQPfS_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB5_3
# %bb.1: # %.lr.ph.preheader
movl %edx, %eax
xorps %xmm0, %xmm0
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB5_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addss (%rdi,%rcx,4), %xmm0
movss %xmm0, (%rsi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB5_2
.LBB5_3: # %._crit_edge
retq
.Lfunc_end5:
.size _Z17inclusiveScan_SEQPfS_i, .Lfunc_end5-_Z17inclusiveScan_SEQPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI6_0:
.long 0xc0a00000 # float -5
.LCPI6_2:
.long 0x3e99999a # float 0.300000012
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI6_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB6_1
# %bb.2:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movl $.L.str.2, %edi
movl $.L.str.3, %esi
callq fopen
movq %rax, %r13
leal (,%r14,4), %eax
movslq %eax, %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r15
movq %r12, 48(%rsp) # 8-byte Spill
movq %r12, %rdi
callq malloc
movq %rax, %r12
movl $0, 4(%rsp)
movq %r14, 40(%rsp) # 8-byte Spill
testl %r14d, %r14d
jle .LBB6_7
# %bb.3: # %.lr.ph.preheader.i
movl 40(%rsp), %ebp # 4-byte Reload
movq %rbx, %r14
jmp .LBB6_4
.p2align 4, 0x90
.LBB6_6: # in Loop: Header=BB6_4 Depth=1
movss (%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss .LCPI6_0(%rip), %xmm0
movss %xmm0, (%r14)
addq $4, %r14
decq %rbp
je .LBB6_7
.LBB6_4: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $.L.str, %esi
movq %r13, %rdi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
jne .LBB6_6
# %bb.5: # in Loop: Header=BB6_4 Depth=1
movq %r13, %rdi
callq rewind
jmp .LBB6_6
.LBB6_1:
movq (%rsi), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $1, %r13d
jmp .LBB6_16
.LBB6_7: # %_Z15initializeArrayP8_IO_FILEPfi.exit
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %r13d, %r13d
xorl %esi, %esi
callq hipEventRecord
leaq 24(%rsp), %rdi
movq 48(%rsp), %rbp # 8-byte Reload
movq %rbp, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq 16(%rsp), %rsi
movq 40(%rsp), %r14 # 8-byte Reload
movl %r14d, %edx
callq _Z10prefixScanPfS_i
movq 16(%rsp), %rsi
movq %r12, %rdi
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movq 32(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
testl %r14d, %r14d
jle .LBB6_15
# %bb.8: # %.lr.ph.preheader.i31
movl %r14d, %eax
xorps %xmm0, %xmm0
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB6_9: # %.lr.ph.i33
# =>This Inner Loop Header: Depth=1
addss (%rbx,%rcx,4), %xmm0
movss %xmm0, (%r15,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB6_9
# %bb.10: # %_Z17inclusiveScan_SEQPfS_i.exit
testl %r14d, %r14d
jle .LBB6_15
# %bb.11: # %.lr.ph.preheader.i37
movl %r14d, %eax
xorl %ecx, %ecx
movaps .LCPI6_1(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movss .LCPI6_2(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorl %edx, %edx
.p2align 4, 0x90
.LBB6_12: # %.lr.ph.i39
# =>This Inner Loop Header: Depth=1
movss (%r12,%rcx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss (%r15,%rcx,4), %xmm2
andps %xmm0, %xmm2
xorl %esi, %esi
ucomiss %xmm1, %xmm2
seta %sil
addl %esi, %edx
incq %rcx
cmpq %rcx, %rax
jne .LBB6_12
# %bb.13: # %_Z12checkResultsPfS_i.exit.loopexit
testl %edx, %edx
je .LBB6_15
# %bb.14:
movl $.Lstr, %edi
callq puts@PLT
.LBB6_15: # %.critedge
movslq %r14d, %rax
movss -4(%r12,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss 4(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str.5, %edi
movl %r14d, %esi
movb $2, %al
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
.LBB6_16:
movl %r13d, %eax
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12parallelScanPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10addPreSumsPfS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12parallelScanPfS_i,@object # @_Z12parallelScanPfS_i
.section .rodata,"a",@progbits
.globl _Z12parallelScanPfS_i
.p2align 3, 0x0
_Z12parallelScanPfS_i:
.quad _Z27__device_stub__parallelScanPfS_i
.size _Z12parallelScanPfS_i, 8
.type _Z10addPreSumsPfS_,@object # @_Z10addPreSumsPfS_
.globl _Z10addPreSumsPfS_
.p2align 3, 0x0
_Z10addPreSumsPfS_:
.quad _Z25__device_stub__addPreSumsPfS_
.size _Z10addPreSumsPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Usage %s N\n"
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "problem1.inp"
.size .L.str.2, 13
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "r"
.size .L.str.3, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d\n%f\n%f\n"
.size .L.str.5, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12parallelScanPfS_i"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10addPreSumsPfS_"
.size .L__unnamed_2, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Test Failed"
.size .Lstr, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__parallelScanPfS_i
.addrsig_sym _Z25__device_stub__addPreSumsPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12parallelScanPfS_i
.addrsig_sym _Z10addPreSumsPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017eef5_00000000-6_problem1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3676:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3676:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12checkResultsPfS_i
.type _Z12checkResultsPfS_i, @function
_Z12checkResultsPfS_i:
.LFB3670:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L8
movslq %edx, %rdx
leaq 0(,%rdx,4), %r8
movl $0, %eax
movl $0, %edx
movss .LC0(%rip), %xmm1
.L7:
movss (%rsi,%rax), %xmm0
subss (%rdi,%rax), %xmm0
andps %xmm1, %xmm0
comiss .LC1(%rip), %xmm0
seta %cl
movzbl %cl, %ecx
addl %ecx, %edx
addq $4, %rax
cmpq %rax, %r8
jne .L7
.L3:
movl %edx, %eax
ret
.L8:
movl $0, %edx
jmp .L3
.cfi_endproc
.LFE3670:
.size _Z12checkResultsPfS_i, .-_Z12checkResultsPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%f"
.text
.globl _Z15initializeArrayP8_IO_FILEPfi
.type _Z15initializeArrayP8_IO_FILEPfi, @function
_Z15initializeArrayP8_IO_FILEPfi:
.LFB3671:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L17
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r12
movq %rsi, %rbx
movslq %edx, %rdx
leaq (%rsi,%rdx,4), %r14
leaq .LC2(%rip), %r13
jmp .L14
.L13:
movss 0(%rbp), %xmm0
subss .LC3(%rip), %xmm0
movss %xmm0, 0(%rbp)
addq $4, %rbx
cmpq %r14, %rbx
je .L20
.L14:
movq %rbx, %rbp
movq %rbx, %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $-1, %eax
jne .L13
movq %r12, %rdi
call rewind@PLT
jmp .L13
.L20:
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
ret
.cfi_endproc
.LFE3671:
.size _Z15initializeArrayP8_IO_FILEPfi, .-_Z15initializeArrayP8_IO_FILEPfi
.globl _Z17inclusiveScan_SEQPfS_i
.type _Z17inclusiveScan_SEQPfS_i, @function
_Z17inclusiveScan_SEQPfS_i:
.LFB3672:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L21
movslq %edx, %rdx
salq $2, %rdx
movl $0, %eax
pxor %xmm0, %xmm0
.L23:
addss (%rdi,%rax), %xmm0
movss %xmm0, (%rsi,%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L23
.L21:
ret
.cfi_endproc
.LFE3672:
.size _Z17inclusiveScan_SEQPfS_i, .-_Z17inclusiveScan_SEQPfS_i
.globl _Z35__device_stub__Z12parallelScanPfS_iPfS_i
.type _Z35__device_stub__Z12parallelScanPfS_iPfS_i, @function
_Z35__device_stub__Z12parallelScanPfS_iPfS_i:
.LFB3698:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12parallelScanPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z35__device_stub__Z12parallelScanPfS_iPfS_i, .-_Z35__device_stub__Z12parallelScanPfS_iPfS_i
.globl _Z12parallelScanPfS_i
.type _Z12parallelScanPfS_i, @function
_Z12parallelScanPfS_i:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12parallelScanPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z12parallelScanPfS_i, .-_Z12parallelScanPfS_i
.globl _Z32__device_stub__Z10addPreSumsPfS_PfS_
.type _Z32__device_stub__Z10addPreSumsPfS_PfS_, @function
_Z32__device_stub__Z10addPreSumsPfS_PfS_:
.LFB3700:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10addPreSumsPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3700:
.size _Z32__device_stub__Z10addPreSumsPfS_PfS_, .-_Z32__device_stub__Z10addPreSumsPfS_PfS_
.globl _Z10addPreSumsPfS_
.type _Z10addPreSumsPfS_, @function
_Z10addPreSumsPfS_:
.LFB3701:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10addPreSumsPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _Z10addPreSumsPfS_, .-_Z10addPreSumsPfS_
.globl _Z10prefixScanPfS_i
.type _Z10prefixScanPfS_i, @function
_Z10prefixScanPfS_i:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r13
movq %rsi, %r12
movl %edx, %ebx
leal 2046(%rdx), %ebp
movl %edx, %eax
addl $1023, %eax
cmovns %eax, %ebp
sarl $10, %ebp
movl %ebp, (%rsp)
movl $1, 4(%rsp)
movl $1024, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $16384, %r8d
movq 12(%rsp), %rdx
movl $1, %ecx
movq (%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L46
.L42:
cmpl $1024, %ebx
jg .L47
.L41:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
movl %ebx, %edx
movq %r13, %rsi
movq %r12, %rdi
call _Z35__device_stub__Z12parallelScanPfS_iPfS_i
jmp .L42
.L47:
movl $1024, 36(%rsp)
movl $1, 40(%rsp)
subl $1, %ebp
movl %ebp, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $8192, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L41
movq %r13, %rsi
movq %r12, %rdi
call _Z32__device_stub__Z10addPreSumsPfS_PfS_
jmp .L41
.cfi_endproc
.LFE3669:
.size _Z10prefixScanPfS_i, .-_Z10prefixScanPfS_i
.section .rodata.str1.1
.LC5:
.string "Usage %s N\n"
.LC6:
.string "r"
.LC7:
.string "problem1.inp"
.LC8:
.string "Test Failed\n"
.LC9:
.string "%d\n%f\n%f\n"
.text
.globl main
.type main, @function
main:
.LFB3673:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
cmpl $2, %edi
je .L49
movq (%rsi), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %eax
.L48:
movq 56(%rsp), %rdx
subq %fs:40, %rdx
jne .L54
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %r14d
leaq .LC6(%rip), %rsi
leaq .LC7(%rip), %rdi
call fopen@PLT
movq %rax, 8(%rsp)
movslq %ebx, %r15
leal 0(,%rbx,4), %ebx
movslq %ebx, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movl $0x00000000, 20(%rsp)
movl %r14d, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call _Z15initializeArrayP8_IO_FILEPfi
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %r14d, %edx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z10prefixScanPfS_i
movl $2, %ecx
movq %rbx, %rdx
movq 48(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 20(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movl %r14d, %edx
movq %r13, %rsi
movq %r12, %rdi
call _Z17inclusiveScan_SEQPfS_i
movl %r14d, %edx
movq %rbp, %rsi
movq %r13, %rdi
call _Z12checkResultsPfS_i
testl %eax, %eax
jne .L55
.L51:
pxor %xmm0, %xmm0
cvtss2sd -4(%rbp,%r15,4), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 20(%rsp), %xmm1
movl %r14d, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movl $0, %eax
jmp .L48
.L55:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L51
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3673:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z10addPreSumsPfS_"
.LC11:
.string "_Z12parallelScanPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3703:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z10addPreSumsPfS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z12parallelScanPfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3703:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC0:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1050253722
.align 4
.LC3:
.long 1084227584
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "problem1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z27__device_stub__parallelScanPfS_i # -- Begin function _Z27__device_stub__parallelScanPfS_i
.p2align 4, 0x90
.type _Z27__device_stub__parallelScanPfS_i,@function
_Z27__device_stub__parallelScanPfS_i: # @_Z27__device_stub__parallelScanPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12parallelScanPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__parallelScanPfS_i, .Lfunc_end0-_Z27__device_stub__parallelScanPfS_i
.cfi_endproc
# -- End function
.globl _Z25__device_stub__addPreSumsPfS_ # -- Begin function _Z25__device_stub__addPreSumsPfS_
.p2align 4, 0x90
.type _Z25__device_stub__addPreSumsPfS_,@function
_Z25__device_stub__addPreSumsPfS_: # @_Z25__device_stub__addPreSumsPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10addPreSumsPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z25__device_stub__addPreSumsPfS_, .Lfunc_end1-_Z25__device_stub__addPreSumsPfS_
.cfi_endproc
# -- End function
.globl _Z10prefixScanPfS_i # -- Begin function _Z10prefixScanPfS_i
.p2align 4, 0x90
.type _Z10prefixScanPfS_i,@function
_Z10prefixScanPfS_i: # @_Z10prefixScanPfS_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edx, %r13d
movq %rsi, %r14
movq %rdi, %rbx
leal 1023(%r13), %eax
leal 2046(%r13), %r15d
testl %eax, %eax
cmovnsl %eax, %r15d
movabsq $4294967296, %r12 # imm = 0x100000000
sarl $10, %r15d
leaq (%r15,%r12), %rdi
leaq 1024(%r12), %rdx
movl $16384, %r8d # imm = 0x4000
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
je .LBB2_1
# %bb.2:
cmpl $1025, %r13d # imm = 0x401
jge .LBB2_3
jmp .LBB2_5
.LBB2_1:
movq %r14, 64(%rsp)
movq %rbx, 56(%rsp)
movl %r13d, 76(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 76(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12parallelScanPfS_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
cmpl $1025, %r13d # imm = 0x401
jl .LBB2_5
.LBB2_3:
decl %r15d
orq %r12, %r15
addq $1024, %r12 # imm = 0x400
movl $8192, %r8d # imm = 0x2000
movq %r15, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
movq %r14, 64(%rsp)
movq %rbx, 56(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10addPreSumsPfS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_5:
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10prefixScanPfS_i, .Lfunc_end2-_Z10prefixScanPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z12checkResultsPfS_i
.LCPI3_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI3_1:
.long 0x3e99999a # float 0.300000012
.text
.globl _Z12checkResultsPfS_i
.p2align 4, 0x90
.type _Z12checkResultsPfS_i,@function
_Z12checkResultsPfS_i: # @_Z12checkResultsPfS_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB3_1
# %bb.3: # %.lr.ph.preheader
movl %edx, %ecx
xorl %edx, %edx
movaps .LCPI3_0(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movss .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rsi,%rdx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss (%rdi,%rdx,4), %xmm2
andps %xmm0, %xmm2
xorl %r8d, %r8d
ucomiss %xmm1, %xmm2
seta %r8b
addl %r8d, %eax
incq %rdx
cmpq %rdx, %rcx
jne .LBB3_4
# %bb.2: # %._crit_edge
retq
.LBB3_1:
xorl %eax, %eax
retq
.Lfunc_end3:
.size _Z12checkResultsPfS_i, .Lfunc_end3-_Z12checkResultsPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z15initializeArrayP8_IO_FILEPfi
.LCPI4_0:
.long 0xc0a00000 # float -5
.text
.globl _Z15initializeArrayP8_IO_FILEPfi
.p2align 4, 0x90
.type _Z15initializeArrayP8_IO_FILEPfi,@function
_Z15initializeArrayP8_IO_FILEPfi: # @_Z15initializeArrayP8_IO_FILEPfi
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB4_6
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
movl %edx, %r15d
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_4: # in Loop: Header=BB4_2 Depth=1
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss .LCPI4_0(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
decq %r15
je .LBB4_5
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str, %esi
movq %r14, %rdi
movq %rbx, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
jne .LBB4_4
# %bb.3: # in Loop: Header=BB4_2 Depth=1
movq %r14, %rdi
callq rewind
jmp .LBB4_4
.LBB4_5:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB4_6: # %._crit_edge
retq
.Lfunc_end4:
.size _Z15initializeArrayP8_IO_FILEPfi, .Lfunc_end4-_Z15initializeArrayP8_IO_FILEPfi
.cfi_endproc
# -- End function
.globl _Z17inclusiveScan_SEQPfS_i # -- Begin function _Z17inclusiveScan_SEQPfS_i
.p2align 4, 0x90
.type _Z17inclusiveScan_SEQPfS_i,@function
_Z17inclusiveScan_SEQPfS_i: # @_Z17inclusiveScan_SEQPfS_i
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB5_3
# %bb.1: # %.lr.ph.preheader
movl %edx, %eax
xorps %xmm0, %xmm0
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB5_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addss (%rdi,%rcx,4), %xmm0
movss %xmm0, (%rsi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB5_2
.LBB5_3: # %._crit_edge
retq
.Lfunc_end5:
.size _Z17inclusiveScan_SEQPfS_i, .Lfunc_end5-_Z17inclusiveScan_SEQPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI6_0:
.long 0xc0a00000 # float -5
.LCPI6_2:
.long 0x3e99999a # float 0.300000012
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI6_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB6_1
# %bb.2:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movl $.L.str.2, %edi
movl $.L.str.3, %esi
callq fopen
movq %rax, %r13
leal (,%r14,4), %eax
movslq %eax, %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r15
movq %r12, 48(%rsp) # 8-byte Spill
movq %r12, %rdi
callq malloc
movq %rax, %r12
movl $0, 4(%rsp)
movq %r14, 40(%rsp) # 8-byte Spill
testl %r14d, %r14d
jle .LBB6_7
# %bb.3: # %.lr.ph.preheader.i
movl 40(%rsp), %ebp # 4-byte Reload
movq %rbx, %r14
jmp .LBB6_4
.p2align 4, 0x90
.LBB6_6: # in Loop: Header=BB6_4 Depth=1
movss (%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss .LCPI6_0(%rip), %xmm0
movss %xmm0, (%r14)
addq $4, %r14
decq %rbp
je .LBB6_7
.LBB6_4: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl $.L.str, %esi
movq %r13, %rdi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
jne .LBB6_6
# %bb.5: # in Loop: Header=BB6_4 Depth=1
movq %r13, %rdi
callq rewind
jmp .LBB6_6
.LBB6_1:
movq (%rsi), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $1, %r13d
jmp .LBB6_16
.LBB6_7: # %_Z15initializeArrayP8_IO_FILEPfi.exit
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %r13d, %r13d
xorl %esi, %esi
callq hipEventRecord
leaq 24(%rsp), %rdi
movq 48(%rsp), %rbp # 8-byte Reload
movq %rbp, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movq 16(%rsp), %rsi
movq 40(%rsp), %r14 # 8-byte Reload
movl %r14d, %edx
callq _Z10prefixScanPfS_i
movq 16(%rsp), %rsi
movq %r12, %rdi
movq %rbp, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 32(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
movq 32(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
testl %r14d, %r14d
jle .LBB6_15
# %bb.8: # %.lr.ph.preheader.i31
movl %r14d, %eax
xorps %xmm0, %xmm0
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB6_9: # %.lr.ph.i33
# =>This Inner Loop Header: Depth=1
addss (%rbx,%rcx,4), %xmm0
movss %xmm0, (%r15,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB6_9
# %bb.10: # %_Z17inclusiveScan_SEQPfS_i.exit
testl %r14d, %r14d
jle .LBB6_15
# %bb.11: # %.lr.ph.preheader.i37
movl %r14d, %eax
xorl %ecx, %ecx
movaps .LCPI6_1(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movss .LCPI6_2(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorl %edx, %edx
.p2align 4, 0x90
.LBB6_12: # %.lr.ph.i39
# =>This Inner Loop Header: Depth=1
movss (%r12,%rcx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss (%r15,%rcx,4), %xmm2
andps %xmm0, %xmm2
xorl %esi, %esi
ucomiss %xmm1, %xmm2
seta %sil
addl %esi, %edx
incq %rcx
cmpq %rcx, %rax
jne .LBB6_12
# %bb.13: # %_Z12checkResultsPfS_i.exit.loopexit
testl %edx, %edx
je .LBB6_15
# %bb.14:
movl $.Lstr, %edi
callq puts@PLT
.LBB6_15: # %.critedge
movslq %r14d, %rax
movss -4(%r12,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss 4(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str.5, %edi
movl %r14d, %esi
movb $2, %al
callq printf
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
.LBB6_16:
movl %r13d, %eax
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12parallelScanPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10addPreSumsPfS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12parallelScanPfS_i,@object # @_Z12parallelScanPfS_i
.section .rodata,"a",@progbits
.globl _Z12parallelScanPfS_i
.p2align 3, 0x0
_Z12parallelScanPfS_i:
.quad _Z27__device_stub__parallelScanPfS_i
.size _Z12parallelScanPfS_i, 8
.type _Z10addPreSumsPfS_,@object # @_Z10addPreSumsPfS_
.globl _Z10addPreSumsPfS_
.p2align 3, 0x0
_Z10addPreSumsPfS_:
.quad _Z25__device_stub__addPreSumsPfS_
.size _Z10addPreSumsPfS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Usage %s N\n"
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "problem1.inp"
.size .L.str.2, 13
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "r"
.size .L.str.3, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d\n%f\n%f\n"
.size .L.str.5, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12parallelScanPfS_i"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10addPreSumsPfS_"
.size .L__unnamed_2, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Test Failed"
.size .Lstr, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__parallelScanPfS_i
.addrsig_sym _Z25__device_stub__addPreSumsPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12parallelScanPfS_i
.addrsig_sym _Z10addPreSumsPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* compile as: nvcc bindlessTexture.cu */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define N 1024
// texture object is a kernel argument
__global__ void kernel(cudaTextureObject_t tex) {
int i = blockIdx.x *blockDim.x + threadIdx.x;
float x = tex1Dfetch<float>(tex, i);
// do some work using x ...
}
void call_kernel(cudaTextureObject_t tex) {
dim3 block(128,1,1);
dim3 grid(N/block.x,1,1);
kernel <<<grid, block>>>(tex);
}
int main() {
// declare and allocate memory
float *buffer;
cudaMalloc(&buffer, N*sizeof(float));
// create texture object
cudaResourceDesc resDesc;
memset(&resDesc, 0, sizeof(resDesc));
resDesc.resType = cudaResourceTypeLinear;
resDesc.res.linear.devPtr = buffer;
resDesc.res.linear.desc.f = cudaChannelFormatKindFloat;
resDesc.res.linear.desc.x = 32; // bits per channel
resDesc.res.linear.sizeInBytes = N*sizeof(float);
cudaTextureDesc texDesc;
memset(&texDesc, 0, sizeof(texDesc));
texDesc.readMode = cudaReadModeElementType;
// create texture object: we only have to do this once!
cudaTextureObject_t tex=0;
cudaCreateTextureObject(&tex, &resDesc, &texDesc, NULL);
call_kernel(tex); // pass texture as argument
// destroy texture object
cudaDestroyTextureObject(tex);
cudaFree(buffer);
} | code for sm_80
Function : _Z6kernely
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* compile as: nvcc bindlessTexture.cu */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define N 1024
// texture object is a kernel argument
__global__ void kernel(cudaTextureObject_t tex) {
int i = blockIdx.x *blockDim.x + threadIdx.x;
float x = tex1Dfetch<float>(tex, i);
// do some work using x ...
}
void call_kernel(cudaTextureObject_t tex) {
dim3 block(128,1,1);
dim3 grid(N/block.x,1,1);
kernel <<<grid, block>>>(tex);
}
int main() {
// declare and allocate memory
float *buffer;
cudaMalloc(&buffer, N*sizeof(float));
// create texture object
cudaResourceDesc resDesc;
memset(&resDesc, 0, sizeof(resDesc));
resDesc.resType = cudaResourceTypeLinear;
resDesc.res.linear.devPtr = buffer;
resDesc.res.linear.desc.f = cudaChannelFormatKindFloat;
resDesc.res.linear.desc.x = 32; // bits per channel
resDesc.res.linear.sizeInBytes = N*sizeof(float);
cudaTextureDesc texDesc;
memset(&texDesc, 0, sizeof(texDesc));
texDesc.readMode = cudaReadModeElementType;
// create texture object: we only have to do this once!
cudaTextureObject_t tex=0;
cudaCreateTextureObject(&tex, &resDesc, &texDesc, NULL);
call_kernel(tex); // pass texture as argument
// destroy texture object
cudaDestroyTextureObject(tex);
cudaFree(buffer);
} | .file "tmpxft_001314ca_00000000-6_bindlessTexture.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z6kernelyy
.type _Z24__device_stub__Z6kernelyy, @function
_Z24__device_stub__Z6kernelyy:
.LFB2083:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernely(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z24__device_stub__Z6kernelyy, .-_Z24__device_stub__Z6kernelyy
.globl _Z6kernely
.type _Z6kernely, @function
_Z6kernely:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z6kernelyy
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z6kernely, .-_Z6kernely
.globl _Z11call_kernely
.type _Z11call_kernely, @function
_Z11call_kernely:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movl $1, 12(%rsp)
movl $8, 20(%rsp)
movl $1, 24(%rsp)
movl $128, 8(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movq %rbx, %rdi
call _Z24__device_stub__Z6kernelyy
jmp .L11
.cfi_endproc
.LFE2057:
.size _Z11call_kernely, .-_Z11call_kernely
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rsi
pxor %xmm0, %xmm0
movups %xmm0, 20(%rsp)
movups %xmm0, 36(%rsp)
movups %xmm0, 52(%rsp)
movups %xmm0, 64(%rsp)
movl $2, 16(%rsp)
movq (%rsp), %rax
movq %rax, 24(%rsp)
movl $2, 48(%rsp)
movl $32, 32(%rsp)
movq $4096, 56(%rsp)
leaq 80(%rsp), %rdx
movaps %xmm0, 80(%rsp)
movaps %xmm0, 96(%rsp)
movaps %xmm0, 112(%rsp)
movaps %xmm0, 128(%rsp)
movq $0, 144(%rsp)
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $0, %ecx
call cudaCreateTextureObject@PLT
movq 8(%rsp), %rdi
call _Z11call_kernely
movq 8(%rsp), %rdi
call cudaDestroyTextureObject@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernely"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernely(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
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