system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* compile as: nvcc bindlessTexture.cu */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define N 1024
// texture object is a kernel argument
__global__ void kernel(cudaTextureObject_t tex) {
int i = blockIdx.x *blockDim.x + threadIdx.x;
float x = tex1Dfetch<float>(tex, i);
// do some work using x ...
}
void call_kernel(cudaTextureObject_t tex) {
dim3 block(128,1,1);
dim3 grid(N/block.x,1,1);
kernel <<<grid, block>>>(tex);
}
int main() {
// declare and allocate memory
float *buffer;
cudaMalloc(&buffer, N*sizeof(float));
// create texture object
cudaResourceDesc resDesc;
memset(&resDesc, 0, sizeof(resDesc));
resDesc.resType = cudaResourceTypeLinear;
resDesc.res.linear.devPtr = buffer;
resDesc.res.linear.desc.f = cudaChannelFormatKindFloat;
resDesc.res.linear.desc.x = 32; // bits per channel
resDesc.res.linear.sizeInBytes = N*sizeof(float);
cudaTextureDesc texDesc;
memset(&texDesc, 0, sizeof(texDesc));
texDesc.readMode = cudaReadModeElementType;
// create texture object: we only have to do this once!
cudaTextureObject_t tex=0;
cudaCreateTextureObject(&tex, &resDesc, &texDesc, NULL);
call_kernel(tex); // pass texture as argument
// destroy texture object
cudaDestroyTextureObject(tex);
cudaFree(buffer);
} | /* compile as: nvcc bindlessTexture.cu */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define N 1024
// texture object is a kernel argument
__global__ void kernel(hipTextureObject_t tex) {
int i = blockIdx.x *blockDim.x + threadIdx.x;
float x = tex1Dfetch<float>(tex, i);
// do some work using x ...
}
void call_kernel(hipTextureObject_t tex) {
dim3 block(128,1,1);
dim3 grid(N/block.x,1,1);
kernel <<<grid, block>>>(tex);
}
int main() {
// declare and allocate memory
float *buffer;
hipMalloc(&buffer, N*sizeof(float));
// create texture object
hipResourceDesc resDesc;
memset(&resDesc, 0, sizeof(resDesc));
resDesc.resType = hipResourceTypeLinear;
resDesc.res.linear.devPtr = buffer;
resDesc.res.linear.desc.f = hipChannelFormatKindFloat;
resDesc.res.linear.desc.x = 32; // bits per channel
resDesc.res.linear.sizeInBytes = N*sizeof(float);
hipTextureDesc texDesc;
memset(&texDesc, 0, sizeof(texDesc));
texDesc.readMode = hipReadModeElementType;
// create texture object: we only have to do this once!
hipTextureObject_t tex=0;
hipCreateTextureObject(&tex, &resDesc, &texDesc, NULL);
call_kernel(tex); // pass texture as argument
// destroy texture object
hipDestroyTextureObject(tex);
hipFree(buffer);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* compile as: nvcc bindlessTexture.cu */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define N 1024
// texture object is a kernel argument
__global__ void kernel(hipTextureObject_t tex) {
int i = blockIdx.x *blockDim.x + threadIdx.x;
float x = tex1Dfetch<float>(tex, i);
// do some work using x ...
}
void call_kernel(hipTextureObject_t tex) {
dim3 block(128,1,1);
dim3 grid(N/block.x,1,1);
kernel <<<grid, block>>>(tex);
}
int main() {
// declare and allocate memory
float *buffer;
hipMalloc(&buffer, N*sizeof(float));
// create texture object
hipResourceDesc resDesc;
memset(&resDesc, 0, sizeof(resDesc));
resDesc.resType = hipResourceTypeLinear;
resDesc.res.linear.devPtr = buffer;
resDesc.res.linear.desc.f = hipChannelFormatKindFloat;
resDesc.res.linear.desc.x = 32; // bits per channel
resDesc.res.linear.sizeInBytes = N*sizeof(float);
hipTextureDesc texDesc;
memset(&texDesc, 0, sizeof(texDesc));
texDesc.readMode = hipReadModeElementType;
// create texture object: we only have to do this once!
hipTextureObject_t tex=0;
hipCreateTextureObject(&tex, &resDesc, &texDesc, NULL);
call_kernel(tex); // pass texture as argument
// destroy texture object
hipDestroyTextureObject(tex);
hipFree(buffer);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelP13__hip_texture
.globl _Z6kernelP13__hip_texture
.p2align 8
.type _Z6kernelP13__hip_texture,@function
_Z6kernelP13__hip_texture:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelP13__hip_texture
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelP13__hip_texture, .Lfunc_end0-_Z6kernelP13__hip_texture
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelP13__hip_texture
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z6kernelP13__hip_texture.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* compile as: nvcc bindlessTexture.cu */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#define N 1024
// texture object is a kernel argument
__global__ void kernel(hipTextureObject_t tex) {
int i = blockIdx.x *blockDim.x + threadIdx.x;
float x = tex1Dfetch<float>(tex, i);
// do some work using x ...
}
void call_kernel(hipTextureObject_t tex) {
dim3 block(128,1,1);
dim3 grid(N/block.x,1,1);
kernel <<<grid, block>>>(tex);
}
int main() {
// declare and allocate memory
float *buffer;
hipMalloc(&buffer, N*sizeof(float));
// create texture object
hipResourceDesc resDesc;
memset(&resDesc, 0, sizeof(resDesc));
resDesc.resType = hipResourceTypeLinear;
resDesc.res.linear.devPtr = buffer;
resDesc.res.linear.desc.f = hipChannelFormatKindFloat;
resDesc.res.linear.desc.x = 32; // bits per channel
resDesc.res.linear.sizeInBytes = N*sizeof(float);
hipTextureDesc texDesc;
memset(&texDesc, 0, sizeof(texDesc));
texDesc.readMode = hipReadModeElementType;
// create texture object: we only have to do this once!
hipTextureObject_t tex=0;
hipCreateTextureObject(&tex, &resDesc, &texDesc, NULL);
call_kernel(tex); // pass texture as argument
// destroy texture object
hipDestroyTextureObject(tex);
hipFree(buffer);
} | .text
.file "bindlessTexture.hip"
.globl _Z21__device_stub__kernelP13__hip_texture # -- Begin function _Z21__device_stub__kernelP13__hip_texture
.p2align 4, 0x90
.type _Z21__device_stub__kernelP13__hip_texture,@function
_Z21__device_stub__kernelP13__hip_texture: # @_Z21__device_stub__kernelP13__hip_texture
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z6kernelP13__hip_texture, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelP13__hip_texture, .Lfunc_end0-_Z21__device_stub__kernelP13__hip_texture
.cfi_endproc
# -- End function
.globl _Z11call_kernelP13__hip_texture # -- Begin function _Z11call_kernelP13__hip_texture
.p2align 4, 0x90
.type _Z11call_kernelP13__hip_texture,@function
_Z11call_kernelP13__hip_texture: # @_Z11call_kernelP13__hip_texture
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
movq %rdi, %rbx
movabsq $4294967304, %rdi # imm = 0x100000008
leaq 120(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %rbx, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, (%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movq %rsp, %r9
movl $_Z6kernelP13__hip_texture, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11call_kernelP13__hip_texture, .Lfunc_end1-_Z11call_kernelP13__hip_texture
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
xorps %xmm0, %xmm0
movaps %xmm0, 16(%rsp)
movaps %xmm0, 48(%rsp)
movaps %xmm0, 32(%rsp)
movaps %xmm0, 64(%rsp)
movl $2, 16(%rsp)
movq 8(%rsp), %rax
movq %rax, 24(%rsp)
movl $2, 48(%rsp)
movl $32, 32(%rsp)
movq $4096, 56(%rsp) # imm = 0x1000
movaps %xmm0, 128(%rsp)
movaps %xmm0, 112(%rsp)
movaps %xmm0, 96(%rsp)
movaps %xmm0, 80(%rsp)
movq $0, (%rsp)
movq %rsp, %rdi
leaq 16(%rsp), %rsi
leaq 80(%rsp), %rdx
xorl %ecx, %ecx
callq hipCreateTextureObject
movq (%rsp), %rdi
callq _Z11call_kernelP13__hip_texture
movq (%rsp), %rdi
callq hipDestroyTextureObject
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelP13__hip_texture, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelP13__hip_texture,@object # @_Z6kernelP13__hip_texture
.section .rodata,"a",@progbits
.globl _Z6kernelP13__hip_texture
.p2align 3, 0x0
_Z6kernelP13__hip_texture:
.quad _Z21__device_stub__kernelP13__hip_texture
.size _Z6kernelP13__hip_texture, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelP13__hip_texture"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelP13__hip_texture
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelP13__hip_texture
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernely
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelP13__hip_texture
.globl _Z6kernelP13__hip_texture
.p2align 8
.type _Z6kernelP13__hip_texture,@function
_Z6kernelP13__hip_texture:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelP13__hip_texture
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelP13__hip_texture, .Lfunc_end0-_Z6kernelP13__hip_texture
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelP13__hip_texture
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z6kernelP13__hip_texture.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001314ca_00000000-6_bindlessTexture.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z6kernelyy
.type _Z24__device_stub__Z6kernelyy, @function
_Z24__device_stub__Z6kernelyy:
.LFB2083:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6kernely(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z24__device_stub__Z6kernelyy, .-_Z24__device_stub__Z6kernelyy
.globl _Z6kernely
.type _Z6kernely, @function
_Z6kernely:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z6kernelyy
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z6kernely, .-_Z6kernely
.globl _Z11call_kernely
.type _Z11call_kernely, @function
_Z11call_kernely:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movl $1, 12(%rsp)
movl $8, 20(%rsp)
movl $1, 24(%rsp)
movl $128, 8(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movq %rbx, %rdi
call _Z24__device_stub__Z6kernelyy
jmp .L11
.cfi_endproc
.LFE2057:
.size _Z11call_kernely, .-_Z11call_kernely
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rsi
pxor %xmm0, %xmm0
movups %xmm0, 20(%rsp)
movups %xmm0, 36(%rsp)
movups %xmm0, 52(%rsp)
movups %xmm0, 64(%rsp)
movl $2, 16(%rsp)
movq (%rsp), %rax
movq %rax, 24(%rsp)
movl $2, 48(%rsp)
movl $32, 32(%rsp)
movq $4096, 56(%rsp)
leaq 80(%rsp), %rdx
movaps %xmm0, 80(%rsp)
movaps %xmm0, 96(%rsp)
movaps %xmm0, 112(%rsp)
movaps %xmm0, 128(%rsp)
movq $0, 144(%rsp)
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $0, %ecx
call cudaCreateTextureObject@PLT
movq 8(%rsp), %rdi
call _Z11call_kernely
movq 8(%rsp), %rdi
call cudaDestroyTextureObject@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernely"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernely(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "bindlessTexture.hip"
.globl _Z21__device_stub__kernelP13__hip_texture # -- Begin function _Z21__device_stub__kernelP13__hip_texture
.p2align 4, 0x90
.type _Z21__device_stub__kernelP13__hip_texture,@function
_Z21__device_stub__kernelP13__hip_texture: # @_Z21__device_stub__kernelP13__hip_texture
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z6kernelP13__hip_texture, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelP13__hip_texture, .Lfunc_end0-_Z21__device_stub__kernelP13__hip_texture
.cfi_endproc
# -- End function
.globl _Z11call_kernelP13__hip_texture # -- Begin function _Z11call_kernelP13__hip_texture
.p2align 4, 0x90
.type _Z11call_kernelP13__hip_texture,@function
_Z11call_kernelP13__hip_texture: # @_Z11call_kernelP13__hip_texture
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $64, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -16
movq %rdi, %rbx
movabsq $4294967304, %rdi # imm = 0x100000008
leaq 120(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %rbx, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, (%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
movq %rsp, %r9
movl $_Z6kernelP13__hip_texture, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $64, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11call_kernelP13__hip_texture, .Lfunc_end1-_Z11call_kernelP13__hip_texture
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
xorps %xmm0, %xmm0
movaps %xmm0, 16(%rsp)
movaps %xmm0, 48(%rsp)
movaps %xmm0, 32(%rsp)
movaps %xmm0, 64(%rsp)
movl $2, 16(%rsp)
movq 8(%rsp), %rax
movq %rax, 24(%rsp)
movl $2, 48(%rsp)
movl $32, 32(%rsp)
movq $4096, 56(%rsp) # imm = 0x1000
movaps %xmm0, 128(%rsp)
movaps %xmm0, 112(%rsp)
movaps %xmm0, 96(%rsp)
movaps %xmm0, 80(%rsp)
movq $0, (%rsp)
movq %rsp, %rdi
leaq 16(%rsp), %rsi
leaq 80(%rsp), %rdx
xorl %ecx, %ecx
callq hipCreateTextureObject
movq (%rsp), %rdi
callq _Z11call_kernelP13__hip_texture
movq (%rsp), %rdi
callq hipDestroyTextureObject
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelP13__hip_texture, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelP13__hip_texture,@object # @_Z6kernelP13__hip_texture
.section .rodata,"a",@progbits
.globl _Z6kernelP13__hip_texture
.p2align 3, 0x0
_Z6kernelP13__hip_texture:
.quad _Z21__device_stub__kernelP13__hip_texture
.size _Z6kernelP13__hip_texture, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6kernelP13__hip_texture"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelP13__hip_texture
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelP13__hip_texture
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#define N 10
__global__ void sum(int *a,
int *b, int *c)
{
int i = blockIdx.x;
c[i] = a[i] + b[i];
}
int main( void ) {
int host_a[N];
int host_b[N];
int host_c[N];
for (int i=0; i<N; i++) {
host_a[i] = i;
host_b[i] = i;
}
int *dev_a, *dev_b, *dev_c;
cudaMalloc(&dev_a, sizeof(int) * N);
cudaMalloc(&dev_b, sizeof(int) * N);
cudaMalloc(&dev_c, sizeof(int) * N);
cudaMemcpy(dev_a, host_a, sizeof(int) * N, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, host_b, sizeof(int) * N,
cudaMemcpyHostToDevice);
sum<<<N, 1>>>(dev_a, dev_b, dev_c);
cudaMemcpy(host_c, dev_c, sizeof(int) * N, cudaMemcpyDeviceToHost);
for (int i=0; i<N; i++) {
printf("%d ", host_c[i]);
}
printf("\n");
} | code for sm_80
Function : _Z3sumPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define N 10
__global__ void sum(int *a,
int *b, int *c)
{
int i = blockIdx.x;
c[i] = a[i] + b[i];
}
int main( void ) {
int host_a[N];
int host_b[N];
int host_c[N];
for (int i=0; i<N; i++) {
host_a[i] = i;
host_b[i] = i;
}
int *dev_a, *dev_b, *dev_c;
cudaMalloc(&dev_a, sizeof(int) * N);
cudaMalloc(&dev_b, sizeof(int) * N);
cudaMalloc(&dev_c, sizeof(int) * N);
cudaMemcpy(dev_a, host_a, sizeof(int) * N, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, host_b, sizeof(int) * N,
cudaMemcpyHostToDevice);
sum<<<N, 1>>>(dev_a, dev_b, dev_c);
cudaMemcpy(host_c, dev_c, sizeof(int) * N, cudaMemcpyDeviceToHost);
for (int i=0; i<N; i++) {
printf("%d ", host_c[i]);
}
printf("\n");
} | .file "tmpxft_00190b0b_00000000-6_2_par_sum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3sumPiS_S_PiS_S_
.type _Z26__device_stub__Z3sumPiS_S_PiS_S_, @function
_Z26__device_stub__Z3sumPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3sumPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3sumPiS_S_PiS_S_, .-_Z26__device_stub__Z3sumPiS_S_PiS_S_
.globl _Z3sumPiS_S_
.type _Z3sumPiS_S_, @function
_Z3sumPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3sumPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3sumPiS_S_, .-_Z3sumPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $192, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
.L12:
movl %eax, 48(%rsp,%rax,4)
movl %eax, 96(%rsp,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L12
movq %rsp, %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $10, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 144(%rsp), %rbx
movl $2, %ecx
movl $40, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 184(%rsp), %r12
leaq .LC0(%rip), %rbp
.L14:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L14
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $192, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3sumPiS_S_PiS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z3sumPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3sumPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define N 10
__global__ void sum(int *a,
int *b, int *c)
{
int i = blockIdx.x;
c[i] = a[i] + b[i];
}
int main( void ) {
int host_a[N];
int host_b[N];
int host_c[N];
for (int i=0; i<N; i++) {
host_a[i] = i;
host_b[i] = i;
}
int *dev_a, *dev_b, *dev_c;
cudaMalloc(&dev_a, sizeof(int) * N);
cudaMalloc(&dev_b, sizeof(int) * N);
cudaMalloc(&dev_c, sizeof(int) * N);
cudaMemcpy(dev_a, host_a, sizeof(int) * N, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, host_b, sizeof(int) * N,
cudaMemcpyHostToDevice);
sum<<<N, 1>>>(dev_a, dev_b, dev_c);
cudaMemcpy(host_c, dev_c, sizeof(int) * N, cudaMemcpyDeviceToHost);
for (int i=0; i<N; i++) {
printf("%d ", host_c[i]);
}
printf("\n");
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define N 10
__global__ void sum(int *a,
int *b, int *c)
{
int i = blockIdx.x;
c[i] = a[i] + b[i];
}
int main( void ) {
int host_a[N];
int host_b[N];
int host_c[N];
for (int i=0; i<N; i++) {
host_a[i] = i;
host_b[i] = i;
}
int *dev_a, *dev_b, *dev_c;
hipMalloc(&dev_a, sizeof(int) * N);
hipMalloc(&dev_b, sizeof(int) * N);
hipMalloc(&dev_c, sizeof(int) * N);
hipMemcpy(dev_a, host_a, sizeof(int) * N, hipMemcpyHostToDevice);
hipMemcpy(dev_b, host_b, sizeof(int) * N,
hipMemcpyHostToDevice);
sum<<<N, 1>>>(dev_a, dev_b, dev_c);
hipMemcpy(host_c, dev_c, sizeof(int) * N, hipMemcpyDeviceToHost);
for (int i=0; i<N; i++) {
printf("%d ", host_c[i]);
}
printf("\n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define N 10
__global__ void sum(int *a,
int *b, int *c)
{
int i = blockIdx.x;
c[i] = a[i] + b[i];
}
int main( void ) {
int host_a[N];
int host_b[N];
int host_c[N];
for (int i=0; i<N; i++) {
host_a[i] = i;
host_b[i] = i;
}
int *dev_a, *dev_b, *dev_c;
hipMalloc(&dev_a, sizeof(int) * N);
hipMalloc(&dev_b, sizeof(int) * N);
hipMalloc(&dev_c, sizeof(int) * N);
hipMemcpy(dev_a, host_a, sizeof(int) * N, hipMemcpyHostToDevice);
hipMemcpy(dev_b, host_b, sizeof(int) * N,
hipMemcpyHostToDevice);
sum<<<N, 1>>>(dev_a, dev_b, dev_c);
hipMemcpy(host_c, dev_c, sizeof(int) * N, hipMemcpyDeviceToHost);
for (int i=0; i<N; i++) {
printf("%d ", host_c[i]);
}
printf("\n");
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3sumPiS_S_
.globl _Z3sumPiS_S_
.p2align 8
.type _Z3sumPiS_S_,@function
_Z3sumPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3sumPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3sumPiS_S_, .Lfunc_end0-_Z3sumPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3sumPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3sumPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define N 10
__global__ void sum(int *a,
int *b, int *c)
{
int i = blockIdx.x;
c[i] = a[i] + b[i];
}
int main( void ) {
int host_a[N];
int host_b[N];
int host_c[N];
for (int i=0; i<N; i++) {
host_a[i] = i;
host_b[i] = i;
}
int *dev_a, *dev_b, *dev_c;
hipMalloc(&dev_a, sizeof(int) * N);
hipMalloc(&dev_b, sizeof(int) * N);
hipMalloc(&dev_c, sizeof(int) * N);
hipMemcpy(dev_a, host_a, sizeof(int) * N, hipMemcpyHostToDevice);
hipMemcpy(dev_b, host_b, sizeof(int) * N,
hipMemcpyHostToDevice);
sum<<<N, 1>>>(dev_a, dev_b, dev_c);
hipMemcpy(host_c, dev_c, sizeof(int) * N, hipMemcpyDeviceToHost);
for (int i=0; i<N; i++) {
printf("%d ", host_c[i]);
}
printf("\n");
} | .text
.file "2_par_sum.hip"
.globl _Z18__device_stub__sumPiS_S_ # -- Begin function _Z18__device_stub__sumPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__sumPiS_S_,@function
_Z18__device_stub__sumPiS_S_: # @_Z18__device_stub__sumPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3sumPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__sumPiS_S_, .Lfunc_end0-_Z18__device_stub__sumPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $240, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, 192(%rsp,%rax,4)
movl %eax, 144(%rsp,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq %rsp, %rdi
movl $40, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 192(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 144(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 9(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3sumPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 96(%rsp,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB1_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $240, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3sumPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3sumPiS_S_,@object # @_Z3sumPiS_S_
.section .rodata,"a",@progbits
.globl _Z3sumPiS_S_
.p2align 3, 0x0
_Z3sumPiS_S_:
.quad _Z18__device_stub__sumPiS_S_
.size _Z3sumPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3sumPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__sumPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3sumPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3sumPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3sumPiS_S_
.globl _Z3sumPiS_S_
.p2align 8
.type _Z3sumPiS_S_,@function
_Z3sumPiS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3sumPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3sumPiS_S_, .Lfunc_end0-_Z3sumPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3sumPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3sumPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00190b0b_00000000-6_2_par_sum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3sumPiS_S_PiS_S_
.type _Z26__device_stub__Z3sumPiS_S_PiS_S_, @function
_Z26__device_stub__Z3sumPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3sumPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3sumPiS_S_PiS_S_, .-_Z26__device_stub__Z3sumPiS_S_PiS_S_
.globl _Z3sumPiS_S_
.type _Z3sumPiS_S_, @function
_Z3sumPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3sumPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3sumPiS_S_, .-_Z3sumPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $192, %rsp
.cfi_def_cfa_offset 224
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
.L12:
movl %eax, 48(%rsp,%rax,4)
movl %eax, 96(%rsp,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L12
movq %rsp, %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $10, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 144(%rsp), %rbx
movl $2, %ecx
movl $40, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 184(%rsp), %r12
leaq .LC0(%rip), %rbp
.L14:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L14
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $192, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3sumPiS_S_PiS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z3sumPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3sumPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "2_par_sum.hip"
.globl _Z18__device_stub__sumPiS_S_ # -- Begin function _Z18__device_stub__sumPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__sumPiS_S_,@function
_Z18__device_stub__sumPiS_S_: # @_Z18__device_stub__sumPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3sumPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__sumPiS_S_, .Lfunc_end0-_Z18__device_stub__sumPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $240, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, 192(%rsp,%rax,4)
movl %eax, 144(%rsp,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq %rsp, %rdi
movl $40, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 192(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 144(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 9(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3sumPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 96(%rsp,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB1_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $240, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3sumPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3sumPiS_S_,@object # @_Z3sumPiS_S_
.section .rodata,"a",@progbits
.globl _Z3sumPiS_S_
.p2align 3, 0x0
_Z3sumPiS_S_:
.quad _Z18__device_stub__sumPiS_S_
.size _Z3sumPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3sumPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__sumPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3sumPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <vector>
bool cudaCheck(cudaError_t err) {
if (err != cudaSuccess) {
std::cerr << "Code Failed due to " << cudaGetErrorString(err) << std::endl;
exit(EXIT_FAILURE);
}
return true;
}
void printProp(cudaDeviceProp devP) {
std::cout << "Name: " << devP.name << std::endl;
std::cout << "\tTotal Global Memory: " << devP.totalGlobalMem << std::endl;
std::cout << "\tShared Memory per Block: " << devP.sharedMemPerBlock << std::endl;
std::cout << "\tWarp Size: " << devP.warpSize << std::endl;
std::cout << "\tMax Threads per Block: " << devP.maxThreadsPerBlock << std::endl;
std::cout << "\tNumber of multiprocessors: " << devP.multiProcessorCount << std::endl;
for (int i = 0; i < 3; i++) {
std::cout << "\tMax of dimension " << i << " of block: " << devP.maxThreadsDim[i] << std::endl;
}
for (int i = 0; i < 3; i++) {
std::cout << "\tMax of dimension " << i << " of grid: " << devP.maxGridSize[i] << std::endl;
}
}
void DeviceProp() {
int devCount ;
cudaGetDeviceCount(&devCount) ;
for (int i = 0; i < devCount ; ++i) {
cudaDeviceProp devP;
cudaGetDeviceProperties(&devP, i);
printProp(devP);
}
}
int vecToArr(std::vector< int > &v, int **A) {
*A = new int[v.size()];
for (int i = 0; i < v.size(); i++) {
(*A)[i] = v[i];
}
return v.size();
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <vector>
bool cudaCheck(cudaError_t err) {
if (err != cudaSuccess) {
std::cerr << "Code Failed due to " << cudaGetErrorString(err) << std::endl;
exit(EXIT_FAILURE);
}
return true;
}
void printProp(cudaDeviceProp devP) {
std::cout << "Name: " << devP.name << std::endl;
std::cout << "\tTotal Global Memory: " << devP.totalGlobalMem << std::endl;
std::cout << "\tShared Memory per Block: " << devP.sharedMemPerBlock << std::endl;
std::cout << "\tWarp Size: " << devP.warpSize << std::endl;
std::cout << "\tMax Threads per Block: " << devP.maxThreadsPerBlock << std::endl;
std::cout << "\tNumber of multiprocessors: " << devP.multiProcessorCount << std::endl;
for (int i = 0; i < 3; i++) {
std::cout << "\tMax of dimension " << i << " of block: " << devP.maxThreadsDim[i] << std::endl;
}
for (int i = 0; i < 3; i++) {
std::cout << "\tMax of dimension " << i << " of grid: " << devP.maxGridSize[i] << std::endl;
}
}
void DeviceProp() {
int devCount ;
cudaGetDeviceCount(&devCount) ;
for (int i = 0; i < devCount ; ++i) {
cudaDeviceProp devP;
cudaGetDeviceProperties(&devP, i);
printProp(devP);
}
}
int vecToArr(std::vector< int > &v, int **A) {
*A = new int[v.size()];
for (int i = 0; i < v.size(); i++) {
(*A)[i] = v[i];
}
return v.size();
} | .file "tmpxft_0018b3bd_00000000-6_core.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4038:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4038:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Code Failed due to "
.text
.globl _Z9cudaCheck9cudaError
.type _Z9cudaCheck9cudaError, @function
_Z9cudaCheck9cudaError:
.LFB4032:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
movl $1, %eax
ret
.L8:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl %edi, %ebx
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE4032:
.size _Z9cudaCheck9cudaError, .-_Z9cudaCheck9cudaError
.section .rodata.str1.1
.LC1:
.string "Name: "
.LC2:
.string "\tTotal Global Memory: "
.LC3:
.string "\tShared Memory per Block: "
.LC4:
.string "\tWarp Size: "
.LC5:
.string "\tMax Threads per Block: "
.LC6:
.string "\tNumber of multiprocessors: "
.LC7:
.string "\tMax of dimension "
.LC8:
.string " of block: "
.LC9:
.string " of grid: "
.text
.globl _Z9printProp14cudaDeviceProp
.type _Z9printProp14cudaDeviceProp, @function
_Z9printProp14cudaDeviceProp:
.LFB4033:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl $6, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
leaq 64(%rsp), %rdi
call strlen@PLT
movq %rax, %rdx
leaq 64(%rsp), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L39
cmpb $0, 56(%rbx)
je .L11
movzbl 67(%rbx), %esi
.L12:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $22, %edx
leaq .LC2(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 352(%rsp), %rsi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L40
cmpb $0, 56(%rbp)
je .L14
movzbl 67(%rbp), %esi
.L15:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $26, %edx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 360(%rsp), %rsi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L41
cmpb $0, 56(%rbp)
je .L17
movzbl 67(%rbp), %esi
.L18:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $12, %edx
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 372(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L42
cmpb $0, 56(%rbp)
je .L20
movzbl 67(%rbp), %esi
.L21:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $24, %edx
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 384(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L43
cmpb $0, 56(%rbp)
je .L23
movzbl 67(%rbp), %esi
.L24:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $28, %edx
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 452(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L44
cmpb $0, 56(%rbp)
je .L26
movzbl 67(%rbp), %esi
.L27:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $0, %ebp
leaq .LC7(%rip), %r14
leaq _ZSt4cout(%rip), %r12
leaq .LC8(%rip), %r13
jmp .L31
.L39:
call _ZSt16__throw_bad_castv@PLT
.L11:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L12
.L40:
call _ZSt16__throw_bad_castv@PLT
.L14:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L15
.L41:
call _ZSt16__throw_bad_castv@PLT
.L17:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L18
.L42:
call _ZSt16__throw_bad_castv@PLT
.L20:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L21
.L43:
call _ZSt16__throw_bad_castv@PLT
.L23:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L24
.L44:
call _ZSt16__throw_bad_castv@PLT
.L26:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L27
.L46:
call _ZSt16__throw_bad_castv@PLT
.L29:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
.L30:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbp
cmpq $3, %rbp
je .L45
.L31:
movl $18, %edx
movq %r14, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $11, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 388(%rsp,%rbp,4), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .L46
cmpb $0, 56(%r15)
je .L29
movzbl 67(%r15), %esi
jmp .L30
.L45:
movl $0, %ebp
leaq .LC7(%rip), %r14
leaq _ZSt4cout(%rip), %r12
leaq .LC9(%rip), %r13
jmp .L35
.L48:
call _ZSt16__throw_bad_castv@PLT
.L33:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
.L34:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbp
cmpq $3, %rbp
je .L47
.L35:
movl $18, %edx
movq %r14, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $10, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 400(%rsp,%rbp,4), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .L48
cmpb $0, 56(%r15)
je .L33
movzbl 67(%r15), %esi
jmp .L34
.L47:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4033:
.size _Z9printProp14cudaDeviceProp, .-_Z9printProp14cudaDeviceProp
.globl _Z10DevicePropv
.type _Z10DevicePropv, @function
_Z10DevicePropv:
.LFB4034:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1064, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
jle .L49
movl $0, %ebx
leaq 16(%rsp), %rbp
.L51:
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
subq $1040, %rsp
.cfi_def_cfa_offset 2128
movl $129, %ecx
movq %rsp, %rdi
movq %rbp, %rsi
rep movsq
call _Z9printProp14cudaDeviceProp
addl $1, %ebx
addq $1040, %rsp
.cfi_def_cfa_offset 1088
cmpl %ebx, 12(%rsp)
jg .L51
.L49:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L55
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4034:
.size _Z10DevicePropv, .-_Z10DevicePropv
.globl _Z8vecToArrRSt6vectorIiSaIiEEPPi
.type _Z8vecToArrRSt6vectorIiSaIiEEPPi, @function
_Z8vecToArrRSt6vectorIiSaIiEEPPi:
.LFB4035:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movq 8(%rdi), %rdi
subq (%rbx), %rdi
movabsq $9223372036854775800, %rax
cmpq %rdi, %rax
jb .L57
movq %rsi, %rbp
call _Znam@PLT
movq %rax, 0(%rbp)
movq (%rbx), %rsi
movl $0, %ecx
movl $0, %eax
cmpq %rsi, 8(%rbx)
je .L59
.L58:
movl (%rsi,%rcx,4), %edx
movq 0(%rbp), %rax
movl %edx, (%rax,%rcx,4)
movq (%rbx), %rsi
movq 8(%rbx), %rdx
subq %rsi, %rdx
sarq $2, %rdx
movq %rdx, %rax
addq $1, %rcx
cmpq %rdx, %rcx
jb .L58
.L59:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L57:
.cfi_restore_state
call __cxa_throw_bad_array_new_length@PLT
.cfi_endproc
.LFE4035:
.size _Z8vecToArrRSt6vectorIiSaIiEEPPi, .-_Z8vecToArrRSt6vectorIiSaIiEEPPi
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4061:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <vector>
bool cudaCheck(cudaError_t err) {
if (err != cudaSuccess) {
std::cerr << "Code Failed due to " << cudaGetErrorString(err) << std::endl;
exit(EXIT_FAILURE);
}
return true;
}
void printProp(cudaDeviceProp devP) {
std::cout << "Name: " << devP.name << std::endl;
std::cout << "\tTotal Global Memory: " << devP.totalGlobalMem << std::endl;
std::cout << "\tShared Memory per Block: " << devP.sharedMemPerBlock << std::endl;
std::cout << "\tWarp Size: " << devP.warpSize << std::endl;
std::cout << "\tMax Threads per Block: " << devP.maxThreadsPerBlock << std::endl;
std::cout << "\tNumber of multiprocessors: " << devP.multiProcessorCount << std::endl;
for (int i = 0; i < 3; i++) {
std::cout << "\tMax of dimension " << i << " of block: " << devP.maxThreadsDim[i] << std::endl;
}
for (int i = 0; i < 3; i++) {
std::cout << "\tMax of dimension " << i << " of grid: " << devP.maxGridSize[i] << std::endl;
}
}
void DeviceProp() {
int devCount ;
cudaGetDeviceCount(&devCount) ;
for (int i = 0; i < devCount ; ++i) {
cudaDeviceProp devP;
cudaGetDeviceProperties(&devP, i);
printProp(devP);
}
}
int vecToArr(std::vector< int > &v, int **A) {
*A = new int[v.size()];
for (int i = 0; i < v.size(); i++) {
(*A)[i] = v[i];
}
return v.size();
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <vector>
bool cudaCheck(hipError_t err) {
if (err != hipSuccess) {
std::cerr << "Code Failed due to " << hipGetErrorString(err) << std::endl;
exit(EXIT_FAILURE);
}
return true;
}
void printProp(hipDeviceProp_t devP) {
std::cout << "Name: " << devP.name << std::endl;
std::cout << "\tTotal Global Memory: " << devP.totalGlobalMem << std::endl;
std::cout << "\tShared Memory per Block: " << devP.sharedMemPerBlock << std::endl;
std::cout << "\tWarp Size: " << devP.warpSize << std::endl;
std::cout << "\tMax Threads per Block: " << devP.maxThreadsPerBlock << std::endl;
std::cout << "\tNumber of multiprocessors: " << devP.multiProcessorCount << std::endl;
for (int i = 0; i < 3; i++) {
std::cout << "\tMax of dimension " << i << " of block: " << devP.maxThreadsDim[i] << std::endl;
}
for (int i = 0; i < 3; i++) {
std::cout << "\tMax of dimension " << i << " of grid: " << devP.maxGridSize[i] << std::endl;
}
}
void DeviceProp() {
int devCount ;
hipGetDeviceCount(&devCount) ;
for (int i = 0; i < devCount ; ++i) {
hipDeviceProp_t devP;
hipGetDeviceProperties(&devP, i);
printProp(devP);
}
}
int vecToArr(std::vector< int > &v, int **A) {
*A = new int[v.size()];
for (int i = 0; i < v.size(); i++) {
(*A)[i] = v[i];
}
return v.size();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <vector>
bool cudaCheck(hipError_t err) {
if (err != hipSuccess) {
std::cerr << "Code Failed due to " << hipGetErrorString(err) << std::endl;
exit(EXIT_FAILURE);
}
return true;
}
void printProp(hipDeviceProp_t devP) {
std::cout << "Name: " << devP.name << std::endl;
std::cout << "\tTotal Global Memory: " << devP.totalGlobalMem << std::endl;
std::cout << "\tShared Memory per Block: " << devP.sharedMemPerBlock << std::endl;
std::cout << "\tWarp Size: " << devP.warpSize << std::endl;
std::cout << "\tMax Threads per Block: " << devP.maxThreadsPerBlock << std::endl;
std::cout << "\tNumber of multiprocessors: " << devP.multiProcessorCount << std::endl;
for (int i = 0; i < 3; i++) {
std::cout << "\tMax of dimension " << i << " of block: " << devP.maxThreadsDim[i] << std::endl;
}
for (int i = 0; i < 3; i++) {
std::cout << "\tMax of dimension " << i << " of grid: " << devP.maxGridSize[i] << std::endl;
}
}
void DeviceProp() {
int devCount ;
hipGetDeviceCount(&devCount) ;
for (int i = 0; i < devCount ; ++i) {
hipDeviceProp_t devP;
hipGetDeviceProperties(&devP, i);
printProp(devP);
}
}
int vecToArr(std::vector< int > &v, int **A) {
*A = new int[v.size()];
for (int i = 0; i < v.size(); i++) {
(*A)[i] = v[i];
}
return v.size();
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <vector>
bool cudaCheck(hipError_t err) {
if (err != hipSuccess) {
std::cerr << "Code Failed due to " << hipGetErrorString(err) << std::endl;
exit(EXIT_FAILURE);
}
return true;
}
void printProp(hipDeviceProp_t devP) {
std::cout << "Name: " << devP.name << std::endl;
std::cout << "\tTotal Global Memory: " << devP.totalGlobalMem << std::endl;
std::cout << "\tShared Memory per Block: " << devP.sharedMemPerBlock << std::endl;
std::cout << "\tWarp Size: " << devP.warpSize << std::endl;
std::cout << "\tMax Threads per Block: " << devP.maxThreadsPerBlock << std::endl;
std::cout << "\tNumber of multiprocessors: " << devP.multiProcessorCount << std::endl;
for (int i = 0; i < 3; i++) {
std::cout << "\tMax of dimension " << i << " of block: " << devP.maxThreadsDim[i] << std::endl;
}
for (int i = 0; i < 3; i++) {
std::cout << "\tMax of dimension " << i << " of grid: " << devP.maxGridSize[i] << std::endl;
}
}
void DeviceProp() {
int devCount ;
hipGetDeviceCount(&devCount) ;
for (int i = 0; i < devCount ; ++i) {
hipDeviceProp_t devP;
hipGetDeviceProperties(&devP, i);
printProp(devP);
}
}
int vecToArr(std::vector< int > &v, int **A) {
*A = new int[v.size()];
for (int i = 0; i < v.size(); i++) {
(*A)[i] = v[i];
}
return v.size();
} | .text
.file "core.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z9cudaCheck10hipError_t # -- Begin function _Z9cudaCheck10hipError_t
.p2align 4, 0x90
.type _Z9cudaCheck10hipError_t,@function
_Z9cudaCheck10hipError_t: # @_Z9cudaCheck10hipError_t
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB0_2
# %bb.1:
movb $1, %al
retq
.LBB0_2:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edi, %ebx
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z9cudaCheck10hipError_t, .Lfunc_end0-_Z9cudaCheck10hipError_t
.cfi_endproc
# -- End function
.globl _Z9printProp20hipDeviceProp_tR0600 # -- Begin function _Z9printProp20hipDeviceProp_tR0600
.p2align 4, 0x90
.type _Z9printProp20hipDeviceProp_tR0600,@function
_Z9printProp20hipDeviceProp_tR0600: # @_Z9printProp20hipDeviceProp_tR0600
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 48(%rsp), %rbx
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
callq strlen
movl $_ZSt4cout, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB1_37
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_3
# %bb.2:
movzbl 67(%r14), %eax
jmp .LBB1_4
.LBB1_3:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 288(%rbx), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_37
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i10
cmpb $0, 56(%r14)
je .LBB1_7
# %bb.6:
movzbl 67(%r14), %ecx
jmp .LBB1_8
.LBB1_7:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit13
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $26, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 296(%rbx), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_37
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i15
cmpb $0, 56(%r14)
je .LBB1_11
# %bb.10:
movzbl 67(%r14), %ecx
jmp .LBB1_12
.LBB1_11:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit18
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 308(%rbx), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_37
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i20
cmpb $0, 56(%r14)
je .LBB1_15
# %bb.14:
movzbl 67(%r14), %ecx
jmp .LBB1_16
.LBB1_15:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit23
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $24, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 320(%rbx), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_37
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i25
cmpb $0, 56(%r14)
je .LBB1_19
# %bb.18:
movzbl 67(%r14), %ecx
jmp .LBB1_20
.LBB1_19:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit28
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $28, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 388(%rbx), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_37
# %bb.21: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i30
cmpb $0, 56(%r14)
je .LBB1_23
# %bb.22:
movzbl 67(%r14), %ecx
jmp .LBB1_24
.LBB1_23:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_24: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit33
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r14d, %r14d
jmp .LBB1_25
.p2align 4, 0x90
.LBB1_28: # in Loop: Header=BB1_25 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB1_29: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit38
# in Loop: Header=BB1_25 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r14
cmpq $3, %r14
je .LBB1_30
.LBB1_25: # =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.8, %esi
movl $11, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 324(%rbx,%r14,4), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB1_37
# %bb.26: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i35
# in Loop: Header=BB1_25 Depth=1
cmpb $0, 56(%r15)
je .LBB1_28
# %bb.27: # in Loop: Header=BB1_25 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB1_29
.LBB1_30: # %.preheader.preheader
xorl %r14d, %r14d
jmp .LBB1_31
.p2align 4, 0x90
.LBB1_34: # in Loop: Header=BB1_31 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB1_35: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit43
# in Loop: Header=BB1_31 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r14
cmpq $3, %r14
je .LBB1_36
.LBB1_31: # %.preheader
# =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.9, %esi
movl $10, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 336(%rbx,%r14,4), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB1_37
# %bb.32: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i40
# in Loop: Header=BB1_31 Depth=1
cmpb $0, 56(%r15)
je .LBB1_34
# %bb.33: # in Loop: Header=BB1_31 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB1_35
.LBB1_36:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_37:
.cfi_def_cfa_offset 48
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z9printProp20hipDeviceProp_tR0600, .Lfunc_end1-_Z9printProp20hipDeviceProp_tR0600
.cfi_endproc
# -- End function
.globl _Z10DevicePropv # -- Begin function _Z10DevicePropv
.p2align 4, 0x90
.type _Z10DevicePropv,@function
_Z10DevicePropv: # @_Z10DevicePropv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $2952, %rsp # imm = 0xB88
.cfi_def_cfa_offset 2976
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 1476(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 1476(%rsp)
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
xorl %ebx, %ebx
leaq 1480(%rsp), %r14
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
movl $184, %ecx
movq %rsp, %rdi
movq %r14, %rsi
rep
callq _Z9printProp20hipDeviceProp_tR0600
incl %ebx
cmpl 1476(%rsp), %ebx
jl .LBB2_2
.LBB2_3: # %._crit_edge
addq $2952, %rsp # imm = 0xB88
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10DevicePropv, .Lfunc_end2-_Z10DevicePropv
.cfi_endproc
# -- End function
.globl _Z8vecToArrRSt6vectorIiSaIiEEPPi # -- Begin function _Z8vecToArrRSt6vectorIiSaIiEEPPi
.p2align 4, 0x90
.type _Z8vecToArrRSt6vectorIiSaIiEEPPi,@function
_Z8vecToArrRSt6vectorIiSaIiEEPPi: # @_Z8vecToArrRSt6vectorIiSaIiEEPPi
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
movq 8(%rdi), %rax
subq (%rdi), %rax
movq %rsi, %r14
movq $-1, %rdi
cmovnsq %rax, %rdi
callq _Znam
movq %rax, (%r14)
movq (%rbx), %rdx
movq 8(%rbx), %rsi
movq %rsi, %rcx
subq %rdx, %rcx
sarq $2, %rcx
cmpq %rdx, %rsi
je .LBB3_3
# %bb.1: # %.lr.ph.preheader
cmpq $1, %rcx
movq %rcx, %rsi
adcq $0, %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rdx,%rdi,4), %r8d
movl %r8d, (%rax,%rdi,4)
incq %rdi
cmpq %rdi, %rsi
jne .LBB3_2
.LBB3_3: # %._crit_edge
movl %ecx, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z8vecToArrRSt6vectorIiSaIiEEPPi, .Lfunc_end3-_Z8vecToArrRSt6vectorIiSaIiEEPPi
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Code Failed due to "
.size .L.str, 20
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Name: "
.size .L.str.1, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\tTotal Global Memory: "
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\tShared Memory per Block: "
.size .L.str.3, 27
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\tWarp Size: "
.size .L.str.4, 13
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\tMax Threads per Block: "
.size .L.str.5, 25
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\tNumber of multiprocessors: "
.size .L.str.6, 29
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\tMax of dimension "
.size .L.str.7, 19
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " of block: "
.size .L.str.8, 12
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " of grid: "
.size .L.str.9, 11
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018b3bd_00000000-6_core.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4038:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4038:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Code Failed due to "
.text
.globl _Z9cudaCheck9cudaError
.type _Z9cudaCheck9cudaError, @function
_Z9cudaCheck9cudaError:
.LFB4032:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L8
movl $1, %eax
ret
.L8:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl %edi, %ebx
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE4032:
.size _Z9cudaCheck9cudaError, .-_Z9cudaCheck9cudaError
.section .rodata.str1.1
.LC1:
.string "Name: "
.LC2:
.string "\tTotal Global Memory: "
.LC3:
.string "\tShared Memory per Block: "
.LC4:
.string "\tWarp Size: "
.LC5:
.string "\tMax Threads per Block: "
.LC6:
.string "\tNumber of multiprocessors: "
.LC7:
.string "\tMax of dimension "
.LC8:
.string " of block: "
.LC9:
.string " of grid: "
.text
.globl _Z9printProp14cudaDeviceProp
.type _Z9printProp14cudaDeviceProp, @function
_Z9printProp14cudaDeviceProp:
.LFB4033:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl $6, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
leaq 64(%rsp), %rdi
call strlen@PLT
movq %rax, %rdx
leaq 64(%rsp), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L39
cmpb $0, 56(%rbx)
je .L11
movzbl 67(%rbx), %esi
.L12:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $22, %edx
leaq .LC2(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 352(%rsp), %rsi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L40
cmpb $0, 56(%rbp)
je .L14
movzbl 67(%rbp), %esi
.L15:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $26, %edx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 360(%rsp), %rsi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L41
cmpb $0, 56(%rbp)
je .L17
movzbl 67(%rbp), %esi
.L18:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $12, %edx
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 372(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L42
cmpb $0, 56(%rbp)
je .L20
movzbl 67(%rbp), %esi
.L21:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $24, %edx
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 384(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L43
cmpb $0, 56(%rbp)
je .L23
movzbl 67(%rbp), %esi
.L24:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $28, %edx
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 452(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L44
cmpb $0, 56(%rbp)
je .L26
movzbl 67(%rbp), %esi
.L27:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $0, %ebp
leaq .LC7(%rip), %r14
leaq _ZSt4cout(%rip), %r12
leaq .LC8(%rip), %r13
jmp .L31
.L39:
call _ZSt16__throw_bad_castv@PLT
.L11:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L12
.L40:
call _ZSt16__throw_bad_castv@PLT
.L14:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L15
.L41:
call _ZSt16__throw_bad_castv@PLT
.L17:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L18
.L42:
call _ZSt16__throw_bad_castv@PLT
.L20:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L21
.L43:
call _ZSt16__throw_bad_castv@PLT
.L23:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L24
.L44:
call _ZSt16__throw_bad_castv@PLT
.L26:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L27
.L46:
call _ZSt16__throw_bad_castv@PLT
.L29:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
.L30:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbp
cmpq $3, %rbp
je .L45
.L31:
movl $18, %edx
movq %r14, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $11, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 388(%rsp,%rbp,4), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .L46
cmpb $0, 56(%r15)
je .L29
movzbl 67(%r15), %esi
jmp .L30
.L45:
movl $0, %ebp
leaq .LC7(%rip), %r14
leaq _ZSt4cout(%rip), %r12
leaq .LC9(%rip), %r13
jmp .L35
.L48:
call _ZSt16__throw_bad_castv@PLT
.L33:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
.L34:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbp
cmpq $3, %rbp
je .L47
.L35:
movl $18, %edx
movq %r14, %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $10, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 400(%rsp,%rbp,4), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .L48
cmpb $0, 56(%r15)
je .L33
movzbl 67(%r15), %esi
jmp .L34
.L47:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4033:
.size _Z9printProp14cudaDeviceProp, .-_Z9printProp14cudaDeviceProp
.globl _Z10DevicePropv
.type _Z10DevicePropv, @function
_Z10DevicePropv:
.LFB4034:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1064, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
jle .L49
movl $0, %ebx
leaq 16(%rsp), %rbp
.L51:
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
subq $1040, %rsp
.cfi_def_cfa_offset 2128
movl $129, %ecx
movq %rsp, %rdi
movq %rbp, %rsi
rep movsq
call _Z9printProp14cudaDeviceProp
addl $1, %ebx
addq $1040, %rsp
.cfi_def_cfa_offset 1088
cmpl %ebx, 12(%rsp)
jg .L51
.L49:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L55
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4034:
.size _Z10DevicePropv, .-_Z10DevicePropv
.globl _Z8vecToArrRSt6vectorIiSaIiEEPPi
.type _Z8vecToArrRSt6vectorIiSaIiEEPPi, @function
_Z8vecToArrRSt6vectorIiSaIiEEPPi:
.LFB4035:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movq 8(%rdi), %rdi
subq (%rbx), %rdi
movabsq $9223372036854775800, %rax
cmpq %rdi, %rax
jb .L57
movq %rsi, %rbp
call _Znam@PLT
movq %rax, 0(%rbp)
movq (%rbx), %rsi
movl $0, %ecx
movl $0, %eax
cmpq %rsi, 8(%rbx)
je .L59
.L58:
movl (%rsi,%rcx,4), %edx
movq 0(%rbp), %rax
movl %edx, (%rax,%rcx,4)
movq (%rbx), %rsi
movq 8(%rbx), %rdx
subq %rsi, %rdx
sarq $2, %rdx
movq %rdx, %rax
addq $1, %rcx
cmpq %rdx, %rcx
jb .L58
.L59:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L57:
.cfi_restore_state
call __cxa_throw_bad_array_new_length@PLT
.cfi_endproc
.LFE4035:
.size _Z8vecToArrRSt6vectorIiSaIiEEPPi, .-_Z8vecToArrRSt6vectorIiSaIiEEPPi
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4061:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "core.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z9cudaCheck10hipError_t # -- Begin function _Z9cudaCheck10hipError_t
.p2align 4, 0x90
.type _Z9cudaCheck10hipError_t,@function
_Z9cudaCheck10hipError_t: # @_Z9cudaCheck10hipError_t
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB0_2
# %bb.1:
movb $1, %al
retq
.LBB0_2:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %edi, %ebx
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z9cudaCheck10hipError_t, .Lfunc_end0-_Z9cudaCheck10hipError_t
.cfi_endproc
# -- End function
.globl _Z9printProp20hipDeviceProp_tR0600 # -- Begin function _Z9printProp20hipDeviceProp_tR0600
.p2align 4, 0x90
.type _Z9printProp20hipDeviceProp_tR0600,@function
_Z9printProp20hipDeviceProp_tR0600: # @_Z9printProp20hipDeviceProp_tR0600
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 48(%rsp), %rbx
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
callq strlen
movl $_ZSt4cout, %edi
movq %rbx, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB1_37
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_3
# %bb.2:
movzbl 67(%r14), %eax
jmp .LBB1_4
.LBB1_3:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 288(%rbx), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_37
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i10
cmpb $0, 56(%r14)
je .LBB1_7
# %bb.6:
movzbl 67(%r14), %ecx
jmp .LBB1_8
.LBB1_7:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit13
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $26, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 296(%rbx), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_37
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i15
cmpb $0, 56(%r14)
je .LBB1_11
# %bb.10:
movzbl 67(%r14), %ecx
jmp .LBB1_12
.LBB1_11:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit18
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 308(%rbx), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_37
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i20
cmpb $0, 56(%r14)
je .LBB1_15
# %bb.14:
movzbl 67(%r14), %ecx
jmp .LBB1_16
.LBB1_15:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit23
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $24, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 320(%rbx), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_37
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i25
cmpb $0, 56(%r14)
je .LBB1_19
# %bb.18:
movzbl 67(%r14), %ecx
jmp .LBB1_20
.LBB1_19:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit28
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $28, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 388(%rbx), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB1_37
# %bb.21: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i30
cmpb $0, 56(%r14)
je .LBB1_23
# %bb.22:
movzbl 67(%r14), %ecx
jmp .LBB1_24
.LBB1_23:
movq %r14, %rdi
movq %rax, %r15
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r15, %rax
.LBB1_24: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit33
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r14d, %r14d
jmp .LBB1_25
.p2align 4, 0x90
.LBB1_28: # in Loop: Header=BB1_25 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB1_29: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit38
# in Loop: Header=BB1_25 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r14
cmpq $3, %r14
je .LBB1_30
.LBB1_25: # =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.8, %esi
movl $11, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 324(%rbx,%r14,4), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB1_37
# %bb.26: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i35
# in Loop: Header=BB1_25 Depth=1
cmpb $0, 56(%r15)
je .LBB1_28
# %bb.27: # in Loop: Header=BB1_25 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB1_29
.LBB1_30: # %.preheader.preheader
xorl %r14d, %r14d
jmp .LBB1_31
.p2align 4, 0x90
.LBB1_34: # in Loop: Header=BB1_31 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB1_35: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit43
# in Loop: Header=BB1_31 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r14
cmpq $3, %r14
je .LBB1_36
.LBB1_31: # %.preheader
# =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.9, %esi
movl $10, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 336(%rbx,%r14,4), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB1_37
# %bb.32: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i40
# in Loop: Header=BB1_31 Depth=1
cmpb $0, 56(%r15)
je .LBB1_34
# %bb.33: # in Loop: Header=BB1_31 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB1_35
.LBB1_36:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_37:
.cfi_def_cfa_offset 48
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z9printProp20hipDeviceProp_tR0600, .Lfunc_end1-_Z9printProp20hipDeviceProp_tR0600
.cfi_endproc
# -- End function
.globl _Z10DevicePropv # -- Begin function _Z10DevicePropv
.p2align 4, 0x90
.type _Z10DevicePropv,@function
_Z10DevicePropv: # @_Z10DevicePropv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $2952, %rsp # imm = 0xB88
.cfi_def_cfa_offset 2976
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 1476(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 1476(%rsp)
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
xorl %ebx, %ebx
leaq 1480(%rsp), %r14
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
movl $184, %ecx
movq %rsp, %rdi
movq %r14, %rsi
rep
callq _Z9printProp20hipDeviceProp_tR0600
incl %ebx
cmpl 1476(%rsp), %ebx
jl .LBB2_2
.LBB2_3: # %._crit_edge
addq $2952, %rsp # imm = 0xB88
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10DevicePropv, .Lfunc_end2-_Z10DevicePropv
.cfi_endproc
# -- End function
.globl _Z8vecToArrRSt6vectorIiSaIiEEPPi # -- Begin function _Z8vecToArrRSt6vectorIiSaIiEEPPi
.p2align 4, 0x90
.type _Z8vecToArrRSt6vectorIiSaIiEEPPi,@function
_Z8vecToArrRSt6vectorIiSaIiEEPPi: # @_Z8vecToArrRSt6vectorIiSaIiEEPPi
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
movq 8(%rdi), %rax
subq (%rdi), %rax
movq %rsi, %r14
movq $-1, %rdi
cmovnsq %rax, %rdi
callq _Znam
movq %rax, (%r14)
movq (%rbx), %rdx
movq 8(%rbx), %rsi
movq %rsi, %rcx
subq %rdx, %rcx
sarq $2, %rcx
cmpq %rdx, %rsi
je .LBB3_3
# %bb.1: # %.lr.ph.preheader
cmpq $1, %rcx
movq %rcx, %rsi
adcq $0, %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rdx,%rdi,4), %r8d
movl %r8d, (%rax,%rdi,4)
incq %rdi
cmpq %rdi, %rsi
jne .LBB3_2
.LBB3_3: # %._crit_edge
movl %ecx, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z8vecToArrRSt6vectorIiSaIiEEPPi, .Lfunc_end3-_Z8vecToArrRSt6vectorIiSaIiEEPPi
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Code Failed due to "
.size .L.str, 20
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Name: "
.size .L.str.1, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\tTotal Global Memory: "
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\tShared Memory per Block: "
.size .L.str.3, 27
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\tWarp Size: "
.size .L.str.4, 13
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\tMax Threads per Block: "
.size .L.str.5, 25
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\tNumber of multiprocessors: "
.size .L.str.6, 29
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\tMax of dimension "
.size .L.str.7, 19
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " of block: "
.size .L.str.8, 12
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " of grid: "
.size .L.str.9, 11
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <iostream>
#include <cuda_profiler_api.h>
//#include <cutil.h>
#include <cuda_runtime.h>
float* h_A;
float* h_B;
float* h_C;
float* h_res;
float* d_A;
float* d_B;
float* d_C;
float* d_res;
__global__
//void compute(const float* A, const float* B, const float* C, float* D, int n) {
void compute(float* D, int n, int div) {
int tid = blockDim.x * blockIdx.x + threadIdx.x;
float I1 = tid * 2.0;
int thread_id = threadIdx.x % 32;
if (thread_id < div) {
__asm volatile (
" .reg .f32 %r1111;\n\t"
" .reg .f32 %r1112;\n\t"
" .reg .f32 %r1113;\n\t"
" .reg .f32 %r1114;\n\t"
" .reg .f32 %r1115;\n\t"
" .reg .f32 %r1116;\n\t"
" .reg .f32 %r1117;\n\t"
" .reg .f32 %r1118;\n\t"
" .reg .f32 %r1119;\n\t"
" .reg .f32 %r1120;\n\t"
" .reg .f32 %r1121;\n\t"
" .reg .f32 %r1122;\n\t"
" .reg .f32 %r1123;\n\t"
" .reg .f32 %r1124;\n\t"
" .reg .f32 %r1125;\n\t"
" .reg .f32 %r1126;\n\t"
" .reg .f32 %r1127;\n\t"
" .reg .f32 %r1128;\n\t"
"mov.f32 %r1112, 4.4;\n\t"
"mov.f32 %r1113, %r1112;\n\t"
"mov.f32 %r1114, 2.2;\n\t"
"mov.f32 %r1115, 3.3;\n\t"
"mov.f32 %r1116, 1.23;\n\t"
"mov.f32 %r1117, 2.42;\n\t"
"mov.f32 %r1118, 3.34;\n\t"
"mov.f32 %r1119, 5.62;\n\t"
"mov.f32 %r1120, 2.56;\n\t"
"mov.f32 %r1121, 1.56;\n\t"
"mov.f32 %r1122, 2.56;\n\t"
"mov.f32 %r1123, 5.56;\n\t"
"mov.f32 %r1124, 8.56;\n\t"
"mov.f32 %r1125, 3.56;\n\t"
"mov.f32 %r1126, 5.56;\n\t"
"mov.f32 %r1127, 6.56;\n\t"
"mov.f32 %r1128, 0.56;\n\t"
);
for (int k = 0; k < n; k++) {
__asm volatile (
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
);
}
}
__syncthreads();
// if ((blockDim.x * blockIdx.x + threadIdx.x) == 0)
*D = I1;
__syncthreads();
}
void usage() {
std::cout << "Usage ./binary <num_blocks> <num_threads_per_block> <iterations>" "threads active per warp" << std::endl;
}
int main(int argc, char **argv)
{
if (argc != 5) {
usage();
exit(1);
}
int num_blocks = atoi(argv[1]);
int num_threads_per_block = atoi(argv[2]);
int iterations = atoi(argv[3]);
int divergence = atoi(argv[4]);
// h_A = new float(2.0);
// h_B = new float(3.0);
// h_C = new float(4.0);
// cudaMalloc((void**)&d_A, sizeof(float));
// cudaMalloc((void**)&d_B, sizeof(float));
// cudaMalloc((void**)&d_C, sizeof(float));
cudaMalloc((void**)&d_res, sizeof(float));
// cudaMemcpy(d_A, h_A, sizeof(float), cudaMemcpyHostToDevice);
// cudaMemcpy(d_B, h_B, sizeof(float), cudaMemcpyHostToDevice);
// cudaMemcpy(d_C, h_C, sizeof(float), cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
float time;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
cudaProfilerStart();
// compute<<<num_blocks, num_threads_per_block>>>(d_A, d_B, d_C, d_res, iterations);
compute<<<num_blocks, num_threads_per_block>>>(d_res, iterations, divergence);
cudaProfilerStop();
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
std::cout << "GPU Elapsed Time = " << time << std::endl;
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaDeviceSynchronize();
cudaMemcpy(h_res, d_res, sizeof(float), cudaMemcpyDeviceToHost);
return 0;
} | code for sm_80
Function : _Z7computePfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0060*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0070*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0080*/ I2F.F64 R2, R0 ; /* 0x0000000000027312 */
/* 0x000e240000201c00 */
/*0090*/ DADD R2, R2, R2 ; /* 0x0000000002027229 */
/* 0x001e140000000002 */
/*00a0*/ F2F.F32.F64 R3, R2 ; /* 0x0000000200037310 */
/* 0x001e240000301000 */
/*00b0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x001fe8000c101904 */
/*00c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <iostream>
#include <cuda_profiler_api.h>
//#include <cutil.h>
#include <cuda_runtime.h>
float* h_A;
float* h_B;
float* h_C;
float* h_res;
float* d_A;
float* d_B;
float* d_C;
float* d_res;
__global__
//void compute(const float* A, const float* B, const float* C, float* D, int n) {
void compute(float* D, int n, int div) {
int tid = blockDim.x * blockIdx.x + threadIdx.x;
float I1 = tid * 2.0;
int thread_id = threadIdx.x % 32;
if (thread_id < div) {
__asm volatile (
" .reg .f32 %r1111;\n\t"
" .reg .f32 %r1112;\n\t"
" .reg .f32 %r1113;\n\t"
" .reg .f32 %r1114;\n\t"
" .reg .f32 %r1115;\n\t"
" .reg .f32 %r1116;\n\t"
" .reg .f32 %r1117;\n\t"
" .reg .f32 %r1118;\n\t"
" .reg .f32 %r1119;\n\t"
" .reg .f32 %r1120;\n\t"
" .reg .f32 %r1121;\n\t"
" .reg .f32 %r1122;\n\t"
" .reg .f32 %r1123;\n\t"
" .reg .f32 %r1124;\n\t"
" .reg .f32 %r1125;\n\t"
" .reg .f32 %r1126;\n\t"
" .reg .f32 %r1127;\n\t"
" .reg .f32 %r1128;\n\t"
"mov.f32 %r1112, 4.4;\n\t"
"mov.f32 %r1113, %r1112;\n\t"
"mov.f32 %r1114, 2.2;\n\t"
"mov.f32 %r1115, 3.3;\n\t"
"mov.f32 %r1116, 1.23;\n\t"
"mov.f32 %r1117, 2.42;\n\t"
"mov.f32 %r1118, 3.34;\n\t"
"mov.f32 %r1119, 5.62;\n\t"
"mov.f32 %r1120, 2.56;\n\t"
"mov.f32 %r1121, 1.56;\n\t"
"mov.f32 %r1122, 2.56;\n\t"
"mov.f32 %r1123, 5.56;\n\t"
"mov.f32 %r1124, 8.56;\n\t"
"mov.f32 %r1125, 3.56;\n\t"
"mov.f32 %r1126, 5.56;\n\t"
"mov.f32 %r1127, 6.56;\n\t"
"mov.f32 %r1128, 0.56;\n\t"
);
for (int k = 0; k < n; k++) {
__asm volatile (
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
);
}
}
__syncthreads();
// if ((blockDim.x * blockIdx.x + threadIdx.x) == 0)
*D = I1;
__syncthreads();
}
void usage() {
std::cout << "Usage ./binary <num_blocks> <num_threads_per_block> <iterations>" "threads active per warp" << std::endl;
}
int main(int argc, char **argv)
{
if (argc != 5) {
usage();
exit(1);
}
int num_blocks = atoi(argv[1]);
int num_threads_per_block = atoi(argv[2]);
int iterations = atoi(argv[3]);
int divergence = atoi(argv[4]);
// h_A = new float(2.0);
// h_B = new float(3.0);
// h_C = new float(4.0);
// cudaMalloc((void**)&d_A, sizeof(float));
// cudaMalloc((void**)&d_B, sizeof(float));
// cudaMalloc((void**)&d_C, sizeof(float));
cudaMalloc((void**)&d_res, sizeof(float));
// cudaMemcpy(d_A, h_A, sizeof(float), cudaMemcpyHostToDevice);
// cudaMemcpy(d_B, h_B, sizeof(float), cudaMemcpyHostToDevice);
// cudaMemcpy(d_C, h_C, sizeof(float), cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
float time;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
cudaProfilerStart();
// compute<<<num_blocks, num_threads_per_block>>>(d_A, d_B, d_C, d_res, iterations);
compute<<<num_blocks, num_threads_per_block>>>(d_res, iterations, divergence);
cudaProfilerStop();
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
std::cout << "GPU Elapsed Time = " << time << std::endl;
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaDeviceSynchronize();
cudaMemcpy(h_res, d_res, sizeof(float), cudaMemcpyDeviceToHost);
return 0;
} | .file "tmpxft_000a18d6_00000000-6_fma_32p_asm.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Usage ./binary <num_blocks> <num_threads_per_block> <iterations>threads active per warp"
.text
.globl _Z5usagev
.type _Z5usagev, @function
_Z5usagev:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl $87, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L8
cmpb $0, 56(%rbx)
je .L5
movzbl 67(%rbx), %esi
.L6:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L5:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L6
.cfi_endproc
.LFE3669:
.size _Z5usagev, .-_Z5usagev
.globl _Z28__device_stub__Z7computePfiiPfii
.type _Z28__device_stub__Z7computePfiiPfii, @function
_Z28__device_stub__Z7computePfiiPfii:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7computePfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z28__device_stub__Z7computePfiiPfii, .-_Z28__device_stub__Z7computePfiiPfii
.globl _Z7computePfii
.type _Z7computePfii, @function
_Z7computePfii:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7computePfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z7computePfii, .-_Z7computePfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "GPU Elapsed Time = "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
cmpl $5, %edi
jne .L22
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movq 32(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl $4, %esi
leaq d_res(%rip), %rdi
call cudaMalloc@PLT
movq %rsp, %rdi
call cudaEventCreate@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq (%rsp), %rdi
call cudaEventRecord@PLT
call cudaProfilerStart@PLT
movl %r12d, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %ebp, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
call cudaProfilerStop@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movq 8(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 28(%rsp), %rdi
movq 8(%rsp), %rdx
movq (%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 28(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq (%rsp), %rdi
call cudaEventDestroy@PLT
movq 8(%rsp), %rdi
call cudaEventDestroy@PLT
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $4, %edx
movq d_res(%rip), %rsi
movq h_res(%rip), %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call _Z5usagev
movl $1, %edi
call exit@PLT
.L23:
movl %ebx, %edx
movl %r13d, %esi
movq d_res(%rip), %rdi
call _Z28__device_stub__Z7computePfiiPfii
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z7computePfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computePfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl d_res
.bss
.align 8
.type d_res, @object
.size d_res, 8
d_res:
.zero 8
.globl d_C
.align 8
.type d_C, @object
.size d_C, 8
d_C:
.zero 8
.globl d_B
.align 8
.type d_B, @object
.size d_B, 8
d_B:
.zero 8
.globl d_A
.align 8
.type d_A, @object
.size d_A, 8
d_A:
.zero 8
.globl h_res
.align 8
.type h_res, @object
.size h_res, 8
h_res:
.zero 8
.globl h_C
.align 8
.type h_C, @object
.size h_C, 8
h_C:
.zero 8
.globl h_B
.align 8
.type h_B, @object
.size h_B, 8
h_B:
.zero 8
.globl h_A
.align 8
.type h_A, @object
.size h_A, 8
h_A:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <iostream>
#include <cuda_profiler_api.h>
//#include <cutil.h>
#include <cuda_runtime.h>
float* h_A;
float* h_B;
float* h_C;
float* h_res;
float* d_A;
float* d_B;
float* d_C;
float* d_res;
__global__
//void compute(const float* A, const float* B, const float* C, float* D, int n) {
void compute(float* D, int n, int div) {
int tid = blockDim.x * blockIdx.x + threadIdx.x;
float I1 = tid * 2.0;
int thread_id = threadIdx.x % 32;
if (thread_id < div) {
__asm volatile (
" .reg .f32 %r1111;\n\t"
" .reg .f32 %r1112;\n\t"
" .reg .f32 %r1113;\n\t"
" .reg .f32 %r1114;\n\t"
" .reg .f32 %r1115;\n\t"
" .reg .f32 %r1116;\n\t"
" .reg .f32 %r1117;\n\t"
" .reg .f32 %r1118;\n\t"
" .reg .f32 %r1119;\n\t"
" .reg .f32 %r1120;\n\t"
" .reg .f32 %r1121;\n\t"
" .reg .f32 %r1122;\n\t"
" .reg .f32 %r1123;\n\t"
" .reg .f32 %r1124;\n\t"
" .reg .f32 %r1125;\n\t"
" .reg .f32 %r1126;\n\t"
" .reg .f32 %r1127;\n\t"
" .reg .f32 %r1128;\n\t"
"mov.f32 %r1112, 4.4;\n\t"
"mov.f32 %r1113, %r1112;\n\t"
"mov.f32 %r1114, 2.2;\n\t"
"mov.f32 %r1115, 3.3;\n\t"
"mov.f32 %r1116, 1.23;\n\t"
"mov.f32 %r1117, 2.42;\n\t"
"mov.f32 %r1118, 3.34;\n\t"
"mov.f32 %r1119, 5.62;\n\t"
"mov.f32 %r1120, 2.56;\n\t"
"mov.f32 %r1121, 1.56;\n\t"
"mov.f32 %r1122, 2.56;\n\t"
"mov.f32 %r1123, 5.56;\n\t"
"mov.f32 %r1124, 8.56;\n\t"
"mov.f32 %r1125, 3.56;\n\t"
"mov.f32 %r1126, 5.56;\n\t"
"mov.f32 %r1127, 6.56;\n\t"
"mov.f32 %r1128, 0.56;\n\t"
);
for (int k = 0; k < n; k++) {
__asm volatile (
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
);
}
}
__syncthreads();
// if ((blockDim.x * blockIdx.x + threadIdx.x) == 0)
*D = I1;
__syncthreads();
}
void usage() {
std::cout << "Usage ./binary <num_blocks> <num_threads_per_block> <iterations>" "threads active per warp" << std::endl;
}
int main(int argc, char **argv)
{
if (argc != 5) {
usage();
exit(1);
}
int num_blocks = atoi(argv[1]);
int num_threads_per_block = atoi(argv[2]);
int iterations = atoi(argv[3]);
int divergence = atoi(argv[4]);
// h_A = new float(2.0);
// h_B = new float(3.0);
// h_C = new float(4.0);
// cudaMalloc((void**)&d_A, sizeof(float));
// cudaMalloc((void**)&d_B, sizeof(float));
// cudaMalloc((void**)&d_C, sizeof(float));
cudaMalloc((void**)&d_res, sizeof(float));
// cudaMemcpy(d_A, h_A, sizeof(float), cudaMemcpyHostToDevice);
// cudaMemcpy(d_B, h_B, sizeof(float), cudaMemcpyHostToDevice);
// cudaMemcpy(d_C, h_C, sizeof(float), cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
float time;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
cudaProfilerStart();
// compute<<<num_blocks, num_threads_per_block>>>(d_A, d_B, d_C, d_res, iterations);
compute<<<num_blocks, num_threads_per_block>>>(d_res, iterations, divergence);
cudaProfilerStop();
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time, start, stop);
std::cout << "GPU Elapsed Time = " << time << std::endl;
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaDeviceSynchronize();
cudaMemcpy(h_res, d_res, sizeof(float), cudaMemcpyDeviceToHost);
return 0;
} | #include <stdio.h>
#include <iostream>
#include <hip/hip_runtime_api.h>
//#include <cutil.h>
#include <hip/hip_runtime.h>
float* h_A;
float* h_B;
float* h_C;
float* h_res;
float* d_A;
float* d_B;
float* d_C;
float* d_res;
__global__
//void compute(const float* A, const float* B, const float* C, float* D, int n) {
void compute(float* D, int n, int div) {
int tid = blockDim.x * blockIdx.x + threadIdx.x;
float I1 = tid * 2.0;
int thread_id = threadIdx.x % 32;
if (thread_id < div) {
__asm volatile (
" .reg .f32 %r1111;\n\t"
" .reg .f32 %r1112;\n\t"
" .reg .f32 %r1113;\n\t"
" .reg .f32 %r1114;\n\t"
" .reg .f32 %r1115;\n\t"
" .reg .f32 %r1116;\n\t"
" .reg .f32 %r1117;\n\t"
" .reg .f32 %r1118;\n\t"
" .reg .f32 %r1119;\n\t"
" .reg .f32 %r1120;\n\t"
" .reg .f32 %r1121;\n\t"
" .reg .f32 %r1122;\n\t"
" .reg .f32 %r1123;\n\t"
" .reg .f32 %r1124;\n\t"
" .reg .f32 %r1125;\n\t"
" .reg .f32 %r1126;\n\t"
" .reg .f32 %r1127;\n\t"
" .reg .f32 %r1128;\n\t"
"mov.f32 %r1112, 4.4;\n\t"
"mov.f32 %r1113, %r1112;\n\t"
"mov.f32 %r1114, 2.2;\n\t"
"mov.f32 %r1115, 3.3;\n\t"
"mov.f32 %r1116, 1.23;\n\t"
"mov.f32 %r1117, 2.42;\n\t"
"mov.f32 %r1118, 3.34;\n\t"
"mov.f32 %r1119, 5.62;\n\t"
"mov.f32 %r1120, 2.56;\n\t"
"mov.f32 %r1121, 1.56;\n\t"
"mov.f32 %r1122, 2.56;\n\t"
"mov.f32 %r1123, 5.56;\n\t"
"mov.f32 %r1124, 8.56;\n\t"
"mov.f32 %r1125, 3.56;\n\t"
"mov.f32 %r1126, 5.56;\n\t"
"mov.f32 %r1127, 6.56;\n\t"
"mov.f32 %r1128, 0.56;\n\t"
);
for (int k = 0; k < n; k++) {
__asm volatile (
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
);
}
}
__syncthreads();
// if ((blockDim.x * blockIdx.x + threadIdx.x) == 0)
*D = I1;
__syncthreads();
}
void usage() {
std::cout << "Usage ./binary <num_blocks> <num_threads_per_block> <iterations>" "threads active per warp" << std::endl;
}
int main(int argc, char **argv)
{
if (argc != 5) {
usage();
exit(1);
}
int num_blocks = atoi(argv[1]);
int num_threads_per_block = atoi(argv[2]);
int iterations = atoi(argv[3]);
int divergence = atoi(argv[4]);
// h_A = new float(2.0);
// h_B = new float(3.0);
// h_C = new float(4.0);
// cudaMalloc((void**)&d_A, sizeof(float));
// cudaMalloc((void**)&d_B, sizeof(float));
// cudaMalloc((void**)&d_C, sizeof(float));
hipMalloc((void**)&d_res, sizeof(float));
// cudaMemcpy(d_A, h_A, sizeof(float), cudaMemcpyHostToDevice);
// cudaMemcpy(d_B, h_B, sizeof(float), cudaMemcpyHostToDevice);
// cudaMemcpy(d_C, h_C, sizeof(float), cudaMemcpyHostToDevice);
hipEvent_t start, stop;
float time;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
hipProfilerStart();
// compute<<<num_blocks, num_threads_per_block>>>(d_A, d_B, d_C, d_res, iterations);
compute<<<num_blocks, num_threads_per_block>>>(d_res, iterations, divergence);
hipProfilerStop();
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
std::cout << "GPU Elapsed Time = " << time << std::endl;
hipEventDestroy(start);
hipEventDestroy(stop);
hipDeviceSynchronize();
hipMemcpy(h_res, d_res, sizeof(float), hipMemcpyDeviceToHost);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <iostream>
#include <hip/hip_runtime_api.h>
//#include <cutil.h>
#include <hip/hip_runtime.h>
float* h_A;
float* h_B;
float* h_C;
float* h_res;
float* d_A;
float* d_B;
float* d_C;
float* d_res;
__global__
//void compute(const float* A, const float* B, const float* C, float* D, int n) {
void compute(float* D, int n, int div) {
int tid = blockDim.x * blockIdx.x + threadIdx.x;
float I1 = tid * 2.0;
int thread_id = threadIdx.x % 32;
if (thread_id < div) {
__asm volatile (
" .reg .f32 %r1111;\n\t"
" .reg .f32 %r1112;\n\t"
" .reg .f32 %r1113;\n\t"
" .reg .f32 %r1114;\n\t"
" .reg .f32 %r1115;\n\t"
" .reg .f32 %r1116;\n\t"
" .reg .f32 %r1117;\n\t"
" .reg .f32 %r1118;\n\t"
" .reg .f32 %r1119;\n\t"
" .reg .f32 %r1120;\n\t"
" .reg .f32 %r1121;\n\t"
" .reg .f32 %r1122;\n\t"
" .reg .f32 %r1123;\n\t"
" .reg .f32 %r1124;\n\t"
" .reg .f32 %r1125;\n\t"
" .reg .f32 %r1126;\n\t"
" .reg .f32 %r1127;\n\t"
" .reg .f32 %r1128;\n\t"
"mov.f32 %r1112, 4.4;\n\t"
"mov.f32 %r1113, %r1112;\n\t"
"mov.f32 %r1114, 2.2;\n\t"
"mov.f32 %r1115, 3.3;\n\t"
"mov.f32 %r1116, 1.23;\n\t"
"mov.f32 %r1117, 2.42;\n\t"
"mov.f32 %r1118, 3.34;\n\t"
"mov.f32 %r1119, 5.62;\n\t"
"mov.f32 %r1120, 2.56;\n\t"
"mov.f32 %r1121, 1.56;\n\t"
"mov.f32 %r1122, 2.56;\n\t"
"mov.f32 %r1123, 5.56;\n\t"
"mov.f32 %r1124, 8.56;\n\t"
"mov.f32 %r1125, 3.56;\n\t"
"mov.f32 %r1126, 5.56;\n\t"
"mov.f32 %r1127, 6.56;\n\t"
"mov.f32 %r1128, 0.56;\n\t"
);
for (int k = 0; k < n; k++) {
__asm volatile (
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
"fma.rn.f32 %r1113, %r1111, %r1113, %r1112;\n\t"
"fma.rn.f32 %r1114, %r1111, %r1114, %r1112;\n\t"
"fma.rn.f32 %r1115, %r1111, %r1115, %r1112;\n\t"
"fma.rn.f32 %r1116, %r1111, %r1116, %r1112;\n\t"
"fma.rn.f32 %r1117, %r1111, %r1117, %r1112;\n\t"
"fma.rn.f32 %r1118, %r1111, %r1118, %r1112;\n\t"
"fma.rn.f32 %r1119, %r1111, %r1119, %r1112;\n\t"
"fma.rn.f32 %r1120, %r1111, %r1120, %r1112;\n\t"
"fma.rn.f32 %r1121, %r1111, %r1121, %r1112;\n\t"
"fma.rn.f32 %r1122, %r1111, %r1122, %r1112;\n\t"
"fma.rn.f32 %r1123, %r1111, %r1123, %r1112;\n\t"
"fma.rn.f32 %r1124, %r1111, %r1124, %r1112;\n\t"
"fma.rn.f32 %r1125, %r1111, %r1125, %r1112;\n\t"
"fma.rn.f32 %r1126, %r1111, %r1126, %r1112;\n\t"
"fma.rn.f32 %r1127, %r1111, %r1127, %r1112;\n\t"
"fma.rn.f32 %r1128, %r1111, %r1128, %r1112;\n\t"
);
}
}
__syncthreads();
// if ((blockDim.x * blockIdx.x + threadIdx.x) == 0)
*D = I1;
__syncthreads();
}
void usage() {
std::cout << "Usage ./binary <num_blocks> <num_threads_per_block> <iterations>" "threads active per warp" << std::endl;
}
int main(int argc, char **argv)
{
if (argc != 5) {
usage();
exit(1);
}
int num_blocks = atoi(argv[1]);
int num_threads_per_block = atoi(argv[2]);
int iterations = atoi(argv[3]);
int divergence = atoi(argv[4]);
// h_A = new float(2.0);
// h_B = new float(3.0);
// h_C = new float(4.0);
// cudaMalloc((void**)&d_A, sizeof(float));
// cudaMalloc((void**)&d_B, sizeof(float));
// cudaMalloc((void**)&d_C, sizeof(float));
hipMalloc((void**)&d_res, sizeof(float));
// cudaMemcpy(d_A, h_A, sizeof(float), cudaMemcpyHostToDevice);
// cudaMemcpy(d_B, h_B, sizeof(float), cudaMemcpyHostToDevice);
// cudaMemcpy(d_C, h_C, sizeof(float), cudaMemcpyHostToDevice);
hipEvent_t start, stop;
float time;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
hipProfilerStart();
// compute<<<num_blocks, num_threads_per_block>>>(d_A, d_B, d_C, d_res, iterations);
compute<<<num_blocks, num_threads_per_block>>>(d_res, iterations, divergence);
hipProfilerStop();
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time, start, stop);
std::cout << "GPU Elapsed Time = " << time << std::endl;
hipEventDestroy(start);
hipEventDestroy(stop);
hipDeviceSynchronize();
hipMemcpy(h_res, d_res, sizeof(float), hipMemcpyDeviceToHost);
return 0;
} | .text
.file "fma_32p_asm.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__computePfii # -- Begin function _Z22__device_stub__computePfii
.p2align 4, 0x90
.type _Z22__device_stub__computePfii,@function
_Z22__device_stub__computePfii: # @_Z22__device_stub__computePfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7computePfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__computePfii, .Lfunc_end0-_Z22__device_stub__computePfii
.cfi_endproc
# -- End function
.globl _Z5usagev # -- Begin function _Z5usagev
.p2align 4, 0x90
.type _Z5usagev,@function
_Z5usagev: # @_Z5usagev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $87, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_5
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB1_5:
.cfi_def_cfa_offset 16
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z5usagev, .Lfunc_end1-_Z5usagev
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
cmpl $5, %edi
jne .LBB2_8
# %bb.1:
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movq 24(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 32(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movl $d_res, %edi
movl $4, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
callq hipProfilerStart
movl %r15d, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %r12d, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_3
# %bb.2:
movq d_res(%rip), %rax
movq %rax, 112(%rsp)
movl %ebx, 28(%rsp)
movl %r14d, 24(%rsp)
leaq 112(%rsp), %rax
movq %rax, 32(%rsp)
leaq 28(%rsp), %rax
movq %rax, 40(%rsp)
leaq 24(%rsp), %rax
movq %rax, 48(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z7computePfii, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_3:
callq hipProfilerStop
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_9
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB2_6
# %bb.5:
movzbl 67(%rbx), %ecx
jmp .LBB2_7
.LBB2_6:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_7: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
callq hipDeviceSynchronize
movq h_res(%rip), %rdi
movq d_res(%rip), %rsi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_8:
.cfi_def_cfa_offset 160
callq _Z5usagev
movl $1, %edi
callq exit
.LBB2_9:
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computePfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type h_A,@object # @h_A
.bss
.globl h_A
.p2align 3, 0x0
h_A:
.quad 0
.size h_A, 8
.type h_B,@object # @h_B
.globl h_B
.p2align 3, 0x0
h_B:
.quad 0
.size h_B, 8
.type h_C,@object # @h_C
.globl h_C
.p2align 3, 0x0
h_C:
.quad 0
.size h_C, 8
.type h_res,@object # @h_res
.globl h_res
.p2align 3, 0x0
h_res:
.quad 0
.size h_res, 8
.type d_A,@object # @d_A
.globl d_A
.p2align 3, 0x0
d_A:
.quad 0
.size d_A, 8
.type d_B,@object # @d_B
.globl d_B
.p2align 3, 0x0
d_B:
.quad 0
.size d_B, 8
.type d_C,@object # @d_C
.globl d_C
.p2align 3, 0x0
d_C:
.quad 0
.size d_C, 8
.type d_res,@object # @d_res
.globl d_res
.p2align 3, 0x0
d_res:
.quad 0
.size d_res, 8
.type _Z7computePfii,@object # @_Z7computePfii
.section .rodata,"a",@progbits
.globl _Z7computePfii
.p2align 3, 0x0
_Z7computePfii:
.quad _Z22__device_stub__computePfii
.size _Z7computePfii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Usage ./binary <num_blocks> <num_threads_per_block> <iterations>threads active per warp"
.size .L.str, 88
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU Elapsed Time = "
.size .L.str.1, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7computePfii"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computePfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_res
.addrsig_sym _Z7computePfii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7computePfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0060*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0070*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0080*/ I2F.F64 R2, R0 ; /* 0x0000000000027312 */
/* 0x000e240000201c00 */
/*0090*/ DADD R2, R2, R2 ; /* 0x0000000002027229 */
/* 0x001e140000000002 */
/*00a0*/ F2F.F32.F64 R3, R2 ; /* 0x0000000200037310 */
/* 0x001e240000301000 */
/*00b0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x001fe8000c101904 */
/*00c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7computePfii
.globl _Z7computePfii
.p2align 8
.type _Z7computePfii,@function
_Z7computePfii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0xc
s_load_b32 s2, s[0:1], 0x1c
v_and_b32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b32 s4, s[0:1], 0x8
.reg .f32 %r1111
.reg .f32 %r1112
.reg .f32 %r1113
.reg .f32 %r1114
.reg .f32 %r1115
.reg .f32 %r1116
.reg .f32 %r1117
.reg .f32 %r1118
.reg .f32 %r1119
.reg .f32 %r1120
.reg .f32 %r1121
.reg .f32 %r1122
.reg .f32 %r1123
.reg .f32 %r1124
.reg .f32 %r1125
.reg .f32 %r1126
.reg .f32 %r1127
.reg .f32 %r1128
mov.f32 %r1112, 4.4
mov.f32 %r1113, %r1112
mov.f32 %r1114, 2.2
mov.f32 %r1115, 3.3
mov.f32 %r1116, 1.23
mov.f32 %r1117, 2.42
mov.f32 %r1118, 3.34
mov.f32 %r1119, 5.62
mov.f32 %r1120, 2.56
mov.f32 %r1121, 1.56
mov.f32 %r1122, 2.56
mov.f32 %r1123, 5.56
mov.f32 %r1124, 8.56
mov.f32 %r1125, 3.56
mov.f32 %r1126, 5.56
mov.f32 %r1127, 6.56
mov.f32 %r1128, 0.56
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
.LBB0_2:
s_add_i32 s4, s4, -1
fma.rn.f32 %r1113, %r1111, %r1113, %r1112
fma.rn.f32 %r1114, %r1111, %r1114, %r1112
fma.rn.f32 %r1115, %r1111, %r1115, %r1112
fma.rn.f32 %r1116, %r1111, %r1116, %r1112
fma.rn.f32 %r1117, %r1111, %r1117, %r1112
fma.rn.f32 %r1118, %r1111, %r1118, %r1112
fma.rn.f32 %r1119, %r1111, %r1119, %r1112
fma.rn.f32 %r1120, %r1111, %r1120, %r1112
fma.rn.f32 %r1121, %r1111, %r1121, %r1112
fma.rn.f32 %r1122, %r1111, %r1122, %r1112
fma.rn.f32 %r1123, %r1111, %r1123, %r1112
fma.rn.f32 %r1124, %r1111, %r1124, %r1112
fma.rn.f32 %r1125, %r1111, %r1125, %r1112
fma.rn.f32 %r1126, %r1111, %r1126, %r1112
fma.rn.f32 %r1127, %r1111, %r1127, %r1112
fma.rn.f32 %r1128, %r1111, %r1128, %r1112
fma.rn.f32 %r1113, %r1111, %r1113, %r1112
fma.rn.f32 %r1114, %r1111, %r1114, %r1112
fma.rn.f32 %r1115, %r1111, %r1115, %r1112
fma.rn.f32 %r1116, %r1111, %r1116, %r1112
fma.rn.f32 %r1117, %r1111, %r1117, %r1112
fma.rn.f32 %r1118, %r1111, %r1118, %r1112
fma.rn.f32 %r1119, %r1111, %r1119, %r1112
fma.rn.f32 %r1120, %r1111, %r1120, %r1112
fma.rn.f32 %r1121, %r1111, %r1121, %r1112
fma.rn.f32 %r1122, %r1111, %r1122, %r1112
fma.rn.f32 %r1123, %r1111, %r1123, %r1112
fma.rn.f32 %r1124, %r1111, %r1124, %r1112
fma.rn.f32 %r1125, %r1111, %r1125, %r1112
fma.rn.f32 %r1126, %r1111, %r1126, %r1112
fma.rn.f32 %r1127, %r1111, %r1127, %r1112
fma.rn.f32 %r1128, %r1111, %r1128, %r1112
fma.rn.f32 %r1113, %r1111, %r1113, %r1112
fma.rn.f32 %r1114, %r1111, %r1114, %r1112
fma.rn.f32 %r1115, %r1111, %r1115, %r1112
fma.rn.f32 %r1116, %r1111, %r1116, %r1112
fma.rn.f32 %r1117, %r1111, %r1117, %r1112
fma.rn.f32 %r1118, %r1111, %r1118, %r1112
fma.rn.f32 %r1119, %r1111, %r1119, %r1112
fma.rn.f32 %r1120, %r1111, %r1120, %r1112
fma.rn.f32 %r1121, %r1111, %r1121, %r1112
fma.rn.f32 %r1122, %r1111, %r1122, %r1112
fma.rn.f32 %r1123, %r1111, %r1123, %r1112
fma.rn.f32 %r1124, %r1111, %r1124, %r1112
fma.rn.f32 %r1125, %r1111, %r1125, %r1112
fma.rn.f32 %r1126, %r1111, %r1126, %r1112
fma.rn.f32 %r1127, %r1111, %r1127, %r1112
fma.rn.f32 %r1128, %r1111, %r1128, %r1112
fma.rn.f32 %r1113, %r1111, %r1113, %r1112
fma.rn.f32 %r1114, %r1111, %r1114, %r1112
fma.rn.f32 %r1115, %r1111, %r1115, %r1112
fma.rn.f32 %r1116, %r1111, %r1116, %r1112
fma.rn.f32 %r1117, %r1111, %r1117, %r1112
fma.rn.f32 %r1118, %r1111, %r1118, %r1112
fma.rn.f32 %r1119, %r1111, %r1119, %r1112
fma.rn.f32 %r1120, %r1111, %r1120, %r1112
fma.rn.f32 %r1121, %r1111, %r1121, %r1112
fma.rn.f32 %r1122, %r1111, %r1122, %r1112
fma.rn.f32 %r1123, %r1111, %r1123, %r1112
fma.rn.f32 %r1124, %r1111, %r1124, %r1112
fma.rn.f32 %r1125, %r1111, %r1125, %r1112
fma.rn.f32 %r1126, %r1111, %r1126, %r1112
fma.rn.f32 %r1127, %r1111, %r1127, %r1112
fma.rn.f32 %r1128, %r1111, %r1128, %r1112
fma.rn.f32 %r1113, %r1111, %r1113, %r1112
fma.rn.f32 %r1114, %r1111, %r1114, %r1112
fma.rn.f32 %r1115, %r1111, %r1115, %r1112
fma.rn.f32 %r1116, %r1111, %r1116, %r1112
fma.rn.f32 %r1117, %r1111, %r1117, %r1112
fma.rn.f32 %r1118, %r1111, %r1118, %r1112
fma.rn.f32 %r1119, %r1111, %r1119, %r1112
fma.rn.f32 %r1120, %r1111, %r1120, %r1112
fma.rn.f32 %r1121, %r1111, %r1121, %r1112
fma.rn.f32 %r1122, %r1111, %r1122, %r1112
fma.rn.f32 %r1123, %r1111, %r1123, %r1112
fma.rn.f32 %r1124, %r1111, %r1124, %r1112
fma.rn.f32 %r1125, %r1111, %r1125, %r1112
fma.rn.f32 %r1126, %r1111, %r1126, %r1112
fma.rn.f32 %r1127, %r1111, %r1127, %r1112
fma.rn.f32 %r1128, %r1111, %r1128, %r1112
fma.rn.f32 %r1113, %r1111, %r1113, %r1112
fma.rn.f32 %r1114, %r1111, %r1114, %r1112
fma.rn.f32 %r1115, %r1111, %r1115, %r1112
fma.rn.f32 %r1116, %r1111, %r1116, %r1112
fma.rn.f32 %r1117, %r1111, %r1117, %r1112
fma.rn.f32 %r1118, %r1111, %r1118, %r1112
fma.rn.f32 %r1119, %r1111, %r1119, %r1112
fma.rn.f32 %r1120, %r1111, %r1120, %r1112
fma.rn.f32 %r1121, %r1111, %r1121, %r1112
fma.rn.f32 %r1122, %r1111, %r1122, %r1112
fma.rn.f32 %r1123, %r1111, %r1123, %r1112
fma.rn.f32 %r1124, %r1111, %r1124, %r1112
fma.rn.f32 %r1125, %r1111, %r1125, %r1112
fma.rn.f32 %r1126, %r1111, %r1126, %r1112
fma.rn.f32 %r1127, %r1111, %r1127, %r1112
fma.rn.f32 %r1128, %r1111, %r1128, %r1112
fma.rn.f32 %r1113, %r1111, %r1113, %r1112
fma.rn.f32 %r1114, %r1111, %r1114, %r1112
fma.rn.f32 %r1115, %r1111, %r1115, %r1112
fma.rn.f32 %r1116, %r1111, %r1116, %r1112
fma.rn.f32 %r1117, %r1111, %r1117, %r1112
fma.rn.f32 %r1118, %r1111, %r1118, %r1112
fma.rn.f32 %r1119, %r1111, %r1119, %r1112
fma.rn.f32 %r1120, %r1111, %r1120, %r1112
fma.rn.f32 %r1121, %r1111, %r1121, %r1112
fma.rn.f32 %r1122, %r1111, %r1122, %r1112
fma.rn.f32 %r1123, %r1111, %r1123, %r1112
fma.rn.f32 %r1124, %r1111, %r1124, %r1112
fma.rn.f32 %r1125, %r1111, %r1125, %r1112
fma.rn.f32 %r1126, %r1111, %r1126, %r1112
fma.rn.f32 %r1127, %r1111, %r1127, %r1112
fma.rn.f32 %r1128, %r1111, %r1128, %r1112
fma.rn.f32 %r1113, %r1111, %r1113, %r1112
fma.rn.f32 %r1114, %r1111, %r1114, %r1112
fma.rn.f32 %r1115, %r1111, %r1115, %r1112
fma.rn.f32 %r1116, %r1111, %r1116, %r1112
fma.rn.f32 %r1117, %r1111, %r1117, %r1112
fma.rn.f32 %r1118, %r1111, %r1118, %r1112
fma.rn.f32 %r1119, %r1111, %r1119, %r1112
fma.rn.f32 %r1120, %r1111, %r1120, %r1112
fma.rn.f32 %r1121, %r1111, %r1121, %r1112
fma.rn.f32 %r1122, %r1111, %r1122, %r1112
fma.rn.f32 %r1123, %r1111, %r1123, %r1112
fma.rn.f32 %r1124, %r1111, %r1124, %r1112
fma.rn.f32 %r1125, %r1111, %r1125, %r1112
fma.rn.f32 %r1126, %r1111, %r1126, %r1112
fma.rn.f32 %r1127, %r1111, %r1127, %r1112
fma.rn.f32 %r1128, %r1111, %r1128, %r1112
fma.rn.f32 %r1113, %r1111, %r1113, %r1112
fma.rn.f32 %r1114, %r1111, %r1114, %r1112
fma.rn.f32 %r1115, %r1111, %r1115, %r1112
fma.rn.f32 %r1116, %r1111, %r1116, %r1112
fma.rn.f32 %r1117, %r1111, %r1117, %r1112
fma.rn.f32 %r1118, %r1111, %r1118, %r1112
fma.rn.f32 %r1119, %r1111, %r1119, %r1112
fma.rn.f32 %r1120, %r1111, %r1120, %r1112
fma.rn.f32 %r1121, %r1111, %r1121, %r1112
fma.rn.f32 %r1122, %r1111, %r1122, %r1112
fma.rn.f32 %r1123, %r1111, %r1123, %r1112
fma.rn.f32 %r1124, %r1111, %r1124, %r1112
fma.rn.f32 %r1125, %r1111, %r1125, %r1112
fma.rn.f32 %r1126, %r1111, %r1126, %r1112
fma.rn.f32 %r1127, %r1111, %r1127, %r1112
fma.rn.f32 %r1128, %r1111, %r1128, %r1112
fma.rn.f32 %r1113, %r1111, %r1113, %r1112
fma.rn.f32 %r1114, %r1111, %r1114, %r1112
fma.rn.f32 %r1115, %r1111, %r1115, %r1112
fma.rn.f32 %r1116, %r1111, %r1116, %r1112
fma.rn.f32 %r1117, %r1111, %r1117, %r1112
fma.rn.f32 %r1118, %r1111, %r1118, %r1112
fma.rn.f32 %r1119, %r1111, %r1119, %r1112
fma.rn.f32 %r1120, %r1111, %r1120, %r1112
fma.rn.f32 %r1121, %r1111, %r1121, %r1112
fma.rn.f32 %r1122, %r1111, %r1122, %r1112
fma.rn.f32 %r1123, %r1111, %r1123, %r1112
fma.rn.f32 %r1124, %r1111, %r1124, %r1112
fma.rn.f32 %r1125, %r1111, %r1125, %r1112
fma.rn.f32 %r1126, %r1111, %r1126, %r1112
fma.rn.f32 %r1127, %r1111, %r1127, %r1112
fma.rn.f32 %r1128, %r1111, %r1128, %r1112
fma.rn.f32 %r1113, %r1111, %r1113, %r1112
fma.rn.f32 %r1114, %r1111, %r1114, %r1112
fma.rn.f32 %r1115, %r1111, %r1115, %r1112
fma.rn.f32 %r1116, %r1111, %r1116, %r1112
fma.rn.f32 %r1117, %r1111, %r1117, %r1112
fma.rn.f32 %r1118, %r1111, %r1118, %r1112
fma.rn.f32 %r1119, %r1111, %r1119, %r1112
fma.rn.f32 %r1120, %r1111, %r1120, %r1112
fma.rn.f32 %r1121, %r1111, %r1121, %r1112
fma.rn.f32 %r1122, %r1111, %r1122, %r1112
fma.rn.f32 %r1123, %r1111, %r1123, %r1112
fma.rn.f32 %r1124, %r1111, %r1124, %r1112
fma.rn.f32 %r1125, %r1111, %r1125, %r1112
fma.rn.f32 %r1126, %r1111, %r1126, %r1112
fma.rn.f32 %r1127, %r1111, %r1127, %r1112
fma.rn.f32 %r1128, %r1111, %r1128, %r1112
fma.rn.f32 %r1113, %r1111, %r1113, %r1112
fma.rn.f32 %r1114, %r1111, %r1114, %r1112
fma.rn.f32 %r1115, %r1111, %r1115, %r1112
fma.rn.f32 %r1116, %r1111, %r1116, %r1112
fma.rn.f32 %r1117, %r1111, %r1117, %r1112
fma.rn.f32 %r1118, %r1111, %r1118, %r1112
fma.rn.f32 %r1119, %r1111, %r1119, %r1112
fma.rn.f32 %r1120, %r1111, %r1120, %r1112
fma.rn.f32 %r1121, %r1111, %r1121, %r1112
fma.rn.f32 %r1122, %r1111, %r1122, %r1112
fma.rn.f32 %r1123, %r1111, %r1123, %r1112
fma.rn.f32 %r1124, %r1111, %r1124, %r1112
fma.rn.f32 %r1125, %r1111, %r1125, %r1112
fma.rn.f32 %r1126, %r1111, %r1126, %r1112
fma.rn.f32 %r1127, %r1111, %r1127, %r1112
fma.rn.f32 %r1128, %r1111, %r1128, %r1112
fma.rn.f32 %r1113, %r1111, %r1113, %r1112
fma.rn.f32 %r1114, %r1111, %r1114, %r1112
fma.rn.f32 %r1115, %r1111, %r1115, %r1112
fma.rn.f32 %r1116, %r1111, %r1116, %r1112
fma.rn.f32 %r1117, %r1111, %r1117, %r1112
fma.rn.f32 %r1118, %r1111, %r1118, %r1112
fma.rn.f32 %r1119, %r1111, %r1119, %r1112
fma.rn.f32 %r1120, %r1111, %r1120, %r1112
fma.rn.f32 %r1121, %r1111, %r1121, %r1112
fma.rn.f32 %r1122, %r1111, %r1122, %r1112
fma.rn.f32 %r1123, %r1111, %r1123, %r1112
fma.rn.f32 %r1124, %r1111, %r1124, %r1112
fma.rn.f32 %r1125, %r1111, %r1125, %r1112
fma.rn.f32 %r1126, %r1111, %r1126, %r1112
fma.rn.f32 %r1127, %r1111, %r1127, %r1112
fma.rn.f32 %r1128, %r1111, %r1128, %r1112
fma.rn.f32 %r1113, %r1111, %r1113, %r1112
fma.rn.f32 %r1114, %r1111, %r1114, %r1112
fma.rn.f32 %r1115, %r1111, %r1115, %r1112
fma.rn.f32 %r1116, %r1111, %r1116, %r1112
fma.rn.f32 %r1117, %r1111, %r1117, %r1112
fma.rn.f32 %r1118, %r1111, %r1118, %r1112
fma.rn.f32 %r1119, %r1111, %r1119, %r1112
fma.rn.f32 %r1120, %r1111, %r1120, %r1112
fma.rn.f32 %r1121, %r1111, %r1121, %r1112
fma.rn.f32 %r1122, %r1111, %r1122, %r1112
fma.rn.f32 %r1123, %r1111, %r1123, %r1112
fma.rn.f32 %r1124, %r1111, %r1124, %r1112
fma.rn.f32 %r1125, %r1111, %r1125, %r1112
fma.rn.f32 %r1126, %r1111, %r1126, %r1112
fma.rn.f32 %r1127, %r1111, %r1127, %r1112
fma.rn.f32 %r1128, %r1111, %r1128, %r1112
fma.rn.f32 %r1113, %r1111, %r1113, %r1112
fma.rn.f32 %r1114, %r1111, %r1114, %r1112
fma.rn.f32 %r1115, %r1111, %r1115, %r1112
fma.rn.f32 %r1116, %r1111, %r1116, %r1112
fma.rn.f32 %r1117, %r1111, %r1117, %r1112
fma.rn.f32 %r1118, %r1111, %r1118, %r1112
fma.rn.f32 %r1119, %r1111, %r1119, %r1112
fma.rn.f32 %r1120, %r1111, %r1120, %r1112
fma.rn.f32 %r1121, %r1111, %r1121, %r1112
fma.rn.f32 %r1122, %r1111, %r1122, %r1112
fma.rn.f32 %r1123, %r1111, %r1123, %r1112
fma.rn.f32 %r1124, %r1111, %r1124, %r1112
fma.rn.f32 %r1125, %r1111, %r1125, %r1112
fma.rn.f32 %r1126, %r1111, %r1126, %r1112
fma.rn.f32 %r1127, %r1111, %r1127, %r1112
fma.rn.f32 %r1128, %r1111, %r1128, %r1112
fma.rn.f32 %r1113, %r1111, %r1113, %r1112
fma.rn.f32 %r1114, %r1111, %r1114, %r1112
fma.rn.f32 %r1115, %r1111, %r1115, %r1112
fma.rn.f32 %r1116, %r1111, %r1116, %r1112
fma.rn.f32 %r1117, %r1111, %r1117, %r1112
fma.rn.f32 %r1118, %r1111, %r1118, %r1112
fma.rn.f32 %r1119, %r1111, %r1119, %r1112
fma.rn.f32 %r1120, %r1111, %r1120, %r1112
fma.rn.f32 %r1121, %r1111, %r1121, %r1112
fma.rn.f32 %r1122, %r1111, %r1122, %r1112
fma.rn.f32 %r1123, %r1111, %r1123, %r1112
fma.rn.f32 %r1124, %r1111, %r1124, %r1112
fma.rn.f32 %r1125, %r1111, %r1125, %r1112
fma.rn.f32 %r1126, %r1111, %r1126, %r1112
fma.rn.f32 %r1127, %r1111, %r1127, %r1112
fma.rn.f32 %r1128, %r1111, %r1128, %r1112
s_cmp_lg_u32 s4, 0
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s3
s_and_b32 s2, 0xffff, s2
s_load_b64 s[0:1], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cvt_f64_i32_e32 v[0:1], v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[0:1], v[0:1], v[0:1]
v_cvt_f32_f64_e32 v0, v[0:1]
v_mov_b32_e32 v1, 0
global_store_b32 v1, v0, s[0:1]
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7computePfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7computePfii, .Lfunc_end0-_Z7computePfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7computePfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7computePfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a18d6_00000000-6_fma_32p_asm.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Usage ./binary <num_blocks> <num_threads_per_block> <iterations>threads active per warp"
.text
.globl _Z5usagev
.type _Z5usagev, @function
_Z5usagev:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl $87, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L8
cmpb $0, 56(%rbx)
je .L5
movzbl 67(%rbx), %esi
.L6:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L5:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L6
.cfi_endproc
.LFE3669:
.size _Z5usagev, .-_Z5usagev
.globl _Z28__device_stub__Z7computePfiiPfii
.type _Z28__device_stub__Z7computePfiiPfii, @function
_Z28__device_stub__Z7computePfiiPfii:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7computePfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z28__device_stub__Z7computePfiiPfii, .-_Z28__device_stub__Z7computePfiiPfii
.globl _Z7computePfii
.type _Z7computePfii, @function
_Z7computePfii:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7computePfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z7computePfii, .-_Z7computePfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "GPU Elapsed Time = "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
cmpl $5, %edi
jne .L22
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movq 32(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl $4, %esi
leaq d_res(%rip), %rdi
call cudaMalloc@PLT
movq %rsp, %rdi
call cudaEventCreate@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq (%rsp), %rdi
call cudaEventRecord@PLT
call cudaProfilerStart@PLT
movl %r12d, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %ebp, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
call cudaProfilerStop@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movq 8(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 28(%rsp), %rdi
movq 8(%rsp), %rdx
movq (%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 28(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq (%rsp), %rdi
call cudaEventDestroy@PLT
movq 8(%rsp), %rdi
call cudaEventDestroy@PLT
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $4, %edx
movq d_res(%rip), %rsi
movq h_res(%rip), %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
call _Z5usagev
movl $1, %edi
call exit@PLT
.L23:
movl %ebx, %edx
movl %r13d, %esi
movq d_res(%rip), %rdi
call _Z28__device_stub__Z7computePfiiPfii
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z7computePfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computePfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl d_res
.bss
.align 8
.type d_res, @object
.size d_res, 8
d_res:
.zero 8
.globl d_C
.align 8
.type d_C, @object
.size d_C, 8
d_C:
.zero 8
.globl d_B
.align 8
.type d_B, @object
.size d_B, 8
d_B:
.zero 8
.globl d_A
.align 8
.type d_A, @object
.size d_A, 8
d_A:
.zero 8
.globl h_res
.align 8
.type h_res, @object
.size h_res, 8
h_res:
.zero 8
.globl h_C
.align 8
.type h_C, @object
.size h_C, 8
h_C:
.zero 8
.globl h_B
.align 8
.type h_B, @object
.size h_B, 8
h_B:
.zero 8
.globl h_A
.align 8
.type h_A, @object
.size h_A, 8
h_A:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "fma_32p_asm.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__computePfii # -- Begin function _Z22__device_stub__computePfii
.p2align 4, 0x90
.type _Z22__device_stub__computePfii,@function
_Z22__device_stub__computePfii: # @_Z22__device_stub__computePfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7computePfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__computePfii, .Lfunc_end0-_Z22__device_stub__computePfii
.cfi_endproc
# -- End function
.globl _Z5usagev # -- Begin function _Z5usagev
.p2align 4, 0x90
.type _Z5usagev,@function
_Z5usagev: # @_Z5usagev
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $87, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_5
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB1_5:
.cfi_def_cfa_offset 16
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z5usagev, .Lfunc_end1-_Z5usagev
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
cmpl $5, %edi
jne .LBB2_8
# %bb.1:
movq %rsi, %r14
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 16(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movq 24(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 32(%r14), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movl $d_res, %edi
movl $4, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
callq hipProfilerStart
movl %r15d, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %r12d, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_3
# %bb.2:
movq d_res(%rip), %rax
movq %rax, 112(%rsp)
movl %ebx, 28(%rsp)
movl %r14d, 24(%rsp)
leaq 112(%rsp), %rax
movq %rax, 32(%rsp)
leaq 28(%rsp), %rax
movq %rax, 40(%rsp)
leaq 24(%rsp), %rax
movq %rax, 48(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z7computePfii, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_3:
callq hipProfilerStop
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_9
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB2_6
# %bb.5:
movzbl 67(%rbx), %ecx
jmp .LBB2_7
.LBB2_6:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_7: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
callq hipDeviceSynchronize
movq h_res(%rip), %rdi
movq d_res(%rip), %rsi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_8:
.cfi_def_cfa_offset 160
callq _Z5usagev
movl $1, %edi
callq exit
.LBB2_9:
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computePfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type h_A,@object # @h_A
.bss
.globl h_A
.p2align 3, 0x0
h_A:
.quad 0
.size h_A, 8
.type h_B,@object # @h_B
.globl h_B
.p2align 3, 0x0
h_B:
.quad 0
.size h_B, 8
.type h_C,@object # @h_C
.globl h_C
.p2align 3, 0x0
h_C:
.quad 0
.size h_C, 8
.type h_res,@object # @h_res
.globl h_res
.p2align 3, 0x0
h_res:
.quad 0
.size h_res, 8
.type d_A,@object # @d_A
.globl d_A
.p2align 3, 0x0
d_A:
.quad 0
.size d_A, 8
.type d_B,@object # @d_B
.globl d_B
.p2align 3, 0x0
d_B:
.quad 0
.size d_B, 8
.type d_C,@object # @d_C
.globl d_C
.p2align 3, 0x0
d_C:
.quad 0
.size d_C, 8
.type d_res,@object # @d_res
.globl d_res
.p2align 3, 0x0
d_res:
.quad 0
.size d_res, 8
.type _Z7computePfii,@object # @_Z7computePfii
.section .rodata,"a",@progbits
.globl _Z7computePfii
.p2align 3, 0x0
_Z7computePfii:
.quad _Z22__device_stub__computePfii
.size _Z7computePfii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Usage ./binary <num_blocks> <num_threads_per_block> <iterations>threads active per warp"
.size .L.str, 88
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "GPU Elapsed Time = "
.size .L.str.1, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7computePfii"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computePfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_res
.addrsig_sym _Z7computePfii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "subroutines.cuh"
//-----------------------------------------------------------------------//
//* Some common small functions and constants *//
//-----------------------------------------------------------------------//
const int constSharedMemSize = 256;
const int maxThreads = 256; // number of threads per block
#define imin(a,b) (a<b?a:b)
bool isPow2(unsigned int x) {
return ((x&(x - 1)) == 0);
}
unsigned int nextPow2(unsigned int x) {
--x;
x |= x >> 1;
x |= x >> 2;
x |= x >> 4;
x |= x >> 8;
x |= x >> 16;
return ++x;
}
__global__ void add_two_values_in_gpu(double *d_input, double *d_res)
{
int tid = threadIdx.x;
if (tid == 0)
d_res[0] = d_input[0] + d_res[1];
}
__global__ void access_value_in_gpu(double *d_input, double *d_res, int index)
{
int tid = threadIdx.x;
if (tid == 0)
d_res[0] = d_input[index];
}
//-----------------------------------------------------------------------//
//* Reduce from cuda book *//
//-----------------------------------------------------------------------//
__global__ void kernel_sum(double *d_data, double *d_result, int data_size)
{
__shared__ double s_data[constSharedMemSize];
long index = threadIdx.x + blockIdx.x * blockDim.x;
int id = threadIdx.x;
s_data[id] = 0.0;
if (index < data_size)
s_data[id] = d_data[index];
__syncthreads();
int step = constSharedMemSize / 2;
while (step != 0) {
if (id < step)
s_data[id] += s_data[id + step];
__syncthreads();
step /= 2;
}
if (id == 0)
d_result[blockIdx.x] = s_data[0];
}
double sum_gpu(double *d_data, int data_size){
int threadsPerBlock = constSharedMemSize;
int numBlocks = imin(65536, (data_size + constSharedMemSize - 1) / constSharedMemSize);
double *h_result;
double *d_result;
h_result = (double*)malloc(numBlocks*sizeof(double));
cudaMalloc((void**)&d_result, numBlocks*sizeof(double));
kernel_sum << <numBlocks, threadsPerBlock >> >(d_data, d_result, data_size);
cudaMemcpy(h_result, d_result, numBlocks*sizeof(double), cudaMemcpyDeviceToHost);
double sum = 0.0;
for (int j = 0; j < numBlocks; j++){
sum += h_result[j];
}
free(h_result);
cudaFree(d_result);
return sum;
}
//----------------------------------------------------------------------------//
//* Three kernels of reduce algorithms using threads matching the data size *//
//----------------------------------------------------------------------------//
__global__ void kernel_reduce_score10(double *d_input, double *d_res, int size)
{
__shared__ double s_data[constSharedMemSize];
long index = threadIdx.x + blockIdx.x*blockDim.x;
int tid = threadIdx.x;
s_data[tid] = 0.0;
if (index < size)
s_data[tid] = d_input[index];
__syncthreads();
for (int s = 2; s <= blockDim.x; s = s * 2)
{
if ((tid % s) == 0)
s_data[tid] += s_data[tid + s / 2];
__syncthreads();
}
if (tid == 0){
d_res[blockIdx.x] = s_data[0];
}
}
// replace % operator, avoid highly divergent wraps and slow operators
__global__ void kernel_reduce_score20(double *d_input, double *d_res, int size)
{
__shared__ double s_data[constSharedMemSize];
long index = threadIdx.x + blockIdx.x*blockDim.x;
int tid = threadIdx.x;
s_data[tid] = 0.0;
if (index < size)
s_data[tid] = d_input[index];
__syncthreads();
for (int s = 2; s <= blockDim.x; s = s * 2){
index = tid * s;
if (index < blockDim.x)
s_data[index] += s_data[index + s / 2];
__syncthreads();
}
if (tid == 0)
d_res[blockIdx.x] = s_data[0];
}
// deal with shared memory bank conflicts
__global__ void kernel_reduce_score30(double *d_input, double *d_res, int size)
{
__shared__ double s_data[constSharedMemSize];
long index = threadIdx.x + blockIdx.x*blockDim.x;
int tid = threadIdx.x;
s_data[tid] = 0.0;
if (index < size)
s_data[tid] = d_input[index];
__syncthreads();
for (int s = blockDim.x / 2; s >= 1; s = s >> 1){
if (tid < s)
s_data[tid] += s_data[tid + s];
__syncthreads();
}
if (tid == 0)
d_res[blockIdx.x] = s_data[tid];
}
double sum_gpu_reduce_full(void(*kernel)(double*, double*, int), double *d_input, int size, int flag)
{
//int threadsPerBlock = constSharedMemSize;
//int numBlocks = imin(65536, (size + constSharedMemSize - 1) / constSharedMemSize);
int threadsPerBlock = constSharedMemSize;
int numBlocks = imin(65536, (nextPow2(size - 1) + constSharedMemSize - 1) / constSharedMemSize);
double *d_result;
cudaMalloc((void**)&d_result, numBlocks * sizeof(double));
kernel << <numBlocks, threadsPerBlock >> >(d_input, d_result, size);
cudaDeviceSynchronize();
if (numBlocks == 1){
double h_result;
cudaMemcpy(&h_result, d_result, sizeof(double), cudaMemcpyDeviceToHost);
if (flag)
cudaFree(d_result);
return h_result;
}
return sum_gpu_reduce_full(kernel, d_result, numBlocks, 1);
}
//----------------------------------------------------------------------------//
//* Three kernels of reduce algorithms using half threads of data size *//
//----------------------------------------------------------------------------//
__device__ void warpReduce(volatile double* s_data, int tid) {
s_data[tid] += s_data[tid + 32];
s_data[tid] += s_data[tid + 16];
s_data[tid] += s_data[tid + 8];
s_data[tid] += s_data[tid + 4];
s_data[tid] += s_data[tid + 2];
s_data[tid] += s_data[tid + 1];
}
// deal with the first loop of idea threads
__global__ void kernel_reduce_half_score40(double *d_input, double *d_res, int size)
{
__shared__ double s_data[constSharedMemSize];
long index = threadIdx.x + blockIdx.x * blockDim.x;
int tid = threadIdx.x;
/*double mySum = (index < size / 2) ? d_input[index] : 0.0f;
if (index + size / 2 < size)
mySum += d_input[index + size / 2];
s_data[tid] = mySum;
__syncthreads();*/
s_data[tid] = 0.0;
if (index < size / 2)
s_data[tid] = d_input[index] + d_input[index + size / 2];
__syncthreads();
for (int s = blockDim.x / 2; s >= 1; s = s >> 1){
if (tid < s)
s_data[tid] += s_data[tid + s];
__syncthreads();
}
if (tid == 0)
d_res[blockIdx.x] = s_data[tid];
}
// deal with first loop and uproll last wrap
__global__ void kernel_reduce_half_score50(double *d_input, double *d_res, int size)
{
__shared__ volatile double s_data[constSharedMemSize];
long index = threadIdx.x + blockIdx.x * blockDim.x;
int tid = threadIdx.x;
/*
double mySum = (index < size / 2) ? d_input[index] : 0.0f;
if (index < size / 2)
mySum += d_input[index + size / 2];
s_data[tid] = mySum;
__syncthreads();*/
s_data[tid] = 0.0;
if (index < size / 2)
s_data[tid] = d_input[index] + d_input[index + size / 2];
__syncthreads();
for (int s = blockDim.x / 2; s >= 64; s = s >> 1){
if (tid < s)
s_data[tid] += s_data[tid + s];
__syncthreads();
}
if (tid < 32)
warpReduce(s_data, tid);
if (tid == 0)
d_res[blockIdx.x] = s_data[tid];
}
double sum_gpu_reduce_half(void(*kernel)(double*, double*, int), double *d_input, int size, int flag)
{
//int threadsPerBlock = constSharedMemSize;
//int numBlocks = imin(65536, (size / 2 + constSharedMemSize - 1) / constSharedMemSize);
int threadsPerBlock = constSharedMemSize;
int numBlocks = imin(65536, (nextPow2((size - 1) / 2) + constSharedMemSize - 1) / constSharedMemSize);
double *d_result;
cudaMalloc((void**)&d_result, numBlocks * sizeof(double));
kernel << <numBlocks, threadsPerBlock >> >(d_input, d_result, size);
cudaDeviceSynchronize();
if (numBlocks == 1){
double h_result;
cudaMemcpy(&h_result, d_result, sizeof(double), cudaMemcpyDeviceToHost);
if (flag)
cudaFree(d_result);
return h_result;
}
return sum_gpu_reduce_half(kernel, d_result, numBlocks, 1);
}
double sum_gpu_reduce_half_wrap(void(*kernel)(double*, double*, int), double *d_input, int size, int flag){
double value = sum_gpu_reduce_half(kernel, d_input, size, flag);
double value_gpu = 0.0;
if (size & 1) // checked if size is odd number
{
double *d_value;
cudaMalloc((void**)&d_value, sizeof(double));
access_value_in_gpu << <1, 1 >> >(d_input, d_value, size - 1);
cudaMemcpy(&value_gpu, d_value, sizeof(double), cudaMemcpyDeviceToHost);
}
return value + value_gpu;
}
//----------------------------------------------------------------------------//
//* Complete unroll last warp, using template *//
//----------------------------------------------------------------------------//
template <unsigned int blockSize>
__device__ void warpReduce2(volatile double *sdata, int tid) {
if (blockSize >= 64) sdata[tid] += sdata[tid + 32];
if (blockSize >= 32) sdata[tid] += sdata[tid + 16];
if (blockSize >= 16) sdata[tid] += sdata[tid + 8];
if (blockSize >= 8) sdata[tid] += sdata[tid + 4];
if (blockSize >= 4) sdata[tid] += sdata[tid + 2];
if (blockSize >= 2) sdata[tid] += sdata[tid + 1];
}
template <unsigned int blockSize> //, bool nIsPow2
__global__ void reduce_kernel(double *d_input, double *d_res, int size) {
extern __shared__ volatile double sdata[];
int tid = threadIdx.x;
int i = blockIdx.x * (blockSize * 2) + tid;
int gridSize = blockSize * 2 * gridDim.x;
double mySum = 0.0;
while (i < size) {
mySum += d_input[i];
// ensure we don't read out of bounds -- this is optimized away for powerOf2 sized arrays
if (i + blockSize < size)
mySum += d_input[i + blockSize];
i += gridSize;
}
sdata[tid] = mySum;
__syncthreads();
/*sdata[tid] = 0;
while (i < size) {
sdata[tid] += d_input[i] + d_input[i + blockSize];
i += gridSize;
}
__syncthreads();*/
if (blockSize >= 512) { if (tid < 256) { sdata[tid] += sdata[tid + 256]; } __syncthreads(); }
if (blockSize >= 256) { if (tid < 128) { sdata[tid] += sdata[tid + 128]; } __syncthreads(); }
if (blockSize >= 128) { if (tid < 64) { sdata[tid] += sdata[tid + 64]; } __syncthreads(); }
if (tid < 32) warpReduce2<blockSize>(sdata, tid);
if (tid == 0) d_res[blockIdx.x] = sdata[0];
}
double sum_reduce_recursive_cuda(double *d_data, int size, int flag){
int threads = (size < maxThreads * 2) ? nextPow2((size + 1) / 2) : maxThreads;
int blocks = (size + (threads * 2 - 1)) / (threads * 2);
// when there is only one warp per block, we need to allocate two warps
// worth of shared memory so that we don't index shared memory out of bounds
int smemSize = (threads <= 32) ? 2 * threads * sizeof(double) : threads * sizeof(double);
double *d_result;
cudaMalloc((void**)&d_result, blocks*sizeof(double));
switch (threads)
{
case 512:
reduce_kernel<512> << < blocks, threads, smemSize >> >(d_data, d_result, size); break;
case 256:
reduce_kernel<256> << < blocks, threads, smemSize >> >(d_data, d_result, size); break;
case 128:
reduce_kernel<128> << < blocks, threads, smemSize >> >(d_data, d_result, size); break;
case 64:
reduce_kernel< 64> << < blocks, threads, smemSize >> >(d_data, d_result, size); break;
case 32:
reduce_kernel< 32> << < blocks, threads, smemSize >> >(d_data, d_result, size); break;
case 16:
reduce_kernel< 16> << < blocks, threads, smemSize >> >(d_data, d_result, size); break;
case 8:
reduce_kernel< 8> << < blocks, threads, smemSize >> >(d_data, d_result, size); break;
case 4:
reduce_kernel< 4> << < blocks, threads, smemSize >> >(d_data, d_result, size); break;
case 2:
reduce_kernel< 2> << < blocks, threads, smemSize >> >(d_data, d_result, size); break;
case 1:
reduce_kernel< 1> << < blocks, threads, smemSize >> >(d_data, d_result, size); break;
}
cudaDeviceSynchronize();
if (blocks == 1){
double h_result;
cudaMemcpy(&h_result, d_result, sizeof(double), cudaMemcpyDeviceToHost);
if (flag){
cudaFree(d_result);
}
return h_result;
}
return sum_reduce_recursive_cuda(d_result, blocks, 1);
} | #include <stdio.h>
#include <time.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <hip/device_functions.h>
// kernel of summation from book
__global__ void kernel_sum(double *d_data, double *d_result, int data_size);
double sum_gpu(double *d_data, int data_size);
// Original kernel_A, used to generate the reference result
__global__ void kernel_reduce_score10(double *d_input, double *d_res, int size);
__global__ void kernel_reduce_score20(double *d_input, double *d_res, int size);
__global__ void kernel_reduce_score30(double *d_input, double *d_res, int size);
double sum_gpu_reduce_full(void(*kernel)(double*, double*, int), double *d_data, int data_size, int flag);
__global__ void kernel_reduce_half_score40(double *d_input, double *d_res, int size);
__global__ void kernel_reduce_half_score50(double *d_input, double *d_res, int size);
double sum_gpu_reduce_half(void(*kernel)(double*, double*, int), double *d_data, int data_size, int flag);
double sum_gpu_reduce_half_wrap(void(*kernel)(double*, double*, int), double *d_input, int size, int flag);
double sum_reduce_recursive_cuda(double *d_data, int size, int flag);
bool isPow2(unsigned int x);
unsigned int nextPow2(unsigned int x); |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <time.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <hip/device_functions.h>
// kernel of summation from book
__global__ void kernel_sum(double *d_data, double *d_result, int data_size);
double sum_gpu(double *d_data, int data_size);
// Original kernel_A, used to generate the reference result
__global__ void kernel_reduce_score10(double *d_input, double *d_res, int size);
__global__ void kernel_reduce_score20(double *d_input, double *d_res, int size);
__global__ void kernel_reduce_score30(double *d_input, double *d_res, int size);
double sum_gpu_reduce_full(void(*kernel)(double*, double*, int), double *d_data, int data_size, int flag);
__global__ void kernel_reduce_half_score40(double *d_input, double *d_res, int size);
__global__ void kernel_reduce_half_score50(double *d_input, double *d_res, int size);
double sum_gpu_reduce_half(void(*kernel)(double*, double*, int), double *d_data, int data_size, int flag);
double sum_gpu_reduce_half_wrap(void(*kernel)(double*, double*, int), double *d_input, int size, int flag);
double sum_reduce_recursive_cuda(double *d_data, int size, int flag);
bool isPow2(unsigned int x);
unsigned int nextPow2(unsigned int x); | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <time.h>
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <hip/device_functions.h>
// kernel of summation from book
__global__ void kernel_sum(double *d_data, double *d_result, int data_size);
double sum_gpu(double *d_data, int data_size);
// Original kernel_A, used to generate the reference result
__global__ void kernel_reduce_score10(double *d_input, double *d_res, int size);
__global__ void kernel_reduce_score20(double *d_input, double *d_res, int size);
__global__ void kernel_reduce_score30(double *d_input, double *d_res, int size);
double sum_gpu_reduce_full(void(*kernel)(double*, double*, int), double *d_data, int data_size, int flag);
__global__ void kernel_reduce_half_score40(double *d_input, double *d_res, int size);
__global__ void kernel_reduce_half_score50(double *d_input, double *d_res, int size);
double sum_gpu_reduce_half(void(*kernel)(double*, double*, int), double *d_data, int data_size, int flag);
double sum_gpu_reduce_half_wrap(void(*kernel)(double*, double*, int), double *d_input, int size, int flag);
double sum_reduce_recursive_cuda(double *d_data, int size, int flag);
bool isPow2(unsigned int x);
unsigned int nextPow2(unsigned int x); | .text
.file "subroutines.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <device_launch_parameters.h>
#include <cuda_runtime_api.h>
#include <iostream>
// CUDA kernel. Each thread takes care of one element of c
__global__ void deviceIteration(int *c, int *a, int H, int W)
{
// Tomamos el indice y lugar donde se calculará si vive o no.
const int k = blockIdx.x * blockDim.x + threadIdx.x;
// En caso de pasarnos no lo consideramos.
if (k < W*H) {
// Calculamos la posición en la matriz.
const int i = k / H;
const int j = k % H;
int sum = 0;
// Ahora obtenemos los indices de los vecinos.
const int left = (i + W - 1) % W;
const int right = (i + 1) % W;
const int down = (j + 1) % H;
const int up = (j + H - 1) % H;
// Calculamos la suma de los valores vecinos.
// left
if (a[right * H + j])
sum++;
// right
if (a[left * H + j])
sum++;
// up
if (a[i * H + up])
sum++;
// down
if (a[i * H + down])
sum++;
// upright
if (a[right * H + up])
sum++;
// downright
if (a[right * H + down])
sum++;
// upleft
if (a[left * H + up])
sum++;
// downleft
if (a[left * H + down])
sum++;
int value = a[k];
int result = 0;
// Guardamos el resultado obtenido, si esta vivo o no
if ((value == 1 && (sum == 2 || sum == 3)) || (value == 0 && (sum == 3 || sum == 6))) {
result = 1;
}
// Lo dejamos en la matriz final.
c[k] = result;
}
}
// CUDA kernel. Each thread takes care of one element of c
__global__ void deviceIterationNotIf(int *c, int *a, int H, int W)
{
// Tomamos el indice y lugar donde se calculará si vive o no.
const int k = blockIdx.x * blockDim.x + threadIdx.x;
// En caso de pasarnos no lo consideramos.
if (k < W*H) {
// Calculamos la posición en la matriz.
const int i = k / H;
const int j = k % H;
int sum = 0;
// Ahora obtenemos los indices de los vecinos.
const int left = (i + W - 1) % W;
const int right = (i + 1) % W;
const int down = (j + 1) % H;
const int up = (j + H - 1) % H;
// Calculamos la suma de los valores vecinos.
// left
sum += a[right * H + j];
// right
sum += a[left * H + j];
// up
sum += a[i * H + up];
// down
sum += a[i * H + down];
// upright
sum += a[right * H + up];
// downright
sum += a[right * H + down];
// upleft
sum += a[left * H + up];
// downleft
sum += a[left * H + down];
int value = a[k];
// Guardamos el resultado obtenido, si esta vivo o no
c[k] = (value == 1 && (sum == 2 || sum == 3)) || (value == 0 && (sum == 3 || sum == 6));
}
}
void run(int* a, int W, int H){
//Host output vector
int *h_c;
// Device input vectors
int *d_a;
//Device output vector
int *d_c;
// Size, in bytes, of each vector
size_t bytes = W*H*sizeof(int);
// Allocate memory for each vector on host
h_c = (int*)malloc(bytes);
// Allocate memory for each vector on GPU
cudaMalloc((void **) &d_a, bytes);
cudaMalloc((void **) &d_c, bytes);
// Copy host vectors to device
cudaMemcpy(d_a, a, bytes, cudaMemcpyHostToDevice);
int blockSize, gridSize, n;
// Tamaño de la matriz.
n = H*W;
// Tamaño del bloque. Elegir entre 32 y 31.
//blockSize = 32;
blockSize = 8;
// Number of thread blocks in grid
gridSize = (int)ceil((float)n/blockSize);
// Execute the kernel
deviceIterationNotIf<<< gridSize, blockSize >>>(d_c, d_a, H, W);
// Copy array back to host
cudaMemcpy( h_c, d_c, bytes, cudaMemcpyDeviceToHost );
// Sum up vector c and print result divided by n, this should equal 1 within error
int i,j;
for(i=0; i<W; i++) {
for(j=0; j<H; j++) {
a[i*H + j] = h_c[i*H + j];
}
}
// Release device memory
cudaFree(d_a);
cudaFree(d_c);
// Release host memory
free(h_c);
} | code for sm_80
Function : _Z20deviceIterationNotIfPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IABS R2, c[0x0][0x170] ; /* 0x00005c0000027a13 */
/* 0x000fe20000000000 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IABS R9, R0 ; /* 0x0000000000097213 */
/* 0x000fe40000000000 */
/*00b0*/ I2F.RP R3, R2 ; /* 0x0000000200037306 */
/* 0x000e300000209400 */
/*00c0*/ MUFU.RCP R3, R3 ; /* 0x0000000300037308 */
/* 0x001e240000001000 */
/*00d0*/ IADD3 R4, R3, 0xffffffe, RZ ; /* 0x0ffffffe03047810 */
/* 0x001fc40007ffe0ff */
/*00e0*/ IABS R3, c[0x0][0x174] ; /* 0x00005d0000037a13 */
/* 0x000fc80000000000 */
/*00f0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000070000021f000 */
/*0100*/ I2F.RP R6, R3 ; /* 0x0000000300067306 */
/* 0x000ea20000209400 */
/*0110*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0120*/ IMAD.MOV R7, RZ, RZ, -R5 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a05 */
/*0130*/ IMAD R7, R7, R2, RZ ; /* 0x0000000207077224 */
/* 0x000fc800078e02ff */
/*0140*/ IMAD.HI.U32 R7, R5, R7, R4 ; /* 0x0000000705077227 */
/* 0x000fe200078e0004 */
/*0150*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x004e2a0000001000 */
/*0160*/ IMAD.HI.U32 R5, R7, R9, RZ ; /* 0x0000000907057227 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.MOV R4, RZ, RZ, -R5 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a05 */
/*0180*/ IMAD R9, R2, R4, R9 ; /* 0x0000000402097224 */
/* 0x000fe200078e0209 */
/*0190*/ LOP3.LUT R4, R0, c[0x0][0x170], RZ, 0x3c, !PT ; /* 0x00005c0000047a12 */
/* 0x000fe400078e3cff */
/*01a0*/ IADD3 R8, R6, 0xffffffe, RZ ; /* 0x0ffffffe06087810 */
/* 0x001fe40007ffe0ff */
/*01b0*/ ISETP.GT.U32.AND P1, PT, R2, R9, PT ; /* 0x000000090200720c */
/* 0x000fe40003f24070 */
/*01c0*/ ISETP.GE.AND P2, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f46270 */
/*01d0*/ LOP3.LUT R4, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff047a12 */
/* 0x000fd200078e33ff */
/*01e0*/ @!P1 IMAD.IADD R9, R9, 0x1, -R2 ; /* 0x0000000109099824 */
/* 0x000fe200078e0a02 */
/*01f0*/ @!P1 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105059810 */
/* 0x000fc80007ffe0ff */
/*0200*/ ISETP.GE.U32.AND P0, PT, R9, R2, PT ; /* 0x000000020900720c */
/* 0x000fe40003f06070 */
/*0210*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000064000021f000 */
/*0220*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x001fd200078e00ff */
/*0230*/ @P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105050810 */
/* 0x000fe40007ffe0ff */
/*0240*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fe40003f05270 */
/*0250*/ @!P2 IADD3 R5, -R5, RZ, RZ ; /* 0x000000ff0505a210 */
/* 0x000fe20007ffe1ff */
/*0260*/ IMAD.MOV R6, RZ, RZ, -R9 ; /* 0x000000ffff067224 */
/* 0x002fc600078e0a09 */
/*0270*/ SEL R5, R4, R5, !P0 ; /* 0x0000000504057207 */
/* 0x000fe20004000000 */
/*0280*/ IMAD R11, R6, R3, RZ ; /* 0x00000003060b7224 */
/* 0x000fc600078e02ff */
/*0290*/ IADD3 R10, R5.reuse, c[0x0][0x174], RZ ; /* 0x00005d00050a7a10 */
/* 0x040fe20007ffe0ff */
/*02a0*/ IMAD.MOV R13, RZ, RZ, -R5 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0a05 */
/*02b0*/ IADD3 R15, R5, 0x1, RZ ; /* 0x00000001050f7810 */
/* 0x000fe20007ffe0ff */
/*02c0*/ IMAD.HI.U32 R9, R9, R11, R8 ; /* 0x0000000b09097227 */
/* 0x000fe200078e0008 */
/*02d0*/ IADD3 R10, R10, -0x1, RZ ; /* 0xffffffff0a0a7810 */
/* 0x000fe40007ffe0ff */
/*02e0*/ IABS R14, R15 ; /* 0x0000000f000e7213 */
/* 0x000fe20000000000 */
/*02f0*/ IMAD R6, R13, c[0x0][0x170], R0 ; /* 0x00005c000d067a24 */
/* 0x000fe200078e0200 */
/*0300*/ IABS R12, R10 ; /* 0x0000000a000c7213 */
/* 0x000fc60000000000 */
/*0310*/ IMAD.HI.U32 R11, R9.reuse, R14, RZ ; /* 0x0000000e090b7227 */
/* 0x040fe200078e00ff */
/*0320*/ IADD3 R8, R6.reuse, c[0x0][0x170], RZ ; /* 0x00005c0006087a10 */
/* 0x040fe40007ffe0ff */
/*0330*/ IADD3 R17, R6, 0x1, RZ ; /* 0x0000000106117810 */
/* 0x000fe20007ffe0ff */
/*0340*/ IMAD.MOV R11, RZ, RZ, -R11 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a0b */
/*0350*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fe20007ffe0ff */
/*0360*/ IMAD.HI.U32 R9, R9, R12, RZ ; /* 0x0000000c09097227 */
/* 0x000fe200078e00ff */
/*0370*/ IABS R13, R17 ; /* 0x00000011000d7213 */
/* 0x000fe40000000000 */
/*0380*/ IABS R16, R8 ; /* 0x0000000800107213 */
/* 0x000fe20000000000 */
/*0390*/ IMAD R14, R3, R11, R14 ; /* 0x0000000b030e7224 */
/* 0x000fe200078e020e */
/*03a0*/ IADD3 R11, -R9, RZ, RZ ; /* 0x000000ff090b7210 */
/* 0x000fe20007ffe1ff */
/*03b0*/ IMAD.HI.U32 R9, R7, R13, RZ ; /* 0x0000000d07097227 */
/* 0x000fe200078e00ff */
/*03c0*/ ISETP.GE.AND P5, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fc40003fa6270 */
/*03d0*/ ISETP.GT.U32.AND P2, PT, R3, R14, PT ; /* 0x0000000e0300720c */
/* 0x000fe20003f44070 */
/*03e0*/ IMAD.HI.U32 R7, R7, R16, RZ ; /* 0x0000001007077227 */
/* 0x000fc800078e00ff */
/*03f0*/ IMAD R12, R3.reuse, R11, R12 ; /* 0x0000000b030c7224 */
/* 0x040fe400078e020c */
/*0400*/ IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0a07 */
/*0410*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*0420*/ ISETP.GT.U32.AND P1, PT, R3, R12, PT ; /* 0x0000000c0300720c */
/* 0x000fe20003f24070 */
/*0430*/ IMAD R11, R2.reuse, R7, R16 ; /* 0x00000007020b7224 */
/* 0x040fe200078e0210 */
/*0440*/ LOP3.LUT R7, RZ, c[0x0][0x174], RZ, 0x33, !PT ; /* 0x00005d00ff077a12 */
/* 0x000fe200078e33ff */
/*0450*/ IMAD R9, R2, R9, R13 ; /* 0x0000000902097224 */
/* 0x000fe400078e020d */
/*0460*/ @!P2 IMAD.IADD R14, R14, 0x1, -R3 ; /* 0x000000010e0ea824 */
/* 0x000fe200078e0a03 */
/*0470*/ ISETP.GT.U32.AND P4, PT, R2, R11, PT ; /* 0x0000000b0200720c */
/* 0x000fc40003f84070 */
/*0480*/ ISETP.GT.U32.AND P3, PT, R2, R9, PT ; /* 0x000000090200720c */
/* 0x000fe40003f64070 */
/*0490*/ ISETP.GT.U32.AND P2, PT, R3, R14, PT ; /* 0x0000000e0300720c */
/* 0x000fc60003f44070 */
/*04a0*/ @!P1 IMAD.IADD R12, R12, 0x1, -R3 ; /* 0x000000010c0c9824 */
/* 0x000fe200078e0a03 */
/*04b0*/ ISETP.GE.AND P1, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fc80003f26270 */
/*04c0*/ ISETP.GT.U32.AND P6, PT, R3, R12, PT ; /* 0x0000000c0300720c */
/* 0x000fe20003fc4070 */
/*04d0*/ @!P4 IMAD.IADD R11, R11, 0x1, -R2 ; /* 0x000000010b0bc824 */
/* 0x000fe200078e0a02 */
/*04e0*/ ISETP.GE.AND P4, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f86270 */
/*04f0*/ @!P3 IADD3 R9, R9, -R2, RZ ; /* 0x800000020909b210 */
/* 0x000fe20007ffe0ff */
/*0500*/ @!P2 IMAD.IADD R14, R14, 0x1, -R3 ; /* 0x000000010e0ea824 */
/* 0x000fe200078e0a03 */
/*0510*/ ISETP.GT.U32.AND P3, PT, R2.reuse, R11, PT ; /* 0x0000000b0200720c */
/* 0x040fe40003f64070 */
/*0520*/ ISETP.GT.U32.AND P2, PT, R2, R9, PT ; /* 0x000000090200720c */
/* 0x000fe20003f44070 */
/*0530*/ @!P1 IMAD.MOV R14, RZ, RZ, -R14 ; /* 0x000000ffff0e9224 */
/* 0x000fe200078e0a0e */
/*0540*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x174], PT ; /* 0x00005d00ff007a0c */
/* 0x000fc60003f25270 */
/*0550*/ @!P6 IMAD.IADD R12, R12, 0x1, -R3 ; /* 0x000000010c0ce824 */
/* 0x000fe200078e0a03 */
/*0560*/ ISETP.GE.AND P6, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003fc6270 */
/*0570*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0580*/ SEL R15, R7, R14, !P1 ; /* 0x0000000e070f7207 */
/* 0x000fe20004800000 */
/*0590*/ @!P4 IMAD.MOV R12, RZ, RZ, -R12 ; /* 0x000000ffff0cc224 */
/* 0x000fe400078e0a0c */
/*05a0*/ @!P3 IMAD.IADD R11, R11, 0x1, -R2 ; /* 0x000000010b0bb824 */
/* 0x000fe400078e0a02 */
/*05b0*/ @!P2 IADD3 R9, R9, -R2, RZ ; /* 0x800000020909a210 */
/* 0x000fe20007ffe0ff */
/*05c0*/ IMAD R10, R15, c[0x0][0x170], R6 ; /* 0x00005c000f0a7a24 */
/* 0x000fe200078e0206 */
/*05d0*/ SEL R7, R7, R12, !P1 ; /* 0x0000000c07077207 */
/* 0x000fe20004800000 */
/*05e0*/ IMAD.MOV.U32 R13, RZ, RZ, R11 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e000b */
/*05f0*/ @!P5 IADD3 R9, -R9, RZ, RZ ; /* 0x000000ff0909d210 */
/* 0x000fe20007ffe1ff */
/*0600*/ IMAD.WIDE R10, R10, R3, c[0x0][0x168] ; /* 0x00005a000a0a7625 */
/* 0x000fc600078e0203 */
/*0610*/ SEL R16, R4.reuse, R9, !P0 ; /* 0x0000000904107207 */
/* 0x040fe20004000000 */
/*0620*/ @!P6 IMAD.MOV R13, RZ, RZ, -R13 ; /* 0x000000ffff0de224 */
/* 0x000fe200078e0a0d */
/*0630*/ LDG.E R2, [R10.64] ; /* 0x000000040a027981 */
/* 0x0000a8000c1e1900 */
/*0640*/ SEL R12, R4, R13, !P0 ; /* 0x0000000d040c7207 */
/* 0x000fe20004000000 */
/*0650*/ IMAD R8, R7, c[0x0][0x170], R6 ; /* 0x00005c0007087a24 */
/* 0x000fc800078e0206 */
/*0660*/ IMAD R4, R5.reuse, c[0x0][0x170], R12 ; /* 0x00005c0005047a24 */
/* 0x040fe400078e020c */
/*0670*/ IMAD R14, R5, c[0x0][0x170], R16.reuse ; /* 0x00005c00050e7a24 */
/* 0x100fe400078e0210 */
/*0680*/ IMAD R18, R15, c[0x0][0x170], R16.reuse ; /* 0x00005c000f127a24 */
/* 0x100fe400078e0210 */
/*0690*/ IMAD R6, R7, c[0x0][0x170], R16 ; /* 0x00005c0007067a24 */
/* 0x000fe400078e0210 */
/*06a0*/ IMAD R16, R15, c[0x0][0x170], R12 ; /* 0x00005c000f107a24 */
/* 0x000fe400078e020c */
/*06b0*/ IMAD.WIDE R4, R4, R3, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0203 */
/*06c0*/ IMAD.WIDE R8, R8, R3.reuse, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x080fe400078e0203 */
/*06d0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*06e0*/ IMAD R20, R7, c[0x0][0x170], R12 ; /* 0x00005c0007147a24 */
/* 0x000fe400078e020c */
/*06f0*/ IMAD.WIDE R12, R14, R3.reuse, c[0x0][0x168] ; /* 0x00005a000e0c7625 */
/* 0x080fe200078e0203 */
/*0700*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x0002a6000c1e1900 */
/*0710*/ IMAD.WIDE R10, R16, R3, c[0x0][0x168] ; /* 0x00005a00100a7625 */
/* 0x001fc400078e0203 */
/*0720*/ LDG.E R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000ee4000c1e1900 */
/*0730*/ IMAD.WIDE R14, R18, R3.reuse, c[0x0][0x168] ; /* 0x00005a00120e7625 */
/* 0x080fe400078e0203 */
/*0740*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee4000c1e1900 */
/*0750*/ IMAD.WIDE R16, R20, R3.reuse, c[0x0][0x168] ; /* 0x00005a0014107625 */
/* 0x080fe400078e0203 */
/*0760*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000f24000c1e1900 */
/*0770*/ IMAD.WIDE R6, R6, R3, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc400078e0203 */
/*0780*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0790*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000f62000c1e1900 */
/*07a0*/ IMAD.WIDE R8, R0, R3, c[0x0][0x168] ; /* 0x00005a0000087625 */
/* 0x002fcc00078e0203 */
/*07b0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IADD3 R2, R4, R19, R2 ; /* 0x0000001304027210 */
/* 0x004fc80007ffe002 */
/*07d0*/ IADD3 R2, R10, R2, R13 ; /* 0x000000020a027210 */
/* 0x008fc80007ffe00d */
/*07e0*/ IADD3 R2, R16, R2, R15 ; /* 0x0000000210027210 */
/* 0x010fca0007ffe00f */
/*07f0*/ IMAD.IADD R2, R2, 0x1, R7 ; /* 0x0000000102027824 */
/* 0x020fca00078e0207 */
/*0800*/ LOP3.LUT R4, R2.reuse, 0x1, RZ, 0xfc, !PT ; /* 0x0000000102047812 */
/* 0x040fe400078efcff */
/*0810*/ ISETP.NE.AND P1, PT, R2, 0x6, PT ; /* 0x000000060200780c */
/* 0x000fe40003f25270 */
/*0820*/ ISETP.NE.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f05270 */
/*0830*/ ISETP.EQ.OR P1, PT, R2, 0x3, !P1 ; /* 0x000000030200780c */
/* 0x000fe40004f22670 */
/*0840*/ ISETP.EQ.AND P0, PT, R8.reuse, 0x1, !P0 ; /* 0x000000010800780c */
/* 0x040fe40004702270 */
/*0850*/ ISETP.EQ.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fc80000f22270 */
/*0860*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20000703570 */
/*0870*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc600078e0203 */
/*0880*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fca0004000000 */
/*0890*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*08a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08b0*/ BRA 0x8b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15deviceIterationPiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IABS R2, c[0x0][0x170] ; /* 0x00005c0000027a13 */
/* 0x000fe20000000000 */
/*0090*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*00a0*/ IABS R4, R0 ; /* 0x0000000000047213 */
/* 0x000fe20000000000 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ I2F.RP R3, R2 ; /* 0x0000000200037306 */
/* 0x000e300000209400 */
/*00d0*/ MUFU.RCP R3, R3 ; /* 0x0000000300037308 */
/* 0x001e240000001000 */
/*00e0*/ IADD3 R7, R3, 0xffffffe, RZ ; /* 0x0ffffffe03077810 */
/* 0x001fc40007ffe0ff */
/*00f0*/ IABS R3, c[0x0][0x174] ; /* 0x00005d0000037a13 */
/* 0x000fc80000000000 */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e24000021f000 */
/*0110*/ IMAD.MOV R5, RZ, RZ, -R7 ; /* 0x000000ffff057224 */
/* 0x001fc800078e0a07 */
/*0120*/ IMAD R5, R5, R2, RZ ; /* 0x0000000205057224 */
/* 0x000fc800078e02ff */
/*0130*/ IMAD.HI.U32 R6, R7, R5, R6 ; /* 0x0000000507067227 */
/* 0x000fe400078e0006 */
/*0140*/ I2F.RP R7, R3 ; /* 0x0000000300077306 */
/* 0x000e240000209400 */
/*0150*/ IMAD.MOV.U32 R5, RZ, RZ, R4 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0004 */
/*0160*/ IMAD.HI.U32 R4, R6, R5, RZ ; /* 0x0000000506047227 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.MOV R8, RZ, RZ, -R4 ; /* 0x000000ffff087224 */
/* 0x000fc800078e0a04 */
/*0180*/ IMAD R5, R2.reuse, R8, R5 ; /* 0x0000000802057224 */
/* 0x040fe200078e0205 */
/*0190*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e280000001000 */
/*01a0*/ ISETP.GT.U32.AND P1, PT, R2, R5, PT ; /* 0x000000050200720c */
/* 0x000fda0003f24070 */
/*01b0*/ @!P1 IMAD.IADD R5, R5, 0x1, -R2 ; /* 0x0000000105059824 */
/* 0x000fe200078e0a02 */
/*01c0*/ IADD3 R8, R7, 0xffffffe, RZ ; /* 0x0ffffffe07087810 */
/* 0x001fe40007ffe0ff */
/*01d0*/ @!P1 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104049810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x000fe20003f06070 */
/*01f0*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000062000021f000 */
/*0200*/ LOP3.LUT R5, R0, c[0x0][0x170], RZ, 0x3c, !PT ; /* 0x00005c0000057a12 */
/* 0x000fc800078e3cff */
/*0210*/ ISETP.GE.AND P2, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f46270 */
/*0220*/ LOP3.LUT R5, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff057a12 */
/* 0x000fe200078e33ff */
/*0230*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x001fc800078e00ff */
/*0240*/ @P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104040810 */
/* 0x000fe40007ffe0ff */
/*0250*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fe20003f05270 */
/*0260*/ IMAD.MOV R12, RZ, RZ, -R9 ; /* 0x000000ffff0c7224 */
/* 0x002fc600078e0a09 */
/*0270*/ @!P2 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff04a224 */
/* 0x000fe400078e0a04 */
/*0280*/ IMAD R11, R12, R3, RZ ; /* 0x000000030c0b7224 */
/* 0x000fc600078e02ff */
/*0290*/ SEL R4, R5, R4, !P0 ; /* 0x0000000405047207 */
/* 0x000fe20004000000 */
/*02a0*/ IMAD.HI.U32 R9, R9, R11, R8 ; /* 0x0000000b09097227 */
/* 0x000fc600078e0008 */
/*02b0*/ IADD3 R10, R4.reuse, c[0x0][0x174], RZ ; /* 0x00005d00040a7a10 */
/* 0x040fe20007ffe0ff */
/*02c0*/ IMAD.MOV R7, RZ, RZ, -R4 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a04 */
/*02d0*/ IADD3 R15, R4, 0x1, RZ ; /* 0x00000001040f7810 */
/* 0x000fe40007ffe0ff */
/*02e0*/ IADD3 R10, R10, -0x1, RZ ; /* 0xffffffff0a0a7810 */
/* 0x000fe20007ffe0ff */
/*02f0*/ IMAD R7, R7, c[0x0][0x170], R0 ; /* 0x00005c0007077a24 */
/* 0x000fe200078e0200 */
/*0300*/ IABS R14, R15 ; /* 0x0000000f000e7213 */
/* 0x000fe40000000000 */
/*0310*/ IABS R12, R10 ; /* 0x0000000a000c7213 */
/* 0x000fe40000000000 */
/*0320*/ IADD3 R8, R7, c[0x0][0x170], RZ ; /* 0x00005c0007087a10 */
/* 0x000fc40007ffe0ff */
/*0330*/ IADD3 R16, R7, 0x1, RZ ; /* 0x0000000107107810 */
/* 0x000fe20007ffe0ff */
/*0340*/ IMAD.HI.U32 R11, R9.reuse, R12, RZ ; /* 0x0000000c090b7227 */
/* 0x040fe200078e00ff */
/*0350*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fe40007ffe0ff */
/*0360*/ IABS R13, R16 ; /* 0x00000010000d7213 */
/* 0x000fe20000000000 */
/*0370*/ IMAD.MOV R11, RZ, RZ, -R11 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a0b */
/*0380*/ IABS R17, R8 ; /* 0x0000000800117213 */
/* 0x000fe20000000000 */
/*0390*/ IMAD.HI.U32 R9, R9, R14, RZ ; /* 0x0000000e09097227 */
/* 0x000fc800078e00ff */
/*03a0*/ IMAD R12, R3, R11, R12 ; /* 0x0000000b030c7224 */
/* 0x000fe400078e020c */
/*03b0*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0a09 */
/*03c0*/ ISETP.GT.U32.AND P1, PT, R3.reuse, R12, PT ; /* 0x0000000c0300720c */
/* 0x040fe20003f24070 */
/*03d0*/ IMAD R14, R3, R9, R14 ; /* 0x00000009030e7224 */
/* 0x000fe400078e020e */
/*03e0*/ IMAD.HI.U32 R9, R6, R13, RZ ; /* 0x0000000d06097227 */
/* 0x000fc600078e00ff */
/*03f0*/ ISETP.GT.U32.AND P2, PT, R3, R14, PT ; /* 0x0000000e0300720c */
/* 0x000fe20003f44070 */
/*0400*/ IMAD.HI.U32 R6, R6, R17, RZ ; /* 0x0000001106067227 */
/* 0x000fc800078e00ff */
/*0410*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0a09 */
/*0420*/ IMAD.MOV R6, RZ, RZ, -R6 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0a06 */
/*0430*/ IMAD R9, R2.reuse, R9, R13 ; /* 0x0000000902097224 */
/* 0x040fe400078e020d */
/*0440*/ IMAD R11, R2, R6, R17 ; /* 0x00000006020b7224 */
/* 0x000fe400078e0211 */
/*0450*/ @!P1 IMAD.IADD R12, R12, 0x1, -R3.reuse ; /* 0x000000010c0c9824 */
/* 0x100fe200078e0a03 */
/*0460*/ ISETP.GT.U32.AND P4, PT, R2, R9, PT ; /* 0x000000090200720c */
/* 0x000fe20003f84070 */
/*0470*/ @!P2 IMAD.IADD R14, R14, 0x1, -R3 ; /* 0x000000010e0ea824 */
/* 0x000fe200078e0a03 */
/*0480*/ ISETP.GT.U32.AND P6, PT, R2, R11, PT ; /* 0x0000000b0200720c */
/* 0x000fc40003fc4070 */
/*0490*/ ISETP.GT.U32.AND P3, PT, R3.reuse, R12, PT ; /* 0x0000000c0300720c */
/* 0x040fe40003f64070 */
/*04a0*/ ISETP.GT.U32.AND P5, PT, R3, R14, PT ; /* 0x0000000e0300720c */
/* 0x000fe40003fa4070 */
/*04b0*/ ISETP.GE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f26270 */
/*04c0*/ ISETP.GE.AND P2, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fc60003f46270 */
/*04d0*/ @!P4 IMAD.IADD R9, R9, 0x1, -R2 ; /* 0x000000010909c824 */
/* 0x000fe400078e0a02 */
/*04e0*/ @!P6 IADD3 R11, R11, -R2, RZ ; /* 0x800000020b0be210 */
/* 0x000fe40007ffe0ff */
/*04f0*/ @!P3 IMAD.IADD R12, R12, 0x1, -R3.reuse ; /* 0x000000010c0cb824 */
/* 0x100fe200078e0a03 */
/*0500*/ ISETP.GT.U32.AND P3, PT, R2, R9, PT ; /* 0x000000090200720c */
/* 0x000fe20003f64070 */
/*0510*/ @!P5 IMAD.IADD R14, R14, 0x1, -R3 ; /* 0x000000010e0ed824 */
/* 0x000fe200078e0a03 */
/*0520*/ ISETP.GT.U32.AND P4, PT, R2, R11, PT ; /* 0x0000000b0200720c */
/* 0x000fe20003f84070 */
/*0530*/ @!P1 IMAD.MOV R12, RZ, RZ, -R12 ; /* 0x000000ffff0c9224 */
/* 0x000fe200078e0a0c */
/*0540*/ ISETP.GE.AND P6, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe20003fc6270 */
/*0550*/ @!P2 IMAD.MOV R14, RZ, RZ, -R14 ; /* 0x000000ffff0ea224 */
/* 0x000fe200078e0a0e */
/*0560*/ ISETP.GE.AND P5, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fc40003fa6270 */
/*0570*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x174], PT ; /* 0x00005d00ff007a0c */
/* 0x000fe40003f25270 */
/*0580*/ LOP3.LUT R3, RZ, c[0x0][0x174], RZ, 0x33, !PT ; /* 0x00005d00ff037a12 */
/* 0x000fc600078e33ff */
/*0590*/ @!P3 IMAD.IADD R9, R9, 0x1, -R2.reuse ; /* 0x000000010909b824 */
/* 0x100fe200078e0a02 */
/*05a0*/ SEL R6, R3, R14, !P1 ; /* 0x0000000e03067207 */
/* 0x000fe20004800000 */
/*05b0*/ @!P4 IMAD.IADD R11, R11, 0x1, -R2 ; /* 0x000000010b0bc824 */
/* 0x000fe200078e0a02 */
/*05c0*/ SEL R2, R3, R12, !P1 ; /* 0x0000000c03027207 */
/* 0x000fe20004800000 */
/*05d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*05e0*/ @!P6 IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff09e224 */
/* 0x000fe200078e0a09 */
/*05f0*/ @!P5 IADD3 R11, -R11, RZ, RZ ; /* 0x000000ff0b0bd210 */
/* 0x000fe20007ffe1ff */
/*0600*/ IMAD R12, R2, c[0x0][0x170], R7.reuse ; /* 0x00005c00020c7a24 */
/* 0x100fe400078e0207 */
/*0610*/ IMAD R10, R6, c[0x0][0x170], R7 ; /* 0x00005c00060a7a24 */
/* 0x000fe200078e0207 */
/*0620*/ SEL R21, R5.reuse, R11, !P0 ; /* 0x0000000b05157207 */
/* 0x040fe20004000000 */
/*0630*/ IMAD.WIDE R12, R12, R3, c[0x0][0x168] ; /* 0x00005a000c0c7625 */
/* 0x000fe200078e0203 */
/*0640*/ SEL R7, R5, R9, !P0 ; /* 0x0000000905077207 */
/* 0x000fc60004000000 */
/*0650*/ IMAD.WIDE R10, R10, R3.reuse, c[0x0][0x168] ; /* 0x00005a000a0a7625 */
/* 0x080fe200078e0203 */
/*0660*/ LDG.E R5, [R12.64] ; /* 0x000000040c057981 */
/* 0x0000a6000c1e1900 */
/*0670*/ IMAD R14, R4.reuse, c[0x0][0x170], R21 ; /* 0x00005c00040e7a24 */
/* 0x040fe200078e0215 */
/*0680*/ LDG.E R8, [R10.64] ; /* 0x000000040a087981 */
/* 0x0002e2000c1e1900 */
/*0690*/ IMAD R16, R4, c[0x0][0x170], R7 ; /* 0x00005c0004107a24 */
/* 0x000fe400078e0207 */
/*06a0*/ IMAD.WIDE R14, R14, R3, c[0x0][0x168] ; /* 0x00005a000e0e7625 */
/* 0x000fc800078e0203 */
/*06b0*/ IMAD.WIDE R16, R16, R3.reuse, c[0x0][0x168] ; /* 0x00005a0010107625 */
/* 0x080fe200078e0203 */
/*06c0*/ LDG.E R4, [R14.64] ; /* 0x000000040e047981 */
/* 0x000966000c1e1900 */
/*06d0*/ IMAD R18, R6.reuse, c[0x0][0x170], R21 ; /* 0x00005c0006127a24 */
/* 0x040fe200078e0215 */
/*06e0*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000f62000c1e1900 */
/*06f0*/ IMAD R6, R6, c[0x0][0x170], R7 ; /* 0x00005c0006067a24 */
/* 0x000fe400078e0207 */
/*0700*/ IMAD.WIDE R18, R18, R3, c[0x0][0x168] ; /* 0x00005a0012127625 */
/* 0x000fc800078e0203 */
/*0710*/ IMAD.WIDE R12, R6, R3.reuse, c[0x0][0x168] ; /* 0x00005a00060c7625 */
/* 0x081fe400078e0203 */
/*0720*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f64000c1e1900 */
/*0730*/ IMAD R10, R2.reuse, c[0x0][0x170], R21 ; /* 0x00005c00020a7a24 */
/* 0x042fe400078e0215 */
/*0740*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f62000c1e1900 */
/*0750*/ IMAD R6, R2, c[0x0][0x170], R7 ; /* 0x00005c0002067a24 */
/* 0x000fe400078e0207 */
/*0760*/ IMAD.WIDE R10, R10, R3, c[0x0][0x168] ; /* 0x00005a000a0a7625 */
/* 0x000fc800078e0203 */
/*0770*/ IMAD.WIDE R6, R6, R3.reuse, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x080fe400078e0203 */
/*0780*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f68000c1e1900 */
/*0790*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f62000c1e1900 */
/*07a0*/ IMAD.WIDE R14, R0, R3, c[0x0][0x168] ; /* 0x00005a00000e7625 */
/* 0x010fcc00078e0203 */
/*07b0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f22000c1e1900 */
/*07c0*/ ISETP.NE.AND P2, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x004fe20003f45270 */
/*07d0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x2 ; /* 0x00000002ff057424 */
/* 0x000fe200078e00ff */
/*07e0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x008fc80003f05270 */
/*07f0*/ SEL R2, RZ, 0x1, !P0 ; /* 0x00000001ff027807 */
/* 0x000fe40004000000 */
/*0800*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x020fca0003f25270 */
/*0810*/ @P2 SEL R2, R5, 0x1, P0 ; /* 0x0000000105022807 */
/* 0x000fe40000000000 */
/*0820*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f05270 */
/*0830*/ SEL R5, RZ, 0x1, !P1 ; /* 0x00000001ff057807 */
/* 0x000fca0004800000 */
/*0840*/ IMAD.IADD R2, R2, 0x1, R5 ; /* 0x0000000102027824 */
/* 0x000fe200078e0205 */
/*0850*/ ISETP.NE.AND P1, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fc80003f25270 */
/*0860*/ IADD3 R4, R2, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x000fe20007ffe0ff */
/*0870*/ @!P0 IMAD.MOV R4, RZ, RZ, R2 ; /* 0x000000ffff048224 */
/* 0x000fe200078e0202 */
/*0880*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fc80003f05270 */
/*0890*/ IADD3 R2, R4, 0x1, RZ ; /* 0x0000000104027810 */
/* 0x000fc60007ffe0ff */
/*08a0*/ @!P1 IMAD.MOV R2, RZ, RZ, R4 ; /* 0x000000ffff029224 */
/* 0x000fe200078e0204 */
/*08b0*/ ISETP.NE.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fc80003f25270 */
/*08c0*/ IADD3 R4, R2, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x000fe20007ffe0ff */
/*08d0*/ @!P0 IMAD.MOV R4, RZ, RZ, R2 ; /* 0x000000ffff048224 */
/* 0x000fe200078e0202 */
/*08e0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc80003f05270 */
/*08f0*/ IADD3 R2, R4, 0x1, RZ ; /* 0x0000000104027810 */
/* 0x000fc60007ffe0ff */
/*0900*/ @!P1 IMAD.MOV R2, RZ, RZ, R4 ; /* 0x000000ffff029224 */
/* 0x000fca00078e0204 */
/*0910*/ IADD3 R4, R2, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x000fe20007ffe0ff */
/*0920*/ @!P0 IMAD.MOV R4, RZ, RZ, R2 ; /* 0x000000ffff048224 */
/* 0x000fca00078e0202 */
/*0930*/ LOP3.LUT R2, R4.reuse, 0x1, RZ, 0xfc, !PT ; /* 0x0000000104027812 */
/* 0x040fe400078efcff */
/*0940*/ ISETP.NE.AND P1, PT, R4, 0x6, PT ; /* 0x000000060400780c */
/* 0x000fe40003f25270 */
/*0950*/ ISETP.NE.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f05270 */
/*0960*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fe200078e0203 */
/*0970*/ ISETP.EQ.OR P1, PT, R4, 0x3, !P1 ; /* 0x000000030400780c */
/* 0x000fe40004f22670 */
/*0980*/ ISETP.EQ.AND P0, PT, R14.reuse, 0x1, !P0 ; /* 0x000000010e00780c */
/* 0x050fe40004702270 */
/*0990*/ ISETP.EQ.AND P1, PT, R14, RZ, P1 ; /* 0x000000ff0e00720c */
/* 0x000fc80000f22270 */
/*09a0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc80000703570 */
/*09b0*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fca0004000000 */
/*09c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*09d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09e0*/ BRA 0x9e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <device_launch_parameters.h>
#include <cuda_runtime_api.h>
#include <iostream>
// CUDA kernel. Each thread takes care of one element of c
__global__ void deviceIteration(int *c, int *a, int H, int W)
{
// Tomamos el indice y lugar donde se calculará si vive o no.
const int k = blockIdx.x * blockDim.x + threadIdx.x;
// En caso de pasarnos no lo consideramos.
if (k < W*H) {
// Calculamos la posición en la matriz.
const int i = k / H;
const int j = k % H;
int sum = 0;
// Ahora obtenemos los indices de los vecinos.
const int left = (i + W - 1) % W;
const int right = (i + 1) % W;
const int down = (j + 1) % H;
const int up = (j + H - 1) % H;
// Calculamos la suma de los valores vecinos.
// left
if (a[right * H + j])
sum++;
// right
if (a[left * H + j])
sum++;
// up
if (a[i * H + up])
sum++;
// down
if (a[i * H + down])
sum++;
// upright
if (a[right * H + up])
sum++;
// downright
if (a[right * H + down])
sum++;
// upleft
if (a[left * H + up])
sum++;
// downleft
if (a[left * H + down])
sum++;
int value = a[k];
int result = 0;
// Guardamos el resultado obtenido, si esta vivo o no
if ((value == 1 && (sum == 2 || sum == 3)) || (value == 0 && (sum == 3 || sum == 6))) {
result = 1;
}
// Lo dejamos en la matriz final.
c[k] = result;
}
}
// CUDA kernel. Each thread takes care of one element of c
__global__ void deviceIterationNotIf(int *c, int *a, int H, int W)
{
// Tomamos el indice y lugar donde se calculará si vive o no.
const int k = blockIdx.x * blockDim.x + threadIdx.x;
// En caso de pasarnos no lo consideramos.
if (k < W*H) {
// Calculamos la posición en la matriz.
const int i = k / H;
const int j = k % H;
int sum = 0;
// Ahora obtenemos los indices de los vecinos.
const int left = (i + W - 1) % W;
const int right = (i + 1) % W;
const int down = (j + 1) % H;
const int up = (j + H - 1) % H;
// Calculamos la suma de los valores vecinos.
// left
sum += a[right * H + j];
// right
sum += a[left * H + j];
// up
sum += a[i * H + up];
// down
sum += a[i * H + down];
// upright
sum += a[right * H + up];
// downright
sum += a[right * H + down];
// upleft
sum += a[left * H + up];
// downleft
sum += a[left * H + down];
int value = a[k];
// Guardamos el resultado obtenido, si esta vivo o no
c[k] = (value == 1 && (sum == 2 || sum == 3)) || (value == 0 && (sum == 3 || sum == 6));
}
}
void run(int* a, int W, int H){
//Host output vector
int *h_c;
// Device input vectors
int *d_a;
//Device output vector
int *d_c;
// Size, in bytes, of each vector
size_t bytes = W*H*sizeof(int);
// Allocate memory for each vector on host
h_c = (int*)malloc(bytes);
// Allocate memory for each vector on GPU
cudaMalloc((void **) &d_a, bytes);
cudaMalloc((void **) &d_c, bytes);
// Copy host vectors to device
cudaMemcpy(d_a, a, bytes, cudaMemcpyHostToDevice);
int blockSize, gridSize, n;
// Tamaño de la matriz.
n = H*W;
// Tamaño del bloque. Elegir entre 32 y 31.
//blockSize = 32;
blockSize = 8;
// Number of thread blocks in grid
gridSize = (int)ceil((float)n/blockSize);
// Execute the kernel
deviceIterationNotIf<<< gridSize, blockSize >>>(d_c, d_a, H, W);
// Copy array back to host
cudaMemcpy( h_c, d_c, bytes, cudaMemcpyDeviceToHost );
// Sum up vector c and print result divided by n, this should equal 1 within error
int i,j;
for(i=0; i<W; i++) {
for(j=0; j<H; j++) {
a[i*H + j] = h_c[i*H + j];
}
}
// Release device memory
cudaFree(d_a);
cudaFree(d_c);
// Release host memory
free(h_c);
} | .file "tmpxft_0011b632_00000000-6_parallelCuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z15deviceIterationPiS_iiPiS_ii
.type _Z39__device_stub__Z15deviceIterationPiS_iiPiS_ii, @function
_Z39__device_stub__Z15deviceIterationPiS_iiPiS_ii:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15deviceIterationPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z39__device_stub__Z15deviceIterationPiS_iiPiS_ii, .-_Z39__device_stub__Z15deviceIterationPiS_iiPiS_ii
.globl _Z15deviceIterationPiS_ii
.type _Z15deviceIterationPiS_ii, @function
_Z15deviceIterationPiS_ii:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15deviceIterationPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z15deviceIterationPiS_ii, .-_Z15deviceIterationPiS_ii
.globl _Z44__device_stub__Z20deviceIterationNotIfPiS_iiPiS_ii
.type _Z44__device_stub__Z20deviceIterationNotIfPiS_iiPiS_ii, @function
_Z44__device_stub__Z20deviceIterationNotIfPiS_iiPiS_ii:
.LFB3696:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20deviceIterationNotIfPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z44__device_stub__Z20deviceIterationNotIfPiS_iiPiS_ii, .-_Z44__device_stub__Z20deviceIterationNotIfPiS_iiPiS_ii
.globl _Z20deviceIterationNotIfPiS_ii
.type _Z20deviceIterationNotIfPiS_ii, @function
_Z20deviceIterationNotIfPiS_ii:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z20deviceIterationNotIfPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z20deviceIterationNotIfPiS_ii, .-_Z20deviceIterationNotIfPiS_ii
.globl _Z3runPiii
.type _Z3runPiii, @function
_Z3runPiii:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %rbp
movl %esi, %r13d
movl %edx, %r12d
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl %esi, %r15d
imull %edx, %r15d
movslq %r15d, %r14
salq $2, %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbx
movq %rsp, %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %r15d, %xmm0
mulss .LC0(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC4(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC1(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L20
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC3(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L20:
movl $8, 28(%rsp)
movl $1, 32(%rsp)
cvttss2sil %xmm3, %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L21:
movl $2, %ecx
movq %r14, %rdx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
testl %r13d, %r13d
jle .L22
movl $0, %edi
movl $0, %esi
movslq %r12d, %r8
jmp .L23
.L30:
movl %r13d, %ecx
movl %r12d, %edx
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z44__device_stub__Z20deviceIterationNotIfPiS_iiPiS_ii
jmp .L21
.L25:
movslq %edi, %rcx
leaq 0(,%rcx,4), %rax
addq %r8, %rcx
salq $2, %rcx
.L24:
movl (%rbx,%rax), %edx
movl %edx, 0(%rbp,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L24
.L26:
addl $1, %esi
addl %r12d, %edi
cmpl %esi, %r13d
je .L22
.L23:
testl %r12d, %r12d
jg .L25
jmp .L26
.L22:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z3runPiii, .-_Z3runPiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "_Z20deviceIterationNotIfPiS_ii"
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "_Z15deviceIterationPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z20deviceIterationNotIfPiS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z15deviceIterationPiS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1040187392
.align 4
.LC1:
.long 1258291200
.align 4
.LC3:
.long 1065353216
.align 4
.LC4:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <device_launch_parameters.h>
#include <cuda_runtime_api.h>
#include <iostream>
// CUDA kernel. Each thread takes care of one element of c
__global__ void deviceIteration(int *c, int *a, int H, int W)
{
// Tomamos el indice y lugar donde se calculará si vive o no.
const int k = blockIdx.x * blockDim.x + threadIdx.x;
// En caso de pasarnos no lo consideramos.
if (k < W*H) {
// Calculamos la posición en la matriz.
const int i = k / H;
const int j = k % H;
int sum = 0;
// Ahora obtenemos los indices de los vecinos.
const int left = (i + W - 1) % W;
const int right = (i + 1) % W;
const int down = (j + 1) % H;
const int up = (j + H - 1) % H;
// Calculamos la suma de los valores vecinos.
// left
if (a[right * H + j])
sum++;
// right
if (a[left * H + j])
sum++;
// up
if (a[i * H + up])
sum++;
// down
if (a[i * H + down])
sum++;
// upright
if (a[right * H + up])
sum++;
// downright
if (a[right * H + down])
sum++;
// upleft
if (a[left * H + up])
sum++;
// downleft
if (a[left * H + down])
sum++;
int value = a[k];
int result = 0;
// Guardamos el resultado obtenido, si esta vivo o no
if ((value == 1 && (sum == 2 || sum == 3)) || (value == 0 && (sum == 3 || sum == 6))) {
result = 1;
}
// Lo dejamos en la matriz final.
c[k] = result;
}
}
// CUDA kernel. Each thread takes care of one element of c
__global__ void deviceIterationNotIf(int *c, int *a, int H, int W)
{
// Tomamos el indice y lugar donde se calculará si vive o no.
const int k = blockIdx.x * blockDim.x + threadIdx.x;
// En caso de pasarnos no lo consideramos.
if (k < W*H) {
// Calculamos la posición en la matriz.
const int i = k / H;
const int j = k % H;
int sum = 0;
// Ahora obtenemos los indices de los vecinos.
const int left = (i + W - 1) % W;
const int right = (i + 1) % W;
const int down = (j + 1) % H;
const int up = (j + H - 1) % H;
// Calculamos la suma de los valores vecinos.
// left
sum += a[right * H + j];
// right
sum += a[left * H + j];
// up
sum += a[i * H + up];
// down
sum += a[i * H + down];
// upright
sum += a[right * H + up];
// downright
sum += a[right * H + down];
// upleft
sum += a[left * H + up];
// downleft
sum += a[left * H + down];
int value = a[k];
// Guardamos el resultado obtenido, si esta vivo o no
c[k] = (value == 1 && (sum == 2 || sum == 3)) || (value == 0 && (sum == 3 || sum == 6));
}
}
void run(int* a, int W, int H){
//Host output vector
int *h_c;
// Device input vectors
int *d_a;
//Device output vector
int *d_c;
// Size, in bytes, of each vector
size_t bytes = W*H*sizeof(int);
// Allocate memory for each vector on host
h_c = (int*)malloc(bytes);
// Allocate memory for each vector on GPU
cudaMalloc((void **) &d_a, bytes);
cudaMalloc((void **) &d_c, bytes);
// Copy host vectors to device
cudaMemcpy(d_a, a, bytes, cudaMemcpyHostToDevice);
int blockSize, gridSize, n;
// Tamaño de la matriz.
n = H*W;
// Tamaño del bloque. Elegir entre 32 y 31.
//blockSize = 32;
blockSize = 8;
// Number of thread blocks in grid
gridSize = (int)ceil((float)n/blockSize);
// Execute the kernel
deviceIterationNotIf<<< gridSize, blockSize >>>(d_c, d_a, H, W);
// Copy array back to host
cudaMemcpy( h_c, d_c, bytes, cudaMemcpyDeviceToHost );
// Sum up vector c and print result divided by n, this should equal 1 within error
int i,j;
for(i=0; i<W; i++) {
for(j=0; j<H; j++) {
a[i*H + j] = h_c[i*H + j];
}
}
// Release device memory
cudaFree(d_a);
cudaFree(d_c);
// Release host memory
free(h_c);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime_api.h>
#include <iostream>
// CUDA kernel. Each thread takes care of one element of c
__global__ void deviceIteration(int *c, int *a, int H, int W)
{
// Tomamos el indice y lugar donde se calculará si vive o no.
const int k = blockIdx.x * blockDim.x + threadIdx.x;
// En caso de pasarnos no lo consideramos.
if (k < W*H) {
// Calculamos la posición en la matriz.
const int i = k / H;
const int j = k % H;
int sum = 0;
// Ahora obtenemos los indices de los vecinos.
const int left = (i + W - 1) % W;
const int right = (i + 1) % W;
const int down = (j + 1) % H;
const int up = (j + H - 1) % H;
// Calculamos la suma de los valores vecinos.
// left
if (a[right * H + j])
sum++;
// right
if (a[left * H + j])
sum++;
// up
if (a[i * H + up])
sum++;
// down
if (a[i * H + down])
sum++;
// upright
if (a[right * H + up])
sum++;
// downright
if (a[right * H + down])
sum++;
// upleft
if (a[left * H + up])
sum++;
// downleft
if (a[left * H + down])
sum++;
int value = a[k];
int result = 0;
// Guardamos el resultado obtenido, si esta vivo o no
if ((value == 1 && (sum == 2 || sum == 3)) || (value == 0 && (sum == 3 || sum == 6))) {
result = 1;
}
// Lo dejamos en la matriz final.
c[k] = result;
}
}
// CUDA kernel. Each thread takes care of one element of c
__global__ void deviceIterationNotIf(int *c, int *a, int H, int W)
{
// Tomamos el indice y lugar donde se calculará si vive o no.
const int k = blockIdx.x * blockDim.x + threadIdx.x;
// En caso de pasarnos no lo consideramos.
if (k < W*H) {
// Calculamos la posición en la matriz.
const int i = k / H;
const int j = k % H;
int sum = 0;
// Ahora obtenemos los indices de los vecinos.
const int left = (i + W - 1) % W;
const int right = (i + 1) % W;
const int down = (j + 1) % H;
const int up = (j + H - 1) % H;
// Calculamos la suma de los valores vecinos.
// left
sum += a[right * H + j];
// right
sum += a[left * H + j];
// up
sum += a[i * H + up];
// down
sum += a[i * H + down];
// upright
sum += a[right * H + up];
// downright
sum += a[right * H + down];
// upleft
sum += a[left * H + up];
// downleft
sum += a[left * H + down];
int value = a[k];
// Guardamos el resultado obtenido, si esta vivo o no
c[k] = (value == 1 && (sum == 2 || sum == 3)) || (value == 0 && (sum == 3 || sum == 6));
}
}
void run(int* a, int W, int H){
//Host output vector
int *h_c;
// Device input vectors
int *d_a;
//Device output vector
int *d_c;
// Size, in bytes, of each vector
size_t bytes = W*H*sizeof(int);
// Allocate memory for each vector on host
h_c = (int*)malloc(bytes);
// Allocate memory for each vector on GPU
hipMalloc((void **) &d_a, bytes);
hipMalloc((void **) &d_c, bytes);
// Copy host vectors to device
hipMemcpy(d_a, a, bytes, hipMemcpyHostToDevice);
int blockSize, gridSize, n;
// Tamaño de la matriz.
n = H*W;
// Tamaño del bloque. Elegir entre 32 y 31.
//blockSize = 32;
blockSize = 8;
// Number of thread blocks in grid
gridSize = (int)ceil((float)n/blockSize);
// Execute the kernel
deviceIterationNotIf<<< gridSize, blockSize >>>(d_c, d_a, H, W);
// Copy array back to host
hipMemcpy( h_c, d_c, bytes, hipMemcpyDeviceToHost );
// Sum up vector c and print result divided by n, this should equal 1 within error
int i,j;
for(i=0; i<W; i++) {
for(j=0; j<H; j++) {
a[i*H + j] = h_c[i*H + j];
}
}
// Release device memory
hipFree(d_a);
hipFree(d_c);
// Release host memory
free(h_c);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime_api.h>
#include <iostream>
// CUDA kernel. Each thread takes care of one element of c
__global__ void deviceIteration(int *c, int *a, int H, int W)
{
// Tomamos el indice y lugar donde se calculará si vive o no.
const int k = blockIdx.x * blockDim.x + threadIdx.x;
// En caso de pasarnos no lo consideramos.
if (k < W*H) {
// Calculamos la posición en la matriz.
const int i = k / H;
const int j = k % H;
int sum = 0;
// Ahora obtenemos los indices de los vecinos.
const int left = (i + W - 1) % W;
const int right = (i + 1) % W;
const int down = (j + 1) % H;
const int up = (j + H - 1) % H;
// Calculamos la suma de los valores vecinos.
// left
if (a[right * H + j])
sum++;
// right
if (a[left * H + j])
sum++;
// up
if (a[i * H + up])
sum++;
// down
if (a[i * H + down])
sum++;
// upright
if (a[right * H + up])
sum++;
// downright
if (a[right * H + down])
sum++;
// upleft
if (a[left * H + up])
sum++;
// downleft
if (a[left * H + down])
sum++;
int value = a[k];
int result = 0;
// Guardamos el resultado obtenido, si esta vivo o no
if ((value == 1 && (sum == 2 || sum == 3)) || (value == 0 && (sum == 3 || sum == 6))) {
result = 1;
}
// Lo dejamos en la matriz final.
c[k] = result;
}
}
// CUDA kernel. Each thread takes care of one element of c
__global__ void deviceIterationNotIf(int *c, int *a, int H, int W)
{
// Tomamos el indice y lugar donde se calculará si vive o no.
const int k = blockIdx.x * blockDim.x + threadIdx.x;
// En caso de pasarnos no lo consideramos.
if (k < W*H) {
// Calculamos la posición en la matriz.
const int i = k / H;
const int j = k % H;
int sum = 0;
// Ahora obtenemos los indices de los vecinos.
const int left = (i + W - 1) % W;
const int right = (i + 1) % W;
const int down = (j + 1) % H;
const int up = (j + H - 1) % H;
// Calculamos la suma de los valores vecinos.
// left
sum += a[right * H + j];
// right
sum += a[left * H + j];
// up
sum += a[i * H + up];
// down
sum += a[i * H + down];
// upright
sum += a[right * H + up];
// downright
sum += a[right * H + down];
// upleft
sum += a[left * H + up];
// downleft
sum += a[left * H + down];
int value = a[k];
// Guardamos el resultado obtenido, si esta vivo o no
c[k] = (value == 1 && (sum == 2 || sum == 3)) || (value == 0 && (sum == 3 || sum == 6));
}
}
void run(int* a, int W, int H){
//Host output vector
int *h_c;
// Device input vectors
int *d_a;
//Device output vector
int *d_c;
// Size, in bytes, of each vector
size_t bytes = W*H*sizeof(int);
// Allocate memory for each vector on host
h_c = (int*)malloc(bytes);
// Allocate memory for each vector on GPU
hipMalloc((void **) &d_a, bytes);
hipMalloc((void **) &d_c, bytes);
// Copy host vectors to device
hipMemcpy(d_a, a, bytes, hipMemcpyHostToDevice);
int blockSize, gridSize, n;
// Tamaño de la matriz.
n = H*W;
// Tamaño del bloque. Elegir entre 32 y 31.
//blockSize = 32;
blockSize = 8;
// Number of thread blocks in grid
gridSize = (int)ceil((float)n/blockSize);
// Execute the kernel
deviceIterationNotIf<<< gridSize, blockSize >>>(d_c, d_a, H, W);
// Copy array back to host
hipMemcpy( h_c, d_c, bytes, hipMemcpyDeviceToHost );
// Sum up vector c and print result divided by n, this should equal 1 within error
int i,j;
for(i=0; i<W; i++) {
for(j=0; j<H; j++) {
a[i*H + j] = h_c[i*H + j];
}
}
// Release device memory
hipFree(d_a);
hipFree(d_c);
// Release host memory
free(h_c);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15deviceIterationPiS_ii
.globl _Z15deviceIterationPiS_ii
.p2align 8
.type _Z15deviceIterationPiS_ii,@function
_Z15deviceIterationPiS_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mul_i32 s4, s3, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_6
s_ashr_i32 s4, s2, 31
v_ashrrev_i32_e32 v3, 31, v1
s_add_i32 s5, s2, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s5, s5, s4
v_add_nc_u32_e32 v4, v1, v3
v_cvt_f32_u32_e32 v0, s5
s_sub_i32 s6, 0, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v4, v3
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v3, s4, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s6, v0
s_ashr_i32 s6, s3, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s3, s6
s_xor_b32 s6, s7, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_u32_e32 v6, s6
v_mul_hi_u32 v2, v0, v2
s_sub_i32 s4, 0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
v_mul_hi_u32 v2, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v2, s5
v_sub_nc_u32_e32 v4, v4, v5
v_add_nc_u32_e32 v5, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s5, v4
v_subrev_nc_u32_e32 v7, s5, v4
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
v_rcp_iflag_f32_e32 v5, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v4, v7, vcc_lo
v_add_nc_u32_e32 v6, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_le_u32_e32 vcc_lo, s5, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v5
v_cvt_u32_f32_e32 v4, v4
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v3
v_sub_nc_u32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, s4, v4
v_add3_u32 v5, s3, -1, v2
v_mul_lo_u32 v8, v2, s2
v_add_nc_u32_e32 v2, 1, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_hi_u32 v3, v4, v3
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v7, 31, v2
v_sub_nc_u32_e32 v9, v1, v8
v_add_nc_u32_e32 v5, v5, v6
v_add_nc_u32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v2, v2, v7
v_add_nc_u32_e32 v4, 1, v9
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_xor_b32_e32 v5, v5, v6
v_add3_u32 v10, s2, -1, v9
v_xor_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v11, 31, v4
v_mul_hi_u32 v13, v5, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v12, 31, v10
v_mul_hi_u32 v3, v2, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v4, v4, v11
v_add_nc_u32_e32 v10, v10, v12
v_mul_lo_u32 v13, v13, s6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_xor_b32_e32 v4, v4, v11
v_mul_lo_u32 v3, v3, s6
v_xor_b32_e32 v10, v10, v12
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v5, v5, v13
v_sub_nc_u32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s6, v5
v_cmp_le_u32_e32 vcc_lo, s6, v5
v_cndmask_b32_e32 v3, v5, v3, vcc_lo
v_mul_hi_u32 v14, v4, v0
v_mul_hi_u32 v0, v10, v0
v_cmp_le_u32_e32 vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_subrev_nc_u32_e32 v5, s6, v3
v_mul_lo_u32 v13, v14, s5
v_subrev_nc_u32_e32 v14, s6, v2
v_mul_lo_u32 v0, v0, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v2, v2, v14, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s6, v3
v_sub_nc_u32_e32 v4, v4, v13
v_sub_nc_u32_e32 v0, v10, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_subrev_nc_u32_e32 v10, s6, v2
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s6, v2
v_subrev_nc_u32_e32 v13, s5, v4
v_subrev_nc_u32_e32 v14, s5, v0
v_xor_b32_e32 v3, v3, v6
v_cndmask_b32_e32 v2, v2, v10, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s5, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v3, v3, v6
v_xor_b32_e32 v2, v2, v7
v_cndmask_b32_e32 v4, v4, v13, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s5, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v2, v2, v7
v_subrev_nc_u32_e32 v5, s5, v4
v_cndmask_b32_e32 v0, v0, v14, vcc_lo
v_mul_lo_u32 v14, v3, s2
v_cmp_le_u32_e32 vcc_lo, s5, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
v_add_nc_u32_e32 v5, v14, v9
v_subrev_nc_u32_e32 v10, s5, v0
v_cmp_le_u32_e32 vcc_lo, s5, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v6, 31, v5
v_cndmask_b32_e32 v0, v0, v10, vcc_lo
v_mul_lo_u32 v10, v2, s2
s_load_b64 s[2:3], s[0:1], 0x8
v_xor_b32_e32 v2, v4, v11
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_xor_b32_e32 v0, v0, v12
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, v10, v9
v_sub_nc_u32_e32 v0, v0, v12
v_sub_nc_u32_e32 v12, v2, v11
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v4, 31, v3
v_add_nc_u32_e32 v7, v0, v8
s_delay_alu instid0(VALU_DEP_4)
v_add_nc_u32_e32 v9, v12, v8
v_add_nc_u32_e32 v11, v0, v10
v_add_nc_u32_e32 v13, v10, v12
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_ashrrev_i32_e32 v8, 31, v7
v_ashrrev_i32_e32 v10, 31, v9
v_add_nc_u32_e32 v17, v12, v14
v_ashrrev_i32_e32 v12, 31, v11
v_add_nc_u32_e32 v15, v0, v14
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
v_lshlrev_b64 v[11:12], 2, v[11:12]
global_load_b32 v19, v[3:4], off
v_add_co_u32 v3, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v8, vcc_lo
v_add_co_u32 v7, vcc_lo, s2, v9
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v10, vcc_lo
v_add_co_u32 v9, vcc_lo, s2, v11
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v12, vcc_lo
s_clause 0x1
global_load_b32 v11, v[5:6], off
global_load_b32 v12, v[3:4], off
v_ashrrev_i32_e32 v14, 31, v13
v_ashrrev_i32_e32 v16, 31, v15
s_clause 0x1
global_load_b32 v7, v[7:8], off
global_load_b32 v8, v[9:10], off
v_ashrrev_i32_e32 v18, 31, v17
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_lshlrev_b64 v[13:14], 2, v[13:14]
v_lshlrev_b64 v[15:16], 2, v[15:16]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[17:18], 2, v[17:18]
v_add_co_u32 v3, vcc_lo, s2, v13
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v14, vcc_lo
v_add_co_u32 v5, vcc_lo, s2, v15
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v16, vcc_lo
global_load_b32 v9, v[3:4], off
v_add_co_u32 v3, vcc_lo, s2, v17
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v18, vcc_lo
global_load_b32 v5, v[5:6], off
v_add_co_u32 v2, vcc_lo, s2, v0
global_load_b32 v4, v[3:4], off
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(8)
v_cmp_ne_u32_e32 vcc_lo, 0, v19
v_cndmask_b32_e64 v3, 0, 1, vcc_lo
v_cndmask_b32_e64 v6, 1, 2, vcc_lo
s_waitcnt vmcnt(6)
v_cmp_ne_u32_e32 vcc_lo, 0, v12
v_cndmask_b32_e64 v10, 0, 1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v11
v_cndmask_b32_e32 v3, v6, v3, vcc_lo
s_waitcnt vmcnt(4)
v_cmp_ne_u32_e32 vcc_lo, 0, v8
v_cndmask_b32_e64 v6, 0, 1, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v7
v_add_co_ci_u32_e32 v3, vcc_lo, v3, v10, vcc_lo
s_waitcnt vmcnt(3)
v_cmp_ne_u32_e32 vcc_lo, 0, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, v3, v6, vcc_lo
s_waitcnt vmcnt(2)
v_cmp_ne_u32_e32 vcc_lo, 0, v5
v_cndmask_b32_e64 v5, 0, 1, vcc_lo
s_waitcnt vmcnt(1)
v_cmp_ne_u32_e32 vcc_lo, 0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, v3, v5, vcc_lo
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 1, v2
v_and_b32_e32 v3, -2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_ne_u32_e64 s2, 2, v3
v_mov_b32_e32 v3, 1
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v2
v_cmp_eq_u32_e32 vcc_lo, 6, v4
v_cmp_eq_u32_e64 s2, 3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, vcc_lo, s2
v_cndmask_b32_e64 v3, 0, 1, s2
s_or_b32 exec_lo, exec_lo, s4
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15deviceIterationPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15deviceIterationPiS_ii, .Lfunc_end0-_Z15deviceIterationPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z20deviceIterationNotIfPiS_ii
.globl _Z20deviceIterationNotIfPiS_ii
.p2align 8
.type _Z20deviceIterationNotIfPiS_ii,@function
_Z20deviceIterationNotIfPiS_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mul_i32 s4, s3, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s4, v1
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB1_6
s_ashr_i32 s4, s2, 31
v_ashrrev_i32_e32 v3, 31, v1
s_add_i32 s5, s2, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s5, s5, s4
v_add_nc_u32_e32 v4, v1, v3
v_cvt_f32_u32_e32 v0, s5
s_sub_i32 s6, 0, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v4, v3
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v3, s4, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s6, v0
s_ashr_i32 s6, s3, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s3, s6
s_xor_b32 s6, s7, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_u32_e32 v6, s6
v_mul_hi_u32 v2, v0, v2
s_sub_i32 s4, 0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
v_mul_hi_u32 v2, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v2, s5
v_sub_nc_u32_e32 v4, v4, v5
v_add_nc_u32_e32 v5, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s5, v4
v_subrev_nc_u32_e32 v7, s5, v4
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
v_rcp_iflag_f32_e32 v5, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v4, v7, vcc_lo
v_add_nc_u32_e32 v6, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_le_u32_e32 vcc_lo, s5, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v5
v_cvt_u32_f32_e32 v4, v4
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v3
v_sub_nc_u32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, s4, v4
v_add3_u32 v5, s3, -1, v2
v_mul_lo_u32 v8, v2, s2
v_add_nc_u32_e32 v2, 1, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_hi_u32 v3, v4, v3
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v7, 31, v2
v_sub_nc_u32_e32 v9, v1, v8
v_add_nc_u32_e32 v5, v5, v6
v_add_nc_u32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v2, v2, v7
v_add_nc_u32_e32 v4, 1, v9
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_xor_b32_e32 v5, v5, v6
v_add3_u32 v10, s2, -1, v9
v_xor_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v11, 31, v4
v_mul_hi_u32 v13, v5, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v12, 31, v10
v_mul_hi_u32 v3, v2, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v4, v4, v11
v_add_nc_u32_e32 v10, v10, v12
v_mul_lo_u32 v13, v13, s6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_xor_b32_e32 v4, v4, v11
v_mul_lo_u32 v3, v3, s6
v_xor_b32_e32 v10, v10, v12
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v5, v5, v13
v_sub_nc_u32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s6, v5
v_cmp_le_u32_e32 vcc_lo, s6, v5
v_cndmask_b32_e32 v3, v5, v3, vcc_lo
v_mul_hi_u32 v14, v4, v0
v_mul_hi_u32 v0, v10, v0
v_cmp_le_u32_e32 vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_subrev_nc_u32_e32 v5, s6, v3
v_mul_lo_u32 v13, v14, s5
v_subrev_nc_u32_e32 v14, s6, v2
v_mul_lo_u32 v0, v0, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v2, v2, v14, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s6, v3
v_sub_nc_u32_e32 v4, v4, v13
v_sub_nc_u32_e32 v0, v10, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_subrev_nc_u32_e32 v10, s6, v2
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s6, v2
v_subrev_nc_u32_e32 v13, s5, v4
v_subrev_nc_u32_e32 v14, s5, v0
v_xor_b32_e32 v3, v3, v6
v_cndmask_b32_e32 v2, v2, v10, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s5, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v3, v3, v6
v_xor_b32_e32 v2, v2, v7
v_cndmask_b32_e32 v4, v4, v13, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s5, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v2, v2, v7
v_subrev_nc_u32_e32 v5, s5, v4
v_cndmask_b32_e32 v0, v0, v14, vcc_lo
v_mul_lo_u32 v14, v3, s2
v_cmp_le_u32_e32 vcc_lo, s5, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
v_add_nc_u32_e32 v5, v14, v9
v_subrev_nc_u32_e32 v10, s5, v0
v_cmp_le_u32_e32 vcc_lo, s5, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v6, 31, v5
v_cndmask_b32_e32 v0, v0, v10, vcc_lo
v_mul_lo_u32 v10, v2, s2
s_load_b64 s[2:3], s[0:1], 0x8
v_xor_b32_e32 v2, v4, v11
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_xor_b32_e32 v0, v0, v12
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, v10, v9
v_sub_nc_u32_e32 v0, v0, v12
v_sub_nc_u32_e32 v12, v2, v11
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v4, 31, v3
v_add_nc_u32_e32 v7, v0, v8
s_delay_alu instid0(VALU_DEP_4)
v_add_nc_u32_e32 v9, v12, v8
v_add_nc_u32_e32 v11, v0, v10
v_add_nc_u32_e32 v13, v10, v12
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_ashrrev_i32_e32 v8, 31, v7
v_ashrrev_i32_e32 v10, 31, v9
v_add_nc_u32_e32 v17, v12, v14
v_ashrrev_i32_e32 v12, 31, v11
v_add_nc_u32_e32 v15, v0, v14
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
v_lshlrev_b64 v[9:10], 2, v[9:10]
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_clause 0x1
global_load_b32 v19, v[3:4], off
global_load_b32 v20, v[5:6], off
v_add_co_u32 v3, vcc_lo, s2, v7
v_ashrrev_i32_e32 v16, 31, v15
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v8, vcc_lo
v_lshlrev_b64 v[13:14], 2, v[13:14]
v_add_co_u32 v5, vcc_lo, s2, v9
v_ashrrev_i32_e32 v18, 31, v17
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v10, vcc_lo
v_lshlrev_b64 v[15:16], 2, v[15:16]
v_add_co_u32 v7, vcc_lo, s2, v11
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v12, vcc_lo
v_lshlrev_b64 v[17:18], 2, v[17:18]
v_add_co_u32 v9, vcc_lo, s2, v13
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v14, vcc_lo
s_clause 0x1
global_load_b32 v13, v[3:4], off
global_load_b32 v5, v[5:6], off
v_add_co_u32 v11, vcc_lo, s2, v15
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v16, vcc_lo
v_add_co_u32 v3, vcc_lo, s2, v17
s_clause 0x1
global_load_b32 v6, v[7:8], off
global_load_b32 v7, v[9:10], off
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v18, vcc_lo
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_clause 0x1
global_load_b32 v8, v[11:12], off
global_load_b32 v9, v[3:4], off
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(7)
v_add_nc_u32_e32 v2, v20, v19
s_waitcnt vmcnt(5)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add3_u32 v2, v2, v13, v5
s_waitcnt vmcnt(3)
v_add3_u32 v2, v2, v6, v7
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v3, v2, v8, v9
v_and_b32_e32 v2, -2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cmp_ne_u32_e64 s2, 2, v2
v_mov_b32_e32 v2, 1
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 1, v4
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_5
v_mov_b32_e32 v2, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v4
v_cmp_eq_u32_e32 vcc_lo, 3, v3
v_cmp_eq_u32_e64 s2, 6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, vcc_lo, s2
v_cndmask_b32_e64 v2, 0, 1, s2
s_or_b32 exec_lo, exec_lo, s4
.LBB1_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB1_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20deviceIterationNotIfPiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z20deviceIterationNotIfPiS_ii, .Lfunc_end1-_Z20deviceIterationNotIfPiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15deviceIterationPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15deviceIterationPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20deviceIterationNotIfPiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20deviceIterationNotIfPiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <hip/hip_runtime_api.h>
#include <iostream>
// CUDA kernel. Each thread takes care of one element of c
__global__ void deviceIteration(int *c, int *a, int H, int W)
{
// Tomamos el indice y lugar donde se calculará si vive o no.
const int k = blockIdx.x * blockDim.x + threadIdx.x;
// En caso de pasarnos no lo consideramos.
if (k < W*H) {
// Calculamos la posición en la matriz.
const int i = k / H;
const int j = k % H;
int sum = 0;
// Ahora obtenemos los indices de los vecinos.
const int left = (i + W - 1) % W;
const int right = (i + 1) % W;
const int down = (j + 1) % H;
const int up = (j + H - 1) % H;
// Calculamos la suma de los valores vecinos.
// left
if (a[right * H + j])
sum++;
// right
if (a[left * H + j])
sum++;
// up
if (a[i * H + up])
sum++;
// down
if (a[i * H + down])
sum++;
// upright
if (a[right * H + up])
sum++;
// downright
if (a[right * H + down])
sum++;
// upleft
if (a[left * H + up])
sum++;
// downleft
if (a[left * H + down])
sum++;
int value = a[k];
int result = 0;
// Guardamos el resultado obtenido, si esta vivo o no
if ((value == 1 && (sum == 2 || sum == 3)) || (value == 0 && (sum == 3 || sum == 6))) {
result = 1;
}
// Lo dejamos en la matriz final.
c[k] = result;
}
}
// CUDA kernel. Each thread takes care of one element of c
__global__ void deviceIterationNotIf(int *c, int *a, int H, int W)
{
// Tomamos el indice y lugar donde se calculará si vive o no.
const int k = blockIdx.x * blockDim.x + threadIdx.x;
// En caso de pasarnos no lo consideramos.
if (k < W*H) {
// Calculamos la posición en la matriz.
const int i = k / H;
const int j = k % H;
int sum = 0;
// Ahora obtenemos los indices de los vecinos.
const int left = (i + W - 1) % W;
const int right = (i + 1) % W;
const int down = (j + 1) % H;
const int up = (j + H - 1) % H;
// Calculamos la suma de los valores vecinos.
// left
sum += a[right * H + j];
// right
sum += a[left * H + j];
// up
sum += a[i * H + up];
// down
sum += a[i * H + down];
// upright
sum += a[right * H + up];
// downright
sum += a[right * H + down];
// upleft
sum += a[left * H + up];
// downleft
sum += a[left * H + down];
int value = a[k];
// Guardamos el resultado obtenido, si esta vivo o no
c[k] = (value == 1 && (sum == 2 || sum == 3)) || (value == 0 && (sum == 3 || sum == 6));
}
}
void run(int* a, int W, int H){
//Host output vector
int *h_c;
// Device input vectors
int *d_a;
//Device output vector
int *d_c;
// Size, in bytes, of each vector
size_t bytes = W*H*sizeof(int);
// Allocate memory for each vector on host
h_c = (int*)malloc(bytes);
// Allocate memory for each vector on GPU
hipMalloc((void **) &d_a, bytes);
hipMalloc((void **) &d_c, bytes);
// Copy host vectors to device
hipMemcpy(d_a, a, bytes, hipMemcpyHostToDevice);
int blockSize, gridSize, n;
// Tamaño de la matriz.
n = H*W;
// Tamaño del bloque. Elegir entre 32 y 31.
//blockSize = 32;
blockSize = 8;
// Number of thread blocks in grid
gridSize = (int)ceil((float)n/blockSize);
// Execute the kernel
deviceIterationNotIf<<< gridSize, blockSize >>>(d_c, d_a, H, W);
// Copy array back to host
hipMemcpy( h_c, d_c, bytes, hipMemcpyDeviceToHost );
// Sum up vector c and print result divided by n, this should equal 1 within error
int i,j;
for(i=0; i<W; i++) {
for(j=0; j<H; j++) {
a[i*H + j] = h_c[i*H + j];
}
}
// Release device memory
hipFree(d_a);
hipFree(d_c);
// Release host memory
free(h_c);
} | .text
.file "parallelCuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z30__device_stub__deviceIterationPiS_ii # -- Begin function _Z30__device_stub__deviceIterationPiS_ii
.p2align 4, 0x90
.type _Z30__device_stub__deviceIterationPiS_ii,@function
_Z30__device_stub__deviceIterationPiS_ii: # @_Z30__device_stub__deviceIterationPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15deviceIterationPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__deviceIterationPiS_ii, .Lfunc_end0-_Z30__device_stub__deviceIterationPiS_ii
.cfi_endproc
# -- End function
.globl _Z35__device_stub__deviceIterationNotIfPiS_ii # -- Begin function _Z35__device_stub__deviceIterationNotIfPiS_ii
.p2align 4, 0x90
.type _Z35__device_stub__deviceIterationNotIfPiS_ii,@function
_Z35__device_stub__deviceIterationNotIfPiS_ii: # @_Z35__device_stub__deviceIterationNotIfPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20deviceIterationNotIfPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z35__device_stub__deviceIterationNotIfPiS_ii, .Lfunc_end1-_Z35__device_stub__deviceIterationNotIfPiS_ii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z3runPiii
.LCPI2_0:
.long 0x3e000000 # float 0.125
.text
.globl _Z3runPiii
.p2align 4, 0x90
.type _Z3runPiii,@function
_Z3runPiii: # @_Z3runPiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movl %esi, %r15d
movq %rdi, %r14
movl %edx, %eax
imull %esi, %eax
movslq %eax, %r13
leaq (,%r13,4), %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
cvtsi2ss %r13d, %xmm0
mulss .LCPI2_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $8, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %ebp, 28(%rsp)
movl %r15d, 24(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20deviceIterationNotIfPiS_ii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
testl %r15d, %r15d
jle .LBB2_7
# %bb.3: # %.preheader.lr.ph
movl %ebp, %r12d
shlq $2, %r12
movl %r15d, %r15d
xorl %r13d, %r13d
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_6: # %._crit_edge
# in Loop: Header=BB2_4 Depth=1
addl %ebp, %r13d
decq %r15
je .LBB2_7
.LBB2_4: # %.preheader
# =>This Inner Loop Header: Depth=1
testl %ebp, %ebp
jle .LBB2_6
# %bb.5: # %.lr.ph
# in Loop: Header=BB2_4 Depth=1
movl %r13d, %eax
leaq (%rbx,%rax,4), %rsi
leaq (%r14,%rax,4), %rdi
movq %r12, %rdx
callq memcpy@PLT
jmp .LBB2_6
.LBB2_7: # %._crit_edge40
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z3runPiii, .Lfunc_end2-_Z3runPiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15deviceIterationPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20deviceIterationNotIfPiS_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15deviceIterationPiS_ii,@object # @_Z15deviceIterationPiS_ii
.section .rodata,"a",@progbits
.globl _Z15deviceIterationPiS_ii
.p2align 3, 0x0
_Z15deviceIterationPiS_ii:
.quad _Z30__device_stub__deviceIterationPiS_ii
.size _Z15deviceIterationPiS_ii, 8
.type _Z20deviceIterationNotIfPiS_ii,@object # @_Z20deviceIterationNotIfPiS_ii
.globl _Z20deviceIterationNotIfPiS_ii
.p2align 3, 0x0
_Z20deviceIterationNotIfPiS_ii:
.quad _Z35__device_stub__deviceIterationNotIfPiS_ii
.size _Z20deviceIterationNotIfPiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15deviceIterationPiS_ii"
.size .L__unnamed_1, 26
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z20deviceIterationNotIfPiS_ii"
.size .L__unnamed_2, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__deviceIterationPiS_ii
.addrsig_sym _Z35__device_stub__deviceIterationNotIfPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15deviceIterationPiS_ii
.addrsig_sym _Z20deviceIterationNotIfPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011b632_00000000-6_parallelCuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z15deviceIterationPiS_iiPiS_ii
.type _Z39__device_stub__Z15deviceIterationPiS_iiPiS_ii, @function
_Z39__device_stub__Z15deviceIterationPiS_iiPiS_ii:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15deviceIterationPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z39__device_stub__Z15deviceIterationPiS_iiPiS_ii, .-_Z39__device_stub__Z15deviceIterationPiS_iiPiS_ii
.globl _Z15deviceIterationPiS_ii
.type _Z15deviceIterationPiS_ii, @function
_Z15deviceIterationPiS_ii:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15deviceIterationPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z15deviceIterationPiS_ii, .-_Z15deviceIterationPiS_ii
.globl _Z44__device_stub__Z20deviceIterationNotIfPiS_iiPiS_ii
.type _Z44__device_stub__Z20deviceIterationNotIfPiS_iiPiS_ii, @function
_Z44__device_stub__Z20deviceIterationNotIfPiS_iiPiS_ii:
.LFB3696:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20deviceIterationNotIfPiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z44__device_stub__Z20deviceIterationNotIfPiS_iiPiS_ii, .-_Z44__device_stub__Z20deviceIterationNotIfPiS_iiPiS_ii
.globl _Z20deviceIterationNotIfPiS_ii
.type _Z20deviceIterationNotIfPiS_ii, @function
_Z20deviceIterationNotIfPiS_ii:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z20deviceIterationNotIfPiS_iiPiS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z20deviceIterationNotIfPiS_ii, .-_Z20deviceIterationNotIfPiS_ii
.globl _Z3runPiii
.type _Z3runPiii, @function
_Z3runPiii:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %rbp
movl %esi, %r13d
movl %edx, %r12d
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl %esi, %r15d
imull %edx, %r15d
movslq %r15d, %r14
salq $2, %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbx
movq %rsp, %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %r15d, %xmm0
mulss .LC0(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC4(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC1(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L20
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC3(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L20:
movl $8, 28(%rsp)
movl $1, 32(%rsp)
cvttss2sil %xmm3, %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L21:
movl $2, %ecx
movq %r14, %rdx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
testl %r13d, %r13d
jle .L22
movl $0, %edi
movl $0, %esi
movslq %r12d, %r8
jmp .L23
.L30:
movl %r13d, %ecx
movl %r12d, %edx
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z44__device_stub__Z20deviceIterationNotIfPiS_iiPiS_ii
jmp .L21
.L25:
movslq %edi, %rcx
leaq 0(,%rcx,4), %rax
addq %r8, %rcx
salq $2, %rcx
.L24:
movl (%rbx,%rax), %edx
movl %edx, 0(%rbp,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L24
.L26:
addl $1, %esi
addl %r12d, %edi
cmpl %esi, %r13d
je .L22
.L23:
testl %r12d, %r12d
jg .L25
jmp .L26
.L22:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z3runPiii, .-_Z3runPiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "_Z20deviceIterationNotIfPiS_ii"
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "_Z15deviceIterationPiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z20deviceIterationNotIfPiS_ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z15deviceIterationPiS_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1040187392
.align 4
.LC1:
.long 1258291200
.align 4
.LC3:
.long 1065353216
.align 4
.LC4:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "parallelCuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z30__device_stub__deviceIterationPiS_ii # -- Begin function _Z30__device_stub__deviceIterationPiS_ii
.p2align 4, 0x90
.type _Z30__device_stub__deviceIterationPiS_ii,@function
_Z30__device_stub__deviceIterationPiS_ii: # @_Z30__device_stub__deviceIterationPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15deviceIterationPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z30__device_stub__deviceIterationPiS_ii, .Lfunc_end0-_Z30__device_stub__deviceIterationPiS_ii
.cfi_endproc
# -- End function
.globl _Z35__device_stub__deviceIterationNotIfPiS_ii # -- Begin function _Z35__device_stub__deviceIterationNotIfPiS_ii
.p2align 4, 0x90
.type _Z35__device_stub__deviceIterationNotIfPiS_ii,@function
_Z35__device_stub__deviceIterationNotIfPiS_ii: # @_Z35__device_stub__deviceIterationNotIfPiS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20deviceIterationNotIfPiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z35__device_stub__deviceIterationNotIfPiS_ii, .Lfunc_end1-_Z35__device_stub__deviceIterationNotIfPiS_ii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z3runPiii
.LCPI2_0:
.long 0x3e000000 # float 0.125
.text
.globl _Z3runPiii
.p2align 4, 0x90
.type _Z3runPiii,@function
_Z3runPiii: # @_Z3runPiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movl %esi, %r15d
movq %rdi, %r14
movl %edx, %eax
imull %esi, %eax
movslq %eax, %r13
leaq (,%r13,4), %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
cvtsi2ss %r13d, %xmm0
mulss .LCPI2_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $8, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %ebp, 28(%rsp)
movl %r15d, 24(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20deviceIterationNotIfPiS_ii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
testl %r15d, %r15d
jle .LBB2_7
# %bb.3: # %.preheader.lr.ph
movl %ebp, %r12d
shlq $2, %r12
movl %r15d, %r15d
xorl %r13d, %r13d
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_6: # %._crit_edge
# in Loop: Header=BB2_4 Depth=1
addl %ebp, %r13d
decq %r15
je .LBB2_7
.LBB2_4: # %.preheader
# =>This Inner Loop Header: Depth=1
testl %ebp, %ebp
jle .LBB2_6
# %bb.5: # %.lr.ph
# in Loop: Header=BB2_4 Depth=1
movl %r13d, %eax
leaq (%rbx,%rax,4), %rsi
leaq (%r14,%rax,4), %rdi
movq %r12, %rdx
callq memcpy@PLT
jmp .LBB2_6
.LBB2_7: # %._crit_edge40
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z3runPiii, .Lfunc_end2-_Z3runPiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15deviceIterationPiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20deviceIterationNotIfPiS_ii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15deviceIterationPiS_ii,@object # @_Z15deviceIterationPiS_ii
.section .rodata,"a",@progbits
.globl _Z15deviceIterationPiS_ii
.p2align 3, 0x0
_Z15deviceIterationPiS_ii:
.quad _Z30__device_stub__deviceIterationPiS_ii
.size _Z15deviceIterationPiS_ii, 8
.type _Z20deviceIterationNotIfPiS_ii,@object # @_Z20deviceIterationNotIfPiS_ii
.globl _Z20deviceIterationNotIfPiS_ii
.p2align 3, 0x0
_Z20deviceIterationNotIfPiS_ii:
.quad _Z35__device_stub__deviceIterationNotIfPiS_ii
.size _Z20deviceIterationNotIfPiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15deviceIterationPiS_ii"
.size .L__unnamed_1, 26
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z20deviceIterationNotIfPiS_ii"
.size .L__unnamed_2, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__deviceIterationPiS_ii
.addrsig_sym _Z35__device_stub__deviceIterationNotIfPiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15deviceIterationPiS_ii
.addrsig_sym _Z20deviceIterationNotIfPiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void addVector(int *d1_in, int *d2_in, int *d_out, int n){
int ind = blockDim.x*blockIdx.x + threadIdx.x;
if(ind<n){
d_out[ind] = d1_in[ind]+d2_in[ind];
}
} | code for sm_80
Function : _Z9addVectorPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void addVector(int *d1_in, int *d2_in, int *d_out, int n){
int ind = blockDim.x*blockIdx.x + threadIdx.x;
if(ind<n){
d_out[ind] = d1_in[ind]+d2_in[ind];
}
} | .file "tmpxft_00149ee2_00000000-6_addVector.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9addVectorPiS_S_iPiS_S_i
.type _Z33__device_stub__Z9addVectorPiS_S_iPiS_S_i, @function
_Z33__device_stub__Z9addVectorPiS_S_iPiS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addVectorPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z9addVectorPiS_S_iPiS_S_i, .-_Z33__device_stub__Z9addVectorPiS_S_iPiS_S_i
.globl _Z9addVectorPiS_S_i
.type _Z9addVectorPiS_S_i, @function
_Z9addVectorPiS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9addVectorPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9addVectorPiS_S_i, .-_Z9addVectorPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9addVectorPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addVectorPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void addVector(int *d1_in, int *d2_in, int *d_out, int n){
int ind = blockDim.x*blockIdx.x + threadIdx.x;
if(ind<n){
d_out[ind] = d1_in[ind]+d2_in[ind];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void addVector(int *d1_in, int *d2_in, int *d_out, int n){
int ind = blockDim.x*blockIdx.x + threadIdx.x;
if(ind<n){
d_out[ind] = d1_in[ind]+d2_in[ind];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void addVector(int *d1_in, int *d2_in, int *d_out, int n){
int ind = blockDim.x*blockIdx.x + threadIdx.x;
if(ind<n){
d_out[ind] = d1_in[ind]+d2_in[ind];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addVectorPiS_S_i
.globl _Z9addVectorPiS_S_i
.p2align 8
.type _Z9addVectorPiS_S_i,@function
_Z9addVectorPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addVectorPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addVectorPiS_S_i, .Lfunc_end0-_Z9addVectorPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addVectorPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9addVectorPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void addVector(int *d1_in, int *d2_in, int *d_out, int n){
int ind = blockDim.x*blockIdx.x + threadIdx.x;
if(ind<n){
d_out[ind] = d1_in[ind]+d2_in[ind];
}
} | .text
.file "addVector.hip"
.globl _Z24__device_stub__addVectorPiS_S_i # -- Begin function _Z24__device_stub__addVectorPiS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__addVectorPiS_S_i,@function
_Z24__device_stub__addVectorPiS_S_i: # @_Z24__device_stub__addVectorPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addVectorPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__addVectorPiS_S_i, .Lfunc_end0-_Z24__device_stub__addVectorPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addVectorPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addVectorPiS_S_i,@object # @_Z9addVectorPiS_S_i
.section .rodata,"a",@progbits
.globl _Z9addVectorPiS_S_i
.p2align 3, 0x0
_Z9addVectorPiS_S_i:
.quad _Z24__device_stub__addVectorPiS_S_i
.size _Z9addVectorPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9addVectorPiS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addVectorPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addVectorPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9addVectorPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addVectorPiS_S_i
.globl _Z9addVectorPiS_S_i
.p2align 8
.type _Z9addVectorPiS_S_i,@function
_Z9addVectorPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addVectorPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addVectorPiS_S_i, .Lfunc_end0-_Z9addVectorPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addVectorPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9addVectorPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00149ee2_00000000-6_addVector.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9addVectorPiS_S_iPiS_S_i
.type _Z33__device_stub__Z9addVectorPiS_S_iPiS_S_i, @function
_Z33__device_stub__Z9addVectorPiS_S_iPiS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addVectorPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z9addVectorPiS_S_iPiS_S_i, .-_Z33__device_stub__Z9addVectorPiS_S_iPiS_S_i
.globl _Z9addVectorPiS_S_i
.type _Z9addVectorPiS_S_i, @function
_Z9addVectorPiS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9addVectorPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9addVectorPiS_S_i, .-_Z9addVectorPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9addVectorPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addVectorPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "addVector.hip"
.globl _Z24__device_stub__addVectorPiS_S_i # -- Begin function _Z24__device_stub__addVectorPiS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__addVectorPiS_S_i,@function
_Z24__device_stub__addVectorPiS_S_i: # @_Z24__device_stub__addVectorPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addVectorPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__addVectorPiS_S_i, .Lfunc_end0-_Z24__device_stub__addVectorPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addVectorPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addVectorPiS_S_i,@object # @_Z9addVectorPiS_S_i
.section .rodata,"a",@progbits
.globl _Z9addVectorPiS_S_i
.p2align 3, 0x0
_Z9addVectorPiS_S_i:
.quad _Z24__device_stub__addVectorPiS_S_i
.size _Z9addVectorPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9addVectorPiS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addVectorPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addVectorPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // ###
// ###
// ### Practical Course: GPU Programming in Computer Vision
// ###
// ###
// ### Technical University Munich, Computer Vision Group
// ### Summer Semester 2017, September 11 - October 9
// ###
#include <cuda_runtime.h>
#include <iostream>
using namespace std;
// cuda error checking
#define CUDA_CHECK cuda_check(__FILE__,__LINE__)
void cuda_check(string file, int line)
{
cudaError_t e = cudaGetLastError();
if (e != cudaSuccess)
{
cout << endl << file << ", line " << line << ": " << cudaGetErrorString(e) << " (" << e << ")" << endl;
exit(1);
}
}
__device__ float square(float a) {return a*a;}
__global__ void g_square(float*a, int n)
{
int ind = threadIdx.x + blockDim.x * blockIdx.x;
if(ind<n) a[ind]=square(a[ind]);
}
int main(int argc, char **argv)
{
// alloc and init input arrays on host (CPU)
int n = 10;
float *a = new float[n];
for(int i=0; i<n; i++) a[i] = i;
// CPU computation
for(int i=0; i<n; i++)
{
float val = a[i];
val = val*val;
a[i] = val;
}
// print result
cout << "CPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << endl;
cout << endl;
// GPU computation
// reinit data
for(int i=0; i<n; i++) a[i] = i;
// ###
// ### TODO: Implement the "square array" operation on the GPU and store the result in "a"
// ###
// ### Notes:
// ### 1. Remember to free all GPU arrays after the computation
// ### 2. Always use the macro CUDA_CHECK after each CUDA call, e.g. "cudaMalloc(...); CUDA_CHECK;"
// ### For convenience this macro is defined directly in this file, later we will only include "helper.h"
dim3 block = dim3(10,1,1);
dim3 grid = dim3((n+block.x-1)/block.x,1,1);
float *d_a;
cudaMalloc(&d_a,n*sizeof(float));
CUDA_CHECK;
cudaMemcpy( d_a, a, n * sizeof(float), cudaMemcpyHostToDevice );CUDA_CHECK;
g_square<<<grid,block>>>(d_a,n);
cudaMemcpy( a, d_a, n * sizeof(float), cudaMemcpyDeviceToHost );CUDA_CHECK;
cudaFree(d_a);CUDA_CHECK;
// print result
cout << "GPU:" << endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << endl;
cout << endl;
// free CPU arrays
delete[] a;
} | code for sm_80
Function : _Z8g_squarePfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FMUL R5, R0, R0 ; /* 0x0000000000057220 */
/* 0x004fca0000400000 */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // ###
// ###
// ### Practical Course: GPU Programming in Computer Vision
// ###
// ###
// ### Technical University Munich, Computer Vision Group
// ### Summer Semester 2017, September 11 - October 9
// ###
#include <cuda_runtime.h>
#include <iostream>
using namespace std;
// cuda error checking
#define CUDA_CHECK cuda_check(__FILE__,__LINE__)
void cuda_check(string file, int line)
{
cudaError_t e = cudaGetLastError();
if (e != cudaSuccess)
{
cout << endl << file << ", line " << line << ": " << cudaGetErrorString(e) << " (" << e << ")" << endl;
exit(1);
}
}
__device__ float square(float a) {return a*a;}
__global__ void g_square(float*a, int n)
{
int ind = threadIdx.x + blockDim.x * blockIdx.x;
if(ind<n) a[ind]=square(a[ind]);
}
int main(int argc, char **argv)
{
// alloc and init input arrays on host (CPU)
int n = 10;
float *a = new float[n];
for(int i=0; i<n; i++) a[i] = i;
// CPU computation
for(int i=0; i<n; i++)
{
float val = a[i];
val = val*val;
a[i] = val;
}
// print result
cout << "CPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << endl;
cout << endl;
// GPU computation
// reinit data
for(int i=0; i<n; i++) a[i] = i;
// ###
// ### TODO: Implement the "square array" operation on the GPU and store the result in "a"
// ###
// ### Notes:
// ### 1. Remember to free all GPU arrays after the computation
// ### 2. Always use the macro CUDA_CHECK after each CUDA call, e.g. "cudaMalloc(...); CUDA_CHECK;"
// ### For convenience this macro is defined directly in this file, later we will only include "helper.h"
dim3 block = dim3(10,1,1);
dim3 grid = dim3((n+block.x-1)/block.x,1,1);
float *d_a;
cudaMalloc(&d_a,n*sizeof(float));
CUDA_CHECK;
cudaMemcpy( d_a, a, n * sizeof(float), cudaMemcpyHostToDevice );CUDA_CHECK;
g_square<<<grid,block>>>(d_a,n);
cudaMemcpy( a, d_a, n * sizeof(float), cudaMemcpyDeviceToHost );CUDA_CHECK;
cudaFree(d_a);CUDA_CHECK;
// print result
cout << "GPU:" << endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << endl;
cout << endl;
// free CPU arrays
delete[] a;
} | .file "tmpxft_000de3f6_00000000-6_squareArray.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string ", line "
.LC1:
.string ": "
.LC2:
.string " ("
.LC3:
.string ")"
.text
.globl _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.type _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi, @function
_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbp
movl %esi, %r12d
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %ebx
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
movq 8(%rbp), %rdx
movq 0(%rbp), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r12d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi, .-_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.globl _Z6squaref
.type _Z6squaref, @function
_Z6squaref:
.LFB3670:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size _Z6squaref, .-_Z6squaref
.globl _Z28__device_stub__Z8g_squarePfiPfi
.type _Z28__device_stub__Z8g_squarePfiPfi, @function
_Z28__device_stub__Z8g_squarePfiPfi:
.LFB3696:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8g_squarePfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z28__device_stub__Z8g_squarePfiPfi, .-_Z28__device_stub__Z8g_squarePfiPfi
.globl _Z8g_squarePfi
.type _Z8g_squarePfi, @function
_Z8g_squarePfi:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z8g_squarePfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z8g_squarePfi, .-_Z8g_squarePfi
.section .rodata.str1.1
.LC4:
.string "_Z8g_squarePfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z8g_squarePfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "basic_string: construction from null is not valid"
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC5IS3_EEPKcRKS3_,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_:
.LFB4006:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 16(%rdi), %r12
movq %r12, (%rdi)
testq %rsi, %rsi
je .L28
movq %rdi, %rbx
movq %rsi, %r13
movq %rsi, %rdi
call strlen@PLT
movq %rax, %rbp
movq %rax, (%rsp)
cmpq $15, %rax
ja .L29
cmpq $1, %rax
jne .L24
movzbl 0(%r13), %eax
movb %al, 16(%rbx)
.L25:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L31
leaq .LC5(%rip), %rdi
call _ZSt19__throw_logic_errorPKc@PLT
.L31:
call __stack_chk_fail@PLT
.L29:
movq %rsp, %rsi
movl $0, %edx
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %r12
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L23:
movq %rbp, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memcpy@PLT
jmp .L25
.L24:
testq %rax, %rax
je .L25
jmp .L23
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4006:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.set _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.section .rodata.str1.1
.LC6:
.string "CPU:"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "/home/ubuntu/Datasets/stackv2/train-structured/a-parida12/GPUCuda/master/Day1/CUDA_kernel/squareArray.cu"
.section .rodata.str1.1
.LC8:
.string "GPU:"
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3671
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $40, %edi
.LEHB0:
call _Znam@PLT
movq %rax, %rbp
movl $0, %eax
.L33:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L33
movq %rbp, %rax
leaq 40(%rbp), %rdx
.L34:
movss (%rax), %xmm0
mulss %xmm0, %xmm0
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L34
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %r12d
leaq _ZSt4cout(%rip), %r14
leaq .LC1(%rip), %r13
jmp .L39
.L69:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L67
call _ZSt16__throw_bad_castv@PLT
.L67:
call __stack_chk_fail@PLT
.L37:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
.L38:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %r12
cmpq $10, %r12
je .L68
.L39:
movl %r12d, %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $2, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%r12,4), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .L69
cmpb $0, 56(%r15)
je .L37
movzbl 67(%r15), %esi
jmp .L38
.L68:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %eax
.L40:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L40
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 15(%rsp), %rdx
leaq 48(%rsp), %rbx
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE0:
movl $72, %esi
movq %rbx, %rdi
.LEHB1:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE1:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $1, %ecx
movl $40, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
.LEHB2:
call cudaMemcpy@PLT
leaq 15(%rsp), %rdx
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE2:
movl $75, %esi
movq %rbx, %rdi
.LEHB3:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE3:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $10, 24(%rsp)
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
.LEHB4:
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L70
.L41:
movl $2, %ecx
movl $40, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq 15(%rsp), %rdx
leaq 48(%rsp), %rbx
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE4:
movl $79, %esi
movq %rbx, %rdi
.LEHB5:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE5:
jmp .L71
.L70:
movl $10, %esi
movq 16(%rsp), %rdi
.LEHB6:
call _Z28__device_stub__Z8g_squarePfiPfi
jmp .L41
.L71:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq 15(%rsp), %rdx
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE6:
movl $80, %esi
movq %rbx, %rdi
.LEHB7:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE7:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB8:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %r12d
leaq _ZSt4cout(%rip), %r14
leaq .LC1(%rip), %r13
jmp .L46
.L74:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L72
call _ZSt16__throw_bad_castv@PLT
.L72:
call __stack_chk_fail@PLT
.L44:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
.L45:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %r12
cmpq $10, %r12
je .L73
.L46:
movl %r12d, %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $2, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%r12,4), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .L74
cmpb $0, 56(%r15)
je .L44
movzbl 67(%r15), %esi
jmp .L45
.L73:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L75
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L56:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
je .L48
call __stack_chk_fail@PLT
.L48:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L57:
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
je .L50
call __stack_chk_fail@PLT
.L50:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L58:
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
je .L52
call __stack_chk_fail@PLT
.L52:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L59:
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
je .L54
call __stack_chk_fail@PLT
.L54:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE8:
.L75:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3671:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3671-.LLSDACSB3671
.LLSDACSB3671:
.uleb128 .LEHB0-.LFB3671
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3671
.uleb128 .LEHE1-.LEHB1
.uleb128 .L56-.LFB3671
.uleb128 0
.uleb128 .LEHB2-.LFB3671
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB3671
.uleb128 .LEHE3-.LEHB3
.uleb128 .L57-.LFB3671
.uleb128 0
.uleb128 .LEHB4-.LFB3671
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.uleb128 .LEHB5-.LFB3671
.uleb128 .LEHE5-.LEHB5
.uleb128 .L58-.LFB3671
.uleb128 0
.uleb128 .LEHB6-.LFB3671
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.uleb128 .LEHB7-.LFB3671
.uleb128 .LEHE7-.LEHB7
.uleb128 .L59-.LFB3671
.uleb128 0
.uleb128 .LEHB8-.LFB3671
.uleb128 .LEHE8-.LEHB8
.uleb128 0
.uleb128 0
.LLSDACSE3671:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // ###
// ###
// ### Practical Course: GPU Programming in Computer Vision
// ###
// ###
// ### Technical University Munich, Computer Vision Group
// ### Summer Semester 2017, September 11 - October 9
// ###
#include <cuda_runtime.h>
#include <iostream>
using namespace std;
// cuda error checking
#define CUDA_CHECK cuda_check(__FILE__,__LINE__)
void cuda_check(string file, int line)
{
cudaError_t e = cudaGetLastError();
if (e != cudaSuccess)
{
cout << endl << file << ", line " << line << ": " << cudaGetErrorString(e) << " (" << e << ")" << endl;
exit(1);
}
}
__device__ float square(float a) {return a*a;}
__global__ void g_square(float*a, int n)
{
int ind = threadIdx.x + blockDim.x * blockIdx.x;
if(ind<n) a[ind]=square(a[ind]);
}
int main(int argc, char **argv)
{
// alloc and init input arrays on host (CPU)
int n = 10;
float *a = new float[n];
for(int i=0; i<n; i++) a[i] = i;
// CPU computation
for(int i=0; i<n; i++)
{
float val = a[i];
val = val*val;
a[i] = val;
}
// print result
cout << "CPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << endl;
cout << endl;
// GPU computation
// reinit data
for(int i=0; i<n; i++) a[i] = i;
// ###
// ### TODO: Implement the "square array" operation on the GPU and store the result in "a"
// ###
// ### Notes:
// ### 1. Remember to free all GPU arrays after the computation
// ### 2. Always use the macro CUDA_CHECK after each CUDA call, e.g. "cudaMalloc(...); CUDA_CHECK;"
// ### For convenience this macro is defined directly in this file, later we will only include "helper.h"
dim3 block = dim3(10,1,1);
dim3 grid = dim3((n+block.x-1)/block.x,1,1);
float *d_a;
cudaMalloc(&d_a,n*sizeof(float));
CUDA_CHECK;
cudaMemcpy( d_a, a, n * sizeof(float), cudaMemcpyHostToDevice );CUDA_CHECK;
g_square<<<grid,block>>>(d_a,n);
cudaMemcpy( a, d_a, n * sizeof(float), cudaMemcpyDeviceToHost );CUDA_CHECK;
cudaFree(d_a);CUDA_CHECK;
// print result
cout << "GPU:" << endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << endl;
cout << endl;
// free CPU arrays
delete[] a;
} | // ###
// ###
// ### Practical Course: GPU Programming in Computer Vision
// ###
// ###
// ### Technical University Munich, Computer Vision Group
// ### Summer Semester 2017, September 11 - October 9
// ###
#include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
// cuda error checking
#define CUDA_CHECK cuda_check(__FILE__,__LINE__)
void cuda_check(string file, int line)
{
hipError_t e = hipGetLastError();
if (e != hipSuccess)
{
cout << endl << file << ", line " << line << ": " << hipGetErrorString(e) << " (" << e << ")" << endl;
exit(1);
}
}
__device__ float square(float a) {return a*a;}
__global__ void g_square(float*a, int n)
{
int ind = threadIdx.x + blockDim.x * blockIdx.x;
if(ind<n) a[ind]=square(a[ind]);
}
int main(int argc, char **argv)
{
// alloc and init input arrays on host (CPU)
int n = 10;
float *a = new float[n];
for(int i=0; i<n; i++) a[i] = i;
// CPU computation
for(int i=0; i<n; i++)
{
float val = a[i];
val = val*val;
a[i] = val;
}
// print result
cout << "CPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << endl;
cout << endl;
// GPU computation
// reinit data
for(int i=0; i<n; i++) a[i] = i;
// ###
// ### TODO: Implement the "square array" operation on the GPU and store the result in "a"
// ###
// ### Notes:
// ### 1. Remember to free all GPU arrays after the computation
// ### 2. Always use the macro CUDA_CHECK after each CUDA call, e.g. "cudaMalloc(...); CUDA_CHECK;"
// ### For convenience this macro is defined directly in this file, later we will only include "helper.h"
dim3 block = dim3(10,1,1);
dim3 grid = dim3((n+block.x-1)/block.x,1,1);
float *d_a;
hipMalloc(&d_a,n*sizeof(float));
CUDA_CHECK;
hipMemcpy( d_a, a, n * sizeof(float), hipMemcpyHostToDevice );CUDA_CHECK;
g_square<<<grid,block>>>(d_a,n);
hipMemcpy( a, d_a, n * sizeof(float), hipMemcpyDeviceToHost );CUDA_CHECK;
hipFree(d_a);CUDA_CHECK;
// print result
cout << "GPU:" << endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << endl;
cout << endl;
// free CPU arrays
delete[] a;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // ###
// ###
// ### Practical Course: GPU Programming in Computer Vision
// ###
// ###
// ### Technical University Munich, Computer Vision Group
// ### Summer Semester 2017, September 11 - October 9
// ###
#include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
// cuda error checking
#define CUDA_CHECK cuda_check(__FILE__,__LINE__)
void cuda_check(string file, int line)
{
hipError_t e = hipGetLastError();
if (e != hipSuccess)
{
cout << endl << file << ", line " << line << ": " << hipGetErrorString(e) << " (" << e << ")" << endl;
exit(1);
}
}
__device__ float square(float a) {return a*a;}
__global__ void g_square(float*a, int n)
{
int ind = threadIdx.x + blockDim.x * blockIdx.x;
if(ind<n) a[ind]=square(a[ind]);
}
int main(int argc, char **argv)
{
// alloc and init input arrays on host (CPU)
int n = 10;
float *a = new float[n];
for(int i=0; i<n; i++) a[i] = i;
// CPU computation
for(int i=0; i<n; i++)
{
float val = a[i];
val = val*val;
a[i] = val;
}
// print result
cout << "CPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << endl;
cout << endl;
// GPU computation
// reinit data
for(int i=0; i<n; i++) a[i] = i;
// ###
// ### TODO: Implement the "square array" operation on the GPU and store the result in "a"
// ###
// ### Notes:
// ### 1. Remember to free all GPU arrays after the computation
// ### 2. Always use the macro CUDA_CHECK after each CUDA call, e.g. "cudaMalloc(...); CUDA_CHECK;"
// ### For convenience this macro is defined directly in this file, later we will only include "helper.h"
dim3 block = dim3(10,1,1);
dim3 grid = dim3((n+block.x-1)/block.x,1,1);
float *d_a;
hipMalloc(&d_a,n*sizeof(float));
CUDA_CHECK;
hipMemcpy( d_a, a, n * sizeof(float), hipMemcpyHostToDevice );CUDA_CHECK;
g_square<<<grid,block>>>(d_a,n);
hipMemcpy( a, d_a, n * sizeof(float), hipMemcpyDeviceToHost );CUDA_CHECK;
hipFree(d_a);CUDA_CHECK;
// print result
cout << "GPU:" << endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << endl;
cout << endl;
// free CPU arrays
delete[] a;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8g_squarePfi
.globl _Z8g_squarePfi
.p2align 8
.type _Z8g_squarePfi,@function
_Z8g_squarePfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8g_squarePfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8g_squarePfi, .Lfunc_end0-_Z8g_squarePfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8g_squarePfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8g_squarePfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // ###
// ###
// ### Practical Course: GPU Programming in Computer Vision
// ###
// ###
// ### Technical University Munich, Computer Vision Group
// ### Summer Semester 2017, September 11 - October 9
// ###
#include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
// cuda error checking
#define CUDA_CHECK cuda_check(__FILE__,__LINE__)
void cuda_check(string file, int line)
{
hipError_t e = hipGetLastError();
if (e != hipSuccess)
{
cout << endl << file << ", line " << line << ": " << hipGetErrorString(e) << " (" << e << ")" << endl;
exit(1);
}
}
__device__ float square(float a) {return a*a;}
__global__ void g_square(float*a, int n)
{
int ind = threadIdx.x + blockDim.x * blockIdx.x;
if(ind<n) a[ind]=square(a[ind]);
}
int main(int argc, char **argv)
{
// alloc and init input arrays on host (CPU)
int n = 10;
float *a = new float[n];
for(int i=0; i<n; i++) a[i] = i;
// CPU computation
for(int i=0; i<n; i++)
{
float val = a[i];
val = val*val;
a[i] = val;
}
// print result
cout << "CPU:"<<endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << endl;
cout << endl;
// GPU computation
// reinit data
for(int i=0; i<n; i++) a[i] = i;
// ###
// ### TODO: Implement the "square array" operation on the GPU and store the result in "a"
// ###
// ### Notes:
// ### 1. Remember to free all GPU arrays after the computation
// ### 2. Always use the macro CUDA_CHECK after each CUDA call, e.g. "cudaMalloc(...); CUDA_CHECK;"
// ### For convenience this macro is defined directly in this file, later we will only include "helper.h"
dim3 block = dim3(10,1,1);
dim3 grid = dim3((n+block.x-1)/block.x,1,1);
float *d_a;
hipMalloc(&d_a,n*sizeof(float));
CUDA_CHECK;
hipMemcpy( d_a, a, n * sizeof(float), hipMemcpyHostToDevice );CUDA_CHECK;
g_square<<<grid,block>>>(d_a,n);
hipMemcpy( a, d_a, n * sizeof(float), hipMemcpyDeviceToHost );CUDA_CHECK;
hipFree(d_a);CUDA_CHECK;
// print result
cout << "GPU:" << endl;
for(int i=0; i<n; i++) cout << i << ": " << a[i] << endl;
cout << endl;
// free CPU arrays
delete[] a;
} | .text
.file "squareArray.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi # -- Begin function _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.p2align 4, 0x90
.type _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi,@function
_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi: # @_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %r14
callq hipGetLastError
testl %eax, %eax
jne .LBB0_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 32
movl $_ZSt4cout, %edi
movl %eax, %ebx
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movq %rax, %rdi
movq %r14, %rsi
callq _ZStlsIcSt11char_traitsIcESaIcEERSt13basic_ostreamIT_T0_ES7_RKNSt7__cxx1112basic_stringIS4_S5_T1_EE
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebp, %esi
callq _ZNSolsEi
movl $.L.str.1, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.2, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebx, %esi
callq _ZNSolsEi
movl $.L.str.3, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi, .Lfunc_end0-_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.cfi_endproc
# -- End function
.globl _Z23__device_stub__g_squarePfi # -- Begin function _Z23__device_stub__g_squarePfi
.p2align 4, 0x90
.type _Z23__device_stub__g_squarePfi,@function
_Z23__device_stub__g_squarePfi: # @_Z23__device_stub__g_squarePfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8g_squarePfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z23__device_stub__g_squarePfi, .Lfunc_end1-_Z23__device_stub__g_squarePfi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $232, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
.cfi_escape 0x2e, 0x00
movl $40, %edi
callq _Znam
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB2_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm0, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB2_3
# %bb.4:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_62
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB2_7
# %bb.6:
movzbl 67(%r14), %eax
jmp .LBB2_8
.LBB2_7:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r14d, %r14d
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_35: # in Loop: Header=BB2_9 Depth=1
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB2_36: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit122
# in Loop: Header=BB2_9 Depth=1
.cfi_escape 0x2e, 0x00
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r14
cmpq $10, %r14
je .LBB2_11
.LBB2_9: # =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %r15
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB2_10
# %bb.33: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i119
# in Loop: Header=BB2_9 Depth=1
cmpb $0, 56(%r15)
je .LBB2_35
# %bb.34: # in Loop: Header=BB2_9 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB2_36
.LBB2_11:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_63
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i114
cmpb $0, 56(%r14)
je .LBB2_14
# %bb.13:
movzbl 67(%r14), %eax
jmp .LBB2_15
.LBB2_14:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit117
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_16: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB2_16
# %bb.17: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 136(%rsp), %r14
movq %r14, 120(%rsp)
.cfi_escape 0x2e, 0x00
movl $116, %edi
callq _Znwm
movq %rax, 120(%rsp)
movq $115, 136(%rsp)
movups .L.str.5(%rip), %xmm0
movups %xmm0, (%rax)
movups .L.str.5+16(%rip), %xmm0
movups %xmm0, 16(%rax)
movups .L.str.5+32(%rip), %xmm0
movups %xmm0, 32(%rax)
movups .L.str.5+48(%rip), %xmm0
movups %xmm0, 48(%rax)
movups .L.str.5+64(%rip), %xmm0
movups %xmm0, 64(%rax)
movups .L.str.5+80(%rip), %xmm0
movups %xmm0, 80(%rax)
movups .L.str.5+96(%rip), %xmm0
movups %xmm0, 96(%rax)
movl $1885956142, 111(%rax) # imm = 0x7069682E
movq $115, 128(%rsp)
movb $0, 115(%rax)
.Ltmp0:
.cfi_escape 0x2e, 0x00
leaq 120(%rsp), %rdi
movl $72, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp1:
# %bb.18:
movq 120(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_20
# %bb.19: # %.critedge.i.i
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_20: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq 8(%rsp), %rdi
.cfi_escape 0x2e, 0x00
movl $40, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 104(%rsp), %r14
movq %r14, 88(%rsp)
.cfi_escape 0x2e, 0x00
movl $116, %edi
callq _Znwm
movq %rax, 88(%rsp)
movq $115, 104(%rsp)
movups .L.str.5(%rip), %xmm0
movups %xmm0, (%rax)
movups .L.str.5+16(%rip), %xmm0
movups %xmm0, 16(%rax)
movups .L.str.5+32(%rip), %xmm0
movups %xmm0, 32(%rax)
movups .L.str.5+48(%rip), %xmm0
movups %xmm0, 48(%rax)
movups .L.str.5+64(%rip), %xmm0
movups %xmm0, 64(%rax)
movups .L.str.5+80(%rip), %xmm0
movups %xmm0, 80(%rax)
movups .L.str.5+96(%rip), %xmm0
movups %xmm0, 96(%rax)
movl $1885956142, 111(%rax) # imm = 0x7069682E
movq $115, 96(%rsp)
movb $0, 115(%rax)
.Ltmp3:
.cfi_escape 0x2e, 0x00
leaq 88(%rsp), %rdi
movl $75, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp4:
# %bb.21:
movq 88(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_23
# %bb.22: # %.critedge.i.i78
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_23: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit80
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
.cfi_escape 0x2e, 0x00
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_25
# %bb.24:
movq 8(%rsp), %rax
movq %rax, 200(%rsp)
movl $10, 20(%rsp)
leaq 200(%rsp), %rax
movq %rax, 208(%rsp)
leaq 20(%rsp), %rax
movq %rax, 216(%rsp)
.cfi_escape 0x2e, 0x00
leaq 184(%rsp), %rdi
leaq 168(%rsp), %rsi
leaq 160(%rsp), %rdx
leaq 152(%rsp), %rcx
callq __hipPopCallConfiguration
movq 184(%rsp), %rsi
movl 192(%rsp), %edx
movq 168(%rsp), %rcx
movl 176(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 208(%rsp), %r9
movl $_Z8g_squarePfi, %edi
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_25: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i87
movq 8(%rsp), %rsi
.cfi_escape 0x2e, 0x00
movl $40, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
leaq 72(%rsp), %r14
movq %r14, 56(%rsp)
.cfi_escape 0x2e, 0x00
movl $116, %edi
callq _Znwm
movq %rax, 56(%rsp)
movq $115, 72(%rsp)
movups .L.str.5(%rip), %xmm0
movups %xmm0, (%rax)
movups .L.str.5+16(%rip), %xmm0
movups %xmm0, 16(%rax)
movups .L.str.5+32(%rip), %xmm0
movups %xmm0, 32(%rax)
movups .L.str.5+48(%rip), %xmm0
movups %xmm0, 48(%rax)
movups .L.str.5+64(%rip), %xmm0
movups %xmm0, 64(%rax)
movups .L.str.5+80(%rip), %xmm0
movups %xmm0, 80(%rax)
movups .L.str.5+96(%rip), %xmm0
movups %xmm0, 96(%rax)
movl $1885956142, 111(%rax) # imm = 0x7069682E
movq $115, 64(%rsp)
movb $0, 115(%rax)
.Ltmp6:
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
movl $79, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp7:
# %bb.26:
movq 56(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_28
# %bb.27: # %.critedge.i.i94
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_28: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit96
movq 8(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
leaq 40(%rsp), %r14
movq %r14, 24(%rsp)
.cfi_escape 0x2e, 0x00
movl $116, %edi
callq _Znwm
movq %rax, 24(%rsp)
movq $115, 40(%rsp)
movups .L.str.5(%rip), %xmm0
movups %xmm0, (%rax)
movups .L.str.5+16(%rip), %xmm0
movups %xmm0, 16(%rax)
movups .L.str.5+32(%rip), %xmm0
movups %xmm0, 32(%rax)
movups .L.str.5+48(%rip), %xmm0
movups %xmm0, 48(%rax)
movups .L.str.5+64(%rip), %xmm0
movups %xmm0, 64(%rax)
movups .L.str.5+80(%rip), %xmm0
movups %xmm0, 80(%rax)
movups .L.str.5+96(%rip), %xmm0
movups %xmm0, 96(%rax)
movl $1885956142, 111(%rax) # imm = 0x7069682E
movq $115, 32(%rsp)
movb $0, 115(%rax)
.Ltmp9:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movl $80, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp10:
# %bb.29:
movq 24(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_31
# %bb.30: # %.critedge.i.i104
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_31: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit106
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_32
# %bb.43: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i124
cmpb $0, 56(%r14)
je .LBB2_45
# %bb.44:
movzbl 67(%r14), %eax
jmp .LBB2_46
.LBB2_45:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_46: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit127
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r14d, %r14d
jmp .LBB2_47
.p2align 4, 0x90
.LBB2_60: # in Loop: Header=BB2_47 Depth=1
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB2_61: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit137
# in Loop: Header=BB2_47 Depth=1
.cfi_escape 0x2e, 0x00
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r14
cmpq $10, %r14
je .LBB2_49
.LBB2_47: # =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %r15
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB2_48
# %bb.58: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i134
# in Loop: Header=BB2_47 Depth=1
cmpb $0, 56(%r15)
je .LBB2_60
# %bb.59: # in Loop: Header=BB2_47 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB2_61
.LBB2_49:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_64
# %bb.50: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i129
cmpb $0, 56(%r14)
je .LBB2_52
# %bb.51:
movzbl 67(%r14), %eax
jmp .LBB2_53
.LBB2_52:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_53: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit132
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $232, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_10:
.cfi_def_cfa_offset 272
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_48:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_62:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_63:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_32:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_64:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_56:
.Ltmp11:
movq %rax, %rbx
movq 24(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_40
# %bb.57: # %.critedge.i.i110
.cfi_escape 0x2e, 0x00
jmp .LBB2_39
.LBB2_54:
.Ltmp8:
movq %rax, %rbx
movq 56(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_40
# %bb.55: # %.critedge.i.i107
.cfi_escape 0x2e, 0x00
jmp .LBB2_39
.LBB2_41:
.Ltmp5:
movq %rax, %rbx
movq 88(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_40
# %bb.42: # %.critedge.i.i84
.cfi_escape 0x2e, 0x00
jmp .LBB2_39
.LBB2_37:
.Ltmp2:
movq %rax, %rbx
movq 120(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_40
# %bb.38: # %.critedge.i.i81
.cfi_escape 0x2e, 0x00
.LBB2_39: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit83
callq _ZdlPv
.LBB2_40: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit83
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp6-.Ltmp4 # Call between .Ltmp4 and .Ltmp6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp9-.Ltmp7 # Call between .Ltmp7 and .Ltmp9
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Lfunc_end2-.Ltmp10 # Call between .Ltmp10 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8g_squarePfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz ", line "
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ": "
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " ("
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz ")"
.size .L.str.3, 2
.type _Z8g_squarePfi,@object # @_Z8g_squarePfi
.section .rodata,"a",@progbits
.globl _Z8g_squarePfi
.p2align 3, 0x0
_Z8g_squarePfi:
.quad _Z23__device_stub__g_squarePfi
.size _Z8g_squarePfi, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "CPU:"
.size .L.str.4, 5
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/a-parida12/GPUCuda/master/Day1/CUDA_kernel/squareArray.hip"
.size .L.str.5, 116
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "GPU:"
.size .L.str.6, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8g_squarePfi"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__g_squarePfi
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZSt4cout
.addrsig_sym _Z8g_squarePfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8g_squarePfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FMUL R5, R0, R0 ; /* 0x0000000000057220 */
/* 0x004fca0000400000 */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8g_squarePfi
.globl _Z8g_squarePfi
.p2align 8
.type _Z8g_squarePfi,@function
_Z8g_squarePfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8g_squarePfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8g_squarePfi, .Lfunc_end0-_Z8g_squarePfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8g_squarePfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8g_squarePfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000de3f6_00000000-6_squareArray.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string ", line "
.LC1:
.string ": "
.LC2:
.string " ("
.LC3:
.string ")"
.text
.globl _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.type _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi, @function
_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbp
movl %esi, %r12d
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %ebx
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
movq 8(%rbp), %rdx
movq 0(%rbp), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %r12d, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbp
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi, .-_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.globl _Z6squaref
.type _Z6squaref, @function
_Z6squaref:
.LFB3670:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size _Z6squaref, .-_Z6squaref
.globl _Z28__device_stub__Z8g_squarePfiPfi
.type _Z28__device_stub__Z8g_squarePfiPfi, @function
_Z28__device_stub__Z8g_squarePfiPfi:
.LFB3696:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8g_squarePfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z28__device_stub__Z8g_squarePfiPfi, .-_Z28__device_stub__Z8g_squarePfiPfi
.globl _Z8g_squarePfi
.type _Z8g_squarePfi, @function
_Z8g_squarePfi:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z8g_squarePfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z8g_squarePfi, .-_Z8g_squarePfi
.section .rodata.str1.1
.LC4:
.string "_Z8g_squarePfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z8g_squarePfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "basic_string: construction from null is not valid"
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC5IS3_EEPKcRKS3_,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_:
.LFB4006:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 16(%rdi), %r12
movq %r12, (%rdi)
testq %rsi, %rsi
je .L28
movq %rdi, %rbx
movq %rsi, %r13
movq %rsi, %rdi
call strlen@PLT
movq %rax, %rbp
movq %rax, (%rsp)
cmpq $15, %rax
ja .L29
cmpq $1, %rax
jne .L24
movzbl 0(%r13), %eax
movb %al, 16(%rbx)
.L25:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L31
leaq .LC5(%rip), %rdi
call _ZSt19__throw_logic_errorPKc@PLT
.L31:
call __stack_chk_fail@PLT
.L29:
movq %rsp, %rsi
movl $0, %edx
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %r12
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L23:
movq %rbp, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memcpy@PLT
jmp .L25
.L24:
testq %rax, %rax
je .L25
jmp .L23
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4006:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.set _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.section .rodata.str1.1
.LC6:
.string "CPU:"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "/home/ubuntu/Datasets/stackv2/train-structured/a-parida12/GPUCuda/master/Day1/CUDA_kernel/squareArray.cu"
.section .rodata.str1.1
.LC8:
.string "GPU:"
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3671
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $40, %edi
.LEHB0:
call _Znam@PLT
movq %rax, %rbp
movl $0, %eax
.L33:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L33
movq %rbp, %rax
leaq 40(%rbp), %rdx
.L34:
movss (%rax), %xmm0
mulss %xmm0, %xmm0
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L34
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %r12d
leaq _ZSt4cout(%rip), %r14
leaq .LC1(%rip), %r13
jmp .L39
.L69:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L67
call _ZSt16__throw_bad_castv@PLT
.L67:
call __stack_chk_fail@PLT
.L37:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
.L38:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %r12
cmpq $10, %r12
je .L68
.L39:
movl %r12d, %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $2, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%r12,4), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .L69
cmpb $0, 56(%r15)
je .L37
movzbl 67(%r15), %esi
jmp .L38
.L68:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %eax
.L40:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L40
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 15(%rsp), %rdx
leaq 48(%rsp), %rbx
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE0:
movl $72, %esi
movq %rbx, %rdi
.LEHB1:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE1:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $1, %ecx
movl $40, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
.LEHB2:
call cudaMemcpy@PLT
leaq 15(%rsp), %rdx
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE2:
movl $75, %esi
movq %rbx, %rdi
.LEHB3:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE3:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $10, 24(%rsp)
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
.LEHB4:
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L70
.L41:
movl $2, %ecx
movl $40, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq 15(%rsp), %rdx
leaq 48(%rsp), %rbx
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE4:
movl $79, %esi
movq %rbx, %rdi
.LEHB5:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE5:
jmp .L71
.L70:
movl $10, %esi
movq 16(%rsp), %rdi
.LEHB6:
call _Z28__device_stub__Z8g_squarePfiPfi
jmp .L41
.L71:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq 15(%rsp), %rdx
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE6:
movl $80, %esi
movq %rbx, %rdi
.LEHB7:
call _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.LEHE7:
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB8:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %r12d
leaq _ZSt4cout(%rip), %r14
leaq .LC1(%rip), %r13
jmp .L46
.L74:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L72
call _ZSt16__throw_bad_castv@PLT
.L72:
call __stack_chk_fail@PLT
.L44:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
.L45:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %r12
cmpq $10, %r12
je .L73
.L46:
movl %r12d, %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $2, %edx
movq %r13, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%r12,4), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .L74
cmpb $0, 56(%r15)
je .L44
movzbl 67(%r15), %esi
jmp .L45
.L73:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L75
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L56:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
je .L48
call __stack_chk_fail@PLT
.L48:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L57:
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
je .L50
call __stack_chk_fail@PLT
.L50:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L58:
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
je .L52
call __stack_chk_fail@PLT
.L52:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.L59:
endbr64
movq %rax, %rbx
leaq 48(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
je .L54
call __stack_chk_fail@PLT
.L54:
movq %rbx, %rdi
call _Unwind_Resume@PLT
.LEHE8:
.L75:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3671:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3671-.LLSDACSB3671
.LLSDACSB3671:
.uleb128 .LEHB0-.LFB3671
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3671
.uleb128 .LEHE1-.LEHB1
.uleb128 .L56-.LFB3671
.uleb128 0
.uleb128 .LEHB2-.LFB3671
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB3671
.uleb128 .LEHE3-.LEHB3
.uleb128 .L57-.LFB3671
.uleb128 0
.uleb128 .LEHB4-.LFB3671
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.uleb128 .LEHB5-.LFB3671
.uleb128 .LEHE5-.LEHB5
.uleb128 .L58-.LFB3671
.uleb128 0
.uleb128 .LEHB6-.LFB3671
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.uleb128 .LEHB7-.LFB3671
.uleb128 .LEHE7-.LEHB7
.uleb128 .L59-.LFB3671
.uleb128 0
.uleb128 .LEHB8-.LFB3671
.uleb128 .LEHE8-.LEHB8
.uleb128 0
.uleb128 0
.LLSDACSE3671:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "squareArray.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi # -- Begin function _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.p2align 4, 0x90
.type _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi,@function
_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi: # @_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %r14
callq hipGetLastError
testl %eax, %eax
jne .LBB0_2
# %bb.1:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 32
movl $_ZSt4cout, %edi
movl %eax, %ebx
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movq %rax, %rdi
movq %r14, %rsi
callq _ZStlsIcSt11char_traitsIcESaIcEERSt13basic_ostreamIT_T0_ES7_RKNSt7__cxx1112basic_stringIS4_S5_T1_EE
movl $.L.str, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebp, %esi
callq _ZNSolsEi
movl $.L.str.1, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.2, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %ebx, %esi
callq _ZNSolsEi
movl $.L.str.3, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi, .Lfunc_end0-_Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.cfi_endproc
# -- End function
.globl _Z23__device_stub__g_squarePfi # -- Begin function _Z23__device_stub__g_squarePfi
.p2align 4, 0x90
.type _Z23__device_stub__g_squarePfi,@function
_Z23__device_stub__g_squarePfi: # @_Z23__device_stub__g_squarePfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8g_squarePfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z23__device_stub__g_squarePfi, .Lfunc_end1-_Z23__device_stub__g_squarePfi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $232, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
.cfi_escape 0x2e, 0x00
movl $40, %edi
callq _Znam
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB2_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_3: # %.preheader
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm0, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB2_3
# %bb.4:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_62
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB2_7
# %bb.6:
movzbl 67(%r14), %eax
jmp .LBB2_8
.LBB2_7:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r14d, %r14d
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_35: # in Loop: Header=BB2_9 Depth=1
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB2_36: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit122
# in Loop: Header=BB2_9 Depth=1
.cfi_escape 0x2e, 0x00
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r14
cmpq $10, %r14
je .LBB2_11
.LBB2_9: # =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %r15
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB2_10
# %bb.33: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i119
# in Loop: Header=BB2_9 Depth=1
cmpb $0, 56(%r15)
je .LBB2_35
# %bb.34: # in Loop: Header=BB2_9 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB2_36
.LBB2_11:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_63
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i114
cmpb $0, 56(%r14)
je .LBB2_14
# %bb.13:
movzbl 67(%r14), %eax
jmp .LBB2_15
.LBB2_14:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit117
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_16: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB2_16
# %bb.17: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 136(%rsp), %r14
movq %r14, 120(%rsp)
.cfi_escape 0x2e, 0x00
movl $116, %edi
callq _Znwm
movq %rax, 120(%rsp)
movq $115, 136(%rsp)
movups .L.str.5(%rip), %xmm0
movups %xmm0, (%rax)
movups .L.str.5+16(%rip), %xmm0
movups %xmm0, 16(%rax)
movups .L.str.5+32(%rip), %xmm0
movups %xmm0, 32(%rax)
movups .L.str.5+48(%rip), %xmm0
movups %xmm0, 48(%rax)
movups .L.str.5+64(%rip), %xmm0
movups %xmm0, 64(%rax)
movups .L.str.5+80(%rip), %xmm0
movups %xmm0, 80(%rax)
movups .L.str.5+96(%rip), %xmm0
movups %xmm0, 96(%rax)
movl $1885956142, 111(%rax) # imm = 0x7069682E
movq $115, 128(%rsp)
movb $0, 115(%rax)
.Ltmp0:
.cfi_escape 0x2e, 0x00
leaq 120(%rsp), %rdi
movl $72, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp1:
# %bb.18:
movq 120(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_20
# %bb.19: # %.critedge.i.i
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_20: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq 8(%rsp), %rdi
.cfi_escape 0x2e, 0x00
movl $40, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 104(%rsp), %r14
movq %r14, 88(%rsp)
.cfi_escape 0x2e, 0x00
movl $116, %edi
callq _Znwm
movq %rax, 88(%rsp)
movq $115, 104(%rsp)
movups .L.str.5(%rip), %xmm0
movups %xmm0, (%rax)
movups .L.str.5+16(%rip), %xmm0
movups %xmm0, 16(%rax)
movups .L.str.5+32(%rip), %xmm0
movups %xmm0, 32(%rax)
movups .L.str.5+48(%rip), %xmm0
movups %xmm0, 48(%rax)
movups .L.str.5+64(%rip), %xmm0
movups %xmm0, 64(%rax)
movups .L.str.5+80(%rip), %xmm0
movups %xmm0, 80(%rax)
movups .L.str.5+96(%rip), %xmm0
movups %xmm0, 96(%rax)
movl $1885956142, 111(%rax) # imm = 0x7069682E
movq $115, 96(%rsp)
movb $0, 115(%rax)
.Ltmp3:
.cfi_escape 0x2e, 0x00
leaq 88(%rsp), %rdi
movl $75, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp4:
# %bb.21:
movq 88(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_23
# %bb.22: # %.critedge.i.i78
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_23: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit80
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
.cfi_escape 0x2e, 0x00
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_25
# %bb.24:
movq 8(%rsp), %rax
movq %rax, 200(%rsp)
movl $10, 20(%rsp)
leaq 200(%rsp), %rax
movq %rax, 208(%rsp)
leaq 20(%rsp), %rax
movq %rax, 216(%rsp)
.cfi_escape 0x2e, 0x00
leaq 184(%rsp), %rdi
leaq 168(%rsp), %rsi
leaq 160(%rsp), %rdx
leaq 152(%rsp), %rcx
callq __hipPopCallConfiguration
movq 184(%rsp), %rsi
movl 192(%rsp), %edx
movq 168(%rsp), %rcx
movl 176(%rsp), %r8d
.cfi_escape 0x2e, 0x10
leaq 208(%rsp), %r9
movl $_Z8g_squarePfi, %edi
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_25: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i87
movq 8(%rsp), %rsi
.cfi_escape 0x2e, 0x00
movl $40, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
leaq 72(%rsp), %r14
movq %r14, 56(%rsp)
.cfi_escape 0x2e, 0x00
movl $116, %edi
callq _Znwm
movq %rax, 56(%rsp)
movq $115, 72(%rsp)
movups .L.str.5(%rip), %xmm0
movups %xmm0, (%rax)
movups .L.str.5+16(%rip), %xmm0
movups %xmm0, 16(%rax)
movups .L.str.5+32(%rip), %xmm0
movups %xmm0, 32(%rax)
movups .L.str.5+48(%rip), %xmm0
movups %xmm0, 48(%rax)
movups .L.str.5+64(%rip), %xmm0
movups %xmm0, 64(%rax)
movups .L.str.5+80(%rip), %xmm0
movups %xmm0, 80(%rax)
movups .L.str.5+96(%rip), %xmm0
movups %xmm0, 96(%rax)
movl $1885956142, 111(%rax) # imm = 0x7069682E
movq $115, 64(%rsp)
movb $0, 115(%rax)
.Ltmp6:
.cfi_escape 0x2e, 0x00
leaq 56(%rsp), %rdi
movl $79, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp7:
# %bb.26:
movq 56(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_28
# %bb.27: # %.critedge.i.i94
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_28: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit96
movq 8(%rsp), %rdi
.cfi_escape 0x2e, 0x00
callq hipFree
leaq 40(%rsp), %r14
movq %r14, 24(%rsp)
.cfi_escape 0x2e, 0x00
movl $116, %edi
callq _Znwm
movq %rax, 24(%rsp)
movq $115, 40(%rsp)
movups .L.str.5(%rip), %xmm0
movups %xmm0, (%rax)
movups .L.str.5+16(%rip), %xmm0
movups %xmm0, 16(%rax)
movups .L.str.5+32(%rip), %xmm0
movups %xmm0, 32(%rax)
movups .L.str.5+48(%rip), %xmm0
movups %xmm0, 48(%rax)
movups .L.str.5+64(%rip), %xmm0
movups %xmm0, 64(%rax)
movups .L.str.5+80(%rip), %xmm0
movups %xmm0, 80(%rax)
movups .L.str.5+96(%rip), %xmm0
movups %xmm0, 96(%rax)
movl $1885956142, 111(%rax) # imm = 0x7069682E
movq $115, 32(%rsp)
movb $0, 115(%rax)
.Ltmp9:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movl $80, %esi
callq _Z10cuda_checkNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEi
.Ltmp10:
# %bb.29:
movq 24(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_31
# %bb.30: # %.critedge.i.i104
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB2_31: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit106
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_32
# %bb.43: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i124
cmpb $0, 56(%r14)
je .LBB2_45
# %bb.44:
movzbl 67(%r14), %eax
jmp .LBB2_46
.LBB2_45:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_46: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit127
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r14d, %r14d
jmp .LBB2_47
.p2align 4, 0x90
.LBB2_60: # in Loop: Header=BB2_47 Depth=1
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB2_61: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit137
# in Loop: Header=BB2_47 Depth=1
.cfi_escape 0x2e, 0x00
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r14
cmpq $10, %r14
je .LBB2_49
.LBB2_47: # =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %r15
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB2_48
# %bb.58: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i134
# in Loop: Header=BB2_47 Depth=1
cmpb $0, 56(%r15)
je .LBB2_60
# %bb.59: # in Loop: Header=BB2_47 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB2_61
.LBB2_49:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_64
# %bb.50: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i129
cmpb $0, 56(%r14)
je .LBB2_52
# %bb.51:
movzbl 67(%r14), %eax
jmp .LBB2_53
.LBB2_52:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_53: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit132
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $232, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_10:
.cfi_def_cfa_offset 272
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_48:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_62:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_63:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_32:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_64:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB2_56:
.Ltmp11:
movq %rax, %rbx
movq 24(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_40
# %bb.57: # %.critedge.i.i110
.cfi_escape 0x2e, 0x00
jmp .LBB2_39
.LBB2_54:
.Ltmp8:
movq %rax, %rbx
movq 56(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_40
# %bb.55: # %.critedge.i.i107
.cfi_escape 0x2e, 0x00
jmp .LBB2_39
.LBB2_41:
.Ltmp5:
movq %rax, %rbx
movq 88(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_40
# %bb.42: # %.critedge.i.i84
.cfi_escape 0x2e, 0x00
jmp .LBB2_39
.LBB2_37:
.Ltmp2:
movq %rax, %rbx
movq 120(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_40
# %bb.38: # %.critedge.i.i81
.cfi_escape 0x2e, 0x00
.LBB2_39: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit83
callq _ZdlPv
.LBB2_40: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit83
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp6-.Ltmp4 # Call between .Ltmp4 and .Ltmp6
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp6-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp9-.Ltmp7 # Call between .Ltmp7 and .Ltmp9
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Lfunc_end2-.Ltmp10 # Call between .Ltmp10 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8g_squarePfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz ", line "
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ": "
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " ("
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz ")"
.size .L.str.3, 2
.type _Z8g_squarePfi,@object # @_Z8g_squarePfi
.section .rodata,"a",@progbits
.globl _Z8g_squarePfi
.p2align 3, 0x0
_Z8g_squarePfi:
.quad _Z23__device_stub__g_squarePfi
.size _Z8g_squarePfi, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "CPU:"
.size .L.str.4, 5
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/a-parida12/GPUCuda/master/Day1/CUDA_kernel/squareArray.hip"
.size .L.str.5, 116
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "GPU:"
.size .L.str.6, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8g_squarePfi"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__g_squarePfi
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZSt4cout
.addrsig_sym _Z8g_squarePfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // 使用GPU输出Hello world
#include <stdio.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
__global__ void helloFromGPU (void)
{
printf("Hello World from GPU!\n");
}
int main(void)
{
// hello from cpu
printf("Hello World from CPU!\n");
for(int i=0;i<1000;i++)
{
helloFromGPU <<<1, 100>>>();
cudaDeviceReset();
}
return 0;
} | code for sm_80
Function : _Z12helloFromGPUv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // 使用GPU输出Hello world
#include <stdio.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
__global__ void helloFromGPU (void)
{
printf("Hello World from GPU!\n");
}
int main(void)
{
// hello from cpu
printf("Hello World from CPU!\n");
for(int i=0;i<1000;i++)
{
helloFromGPU <<<1, 100>>>();
cudaDeviceReset();
}
return 0;
} | .file "tmpxft_00140c3d_00000000-6_hellow_world.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z12helloFromGPUvv
.type _Z31__device_stub__Z12helloFromGPUvv, @function
_Z31__device_stub__Z12helloFromGPUvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12helloFromGPUv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z12helloFromGPUvv, .-_Z31__device_stub__Z12helloFromGPUvv
.globl _Z12helloFromGPUv
.type _Z12helloFromGPUv, @function
_Z12helloFromGPUv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z12helloFromGPUvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12helloFromGPUv, .-_Z12helloFromGPUv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World from CPU!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1000, %ebx
jmp .L13
.L12:
call cudaDeviceReset@PLT
subl $1, %ebx
je .L16
.L13:
movl $100, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L12
call _Z31__device_stub__Z12helloFromGPUvv
jmp .L12
.L16:
movl $0, %eax
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z12helloFromGPUv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z12helloFromGPUv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // 使用GPU输出Hello world
#include <stdio.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
__global__ void helloFromGPU (void)
{
printf("Hello World from GPU!\n");
}
int main(void)
{
// hello from cpu
printf("Hello World from CPU!\n");
for(int i=0;i<1000;i++)
{
helloFromGPU <<<1, 100>>>();
cudaDeviceReset();
}
return 0;
} | // 使用GPU输出Hello world
#include <stdio.h>
#include "hip/hip_runtime.h"
__global__ void helloFromGPU (void)
{
printf("Hello World from GPU!\n");
}
int main(void)
{
// hello from cpu
printf("Hello World from CPU!\n");
for(int i=0;i<1000;i++)
{
helloFromGPU <<<1, 100>>>();
hipDeviceReset();
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // 使用GPU输出Hello world
#include <stdio.h>
#include "hip/hip_runtime.h"
__global__ void helloFromGPU (void)
{
printf("Hello World from GPU!\n");
}
int main(void)
{
// hello from cpu
printf("Hello World from CPU!\n");
for(int i=0;i<1000;i++)
{
helloFromGPU <<<1, 100>>>();
hipDeviceReset();
}
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12helloFromGPUv
.globl _Z12helloFromGPUv
.p2align 8
.type _Z12helloFromGPUv,@function
_Z12helloFromGPUv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 23
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12helloFromGPUv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12helloFromGPUv, .Lfunc_end0-_Z12helloFromGPUv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello World from GPU!\n"
.size .str, 23
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12helloFromGPUv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z12helloFromGPUv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // 使用GPU输出Hello world
#include <stdio.h>
#include "hip/hip_runtime.h"
__global__ void helloFromGPU (void)
{
printf("Hello World from GPU!\n");
}
int main(void)
{
// hello from cpu
printf("Hello World from CPU!\n");
for(int i=0;i<1000;i++)
{
helloFromGPU <<<1, 100>>>();
hipDeviceReset();
}
return 0;
} | .text
.file "hellow_world.hip"
.globl _Z27__device_stub__helloFromGPUv # -- Begin function _Z27__device_stub__helloFromGPUv
.p2align 4, 0x90
.type _Z27__device_stub__helloFromGPUv,@function
_Z27__device_stub__helloFromGPUv: # @_Z27__device_stub__helloFromGPUv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z27__device_stub__helloFromGPUv, .Lfunc_end0-_Z27__device_stub__helloFromGPUv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967297, %rbx # imm = 0x100000001
movl $.Lstr, %edi
callq puts@PLT
movl $1000, %r12d # imm = 0x3E8
leaq 99(%rbx), %r14
leaq 8(%rsp), %r13
movq %rsp, %rbp
leaq 48(%rsp), %r15
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
callq hipDeviceReset
decl %r12d
je .LBB1_4
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
movl $_Z12helloFromGPUv, %edi
movq %r15, %r9
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_3
.LBB1_4:
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12helloFromGPUv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12helloFromGPUv,@object # @_Z12helloFromGPUv
.section .rodata,"a",@progbits
.globl _Z12helloFromGPUv
.p2align 3, 0x0
_Z12helloFromGPUv:
.quad _Z27__device_stub__helloFromGPUv
.size _Z12helloFromGPUv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12helloFromGPUv"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World from CPU!"
.size .Lstr, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__helloFromGPUv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12helloFromGPUv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12helloFromGPUv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12helloFromGPUv
.globl _Z12helloFromGPUv
.p2align 8
.type _Z12helloFromGPUv,@function
_Z12helloFromGPUv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 23
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12helloFromGPUv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12helloFromGPUv, .Lfunc_end0-_Z12helloFromGPUv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello World from GPU!\n"
.size .str, 23
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12helloFromGPUv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z12helloFromGPUv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00140c3d_00000000-6_hellow_world.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z12helloFromGPUvv
.type _Z31__device_stub__Z12helloFromGPUvv, @function
_Z31__device_stub__Z12helloFromGPUvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12helloFromGPUv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z12helloFromGPUvv, .-_Z31__device_stub__Z12helloFromGPUvv
.globl _Z12helloFromGPUv
.type _Z12helloFromGPUv, @function
_Z12helloFromGPUv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z12helloFromGPUvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12helloFromGPUv, .-_Z12helloFromGPUv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World from CPU!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $32, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1000, %ebx
jmp .L13
.L12:
call cudaDeviceReset@PLT
subl $1, %ebx
je .L16
.L13:
movl $100, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L12
call _Z31__device_stub__Z12helloFromGPUvv
jmp .L12
.L16:
movl $0, %eax
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z12helloFromGPUv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z12helloFromGPUv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hellow_world.hip"
.globl _Z27__device_stub__helloFromGPUv # -- Begin function _Z27__device_stub__helloFromGPUv
.p2align 4, 0x90
.type _Z27__device_stub__helloFromGPUv,@function
_Z27__device_stub__helloFromGPUv: # @_Z27__device_stub__helloFromGPUv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z27__device_stub__helloFromGPUv, .Lfunc_end0-_Z27__device_stub__helloFromGPUv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967297, %rbx # imm = 0x100000001
movl $.Lstr, %edi
callq puts@PLT
movl $1000, %r12d # imm = 0x3E8
leaq 99(%rbx), %r14
leaq 8(%rsp), %r13
movq %rsp, %rbp
leaq 48(%rsp), %r15
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
callq hipDeviceReset
decl %r12d
je .LBB1_4
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
movl $_Z12helloFromGPUv, %edi
movq %r15, %r9
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_3
.LBB1_4:
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12helloFromGPUv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12helloFromGPUv,@object # @_Z12helloFromGPUv
.section .rodata,"a",@progbits
.globl _Z12helloFromGPUv
.p2align 3, 0x0
_Z12helloFromGPUv:
.quad _Z27__device_stub__helloFromGPUv
.size _Z12helloFromGPUv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12helloFromGPUv"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World from CPU!"
.size .Lstr, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__helloFromGPUv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12helloFromGPUv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdio.h>
__global__ void printk(int *counter) {
do {
while (*counter % 2)
;
++*counter;
//__threadfence_system();
printf("\t%d\n", *counter);
} while (*counter < 10);
}
int main() {
int *counter;
cudaHostAlloc(&counter, sizeof(int), 0);
//cudaHostAlloc(&counter, sizeof(int), cudaHostAllocMapped);
printk <<<1, 1>>>(counter);
do {
printf("%d\n", *counter);
//fflush(stdout);
while (*counter % 2 == 0)
;
++*counter;
//__threadfence_system();
} while (*counter < 10);
cudaFreeHost(counter);
return 0;
} | code for sm_80
Function : _Z6printkPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff107624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff117624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fc80007ffe0ff */
/*0050*/ LDG.E R0, [R16.64] ; /* 0x0000002410007981 */
/* 0x000162000c1e1900 */
/*0060*/ IADD3 R2, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001027a10 */
/* 0x000fca0007f1e0ff */
/*0070*/ IMAD.X R18, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff127624 */
/* 0x000fe400000e06ff */
/*0080*/ LOP3.LUT R3, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100037812 */
/* 0x020fc800078ec0ff */
/*0090*/ ISETP.NE.U32.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fda0003f05070 */
/*00a0*/ @!P0 BRA 0x200 ; /* 0x0000015000008947 */
/* 0x000fea0003800000 */
/*00b0*/ MOV R8, 0x0 ; /* 0x0000000000087802 */
/* 0x000fe20000000f00 */
/*00c0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*00d0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007ffe0ff */
/*00e0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*00f0*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0002 */
/*0100*/ LDC.64 R8, c[0x4][R8] ; /* 0x0100000008087b82 */
/* 0x000e620000000a00 */
/*0110*/ STG.E [R16.64], R0 ; /* 0x0000000010007986 */
/* 0x0005e2000c101924 */
/*0120*/ IMAD.MOV.U32 R7, RZ, RZ, R18 ; /* 0x000000ffff077224 */
/* 0x000fc600078e0012 */
/*0130*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0005e80000100800 */
/*0140*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x000fe20000000000 */
/*0150*/ MOV R3, 0x1c0 ; /* 0x000001c000037802 */
/* 0x000fe40000000f00 */
/*0160*/ MOV R20, 0x140 ; /* 0x0000014000147802 */
/* 0x000fe40000000f00 */
/*0170*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0180*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x004fe40000000f00 */
/*0190*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*01a0*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*01b0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x003fea0003c00000 */
/*01c0*/ LDG.E R0, [R16.64] ; /* 0x0000002410007981 */
/* 0x000ea4000c1e1900 */
/*01d0*/ ISETP.GE.AND P0, PT, R0, 0xa, PT ; /* 0x0000000a0000780c */
/* 0x004fda0003f06270 */
/*01e0*/ @!P0 BRA 0x80 ; /* 0xfffffe9000008947 */
/* 0x000fea000383ffff */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200 ; /* 0xfffffff000007947 */
/* 0x000fea000383ffff */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdio.h>
__global__ void printk(int *counter) {
do {
while (*counter % 2)
;
++*counter;
//__threadfence_system();
printf("\t%d\n", *counter);
} while (*counter < 10);
}
int main() {
int *counter;
cudaHostAlloc(&counter, sizeof(int), 0);
//cudaHostAlloc(&counter, sizeof(int), cudaHostAllocMapped);
printk <<<1, 1>>>(counter);
do {
printf("%d\n", *counter);
//fflush(stdout);
while (*counter % 2 == 0)
;
++*counter;
//__threadfence_system();
} while (*counter < 10);
cudaFreeHost(counter);
return 0;
} | .file "tmpxft_001504af_00000000-6_persistentkernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z6printkPiPi
.type _Z25__device_stub__Z6printkPiPi, @function
_Z25__device_stub__Z6printkPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6printkPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z25__device_stub__Z6printkPiPi, .-_Z25__device_stub__Z6printkPiPi
.globl _Z6printkPi
.type _Z6printkPi, @function
_Z6printkPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z6printkPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6printkPi, .-_Z6printkPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $0, %edx
movl $4, %esi
call cudaHostAlloc@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L12:
leaq .LC0(%rip), %rbx
.L14:
movq 8(%rsp), %rax
movl (%rax), %edx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rcx
movl (%rcx), %edx
movl %edx, %eax
andl $1, %eax
.L13:
testl %eax, %eax
je .L13
addl $1, %edx
movl %edx, (%rcx)
movq 8(%rsp), %rdi
cmpl $9, (%rdi)
jle .L14
call cudaFreeHost@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z25__device_stub__Z6printkPiPi
jmp .L12
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6printkPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6printkPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdio.h>
__global__ void printk(int *counter) {
do {
while (*counter % 2)
;
++*counter;
//__threadfence_system();
printf("\t%d\n", *counter);
} while (*counter < 10);
}
int main() {
int *counter;
cudaHostAlloc(&counter, sizeof(int), 0);
//cudaHostAlloc(&counter, sizeof(int), cudaHostAllocMapped);
printk <<<1, 1>>>(counter);
do {
printf("%d\n", *counter);
//fflush(stdout);
while (*counter % 2 == 0)
;
++*counter;
//__threadfence_system();
} while (*counter < 10);
cudaFreeHost(counter);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void printk(int *counter) {
do {
while (*counter % 2)
;
++*counter;
//__threadfence_system();
printf("\t%d\n", *counter);
} while (*counter < 10);
}
int main() {
int *counter;
hipHostAlloc(&counter, sizeof(int), 0);
//cudaHostAlloc(&counter, sizeof(int), cudaHostAllocMapped);
printk <<<1, 1>>>(counter);
do {
printf("%d\n", *counter);
//fflush(stdout);
while (*counter % 2 == 0)
;
++*counter;
//__threadfence_system();
} while (*counter < 10);
hipHostFree(counter);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void printk(int *counter) {
do {
while (*counter % 2)
;
++*counter;
//__threadfence_system();
printf("\t%d\n", *counter);
} while (*counter < 10);
}
int main() {
int *counter;
hipHostAlloc(&counter, sizeof(int), 0);
//cudaHostAlloc(&counter, sizeof(int), cudaHostAllocMapped);
printk <<<1, 1>>>(counter);
do {
printf("%d\n", *counter);
//fflush(stdout);
while (*counter % 2 == 0)
;
++*counter;
//__threadfence_system();
} while (*counter < 10);
hipHostFree(counter);
return 0;
} | .text
.file "persistentkernel.hip"
.globl _Z21__device_stub__printkPi # -- Begin function _Z21__device_stub__printkPi
.p2align 4, 0x90
.type _Z21__device_stub__printkPi,@function
_Z21__device_stub__printkPi: # @_Z21__device_stub__printkPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z6printkPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z21__device_stub__printkPi, .Lfunc_end0-_Z21__device_stub__printkPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
leaq 8(%rsp), %rdi
movl $4, %esi
xorl %edx, %edx
callq hipHostAlloc
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z6printkPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.p2align 4, 0x90
.LBB1_2: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
movl (%rax), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
movl (%rdi), %eax
leal 1(%rax), %ecx
movl %ecx, (%rdi)
cmpl $9, %eax
jl .LBB1_2
# %bb.3:
callq hipHostFree
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6printkPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6printkPi,@object # @_Z6printkPi
.section .rodata,"a",@progbits
.globl _Z6printkPi
.p2align 3, 0x0
_Z6printkPi:
.quad _Z21__device_stub__printkPi
.size _Z6printkPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\n"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6printkPi"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__printkPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6printkPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001504af_00000000-6_persistentkernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z6printkPiPi
.type _Z25__device_stub__Z6printkPiPi, @function
_Z25__device_stub__Z6printkPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6printkPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z25__device_stub__Z6printkPiPi, .-_Z25__device_stub__Z6printkPiPi
.globl _Z6printkPi
.type _Z6printkPi, @function
_Z6printkPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z6printkPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6printkPi, .-_Z6printkPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $0, %edx
movl $4, %esi
call cudaHostAlloc@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L12:
leaq .LC0(%rip), %rbx
.L14:
movq 8(%rsp), %rax
movl (%rax), %edx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rcx
movl (%rcx), %edx
movl %edx, %eax
andl $1, %eax
.L13:
testl %eax, %eax
je .L13
addl $1, %edx
movl %edx, (%rcx)
movq 8(%rsp), %rdi
cmpl $9, (%rdi)
jle .L14
call cudaFreeHost@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z25__device_stub__Z6printkPiPi
jmp .L12
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6printkPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6printkPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "persistentkernel.hip"
.globl _Z21__device_stub__printkPi # -- Begin function _Z21__device_stub__printkPi
.p2align 4, 0x90
.type _Z21__device_stub__printkPi,@function
_Z21__device_stub__printkPi: # @_Z21__device_stub__printkPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z6printkPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z21__device_stub__printkPi, .Lfunc_end0-_Z21__device_stub__printkPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
leaq 8(%rsp), %rdi
movl $4, %esi
xorl %edx, %edx
callq hipHostAlloc
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z6printkPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.p2align 4, 0x90
.LBB1_2: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
movl (%rax), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
movl (%rdi), %eax
leal 1(%rax), %ecx
movl %ecx, (%rdi)
cmpl $9, %eax
jl .LBB1_2
# %bb.3:
callq hipHostFree
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6printkPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6printkPi,@object # @_Z6printkPi
.section .rodata,"a",@progbits
.globl _Z6printkPi
.p2align 3, 0x0
_Z6printkPi:
.quad _Z21__device_stub__printkPi
.size _Z6printkPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\n"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6printkPi"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__printkPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6printkPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda_runtime_api.h>
#include <time.h>
#include <pthread.h>
pthread_mutex_t mutex = PTHREAD_MUTEX_INITIALIZER;
__device__ int is_a_match (char *attempt) {
char plain_password1[] = "SH1234";
char plain_password2[] = "RE2345";
char plain_password3[] = "EJ3456";
char plain_password4[] = "AN4567";
char *a = attempt;
char *b = attempt;
char *c = attempt;
char *d = attempt;
char *p1 = plain_password1;
char *p2 = plain_password2;
char *p3 = plain_password3;
char *p4 = plain_password4;
while (*a == *p1) {
if (*a == '\0')
{
printf ("Password: %s\n", plain_password1);
break;
}
a++;
p1++;
}
while(*b == *p2) {
if(*b == '\0')
{
printf("Password: %s\n",plain_password2);
break;
}
b++;
p2++;
}
while(*c == *p3) {
if(*c == '\0')
{
printf("Password: %s\n",plain_password3);
break;
}
c++;
p3++;
}
while (*d == *p4) {
if (*d == '\0')
{
printf ("Password: %s\n", plain_password4);
return 1;
}
d++;
p4++;
}
return 0;
}
__global__ void kernel () {
char i1, i2, i3, i4;
char password [7];
password [6] = '\0';
int i = blockIdx.x+65;
int j = threadIdx.x+65;
char firstMatch = i;
char secondMatch = j;
password [0] = firstMatch;
password [1] = secondMatch;
for (i1='0'; i1<='9'; i1++) {
for (i2='0'; i2<='9'; i2++) {
for (i3='0'; i3<='9'; i3++) {
for (i4='0'; i4<='9'; i4++) {
password [2] = i1;
password [3] = i2;
password [4] = i3;
password [5] = i4;
if(is_a_match(password)) {
}
else {
//printf ("tried: %s\n", password);
}
}
}
}
}
}
int time_difference (struct timespec *start, struct timespec *finish, long long int *difference) {
long long int ds = finish->tv_sec - start->tv_sec;
long long int dn = finish->tv_nsec - start->tv_nsec;
if (dn < 0) {
ds--;
dn += 1000000000;
}
*difference = ds * 1000000000 + dn;
return! (*difference > 0);
}
int main () {
struct timespec start, finish;
long long int time_elapsed;
clock_gettime(CLOCK_MONOTONIC, &start);
pthread_mutex_lock(&mutex);
kernel <<<26,26>>>();
cudaThreadSynchronize();
pthread_mutex_unlock(&mutex);
clock_gettime(CLOCK_MONOTONIC, &finish);
time_difference(&start, &finish, &time_elapsed);
printf("Time elapsed was %lldns or %0.9lfs\n", time_elapsed, (time_elapsed/1.0e9));
return 0;
} | code for sm_80
Function : _Z6kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc600078e00ff */
/*0010*/ S2UR UR36, SR_CTAID.X ; /* 0x00000000002479c3 */
/* 0x000e220000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0030*/ IADD3 R1, R1, -0x30, RZ ; /* 0xffffffd001017810 */
/* 0x000fe20007ffe0ff */
/*0040*/ ULDC UR37, c[0x0][0x20] ; /* 0x0000080000257ab9 */
/* 0x000fe20000000800 */
/*0050*/ BSSY B10, 0xfc0 ; /* 0x00000f60000a7945 */
/* 0x000fe20003800000 */
/*0060*/ ULDC UR38, c[0x0][0x24] ; /* 0x0000090000267ab9 */
/* 0x000fe20000000800 */
/*0070*/ IMAD.MOV.U32 R22, RZ, RZ, 0x30 ; /* 0x00000030ff167424 */
/* 0x000fe200078e00ff */
/*0080*/ STL.U8 [R1+0x2e], RZ ; /* 0x00002eff01007387 */
/* 0x0005e20000100000 */
/*0090*/ R2UR UR49, R1 ; /* 0x00000000013173c2 */
/* 0x000ee200000e0000 */
/*00a0*/ IADD3 R23, R1.reuse, 0x7, RZ ; /* 0x0000000701177810 */
/* 0x040fe40007ffe0ff */
/*00b0*/ IADD3 R19, R1, 0xe, RZ ; /* 0x0000000e01137810 */
/* 0x000fe20007ffe0ff */
/*00c0*/ UIADD3 UR36, UR36, 0x41, URZ ; /* 0x0000004124247890 */
/* 0x001fe2000fffe03f */
/*00d0*/ IADD3 R0, R0, 0x41, RZ ; /* 0x0000004100007810 */
/* 0x002fca0007ffe0ff */
/*00e0*/ IMAD.U32 R2, RZ, RZ, UR36 ; /* 0x00000024ff027e24 */
/* 0x000fe2000f8e00ff */
/*00f0*/ STL.U8 [R1+0x29], R0 ; /* 0x0000290001007387 */
/* 0x0005e20000100000 */
/*0100*/ UIADD3 UR37, UP0, UR49, UR37, URZ ; /* 0x0000002531257290 */
/* 0x008fe4000ff1e03f */
/*0110*/ UIADD3 UR42, UR49, 0x15, URZ ; /* 0x00000015312a7890 */
/* 0x000fe2000fffe03f */
/*0120*/ STL.U8 [R1+0x28], R2 ; /* 0x0000280201007387 */
/* 0x0005e20000100000 */
/*0130*/ UIADD3.X UR38, URZ, UR38, URZ, UP0, !UPT ; /* 0x000000263f267290 */
/* 0x000fe400087fe43f */
/*0140*/ UIADD3 UR47, UP0, UR37, 0x7, URZ ; /* 0x00000007252f7890 */
/* 0x000fe4000ff1e03f */
/*0150*/ UIADD3 UR45, UP1, UR37, 0xe, URZ ; /* 0x0000000e252d7890 */
/* 0x000fc4000ff3e03f */
/*0160*/ UIADD3 UR43, UP2, UR37, 0x15, URZ ; /* 0x00000015252b7890 */
/* 0x000fe4000ff5e03f */
/*0170*/ UIADD3 UR40, UP3, UR37, 0x20, URZ ; /* 0x0000002025287890 */
/* 0x000fe4000ff7e03f */
/*0180*/ UIADD3 UR39, UR49, 0x28, URZ ; /* 0x0000002831277890 */
/* 0x000fe4000fffe03f */
/*0190*/ UIADD3.X UR48, URZ, UR38, URZ, UP0, !UPT ; /* 0x000000263f307290 */
/* 0x000fe400087fe43f */
/*01a0*/ UIADD3.X UR46, URZ, UR38, URZ, UP1, !UPT ; /* 0x000000263f2e7290 */
/* 0x000fe40008ffe43f */
/*01b0*/ UIADD3.X UR44, URZ, UR38, URZ, UP2, !UPT ; /* 0x000000263f2c7290 */
/* 0x000fc400097fe43f */
/*01c0*/ UIADD3.X UR41, URZ, UR38, URZ, UP3, !UPT ; /* 0x000000263f297290 */
/* 0x004fc80009ffe43f */
/*01d0*/ BSSY B9, 0xf60 ; /* 0x00000d8000097945 */
/* 0x000fe20003800000 */
/*01e0*/ IMAD.MOV.U32 R18, RZ, RZ, 0x30 ; /* 0x00000030ff127424 */
/* 0x001fce00078e00ff */
/*01f0*/ BSSY B8, 0xf00 ; /* 0x00000d0000087945 */
/* 0x000fe20003800000 */
/*0200*/ IMAD.MOV.U32 R16, RZ, RZ, 0x30 ; /* 0x00000030ff107424 */
/* 0x001fe400078e00ff */
/*0210*/ BSSY B7, 0xea0 ; /* 0x00000c8000077945 */
/* 0x000fe20003800000 */
/*0220*/ IMAD.MOV.U32 R2, RZ, RZ, 0x30 ; /* 0x00000030ff027424 */
/* 0x001fc800078e00ff */
/*0230*/ IMAD.MOV.U32 R3, RZ, RZ, 0x48 ; /* 0x00000048ff037424 */
/* 0x000fe200078e00ff */
/*0240*/ STL.U8 [R1+0x2a], R22 ; /* 0x00002a1601007387 */
/* 0x000fe20000100000 */
/*0250*/ IMAD.MOV.U32 R0, RZ, RZ, 0x53 ; /* 0x00000053ff007424 */
/* 0x000fe400078e00ff */
/*0260*/ IMAD.MOV.U32 R7, RZ, RZ, 0x34 ; /* 0x00000034ff077424 */
/* 0x000fe200078e00ff */
/*0270*/ STL.U8 [R1+0x1], R3 ; /* 0x0000010301007387 */
/* 0x0011e20000100000 */
/*0280*/ IMAD.MOV.U32 R9, RZ, RZ, 0x45 ; /* 0x00000045ff097424 */
/* 0x000fe400078e00ff */
/*0290*/ IMAD.MOV.U32 R8, RZ, RZ, 0x52 ; /* 0x00000052ff087424 */
/* 0x000fe200078e00ff */
/*02a0*/ STL.U8 [R1], R0 ; /* 0x0000000001007387 */
/* 0x0003e20000100000 */
/*02b0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x31 ; /* 0x00000031ff047424 */
/* 0x000fc400078e00ff */
/*02c0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x32 ; /* 0x00000032ff057424 */
/* 0x000fe200078e00ff */
/*02d0*/ STL.U8 [R1+0x5], R7 ; /* 0x0000050701007387 */
/* 0x000fe20000100000 */
/*02e0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x33 ; /* 0x00000033ff067424 */
/* 0x000fe200078e00ff */
/*02f0*/ PRMT R3, R9, 0x7610, R3 ; /* 0x0000761009037816 */
/* 0x001fe20000000003 */
/*0300*/ IMAD.U32 R17, RZ, RZ, UR36 ; /* 0x00000024ff117e24 */
/* 0x000fe2000f8e00ff */
/*0310*/ STL.U8 [R1+0xb], R7 ; /* 0x00000b0701007387 */
/* 0x000fe20000100000 */
/*0320*/ PRMT R0, R8, 0x7610, R0 ; /* 0x0000761008007816 */
/* 0x002fe20000000000 */
/*0330*/ IMAD.MOV.U32 R8, RZ, RZ, 0x37 ; /* 0x00000037ff087424 */
/* 0x000fe400078e00ff */
/*0340*/ STL.U8 [R1+0x11], R7 ; /* 0x0000110701007387 */
/* 0x000fe20000100000 */
/*0350*/ LOP3.LUT R17, R17, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff11117812 */
/* 0x000fc600078ec0ff */
/*0360*/ STL.U8 [R1+0x17], R7 ; /* 0x0000170701007387 */
/* 0x0001e20000100000 */
/*0370*/ ISETP.NE.AND P0, PT, R17, 0x53, PT ; /* 0x000000531100780c */
/* 0x000fc60003f05270 */
/*0380*/ STL.U8 [R1+0x8], R3 ; /* 0x0000080301007387 */
/* 0x000fe80000100000 */
/*0390*/ STL.U8 [R1+0xe], R3 ; /* 0x00000e0301007387 */
/* 0x0003e20000100000 */
/*03a0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4e ; /* 0x0000004eff077424 */
/* 0x001fc600078e00ff */
/*03b0*/ STL.U8 [R1+0x2], R4 ; /* 0x0000020401007387 */
/* 0x0001e80000100000 */
/*03c0*/ STL.U8 [R1+0x3], R5 ; /* 0x0000030501007387 */
/* 0x000fe20000100000 */
/*03d0*/ PRMT R3, R7, 0x7610, R3 ; /* 0x0000761007037816 */
/* 0x002fc60000000003 */
/*03e0*/ STL.U8 [R1+0x9], R5 ; /* 0x0000090501007387 */
/* 0x0003e20000100000 */
/*03f0*/ PRMT R7, R8, 0x7610, R7 ; /* 0x0000761008077816 */
/* 0x000fe20000000007 */
/*0400*/ IMAD.MOV.U32 R4, RZ, RZ, 0x35 ; /* 0x00000035ff047424 */
/* 0x001fe400078e00ff */
/*0410*/ STL.U8 [R1+0x4], R6 ; /* 0x0000040601007387 */
/* 0x000fe80000100000 */
/*0420*/ STL.U8 [R1+0xa], R6 ; /* 0x00000a0601007387 */
/* 0x000fe20000100000 */
/*0430*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4a ; /* 0x0000004aff057424 */
/* 0x002fc600078e00ff */
/*0440*/ STL.U8 [R1+0x10], R6 ; /* 0x0000100601007387 */
/* 0x0001e80000100000 */
/*0450*/ STL.U8 [R1+0xc], R4 ; /* 0x00000c0401007387 */
/* 0x000fe80000100000 */
/*0460*/ STL.U8 [R1+0x12], R4 ; /* 0x0000120401007387 */
/* 0x000fe20000100000 */
/*0470*/ IMAD.MOV.U32 R6, RZ, RZ, 0x36 ; /* 0x00000036ff067424 */
/* 0x001fc600078e00ff */
/*0480*/ STL.U8 [R1+0x18], R4 ; /* 0x0000180401007387 */
/* 0x000fe80000100000 */
/*0490*/ STL.U8 [R1+0xf], R5 ; /* 0x00000f0501007387 */
/* 0x000fe80000100000 */
/*04a0*/ STL.U8 [R1+0x13], R6 ; /* 0x0000130601007387 */
/* 0x000fe80000100000 */
/*04b0*/ STL.U8 [R1+0x19], R6 ; /* 0x0000190601007387 */
/* 0x000fe80000100000 */
/*04c0*/ STL.U8 [R1+0x16], R3 ; /* 0x0000160301007387 */
/* 0x000fe80000100000 */
/*04d0*/ STL.U8 [R1+0x1a], R7 ; /* 0x00001a0701007387 */
/* 0x000fe80000100000 */
/*04e0*/ STL.U8 [R1+0x2b], R18 ; /* 0x00002b1201007387 */
/* 0x000fe80000100000 */
/*04f0*/ STL.U8 [R1+0x2c], R16 ; /* 0x00002c1001007387 */
/* 0x000fe80000100000 */
/*0500*/ STL.U8 [R1+0x2d], R2 ; /* 0x00002d0201007387 */
/* 0x000fe80000100000 */
/*0510*/ STL.U8 [R1+0x6], RZ ; /* 0x000006ff01007387 */
/* 0x000fe80000100000 */
/*0520*/ STL.U8 [R1+0xd], RZ ; /* 0x00000dff01007387 */
/* 0x000fe80000100000 */
/*0530*/ STL.U8 [R1+0x14], RZ ; /* 0x000014ff01007387 */
/* 0x000fe80000100000 */
/*0540*/ STL.U8 [R1+0x1b], RZ ; /* 0x00001bff01007387 */
/* 0x000fe80000100000 */
/*0550*/ STL.U8 [R1+0x7], R0 ; /* 0x0000070001007387 */
/* 0x0001e40000100000 */
/*0560*/ IMAD.MOV.U32 R0, RZ, RZ, 0x41 ; /* 0x00000041ff007424 */
/* 0x001fca00078e00ff */
/*0570*/ STL.U8 [R1+0x15], R0 ; /* 0x0000150001007387 */
/* 0x0001e40000100000 */
/*0580*/ IMAD.MOV.U32 R0, RZ, RZ, 0x52 ; /* 0x00000052ff007424 */
/* 0x001fe200078e00ff */
/*0590*/ @P0 BRA 0x7b0 ; /* 0x0000021000000947 */
/* 0x000fea0003800000 */
/*05a0*/ BSSY B6, 0x7b0 ; /* 0x0000020000067945 */
/* 0x000fe20003800000 */
/*05b0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x53 ; /* 0x00000053ff047424 */
/* 0x000fe400078e00ff */
/*05c0*/ IMAD.U32 R6, RZ, RZ, UR39 ; /* 0x00000027ff067e24 */
/* 0x000fe4000f8e00ff */
/*05d0*/ IMAD.MOV.U32 R3, RZ, RZ, R1 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0001 */
/*05e0*/ LOP3.LUT P0, RZ, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04ff7812 */
/* 0x000fda000780c0ff */
/*05f0*/ @!P0 BRA 0x680 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0600*/ LDL.U8 R5, [R3+0x1] ; /* 0x0000010003057983 */
/* 0x0000a80000100000 */
/*0610*/ LDL.U8 R4, [R6+0x1] ; /* 0x0000010006047983 */
/* 0x000ea20000100000 */
/*0620*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x001fe40007ffe0ff */
/*0630*/ ISETP.NE.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x004fe40003f05270 */
/*0640*/ IADD3 R5, R6, 0x1, RZ ; /* 0x0000000106057810 */
/* 0x000fca0007ffe0ff */
/*0650*/ IMAD.MOV.U32 R6, RZ, RZ, R5 ; /* 0x000000ffff067224 */
/* 0x000fcc00078e0005 */
/*0660*/ @!P0 BRA 0x5e0 ; /* 0xffffff7000008947 */
/* 0x000fea000383ffff */
/*0670*/ BRA 0x7a0 ; /* 0x0000012000007947 */
/* 0x000fea0003800000 */
/*0680*/ MOV R8, 0x0 ; /* 0x0000000000087802 */
/* 0x000fe20000000f00 */
/*0690*/ IMAD.U32 R10, RZ, RZ, UR37 ; /* 0x00000025ff0a7e24 */
/* 0x000fe4000f8e00ff */
/*06a0*/ IMAD.U32 R11, RZ, RZ, UR38 ; /* 0x00000026ff0b7e24 */
/* 0x000fe4000f8e00ff */
/*06b0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*06c0*/ LDC.64 R8, c[0x4][R8] ; /* 0x0100000008087b82 */
/* 0x000e220000000a00 */
/*06d0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*06e0*/ STL.64 [R1+0x20], R10 ; /* 0x0000200a01007387 */
/* 0x0003e20000100a00 */
/*06f0*/ IMAD.U32 R6, RZ, RZ, UR40 ; /* 0x00000028ff067e24 */
/* 0x000fe4000f8e00ff */
/*0700*/ IMAD.U32 R7, RZ, RZ, UR41 ; /* 0x00000029ff077e24 */
/* 0x000fc6000f8e00ff */
/*0710*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x002fe20000000000 */
/*0720*/ MOV R3, 0x790 ; /* 0x0000079000037802 */
/* 0x000fc40000000f00 */
/*0730*/ MOV R20, 0x710 ; /* 0x0000071000147802 */
/* 0x000fe40000000f00 */
/*0740*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0750*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0760*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0770*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0780*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x001fea0003c00000 */
/*0790*/ LDL.U8 R0, [R1+0x7] ; /* 0x0000070001007983 */
/* 0x0001640000100000 */
/*07a0*/ BSYNC B6 ; /* 0x0000000000067941 */
/* 0x000fea0003800000 */
/*07b0*/ LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff00007812 */
/* 0x020fe200078ec0ff */
/*07c0*/ BSSY B6, 0x9e0 ; /* 0x0000021000067945 */
/* 0x000fe60003800000 */
/*07d0*/ ISETP.NE.AND P0, PT, R17, R0, PT ; /* 0x000000001100720c */
/* 0x000fda0003f05270 */
/*07e0*/ @P0 BRA 0x9d0 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*07f0*/ IMAD.U32 R0, RZ, RZ, UR36 ; /* 0x00000024ff007e24 */
/* 0x000fe4000f8e00ff */
/*0800*/ IMAD.U32 R4, RZ, RZ, UR39 ; /* 0x00000027ff047e24 */
/* 0x000fe4000f8e00ff */
/*0810*/ IMAD.MOV.U32 R5, RZ, RZ, R23 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0017 */
/*0820*/ LOP3.LUT P0, RZ, R0, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff00ff7812 */
/* 0x000fda000780c0ff */
/*0830*/ @!P0 BRA 0x8c0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0840*/ LDL.U8 R3, [R5+0x1] ; /* 0x0000010005037983 */
/* 0x000ea80000100000 */
/*0850*/ LDL.U8 R0, [R4+0x1] ; /* 0x0000010004007983 */
/* 0x0002a40000100000 */
/*0860*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x002fe40007ffe0ff */
/*0870*/ ISETP.NE.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x004fe40003f05270 */
/*0880*/ IADD3 R3, R5, 0x1, RZ ; /* 0x0000000105037810 */
/* 0x000fca0007ffe0ff */
/*0890*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fcc00078e0003 */
/*08a0*/ @!P0 BRA 0x820 ; /* 0xffffff7000008947 */
/* 0x000fea000383ffff */
/*08b0*/ BRA 0x9d0 ; /* 0x0000011000007947 */
/* 0x000fea0003800000 */
/*08c0*/ MOV R8, 0x0 ; /* 0x0000000000087802 */
/* 0x000fe20000000f00 */
/*08d0*/ IMAD.U32 R10, RZ, RZ, UR47 ; /* 0x0000002fff0a7e24 */
/* 0x000fe4000f8e00ff */
/*08e0*/ IMAD.U32 R11, RZ, RZ, UR48 ; /* 0x00000030ff0b7e24 */
/* 0x000fe4000f8e00ff */
/*08f0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0900*/ LDC.64 R8, c[0x4][R8] ; /* 0x0100000008087b82 */
/* 0x000e620000000a00 */
/*0910*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0920*/ STL.64 [R1+0x20], R10 ; /* 0x0000200a01007387 */
/* 0x0005e20000100a00 */
/*0930*/ IMAD.U32 R6, RZ, RZ, UR40 ; /* 0x00000028ff067e24 */
/* 0x000fe4000f8e00ff */
/*0940*/ IMAD.U32 R7, RZ, RZ, UR41 ; /* 0x00000029ff077e24 */
/* 0x000fc6000f8e00ff */
/*0950*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x004fe20000000000 */
/*0960*/ MOV R3, 0x9d0 ; /* 0x000009d000037802 */
/* 0x000fc40000000f00 */
/*0970*/ MOV R20, 0x950 ; /* 0x0000095000147802 */
/* 0x000fe40000000f00 */
/*0980*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0990*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*09a0*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*09b0*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*09c0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x003fea0003c00000 */
/*09d0*/ BSYNC B6 ; /* 0x0000000000067941 */
/* 0x000fea0003800000 */
/*09e0*/ LDL.U8 R0, [R1+0xe] ; /* 0x00000e0001007983 */
/* 0x000ea20000100000 */
/*09f0*/ BSSY B6, 0xc10 ; /* 0x0000021000067945 */
/* 0x000fe20003800000 */
/*0a00*/ ISETP.NE.AND P0, PT, R17, R0, PT ; /* 0x000000001100720c */
/* 0x004fda0003f05270 */
/*0a10*/ @P0 BRA 0xc00 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*0a20*/ IMAD.U32 R0, RZ, RZ, UR36 ; /* 0x00000024ff007e24 */
/* 0x000fe4000f8e00ff */
/*0a30*/ IMAD.U32 R4, RZ, RZ, UR39 ; /* 0x00000027ff047e24 */
/* 0x000fe4000f8e00ff */
/*0a40*/ IMAD.MOV.U32 R5, RZ, RZ, R19 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0013 */
/*0a50*/ LOP3.LUT P0, RZ, R0, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff00ff7812 */
/* 0x000fda000780c0ff */
/*0a60*/ @!P0 BRA 0xaf0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0a70*/ LDL.U8 R3, [R5+0x1] ; /* 0x0000010005037983 */
/* 0x000ea80000100000 */
/*0a80*/ LDL.U8 R0, [R4+0x1] ; /* 0x0000010004007983 */
/* 0x0002a40000100000 */
/*0a90*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x002fe40007ffe0ff */
/*0aa0*/ ISETP.NE.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x004fe40003f05270 */
/*0ab0*/ IADD3 R3, R5, 0x1, RZ ; /* 0x0000000105037810 */
/* 0x000fca0007ffe0ff */
/*0ac0*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fcc00078e0003 */
/*0ad0*/ @!P0 BRA 0xa50 ; /* 0xffffff7000008947 */
/* 0x000fea000383ffff */
/*0ae0*/ BRA 0xc00 ; /* 0x0000011000007947 */
/* 0x000fea0003800000 */
/*0af0*/ MOV R8, 0x0 ; /* 0x0000000000087802 */
/* 0x000fe20000000f00 */
/*0b00*/ IMAD.U32 R10, RZ, RZ, UR45 ; /* 0x0000002dff0a7e24 */
/* 0x000fe4000f8e00ff */
/*0b10*/ IMAD.U32 R11, RZ, RZ, UR46 ; /* 0x0000002eff0b7e24 */
/* 0x000fe4000f8e00ff */
/*0b20*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0b30*/ LDC.64 R8, c[0x4][R8] ; /* 0x0100000008087b82 */
/* 0x000e620000000a00 */
/*0b40*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0b50*/ STL.64 [R1+0x20], R10 ; /* 0x0000200a01007387 */
/* 0x0005e20000100a00 */
/*0b60*/ IMAD.U32 R6, RZ, RZ, UR40 ; /* 0x00000028ff067e24 */
/* 0x000fe4000f8e00ff */
/*0b70*/ IMAD.U32 R7, RZ, RZ, UR41 ; /* 0x00000029ff077e24 */
/* 0x000fc6000f8e00ff */
/*0b80*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x004fe20000000000 */
/*0b90*/ MOV R3, 0xc00 ; /* 0x00000c0000037802 */
/* 0x000fc40000000f00 */
/*0ba0*/ MOV R20, 0xb80 ; /* 0x00000b8000147802 */
/* 0x000fe40000000f00 */
/*0bb0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0bc0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0bd0*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0be0*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0bf0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x003fea0003c00000 */
/*0c00*/ BSYNC B6 ; /* 0x0000000000067941 */
/* 0x000fea0003800000 */
/*0c10*/ LDL.U8 R0, [R1+0x15] ; /* 0x0000150001007983 */
/* 0x000ea20000100000 */
/*0c20*/ BSSY B6, 0xe40 ; /* 0x0000021000067945 */
/* 0x000fe20003800000 */
/*0c30*/ ISETP.NE.AND P0, PT, R17, R0, PT ; /* 0x000000001100720c */
/* 0x004fda0003f05270 */
/*0c40*/ @P0 BRA 0xe30 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*0c50*/ IMAD.U32 R0, RZ, RZ, UR36 ; /* 0x00000024ff007e24 */
/* 0x000fe4000f8e00ff */
/*0c60*/ IMAD.U32 R5, RZ, RZ, UR42 ; /* 0x0000002aff057e24 */
/* 0x000fe4000f8e00ff */
/*0c70*/ IMAD.U32 R4, RZ, RZ, UR39 ; /* 0x00000027ff047e24 */
/* 0x000fe4000f8e00ff */
/*0c80*/ LOP3.LUT P0, RZ, R0, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff00ff7812 */
/* 0x000fda000780c0ff */
/*0c90*/ @!P0 BRA 0xd20 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0ca0*/ LDL.U8 R3, [R5+0x1] ; /* 0x0000010005037983 */
/* 0x000ea80000100000 */
/*0cb0*/ LDL.U8 R0, [R4+0x1] ; /* 0x0000010004007983 */
/* 0x0002a40000100000 */
/*0cc0*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x002fe40007ffe0ff */
/*0cd0*/ ISETP.NE.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x004fe40003f05270 */
/*0ce0*/ IADD3 R3, R5, 0x1, RZ ; /* 0x0000000105037810 */
/* 0x000fca0007ffe0ff */
/*0cf0*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fcc00078e0003 */
/*0d00*/ @!P0 BRA 0xc80 ; /* 0xffffff7000008947 */
/* 0x000fea000383ffff */
/*0d10*/ BRA 0xe30 ; /* 0x0000011000007947 */
/* 0x000fea0003800000 */
/*0d20*/ MOV R8, 0x0 ; /* 0x0000000000087802 */
/* 0x000fe20000000f00 */
/*0d30*/ IMAD.U32 R10, RZ, RZ, UR43 ; /* 0x0000002bff0a7e24 */
/* 0x000fe4000f8e00ff */
/*0d40*/ IMAD.U32 R11, RZ, RZ, UR44 ; /* 0x0000002cff0b7e24 */
/* 0x000fe4000f8e00ff */
/*0d50*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0d60*/ LDC.64 R8, c[0x4][R8] ; /* 0x0100000008087b82 */
/* 0x000e620000000a00 */
/*0d70*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0d80*/ STL.64 [R1+0x20], R10 ; /* 0x0000200a01007387 */
/* 0x0005e20000100a00 */
/*0d90*/ IMAD.U32 R6, RZ, RZ, UR40 ; /* 0x00000028ff067e24 */
/* 0x000fe4000f8e00ff */
/*0da0*/ IMAD.U32 R7, RZ, RZ, UR41 ; /* 0x00000029ff077e24 */
/* 0x000fc6000f8e00ff */
/*0db0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x004fe20000000000 */
/*0dc0*/ MOV R3, 0xe30 ; /* 0x00000e3000037802 */
/* 0x000fc40000000f00 */
/*0dd0*/ MOV R20, 0xdb0 ; /* 0x00000db000147802 */
/* 0x000fe40000000f00 */
/*0de0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0df0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0e00*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0e10*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0e20*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x003fea0003c00000 */
/*0e30*/ BSYNC B6 ; /* 0x0000000000067941 */
/* 0x000fea0003800000 */
/*0e40*/ IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x000fc80007ffe0ff */
/*0e50*/ LOP3.LUT R0, R2, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff02007812 */
/* 0x000fc800078ec0ff */
/*0e60*/ ISETP.GE.U32.AND P0, PT, R0, 0x3a, PT ; /* 0x0000003a0000780c */
/* 0x000fda0003f06070 */
/*0e70*/ @P0 CALL.REL.NOINC 0xe90 ; /* 0x0000001000000944 */
/* 0x000fe20003c00000 */
/*0e80*/ BRA 0x230 ; /* 0xfffff3a000007947 */
/* 0x000fea000383ffff */
/*0e90*/ BSYNC B7 ; /* 0x0000000000077941 */
/* 0x000fea0003800000 */
/*0ea0*/ IADD3 R16, R16, 0x1, RZ ; /* 0x0000000110107810 */
/* 0x000fc80007ffe0ff */
/*0eb0*/ LOP3.LUT R0, R16, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff10007812 */
/* 0x000fc800078ec0ff */
/*0ec0*/ ISETP.GE.U32.AND P0, PT, R0, 0x3a, PT ; /* 0x0000003a0000780c */
/* 0x000fda0003f06070 */
/*0ed0*/ @P0 CALL.REL.NOINC 0xef0 ; /* 0x0000001000000944 */
/* 0x000fe20003c00000 */
/*0ee0*/ BRA 0x210 ; /* 0xfffff32000007947 */
/* 0x000fea000383ffff */
/*0ef0*/ BSYNC B8 ; /* 0x0000000000087941 */
/* 0x000fea0003800000 */
/*0f00*/ IADD3 R18, R18, 0x1, RZ ; /* 0x0000000112127810 */
/* 0x000fc80007ffe0ff */
/*0f10*/ LOP3.LUT R0, R18, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff12007812 */
/* 0x000fc800078ec0ff */
/*0f20*/ ISETP.GE.U32.AND P0, PT, R0, 0x3a, PT ; /* 0x0000003a0000780c */
/* 0x000fda0003f06070 */
/*0f30*/ @P0 CALL.REL.NOINC 0xf50 ; /* 0x0000001000000944 */
/* 0x000fe20003c00000 */
/*0f40*/ BRA 0x1f0 ; /* 0xfffff2a000007947 */
/* 0x000fea000383ffff */
/*0f50*/ BSYNC B9 ; /* 0x0000000000097941 */
/* 0x000fea0003800000 */
/*0f60*/ IADD3 R22, R22, 0x1, RZ ; /* 0x0000000116167810 */
/* 0x000fc80007ffe0ff */
/*0f70*/ LOP3.LUT R0, R22, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff16007812 */
/* 0x000fc800078ec0ff */
/*0f80*/ ISETP.GE.U32.AND P0, PT, R0, 0x3a, PT ; /* 0x0000003a0000780c */
/* 0x000fda0003f06070 */
/*0f90*/ @P0 CALL.REL.NOINC 0xfb0 ; /* 0x0000001000000944 */
/* 0x000fe20003c00000 */
/*0fa0*/ BRA 0x1d0 ; /* 0xfffff22000007947 */
/* 0x000fea000383ffff */
/*0fb0*/ BSYNC B10 ; /* 0x00000000000a7941 */
/* 0x000fea0003800000 */
/*0fc0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0fd0*/ BRA 0xfd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0fe0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime_api.h>
#include <time.h>
#include <pthread.h>
pthread_mutex_t mutex = PTHREAD_MUTEX_INITIALIZER;
__device__ int is_a_match (char *attempt) {
char plain_password1[] = "SH1234";
char plain_password2[] = "RE2345";
char plain_password3[] = "EJ3456";
char plain_password4[] = "AN4567";
char *a = attempt;
char *b = attempt;
char *c = attempt;
char *d = attempt;
char *p1 = plain_password1;
char *p2 = plain_password2;
char *p3 = plain_password3;
char *p4 = plain_password4;
while (*a == *p1) {
if (*a == '\0')
{
printf ("Password: %s\n", plain_password1);
break;
}
a++;
p1++;
}
while(*b == *p2) {
if(*b == '\0')
{
printf("Password: %s\n",plain_password2);
break;
}
b++;
p2++;
}
while(*c == *p3) {
if(*c == '\0')
{
printf("Password: %s\n",plain_password3);
break;
}
c++;
p3++;
}
while (*d == *p4) {
if (*d == '\0')
{
printf ("Password: %s\n", plain_password4);
return 1;
}
d++;
p4++;
}
return 0;
}
__global__ void kernel () {
char i1, i2, i3, i4;
char password [7];
password [6] = '\0';
int i = blockIdx.x+65;
int j = threadIdx.x+65;
char firstMatch = i;
char secondMatch = j;
password [0] = firstMatch;
password [1] = secondMatch;
for (i1='0'; i1<='9'; i1++) {
for (i2='0'; i2<='9'; i2++) {
for (i3='0'; i3<='9'; i3++) {
for (i4='0'; i4<='9'; i4++) {
password [2] = i1;
password [3] = i2;
password [4] = i3;
password [5] = i4;
if(is_a_match(password)) {
}
else {
//printf ("tried: %s\n", password);
}
}
}
}
}
}
int time_difference (struct timespec *start, struct timespec *finish, long long int *difference) {
long long int ds = finish->tv_sec - start->tv_sec;
long long int dn = finish->tv_nsec - start->tv_nsec;
if (dn < 0) {
ds--;
dn += 1000000000;
}
*difference = ds * 1000000000 + dn;
return! (*difference > 0);
}
int main () {
struct timespec start, finish;
long long int time_elapsed;
clock_gettime(CLOCK_MONOTONIC, &start);
pthread_mutex_lock(&mutex);
kernel <<<26,26>>>();
cudaThreadSynchronize();
pthread_mutex_unlock(&mutex);
clock_gettime(CLOCK_MONOTONIC, &finish);
time_difference(&start, &finish, &time_elapsed);
printf("Time elapsed was %lldns or %0.9lfs\n", time_elapsed, (time_elapsed/1.0e9));
return 0;
} | .file "tmpxft_00174a9a_00000000-6_Shishir_Ko_CUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2072:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2072:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10is_a_matchPc
.type _Z10is_a_matchPc, @function
_Z10is_a_matchPc:
.LFB2067:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2067:
.size _Z10is_a_matchPc, .-_Z10is_a_matchPc
.globl _Z15time_differenceP8timespecS0_Px
.type _Z15time_differenceP8timespecS0_Px, @function
_Z15time_differenceP8timespecS0_Px:
.LFB2068:
.cfi_startproc
endbr64
movq (%rsi), %rax
subq (%rdi), %rax
movq 8(%rsi), %rcx
subq 8(%rdi), %rcx
js .L7
.L6:
imulq $1000000000, %rax, %rax
addq %rcx, %rax
movq %rax, (%rdx)
testq %rax, %rax
setle %al
movzbl %al, %eax
ret
.L7:
subq $1, %rax
addq $1000000000, %rcx
jmp .L6
.cfi_endproc
.LFE2068:
.size _Z15time_differenceP8timespecS0_Px, .-_Z15time_differenceP8timespecS0_Px
.globl _Z24__device_stub__Z6kernelvv
.type _Z24__device_stub__Z6kernelvv, @function
_Z24__device_stub__Z6kernelvv:
.LFB2094:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2094:
.size _Z24__device_stub__Z6kernelvv, .-_Z24__device_stub__Z6kernelvv
.globl _Z6kernelv
.type _Z6kernelv, @function
_Z6kernelv:
.LFB2095:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z6kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _Z6kernelv, .-_Z6kernelv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Time elapsed was %lldns or %0.9lfs\n"
.text
.globl main
.type main, @function
main:
.LFB2069:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rsi
movl $1, %edi
call clock_gettime@PLT
leaq mutex(%rip), %rdi
call pthread_mutex_lock@PLT
movl $26, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $26, (%rsp)
movl $1, 4(%rsp)
movl $1, 8(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq (%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L17:
call cudaThreadSynchronize@PLT
leaq mutex(%rip), %rdi
call pthread_mutex_unlock@PLT
leaq 32(%rsp), %rbx
movq %rbx, %rsi
movl $1, %edi
call clock_gettime@PLT
movq %rsp, %rdx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call _Z15time_differenceP8timespecS0_Px
movq (%rsp), %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
divsd .LC0(%rip), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call _Z24__device_stub__Z6kernelvv
jmp .L17
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2069:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z6kernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl mutex
.bss
.align 32
.type mutex, @object
.size mutex, 40
mutex:
.zero 40
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime_api.h>
#include <time.h>
#include <pthread.h>
pthread_mutex_t mutex = PTHREAD_MUTEX_INITIALIZER;
__device__ int is_a_match (char *attempt) {
char plain_password1[] = "SH1234";
char plain_password2[] = "RE2345";
char plain_password3[] = "EJ3456";
char plain_password4[] = "AN4567";
char *a = attempt;
char *b = attempt;
char *c = attempt;
char *d = attempt;
char *p1 = plain_password1;
char *p2 = plain_password2;
char *p3 = plain_password3;
char *p4 = plain_password4;
while (*a == *p1) {
if (*a == '\0')
{
printf ("Password: %s\n", plain_password1);
break;
}
a++;
p1++;
}
while(*b == *p2) {
if(*b == '\0')
{
printf("Password: %s\n",plain_password2);
break;
}
b++;
p2++;
}
while(*c == *p3) {
if(*c == '\0')
{
printf("Password: %s\n",plain_password3);
break;
}
c++;
p3++;
}
while (*d == *p4) {
if (*d == '\0')
{
printf ("Password: %s\n", plain_password4);
return 1;
}
d++;
p4++;
}
return 0;
}
__global__ void kernel () {
char i1, i2, i3, i4;
char password [7];
password [6] = '\0';
int i = blockIdx.x+65;
int j = threadIdx.x+65;
char firstMatch = i;
char secondMatch = j;
password [0] = firstMatch;
password [1] = secondMatch;
for (i1='0'; i1<='9'; i1++) {
for (i2='0'; i2<='9'; i2++) {
for (i3='0'; i3<='9'; i3++) {
for (i4='0'; i4<='9'; i4++) {
password [2] = i1;
password [3] = i2;
password [4] = i3;
password [5] = i4;
if(is_a_match(password)) {
}
else {
//printf ("tried: %s\n", password);
}
}
}
}
}
}
int time_difference (struct timespec *start, struct timespec *finish, long long int *difference) {
long long int ds = finish->tv_sec - start->tv_sec;
long long int dn = finish->tv_nsec - start->tv_nsec;
if (dn < 0) {
ds--;
dn += 1000000000;
}
*difference = ds * 1000000000 + dn;
return! (*difference > 0);
}
int main () {
struct timespec start, finish;
long long int time_elapsed;
clock_gettime(CLOCK_MONOTONIC, &start);
pthread_mutex_lock(&mutex);
kernel <<<26,26>>>();
cudaThreadSynchronize();
pthread_mutex_unlock(&mutex);
clock_gettime(CLOCK_MONOTONIC, &finish);
time_difference(&start, &finish, &time_elapsed);
printf("Time elapsed was %lldns or %0.9lfs\n", time_elapsed, (time_elapsed/1.0e9));
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <hip/hip_runtime_api.h>
#include <time.h>
#include <pthread.h>
pthread_mutex_t mutex = PTHREAD_MUTEX_INITIALIZER;
__device__ int is_a_match (char *attempt) {
char plain_password1[] = "SH1234";
char plain_password2[] = "RE2345";
char plain_password3[] = "EJ3456";
char plain_password4[] = "AN4567";
char *a = attempt;
char *b = attempt;
char *c = attempt;
char *d = attempt;
char *p1 = plain_password1;
char *p2 = plain_password2;
char *p3 = plain_password3;
char *p4 = plain_password4;
while (*a == *p1) {
if (*a == '\0')
{
printf ("Password: %s\n", plain_password1);
break;
}
a++;
p1++;
}
while(*b == *p2) {
if(*b == '\0')
{
printf("Password: %s\n",plain_password2);
break;
}
b++;
p2++;
}
while(*c == *p3) {
if(*c == '\0')
{
printf("Password: %s\n",plain_password3);
break;
}
c++;
p3++;
}
while (*d == *p4) {
if (*d == '\0')
{
printf ("Password: %s\n", plain_password4);
return 1;
}
d++;
p4++;
}
return 0;
}
__global__ void kernel () {
char i1, i2, i3, i4;
char password [7];
password [6] = '\0';
int i = blockIdx.x+65;
int j = threadIdx.x+65;
char firstMatch = i;
char secondMatch = j;
password [0] = firstMatch;
password [1] = secondMatch;
for (i1='0'; i1<='9'; i1++) {
for (i2='0'; i2<='9'; i2++) {
for (i3='0'; i3<='9'; i3++) {
for (i4='0'; i4<='9'; i4++) {
password [2] = i1;
password [3] = i2;
password [4] = i3;
password [5] = i4;
if(is_a_match(password)) {
}
else {
//printf ("tried: %s\n", password);
}
}
}
}
}
}
int time_difference (struct timespec *start, struct timespec *finish, long long int *difference) {
long long int ds = finish->tv_sec - start->tv_sec;
long long int dn = finish->tv_nsec - start->tv_nsec;
if (dn < 0) {
ds--;
dn += 1000000000;
}
*difference = ds * 1000000000 + dn;
return! (*difference > 0);
}
int main () {
struct timespec start, finish;
long long int time_elapsed;
clock_gettime(CLOCK_MONOTONIC, &start);
pthread_mutex_lock(&mutex);
kernel <<<26,26>>>();
hipDeviceSynchronize();
pthread_mutex_unlock(&mutex);
clock_gettime(CLOCK_MONOTONIC, &finish);
time_difference(&start, &finish, &time_elapsed);
printf("Time elapsed was %lldns or %0.9lfs\n", time_elapsed, (time_elapsed/1.0e9));
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <hip/hip_runtime_api.h>
#include <time.h>
#include <pthread.h>
pthread_mutex_t mutex = PTHREAD_MUTEX_INITIALIZER;
__device__ int is_a_match (char *attempt) {
char plain_password1[] = "SH1234";
char plain_password2[] = "RE2345";
char plain_password3[] = "EJ3456";
char plain_password4[] = "AN4567";
char *a = attempt;
char *b = attempt;
char *c = attempt;
char *d = attempt;
char *p1 = plain_password1;
char *p2 = plain_password2;
char *p3 = plain_password3;
char *p4 = plain_password4;
while (*a == *p1) {
if (*a == '\0')
{
printf ("Password: %s\n", plain_password1);
break;
}
a++;
p1++;
}
while(*b == *p2) {
if(*b == '\0')
{
printf("Password: %s\n",plain_password2);
break;
}
b++;
p2++;
}
while(*c == *p3) {
if(*c == '\0')
{
printf("Password: %s\n",plain_password3);
break;
}
c++;
p3++;
}
while (*d == *p4) {
if (*d == '\0')
{
printf ("Password: %s\n", plain_password4);
return 1;
}
d++;
p4++;
}
return 0;
}
__global__ void kernel () {
char i1, i2, i3, i4;
char password [7];
password [6] = '\0';
int i = blockIdx.x+65;
int j = threadIdx.x+65;
char firstMatch = i;
char secondMatch = j;
password [0] = firstMatch;
password [1] = secondMatch;
for (i1='0'; i1<='9'; i1++) {
for (i2='0'; i2<='9'; i2++) {
for (i3='0'; i3<='9'; i3++) {
for (i4='0'; i4<='9'; i4++) {
password [2] = i1;
password [3] = i2;
password [4] = i3;
password [5] = i4;
if(is_a_match(password)) {
}
else {
//printf ("tried: %s\n", password);
}
}
}
}
}
}
int time_difference (struct timespec *start, struct timespec *finish, long long int *difference) {
long long int ds = finish->tv_sec - start->tv_sec;
long long int dn = finish->tv_nsec - start->tv_nsec;
if (dn < 0) {
ds--;
dn += 1000000000;
}
*difference = ds * 1000000000 + dn;
return! (*difference > 0);
}
int main () {
struct timespec start, finish;
long long int time_elapsed;
clock_gettime(CLOCK_MONOTONIC, &start);
pthread_mutex_lock(&mutex);
kernel <<<26,26>>>();
hipDeviceSynchronize();
pthread_mutex_unlock(&mutex);
clock_gettime(CLOCK_MONOTONIC, &finish);
time_difference(&start, &finish, &time_elapsed);
printf("Time elapsed was %lldns or %0.9lfs\n", time_elapsed, (time_elapsed/1.0e9));
return 0;
} | .text
.file "Shishir_Ko_CUDA.hip"
.globl _Z21__device_stub__kernelv # -- Begin function _Z21__device_stub__kernelv
.p2align 4, 0x90
.type _Z21__device_stub__kernelv,@function
_Z21__device_stub__kernelv: # @_Z21__device_stub__kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelv, .Lfunc_end0-_Z21__device_stub__kernelv
.cfi_endproc
# -- End function
.globl _Z15time_differenceP8timespecS0_Px # -- Begin function _Z15time_differenceP8timespecS0_Px
.p2align 4, 0x90
.type _Z15time_differenceP8timespecS0_Px,@function
_Z15time_differenceP8timespecS0_Px: # @_Z15time_differenceP8timespecS0_Px
.cfi_startproc
# %bb.0:
movq (%rsi), %rax
subq (%rdi), %rax
movq 8(%rsi), %rcx
subq 8(%rdi), %rcx
leaq 1000000000(%rcx), %rsi
movq %rcx, %rdi
sarq $63, %rdi
addq %rax, %rdi
testq %rcx, %rcx
cmovnsq %rcx, %rsi
imulq $1000000000, %rdi, %rcx # imm = 0x3B9ACA00
xorl %eax, %eax
addq %rsi, %rcx
movq %rcx, (%rdx)
setle %al
retq
.Lfunc_end1:
.size _Z15time_differenceP8timespecS0_Px, .Lfunc_end1-_Z15time_differenceP8timespecS0_Px
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
leaq 48(%rsp), %rsi
movl $1, %edi
callq clock_gettime
movl $mutex, %edi
callq pthread_mutex_lock
movabsq $4294967322, %rdi # imm = 0x10000001A
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq %rsp, %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelv, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
movl $mutex, %edi
callq pthread_mutex_unlock
movq %rsp, %rsi
movl $1, %edi
callq clock_gettime
movq (%rsp), %rax
subq 48(%rsp), %rax
movq 8(%rsp), %rcx
subq 56(%rsp), %rcx
leaq 1000000000(%rcx), %rdx
movq %rcx, %rsi
sarq $63, %rsi
addq %rax, %rsi
testq %rcx, %rcx
cmovnsq %rcx, %rdx
imulq $1000000000, %rsi, %rsi # imm = 0x3B9ACA00
addq %rdx, %rsi
cvtsi2sd %rsi, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type mutex,@object # @mutex
.bss
.globl mutex
.p2align 3, 0x0
mutex:
.zero 40
.size mutex, 40
.type _Z6kernelv,@object # @_Z6kernelv
.section .rodata,"a",@progbits
.globl _Z6kernelv
.p2align 3, 0x0
_Z6kernelv:
.quad _Z21__device_stub__kernelv
.size _Z6kernelv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time elapsed was %lldns or %0.9lfs\n"
.size .L.str, 36
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelv"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym mutex
.addrsig_sym _Z6kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00174a9a_00000000-6_Shishir_Ko_CUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2072:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2072:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10is_a_matchPc
.type _Z10is_a_matchPc, @function
_Z10is_a_matchPc:
.LFB2067:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2067:
.size _Z10is_a_matchPc, .-_Z10is_a_matchPc
.globl _Z15time_differenceP8timespecS0_Px
.type _Z15time_differenceP8timespecS0_Px, @function
_Z15time_differenceP8timespecS0_Px:
.LFB2068:
.cfi_startproc
endbr64
movq (%rsi), %rax
subq (%rdi), %rax
movq 8(%rsi), %rcx
subq 8(%rdi), %rcx
js .L7
.L6:
imulq $1000000000, %rax, %rax
addq %rcx, %rax
movq %rax, (%rdx)
testq %rax, %rax
setle %al
movzbl %al, %eax
ret
.L7:
subq $1, %rax
addq $1000000000, %rcx
jmp .L6
.cfi_endproc
.LFE2068:
.size _Z15time_differenceP8timespecS0_Px, .-_Z15time_differenceP8timespecS0_Px
.globl _Z24__device_stub__Z6kernelvv
.type _Z24__device_stub__Z6kernelvv, @function
_Z24__device_stub__Z6kernelvv:
.LFB2094:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2094:
.size _Z24__device_stub__Z6kernelvv, .-_Z24__device_stub__Z6kernelvv
.globl _Z6kernelv
.type _Z6kernelv, @function
_Z6kernelv:
.LFB2095:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z6kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _Z6kernelv, .-_Z6kernelv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Time elapsed was %lldns or %0.9lfs\n"
.text
.globl main
.type main, @function
main:
.LFB2069:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rsi
movl $1, %edi
call clock_gettime@PLT
leaq mutex(%rip), %rdi
call pthread_mutex_lock@PLT
movl $26, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $26, (%rsp)
movl $1, 4(%rsp)
movl $1, 8(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq (%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L17:
call cudaThreadSynchronize@PLT
leaq mutex(%rip), %rdi
call pthread_mutex_unlock@PLT
leaq 32(%rsp), %rbx
movq %rbx, %rsi
movl $1, %edi
call clock_gettime@PLT
movq %rsp, %rdx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call _Z15time_differenceP8timespecS0_Px
movq (%rsp), %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
divsd .LC0(%rip), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call _Z24__device_stub__Z6kernelvv
jmp .L17
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2069:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z6kernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl mutex
.bss
.align 32
.type mutex, @object
.size mutex, 40
mutex:
.zero 40
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Shishir_Ko_CUDA.hip"
.globl _Z21__device_stub__kernelv # -- Begin function _Z21__device_stub__kernelv
.p2align 4, 0x90
.type _Z21__device_stub__kernelv,@function
_Z21__device_stub__kernelv: # @_Z21__device_stub__kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelv, .Lfunc_end0-_Z21__device_stub__kernelv
.cfi_endproc
# -- End function
.globl _Z15time_differenceP8timespecS0_Px # -- Begin function _Z15time_differenceP8timespecS0_Px
.p2align 4, 0x90
.type _Z15time_differenceP8timespecS0_Px,@function
_Z15time_differenceP8timespecS0_Px: # @_Z15time_differenceP8timespecS0_Px
.cfi_startproc
# %bb.0:
movq (%rsi), %rax
subq (%rdi), %rax
movq 8(%rsi), %rcx
subq 8(%rdi), %rcx
leaq 1000000000(%rcx), %rsi
movq %rcx, %rdi
sarq $63, %rdi
addq %rax, %rdi
testq %rcx, %rcx
cmovnsq %rcx, %rsi
imulq $1000000000, %rdi, %rcx # imm = 0x3B9ACA00
xorl %eax, %eax
addq %rsi, %rcx
movq %rcx, (%rdx)
setle %al
retq
.Lfunc_end1:
.size _Z15time_differenceP8timespecS0_Px, .Lfunc_end1-_Z15time_differenceP8timespecS0_Px
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
leaq 48(%rsp), %rsi
movl $1, %edi
callq clock_gettime
movl $mutex, %edi
callq pthread_mutex_lock
movabsq $4294967322, %rdi # imm = 0x10000001A
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq %rsp, %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6kernelv, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
movl $mutex, %edi
callq pthread_mutex_unlock
movq %rsp, %rsi
movl $1, %edi
callq clock_gettime
movq (%rsp), %rax
subq 48(%rsp), %rax
movq 8(%rsp), %rcx
subq 56(%rsp), %rcx
leaq 1000000000(%rcx), %rdx
movq %rcx, %rsi
sarq $63, %rsi
addq %rax, %rsi
testq %rcx, %rcx
cmovnsq %rcx, %rdx
imulq $1000000000, %rsi, %rsi # imm = 0x3B9ACA00
addq %rdx, %rsi
cvtsi2sd %rsi, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type mutex,@object # @mutex
.bss
.globl mutex
.p2align 3, 0x0
mutex:
.zero 40
.size mutex, 40
.type _Z6kernelv,@object # @_Z6kernelv
.section .rodata,"a",@progbits
.globl _Z6kernelv
.p2align 3, 0x0
_Z6kernelv:
.quad _Z21__device_stub__kernelv
.size _Z6kernelv, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Time elapsed was %lldns or %0.9lfs\n"
.size .L.str, 36
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelv"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym mutex
.addrsig_sym _Z6kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void DrawRgbaTextureKernel(float *target, int targetWidth, int targetHeight, int inputX, int inputY, float *texture, int textureWidth, int textureHeight)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
int targetPixels = targetWidth * targetHeight;
int texturePixels = textureWidth * textureHeight;
int idTextureRgb = id / texturePixels;
int idTexturePixel = (id - idTextureRgb * texturePixels); // same as (id % texturePixels), but the kernel runs 10% faster
int idTextureY = idTexturePixel / textureWidth;
int idTextureX = (idTexturePixel - idTextureY * textureWidth); // same as (id % textureWidth), but the kernel runs another 10% faster
if (idTextureRgb < 3) // 3 channels that we will write to
{
// the texture is in BGR format, we want RGB
switch (idTextureRgb)
{
case 0: // R
idTextureRgb = 2; // B
break;
case 2: // B
idTextureRgb = 0; // R
break;
}
// if the texture pixel offset by inputX, inputY, lies inside the target
if (idTextureX + inputX < targetWidth &&
idTextureX + inputX >= 0 &&
idTextureY + inputY < targetHeight &&
idTextureY + inputY >= 0)
{
int tIndex = targetPixels * idTextureRgb + targetWidth * (idTextureY + inputY) + (idTextureX + inputX);
int aIndex = idTexturePixel + 3 * texturePixels; // the A component of the texture
float a = texture[aIndex];
target[tIndex] = target[tIndex] * (1.0f - a) + a * texture[id];
}
}
} | code for sm_80
Function : _Z21DrawRgbaTextureKernelPfiiiiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff007624 */
/* 0x000fe200078e00ff */
/*0020*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0030*/ IABS R11, c[0x0][0x180] ; /* 0x00006000000b7a13 */
/* 0x000fe40000000000 */
/*0040*/ IMAD R0, R0, c[0x0][0x180], RZ ; /* 0x0000600000007a24 */
/* 0x000fe200078e02ff */
/*0050*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0060*/ IABS R7, R0 ; /* 0x0000000000077213 */
/* 0x000fe20000000000 */
/*0070*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e660000002100 */
/*0080*/ I2F.RP R2, R7 ; /* 0x0000000700027306 */
/* 0x000eb00000209400 */
/*0090*/ MUFU.RCP R2, R2 ; /* 0x0000000200027308 */
/* 0x004ea20000001000 */
/*00a0*/ IMAD R3, R3, c[0x0][0xc], R6 ; /* 0x0000030003037a24 */
/* 0x001fc800078e0206 */
/*00b0*/ IMAD R3, R3, c[0x0][0x0], R8 ; /* 0x0000000003037a24 */
/* 0x002fe200078e0208 */
/*00c0*/ IADD3 R4, R2, 0xffffffe, RZ ; /* 0x0ffffffe02047810 */
/* 0x004fc80007ffe0ff */
/*00d0*/ IABS R2, R3 ; /* 0x0000000300027213 */
/* 0x000fe20000000000 */
/*00e0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*00f0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0100*/ IMAD.MOV R9, RZ, RZ, -R5 ; /* 0x000000ffff097224 */
/* 0x002fca00078e0a05 */
/*0110*/ MOV R6, R9 ; /* 0x0000000900067202 */
/* 0x000fca0000000f00 */
/*0120*/ IMAD R9, R6, R7, RZ ; /* 0x0000000706097224 */
/* 0x000fe200078e02ff */
/*0130*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x000fc60000000000 */
/*0140*/ IMAD.HI.U32 R5, R5, R9, R4 ; /* 0x0000000905057227 */
/* 0x000fe200078e0004 */
/*0150*/ MOV R4, R2 ; /* 0x0000000200047202 */
/* 0x000fc60000000f00 */
/*0160*/ IMAD.MOV R9, RZ, RZ, -R6 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0a06 */
/*0170*/ IMAD.HI.U32 R2, R5, R4, RZ ; /* 0x0000000405027227 */
/* 0x000fe200078e00ff */
/*0180*/ I2F.RP R6, R11 ; /* 0x0000000b00067306 */
/* 0x000e260000209400 */
/*0190*/ IMAD R4, R2, R9, R4 ; /* 0x0000000902047224 */
/* 0x000fca00078e0204 */
/*01a0*/ ISETP.GT.U32.AND P2, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x000fe20003f44070 */
/*01b0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e180000001000 */
/*01c0*/ @!P2 IMAD.IADD R4, R4, 0x1, -R7 ; /* 0x000000010404a824 */
/* 0x000fe200078e0a07 */
/*01d0*/ @!P2 IADD3 R2, R2, 0x1, RZ ; /* 0x000000010202a810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.NE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45270 */
/*01f0*/ ISETP.GE.U32.AND P0, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x000fe40003f06070 */
/*0200*/ LOP3.LUT R4, R3, R0, RZ, 0x3c, !PT ; /* 0x0000000003047212 */
/* 0x000fc800078e3cff */
/*0210*/ ISETP.GE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f26270 */
/*0220*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fc80007ffe0ff */
/*0230*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000062000021f000 */
/*0240*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fca0007ffe0ff */
/*0250*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0002 */
/*0260*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fc800000001ff */
/*0270*/ @!P1 IADD3 R8, -R8, RZ, RZ ; /* 0x000000ff08089210 */
/* 0x000fe40007ffe1ff */
/*0280*/ @!P2 LOP3.LUT R8, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff08a212 */
/* 0x000fe200078e33ff */
/*0290*/ IMAD.MOV R6, RZ, RZ, -R5 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a05 */
/*02a0*/ IMAD.MOV R2, RZ, RZ, -R8 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0a08 */
/*02b0*/ IMAD R7, R6, R11, RZ ; /* 0x0000000b06077224 */
/* 0x000fe400078e02ff */
/*02c0*/ IMAD R13, R0, R2, R3 ; /* 0x00000002000d7224 */
/* 0x000fe400078e0203 */
/*02d0*/ IMAD.HI.U32 R4, R5, R7, R4 ; /* 0x0000000705047227 */
/* 0x000fc600078e0004 */
/*02e0*/ IABS R2, R13 ; /* 0x0000000d00027213 */
/* 0x000fca0000000000 */
/*02f0*/ IMAD.HI.U32 R4, R4, R2, RZ ; /* 0x0000000204047227 */
/* 0x000fc800078e00ff */
/*0300*/ IMAD.MOV R5, RZ, RZ, -R4 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a04 */
/*0310*/ IMAD R2, R11, R5, R2 ; /* 0x000000050b027224 */
/* 0x000fca00078e0202 */
/*0320*/ ISETP.GT.U32.AND P2, PT, R11, R2, PT ; /* 0x000000020b00720c */
/* 0x000fda0003f44070 */
/*0330*/ @!P2 IMAD.IADD R2, R2, 0x1, -R11 ; /* 0x000000010202a824 */
/* 0x000fe200078e0a0b */
/*0340*/ @!P2 IADD3 R4, R4, 0x1, RZ ; /* 0x000000010404a810 */
/* 0x000fe40007ffe0ff */
/*0350*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fe40003f45270 */
/*0360*/ ISETP.GE.U32.AND P0, PT, R2, R11, PT ; /* 0x0000000b0200720c */
/* 0x000fe40003f06070 */
/*0370*/ LOP3.LUT R2, R13, c[0x0][0x180], RZ, 0x3c, !PT ; /* 0x000060000d027a12 */
/* 0x000fc800078e3cff */
/*0380*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fce0003f26270 */
/*0390*/ @P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104040810 */
/* 0x000fe40007ffe0ff */
/*03a0*/ ISETP.GT.AND P0, PT, R8, 0x2, PT ; /* 0x000000020800780c */
/* 0x000fc80003f04270 */
/*03b0*/ @!P1 IADD3 R4, -R4, RZ, RZ ; /* 0x000000ff04049210 */
/* 0x000fe40007ffe1ff */
/*03c0*/ @!P2 LOP3.LUT R4, RZ, c[0x0][0x180], RZ, 0x33, !PT ; /* 0x00006000ff04aa12 */
/* 0x000fce00078e33ff */
/*03d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*03e0*/ IMAD.MOV R2, RZ, RZ, -R4 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0a04 */
/*03f0*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f25270 */
/*0400*/ BSSY B0, 0x4b0 ; /* 0x000000a000007945 */
/* 0x000fe40003800000 */
/*0410*/ IMAD R2, R2, c[0x0][0x180], R13 ; /* 0x0000600002027a24 */
/* 0x000fca00078e020d */
/*0420*/ IADD3 R11, R2, c[0x0][0x170], RZ ; /* 0x00005c00020b7a10 */
/* 0x000fe20007ffe0ff */
/*0430*/ IMAD.MOV.U32 R2, RZ, RZ, 0x2 ; /* 0x00000002ff027424 */
/* 0x000fc600078e00ff */
/*0440*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fc80003f06270 */
/*0450*/ ISETP.GE.OR P0, PT, R11, c[0x0][0x168], !P0 ; /* 0x00005a000b007a0c */
/* 0x000fe20004706670 */
/*0460*/ @!P1 BRA 0x4a0 ; /* 0x0000003000009947 */
/* 0x000fee0003800000 */
/*0470*/ ISETP.NE.AND P1, PT, R8, 0x2, PT ; /* 0x000000020800780c */
/* 0x000fda0003f25270 */
/*0480*/ @!P1 MOV R2, RZ ; /* 0x000000ff00029202 */
/* 0x000fe20000000f00 */
/*0490*/ @P1 IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff021224 */
/* 0x000fe400078e0008 */
/*04a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*04c0*/ IADD3 R5, R4, c[0x0][0x174], RZ ; /* 0x00005d0004057a10 */
/* 0x000fc80007ffe0ff */
/*04d0*/ ISETP.GE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc80003f06270 */
/*04e0*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x16c], !P0 ; /* 0x00005b0005007a0c */
/* 0x000fda0004706670 */
/*04f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0500*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0510*/ IMAD R4, R0, 0x3, R13 ; /* 0x0000000300047824 */
/* 0x000fe200078e020d */
/*0520*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0530*/ IMAD R2, R2, c[0x0][0x16c], R5 ; /* 0x00005b0002027a24 */
/* 0x000fc800078e0205 */
/*0540*/ IMAD R2, R2, c[0x0][0x168], R11 ; /* 0x00005a0002027a24 */
/* 0x000fc600078e020b */
/*0550*/ IMAD.WIDE R4, R4, R9, c[0x0][0x178] ; /* 0x00005e0004047625 */
/* 0x000fc800078e0209 */
/*0560*/ IMAD.WIDE R6, R3, R9.reuse, c[0x0][0x178] ; /* 0x00005e0003067625 */
/* 0x080fe400078e0209 */
/*0570*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*0580*/ IMAD.WIDE R2, R2, R9, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe400078e0209 */
/*0590*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ee8000c1e1900 */
/*05a0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000f22000c1e1900 */
/*05b0*/ FADD R0, -R4, 1 ; /* 0x3f80000004007421 */
/* 0x004fc40000000100 */
/*05c0*/ FMUL R8, R4, R7 ; /* 0x0000000704087220 */
/* 0x008fc80000400000 */
/*05d0*/ FFMA R9, R0, R9, R8 ; /* 0x0000000900097223 */
/* 0x010fca0000000008 */
/*05e0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*05f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0600*/ BRA 0x600; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void DrawRgbaTextureKernel(float *target, int targetWidth, int targetHeight, int inputX, int inputY, float *texture, int textureWidth, int textureHeight)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
int targetPixels = targetWidth * targetHeight;
int texturePixels = textureWidth * textureHeight;
int idTextureRgb = id / texturePixels;
int idTexturePixel = (id - idTextureRgb * texturePixels); // same as (id % texturePixels), but the kernel runs 10% faster
int idTextureY = idTexturePixel / textureWidth;
int idTextureX = (idTexturePixel - idTextureY * textureWidth); // same as (id % textureWidth), but the kernel runs another 10% faster
if (idTextureRgb < 3) // 3 channels that we will write to
{
// the texture is in BGR format, we want RGB
switch (idTextureRgb)
{
case 0: // R
idTextureRgb = 2; // B
break;
case 2: // B
idTextureRgb = 0; // R
break;
}
// if the texture pixel offset by inputX, inputY, lies inside the target
if (idTextureX + inputX < targetWidth &&
idTextureX + inputX >= 0 &&
idTextureY + inputY < targetHeight &&
idTextureY + inputY >= 0)
{
int tIndex = targetPixels * idTextureRgb + targetWidth * (idTextureY + inputY) + (idTextureX + inputX);
int aIndex = idTexturePixel + 3 * texturePixels; // the A component of the texture
float a = texture[aIndex];
target[tIndex] = target[tIndex] * (1.0f - a) + a * texture[id];
}
}
} | .file "tmpxft_00066a33_00000000-6_DrawRgbaTextureKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z21DrawRgbaTextureKernelPfiiiiS_iiPfiiiiS_ii
.type _Z49__device_stub__Z21DrawRgbaTextureKernelPfiiiiS_iiPfiiiiS_ii, @function
_Z49__device_stub__Z21DrawRgbaTextureKernelPfiiiiS_iiPfiiiiS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 200
pushq 40(%rsp)
.cfi_def_cfa_offset 208
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21DrawRgbaTextureKernelPfiiiiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z21DrawRgbaTextureKernelPfiiiiS_iiPfiiiiS_ii, .-_Z49__device_stub__Z21DrawRgbaTextureKernelPfiiiiS_iiPfiiiiS_ii
.globl _Z21DrawRgbaTextureKernelPfiiiiS_ii
.type _Z21DrawRgbaTextureKernelPfiiiiS_ii, @function
_Z21DrawRgbaTextureKernelPfiiiiS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z49__device_stub__Z21DrawRgbaTextureKernelPfiiiiS_iiPfiiiiS_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z21DrawRgbaTextureKernelPfiiiiS_ii, .-_Z21DrawRgbaTextureKernelPfiiiiS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z21DrawRgbaTextureKernelPfiiiiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21DrawRgbaTextureKernelPfiiiiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void DrawRgbaTextureKernel(float *target, int targetWidth, int targetHeight, int inputX, int inputY, float *texture, int textureWidth, int textureHeight)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
int targetPixels = targetWidth * targetHeight;
int texturePixels = textureWidth * textureHeight;
int idTextureRgb = id / texturePixels;
int idTexturePixel = (id - idTextureRgb * texturePixels); // same as (id % texturePixels), but the kernel runs 10% faster
int idTextureY = idTexturePixel / textureWidth;
int idTextureX = (idTexturePixel - idTextureY * textureWidth); // same as (id % textureWidth), but the kernel runs another 10% faster
if (idTextureRgb < 3) // 3 channels that we will write to
{
// the texture is in BGR format, we want RGB
switch (idTextureRgb)
{
case 0: // R
idTextureRgb = 2; // B
break;
case 2: // B
idTextureRgb = 0; // R
break;
}
// if the texture pixel offset by inputX, inputY, lies inside the target
if (idTextureX + inputX < targetWidth &&
idTextureX + inputX >= 0 &&
idTextureY + inputY < targetHeight &&
idTextureY + inputY >= 0)
{
int tIndex = targetPixels * idTextureRgb + targetWidth * (idTextureY + inputY) + (idTextureX + inputX);
int aIndex = idTexturePixel + 3 * texturePixels; // the A component of the texture
float a = texture[aIndex];
target[tIndex] = target[tIndex] * (1.0f - a) + a * texture[id];
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void DrawRgbaTextureKernel(float *target, int targetWidth, int targetHeight, int inputX, int inputY, float *texture, int textureWidth, int textureHeight)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
int targetPixels = targetWidth * targetHeight;
int texturePixels = textureWidth * textureHeight;
int idTextureRgb = id / texturePixels;
int idTexturePixel = (id - idTextureRgb * texturePixels); // same as (id % texturePixels), but the kernel runs 10% faster
int idTextureY = idTexturePixel / textureWidth;
int idTextureX = (idTexturePixel - idTextureY * textureWidth); // same as (id % textureWidth), but the kernel runs another 10% faster
if (idTextureRgb < 3) // 3 channels that we will write to
{
// the texture is in BGR format, we want RGB
switch (idTextureRgb)
{
case 0: // R
idTextureRgb = 2; // B
break;
case 2: // B
idTextureRgb = 0; // R
break;
}
// if the texture pixel offset by inputX, inputY, lies inside the target
if (idTextureX + inputX < targetWidth &&
idTextureX + inputX >= 0 &&
idTextureY + inputY < targetHeight &&
idTextureY + inputY >= 0)
{
int tIndex = targetPixels * idTextureRgb + targetWidth * (idTextureY + inputY) + (idTextureX + inputX);
int aIndex = idTexturePixel + 3 * texturePixels; // the A component of the texture
float a = texture[aIndex];
target[tIndex] = target[tIndex] * (1.0f - a) + a * texture[id];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void DrawRgbaTextureKernel(float *target, int targetWidth, int targetHeight, int inputX, int inputY, float *texture, int textureWidth, int textureHeight)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
int targetPixels = targetWidth * targetHeight;
int texturePixels = textureWidth * textureHeight;
int idTextureRgb = id / texturePixels;
int idTexturePixel = (id - idTextureRgb * texturePixels); // same as (id % texturePixels), but the kernel runs 10% faster
int idTextureY = idTexturePixel / textureWidth;
int idTextureX = (idTexturePixel - idTextureY * textureWidth); // same as (id % textureWidth), but the kernel runs another 10% faster
if (idTextureRgb < 3) // 3 channels that we will write to
{
// the texture is in BGR format, we want RGB
switch (idTextureRgb)
{
case 0: // R
idTextureRgb = 2; // B
break;
case 2: // B
idTextureRgb = 0; // R
break;
}
// if the texture pixel offset by inputX, inputY, lies inside the target
if (idTextureX + inputX < targetWidth &&
idTextureX + inputX >= 0 &&
idTextureY + inputY < targetHeight &&
idTextureY + inputY >= 0)
{
int tIndex = targetPixels * idTextureRgb + targetWidth * (idTextureY + inputY) + (idTextureX + inputX);
int aIndex = idTexturePixel + 3 * texturePixels; // the A component of the texture
float a = texture[aIndex];
target[tIndex] = target[tIndex] * (1.0f - a) + a * texture[id];
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21DrawRgbaTextureKernelPfiiiiS_ii
.globl _Z21DrawRgbaTextureKernelPfiiiiS_ii
.p2align 8
.type _Z21DrawRgbaTextureKernelPfiiiiS_ii,@function
_Z21DrawRgbaTextureKernelPfiiiiS_ii:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x20
s_load_b32 s4, s[0:1], 0x28
s_load_b32 s5, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s2
s_mul_i32 s4, s4, s15
s_ashr_i32 s6, s3, 31
s_and_b32 s5, s5, 0xffff
s_add_i32 s7, s3, s6
s_add_i32 s4, s4, s14
s_xor_b32 s7, s7, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s7
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1)
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
s_sub_i32 s4, 0, s7
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s4, v3
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
v_xor_b32_e32 v4, v4, v2
v_xor_b32_e32 v2, s6, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v0
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, s7
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s7, v3
v_cmp_le_u32_e32 vcc_lo, s7, v3
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s7, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v0, v2
v_cmpx_gt_i32_e32 3, v4
s_cbranch_execz .LBB0_10
s_ashr_i32 s4, s2, 31
v_mul_lo_u32 v2, v4, s3
s_add_i32 s5, s2, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s5, s5, s4
v_cvt_f32_u32_e32 v0, s5
s_sub_i32 s6, 0, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v3, v0
v_sub_nc_u32_e32 v0, v1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, s6, v3
v_ashrrev_i32_e32 v5, 31, v0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v6, v0, v5
v_mul_hi_u32 v2, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v7, v6, v5
v_add_nc_u32_e32 v6, v3, v2
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, v6, 0
v_cmpx_lt_i32_e32 1, v4
s_xor_b32 s6, exec_lo, s6
s_mov_b32 s7, 0
s_or_saveexec_b32 s6, s6
v_mov_b32_e32 v6, s7
s_xor_b32 exec_lo, exec_lo, s6
s_cbranch_execz .LBB0_7
s_mov_b32 s7, exec_lo
v_cmpx_eq_u32_e32 0, v4
v_mov_b32_e32 v4, 2
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v6, v4
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s6
v_mul_lo_u32 v2, v3, s5
v_add_nc_u32_e32 v4, 1, v3
v_xor_b32_e32 v5, s4, v5
s_load_b32 s4, s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v7, v2
v_subrev_nc_u32_e32 v7, s5, v2
v_cmp_le_u32_e32 vcc_lo, s5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v3, v3, v4 :: v_dual_cndmask_b32 v2, v2, v7
v_add_nc_u32_e32 v4, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s5, v2
s_load_b32 s5, s[0:1], 0x10
v_cndmask_b32_e32 v2, v3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v5
v_sub_nc_u32_e32 v3, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v3, s2
v_sub_nc_u32_e32 v2, v0, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, s5, v2
v_cmp_gt_i32_e32 vcc_lo, s4, v2
v_cmp_lt_i32_e64 s2, -1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_10
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b32 s5, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, s2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s5, v3
v_cmp_lt_i32_e64 s2, -1, v3
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_10
v_mad_u64_u32 v[4:5], null, s3, 3, v[0:1]
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x18
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[7:8], null, v6, s5, v[3:4]
v_ashrrev_i32_e32 v5, 31, v4
v_mad_u64_u32 v[8:9], null, v7, s4, v[2:3]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[4:5]
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v9, 31, v8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v4, vcc_lo
v_lshlrev_b64 v[4:5], 2, v[8:9]
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v6, v[2:3], off
v_add_co_u32 v2, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v5, vcc_lo
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[2:3], off
s_waitcnt vmcnt(2)
v_sub_f32_e32 v4, 1.0, v6
s_waitcnt vmcnt(1)
v_mul_f32_e32 v0, v6, v0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v0, v1, v4
global_store_b32 v[2:3], v0, off
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21DrawRgbaTextureKernelPfiiiiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21DrawRgbaTextureKernelPfiiiiS_ii, .Lfunc_end0-_Z21DrawRgbaTextureKernelPfiiiiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21DrawRgbaTextureKernelPfiiiiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21DrawRgbaTextureKernelPfiiiiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void DrawRgbaTextureKernel(float *target, int targetWidth, int targetHeight, int inputX, int inputY, float *texture, int textureWidth, int textureHeight)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
int targetPixels = targetWidth * targetHeight;
int texturePixels = textureWidth * textureHeight;
int idTextureRgb = id / texturePixels;
int idTexturePixel = (id - idTextureRgb * texturePixels); // same as (id % texturePixels), but the kernel runs 10% faster
int idTextureY = idTexturePixel / textureWidth;
int idTextureX = (idTexturePixel - idTextureY * textureWidth); // same as (id % textureWidth), but the kernel runs another 10% faster
if (idTextureRgb < 3) // 3 channels that we will write to
{
// the texture is in BGR format, we want RGB
switch (idTextureRgb)
{
case 0: // R
idTextureRgb = 2; // B
break;
case 2: // B
idTextureRgb = 0; // R
break;
}
// if the texture pixel offset by inputX, inputY, lies inside the target
if (idTextureX + inputX < targetWidth &&
idTextureX + inputX >= 0 &&
idTextureY + inputY < targetHeight &&
idTextureY + inputY >= 0)
{
int tIndex = targetPixels * idTextureRgb + targetWidth * (idTextureY + inputY) + (idTextureX + inputX);
int aIndex = idTexturePixel + 3 * texturePixels; // the A component of the texture
float a = texture[aIndex];
target[tIndex] = target[tIndex] * (1.0f - a) + a * texture[id];
}
}
} | .text
.file "DrawRgbaTextureKernel.hip"
.globl _Z36__device_stub__DrawRgbaTextureKernelPfiiiiS_ii # -- Begin function _Z36__device_stub__DrawRgbaTextureKernelPfiiiiS_ii
.p2align 4, 0x90
.type _Z36__device_stub__DrawRgbaTextureKernelPfiiiiS_ii,@function
_Z36__device_stub__DrawRgbaTextureKernelPfiiiiS_ii: # @_Z36__device_stub__DrawRgbaTextureKernelPfiiiiS_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %r9, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21DrawRgbaTextureKernelPfiiiiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z36__device_stub__DrawRgbaTextureKernelPfiiiiS_ii, .Lfunc_end0-_Z36__device_stub__DrawRgbaTextureKernelPfiiiiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21DrawRgbaTextureKernelPfiiiiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21DrawRgbaTextureKernelPfiiiiS_ii,@object # @_Z21DrawRgbaTextureKernelPfiiiiS_ii
.section .rodata,"a",@progbits
.globl _Z21DrawRgbaTextureKernelPfiiiiS_ii
.p2align 3, 0x0
_Z21DrawRgbaTextureKernelPfiiiiS_ii:
.quad _Z36__device_stub__DrawRgbaTextureKernelPfiiiiS_ii
.size _Z21DrawRgbaTextureKernelPfiiiiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21DrawRgbaTextureKernelPfiiiiS_ii"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__DrawRgbaTextureKernelPfiiiiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21DrawRgbaTextureKernelPfiiiiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z21DrawRgbaTextureKernelPfiiiiS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff007624 */
/* 0x000fe200078e00ff */
/*0020*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e220000002600 */
/*0030*/ IABS R11, c[0x0][0x180] ; /* 0x00006000000b7a13 */
/* 0x000fe40000000000 */
/*0040*/ IMAD R0, R0, c[0x0][0x180], RZ ; /* 0x0000600000007a24 */
/* 0x000fe200078e02ff */
/*0050*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0060*/ IABS R7, R0 ; /* 0x0000000000077213 */
/* 0x000fe20000000000 */
/*0070*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e660000002100 */
/*0080*/ I2F.RP R2, R7 ; /* 0x0000000700027306 */
/* 0x000eb00000209400 */
/*0090*/ MUFU.RCP R2, R2 ; /* 0x0000000200027308 */
/* 0x004ea20000001000 */
/*00a0*/ IMAD R3, R3, c[0x0][0xc], R6 ; /* 0x0000030003037a24 */
/* 0x001fc800078e0206 */
/*00b0*/ IMAD R3, R3, c[0x0][0x0], R8 ; /* 0x0000000003037a24 */
/* 0x002fe200078e0208 */
/*00c0*/ IADD3 R4, R2, 0xffffffe, RZ ; /* 0x0ffffffe02047810 */
/* 0x004fc80007ffe0ff */
/*00d0*/ IABS R2, R3 ; /* 0x0000000300027213 */
/* 0x000fe20000000000 */
/*00e0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*00f0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0100*/ IMAD.MOV R9, RZ, RZ, -R5 ; /* 0x000000ffff097224 */
/* 0x002fca00078e0a05 */
/*0110*/ MOV R6, R9 ; /* 0x0000000900067202 */
/* 0x000fca0000000f00 */
/*0120*/ IMAD R9, R6, R7, RZ ; /* 0x0000000706097224 */
/* 0x000fe200078e02ff */
/*0130*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x000fc60000000000 */
/*0140*/ IMAD.HI.U32 R5, R5, R9, R4 ; /* 0x0000000905057227 */
/* 0x000fe200078e0004 */
/*0150*/ MOV R4, R2 ; /* 0x0000000200047202 */
/* 0x000fc60000000f00 */
/*0160*/ IMAD.MOV R9, RZ, RZ, -R6 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0a06 */
/*0170*/ IMAD.HI.U32 R2, R5, R4, RZ ; /* 0x0000000405027227 */
/* 0x000fe200078e00ff */
/*0180*/ I2F.RP R6, R11 ; /* 0x0000000b00067306 */
/* 0x000e260000209400 */
/*0190*/ IMAD R4, R2, R9, R4 ; /* 0x0000000902047224 */
/* 0x000fca00078e0204 */
/*01a0*/ ISETP.GT.U32.AND P2, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x000fe20003f44070 */
/*01b0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e180000001000 */
/*01c0*/ @!P2 IMAD.IADD R4, R4, 0x1, -R7 ; /* 0x000000010404a824 */
/* 0x000fe200078e0a07 */
/*01d0*/ @!P2 IADD3 R2, R2, 0x1, RZ ; /* 0x000000010202a810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ ISETP.NE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f45270 */
/*01f0*/ ISETP.GE.U32.AND P0, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x000fe40003f06070 */
/*0200*/ LOP3.LUT R4, R3, R0, RZ, 0x3c, !PT ; /* 0x0000000003047212 */
/* 0x000fc800078e3cff */
/*0210*/ ISETP.GE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f26270 */
/*0220*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fc80007ffe0ff */
/*0230*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000062000021f000 */
/*0240*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fca0007ffe0ff */
/*0250*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0002 */
/*0260*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fc800000001ff */
/*0270*/ @!P1 IADD3 R8, -R8, RZ, RZ ; /* 0x000000ff08089210 */
/* 0x000fe40007ffe1ff */
/*0280*/ @!P2 LOP3.LUT R8, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff08a212 */
/* 0x000fe200078e33ff */
/*0290*/ IMAD.MOV R6, RZ, RZ, -R5 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a05 */
/*02a0*/ IMAD.MOV R2, RZ, RZ, -R8 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0a08 */
/*02b0*/ IMAD R7, R6, R11, RZ ; /* 0x0000000b06077224 */
/* 0x000fe400078e02ff */
/*02c0*/ IMAD R13, R0, R2, R3 ; /* 0x00000002000d7224 */
/* 0x000fe400078e0203 */
/*02d0*/ IMAD.HI.U32 R4, R5, R7, R4 ; /* 0x0000000705047227 */
/* 0x000fc600078e0004 */
/*02e0*/ IABS R2, R13 ; /* 0x0000000d00027213 */
/* 0x000fca0000000000 */
/*02f0*/ IMAD.HI.U32 R4, R4, R2, RZ ; /* 0x0000000204047227 */
/* 0x000fc800078e00ff */
/*0300*/ IMAD.MOV R5, RZ, RZ, -R4 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a04 */
/*0310*/ IMAD R2, R11, R5, R2 ; /* 0x000000050b027224 */
/* 0x000fca00078e0202 */
/*0320*/ ISETP.GT.U32.AND P2, PT, R11, R2, PT ; /* 0x000000020b00720c */
/* 0x000fda0003f44070 */
/*0330*/ @!P2 IMAD.IADD R2, R2, 0x1, -R11 ; /* 0x000000010202a824 */
/* 0x000fe200078e0a0b */
/*0340*/ @!P2 IADD3 R4, R4, 0x1, RZ ; /* 0x000000010404a810 */
/* 0x000fe40007ffe0ff */
/*0350*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fe40003f45270 */
/*0360*/ ISETP.GE.U32.AND P0, PT, R2, R11, PT ; /* 0x0000000b0200720c */
/* 0x000fe40003f06070 */
/*0370*/ LOP3.LUT R2, R13, c[0x0][0x180], RZ, 0x3c, !PT ; /* 0x000060000d027a12 */
/* 0x000fc800078e3cff */
/*0380*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fce0003f26270 */
/*0390*/ @P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104040810 */
/* 0x000fe40007ffe0ff */
/*03a0*/ ISETP.GT.AND P0, PT, R8, 0x2, PT ; /* 0x000000020800780c */
/* 0x000fc80003f04270 */
/*03b0*/ @!P1 IADD3 R4, -R4, RZ, RZ ; /* 0x000000ff04049210 */
/* 0x000fe40007ffe1ff */
/*03c0*/ @!P2 LOP3.LUT R4, RZ, c[0x0][0x180], RZ, 0x33, !PT ; /* 0x00006000ff04aa12 */
/* 0x000fce00078e33ff */
/*03d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*03e0*/ IMAD.MOV R2, RZ, RZ, -R4 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0a04 */
/*03f0*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f25270 */
/*0400*/ BSSY B0, 0x4b0 ; /* 0x000000a000007945 */
/* 0x000fe40003800000 */
/*0410*/ IMAD R2, R2, c[0x0][0x180], R13 ; /* 0x0000600002027a24 */
/* 0x000fca00078e020d */
/*0420*/ IADD3 R11, R2, c[0x0][0x170], RZ ; /* 0x00005c00020b7a10 */
/* 0x000fe20007ffe0ff */
/*0430*/ IMAD.MOV.U32 R2, RZ, RZ, 0x2 ; /* 0x00000002ff027424 */
/* 0x000fc600078e00ff */
/*0440*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fc80003f06270 */
/*0450*/ ISETP.GE.OR P0, PT, R11, c[0x0][0x168], !P0 ; /* 0x00005a000b007a0c */
/* 0x000fe20004706670 */
/*0460*/ @!P1 BRA 0x4a0 ; /* 0x0000003000009947 */
/* 0x000fee0003800000 */
/*0470*/ ISETP.NE.AND P1, PT, R8, 0x2, PT ; /* 0x000000020800780c */
/* 0x000fda0003f25270 */
/*0480*/ @!P1 MOV R2, RZ ; /* 0x000000ff00029202 */
/* 0x000fe20000000f00 */
/*0490*/ @P1 IMAD.MOV.U32 R2, RZ, RZ, R8 ; /* 0x000000ffff021224 */
/* 0x000fe400078e0008 */
/*04a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*04c0*/ IADD3 R5, R4, c[0x0][0x174], RZ ; /* 0x00005d0004057a10 */
/* 0x000fc80007ffe0ff */
/*04d0*/ ISETP.GE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fc80003f06270 */
/*04e0*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x16c], !P0 ; /* 0x00005b0005007a0c */
/* 0x000fda0004706670 */
/*04f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0500*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0510*/ IMAD R4, R0, 0x3, R13 ; /* 0x0000000300047824 */
/* 0x000fe200078e020d */
/*0520*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0530*/ IMAD R2, R2, c[0x0][0x16c], R5 ; /* 0x00005b0002027a24 */
/* 0x000fc800078e0205 */
/*0540*/ IMAD R2, R2, c[0x0][0x168], R11 ; /* 0x00005a0002027a24 */
/* 0x000fc600078e020b */
/*0550*/ IMAD.WIDE R4, R4, R9, c[0x0][0x178] ; /* 0x00005e0004047625 */
/* 0x000fc800078e0209 */
/*0560*/ IMAD.WIDE R6, R3, R9.reuse, c[0x0][0x178] ; /* 0x00005e0003067625 */
/* 0x080fe400078e0209 */
/*0570*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*0580*/ IMAD.WIDE R2, R2, R9, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe400078e0209 */
/*0590*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ee8000c1e1900 */
/*05a0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000f22000c1e1900 */
/*05b0*/ FADD R0, -R4, 1 ; /* 0x3f80000004007421 */
/* 0x004fc40000000100 */
/*05c0*/ FMUL R8, R4, R7 ; /* 0x0000000704087220 */
/* 0x008fc80000400000 */
/*05d0*/ FFMA R9, R0, R9, R8 ; /* 0x0000000900097223 */
/* 0x010fca0000000008 */
/*05e0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*05f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0600*/ BRA 0x600; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21DrawRgbaTextureKernelPfiiiiS_ii
.globl _Z21DrawRgbaTextureKernelPfiiiiS_ii
.p2align 8
.type _Z21DrawRgbaTextureKernelPfiiiiS_ii,@function
_Z21DrawRgbaTextureKernelPfiiiiS_ii:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x20
s_load_b32 s4, s[0:1], 0x28
s_load_b32 s5, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s2
s_mul_i32 s4, s4, s15
s_ashr_i32 s6, s3, 31
s_and_b32 s5, s5, 0xffff
s_add_i32 s7, s3, s6
s_add_i32 s4, s4, s14
s_xor_b32 s7, s7, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s7
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1)
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
s_sub_i32 s4, 0, s7
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s4, v3
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
v_xor_b32_e32 v4, v4, v2
v_xor_b32_e32 v2, s6, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v0
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, s7
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s7, v3
v_cmp_le_u32_e32 vcc_lo, s7, v3
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s7, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v0, v2
v_cmpx_gt_i32_e32 3, v4
s_cbranch_execz .LBB0_10
s_ashr_i32 s4, s2, 31
v_mul_lo_u32 v2, v4, s3
s_add_i32 s5, s2, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s5, s5, s4
v_cvt_f32_u32_e32 v0, s5
s_sub_i32 s6, 0, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v3, v0
v_sub_nc_u32_e32 v0, v1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, s6, v3
v_ashrrev_i32_e32 v5, 31, v0
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v6, v0, v5
v_mul_hi_u32 v2, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v7, v6, v5
v_add_nc_u32_e32 v6, v3, v2
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, v6, 0
v_cmpx_lt_i32_e32 1, v4
s_xor_b32 s6, exec_lo, s6
s_mov_b32 s7, 0
s_or_saveexec_b32 s6, s6
v_mov_b32_e32 v6, s7
s_xor_b32 exec_lo, exec_lo, s6
s_cbranch_execz .LBB0_7
s_mov_b32 s7, exec_lo
v_cmpx_eq_u32_e32 0, v4
v_mov_b32_e32 v4, 2
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v6, v4
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s6
v_mul_lo_u32 v2, v3, s5
v_add_nc_u32_e32 v4, 1, v3
v_xor_b32_e32 v5, s4, v5
s_load_b32 s4, s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v7, v2
v_subrev_nc_u32_e32 v7, s5, v2
v_cmp_le_u32_e32 vcc_lo, s5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v3, v3, v4 :: v_dual_cndmask_b32 v2, v2, v7
v_add_nc_u32_e32 v4, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s5, v2
s_load_b32 s5, s[0:1], 0x10
v_cndmask_b32_e32 v2, v3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v2, v2, v5
v_sub_nc_u32_e32 v3, v2, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v3, s2
v_sub_nc_u32_e32 v2, v0, v2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, s5, v2
v_cmp_gt_i32_e32 vcc_lo, s4, v2
v_cmp_lt_i32_e64 s2, -1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_10
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b32 s5, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, s2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s5, v3
v_cmp_lt_i32_e64 s2, -1, v3
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_10
v_mad_u64_u32 v[4:5], null, s3, 3, v[0:1]
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x18
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[7:8], null, v6, s5, v[3:4]
v_ashrrev_i32_e32 v5, 31, v4
v_mad_u64_u32 v[8:9], null, v7, s4, v[2:3]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[4:5]
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v9, 31, v8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v4, vcc_lo
v_lshlrev_b64 v[4:5], 2, v[8:9]
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v6, v[2:3], off
v_add_co_u32 v2, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v5, vcc_lo
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[2:3], off
s_waitcnt vmcnt(2)
v_sub_f32_e32 v4, 1.0, v6
s_waitcnt vmcnt(1)
v_mul_f32_e32 v0, v6, v0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v0, v1, v4
global_store_b32 v[2:3], v0, off
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21DrawRgbaTextureKernelPfiiiiS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21DrawRgbaTextureKernelPfiiiiS_ii, .Lfunc_end0-_Z21DrawRgbaTextureKernelPfiiiiS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21DrawRgbaTextureKernelPfiiiiS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21DrawRgbaTextureKernelPfiiiiS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00066a33_00000000-6_DrawRgbaTextureKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z21DrawRgbaTextureKernelPfiiiiS_iiPfiiiiS_ii
.type _Z49__device_stub__Z21DrawRgbaTextureKernelPfiiiiS_iiPfiiiiS_ii, @function
_Z49__device_stub__Z21DrawRgbaTextureKernelPfiiiiS_iiPfiiiiS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 200
pushq 40(%rsp)
.cfi_def_cfa_offset 208
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21DrawRgbaTextureKernelPfiiiiS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z21DrawRgbaTextureKernelPfiiiiS_iiPfiiiiS_ii, .-_Z49__device_stub__Z21DrawRgbaTextureKernelPfiiiiS_iiPfiiiiS_ii
.globl _Z21DrawRgbaTextureKernelPfiiiiS_ii
.type _Z21DrawRgbaTextureKernelPfiiiiS_ii, @function
_Z21DrawRgbaTextureKernelPfiiiiS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z49__device_stub__Z21DrawRgbaTextureKernelPfiiiiS_iiPfiiiiS_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z21DrawRgbaTextureKernelPfiiiiS_ii, .-_Z21DrawRgbaTextureKernelPfiiiiS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z21DrawRgbaTextureKernelPfiiiiS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21DrawRgbaTextureKernelPfiiiiS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "DrawRgbaTextureKernel.hip"
.globl _Z36__device_stub__DrawRgbaTextureKernelPfiiiiS_ii # -- Begin function _Z36__device_stub__DrawRgbaTextureKernelPfiiiiS_ii
.p2align 4, 0x90
.type _Z36__device_stub__DrawRgbaTextureKernelPfiiiiS_ii,@function
_Z36__device_stub__DrawRgbaTextureKernelPfiiiiS_ii: # @_Z36__device_stub__DrawRgbaTextureKernelPfiiiiS_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %r9, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21DrawRgbaTextureKernelPfiiiiS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z36__device_stub__DrawRgbaTextureKernelPfiiiiS_ii, .Lfunc_end0-_Z36__device_stub__DrawRgbaTextureKernelPfiiiiS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21DrawRgbaTextureKernelPfiiiiS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21DrawRgbaTextureKernelPfiiiiS_ii,@object # @_Z21DrawRgbaTextureKernelPfiiiiS_ii
.section .rodata,"a",@progbits
.globl _Z21DrawRgbaTextureKernelPfiiiiS_ii
.p2align 3, 0x0
_Z21DrawRgbaTextureKernelPfiiiiS_ii:
.quad _Z36__device_stub__DrawRgbaTextureKernelPfiiiiS_ii
.size _Z21DrawRgbaTextureKernelPfiiiiS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21DrawRgbaTextureKernelPfiiiiS_ii"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__DrawRgbaTextureKernelPfiiiiS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21DrawRgbaTextureKernelPfiiiiS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Dan Wolf
#include <iostream>
#include <string>
#include <chrono>
// https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api/14038590#14038590
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void multMat(int n, int *arrForce_d, int *arrDistance_d, int *arrAnswer_d) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n){
arrAnswer_d[i] = arrForce_d[i] * arrDistance_d[i];
}
}
int main(int argc, char **argv) {
auto n = atoi(argv[1]);
size_t bytes = n* sizeof(int);
// host pointers
int* arrForce;
int* arrDistance;
int* arrAnswer;
// device pointers
int* arrForce_d;
int* arrDistance_d;
int* arrAnswer_d;
// allocate on host
arrForce = (int*)malloc(bytes);
arrDistance = (int*)malloc(bytes);
arrAnswer = (int*)malloc(bytes);
// initialize on host, at n=16, this initializes to
// (1, 2, 3, 4, 5, 6, 7, 8, 9, 8, 7, 6, 5, 4, 3, 2)
// (1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 1, 2, 3, 4, 5)
// Answer: 1 + 4 + 9 + 16 + 25 + 36 + 49 + 64 + 81 + 80 + 77 + 6 + 10 + 12 + 12 + 10 = 492
int forceValue = 1;
int distanceValue = 0;
for (int i = 0; i < n; i++){
arrForce[i] = forceValue;
if (i < n/2) {
forceValue = forceValue + 1;
} else {
forceValue = forceValue - 1;
}
distanceValue = distanceValue > 10 ? distanceValue - 10 : distanceValue + 1;
arrDistance[i] = distanceValue;
}
// allocate on device
// print
std::cout << "force: ";
for (int i = 0; i < n; i++){
std::cout << arrForce[i] << " ";
}
std::cout << '\n' << "dist: ";
for (int i = 0; i < n; i++){
std::cout << arrDistance[i] << " ";
}
std::chrono::high_resolution_clock::time_point t1 = std::chrono::high_resolution_clock::now();
// if more than the number of elements is passed in, don't use the gpu
if (argc > 2) {
std::cout << '\n' << "using CPU" << '\n';
for (int i = 0; i < n; i++) {
arrAnswer[i] = arrForce[i] * arrDistance[i];
}
} else {
std::cout << '\n' << "using GPU" << '\n';
const int BLOCK_SIZE = 1024;
dim3 dimBlock (BLOCK_SIZE);
dim3 dimGrid = (int)ceil((float)n / BLOCK_SIZE);
gpuErrchk(cudaMalloc(&arrForce_d, bytes));
gpuErrchk(cudaMalloc(&arrDistance_d, bytes));
gpuErrchk(cudaMalloc(&arrAnswer_d, bytes));
gpuErrchk(cudaMemcpy(arrForce_d, arrForce, bytes, cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(arrDistance_d, arrDistance, bytes, cudaMemcpyHostToDevice));
multMat<<<dimGrid, dimBlock>>>(n, arrForce_d, arrDistance_d, arrAnswer_d);
gpuErrchk(cudaPeekAtLastError());
gpuErrchk(cudaMemcpy(arrAnswer, arrAnswer_d, bytes, cudaMemcpyDeviceToHost));
gpuErrchk(cudaFree(arrForce_d))
gpuErrchk(cudaFree(arrDistance_d))
gpuErrchk(cudaFree(arrAnswer_d))
}
std::chrono::high_resolution_clock::time_point t2 = std::chrono::high_resolution_clock::now();
int total = 0;
for (int i = 0; i < n; i++) {
total = total + arrAnswer[i];
}
std::cout << "answer: " << total << '\n' << '\n';
std::cout << "time for calculation: " << (t2 - t1).count() << "ns";
return 0;
} | code for sm_80
Function : _Z7multMatiPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ IMAD R9, R4, R3, RZ ; /* 0x0000000304097224 */
/* 0x004fca00078e02ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Dan Wolf
#include <iostream>
#include <string>
#include <chrono>
// https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api/14038590#14038590
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void multMat(int n, int *arrForce_d, int *arrDistance_d, int *arrAnswer_d) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n){
arrAnswer_d[i] = arrForce_d[i] * arrDistance_d[i];
}
}
int main(int argc, char **argv) {
auto n = atoi(argv[1]);
size_t bytes = n* sizeof(int);
// host pointers
int* arrForce;
int* arrDistance;
int* arrAnswer;
// device pointers
int* arrForce_d;
int* arrDistance_d;
int* arrAnswer_d;
// allocate on host
arrForce = (int*)malloc(bytes);
arrDistance = (int*)malloc(bytes);
arrAnswer = (int*)malloc(bytes);
// initialize on host, at n=16, this initializes to
// (1, 2, 3, 4, 5, 6, 7, 8, 9, 8, 7, 6, 5, 4, 3, 2)
// (1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 1, 2, 3, 4, 5)
// Answer: 1 + 4 + 9 + 16 + 25 + 36 + 49 + 64 + 81 + 80 + 77 + 6 + 10 + 12 + 12 + 10 = 492
int forceValue = 1;
int distanceValue = 0;
for (int i = 0; i < n; i++){
arrForce[i] = forceValue;
if (i < n/2) {
forceValue = forceValue + 1;
} else {
forceValue = forceValue - 1;
}
distanceValue = distanceValue > 10 ? distanceValue - 10 : distanceValue + 1;
arrDistance[i] = distanceValue;
}
// allocate on device
// print
std::cout << "force: ";
for (int i = 0; i < n; i++){
std::cout << arrForce[i] << " ";
}
std::cout << '\n' << "dist: ";
for (int i = 0; i < n; i++){
std::cout << arrDistance[i] << " ";
}
std::chrono::high_resolution_clock::time_point t1 = std::chrono::high_resolution_clock::now();
// if more than the number of elements is passed in, don't use the gpu
if (argc > 2) {
std::cout << '\n' << "using CPU" << '\n';
for (int i = 0; i < n; i++) {
arrAnswer[i] = arrForce[i] * arrDistance[i];
}
} else {
std::cout << '\n' << "using GPU" << '\n';
const int BLOCK_SIZE = 1024;
dim3 dimBlock (BLOCK_SIZE);
dim3 dimGrid = (int)ceil((float)n / BLOCK_SIZE);
gpuErrchk(cudaMalloc(&arrForce_d, bytes));
gpuErrchk(cudaMalloc(&arrDistance_d, bytes));
gpuErrchk(cudaMalloc(&arrAnswer_d, bytes));
gpuErrchk(cudaMemcpy(arrForce_d, arrForce, bytes, cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(arrDistance_d, arrDistance, bytes, cudaMemcpyHostToDevice));
multMat<<<dimGrid, dimBlock>>>(n, arrForce_d, arrDistance_d, arrAnswer_d);
gpuErrchk(cudaPeekAtLastError());
gpuErrchk(cudaMemcpy(arrAnswer, arrAnswer_d, bytes, cudaMemcpyDeviceToHost));
gpuErrchk(cudaFree(arrForce_d))
gpuErrchk(cudaFree(arrDistance_d))
gpuErrchk(cudaFree(arrAnswer_d))
}
std::chrono::high_resolution_clock::time_point t2 = std::chrono::high_resolution_clock::now();
int total = 0;
for (int i = 0; i < n; i++) {
total = total + arrAnswer[i];
}
std::cout << "answer: " << total << '\n' << '\n';
std::cout << "time for calculation: " << (t2 - t1).count() << "ns";
return 0;
} | .file "tmpxft_000ed6eb_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3774:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3774:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB3768:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE3768:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z31__device_stub__Z7multMatiPiS_S_iPiS_S_
.type _Z31__device_stub__Z7multMatiPiS_S_iPiS_S_, @function
_Z31__device_stub__Z7multMatiPiS_S_iPiS_S_:
.LFB3796:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7multMatiPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3796:
.size _Z31__device_stub__Z7multMatiPiS_S_iPiS_S_, .-_Z31__device_stub__Z7multMatiPiS_S_iPiS_S_
.globl _Z7multMatiPiS_S_
.type _Z7multMatiPiS_S_, @function
_Z7multMatiPiS_S_:
.LFB3797:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z7multMatiPiS_S_iPiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3797:
.size _Z7multMatiPiS_S_, .-_Z7multMatiPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "force: "
.LC2:
.string " "
.LC3:
.string "dist: "
.LC4:
.string "using CPU"
.LC5:
.string "using GPU"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "/home/ubuntu/Datasets/stackv2/train-structured/PaluMacil/biceps/main/main.cu"
.section .rodata.str1.1
.LC8:
.string "answer: "
.LC9:
.string "time for calculation: "
.LC10:
.string "ns"
.text
.globl main
.type main, @function
main:
.LFB3769:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movl %edi, 24(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movl %eax, 28(%rsp)
cltq
leaq 0(,%rax,4), %rbx
movq %rbx, 8(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rdi
call malloc@PLT
movq %rax, (%rsp)
testl %r13d, %r13d
jle .L20
movl %r13d, %r8d
shrl $31, %r8d
addl %r13d, %r8d
sarl %r8d
leal -1(%r13), %r14d
movl $0, %edx
movl $0, %ecx
movl $1, %eax
jmp .L25
.L41:
movq %rsi, %rdx
.L25:
movl %eax, 0(%rbp,%rdx,4)
leal 1(%rax), %esi
subl $1, %eax
cmpl %edx, %r8d
cmovg %esi, %eax
leal -10(%rcx), %esi
leal 1(%rcx), %edi
cmpl $11, %ecx
movl %esi, %ecx
cmovl %edi, %ecx
movl %ecx, (%r12,%rdx,4)
leaq 1(%rdx), %rsi
cmpq %r14, %rdx
jne .L41
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rbp, %rbx
leaq 0(,%r14,4), %rax
movq %rax, 16(%rsp)
leaq 4(%rbp,%rax), %r15
leaq _ZSt4cout(%rip), %r14
.L26:
movl (%rbx), %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC2(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L26
movl $10, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %r12, %rbx
movq 16(%rsp), %rax
leaq 4(%r12,%rax), %r15
leaq _ZSt4cout(%rip), %r14
.L27:
movl (%rbx), %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC2(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L27
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r14
cmpl $2, 24(%rsp)
jg .L39
.L36:
movl $10, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movl $1024, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %r13d, %xmm0
mulss .LC6(%rip), %xmm0
call ceilf@PLT
cvttss2sil %xmm0, %eax
movl %eax, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 40(%rsp), %rdi
movq 8(%rsp), %r15
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $86, %edx
leaq .LC7(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 48(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $87, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 56(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $88, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movq %r15, %rdx
movq %rbp, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $90, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movq %r15, %rdx
movq %r12, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $91, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L32:
call cudaPeekAtLastError@PLT
movl %eax, %edi
movl $1, %ecx
movl $94, %edx
leaq .LC7(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $2, %ecx
movq 8(%rsp), %rdx
movq 56(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $96, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 40(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $98, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 48(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $99, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 56(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $100, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbp
testl %r13d, %r13d
jle .L42
.L37:
movq (%rsp), %rcx
movq %rcx, %rax
leal -1(%r13), %edx
leaq 4(%rcx,%rdx,4), %rdx
movl $0, %ebx
.L34:
addl (%rax), %ebx
addq $4, %rax
cmpq %rdx, %rax
jne .L34
.L33:
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
leaq .LC9(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
subq %r14, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC10(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L52
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movl 28(%rsp), %edi
call _Z31__device_stub__Z7multMatiPiS_S_iPiS_S_
jmp .L32
.L42:
movl $0, %ebx
jmp .L33
.L20:
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $10, %esi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r14
cmpl $2, 24(%rsp)
jle .L36
movl $10, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
testl %r13d, %r13d
jg .L38
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbp
movl $0, %ebx
jmp .L33
.L39:
movl $10, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
.L38:
leal -1(%r13), %ecx
movl $0, %eax
.L30:
movl 0(%rbp,%rax,4), %edx
imull (%r12,%rax,4), %edx
movq (%rsp), %rbx
movl %edx, (%rbx,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %rcx, %rdx
jne .L30
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbp
jmp .L37
.L52:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3769:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z7multMatiPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3799:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z7multMatiPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3799:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 981467136
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Dan Wolf
#include <iostream>
#include <string>
#include <chrono>
// https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api/14038590#14038590
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void multMat(int n, int *arrForce_d, int *arrDistance_d, int *arrAnswer_d) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n){
arrAnswer_d[i] = arrForce_d[i] * arrDistance_d[i];
}
}
int main(int argc, char **argv) {
auto n = atoi(argv[1]);
size_t bytes = n* sizeof(int);
// host pointers
int* arrForce;
int* arrDistance;
int* arrAnswer;
// device pointers
int* arrForce_d;
int* arrDistance_d;
int* arrAnswer_d;
// allocate on host
arrForce = (int*)malloc(bytes);
arrDistance = (int*)malloc(bytes);
arrAnswer = (int*)malloc(bytes);
// initialize on host, at n=16, this initializes to
// (1, 2, 3, 4, 5, 6, 7, 8, 9, 8, 7, 6, 5, 4, 3, 2)
// (1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 1, 2, 3, 4, 5)
// Answer: 1 + 4 + 9 + 16 + 25 + 36 + 49 + 64 + 81 + 80 + 77 + 6 + 10 + 12 + 12 + 10 = 492
int forceValue = 1;
int distanceValue = 0;
for (int i = 0; i < n; i++){
arrForce[i] = forceValue;
if (i < n/2) {
forceValue = forceValue + 1;
} else {
forceValue = forceValue - 1;
}
distanceValue = distanceValue > 10 ? distanceValue - 10 : distanceValue + 1;
arrDistance[i] = distanceValue;
}
// allocate on device
// print
std::cout << "force: ";
for (int i = 0; i < n; i++){
std::cout << arrForce[i] << " ";
}
std::cout << '\n' << "dist: ";
for (int i = 0; i < n; i++){
std::cout << arrDistance[i] << " ";
}
std::chrono::high_resolution_clock::time_point t1 = std::chrono::high_resolution_clock::now();
// if more than the number of elements is passed in, don't use the gpu
if (argc > 2) {
std::cout << '\n' << "using CPU" << '\n';
for (int i = 0; i < n; i++) {
arrAnswer[i] = arrForce[i] * arrDistance[i];
}
} else {
std::cout << '\n' << "using GPU" << '\n';
const int BLOCK_SIZE = 1024;
dim3 dimBlock (BLOCK_SIZE);
dim3 dimGrid = (int)ceil((float)n / BLOCK_SIZE);
gpuErrchk(cudaMalloc(&arrForce_d, bytes));
gpuErrchk(cudaMalloc(&arrDistance_d, bytes));
gpuErrchk(cudaMalloc(&arrAnswer_d, bytes));
gpuErrchk(cudaMemcpy(arrForce_d, arrForce, bytes, cudaMemcpyHostToDevice));
gpuErrchk(cudaMemcpy(arrDistance_d, arrDistance, bytes, cudaMemcpyHostToDevice));
multMat<<<dimGrid, dimBlock>>>(n, arrForce_d, arrDistance_d, arrAnswer_d);
gpuErrchk(cudaPeekAtLastError());
gpuErrchk(cudaMemcpy(arrAnswer, arrAnswer_d, bytes, cudaMemcpyDeviceToHost));
gpuErrchk(cudaFree(arrForce_d))
gpuErrchk(cudaFree(arrDistance_d))
gpuErrchk(cudaFree(arrAnswer_d))
}
std::chrono::high_resolution_clock::time_point t2 = std::chrono::high_resolution_clock::now();
int total = 0;
for (int i = 0; i < n; i++) {
total = total + arrAnswer[i];
}
std::cout << "answer: " << total << '\n' << '\n';
std::cout << "time for calculation: " << (t2 - t1).count() << "ns";
return 0;
} | // Dan Wolf
#include <hip/hip_runtime.h>
#include <iostream>
#include <string>
#include <chrono>
// https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api/14038590#14038590
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void multMat(int n, int *arrForce_d, int *arrDistance_d, int *arrAnswer_d) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n){
arrAnswer_d[i] = arrForce_d[i] * arrDistance_d[i];
}
}
int main(int argc, char **argv) {
auto n = atoi(argv[1]);
size_t bytes = n* sizeof(int);
// host pointers
int* arrForce;
int* arrDistance;
int* arrAnswer;
// device pointers
int* arrForce_d;
int* arrDistance_d;
int* arrAnswer_d;
// allocate on host
arrForce = (int*)malloc(bytes);
arrDistance = (int*)malloc(bytes);
arrAnswer = (int*)malloc(bytes);
// initialize on host, at n=16, this initializes to
// (1, 2, 3, 4, 5, 6, 7, 8, 9, 8, 7, 6, 5, 4, 3, 2)
// (1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 1, 2, 3, 4, 5)
// Answer: 1 + 4 + 9 + 16 + 25 + 36 + 49 + 64 + 81 + 80 + 77 + 6 + 10 + 12 + 12 + 10 = 492
int forceValue = 1;
int distanceValue = 0;
for (int i = 0; i < n; i++){
arrForce[i] = forceValue;
if (i < n/2) {
forceValue = forceValue + 1;
} else {
forceValue = forceValue - 1;
}
distanceValue = distanceValue > 10 ? distanceValue - 10 : distanceValue + 1;
arrDistance[i] = distanceValue;
}
// allocate on device
// print
std::cout << "force: ";
for (int i = 0; i < n; i++){
std::cout << arrForce[i] << " ";
}
std::cout << '\n' << "dist: ";
for (int i = 0; i < n; i++){
std::cout << arrDistance[i] << " ";
}
std::chrono::high_resolution_clock::time_point t1 = std::chrono::high_resolution_clock::now();
// if more than the number of elements is passed in, don't use the gpu
if (argc > 2) {
std::cout << '\n' << "using CPU" << '\n';
for (int i = 0; i < n; i++) {
arrAnswer[i] = arrForce[i] * arrDistance[i];
}
} else {
std::cout << '\n' << "using GPU" << '\n';
const int BLOCK_SIZE = 1024;
dim3 dimBlock (BLOCK_SIZE);
dim3 dimGrid = (int)ceil((float)n / BLOCK_SIZE);
gpuErrchk(hipMalloc(&arrForce_d, bytes));
gpuErrchk(hipMalloc(&arrDistance_d, bytes));
gpuErrchk(hipMalloc(&arrAnswer_d, bytes));
gpuErrchk(hipMemcpy(arrForce_d, arrForce, bytes, hipMemcpyHostToDevice));
gpuErrchk(hipMemcpy(arrDistance_d, arrDistance, bytes, hipMemcpyHostToDevice));
multMat<<<dimGrid, dimBlock>>>(n, arrForce_d, arrDistance_d, arrAnswer_d);
gpuErrchk(hipPeekAtLastError());
gpuErrchk(hipMemcpy(arrAnswer, arrAnswer_d, bytes, hipMemcpyDeviceToHost));
gpuErrchk(hipFree(arrForce_d))
gpuErrchk(hipFree(arrDistance_d))
gpuErrchk(hipFree(arrAnswer_d))
}
std::chrono::high_resolution_clock::time_point t2 = std::chrono::high_resolution_clock::now();
int total = 0;
for (int i = 0; i < n; i++) {
total = total + arrAnswer[i];
}
std::cout << "answer: " << total << '\n' << '\n';
std::cout << "time for calculation: " << (t2 - t1).count() << "ns";
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Dan Wolf
#include <hip/hip_runtime.h>
#include <iostream>
#include <string>
#include <chrono>
// https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api/14038590#14038590
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void multMat(int n, int *arrForce_d, int *arrDistance_d, int *arrAnswer_d) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n){
arrAnswer_d[i] = arrForce_d[i] * arrDistance_d[i];
}
}
int main(int argc, char **argv) {
auto n = atoi(argv[1]);
size_t bytes = n* sizeof(int);
// host pointers
int* arrForce;
int* arrDistance;
int* arrAnswer;
// device pointers
int* arrForce_d;
int* arrDistance_d;
int* arrAnswer_d;
// allocate on host
arrForce = (int*)malloc(bytes);
arrDistance = (int*)malloc(bytes);
arrAnswer = (int*)malloc(bytes);
// initialize on host, at n=16, this initializes to
// (1, 2, 3, 4, 5, 6, 7, 8, 9, 8, 7, 6, 5, 4, 3, 2)
// (1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 1, 2, 3, 4, 5)
// Answer: 1 + 4 + 9 + 16 + 25 + 36 + 49 + 64 + 81 + 80 + 77 + 6 + 10 + 12 + 12 + 10 = 492
int forceValue = 1;
int distanceValue = 0;
for (int i = 0; i < n; i++){
arrForce[i] = forceValue;
if (i < n/2) {
forceValue = forceValue + 1;
} else {
forceValue = forceValue - 1;
}
distanceValue = distanceValue > 10 ? distanceValue - 10 : distanceValue + 1;
arrDistance[i] = distanceValue;
}
// allocate on device
// print
std::cout << "force: ";
for (int i = 0; i < n; i++){
std::cout << arrForce[i] << " ";
}
std::cout << '\n' << "dist: ";
for (int i = 0; i < n; i++){
std::cout << arrDistance[i] << " ";
}
std::chrono::high_resolution_clock::time_point t1 = std::chrono::high_resolution_clock::now();
// if more than the number of elements is passed in, don't use the gpu
if (argc > 2) {
std::cout << '\n' << "using CPU" << '\n';
for (int i = 0; i < n; i++) {
arrAnswer[i] = arrForce[i] * arrDistance[i];
}
} else {
std::cout << '\n' << "using GPU" << '\n';
const int BLOCK_SIZE = 1024;
dim3 dimBlock (BLOCK_SIZE);
dim3 dimGrid = (int)ceil((float)n / BLOCK_SIZE);
gpuErrchk(hipMalloc(&arrForce_d, bytes));
gpuErrchk(hipMalloc(&arrDistance_d, bytes));
gpuErrchk(hipMalloc(&arrAnswer_d, bytes));
gpuErrchk(hipMemcpy(arrForce_d, arrForce, bytes, hipMemcpyHostToDevice));
gpuErrchk(hipMemcpy(arrDistance_d, arrDistance, bytes, hipMemcpyHostToDevice));
multMat<<<dimGrid, dimBlock>>>(n, arrForce_d, arrDistance_d, arrAnswer_d);
gpuErrchk(hipPeekAtLastError());
gpuErrchk(hipMemcpy(arrAnswer, arrAnswer_d, bytes, hipMemcpyDeviceToHost));
gpuErrchk(hipFree(arrForce_d))
gpuErrchk(hipFree(arrDistance_d))
gpuErrchk(hipFree(arrAnswer_d))
}
std::chrono::high_resolution_clock::time_point t2 = std::chrono::high_resolution_clock::now();
int total = 0;
for (int i = 0; i < n; i++) {
total = total + arrAnswer[i];
}
std::cout << "answer: " << total << '\n' << '\n';
std::cout << "time for calculation: " << (t2 - t1).count() << "ns";
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7multMatiPiS_S_
.globl _Z7multMatiPiS_S_
.p2align 8
.type _Z7multMatiPiS_S_,@function
_Z7multMatiPiS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7multMatiPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7multMatiPiS_S_, .Lfunc_end0-_Z7multMatiPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7multMatiPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7multMatiPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Dan Wolf
#include <hip/hip_runtime.h>
#include <iostream>
#include <string>
#include <chrono>
// https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api/14038590#14038590
#define gpuErrchk(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
__global__ void multMat(int n, int *arrForce_d, int *arrDistance_d, int *arrAnswer_d) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n){
arrAnswer_d[i] = arrForce_d[i] * arrDistance_d[i];
}
}
int main(int argc, char **argv) {
auto n = atoi(argv[1]);
size_t bytes = n* sizeof(int);
// host pointers
int* arrForce;
int* arrDistance;
int* arrAnswer;
// device pointers
int* arrForce_d;
int* arrDistance_d;
int* arrAnswer_d;
// allocate on host
arrForce = (int*)malloc(bytes);
arrDistance = (int*)malloc(bytes);
arrAnswer = (int*)malloc(bytes);
// initialize on host, at n=16, this initializes to
// (1, 2, 3, 4, 5, 6, 7, 8, 9, 8, 7, 6, 5, 4, 3, 2)
// (1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 1, 2, 3, 4, 5)
// Answer: 1 + 4 + 9 + 16 + 25 + 36 + 49 + 64 + 81 + 80 + 77 + 6 + 10 + 12 + 12 + 10 = 492
int forceValue = 1;
int distanceValue = 0;
for (int i = 0; i < n; i++){
arrForce[i] = forceValue;
if (i < n/2) {
forceValue = forceValue + 1;
} else {
forceValue = forceValue - 1;
}
distanceValue = distanceValue > 10 ? distanceValue - 10 : distanceValue + 1;
arrDistance[i] = distanceValue;
}
// allocate on device
// print
std::cout << "force: ";
for (int i = 0; i < n; i++){
std::cout << arrForce[i] << " ";
}
std::cout << '\n' << "dist: ";
for (int i = 0; i < n; i++){
std::cout << arrDistance[i] << " ";
}
std::chrono::high_resolution_clock::time_point t1 = std::chrono::high_resolution_clock::now();
// if more than the number of elements is passed in, don't use the gpu
if (argc > 2) {
std::cout << '\n' << "using CPU" << '\n';
for (int i = 0; i < n; i++) {
arrAnswer[i] = arrForce[i] * arrDistance[i];
}
} else {
std::cout << '\n' << "using GPU" << '\n';
const int BLOCK_SIZE = 1024;
dim3 dimBlock (BLOCK_SIZE);
dim3 dimGrid = (int)ceil((float)n / BLOCK_SIZE);
gpuErrchk(hipMalloc(&arrForce_d, bytes));
gpuErrchk(hipMalloc(&arrDistance_d, bytes));
gpuErrchk(hipMalloc(&arrAnswer_d, bytes));
gpuErrchk(hipMemcpy(arrForce_d, arrForce, bytes, hipMemcpyHostToDevice));
gpuErrchk(hipMemcpy(arrDistance_d, arrDistance, bytes, hipMemcpyHostToDevice));
multMat<<<dimGrid, dimBlock>>>(n, arrForce_d, arrDistance_d, arrAnswer_d);
gpuErrchk(hipPeekAtLastError());
gpuErrchk(hipMemcpy(arrAnswer, arrAnswer_d, bytes, hipMemcpyDeviceToHost));
gpuErrchk(hipFree(arrForce_d))
gpuErrchk(hipFree(arrDistance_d))
gpuErrchk(hipFree(arrAnswer_d))
}
std::chrono::high_resolution_clock::time_point t2 = std::chrono::high_resolution_clock::now();
int total = 0;
for (int i = 0; i < n; i++) {
total = total + arrAnswer[i];
}
std::cout << "answer: " << total << '\n' << '\n';
std::cout << "time for calculation: " << (t2 - t1).count() << "ns";
return 0;
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__multMatiPiS_S_ # -- Begin function _Z22__device_stub__multMatiPiS_S_
.p2align 4, 0x90
.type _Z22__device_stub__multMatiPiS_S_,@function
_Z22__device_stub__multMatiPiS_S_: # @_Z22__device_stub__multMatiPiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7multMatiPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__multMatiPiS_S_, .Lfunc_end0-_Z22__device_stub__multMatiPiS_S_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3a800000 # float 9.765625E-4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, 12(%rsp) # 4-byte Spill
movq 8(%rsi), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movslq %ebx, %r12
leaq (,%r12,4), %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbp
movq %r14, %rdi
callq malloc
movq %rax, %r13
movq %r14, 88(%rsp) # 8-byte Spill
movq %r14, %rdi
callq malloc
movq %rax, %r14
testl %r12d, %r12d
jle .LBB1_3
# %bb.1: # %.lr.ph
movl %ebx, %eax
movl %ebx, %ecx
shrl %ecx
movl $1, %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_2: # =>This Inner Loop Header: Depth=1
cmpq %rcx, %rsi
movl $0, %edi
adcl $-1, %edi
movl %edx, (%rbp,%rsi,4)
orl $1, %edi
addl %edi, %edx
leal 1(%r15), %edi
cmpl $11, %r15d
leal -10(%r15), %r8d
cmovll %edi, %r8d
movl %r8d, (%r13,%rsi,4)
incq %rsi
movl %r8d, %r15d
cmpq %rsi, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
testl %ebx, %ebx
jle .LBB1_6
# %bb.4: # %.lr.ph120.preheader
movl %ebx, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # %.lr.ph120
# =>This Inner Loop Header: Depth=1
movl (%rbp,%r12,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r12
cmpq %r12, %r15
jne .LBB1_5
.LBB1_6: # %._crit_edge121
movb $10, 16(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB1_8
# %bb.7:
leaq 16(%rsp), %rsi
movl $_ZSt4cout, %edi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rax, %r15
jmp .LBB1_9
.LBB1_8:
movl $_ZSt4cout, %r15d
movl $_ZSt4cout, %edi
movl $10, %esi
callq _ZNSo3putEc
.LBB1_9: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
movl $.L.str.2, %esi
movl $6, %edx
movq %r15, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
testl %ebx, %ebx
jle .LBB1_12
# %bb.10: # %.lr.ph123.preheader
movl %ebx, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_11: # %.lr.ph123
# =>This Inner Loop Header: Depth=1
movl (%r13,%r12,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r12
cmpq %r12, %r15
jne .LBB1_11
.LBB1_12: # %._crit_edge124
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r12
cmpl $2, 12(%rsp) # 4-byte Folded Reload
jle .LBB1_26
# %bb.13:
movb $10, 16(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB1_15
# %bb.14:
leaq 16(%rsp), %rsi
movl $_ZSt4cout, %edi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rax, %r15
jmp .LBB1_16
.LBB1_26:
movb $10, 16(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB1_28
# %bb.27:
leaq 16(%rsp), %rsi
movl $_ZSt4cout, %edi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rax, %r15
jmp .LBB1_29
.LBB1_15:
movl $_ZSt4cout, %r15d
movl $_ZSt4cout, %edi
movl $10, %esi
callq _ZNSo3putEc
.LBB1_16: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit75
movl $.L.str.3, %esi
movl $9, %edx
movq %r15, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movb $10, 16(%rsp)
movq (%r15), %rax
movq -24(%rax), %rax
cmpq $0, 16(%r15,%rax)
je .LBB1_18
# %bb.17:
leaq 16(%rsp), %rsi
movl $1, %edx
movq %r15, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
testl %ebx, %ebx
jg .LBB1_20
jmp .LBB1_22
.LBB1_28:
movl $_ZSt4cout, %r15d
movl $_ZSt4cout, %edi
movl $10, %esi
callq _ZNSo3putEc
.LBB1_29: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit81
movl $.L.str.4, %esi
movl $9, %edx
movq %r15, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movb $10, 16(%rsp)
movq (%r15), %rax
movq -24(%rax), %rax
cmpq $0, 16(%r15,%rax)
je .LBB1_31
# %bb.30:
leaq 16(%rsp), %rsi
movl $1, %edx
movq %r15, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_32
.LBB1_18:
movq %r15, %rdi
movl $10, %esi
callq _ZNSo3putEc
testl %ebx, %ebx
jle .LBB1_22
.LBB1_20: # %.lr.ph126.preheader
movl %ebx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_21: # %.lr.ph126
# =>This Inner Loop Header: Depth=1
movl (%r13,%rcx,4), %edx
imull (%rbp,%rcx,4), %edx
movl %edx, (%r14,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_21
jmp .LBB1_22
.LBB1_31:
movq %r15, %rdi
movl $10, %esi
callq _ZNSo3putEc
.LBB1_32: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit84
cvtsi2ss %ebx, %xmm0
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
movss %xmm0, 12(%rsp) # 4-byte Spill
leaq 72(%rsp), %rdi
movq 88(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_33
# %bb.35: # %_Z9gpuAssert10hipError_tPKcib.exit
leaq 64(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_36
# %bb.37: # %_Z9gpuAssert10hipError_tPKcib.exit87
leaq 56(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_38
# %bb.39: # %_Z9gpuAssert10hipError_tPKcib.exit89
movq 72(%rsp), %rdi
movq %rbp, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_40
# %bb.41: # %_Z9gpuAssert10hipError_tPKcib.exit91
movq 64(%rsp), %rdi
movq %r13, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_42
# %bb.43: # %_Z9gpuAssert10hipError_tPKcib.exit93
movabsq $4294967296, %rdx # imm = 0x100000000
cvttss2si 12(%rsp), %edi # 4-byte Folded Reload
orq %rdx, %rdi
addq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_45
# %bb.44:
movq 72(%rsp), %rax
movq 64(%rsp), %rcx
movq 56(%rsp), %rdx
movl %ebx, 84(%rsp)
movq %rax, 160(%rsp)
movq %rcx, 152(%rsp)
movq %rdx, 144(%rsp)
leaq 84(%rsp), %rax
movq %rax, 16(%rsp)
leaq 160(%rsp), %rax
movq %rax, 24(%rsp)
leaq 152(%rsp), %rax
movq %rax, 32(%rsp)
leaq 144(%rsp), %rax
movq %rax, 40(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z7multMatiPiS_S_, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_45:
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB1_46
# %bb.47: # %_Z9gpuAssert10hipError_tPKcib.exit95
movq 56(%rsp), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_48
# %bb.49: # %_Z9gpuAssert10hipError_tPKcib.exit97
movq 72(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_50
# %bb.51: # %_Z9gpuAssert10hipError_tPKcib.exit99
movq 64(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_52
# %bb.53: # %_Z9gpuAssert10hipError_tPKcib.exit101
movq 56(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_54
.LBB1_22: # %_Z9gpuAssert10hipError_tPKcib.exit103
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r15
testl %ebx, %ebx
jle .LBB1_23
# %bb.60: # %.lr.ph129.preheader
movl %ebx, %eax
xorl %ecx, %ecx
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_61: # %.lr.ph129
# =>This Inner Loop Header: Depth=1
addl (%r14,%rcx,4), %ebx
incq %rcx
cmpq %rcx, %rax
jne .LBB1_61
jmp .LBB1_24
.LBB1_23:
xorl %ebx, %ebx
.LBB1_24: # %._crit_edge130
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movb $10, 16(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB1_55
# %bb.25:
leaq 16(%rsp), %rsi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rax, %rdi
jmp .LBB1_56
.LBB1_55:
movq %rax, %rbx
movq %rax, %rdi
movl $10, %esi
callq _ZNSo3putEc
movq %rbx, %rdi
.LBB1_56: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit106
movb $10, 16(%rsp)
movq (%rdi), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .LBB1_58
# %bb.57:
leaq 16(%rsp), %rsi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_59
.LBB1_58:
movl $10, %esi
callq _ZNSo3putEc
.LBB1_59: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit109
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r12, %r15
movl $_ZSt4cout, %edi
movq %r15, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movl $.L.str.8, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_33:
.cfi_def_cfa_offset 224
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $88, %r8d
jmp .LBB1_34
.LBB1_36:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $89, %r8d
jmp .LBB1_34
.LBB1_38:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $90, %r8d
jmp .LBB1_34
.LBB1_40:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $92, %r8d
jmp .LBB1_34
.LBB1_42:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $93, %r8d
jmp .LBB1_34
.LBB1_46:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $96, %r8d
jmp .LBB1_34
.LBB1_48:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $98, %r8d
jmp .LBB1_34
.LBB1_50:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $100, %r8d
jmp .LBB1_34
.LBB1_52:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $101, %r8d
jmp .LBB1_34
.LBB1_54:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $102, %r8d
.LBB1_34:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7multMatiPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7multMatiPiS_S_,@object # @_Z7multMatiPiS_S_
.section .rodata,"a",@progbits
.globl _Z7multMatiPiS_S_
.p2align 3, 0x0
_Z7multMatiPiS_S_:
.quad _Z22__device_stub__multMatiPiS_S_
.size _Z7multMatiPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "force: "
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " "
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "dist: "
.size .L.str.2, 7
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "using CPU"
.size .L.str.3, 10
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "using GPU"
.size .L.str.4, 10
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/PaluMacil/biceps/main/main.hip"
.size .L.str.5, 88
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "answer: "
.size .L.str.6, 9
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "time for calculation: "
.size .L.str.7, 23
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "ns"
.size .L.str.8, 3
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.9, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7multMatiPiS_S_"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__multMatiPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7multMatiPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7multMatiPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ IMAD R9, R4, R3, RZ ; /* 0x0000000304097224 */
/* 0x004fca00078e02ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7multMatiPiS_S_
.globl _Z7multMatiPiS_S_
.p2align 8
.type _Z7multMatiPiS_S_,@function
_Z7multMatiPiS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7multMatiPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7multMatiPiS_S_, .Lfunc_end0-_Z7multMatiPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7multMatiPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7multMatiPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ed6eb_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3774:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3774:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB3768:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE3768:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z31__device_stub__Z7multMatiPiS_S_iPiS_S_
.type _Z31__device_stub__Z7multMatiPiS_S_iPiS_S_, @function
_Z31__device_stub__Z7multMatiPiS_S_iPiS_S_:
.LFB3796:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7multMatiPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3796:
.size _Z31__device_stub__Z7multMatiPiS_S_iPiS_S_, .-_Z31__device_stub__Z7multMatiPiS_S_iPiS_S_
.globl _Z7multMatiPiS_S_
.type _Z7multMatiPiS_S_, @function
_Z7multMatiPiS_S_:
.LFB3797:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z7multMatiPiS_S_iPiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3797:
.size _Z7multMatiPiS_S_, .-_Z7multMatiPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "force: "
.LC2:
.string " "
.LC3:
.string "dist: "
.LC4:
.string "using CPU"
.LC5:
.string "using GPU"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "/home/ubuntu/Datasets/stackv2/train-structured/PaluMacil/biceps/main/main.cu"
.section .rodata.str1.1
.LC8:
.string "answer: "
.LC9:
.string "time for calculation: "
.LC10:
.string "ns"
.text
.globl main
.type main, @function
main:
.LFB3769:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movl %edi, 24(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movl %eax, 28(%rsp)
cltq
leaq 0(,%rax,4), %rbx
movq %rbx, 8(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rdi
call malloc@PLT
movq %rax, (%rsp)
testl %r13d, %r13d
jle .L20
movl %r13d, %r8d
shrl $31, %r8d
addl %r13d, %r8d
sarl %r8d
leal -1(%r13), %r14d
movl $0, %edx
movl $0, %ecx
movl $1, %eax
jmp .L25
.L41:
movq %rsi, %rdx
.L25:
movl %eax, 0(%rbp,%rdx,4)
leal 1(%rax), %esi
subl $1, %eax
cmpl %edx, %r8d
cmovg %esi, %eax
leal -10(%rcx), %esi
leal 1(%rcx), %edi
cmpl $11, %ecx
movl %esi, %ecx
cmovl %edi, %ecx
movl %ecx, (%r12,%rdx,4)
leaq 1(%rdx), %rsi
cmpq %r14, %rdx
jne .L41
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rbp, %rbx
leaq 0(,%r14,4), %rax
movq %rax, 16(%rsp)
leaq 4(%rbp,%rax), %r15
leaq _ZSt4cout(%rip), %r14
.L26:
movl (%rbx), %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC2(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L26
movl $10, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %r12, %rbx
movq 16(%rsp), %rax
leaq 4(%r12,%rax), %r15
leaq _ZSt4cout(%rip), %r14
.L27:
movl (%rbx), %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC2(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r15, %rbx
jne .L27
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r14
cmpl $2, 24(%rsp)
jg .L39
.L36:
movl $10, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movq %rax, %rdi
leaq .LC5(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movl $1024, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %r13d, %xmm0
mulss .LC6(%rip), %xmm0
call ceilf@PLT
cvttss2sil %xmm0, %eax
movl %eax, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 40(%rsp), %rdi
movq 8(%rsp), %r15
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $86, %edx
leaq .LC7(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 48(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $87, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
leaq 56(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $88, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movq %r15, %rdx
movq %rbp, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $90, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movq %r15, %rdx
movq %r12, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $91, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L51
.L32:
call cudaPeekAtLastError@PLT
movl %eax, %edi
movl $1, %ecx
movl $94, %edx
leaq .LC7(%rip), %rbx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $2, %ecx
movq 8(%rsp), %rdx
movq 56(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $96, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 40(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $98, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 48(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $99, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movq 56(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $1, %ecx
movl $100, %edx
movq %rbx, %rsi
call _Z9gpuAssert9cudaErrorPKcib
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbp
testl %r13d, %r13d
jle .L42
.L37:
movq (%rsp), %rcx
movq %rcx, %rax
leal -1(%r13), %edx
leaq 4(%rcx,%rdx,4), %rdx
movl $0, %ebx
.L34:
addl (%rax), %ebx
addq $4, %rax
cmpq %rdx, %rax
jne .L34
.L33:
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
leaq .LC9(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbp, %rsi
subq %r14, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC10(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L52
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movl 28(%rsp), %edi
call _Z31__device_stub__Z7multMatiPiS_S_iPiS_S_
jmp .L32
.L42:
movl $0, %ebx
jmp .L33
.L20:
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $10, %esi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r14
cmpl $2, 24(%rsp)
jle .L36
movl $10, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
testl %r13d, %r13d
jg .L38
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbp
movl $0, %ebx
jmp .L33
.L39:
movl $10, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
.L38:
leal -1(%r13), %ecx
movl $0, %eax
.L30:
movl 0(%rbp,%rax,4), %edx
imull (%r12,%rax,4), %edx
movq (%rsp), %rbx
movl %edx, (%rbx,%rax,4)
movq %rax, %rdx
addq $1, %rax
cmpq %rcx, %rdx
jne .L30
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbp
jmp .L37
.L52:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3769:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z7multMatiPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3799:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z7multMatiPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3799:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 981467136
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22__device_stub__multMatiPiS_S_ # -- Begin function _Z22__device_stub__multMatiPiS_S_
.p2align 4, 0x90
.type _Z22__device_stub__multMatiPiS_S_,@function
_Z22__device_stub__multMatiPiS_S_: # @_Z22__device_stub__multMatiPiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7multMatiPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__multMatiPiS_S_, .Lfunc_end0-_Z22__device_stub__multMatiPiS_S_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3a800000 # float 9.765625E-4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, 12(%rsp) # 4-byte Spill
movq 8(%rsi), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movslq %ebx, %r12
leaq (,%r12,4), %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbp
movq %r14, %rdi
callq malloc
movq %rax, %r13
movq %r14, 88(%rsp) # 8-byte Spill
movq %r14, %rdi
callq malloc
movq %rax, %r14
testl %r12d, %r12d
jle .LBB1_3
# %bb.1: # %.lr.ph
movl %ebx, %eax
movl %ebx, %ecx
shrl %ecx
movl $1, %edx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_2: # =>This Inner Loop Header: Depth=1
cmpq %rcx, %rsi
movl $0, %edi
adcl $-1, %edi
movl %edx, (%rbp,%rsi,4)
orl $1, %edi
addl %edi, %edx
leal 1(%r15), %edi
cmpl $11, %r15d
leal -10(%r15), %r8d
cmovll %edi, %r8d
movl %r8d, (%r13,%rsi,4)
incq %rsi
movl %r8d, %r15d
cmpq %rsi, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
testl %ebx, %ebx
jle .LBB1_6
# %bb.4: # %.lr.ph120.preheader
movl %ebx, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # %.lr.ph120
# =>This Inner Loop Header: Depth=1
movl (%rbp,%r12,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r12
cmpq %r12, %r15
jne .LBB1_5
.LBB1_6: # %._crit_edge121
movb $10, 16(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB1_8
# %bb.7:
leaq 16(%rsp), %rsi
movl $_ZSt4cout, %edi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rax, %r15
jmp .LBB1_9
.LBB1_8:
movl $_ZSt4cout, %r15d
movl $_ZSt4cout, %edi
movl $10, %esi
callq _ZNSo3putEc
.LBB1_9: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
movl $.L.str.2, %esi
movl $6, %edx
movq %r15, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
testl %ebx, %ebx
jle .LBB1_12
# %bb.10: # %.lr.ph123.preheader
movl %ebx, %r15d
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_11: # %.lr.ph123
# =>This Inner Loop Header: Depth=1
movl (%r13,%r12,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r12
cmpq %r12, %r15
jne .LBB1_11
.LBB1_12: # %._crit_edge124
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r12
cmpl $2, 12(%rsp) # 4-byte Folded Reload
jle .LBB1_26
# %bb.13:
movb $10, 16(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB1_15
# %bb.14:
leaq 16(%rsp), %rsi
movl $_ZSt4cout, %edi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rax, %r15
jmp .LBB1_16
.LBB1_26:
movb $10, 16(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB1_28
# %bb.27:
leaq 16(%rsp), %rsi
movl $_ZSt4cout, %edi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rax, %r15
jmp .LBB1_29
.LBB1_15:
movl $_ZSt4cout, %r15d
movl $_ZSt4cout, %edi
movl $10, %esi
callq _ZNSo3putEc
.LBB1_16: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit75
movl $.L.str.3, %esi
movl $9, %edx
movq %r15, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movb $10, 16(%rsp)
movq (%r15), %rax
movq -24(%rax), %rax
cmpq $0, 16(%r15,%rax)
je .LBB1_18
# %bb.17:
leaq 16(%rsp), %rsi
movl $1, %edx
movq %r15, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
testl %ebx, %ebx
jg .LBB1_20
jmp .LBB1_22
.LBB1_28:
movl $_ZSt4cout, %r15d
movl $_ZSt4cout, %edi
movl $10, %esi
callq _ZNSo3putEc
.LBB1_29: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit81
movl $.L.str.4, %esi
movl $9, %edx
movq %r15, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movb $10, 16(%rsp)
movq (%r15), %rax
movq -24(%rax), %rax
cmpq $0, 16(%r15,%rax)
je .LBB1_31
# %bb.30:
leaq 16(%rsp), %rsi
movl $1, %edx
movq %r15, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_32
.LBB1_18:
movq %r15, %rdi
movl $10, %esi
callq _ZNSo3putEc
testl %ebx, %ebx
jle .LBB1_22
.LBB1_20: # %.lr.ph126.preheader
movl %ebx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_21: # %.lr.ph126
# =>This Inner Loop Header: Depth=1
movl (%r13,%rcx,4), %edx
imull (%rbp,%rcx,4), %edx
movl %edx, (%r14,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_21
jmp .LBB1_22
.LBB1_31:
movq %r15, %rdi
movl $10, %esi
callq _ZNSo3putEc
.LBB1_32: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit84
cvtsi2ss %ebx, %xmm0
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
movss %xmm0, 12(%rsp) # 4-byte Spill
leaq 72(%rsp), %rdi
movq 88(%rsp), %r15 # 8-byte Reload
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_33
# %bb.35: # %_Z9gpuAssert10hipError_tPKcib.exit
leaq 64(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_36
# %bb.37: # %_Z9gpuAssert10hipError_tPKcib.exit87
leaq 56(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_38
# %bb.39: # %_Z9gpuAssert10hipError_tPKcib.exit89
movq 72(%rsp), %rdi
movq %rbp, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_40
# %bb.41: # %_Z9gpuAssert10hipError_tPKcib.exit91
movq 64(%rsp), %rdi
movq %r13, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_42
# %bb.43: # %_Z9gpuAssert10hipError_tPKcib.exit93
movabsq $4294967296, %rdx # imm = 0x100000000
cvttss2si 12(%rsp), %edi # 4-byte Folded Reload
orq %rdx, %rdi
addq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_45
# %bb.44:
movq 72(%rsp), %rax
movq 64(%rsp), %rcx
movq 56(%rsp), %rdx
movl %ebx, 84(%rsp)
movq %rax, 160(%rsp)
movq %rcx, 152(%rsp)
movq %rdx, 144(%rsp)
leaq 84(%rsp), %rax
movq %rax, 16(%rsp)
leaq 160(%rsp), %rax
movq %rax, 24(%rsp)
leaq 152(%rsp), %rax
movq %rax, 32(%rsp)
leaq 144(%rsp), %rax
movq %rax, 40(%rsp)
leaq 128(%rsp), %rdi
leaq 112(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
movq 112(%rsp), %rcx
movl 120(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z7multMatiPiS_S_, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_45:
callq hipPeekAtLastError
testl %eax, %eax
jne .LBB1_46
# %bb.47: # %_Z9gpuAssert10hipError_tPKcib.exit95
movq 56(%rsp), %rsi
movq %r14, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_48
# %bb.49: # %_Z9gpuAssert10hipError_tPKcib.exit97
movq 72(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_50
# %bb.51: # %_Z9gpuAssert10hipError_tPKcib.exit99
movq 64(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_52
# %bb.53: # %_Z9gpuAssert10hipError_tPKcib.exit101
movq 56(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_54
.LBB1_22: # %_Z9gpuAssert10hipError_tPKcib.exit103
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r15
testl %ebx, %ebx
jle .LBB1_23
# %bb.60: # %.lr.ph129.preheader
movl %ebx, %eax
xorl %ecx, %ecx
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_61: # %.lr.ph129
# =>This Inner Loop Header: Depth=1
addl (%r14,%rcx,4), %ebx
incq %rcx
cmpq %rcx, %rax
jne .LBB1_61
jmp .LBB1_24
.LBB1_23:
xorl %ebx, %ebx
.LBB1_24: # %._crit_edge130
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movb $10, 16(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB1_55
# %bb.25:
leaq 16(%rsp), %rsi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rax, %rdi
jmp .LBB1_56
.LBB1_55:
movq %rax, %rbx
movq %rax, %rdi
movl $10, %esi
callq _ZNSo3putEc
movq %rbx, %rdi
.LBB1_56: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit106
movb $10, 16(%rsp)
movq (%rdi), %rax
movq -24(%rax), %rax
cmpq $0, 16(%rdi,%rax)
je .LBB1_58
# %bb.57:
leaq 16(%rsp), %rsi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_59
.LBB1_58:
movl $10, %esi
callq _ZNSo3putEc
.LBB1_59: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit109
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $22, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r12, %r15
movl $_ZSt4cout, %edi
movq %r15, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movl $.L.str.8, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_33:
.cfi_def_cfa_offset 224
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $88, %r8d
jmp .LBB1_34
.LBB1_36:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $89, %r8d
jmp .LBB1_34
.LBB1_38:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $90, %r8d
jmp .LBB1_34
.LBB1_40:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $92, %r8d
jmp .LBB1_34
.LBB1_42:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $93, %r8d
jmp .LBB1_34
.LBB1_46:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $96, %r8d
jmp .LBB1_34
.LBB1_48:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $98, %r8d
jmp .LBB1_34
.LBB1_50:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $100, %r8d
jmp .LBB1_34
.LBB1_52:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $101, %r8d
jmp .LBB1_34
.LBB1_54:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.9, %esi
movl $.L.str.5, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $102, %r8d
.LBB1_34:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7multMatiPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7multMatiPiS_S_,@object # @_Z7multMatiPiS_S_
.section .rodata,"a",@progbits
.globl _Z7multMatiPiS_S_
.p2align 3, 0x0
_Z7multMatiPiS_S_:
.quad _Z22__device_stub__multMatiPiS_S_
.size _Z7multMatiPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "force: "
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " "
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "dist: "
.size .L.str.2, 7
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "using CPU"
.size .L.str.3, 10
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "using GPU"
.size .L.str.4, 10
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/PaluMacil/biceps/main/main.hip"
.size .L.str.5, 88
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "answer: "
.size .L.str.6, 9
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "time for calculation: "
.size .L.str.7, 23
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "ns"
.size .L.str.8, 3
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "GPUassert: %s %s %d\n"
.size .L.str.9, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7multMatiPiS_S_"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__multMatiPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7multMatiPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<cuda_runtime.h>
#include <stdio.h>
#include <stdlib.h>
int main(int argc, char **argv){
cudaDeviceProp prop;
int count;
cudaGetDeviceCount(&count);
printf("Number of GPUs on the Node is %d\n", count);
for (int i=0; i < count; ++i){
cudaGetDeviceProperties(&prop, i);
printf("--- General Information for device %d----\n", i);
printf("Name: %s\n", prop.name);
printf("Compute capability: %d.%d\n", prop.major, prop.minor);
printf("GPU Clock rate: %.0f MHz\n", prop.clockRate*1e-3f);
printf("------Memory Information for device %d\n", i);
printf("Total global mem: %.2f GBytes\n", (float) prop.totalGlobalMem / pow(1024, 3));
printf("Memory clock rate: %.0f MHz\n", prop.memoryClockRate * 1e-3f);
printf("Memory bus width: %d-bit \n", prop.memoryBusWidth );
printf("L2 cache size: %d Bytes\n", prop.l2CacheSize );
printf("Threads and Blocks information for %d GPU");
printf(" Maximum number of Threads per block %d\n", prop.maxThreadsPerBlock);
printf(" Maximum size of each dimension of block %d x %d x %d\n", prop.maxThreadsDim[0], prop.maxThreadsDim[1], prop.maxThreadsDim[2]);
printf(" Maximum sizes of each dimension of grid %d x %d x %d\n", prop.maxGridSize[0], prop.maxGridSize[1], prop.maxGridSize[2]);
return 0;
}
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<cuda_runtime.h>
#include <stdio.h>
#include <stdlib.h>
int main(int argc, char **argv){
cudaDeviceProp prop;
int count;
cudaGetDeviceCount(&count);
printf("Number of GPUs on the Node is %d\n", count);
for (int i=0; i < count; ++i){
cudaGetDeviceProperties(&prop, i);
printf("--- General Information for device %d----\n", i);
printf("Name: %s\n", prop.name);
printf("Compute capability: %d.%d\n", prop.major, prop.minor);
printf("GPU Clock rate: %.0f MHz\n", prop.clockRate*1e-3f);
printf("------Memory Information for device %d\n", i);
printf("Total global mem: %.2f GBytes\n", (float) prop.totalGlobalMem / pow(1024, 3));
printf("Memory clock rate: %.0f MHz\n", prop.memoryClockRate * 1e-3f);
printf("Memory bus width: %d-bit \n", prop.memoryBusWidth );
printf("L2 cache size: %d Bytes\n", prop.l2CacheSize );
printf("Threads and Blocks information for %d GPU");
printf(" Maximum number of Threads per block %d\n", prop.maxThreadsPerBlock);
printf(" Maximum size of each dimension of block %d x %d x %d\n", prop.maxThreadsDim[0], prop.maxThreadsDim[1], prop.maxThreadsDim[2]);
printf(" Maximum sizes of each dimension of grid %d x %d x %d\n", prop.maxGridSize[0], prop.maxGridSize[1], prop.maxGridSize[2]);
return 0;
}
return 0;
} | .file "tmpxft_00142af3_00000000-6_deviceQuery.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Number of GPUs on the Node is %d\n"
.align 8
.LC1:
.string "--- General Information for device %d----\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Name: %s\n"
.LC3:
.string "Compute capability: %d.%d\n"
.LC5:
.string "GPU Clock rate: %.0f MHz\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "------Memory Information for device %d\n"
.align 8
.LC8:
.string "Total global mem: %.2f GBytes\n"
.section .rodata.str1.1
.LC9:
.string "Memory clock rate: %.0f MHz\n"
.LC10:
.string "Memory bus width: %d-bit \n"
.LC11:
.string "L2 cache size: %d Bytes\n"
.section .rodata.str1.8
.align 8
.LC12:
.string "Threads and Blocks information for %d GPU"
.align 8
.LC13:
.string " Maximum number of Threads per block %d\n"
.align 8
.LC14:
.string " Maximum size of each dimension of block %d x %d x %d\n"
.align 8
.LC15:
.string " Maximum sizes of each dimension of grid %d x %d x %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1056, %rsp
.cfi_def_cfa_offset 1072
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 12(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jg .L9
.L4:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L10
movl $0, %eax
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
leaq 16(%rsp), %rbx
movl $0, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movl $0, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %ecx
movl 376(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2ssl 364(%rsp), %xmm0
mulss .LC4(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rax
testq %rax, %rax
js .L5
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
.L6:
cvtss2sd %xmm0, %xmm0
mulsd .LC7(%rip), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2ssl 624(%rsp), %xmm0
mulss .LC4(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 628(%rsp), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 632(%rsp), %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L4
.L5:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
addss %xmm0, %xmm0
jmp .L6
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 981668463
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC7:
.long 0
.long 1041235968
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<cuda_runtime.h>
#include <stdio.h>
#include <stdlib.h>
int main(int argc, char **argv){
cudaDeviceProp prop;
int count;
cudaGetDeviceCount(&count);
printf("Number of GPUs on the Node is %d\n", count);
for (int i=0; i < count; ++i){
cudaGetDeviceProperties(&prop, i);
printf("--- General Information for device %d----\n", i);
printf("Name: %s\n", prop.name);
printf("Compute capability: %d.%d\n", prop.major, prop.minor);
printf("GPU Clock rate: %.0f MHz\n", prop.clockRate*1e-3f);
printf("------Memory Information for device %d\n", i);
printf("Total global mem: %.2f GBytes\n", (float) prop.totalGlobalMem / pow(1024, 3));
printf("Memory clock rate: %.0f MHz\n", prop.memoryClockRate * 1e-3f);
printf("Memory bus width: %d-bit \n", prop.memoryBusWidth );
printf("L2 cache size: %d Bytes\n", prop.l2CacheSize );
printf("Threads and Blocks information for %d GPU");
printf(" Maximum number of Threads per block %d\n", prop.maxThreadsPerBlock);
printf(" Maximum size of each dimension of block %d x %d x %d\n", prop.maxThreadsDim[0], prop.maxThreadsDim[1], prop.maxThreadsDim[2]);
printf(" Maximum sizes of each dimension of grid %d x %d x %d\n", prop.maxGridSize[0], prop.maxGridSize[1], prop.maxGridSize[2]);
return 0;
}
return 0;
} | #include<hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
int main(int argc, char **argv){
hipDeviceProp_t prop;
int count;
hipGetDeviceCount(&count);
printf("Number of GPUs on the Node is %d\n", count);
for (int i=0; i < count; ++i){
hipGetDeviceProperties(&prop, i);
printf("--- General Information for device %d----\n", i);
printf("Name: %s\n", prop.name);
printf("Compute capability: %d.%d\n", prop.major, prop.minor);
printf("GPU Clock rate: %.0f MHz\n", prop.clockRate*1e-3f);
printf("------Memory Information for device %d\n", i);
printf("Total global mem: %.2f GBytes\n", (float) prop.totalGlobalMem / pow(1024, 3));
printf("Memory clock rate: %.0f MHz\n", prop.memoryClockRate * 1e-3f);
printf("Memory bus width: %d-bit \n", prop.memoryBusWidth );
printf("L2 cache size: %d Bytes\n", prop.l2CacheSize );
printf("Threads and Blocks information for %d GPU");
printf(" Maximum number of Threads per block %d\n", prop.maxThreadsPerBlock);
printf(" Maximum size of each dimension of block %d x %d x %d\n", prop.maxThreadsDim[0], prop.maxThreadsDim[1], prop.maxThreadsDim[2]);
printf(" Maximum sizes of each dimension of grid %d x %d x %d\n", prop.maxGridSize[0], prop.maxGridSize[1], prop.maxGridSize[2]);
return 0;
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
int main(int argc, char **argv){
hipDeviceProp_t prop;
int count;
hipGetDeviceCount(&count);
printf("Number of GPUs on the Node is %d\n", count);
for (int i=0; i < count; ++i){
hipGetDeviceProperties(&prop, i);
printf("--- General Information for device %d----\n", i);
printf("Name: %s\n", prop.name);
printf("Compute capability: %d.%d\n", prop.major, prop.minor);
printf("GPU Clock rate: %.0f MHz\n", prop.clockRate*1e-3f);
printf("------Memory Information for device %d\n", i);
printf("Total global mem: %.2f GBytes\n", (float) prop.totalGlobalMem / pow(1024, 3));
printf("Memory clock rate: %.0f MHz\n", prop.memoryClockRate * 1e-3f);
printf("Memory bus width: %d-bit \n", prop.memoryBusWidth );
printf("L2 cache size: %d Bytes\n", prop.l2CacheSize );
printf("Threads and Blocks information for %d GPU");
printf(" Maximum number of Threads per block %d\n", prop.maxThreadsPerBlock);
printf(" Maximum size of each dimension of block %d x %d x %d\n", prop.maxThreadsDim[0], prop.maxThreadsDim[1], prop.maxThreadsDim[2]);
printf(" Maximum sizes of each dimension of grid %d x %d x %d\n", prop.maxGridSize[0], prop.maxGridSize[1], prop.maxGridSize[2]);
return 0;
}
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
int main(int argc, char **argv){
hipDeviceProp_t prop;
int count;
hipGetDeviceCount(&count);
printf("Number of GPUs on the Node is %d\n", count);
for (int i=0; i < count; ++i){
hipGetDeviceProperties(&prop, i);
printf("--- General Information for device %d----\n", i);
printf("Name: %s\n", prop.name);
printf("Compute capability: %d.%d\n", prop.major, prop.minor);
printf("GPU Clock rate: %.0f MHz\n", prop.clockRate*1e-3f);
printf("------Memory Information for device %d\n", i);
printf("Total global mem: %.2f GBytes\n", (float) prop.totalGlobalMem / pow(1024, 3));
printf("Memory clock rate: %.0f MHz\n", prop.memoryClockRate * 1e-3f);
printf("Memory bus width: %d-bit \n", prop.memoryBusWidth );
printf("L2 cache size: %d Bytes\n", prop.l2CacheSize );
printf("Threads and Blocks information for %d GPU");
printf(" Maximum number of Threads per block %d\n", prop.maxThreadsPerBlock);
printf(" Maximum size of each dimension of block %d x %d x %d\n", prop.maxThreadsDim[0], prop.maxThreadsDim[1], prop.maxThreadsDim[2]);
printf(" Maximum sizes of each dimension of grid %d x %d x %d\n", prop.maxGridSize[0], prop.maxGridSize[1], prop.maxGridSize[2]);
return 0;
}
return 0;
} | .text
.file "deviceQuery.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x3a83126f # float 0.00100000005
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI0_1:
.quad 0x3e10000000000000 # double 9.3132257461547852E-10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -16
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
movl 12(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
cmpl $0, 12(%rsp)
jle .LBB0_5
# %bb.1:
leaq 16(%rsp), %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.1, %edi
xorl %esi, %esi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 376(%rsp), %esi
movl 380(%rsp), %edx
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
cvtsi2ssl 364(%rsp), %xmm0
mulss .LCPI0_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movl $.L.str.5, %edi
xorl %esi, %esi
xorl %eax, %eax
callq printf
movq 304(%rsp), %rax
testq %rax, %rax
js .LBB0_2
# %bb.3:
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
jmp .LBB0_4
.LBB0_2:
movq %rax, %rcx
shrq %rcx
andl $1, %eax
orq %rcx, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
addss %xmm0, %xmm0
.LBB0_4:
cvtss2sd %xmm0, %xmm0
mulsd .LCPI0_1(%rip), %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
xorps %xmm0, %xmm0
cvtsi2ssl 624(%rsp), %xmm0
mulss .LCPI0_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movl 628(%rsp), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl 632(%rsp), %esi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl 336(%rsp), %esi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl 340(%rsp), %esi
movl 344(%rsp), %edx
movl 348(%rsp), %ecx
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movl 352(%rsp), %esi
movl 356(%rsp), %edx
movl 360(%rsp), %ecx
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
.LBB0_5: # %.critedge
xorl %eax, %eax
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Number of GPUs on the Node is %d\n"
.size .L.str, 34
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "--- General Information for device %d----\n"
.size .L.str.1, 43
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Name: %s\n"
.size .L.str.2, 11
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Compute capability: %d.%d\n"
.size .L.str.3, 27
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "GPU Clock rate: %.0f MHz\n"
.size .L.str.4, 26
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "------Memory Information for device %d\n"
.size .L.str.5, 40
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Total global mem: %.2f GBytes\n"
.size .L.str.6, 31
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Memory clock rate: %.0f MHz\n"
.size .L.str.7, 29
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Memory bus width: %d-bit \n"
.size .L.str.8, 27
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "L2 cache size: %d Bytes\n"
.size .L.str.9, 25
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Threads and Blocks information for %d GPU"
.size .L.str.10, 42
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz " Maximum number of Threads per block %d\n"
.size .L.str.11, 41
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz " Maximum size of each dimension of block %d x %d x %d\n"
.size .L.str.12, 56
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz " Maximum sizes of each dimension of grid %d x %d x %d\n"
.size .L.str.13, 55
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00142af3_00000000-6_deviceQuery.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Number of GPUs on the Node is %d\n"
.align 8
.LC1:
.string "--- General Information for device %d----\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Name: %s\n"
.LC3:
.string "Compute capability: %d.%d\n"
.LC5:
.string "GPU Clock rate: %.0f MHz\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "------Memory Information for device %d\n"
.align 8
.LC8:
.string "Total global mem: %.2f GBytes\n"
.section .rodata.str1.1
.LC9:
.string "Memory clock rate: %.0f MHz\n"
.LC10:
.string "Memory bus width: %d-bit \n"
.LC11:
.string "L2 cache size: %d Bytes\n"
.section .rodata.str1.8
.align 8
.LC12:
.string "Threads and Blocks information for %d GPU"
.align 8
.LC13:
.string " Maximum number of Threads per block %d\n"
.align 8
.LC14:
.string " Maximum size of each dimension of block %d x %d x %d\n"
.align 8
.LC15:
.string " Maximum sizes of each dimension of grid %d x %d x %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1056, %rsp
.cfi_def_cfa_offset 1072
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 12(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jg .L9
.L4:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L10
movl $0, %eax
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
leaq 16(%rsp), %rbx
movl $0, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movl $0, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %ecx
movl 376(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2ssl 364(%rsp), %xmm0
mulss .LC4(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rax
testq %rax, %rax
js .L5
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
.L6:
cvtss2sd %xmm0, %xmm0
mulsd .LC7(%rip), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2ssl 624(%rsp), %xmm0
mulss .LC4(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 628(%rsp), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 632(%rsp), %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L4
.L5:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
addss %xmm0, %xmm0
jmp .L6
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 981668463
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC7:
.long 0
.long 1041235968
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "deviceQuery.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x3a83126f # float 0.00100000005
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI0_1:
.quad 0x3e10000000000000 # double 9.3132257461547852E-10
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -16
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
movl 12(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
cmpl $0, 12(%rsp)
jle .LBB0_5
# %bb.1:
leaq 16(%rsp), %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.1, %edi
xorl %esi, %esi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl 376(%rsp), %esi
movl 380(%rsp), %edx
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
cvtsi2ssl 364(%rsp), %xmm0
mulss .LCPI0_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movl $.L.str.5, %edi
xorl %esi, %esi
xorl %eax, %eax
callq printf
movq 304(%rsp), %rax
testq %rax, %rax
js .LBB0_2
# %bb.3:
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
jmp .LBB0_4
.LBB0_2:
movq %rax, %rcx
shrq %rcx
andl $1, %eax
orq %rcx, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
addss %xmm0, %xmm0
.LBB0_4:
cvtss2sd %xmm0, %xmm0
mulsd .LCPI0_1(%rip), %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
xorps %xmm0, %xmm0
cvtsi2ssl 624(%rsp), %xmm0
mulss .LCPI0_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movl 628(%rsp), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl 632(%rsp), %esi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl 336(%rsp), %esi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl 340(%rsp), %esi
movl 344(%rsp), %edx
movl 348(%rsp), %ecx
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movl 352(%rsp), %esi
movl 356(%rsp), %edx
movl 360(%rsp), %ecx
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
.LBB0_5: # %.critedge
xorl %eax, %eax
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Number of GPUs on the Node is %d\n"
.size .L.str, 34
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "--- General Information for device %d----\n"
.size .L.str.1, 43
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Name: %s\n"
.size .L.str.2, 11
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Compute capability: %d.%d\n"
.size .L.str.3, 27
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "GPU Clock rate: %.0f MHz\n"
.size .L.str.4, 26
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "------Memory Information for device %d\n"
.size .L.str.5, 40
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Total global mem: %.2f GBytes\n"
.size .L.str.6, 31
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Memory clock rate: %.0f MHz\n"
.size .L.str.7, 29
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Memory bus width: %d-bit \n"
.size .L.str.8, 27
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "L2 cache size: %d Bytes\n"
.size .L.str.9, 25
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Threads and Blocks information for %d GPU"
.size .L.str.10, 42
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz " Maximum number of Threads per block %d\n"
.size .L.str.11, 41
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz " Maximum size of each dimension of block %d x %d x %d\n"
.size .L.str.12, 56
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz " Maximum sizes of each dimension of grid %d x %d x %d\n"
.size .L.str.13, 55
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <math.h>
#include <curand.h>
#include <curand_kernel.h>
// Kernel function to perform C = A*B
__global__
void mat_mult(int n, float *A, float *B, float *C)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
int sum = 0;
for (int k = 0; k < n; k++){
sum += A[idy*n + k]*B[k*n + idx];
}
C[idy*n +idx] = sum;
}
int main(void)
{
//N is the size of the matrix
int N = 1<<8;
//block_size is the width and height of cuda block
//total threads per block = block_size*block_size
int block_size = 1<<5;
//grid_size is the width and height of a cuda grid
//total blocks per grid = grid_size*grid_size
int grid_size = N/block_size;
// Allocate Unified Memory – accessible from CPU or GPU
float *A, *B, *C;
cudaMallocManaged(&A, N*N*sizeof(float));
cudaMallocManaged(&B, N*N*sizeof(float));
cudaMallocManaged(&C, N*N*sizeof(float));
// initialize A and B arrays on the host
for (int i = 0; i < N; i++) {
for ( int j = 0; j < N; j++){
if(i == j){
A[i*N +j] = i;
B[i*N +j] = i;
} else {
A[i*N +j] = 0;
B[i*N +j] = 0;
}
}
}
// Run kernel with 2-D grid and 2-D blocks.
dim3 block_dim(block_size, block_size);
dim3 grid_dim(grid_size, grid_size);
mat_mult<<<grid_dim, block_dim>>>(N, A, B, C);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
// Check for errors (diagonal should be squares)
int failure = 0;
for (int i = 0; i < N; i++){
for (int j = 0; j < N; j++){
if(i == j && C[i*N + j] != (float)i*i){
failure = 1;
} else if (i !=j && C[i*N + j] != 0.0){
failure = 1;
}
}
}
//Helpful for printing out a matrix/debugging :^)
/*for (int i = 0; i < N; i++){
for (int j = 0; j < N; j++){
printf("%f,",A[i*N +j]);
}
printf("\n");
}*/
if(failure){
printf("There was a failure, big sad!\n");
} else {
printf("Tests Pass!\n");
}
// Free memory
cudaFree(A);
cudaFree(B);
cudaFree(C);
return 0;
} | code for sm_80
Function : _Z8mat_multiPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002600 */
/*0020*/ MOV R0, c[0x0][0x160] ; /* 0x0000580000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R12, -RZ, RZ, 0, 0 ; /* 0x00000000ff0c7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0080*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R4, R4, c[0x0][0x4], R5 ; /* 0x0000010004047a24 */
/* 0x001fc800078e0205 */
/*00a0*/ IMAD R4, R4, c[0x0][0x160], RZ ; /* 0x0000580004047a24 */
/* 0x000fe400078e02ff */
/*00b0*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x002fe200078e0203 */
/*00c0*/ @!P0 BRA 0xf90 ; /* 0x00000ec000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R3, R0.reuse, -0x1, RZ ; /* 0xffffffff00037810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300057812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*0100*/ MOV R12, RZ ; /* 0x000000ff000c7202 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fd20000000f00 */
/*0120*/ @!P0 BRA 0xe50 ; /* 0x00000d2000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R6, -R5, c[0x0][0x160], RZ ; /* 0x0000580005067a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ HFMA2.MMA R19, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff137435 */
/* 0x000fe200000001ff */
/*0150*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0160*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0170*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*0180*/ MOV R12, RZ ; /* 0x000000ff000c7202 */
/* 0x000fca0000000f00 */
/*0190*/ IMAD.WIDE R18, R2, R19, c[0x0][0x170] ; /* 0x00005c0002127625 */
/* 0x000fcc00078e0213 */
/*01a0*/ @!P0 BRA 0xc40 ; /* 0x00000a9000008947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x880 ; /* 0x000006a000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ MOV R14, UR6 ; /* 0x00000006000e7c02 */
/* 0x000fe20008000f00 */
/*0200*/ LDG.E R13, [R18.64] ; /* 0x00000004120d7981 */
/* 0x0010a2000c1e1900 */
/*0210*/ MOV R15, UR7 ; /* 0x00000007000f7c02 */
/* 0x000fca0008000f00 */
/*0220*/ IMAD.WIDE R14, R4, 0x4, R14 ; /* 0x00000004040e7825 */
/* 0x000fca00078e020e */
/*0230*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IMAD.WIDE R10, R0, 0x4, R18 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0212 */
/*0250*/ LDG.E R9, [R14.64+0x4] ; /* 0x000004040e097981 */
/* 0x000ee8000c1e1900 */
/*0260*/ LDG.E R8, [R10.64] ; /* 0x000000040a087981 */
/* 0x0022e2000c1e1900 */
/*0270*/ IMAD.WIDE R28, R0, 0x4, R10 ; /* 0x00000004001c7825 */
/* 0x000fc600078e020a */
/*0280*/ LDG.E R7, [R14.64+0x8] ; /* 0x000008040e077981 */
/* 0x000f28000c1e1900 */
/*0290*/ LDG.E R22, [R28.64] ; /* 0x000000041c167981 */
/* 0x000b22000c1e1900 */
/*02a0*/ IMAD.WIDE R20, R0, 0x4, R28 ; /* 0x0000000400147825 */
/* 0x000fc600078e021c */
/*02b0*/ LDG.E R16, [R14.64+0xc] ; /* 0x00000c040e107981 */
/* 0x000ee8000c1e1900 */
/*02c0*/ LDG.E R17, [R20.64] ; /* 0x0000000414117981 */
/* 0x0002e8000c1e1900 */
/*02d0*/ LDG.E R19, [R14.64+0x10] ; /* 0x000010040e137981 */
/* 0x001ee8000c1e1900 */
/*02e0*/ LDG.E R26, [R14.64+0x14] ; /* 0x000014040e1a7981 */
/* 0x000ee2000c1e1900 */
/*02f0*/ IMAD.WIDE R20, R0, 0x4, R20 ; /* 0x0000000400147825 */
/* 0x002fc600078e0214 */
/*0300*/ LDG.E R28, [R14.64+0x18] ; /* 0x000018040e1c7981 */
/* 0x020f68000c1e1900 */
/*0310*/ LDG.E R18, [R20.64] ; /* 0x0000000414127981 */
/* 0x000122000c1e1900 */
/*0320*/ IMAD.WIDE R10, R0, 0x4, R20 ; /* 0x00000004000a7825 */
/* 0x000fca00078e0214 */
/*0330*/ LDG.E R25, [R10.64] ; /* 0x000000040a197981 */
/* 0x000324000c1e1900 */
/*0340*/ IMAD.WIDE R10, R0, 0x4, R10 ; /* 0x00000004000a7825 */
/* 0x002fca00078e020a */
/*0350*/ LDG.E R27, [R10.64] ; /* 0x000000040a1b7981 */
/* 0x000362000c1e1900 */
/*0360*/ IMAD.WIDE R20, R0, 0x4, R10 ; /* 0x0000000400147825 */
/* 0x001fca00078e020a */
/*0370*/ LDG.E R24, [R20.64] ; /* 0x0000000414187981 */
/* 0x000122000c1e1900 */
/*0380*/ FFMA R29, R13, R23, R12 ; /* 0x000000170d1d7223 */
/* 0x004fc6000000000c */
/*0390*/ LDG.E R23, [R14.64+0x1c] ; /* 0x00001c040e177981 */
/* 0x000ea6000c1e1900 */
/*03a0*/ F2I.TRUNC.NTZ R29, R29 ; /* 0x0000001d001d7305 */
/* 0x000e22000020f100 */
/*03b0*/ IMAD.WIDE R12, R0, 0x4, R20 ; /* 0x00000004000c7825 */
/* 0x000fce00078e0214 */
/*03c0*/ I2F R29, R29 ; /* 0x0000001d001d7306 */
/* 0x001ee40000201400 */
/*03d0*/ FFMA R29, R8, R9, R29 ; /* 0x00000009081d7223 */
/* 0x008fe4000000001d */
/*03e0*/ LDG.E R8, [R14.64+0x20] ; /* 0x000020040e087981 */
/* 0x000ee8000c1e1900 */
/*03f0*/ LDG.E R9, [R12.64] ; /* 0x000000040c097981 */
/* 0x0000e2000c1e1900 */
/*0400*/ F2I.TRUNC.NTZ R10, R29 ; /* 0x0000001d000a7305 */
/* 0x002e70000020f100 */
/*0410*/ I2F R20, R10 ; /* 0x0000000a00147306 */
/* 0x0023240000201400 */
/*0420*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x002fc400078e020c */
/*0430*/ LDG.E R13, [R14.64+0x28] ; /* 0x000028040e0d7981 */
/* 0x001ee4000c1e1900 */
/*0440*/ FFMA R20, R22, R7, R20 ; /* 0x0000000716147223 */
/* 0x010fe40000000014 */
/*0450*/ LDG.E R7, [R14.64+0x24] ; /* 0x000024040e077981 */
/* 0x000f28000c1e1900 */
/*0460*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000122000c1e1900 */
/*0470*/ F2I.TRUNC.NTZ R20, R20 ; /* 0x0000001400147305 */
/* 0x000e70000020f100 */
/*0480*/ I2F R12, R20 ; /* 0x00000014000c7306 */
/* 0x0023640000201400 */
/*0490*/ IMAD.WIDE R20, R0, 0x4, R10 ; /* 0x0000000400147825 */
/* 0x002fc400078e020a */
/*04a0*/ LDG.E R11, [R14.64+0x2c] ; /* 0x00002c040e0b7981 */
/* 0x001f24000c1e1900 */
/*04b0*/ FFMA R16, R17, R16, R12 ; /* 0x0000001011107223 */
/* 0x020fe4000000000c */
/*04c0*/ LDG.E R12, [R20.64] ; /* 0x00000004140c7981 */
/* 0x000164000c1e1900 */
/*04d0*/ F2I.TRUNC.NTZ R29, R16 ; /* 0x00000010001d7305 */
/* 0x000e70000020f100 */
/*04e0*/ I2F R29, R29 ; /* 0x0000001d001d7306 */
/* 0x002e620000201400 */
/*04f0*/ IMAD.WIDE R16, R0, 0x4, R20 ; /* 0x0000000400107825 */
/* 0x000fca00078e0214 */
/*0500*/ LDG.E R10, [R16.64] ; /* 0x00000004100a7981 */
/* 0x000162000c1e1900 */
/*0510*/ FFMA R18, R18, R19, R29 ; /* 0x0000001312127223 */
/* 0x002fcc000000001d */
/*0520*/ F2I.TRUNC.NTZ R18, R18 ; /* 0x0000001200127305 */
/* 0x000e30000020f100 */
/*0530*/ I2F R20, R18 ; /* 0x0000001200147306 */
/* 0x0010640000201400 */
/*0540*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x001fc800078e0210 */
/*0550*/ FFMA R29, R25, R26, R20 ; /* 0x0000001a191d7223 */
/* 0x002fe40000000014 */
/*0560*/ LDG.E R25, [R14.64+0x30] ; /* 0x000030040e197981 */
/* 0x000f68000c1e1900 */
/*0570*/ LDG.E R26, [R18.64] ; /* 0x00000004121a7981 */
/* 0x000162000c1e1900 */
/*0580*/ F2I.TRUNC.NTZ R29, R29 ; /* 0x0000001d001d7305 */
/* 0x000e62000020f100 */
/*0590*/ IMAD.WIDE R20, R0, 0x4, R18 ; /* 0x0000000400147825 */
/* 0x000fce00078e0212 */
/*05a0*/ I2F R29, R29 ; /* 0x0000001d001d7306 */
/* 0x002e640000201400 */
/*05b0*/ FFMA R17, R27, R28, R29 ; /* 0x0000001c1b117223 */
/* 0x002fe4000000001d */
/*05c0*/ LDG.E R28, [R14.64+0x34] ; /* 0x000034040e1c7981 */
/* 0x000f68000c1e1900 */
/*05d0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000562000c1e1900 */
/*05e0*/ F2I.TRUNC.NTZ R17, R17 ; /* 0x0000001100117305 */
/* 0x000e30000020f100 */
/*05f0*/ I2F R18, R17 ; /* 0x0000001100127306 */
/* 0x0010a40000201400 */
/*0600*/ IMAD.WIDE R16, R0, 0x4, R20 ; /* 0x0000000400107825 */
/* 0x001fc800078e0214 */
/*0610*/ FFMA R20, R24, R23, R18 ; /* 0x0000001718147223 */
/* 0x004fe40000000012 */
/*0620*/ LDG.E R24, [R14.64+0x38] ; /* 0x000038040e187981 */
/* 0x000ea8000c1e1900 */
/*0630*/ LDG.E R23, [R16.64] ; /* 0x0000000410177981 */
/* 0x0000a2000c1e1900 */
/*0640*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fe200078e0210 */
/*0650*/ F2I.TRUNC.NTZ R20, R20 ; /* 0x0000001400147305 */
/* 0x000e68000020f100 */
/*0660*/ LDG.E R29, [R18.64] ; /* 0x00000004121d7981 */
/* 0x000ea8000c1e1900 */
/*0670*/ LDG.E R16, [R14.64+0x3c] ; /* 0x00003c040e107981 */
/* 0x001ea2000c1e1900 */
/*0680*/ I2F R21, R20 ; /* 0x0000001400157306 */
/* 0x002ee40000201400 */
/*0690*/ FFMA R8, R9, R8, R21 ; /* 0x0000000809087223 */
/* 0x008fcc0000000015 */
/*06a0*/ F2I.TRUNC.NTZ R8, R8 ; /* 0x0000000800087305 */
/* 0x000e30000020f100 */
/*06b0*/ I2F R9, R8 ; /* 0x0000000800097306 */
/* 0x001f240000201400 */
/*06c0*/ FFMA R7, R22, R7, R9 ; /* 0x0000000716077223 */
/* 0x010fcc0000000009 */
/*06d0*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e30000020f100 */
/*06e0*/ I2F R9, R7 ; /* 0x0000000700097306 */
/* 0x001f640000201400 */
/*06f0*/ FFMA R9, R12, R13, R9 ; /* 0x0000000d0c097223 */
/* 0x020fcc0000000009 */
/*0700*/ F2I.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e30000020f100 */
/*0710*/ I2F R12, R9 ; /* 0x00000009000c7306 */
/* 0x001e240000201400 */
/*0720*/ FFMA R10, R10, R11, R12 ; /* 0x0000000b0a0a7223 */
/* 0x001fcc000000000c */
/*0730*/ F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a7305 */
/* 0x000e30000020f100 */
/*0740*/ I2F R11, R10 ; /* 0x0000000a000b7306 */
/* 0x001e240000201400 */
/*0750*/ FFMA R11, R26, R25, R11 ; /* 0x000000191a0b7223 */
/* 0x001fcc000000000b */
/*0760*/ F2I.TRUNC.NTZ R11, R11 ; /* 0x0000000b000b7305 */
/* 0x000e30000020f100 */
/*0770*/ I2F R8, R11 ; /* 0x0000000b00087306 */
/* 0x001e240000201400 */
/*0780*/ FFMA R8, R27, R28, R8 ; /* 0x0000001c1b087223 */
/* 0x001fcc0000000008 */
/*0790*/ F2I.TRUNC.NTZ R8, R8 ; /* 0x0000000800087305 */
/* 0x000e30000020f100 */
/*07a0*/ I2F R7, R8 ; /* 0x0000000800077306 */
/* 0x001ea40000201400 */
/*07b0*/ FFMA R7, R23, R24, R7 ; /* 0x0000001817077223 */
/* 0x004fcc0000000007 */
/*07c0*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e30000020f100 */
/*07d0*/ I2F R9, R7 ; /* 0x0000000700097306 */
/* 0x001e220000201400 */
/*07e0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fe20007ffe0ff */
/*07f0*/ FFMA R9, R29, R16, R9 ; /* 0x000000101d097223 */
/* 0x001fcc0000000009 */
/*0800*/ F2I.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e22000020f100 */
/*0810*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*0820*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0830*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc60007ffe0ff */
/*0840*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe400087fe43f */
/*0850*/ I2F R12, R9 ; /* 0x00000009000c7306 */
/* 0x0010620000201400 */
/*0860*/ IMAD.WIDE R18, R0, 0x4, R18 ; /* 0x0000000400127825 */
/* 0x000fca00078e0212 */
/*0870*/ @P1 BRA 0x1f0 ; /* 0xfffff97000001947 */
/* 0x000fea000383ffff */
/*0880*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0890*/ @!P1 BRA 0xc20 ; /* 0x0000038000009947 */
/* 0x000fea0003800000 */
/*08a0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*08b0*/ LDG.E R7, [R18.64] ; /* 0x0000000412077981 */
/* 0x0004e2000c1e1900 */
/*08c0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x001fca0008000f00 */
/*08d0*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fca00078e0208 */
/*08e0*/ LDG.E R13, [R8.64] ; /* 0x00000004080d7981 */
/* 0x000ee2000c1e1900 */
/*08f0*/ IMAD.WIDE R28, R0, 0x4, R18 ; /* 0x00000004001c7825 */
/* 0x000fc600078e0212 */
/*0900*/ LDG.E R20, [R8.64+0x4] ; /* 0x0000040408147981 */
/* 0x000f28000c1e1900 */
/*0910*/ LDG.E R23, [R28.64] ; /* 0x000000041c177981 */
/* 0x000122000c1e1900 */
/*0920*/ IMAD.WIDE R10, R0, 0x4, R28 ; /* 0x00000004000a7825 */
/* 0x000fc600078e021c */
/*0930*/ LDG.E R21, [R8.64+0x8] ; /* 0x0000080408157981 */
/* 0x000f68000c1e1900 */
/*0940*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000362000c1e1900 */
/*0950*/ IMAD.WIDE R14, R0, 0x4, R10 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020a */
/*0960*/ LDG.E R25, [R8.64+0xc] ; /* 0x00000c0408197981 */
/* 0x000f28000c1e1900 */
/*0970*/ LDG.E R24, [R14.64] ; /* 0x000000040e187981 */
/* 0x000122000c1e1900 */
/*0980*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*0990*/ LDG.E R27, [R8.64+0x10] ; /* 0x00001004081b7981 */
/* 0x000328000c1e1900 */
/*09a0*/ LDG.E R26, [R16.64] ; /* 0x00000004101a7981 */
/* 0x000322000c1e1900 */
/*09b0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x004fc600078e0210 */
/*09c0*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x0010a8000c1e1900 */
/*09d0*/ LDG.E R28, [R18.64] ; /* 0x00000004121c7981 */
/* 0x0000a2000c1e1900 */
/*09e0*/ IMAD.WIDE R10, R0, 0x4, R18 ; /* 0x00000004000a7825 */
/* 0x002fc600078e0212 */
/*09f0*/ LDG.E R17, [R8.64+0x18] ; /* 0x0000180408117981 */
/* 0x0002a8000c1e1900 */
/*0a00*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0000a2000c1e1900 */
/*0a10*/ IMAD.WIDE R14, R0, 0x4, R10 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020a */
/*0a20*/ LDG.E R11, [R8.64+0x1c] ; /* 0x00001c04080b7981 */
/* 0x0012a8000c1e1900 */
/*0a30*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x000ea2000c1e1900 */
/*0a40*/ FFMA R7, R7, R13, R12 ; /* 0x0000000d07077223 */
/* 0x008fcc000000000c */
/*0a50*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e30000020f100 */
/*0a60*/ I2F R12, R7 ; /* 0x00000007000c7306 */
/* 0x001f240000201400 */
/*0a70*/ FFMA R12, R23, R20, R12 ; /* 0x00000014170c7223 */
/* 0x010fcc000000000c */
/*0a80*/ F2I.TRUNC.NTZ R12, R12 ; /* 0x0000000c000c7305 */
/* 0x000e30000020f100 */
/*0a90*/ I2F R13, R12 ; /* 0x0000000c000d7306 */
/* 0x001f640000201400 */
/*0aa0*/ FFMA R13, R22, R21, R13 ; /* 0x00000015160d7223 */
/* 0x020fcc000000000d */
/*0ab0*/ F2I.TRUNC.NTZ R13, R13 ; /* 0x0000000d000d7305 */
/* 0x000e30000020f100 */
/*0ac0*/ I2F R18, R13 ; /* 0x0000000d00127306 */
/* 0x001e240000201400 */
/*0ad0*/ FFMA R18, R24, R25, R18 ; /* 0x0000001918127223 */
/* 0x001fcc0000000012 */
/*0ae0*/ F2I.TRUNC.NTZ R18, R18 ; /* 0x0000001200127305 */
/* 0x000e70000020f100 */
/*0af0*/ I2F R8, R18 ; /* 0x0000001200087306 */
/* 0x002e240000201400 */
/*0b00*/ FFMA R8, R26, R27, R8 ; /* 0x0000001b1a087223 */
/* 0x001fcc0000000008 */
/*0b10*/ F2I.TRUNC.NTZ R8, R8 ; /* 0x0000000800087305 */
/* 0x000e30000020f100 */
/*0b20*/ I2F R7, R8 ; /* 0x0000000800077306 */
/* 0x001ea40000201400 */
/*0b30*/ FFMA R7, R28, R29, R7 ; /* 0x0000001d1c077223 */
/* 0x004fcc0000000007 */
/*0b40*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e30000020f100 */
/*0b50*/ I2F R9, R7 ; /* 0x0000000700097306 */
/* 0x001e240000201400 */
/*0b60*/ FFMA R9, R16, R17, R9 ; /* 0x0000001110097223 */
/* 0x001fcc0000000009 */
/*0b70*/ F2I.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e30000020f100 */
/*0b80*/ I2F R12, R9 ; /* 0x00000009000c7306 */
/* 0x001e240000201400 */
/*0b90*/ FFMA R10, R10, R11, R12 ; /* 0x0000000b0a0a7223 */
/* 0x001fcc000000000c */
/*0ba0*/ F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a7305 */
/* 0x000e22000020f100 */
/*0bb0*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0bc0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0bd0*/ IMAD.WIDE R18, R0, 0x4, R14 ; /* 0x0000000400127825 */
/* 0x000fe200078e020e */
/*0be0*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fc80007ffe0ff */
/*0bf0*/ I2F R12, R10 ; /* 0x0000000a000c7306 */
/* 0x0010620000201400 */
/*0c00*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0c10*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fcc00087fe43f */
/*0c20*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0c30*/ @!P0 BRA 0xe50 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*0c40*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0c50*/ LDG.E R7, [R18.64] ; /* 0x0000000412077981 */
/* 0x0004e2000c1e1900 */
/*0c60*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x001fca0008000f00 */
/*0c70*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fca00078e0208 */
/*0c80*/ LDG.E R13, [R8.64] ; /* 0x00000004080d7981 */
/* 0x000ee2000c1e1900 */
/*0c90*/ IMAD.WIDE R16, R0, 0x4, R18 ; /* 0x0000000400107825 */
/* 0x000fc600078e0212 */
/*0ca0*/ LDG.E R20, [R8.64+0x4] ; /* 0x0000040408147981 */
/* 0x000f28000c1e1900 */
/*0cb0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x000f22000c1e1900 */
/*0cc0*/ IMAD.WIDE R14, R0, 0x4, R16 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0210 */
/*0cd0*/ LDG.E R22, [R8.64+0x8] ; /* 0x0000080408167981 */
/* 0x000f68000c1e1900 */
/*0ce0*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000f62000c1e1900 */
/*0cf0*/ IMAD.WIDE R10, R0, 0x4, R14 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020e */
/*0d00*/ LDG.E R24, [R8.64+0xc] ; /* 0x00000c0408187981 */
/* 0x000f28000c1e1900 */
/*0d10*/ LDG.E R25, [R10.64] ; /* 0x000000040a197981 */
/* 0x000f22000c1e1900 */
/*0d20*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0d30*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0d40*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0d50*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc60007ffe0ff */
/*0d60*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0d70*/ IMAD.WIDE R18, R0, 0x4, R10 ; /* 0x0000000400127825 */
/* 0x004fc800078e020a */
/*0d80*/ FFMA R7, R7, R13, R12 ; /* 0x0000000d07077223 */
/* 0x00afcc000000000c */
/*0d90*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e30000020f100 */
/*0da0*/ I2F R12, R7 ; /* 0x00000007000c7306 */
/* 0x001f240000201400 */
/*0db0*/ FFMA R20, R21, R20, R12 ; /* 0x0000001415147223 */
/* 0x010fcc000000000c */
/*0dc0*/ F2I.TRUNC.NTZ R20, R20 ; /* 0x0000001400147305 */
/* 0x000e30000020f100 */
/*0dd0*/ I2F R12, R20 ; /* 0x00000014000c7306 */
/* 0x001f640000201400 */
/*0de0*/ FFMA R22, R23, R22, R12 ; /* 0x0000001617167223 */
/* 0x020fcc000000000c */
/*0df0*/ F2I.TRUNC.NTZ R22, R22 ; /* 0x0000001600167305 */
/* 0x000e30000020f100 */
/*0e00*/ I2F R12, R22 ; /* 0x00000016000c7306 */
/* 0x001e240000201400 */
/*0e10*/ FFMA R24, R25, R24, R12 ; /* 0x0000001819187223 */
/* 0x001fcc000000000c */
/*0e20*/ F2I.TRUNC.NTZ R24, R24 ; /* 0x0000001800187305 */
/* 0x000e30000020f100 */
/*0e30*/ I2F R12, R24 ; /* 0x00000018000c7306 */
/* 0x0010640000201400 */
/*0e40*/ @P0 BRA 0xc40 ; /* 0xfffffdf000000947 */
/* 0x003fea000383ffff */
/*0e50*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0e60*/ @!P0 BRA 0xf90 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0e70*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0e80*/ IADD3 R6, R4, R3, RZ ; /* 0x0000000304067210 */
/* 0x000fe20007ffe0ff */
/*0e90*/ IMAD R3, R3, c[0x0][0x160], R2 ; /* 0x0000580003037a24 */
/* 0x000fd000078e0202 */
/*0ea0*/ IMAD.WIDE R6, R6, R8, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0208 */
/*0eb0*/ IMAD.WIDE R8, R3, R8, c[0x0][0x170] ; /* 0x00005c0003087625 */
/* 0x001fe200078e0208 */
/*0ec0*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fc80000000f00 */
/*0ed0*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fe20000000f00 */
/*0ee0*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0010aa000c1e1900 */
/*0ef0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0006a2000c1e1900 */
/*0f00*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0f10*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc40007f3e0ff */
/*0f20*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0f30*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0f40*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x008fc60000ffe4ff */
/*0f50*/ FFMA R3, R3, R6, R12 ; /* 0x0000000603037223 */
/* 0x006fcc000000000c */
/*0f60*/ F2I.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e30000020f100 */
/*0f70*/ I2F R12, R3 ; /* 0x00000003000c7306 */
/* 0x0010620000201400 */
/*0f80*/ @P0 BRA 0xed0 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*0f90*/ IADD3 R2, R2, R4, RZ ; /* 0x0000000402027210 */
/* 0x000fe40007ffe0ff */
/*0fa0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x001fca0000000f00 */
/*0fb0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x178] ; /* 0x00005e0002027625 */
/* 0x000fca00078e0203 */
/*0fc0*/ STG.E [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x002fe2000c101904 */
/*0fd0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0fe0*/ BRA 0xfe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <math.h>
#include <curand.h>
#include <curand_kernel.h>
// Kernel function to perform C = A*B
__global__
void mat_mult(int n, float *A, float *B, float *C)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
int sum = 0;
for (int k = 0; k < n; k++){
sum += A[idy*n + k]*B[k*n + idx];
}
C[idy*n +idx] = sum;
}
int main(void)
{
//N is the size of the matrix
int N = 1<<8;
//block_size is the width and height of cuda block
//total threads per block = block_size*block_size
int block_size = 1<<5;
//grid_size is the width and height of a cuda grid
//total blocks per grid = grid_size*grid_size
int grid_size = N/block_size;
// Allocate Unified Memory – accessible from CPU or GPU
float *A, *B, *C;
cudaMallocManaged(&A, N*N*sizeof(float));
cudaMallocManaged(&B, N*N*sizeof(float));
cudaMallocManaged(&C, N*N*sizeof(float));
// initialize A and B arrays on the host
for (int i = 0; i < N; i++) {
for ( int j = 0; j < N; j++){
if(i == j){
A[i*N +j] = i;
B[i*N +j] = i;
} else {
A[i*N +j] = 0;
B[i*N +j] = 0;
}
}
}
// Run kernel with 2-D grid and 2-D blocks.
dim3 block_dim(block_size, block_size);
dim3 grid_dim(grid_size, grid_size);
mat_mult<<<grid_dim, block_dim>>>(N, A, B, C);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
// Check for errors (diagonal should be squares)
int failure = 0;
for (int i = 0; i < N; i++){
for (int j = 0; j < N; j++){
if(i == j && C[i*N + j] != (float)i*i){
failure = 1;
} else if (i !=j && C[i*N + j] != 0.0){
failure = 1;
}
}
}
//Helpful for printing out a matrix/debugging :^)
/*for (int i = 0; i < N; i++){
for (int j = 0; j < N; j++){
printf("%f,",A[i*N +j]);
}
printf("\n");
}*/
if(failure){
printf("There was a failure, big sad!\n");
} else {
printf("Tests Pass!\n");
}
// Free memory
cudaFree(A);
cudaFree(B);
cudaFree(C);
return 0;
} | .file "tmpxft_0004d034_00000000-6_mult_mat.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2274:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2274:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z8mat_multiPfS_S_iPfS_S_
.type _Z32__device_stub__Z8mat_multiPfS_S_iPfS_S_, @function
_Z32__device_stub__Z8mat_multiPfS_S_iPfS_S_:
.LFB2296:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8mat_multiPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2296:
.size _Z32__device_stub__Z8mat_multiPfS_S_iPfS_S_, .-_Z32__device_stub__Z8mat_multiPfS_S_iPfS_S_
.globl _Z8mat_multiPfS_S_
.type _Z8mat_multiPfS_S_, @function
_Z8mat_multiPfS_S_:
.LFB2297:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8mat_multiPfS_S_iPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2297:
.size _Z8mat_multiPfS_S_, .-_Z8mat_multiPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "There was a failure, big sad!\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Tests Pass!\n"
.text
.globl main
.type main, @function
main:
.LFB2271:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $262144, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $262144, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $262144, %esi
call cudaMallocManaged@PLT
movl $0, %r8d
movl $256, %edi
movl $0, %esi
jmp .L12
.L34:
movslq %eax, %rdx
pxor %xmm0, %xmm0
cvtsi2ssl %esi, %xmm0
movq 8(%rsp), %rcx
movss %xmm0, (%rcx,%rdx,4)
movq 16(%rsp), %rcx
movss %xmm0, (%rcx,%rdx,4)
.L14:
addl $1, %eax
cmpl %edi, %eax
je .L33
.L15:
leal (%rax,%r8), %edx
cmpl %edx, %esi
je .L34
movslq %eax, %rdx
movq 8(%rsp), %rcx
movl $0x00000000, (%rcx,%rdx,4)
movq 16(%rsp), %rcx
movl $0x00000000, (%rcx,%rdx,4)
jmp .L14
.L33:
addl $1, %esi
addl $256, %edi
subl $256, %r8d
cmpl $256, %esi
je .L16
.L12:
movl %esi, %eax
sall $8, %eax
jmp .L15
.L16:
movl $32, 32(%rsp)
movl $32, 36(%rsp)
movl $1, 40(%rsp)
movl $8, 44(%rsp)
movl $8, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L17:
call cudaDeviceSynchronize@PLT
movq 24(%rsp), %rcx
movl $0, %r8d
movl $256, %edi
movl $0, %esi
movl $0, %r9d
pxor %xmm1, %xmm1
movl $1, %r10d
jmp .L18
.L35:
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movl $256, %edi
call _Z32__device_stub__Z8mat_multiPfS_S_iPfS_S_
jmp .L17
.L37:
pxor %xmm0, %xmm0
cvtsi2ssl %esi, %xmm0
movslq %eax, %rdx
mulss %xmm0, %xmm0
ucomiss (%rcx,%rdx,4), %xmm0
jp .L29
je .L20
.L29:
movl %r10d, %r9d
jmp .L20
.L28:
movl %r10d, %r9d
.L20:
addl $1, %eax
cmpl %edi, %eax
je .L36
.L23:
leal (%rax,%r8), %edx
cmpl %edx, %esi
je .L37
movslq %eax, %rdx
ucomiss (%rcx,%rdx,4), %xmm1
jp .L28
je .L20
jmp .L28
.L36:
addl $1, %esi
addl $256, %edi
subl $256, %r8d
cmpl $256, %esi
je .L24
.L18:
movl %esi, %eax
sall $8, %eax
jmp .L23
.L24:
testl %r9d, %r9d
je .L25
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L26:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L38
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L26
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z8mat_multiPfS_S_"
.LC4:
.string "precalc_xorwow_matrix"
.LC5:
.string "precalc_xorwow_offset_matrix"
.LC6:
.string "mrg32k3aM1"
.LC7:
.string "mrg32k3aM2"
.LC8:
.string "mrg32k3aM1SubSeq"
.LC9:
.string "mrg32k3aM2SubSeq"
.LC10:
.string "mrg32k3aM1Seq"
.LC11:
.string "mrg32k3aM2Seq"
.LC12:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2299:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z8mat_multiPfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2299:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <math.h>
#include <curand.h>
#include <curand_kernel.h>
// Kernel function to perform C = A*B
__global__
void mat_mult(int n, float *A, float *B, float *C)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
int sum = 0;
for (int k = 0; k < n; k++){
sum += A[idy*n + k]*B[k*n + idx];
}
C[idy*n +idx] = sum;
}
int main(void)
{
//N is the size of the matrix
int N = 1<<8;
//block_size is the width and height of cuda block
//total threads per block = block_size*block_size
int block_size = 1<<5;
//grid_size is the width and height of a cuda grid
//total blocks per grid = grid_size*grid_size
int grid_size = N/block_size;
// Allocate Unified Memory – accessible from CPU or GPU
float *A, *B, *C;
cudaMallocManaged(&A, N*N*sizeof(float));
cudaMallocManaged(&B, N*N*sizeof(float));
cudaMallocManaged(&C, N*N*sizeof(float));
// initialize A and B arrays on the host
for (int i = 0; i < N; i++) {
for ( int j = 0; j < N; j++){
if(i == j){
A[i*N +j] = i;
B[i*N +j] = i;
} else {
A[i*N +j] = 0;
B[i*N +j] = 0;
}
}
}
// Run kernel with 2-D grid and 2-D blocks.
dim3 block_dim(block_size, block_size);
dim3 grid_dim(grid_size, grid_size);
mat_mult<<<grid_dim, block_dim>>>(N, A, B, C);
// Wait for GPU to finish before accessing on host
cudaDeviceSynchronize();
// Check for errors (diagonal should be squares)
int failure = 0;
for (int i = 0; i < N; i++){
for (int j = 0; j < N; j++){
if(i == j && C[i*N + j] != (float)i*i){
failure = 1;
} else if (i !=j && C[i*N + j] != 0.0){
failure = 1;
}
}
}
//Helpful for printing out a matrix/debugging :^)
/*for (int i = 0; i < N; i++){
for (int j = 0; j < N; j++){
printf("%f,",A[i*N +j]);
}
printf("\n");
}*/
if(failure){
printf("There was a failure, big sad!\n");
} else {
printf("Tests Pass!\n");
}
// Free memory
cudaFree(A);
cudaFree(B);
cudaFree(C);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
// Kernel function to perform C = A*B
__global__
void mat_mult(int n, float *A, float *B, float *C)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
int sum = 0;
for (int k = 0; k < n; k++){
sum += A[idy*n + k]*B[k*n + idx];
}
C[idy*n +idx] = sum;
}
int main(void)
{
//N is the size of the matrix
int N = 1<<8;
//block_size is the width and height of cuda block
//total threads per block = block_size*block_size
int block_size = 1<<5;
//grid_size is the width and height of a cuda grid
//total blocks per grid = grid_size*grid_size
int grid_size = N/block_size;
// Allocate Unified Memory – accessible from CPU or GPU
float *A, *B, *C;
hipMallocManaged(&A, N*N*sizeof(float));
hipMallocManaged(&B, N*N*sizeof(float));
hipMallocManaged(&C, N*N*sizeof(float));
// initialize A and B arrays on the host
for (int i = 0; i < N; i++) {
for ( int j = 0; j < N; j++){
if(i == j){
A[i*N +j] = i;
B[i*N +j] = i;
} else {
A[i*N +j] = 0;
B[i*N +j] = 0;
}
}
}
// Run kernel with 2-D grid and 2-D blocks.
dim3 block_dim(block_size, block_size);
dim3 grid_dim(grid_size, grid_size);
mat_mult<<<grid_dim, block_dim>>>(N, A, B, C);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
// Check for errors (diagonal should be squares)
int failure = 0;
for (int i = 0; i < N; i++){
for (int j = 0; j < N; j++){
if(i == j && C[i*N + j] != (float)i*i){
failure = 1;
} else if (i !=j && C[i*N + j] != 0.0){
failure = 1;
}
}
}
//Helpful for printing out a matrix/debugging :^)
/*for (int i = 0; i < N; i++){
for (int j = 0; j < N; j++){
printf("%f,",A[i*N +j]);
}
printf("\n");
}*/
if(failure){
printf("There was a failure, big sad!\n");
} else {
printf("Tests Pass!\n");
}
// Free memory
hipFree(A);
hipFree(B);
hipFree(C);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
// Kernel function to perform C = A*B
__global__
void mat_mult(int n, float *A, float *B, float *C)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
int sum = 0;
for (int k = 0; k < n; k++){
sum += A[idy*n + k]*B[k*n + idx];
}
C[idy*n +idx] = sum;
}
int main(void)
{
//N is the size of the matrix
int N = 1<<8;
//block_size is the width and height of cuda block
//total threads per block = block_size*block_size
int block_size = 1<<5;
//grid_size is the width and height of a cuda grid
//total blocks per grid = grid_size*grid_size
int grid_size = N/block_size;
// Allocate Unified Memory – accessible from CPU or GPU
float *A, *B, *C;
hipMallocManaged(&A, N*N*sizeof(float));
hipMallocManaged(&B, N*N*sizeof(float));
hipMallocManaged(&C, N*N*sizeof(float));
// initialize A and B arrays on the host
for (int i = 0; i < N; i++) {
for ( int j = 0; j < N; j++){
if(i == j){
A[i*N +j] = i;
B[i*N +j] = i;
} else {
A[i*N +j] = 0;
B[i*N +j] = 0;
}
}
}
// Run kernel with 2-D grid and 2-D blocks.
dim3 block_dim(block_size, block_size);
dim3 grid_dim(grid_size, grid_size);
mat_mult<<<grid_dim, block_dim>>>(N, A, B, C);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
// Check for errors (diagonal should be squares)
int failure = 0;
for (int i = 0; i < N; i++){
for (int j = 0; j < N; j++){
if(i == j && C[i*N + j] != (float)i*i){
failure = 1;
} else if (i !=j && C[i*N + j] != 0.0){
failure = 1;
}
}
}
//Helpful for printing out a matrix/debugging :^)
/*for (int i = 0; i < N; i++){
for (int j = 0; j < N; j++){
printf("%f,",A[i*N +j]);
}
printf("\n");
}*/
if(failure){
printf("There was a failure, big sad!\n");
} else {
printf("Tests Pass!\n");
}
// Free memory
hipFree(A);
hipFree(B);
hipFree(C);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8mat_multiPfS_S_
.globl _Z8mat_multiPfS_S_
.p2align 8
.type _Z8mat_multiPfS_S_,@function
_Z8mat_multiPfS_S_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cvt_f32_i32_e32 v6, v6
s_add_i32 s3, s3, -1
s_cmp_eq_u32 s3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v6, v6
s_cbranch_scc0 .LBB0_2
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_i32_e32 v2, v6
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v1, s2, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8mat_multiPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8mat_multiPfS_S_, .Lfunc_end0-_Z8mat_multiPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8mat_multiPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8mat_multiPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
// Kernel function to perform C = A*B
__global__
void mat_mult(int n, float *A, float *B, float *C)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
int sum = 0;
for (int k = 0; k < n; k++){
sum += A[idy*n + k]*B[k*n + idx];
}
C[idy*n +idx] = sum;
}
int main(void)
{
//N is the size of the matrix
int N = 1<<8;
//block_size is the width and height of cuda block
//total threads per block = block_size*block_size
int block_size = 1<<5;
//grid_size is the width and height of a cuda grid
//total blocks per grid = grid_size*grid_size
int grid_size = N/block_size;
// Allocate Unified Memory – accessible from CPU or GPU
float *A, *B, *C;
hipMallocManaged(&A, N*N*sizeof(float));
hipMallocManaged(&B, N*N*sizeof(float));
hipMallocManaged(&C, N*N*sizeof(float));
// initialize A and B arrays on the host
for (int i = 0; i < N; i++) {
for ( int j = 0; j < N; j++){
if(i == j){
A[i*N +j] = i;
B[i*N +j] = i;
} else {
A[i*N +j] = 0;
B[i*N +j] = 0;
}
}
}
// Run kernel with 2-D grid and 2-D blocks.
dim3 block_dim(block_size, block_size);
dim3 grid_dim(grid_size, grid_size);
mat_mult<<<grid_dim, block_dim>>>(N, A, B, C);
// Wait for GPU to finish before accessing on host
hipDeviceSynchronize();
// Check for errors (diagonal should be squares)
int failure = 0;
for (int i = 0; i < N; i++){
for (int j = 0; j < N; j++){
if(i == j && C[i*N + j] != (float)i*i){
failure = 1;
} else if (i !=j && C[i*N + j] != 0.0){
failure = 1;
}
}
}
//Helpful for printing out a matrix/debugging :^)
/*for (int i = 0; i < N; i++){
for (int j = 0; j < N; j++){
printf("%f,",A[i*N +j]);
}
printf("\n");
}*/
if(failure){
printf("There was a failure, big sad!\n");
} else {
printf("Tests Pass!\n");
}
// Free memory
hipFree(A);
hipFree(B);
hipFree(C);
return 0;
} | .text
.file "mult_mat.hip"
.globl _Z23__device_stub__mat_multiPfS_S_ # -- Begin function _Z23__device_stub__mat_multiPfS_S_
.p2align 4, 0x90
.type _Z23__device_stub__mat_multiPfS_S_,@function
_Z23__device_stub__mat_multiPfS_S_: # @_Z23__device_stub__mat_multiPfS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8mat_multiPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__mat_multiPfS_S_, .Lfunc_end0-_Z23__device_stub__mat_multiPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $152, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 24(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
movl $1, %edx
callq hipMallocManaged
xorl %eax, %eax
xorl %ecx, %ecx
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_1 Depth=1
incq %rcx
addq $1024, %rax # imm = 0x400
cmpq $256, %rcx # imm = 0x100
je .LBB1_6
.LBB1_1: # %.preheader70
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movq 24(%rsp), %rdx
addq %rax, %rdx
movq 16(%rsp), %rsi
addq %rax, %rsi
xorl %edi, %edi
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_4: # in Loop: Header=BB1_2 Depth=2
movss %xmm1, (%rdx,%rdi,4)
movss %xmm1, (%rsi,%rdi,4)
incq %rdi
cmpq $256, %rdi # imm = 0x100
je .LBB1_5
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movaps %xmm0, %xmm1
cmpq %rdi, %rcx
je .LBB1_4
# %bb.3: # in Loop: Header=BB1_2 Depth=2
xorps %xmm1, %xmm1
jmp .LBB1_4
.LBB1_6:
xorl %ebx, %ebx
movabsq $34359738376, %rdi # imm = 0x800000008
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %ebp
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl $256, 36(%rsp) # imm = 0x100
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 104(%rsp), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z8mat_multiPfS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
callq hipDeviceSynchronize
movq 8(%rsp), %rax
xorps %xmm0, %xmm0
xorl %ecx, %ecx
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_12: # in Loop: Header=BB1_9 Depth=1
incq %rcx
addq $1024, %rax # imm = 0x400
cmpq $256, %rcx # imm = 0x100
je .LBB1_13
.LBB1_9: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_10 Depth 2
xorps %xmm1, %xmm1
cvtsi2ss %ecx, %xmm1
mulss %xmm1, %xmm1
xorl %edx, %edx
jmp .LBB1_10
.p2align 4, 0x90
.LBB1_11: # in Loop: Header=BB1_10 Depth=2
ucomiss (%rax,%rdx,4), %xmm1
cmovnel %ebp, %ebx
cmovpl %ebp, %ebx
.LBB1_16: # in Loop: Header=BB1_10 Depth=2
incq %rdx
cmpq $256, %rdx # imm = 0x100
je .LBB1_12
.LBB1_10: # Parent Loop BB1_9 Depth=1
# => This Inner Loop Header: Depth=2
cmpq %rdx, %rcx
je .LBB1_11
# %bb.14: # %.critedge
# in Loop: Header=BB1_10 Depth=2
movss (%rax,%rdx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm2
jne .LBB1_15
jnp .LBB1_16
.LBB1_15: # in Loop: Header=BB1_10 Depth=2
movl $1, %ebx
jmp .LBB1_16
.LBB1_13:
testl %ebx, %ebx
movl $.Lstr, %eax
movl $.Lstr.1, %edi
cmoveq %rax, %rdi
callq puts@PLT
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8mat_multiPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8mat_multiPfS_S_,@object # @_Z8mat_multiPfS_S_
.section .rodata,"a",@progbits
.globl _Z8mat_multiPfS_S_
.p2align 3, 0x0
_Z8mat_multiPfS_S_:
.quad _Z23__device_stub__mat_multiPfS_S_
.size _Z8mat_multiPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8mat_multiPfS_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Tests Pass!"
.size .Lstr, 12
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "There was a failure, big sad!"
.size .Lstr.1, 30
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__mat_multiPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8mat_multiPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8mat_multiPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002600 */
/*0020*/ MOV R0, c[0x0][0x160] ; /* 0x0000580000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R12, -RZ, RZ, 0, 0 ; /* 0x00000000ff0c7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002200 */
/*0060*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc60003f06270 */
/*0070*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0080*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R4, R4, c[0x0][0x4], R5 ; /* 0x0000010004047a24 */
/* 0x001fc800078e0205 */
/*00a0*/ IMAD R4, R4, c[0x0][0x160], RZ ; /* 0x0000580004047a24 */
/* 0x000fe400078e02ff */
/*00b0*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x002fe200078e0203 */
/*00c0*/ @!P0 BRA 0xf90 ; /* 0x00000ec000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R3, R0.reuse, -0x1, RZ ; /* 0xffffffff00037810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ LOP3.LUT R5, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300057812 */
/* 0x000fe400078ec0ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*0100*/ MOV R12, RZ ; /* 0x000000ff000c7202 */
/* 0x000fe40000000f00 */
/*0110*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fd20000000f00 */
/*0120*/ @!P0 BRA 0xe50 ; /* 0x00000d2000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R6, -R5, c[0x0][0x160], RZ ; /* 0x0000580005067a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ HFMA2.MMA R19, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff137435 */
/* 0x000fe200000001ff */
/*0150*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0160*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0170*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f04270 */
/*0180*/ MOV R12, RZ ; /* 0x000000ff000c7202 */
/* 0x000fca0000000f00 */
/*0190*/ IMAD.WIDE R18, R2, R19, c[0x0][0x170] ; /* 0x00005c0002127625 */
/* 0x000fcc00078e0213 */
/*01a0*/ @!P0 BRA 0xc40 ; /* 0x00000a9000008947 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x880 ; /* 0x000006a000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ MOV R14, UR6 ; /* 0x00000006000e7c02 */
/* 0x000fe20008000f00 */
/*0200*/ LDG.E R13, [R18.64] ; /* 0x00000004120d7981 */
/* 0x0010a2000c1e1900 */
/*0210*/ MOV R15, UR7 ; /* 0x00000007000f7c02 */
/* 0x000fca0008000f00 */
/*0220*/ IMAD.WIDE R14, R4, 0x4, R14 ; /* 0x00000004040e7825 */
/* 0x000fca00078e020e */
/*0230*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IMAD.WIDE R10, R0, 0x4, R18 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0212 */
/*0250*/ LDG.E R9, [R14.64+0x4] ; /* 0x000004040e097981 */
/* 0x000ee8000c1e1900 */
/*0260*/ LDG.E R8, [R10.64] ; /* 0x000000040a087981 */
/* 0x0022e2000c1e1900 */
/*0270*/ IMAD.WIDE R28, R0, 0x4, R10 ; /* 0x00000004001c7825 */
/* 0x000fc600078e020a */
/*0280*/ LDG.E R7, [R14.64+0x8] ; /* 0x000008040e077981 */
/* 0x000f28000c1e1900 */
/*0290*/ LDG.E R22, [R28.64] ; /* 0x000000041c167981 */
/* 0x000b22000c1e1900 */
/*02a0*/ IMAD.WIDE R20, R0, 0x4, R28 ; /* 0x0000000400147825 */
/* 0x000fc600078e021c */
/*02b0*/ LDG.E R16, [R14.64+0xc] ; /* 0x00000c040e107981 */
/* 0x000ee8000c1e1900 */
/*02c0*/ LDG.E R17, [R20.64] ; /* 0x0000000414117981 */
/* 0x0002e8000c1e1900 */
/*02d0*/ LDG.E R19, [R14.64+0x10] ; /* 0x000010040e137981 */
/* 0x001ee8000c1e1900 */
/*02e0*/ LDG.E R26, [R14.64+0x14] ; /* 0x000014040e1a7981 */
/* 0x000ee2000c1e1900 */
/*02f0*/ IMAD.WIDE R20, R0, 0x4, R20 ; /* 0x0000000400147825 */
/* 0x002fc600078e0214 */
/*0300*/ LDG.E R28, [R14.64+0x18] ; /* 0x000018040e1c7981 */
/* 0x020f68000c1e1900 */
/*0310*/ LDG.E R18, [R20.64] ; /* 0x0000000414127981 */
/* 0x000122000c1e1900 */
/*0320*/ IMAD.WIDE R10, R0, 0x4, R20 ; /* 0x00000004000a7825 */
/* 0x000fca00078e0214 */
/*0330*/ LDG.E R25, [R10.64] ; /* 0x000000040a197981 */
/* 0x000324000c1e1900 */
/*0340*/ IMAD.WIDE R10, R0, 0x4, R10 ; /* 0x00000004000a7825 */
/* 0x002fca00078e020a */
/*0350*/ LDG.E R27, [R10.64] ; /* 0x000000040a1b7981 */
/* 0x000362000c1e1900 */
/*0360*/ IMAD.WIDE R20, R0, 0x4, R10 ; /* 0x0000000400147825 */
/* 0x001fca00078e020a */
/*0370*/ LDG.E R24, [R20.64] ; /* 0x0000000414187981 */
/* 0x000122000c1e1900 */
/*0380*/ FFMA R29, R13, R23, R12 ; /* 0x000000170d1d7223 */
/* 0x004fc6000000000c */
/*0390*/ LDG.E R23, [R14.64+0x1c] ; /* 0x00001c040e177981 */
/* 0x000ea6000c1e1900 */
/*03a0*/ F2I.TRUNC.NTZ R29, R29 ; /* 0x0000001d001d7305 */
/* 0x000e22000020f100 */
/*03b0*/ IMAD.WIDE R12, R0, 0x4, R20 ; /* 0x00000004000c7825 */
/* 0x000fce00078e0214 */
/*03c0*/ I2F R29, R29 ; /* 0x0000001d001d7306 */
/* 0x001ee40000201400 */
/*03d0*/ FFMA R29, R8, R9, R29 ; /* 0x00000009081d7223 */
/* 0x008fe4000000001d */
/*03e0*/ LDG.E R8, [R14.64+0x20] ; /* 0x000020040e087981 */
/* 0x000ee8000c1e1900 */
/*03f0*/ LDG.E R9, [R12.64] ; /* 0x000000040c097981 */
/* 0x0000e2000c1e1900 */
/*0400*/ F2I.TRUNC.NTZ R10, R29 ; /* 0x0000001d000a7305 */
/* 0x002e70000020f100 */
/*0410*/ I2F R20, R10 ; /* 0x0000000a00147306 */
/* 0x0023240000201400 */
/*0420*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x002fc400078e020c */
/*0430*/ LDG.E R13, [R14.64+0x28] ; /* 0x000028040e0d7981 */
/* 0x001ee4000c1e1900 */
/*0440*/ FFMA R20, R22, R7, R20 ; /* 0x0000000716147223 */
/* 0x010fe40000000014 */
/*0450*/ LDG.E R7, [R14.64+0x24] ; /* 0x000024040e077981 */
/* 0x000f28000c1e1900 */
/*0460*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000122000c1e1900 */
/*0470*/ F2I.TRUNC.NTZ R20, R20 ; /* 0x0000001400147305 */
/* 0x000e70000020f100 */
/*0480*/ I2F R12, R20 ; /* 0x00000014000c7306 */
/* 0x0023640000201400 */
/*0490*/ IMAD.WIDE R20, R0, 0x4, R10 ; /* 0x0000000400147825 */
/* 0x002fc400078e020a */
/*04a0*/ LDG.E R11, [R14.64+0x2c] ; /* 0x00002c040e0b7981 */
/* 0x001f24000c1e1900 */
/*04b0*/ FFMA R16, R17, R16, R12 ; /* 0x0000001011107223 */
/* 0x020fe4000000000c */
/*04c0*/ LDG.E R12, [R20.64] ; /* 0x00000004140c7981 */
/* 0x000164000c1e1900 */
/*04d0*/ F2I.TRUNC.NTZ R29, R16 ; /* 0x00000010001d7305 */
/* 0x000e70000020f100 */
/*04e0*/ I2F R29, R29 ; /* 0x0000001d001d7306 */
/* 0x002e620000201400 */
/*04f0*/ IMAD.WIDE R16, R0, 0x4, R20 ; /* 0x0000000400107825 */
/* 0x000fca00078e0214 */
/*0500*/ LDG.E R10, [R16.64] ; /* 0x00000004100a7981 */
/* 0x000162000c1e1900 */
/*0510*/ FFMA R18, R18, R19, R29 ; /* 0x0000001312127223 */
/* 0x002fcc000000001d */
/*0520*/ F2I.TRUNC.NTZ R18, R18 ; /* 0x0000001200127305 */
/* 0x000e30000020f100 */
/*0530*/ I2F R20, R18 ; /* 0x0000001200147306 */
/* 0x0010640000201400 */
/*0540*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x001fc800078e0210 */
/*0550*/ FFMA R29, R25, R26, R20 ; /* 0x0000001a191d7223 */
/* 0x002fe40000000014 */
/*0560*/ LDG.E R25, [R14.64+0x30] ; /* 0x000030040e197981 */
/* 0x000f68000c1e1900 */
/*0570*/ LDG.E R26, [R18.64] ; /* 0x00000004121a7981 */
/* 0x000162000c1e1900 */
/*0580*/ F2I.TRUNC.NTZ R29, R29 ; /* 0x0000001d001d7305 */
/* 0x000e62000020f100 */
/*0590*/ IMAD.WIDE R20, R0, 0x4, R18 ; /* 0x0000000400147825 */
/* 0x000fce00078e0212 */
/*05a0*/ I2F R29, R29 ; /* 0x0000001d001d7306 */
/* 0x002e640000201400 */
/*05b0*/ FFMA R17, R27, R28, R29 ; /* 0x0000001c1b117223 */
/* 0x002fe4000000001d */
/*05c0*/ LDG.E R28, [R14.64+0x34] ; /* 0x000034040e1c7981 */
/* 0x000f68000c1e1900 */
/*05d0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000562000c1e1900 */
/*05e0*/ F2I.TRUNC.NTZ R17, R17 ; /* 0x0000001100117305 */
/* 0x000e30000020f100 */
/*05f0*/ I2F R18, R17 ; /* 0x0000001100127306 */
/* 0x0010a40000201400 */
/*0600*/ IMAD.WIDE R16, R0, 0x4, R20 ; /* 0x0000000400107825 */
/* 0x001fc800078e0214 */
/*0610*/ FFMA R20, R24, R23, R18 ; /* 0x0000001718147223 */
/* 0x004fe40000000012 */
/*0620*/ LDG.E R24, [R14.64+0x38] ; /* 0x000038040e187981 */
/* 0x000ea8000c1e1900 */
/*0630*/ LDG.E R23, [R16.64] ; /* 0x0000000410177981 */
/* 0x0000a2000c1e1900 */
/*0640*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fe200078e0210 */
/*0650*/ F2I.TRUNC.NTZ R20, R20 ; /* 0x0000001400147305 */
/* 0x000e68000020f100 */
/*0660*/ LDG.E R29, [R18.64] ; /* 0x00000004121d7981 */
/* 0x000ea8000c1e1900 */
/*0670*/ LDG.E R16, [R14.64+0x3c] ; /* 0x00003c040e107981 */
/* 0x001ea2000c1e1900 */
/*0680*/ I2F R21, R20 ; /* 0x0000001400157306 */
/* 0x002ee40000201400 */
/*0690*/ FFMA R8, R9, R8, R21 ; /* 0x0000000809087223 */
/* 0x008fcc0000000015 */
/*06a0*/ F2I.TRUNC.NTZ R8, R8 ; /* 0x0000000800087305 */
/* 0x000e30000020f100 */
/*06b0*/ I2F R9, R8 ; /* 0x0000000800097306 */
/* 0x001f240000201400 */
/*06c0*/ FFMA R7, R22, R7, R9 ; /* 0x0000000716077223 */
/* 0x010fcc0000000009 */
/*06d0*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e30000020f100 */
/*06e0*/ I2F R9, R7 ; /* 0x0000000700097306 */
/* 0x001f640000201400 */
/*06f0*/ FFMA R9, R12, R13, R9 ; /* 0x0000000d0c097223 */
/* 0x020fcc0000000009 */
/*0700*/ F2I.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e30000020f100 */
/*0710*/ I2F R12, R9 ; /* 0x00000009000c7306 */
/* 0x001e240000201400 */
/*0720*/ FFMA R10, R10, R11, R12 ; /* 0x0000000b0a0a7223 */
/* 0x001fcc000000000c */
/*0730*/ F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a7305 */
/* 0x000e30000020f100 */
/*0740*/ I2F R11, R10 ; /* 0x0000000a000b7306 */
/* 0x001e240000201400 */
/*0750*/ FFMA R11, R26, R25, R11 ; /* 0x000000191a0b7223 */
/* 0x001fcc000000000b */
/*0760*/ F2I.TRUNC.NTZ R11, R11 ; /* 0x0000000b000b7305 */
/* 0x000e30000020f100 */
/*0770*/ I2F R8, R11 ; /* 0x0000000b00087306 */
/* 0x001e240000201400 */
/*0780*/ FFMA R8, R27, R28, R8 ; /* 0x0000001c1b087223 */
/* 0x001fcc0000000008 */
/*0790*/ F2I.TRUNC.NTZ R8, R8 ; /* 0x0000000800087305 */
/* 0x000e30000020f100 */
/*07a0*/ I2F R7, R8 ; /* 0x0000000800077306 */
/* 0x001ea40000201400 */
/*07b0*/ FFMA R7, R23, R24, R7 ; /* 0x0000001817077223 */
/* 0x004fcc0000000007 */
/*07c0*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e30000020f100 */
/*07d0*/ I2F R9, R7 ; /* 0x0000000700097306 */
/* 0x001e220000201400 */
/*07e0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fe20007ffe0ff */
/*07f0*/ FFMA R9, R29, R16, R9 ; /* 0x000000101d097223 */
/* 0x001fcc0000000009 */
/*0800*/ F2I.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e22000020f100 */
/*0810*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*0820*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0830*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fc60007ffe0ff */
/*0840*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe400087fe43f */
/*0850*/ I2F R12, R9 ; /* 0x00000009000c7306 */
/* 0x0010620000201400 */
/*0860*/ IMAD.WIDE R18, R0, 0x4, R18 ; /* 0x0000000400127825 */
/* 0x000fca00078e0212 */
/*0870*/ @P1 BRA 0x1f0 ; /* 0xfffff97000001947 */
/* 0x000fea000383ffff */
/*0880*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*0890*/ @!P1 BRA 0xc20 ; /* 0x0000038000009947 */
/* 0x000fea0003800000 */
/*08a0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*08b0*/ LDG.E R7, [R18.64] ; /* 0x0000000412077981 */
/* 0x0004e2000c1e1900 */
/*08c0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x001fca0008000f00 */
/*08d0*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fca00078e0208 */
/*08e0*/ LDG.E R13, [R8.64] ; /* 0x00000004080d7981 */
/* 0x000ee2000c1e1900 */
/*08f0*/ IMAD.WIDE R28, R0, 0x4, R18 ; /* 0x00000004001c7825 */
/* 0x000fc600078e0212 */
/*0900*/ LDG.E R20, [R8.64+0x4] ; /* 0x0000040408147981 */
/* 0x000f28000c1e1900 */
/*0910*/ LDG.E R23, [R28.64] ; /* 0x000000041c177981 */
/* 0x000122000c1e1900 */
/*0920*/ IMAD.WIDE R10, R0, 0x4, R28 ; /* 0x00000004000a7825 */
/* 0x000fc600078e021c */
/*0930*/ LDG.E R21, [R8.64+0x8] ; /* 0x0000080408157981 */
/* 0x000f68000c1e1900 */
/*0940*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000362000c1e1900 */
/*0950*/ IMAD.WIDE R14, R0, 0x4, R10 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020a */
/*0960*/ LDG.E R25, [R8.64+0xc] ; /* 0x00000c0408197981 */
/* 0x000f28000c1e1900 */
/*0970*/ LDG.E R24, [R14.64] ; /* 0x000000040e187981 */
/* 0x000122000c1e1900 */
/*0980*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc600078e020e */
/*0990*/ LDG.E R27, [R8.64+0x10] ; /* 0x00001004081b7981 */
/* 0x000328000c1e1900 */
/*09a0*/ LDG.E R26, [R16.64] ; /* 0x00000004101a7981 */
/* 0x000322000c1e1900 */
/*09b0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x004fc600078e0210 */
/*09c0*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x0010a8000c1e1900 */
/*09d0*/ LDG.E R28, [R18.64] ; /* 0x00000004121c7981 */
/* 0x0000a2000c1e1900 */
/*09e0*/ IMAD.WIDE R10, R0, 0x4, R18 ; /* 0x00000004000a7825 */
/* 0x002fc600078e0212 */
/*09f0*/ LDG.E R17, [R8.64+0x18] ; /* 0x0000180408117981 */
/* 0x0002a8000c1e1900 */
/*0a00*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0000a2000c1e1900 */
/*0a10*/ IMAD.WIDE R14, R0, 0x4, R10 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020a */
/*0a20*/ LDG.E R11, [R8.64+0x1c] ; /* 0x00001c04080b7981 */
/* 0x0012a8000c1e1900 */
/*0a30*/ LDG.E R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x000ea2000c1e1900 */
/*0a40*/ FFMA R7, R7, R13, R12 ; /* 0x0000000d07077223 */
/* 0x008fcc000000000c */
/*0a50*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e30000020f100 */
/*0a60*/ I2F R12, R7 ; /* 0x00000007000c7306 */
/* 0x001f240000201400 */
/*0a70*/ FFMA R12, R23, R20, R12 ; /* 0x00000014170c7223 */
/* 0x010fcc000000000c */
/*0a80*/ F2I.TRUNC.NTZ R12, R12 ; /* 0x0000000c000c7305 */
/* 0x000e30000020f100 */
/*0a90*/ I2F R13, R12 ; /* 0x0000000c000d7306 */
/* 0x001f640000201400 */
/*0aa0*/ FFMA R13, R22, R21, R13 ; /* 0x00000015160d7223 */
/* 0x020fcc000000000d */
/*0ab0*/ F2I.TRUNC.NTZ R13, R13 ; /* 0x0000000d000d7305 */
/* 0x000e30000020f100 */
/*0ac0*/ I2F R18, R13 ; /* 0x0000000d00127306 */
/* 0x001e240000201400 */
/*0ad0*/ FFMA R18, R24, R25, R18 ; /* 0x0000001918127223 */
/* 0x001fcc0000000012 */
/*0ae0*/ F2I.TRUNC.NTZ R18, R18 ; /* 0x0000001200127305 */
/* 0x000e70000020f100 */
/*0af0*/ I2F R8, R18 ; /* 0x0000001200087306 */
/* 0x002e240000201400 */
/*0b00*/ FFMA R8, R26, R27, R8 ; /* 0x0000001b1a087223 */
/* 0x001fcc0000000008 */
/*0b10*/ F2I.TRUNC.NTZ R8, R8 ; /* 0x0000000800087305 */
/* 0x000e30000020f100 */
/*0b20*/ I2F R7, R8 ; /* 0x0000000800077306 */
/* 0x001ea40000201400 */
/*0b30*/ FFMA R7, R28, R29, R7 ; /* 0x0000001d1c077223 */
/* 0x004fcc0000000007 */
/*0b40*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e30000020f100 */
/*0b50*/ I2F R9, R7 ; /* 0x0000000700097306 */
/* 0x001e240000201400 */
/*0b60*/ FFMA R9, R16, R17, R9 ; /* 0x0000001110097223 */
/* 0x001fcc0000000009 */
/*0b70*/ F2I.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e30000020f100 */
/*0b80*/ I2F R12, R9 ; /* 0x00000009000c7306 */
/* 0x001e240000201400 */
/*0b90*/ FFMA R10, R10, R11, R12 ; /* 0x0000000b0a0a7223 */
/* 0x001fcc000000000c */
/*0ba0*/ F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a7305 */
/* 0x000e22000020f100 */
/*0bb0*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0bc0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0bd0*/ IMAD.WIDE R18, R0, 0x4, R14 ; /* 0x0000000400127825 */
/* 0x000fe200078e020e */
/*0be0*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fc80007ffe0ff */
/*0bf0*/ I2F R12, R10 ; /* 0x0000000a000c7306 */
/* 0x0010620000201400 */
/*0c00*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*0c10*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fcc00087fe43f */
/*0c20*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0c30*/ @!P0 BRA 0xe50 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*0c40*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0c50*/ LDG.E R7, [R18.64] ; /* 0x0000000412077981 */
/* 0x0004e2000c1e1900 */
/*0c60*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x001fca0008000f00 */
/*0c70*/ IMAD.WIDE R8, R4, 0x4, R8 ; /* 0x0000000404087825 */
/* 0x000fca00078e0208 */
/*0c80*/ LDG.E R13, [R8.64] ; /* 0x00000004080d7981 */
/* 0x000ee2000c1e1900 */
/*0c90*/ IMAD.WIDE R16, R0, 0x4, R18 ; /* 0x0000000400107825 */
/* 0x000fc600078e0212 */
/*0ca0*/ LDG.E R20, [R8.64+0x4] ; /* 0x0000040408147981 */
/* 0x000f28000c1e1900 */
/*0cb0*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x000f22000c1e1900 */
/*0cc0*/ IMAD.WIDE R14, R0, 0x4, R16 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0210 */
/*0cd0*/ LDG.E R22, [R8.64+0x8] ; /* 0x0000080408167981 */
/* 0x000f68000c1e1900 */
/*0ce0*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000f62000c1e1900 */
/*0cf0*/ IMAD.WIDE R10, R0, 0x4, R14 ; /* 0x00000004000a7825 */
/* 0x000fc600078e020e */
/*0d00*/ LDG.E R24, [R8.64+0xc] ; /* 0x00000c0408187981 */
/* 0x000f28000c1e1900 */
/*0d10*/ LDG.E R25, [R10.64] ; /* 0x000000040a197981 */
/* 0x000f22000c1e1900 */
/*0d20*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0d30*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0d40*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0d50*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc60007ffe0ff */
/*0d60*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0d70*/ IMAD.WIDE R18, R0, 0x4, R10 ; /* 0x0000000400127825 */
/* 0x004fc800078e020a */
/*0d80*/ FFMA R7, R7, R13, R12 ; /* 0x0000000d07077223 */
/* 0x00afcc000000000c */
/*0d90*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e30000020f100 */
/*0da0*/ I2F R12, R7 ; /* 0x00000007000c7306 */
/* 0x001f240000201400 */
/*0db0*/ FFMA R20, R21, R20, R12 ; /* 0x0000001415147223 */
/* 0x010fcc000000000c */
/*0dc0*/ F2I.TRUNC.NTZ R20, R20 ; /* 0x0000001400147305 */
/* 0x000e30000020f100 */
/*0dd0*/ I2F R12, R20 ; /* 0x00000014000c7306 */
/* 0x001f640000201400 */
/*0de0*/ FFMA R22, R23, R22, R12 ; /* 0x0000001617167223 */
/* 0x020fcc000000000c */
/*0df0*/ F2I.TRUNC.NTZ R22, R22 ; /* 0x0000001600167305 */
/* 0x000e30000020f100 */
/*0e00*/ I2F R12, R22 ; /* 0x00000016000c7306 */
/* 0x001e240000201400 */
/*0e10*/ FFMA R24, R25, R24, R12 ; /* 0x0000001819187223 */
/* 0x001fcc000000000c */
/*0e20*/ F2I.TRUNC.NTZ R24, R24 ; /* 0x0000001800187305 */
/* 0x000e30000020f100 */
/*0e30*/ I2F R12, R24 ; /* 0x00000018000c7306 */
/* 0x0010640000201400 */
/*0e40*/ @P0 BRA 0xc40 ; /* 0xfffffdf000000947 */
/* 0x003fea000383ffff */
/*0e50*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0e60*/ @!P0 BRA 0xf90 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0e70*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0e80*/ IADD3 R6, R4, R3, RZ ; /* 0x0000000304067210 */
/* 0x000fe20007ffe0ff */
/*0e90*/ IMAD R3, R3, c[0x0][0x160], R2 ; /* 0x0000580003037a24 */
/* 0x000fd000078e0202 */
/*0ea0*/ IMAD.WIDE R6, R6, R8, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0208 */
/*0eb0*/ IMAD.WIDE R8, R3, R8, c[0x0][0x170] ; /* 0x00005c0003087625 */
/* 0x001fe200078e0208 */
/*0ec0*/ MOV R10, R6 ; /* 0x00000006000a7202 */
/* 0x000fc80000000f00 */
/*0ed0*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fe20000000f00 */
/*0ee0*/ LDG.E R3, [R8.64] ; /* 0x0000000408037981 */
/* 0x0010aa000c1e1900 */
/*0ef0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x0006a2000c1e1900 */
/*0f00*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*0f10*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fc40007f3e0ff */
/*0f20*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0f30*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fe200078e0208 */
/*0f40*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x008fc60000ffe4ff */
/*0f50*/ FFMA R3, R3, R6, R12 ; /* 0x0000000603037223 */
/* 0x006fcc000000000c */
/*0f60*/ F2I.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e30000020f100 */
/*0f70*/ I2F R12, R3 ; /* 0x00000003000c7306 */
/* 0x0010620000201400 */
/*0f80*/ @P0 BRA 0xed0 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*0f90*/ IADD3 R2, R2, R4, RZ ; /* 0x0000000402027210 */
/* 0x000fe40007ffe0ff */
/*0fa0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x001fca0000000f00 */
/*0fb0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x178] ; /* 0x00005e0002027625 */
/* 0x000fca00078e0203 */
/*0fc0*/ STG.E [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x002fe2000c101904 */
/*0fd0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0fe0*/ BRA 0xfe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ff0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8mat_multiPfS_S_
.globl _Z8mat_multiPfS_S_
.p2align 8
.type _Z8mat_multiPfS_S_,@function
_Z8mat_multiPfS_S_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_mul_lo_u32 v2, v1, s2
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v0
s_mov_b32 s3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cvt_f32_i32_e32 v6, v6
s_add_i32 s3, s3, -1
s_cmp_eq_u32 s3, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s2, v4
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v6, v6
s_cbranch_scc0 .LBB0_2
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_i32_e32 v2, v6
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v1, s2, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8mat_multiPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8mat_multiPfS_S_, .Lfunc_end0-_Z8mat_multiPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8mat_multiPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8mat_multiPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004d034_00000000-6_mult_mat.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2274:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2274:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z8mat_multiPfS_S_iPfS_S_
.type _Z32__device_stub__Z8mat_multiPfS_S_iPfS_S_, @function
_Z32__device_stub__Z8mat_multiPfS_S_iPfS_S_:
.LFB2296:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8mat_multiPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2296:
.size _Z32__device_stub__Z8mat_multiPfS_S_iPfS_S_, .-_Z32__device_stub__Z8mat_multiPfS_S_iPfS_S_
.globl _Z8mat_multiPfS_S_
.type _Z8mat_multiPfS_S_, @function
_Z8mat_multiPfS_S_:
.LFB2297:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8mat_multiPfS_S_iPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2297:
.size _Z8mat_multiPfS_S_, .-_Z8mat_multiPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "There was a failure, big sad!\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Tests Pass!\n"
.text
.globl main
.type main, @function
main:
.LFB2271:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $262144, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $262144, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $262144, %esi
call cudaMallocManaged@PLT
movl $0, %r8d
movl $256, %edi
movl $0, %esi
jmp .L12
.L34:
movslq %eax, %rdx
pxor %xmm0, %xmm0
cvtsi2ssl %esi, %xmm0
movq 8(%rsp), %rcx
movss %xmm0, (%rcx,%rdx,4)
movq 16(%rsp), %rcx
movss %xmm0, (%rcx,%rdx,4)
.L14:
addl $1, %eax
cmpl %edi, %eax
je .L33
.L15:
leal (%rax,%r8), %edx
cmpl %edx, %esi
je .L34
movslq %eax, %rdx
movq 8(%rsp), %rcx
movl $0x00000000, (%rcx,%rdx,4)
movq 16(%rsp), %rcx
movl $0x00000000, (%rcx,%rdx,4)
jmp .L14
.L33:
addl $1, %esi
addl $256, %edi
subl $256, %r8d
cmpl $256, %esi
je .L16
.L12:
movl %esi, %eax
sall $8, %eax
jmp .L15
.L16:
movl $32, 32(%rsp)
movl $32, 36(%rsp)
movl $1, 40(%rsp)
movl $8, 44(%rsp)
movl $8, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L17:
call cudaDeviceSynchronize@PLT
movq 24(%rsp), %rcx
movl $0, %r8d
movl $256, %edi
movl $0, %esi
movl $0, %r9d
pxor %xmm1, %xmm1
movl $1, %r10d
jmp .L18
.L35:
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movl $256, %edi
call _Z32__device_stub__Z8mat_multiPfS_S_iPfS_S_
jmp .L17
.L37:
pxor %xmm0, %xmm0
cvtsi2ssl %esi, %xmm0
movslq %eax, %rdx
mulss %xmm0, %xmm0
ucomiss (%rcx,%rdx,4), %xmm0
jp .L29
je .L20
.L29:
movl %r10d, %r9d
jmp .L20
.L28:
movl %r10d, %r9d
.L20:
addl $1, %eax
cmpl %edi, %eax
je .L36
.L23:
leal (%rax,%r8), %edx
cmpl %edx, %esi
je .L37
movslq %eax, %rdx
ucomiss (%rcx,%rdx,4), %xmm1
jp .L28
je .L20
jmp .L28
.L36:
addl $1, %esi
addl $256, %edi
subl $256, %r8d
cmpl $256, %esi
je .L24
.L18:
movl %esi, %eax
sall $8, %eax
jmp .L23
.L24:
testl %r9d, %r9d
je .L25
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L26:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L38
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L26
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z8mat_multiPfS_S_"
.LC4:
.string "precalc_xorwow_matrix"
.LC5:
.string "precalc_xorwow_offset_matrix"
.LC6:
.string "mrg32k3aM1"
.LC7:
.string "mrg32k3aM2"
.LC8:
.string "mrg32k3aM1SubSeq"
.LC9:
.string "mrg32k3aM2SubSeq"
.LC10:
.string "mrg32k3aM1Seq"
.LC11:
.string "mrg32k3aM2Seq"
.LC12:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2299:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z8mat_multiPfS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2299:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mult_mat.hip"
.globl _Z23__device_stub__mat_multiPfS_S_ # -- Begin function _Z23__device_stub__mat_multiPfS_S_
.p2align 4, 0x90
.type _Z23__device_stub__mat_multiPfS_S_,@function
_Z23__device_stub__mat_multiPfS_S_: # @_Z23__device_stub__mat_multiPfS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8mat_multiPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__mat_multiPfS_S_, .Lfunc_end0-_Z23__device_stub__mat_multiPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $152, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 24(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
movl $1, %edx
callq hipMallocManaged
xorl %eax, %eax
xorl %ecx, %ecx
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_1 Depth=1
incq %rcx
addq $1024, %rax # imm = 0x400
cmpq $256, %rcx # imm = 0x100
je .LBB1_6
.LBB1_1: # %.preheader70
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movq 24(%rsp), %rdx
addq %rax, %rdx
movq 16(%rsp), %rsi
addq %rax, %rsi
xorl %edi, %edi
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_4: # in Loop: Header=BB1_2 Depth=2
movss %xmm1, (%rdx,%rdi,4)
movss %xmm1, (%rsi,%rdi,4)
incq %rdi
cmpq $256, %rdi # imm = 0x100
je .LBB1_5
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movaps %xmm0, %xmm1
cmpq %rdi, %rcx
je .LBB1_4
# %bb.3: # in Loop: Header=BB1_2 Depth=2
xorps %xmm1, %xmm1
jmp .LBB1_4
.LBB1_6:
xorl %ebx, %ebx
movabsq $34359738376, %rdi # imm = 0x800000008
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %ebp
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl $256, 36(%rsp) # imm = 0x100
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 104(%rsp), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z8mat_multiPfS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
callq hipDeviceSynchronize
movq 8(%rsp), %rax
xorps %xmm0, %xmm0
xorl %ecx, %ecx
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_12: # in Loop: Header=BB1_9 Depth=1
incq %rcx
addq $1024, %rax # imm = 0x400
cmpq $256, %rcx # imm = 0x100
je .LBB1_13
.LBB1_9: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_10 Depth 2
xorps %xmm1, %xmm1
cvtsi2ss %ecx, %xmm1
mulss %xmm1, %xmm1
xorl %edx, %edx
jmp .LBB1_10
.p2align 4, 0x90
.LBB1_11: # in Loop: Header=BB1_10 Depth=2
ucomiss (%rax,%rdx,4), %xmm1
cmovnel %ebp, %ebx
cmovpl %ebp, %ebx
.LBB1_16: # in Loop: Header=BB1_10 Depth=2
incq %rdx
cmpq $256, %rdx # imm = 0x100
je .LBB1_12
.LBB1_10: # Parent Loop BB1_9 Depth=1
# => This Inner Loop Header: Depth=2
cmpq %rdx, %rcx
je .LBB1_11
# %bb.14: # %.critedge
# in Loop: Header=BB1_10 Depth=2
movss (%rax,%rdx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm2
jne .LBB1_15
jnp .LBB1_16
.LBB1_15: # in Loop: Header=BB1_10 Depth=2
movl $1, %ebx
jmp .LBB1_16
.LBB1_13:
testl %ebx, %ebx
movl $.Lstr, %eax
movl $.Lstr.1, %edi
cmoveq %rax, %rdi
callq puts@PLT
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8mat_multiPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8mat_multiPfS_S_,@object # @_Z8mat_multiPfS_S_
.section .rodata,"a",@progbits
.globl _Z8mat_multiPfS_S_
.p2align 3, 0x0
_Z8mat_multiPfS_S_:
.quad _Z23__device_stub__mat_multiPfS_S_
.size _Z8mat_multiPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8mat_multiPfS_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Tests Pass!"
.size .Lstr, 12
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "There was a failure, big sad!"
.size .Lstr.1, 30
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__mat_multiPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8mat_multiPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#define BLOCK_SIZE 32
#define N 321
__global__ void sumValues(int *arr, int *sum) {
int index = BLOCK_SIZE * blockIdx.x + threadIdx.x;
__shared__ float temp[BLOCK_SIZE];
if (index < N) {
temp[threadIdx.x] = arr[index] * arr[index];
__syncthreads();
// The thread with index zero will sum up the values in temp
if (threadIdx.x == 0) {
int s = 0;
for (int i = 0; i < BLOCK_SIZE; i++) {
s += temp[i];
}
// Add the sum for this block to the
atomicAdd(sum, s);
}
}
}
int main() {
int *arr;
int *sum;
// Allocate Unified Memory -- accessible from CPU or GPU
cudaMallocManaged(&arr, N * sizeof(int));
cudaMallocManaged(&sum, sizeof(int));
for (int i = 0; i < N; i++) {
arr[i] = i;
}
int block_number =
N / BLOCK_SIZE * BLOCK_SIZE == N ? N / BLOCK_SIZE : N / BLOCK_SIZE + 1;
sumValues<<<block_number, BLOCK_SIZE>>>(arr, sum);
cudaDeviceSynchronize();
printf("sum = %d\n", *sum);
return 0;
} | code for sm_80
Function : _Z9sumValuesPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0030*/ LEA R2, R2, R5, 0x5 ; /* 0x0000000502027211 */
/* 0x001fc800078e28ff */
/*0040*/ ISETP.GT.AND P0, PT, R2, 0x140, PT ; /* 0x000001400200780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*00b0*/ IMAD R0, R2, R2, RZ ; /* 0x0000000202007224 */
/* 0x004fcc00078e02ff */
/*00c0*/ I2F R0, R0 ; /* 0x0000000000007306 */
/* 0x000e240000201400 */
/*00d0*/ STS [R5.X4], R0 ; /* 0x0000000005007388 */
/* 0x0011e80000004800 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ LDS.128 R4, [RZ] ; /* 0x00000000ff047984 */
/* 0x001e280000000c00 */
/*0110*/ LDS.128 R8, [0x10] ; /* 0x00001000ff087984 */
/* 0x000e620000000c00 */
/*0120*/ FADD R4, RZ, R4 ; /* 0x00000004ff047221 */
/* 0x001fcc0000000000 */
/*0130*/ F2I.TRUNC.NTZ R4, R4 ; /* 0x0000000400047305 */
/* 0x000e30000020f100 */
/*0140*/ I2F R0, R4 ; /* 0x0000000400007306 */
/* 0x001e240000201400 */
/*0150*/ FADD R0, R0, R5 ; /* 0x0000000500007221 */
/* 0x001fcc0000000000 */
/*0160*/ F2I.TRUNC.NTZ R0, R0 ; /* 0x0000000000007305 */
/* 0x000e30000020f100 */
/*0170*/ I2F R3, R0 ; /* 0x0000000000037306 */
/* 0x001e240000201400 */
/*0180*/ FADD R3, R3, R6 ; /* 0x0000000603037221 */
/* 0x001fcc0000000000 */
/*0190*/ F2I.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e30000020f100 */
/*01a0*/ I2F R2, R3 ; /* 0x0000000300027306 */
/* 0x001e240000201400 */
/*01b0*/ FADD R2, R2, R7 ; /* 0x0000000702027221 */
/* 0x001fcc0000000000 */
/*01c0*/ F2I.TRUNC.NTZ R2, R2 ; /* 0x0000000200027305 */
/* 0x000e30000020f100 */
/*01d0*/ I2F R5, R2 ; /* 0x0000000200057306 */
/* 0x001e640000201400 */
/*01e0*/ FADD R8, R5, R8 ; /* 0x0000000805087221 */
/* 0x002fcc0000000000 */
/*01f0*/ F2I.TRUNC.NTZ R8, R8 ; /* 0x0000000800087305 */
/* 0x000e30000020f100 */
/*0200*/ I2F R4, R8 ; /* 0x0000000800047306 */
/* 0x001e240000201400 */
/*0210*/ FADD R9, R4, R9 ; /* 0x0000000904097221 */
/* 0x001fcc0000000000 */
/*0220*/ F2I.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e30000020f100 */
/*0230*/ I2F R5, R9 ; /* 0x0000000900057306 */
/* 0x001e240000201400 */
/*0240*/ FADD R10, R5, R10 ; /* 0x0000000a050a7221 */
/* 0x001fc40000000000 */
/*0250*/ LDS.128 R4, [0x20] ; /* 0x00002000ff047984 */
/* 0x000e280000000c00 */
/*0260*/ F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a7305 */
/* 0x000e70000020f100 */
/*0270*/ I2F R0, R10 ; /* 0x0000000a00007306 */
/* 0x002e640000201400 */
/*0280*/ FADD R0, R0, R11 ; /* 0x0000000b00007221 */
/* 0x002fc40000000000 */
/*0290*/ LDS.128 R8, [0x30] ; /* 0x00003000ff087984 */
/* 0x000e680000000c00 */
/*02a0*/ F2I.TRUNC.NTZ R0, R0 ; /* 0x0000000000007305 */
/* 0x000eb0000020f100 */
/*02b0*/ I2F R3, R0 ; /* 0x0000000000037306 */
/* 0x004e240000201400 */
/*02c0*/ FADD R3, R3, R4 ; /* 0x0000000403037221 */
/* 0x001fcc0000000000 */
/*02d0*/ F2I.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e30000020f100 */
/*02e0*/ I2F R2, R3 ; /* 0x0000000300027306 */
/* 0x001e240000201400 */
/*02f0*/ FADD R2, R2, R5 ; /* 0x0000000502027221 */
/* 0x001fcc0000000000 */
/*0300*/ F2I.TRUNC.NTZ R2, R2 ; /* 0x0000000200027305 */
/* 0x000e30000020f100 */
/*0310*/ I2F R5, R2 ; /* 0x0000000200057306 */
/* 0x001e240000201400 */
/*0320*/ FADD R5, R5, R6 ; /* 0x0000000605057221 */
/* 0x001fcc0000000000 */
/*0330*/ F2I.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e30000020f100 */
/*0340*/ I2F R4, R5 ; /* 0x0000000500047306 */
/* 0x001e240000201400 */
/*0350*/ FADD R4, R4, R7 ; /* 0x0000000704047221 */
/* 0x001fcc0000000000 */
/*0360*/ F2I.TRUNC.NTZ R0, R4 ; /* 0x0000000400007305 */
/* 0x000e30000020f100 */
/*0370*/ I2F R7, R0 ; /* 0x0000000000077306 */
/* 0x001e640000201400 */
/*0380*/ FADD R8, R7, R8 ; /* 0x0000000807087221 */
/* 0x002fcc0000000000 */
/*0390*/ F2I.TRUNC.NTZ R8, R8 ; /* 0x0000000800087305 */
/* 0x000e30000020f100 */
/*03a0*/ I2F R6, R8 ; /* 0x0000000800067306 */
/* 0x001e240000201400 */
/*03b0*/ FADD R9, R6, R9 ; /* 0x0000000906097221 */
/* 0x001fc40000000000 */
/*03c0*/ LDS.128 R4, [0x40] ; /* 0x00004000ff047984 */
/* 0x000e280000000c00 */
/*03d0*/ F2I.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e70000020f100 */
/*03e0*/ I2F R3, R9 ; /* 0x0000000900037306 */
/* 0x002e640000201400 */
/*03f0*/ FADD R3, R3, R10 ; /* 0x0000000a03037221 */
/* 0x002fcc0000000000 */
/*0400*/ F2I.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e70000020f100 */
/*0410*/ I2F R2, R3 ; /* 0x0000000300027306 */
/* 0x002e640000201400 */
/*0420*/ FADD R2, R2, R11 ; /* 0x0000000b02027221 */
/* 0x002fcc0000000000 */
/*0430*/ F2I.TRUNC.NTZ R2, R2 ; /* 0x0000000200027305 */
/* 0x000e70000020f100 */
/*0440*/ I2F R11, R2 ; /* 0x00000002000b7306 */
/* 0x002e240000201400 */
/*0450*/ FADD R4, R11, R4 ; /* 0x000000040b047221 */
/* 0x001fc40000000000 */
/*0460*/ LDS.128 R8, [0x50] ; /* 0x00005000ff087984 */
/* 0x000e280000000c00 */
/*0470*/ F2I.TRUNC.NTZ R4, R4 ; /* 0x0000000400047305 */
/* 0x000e70000020f100 */
/*0480*/ I2F R0, R4 ; /* 0x0000000400007306 */
/* 0x002e640000201400 */
/*0490*/ FADD R0, R0, R5 ; /* 0x0000000500007221 */
/* 0x002fcc0000000000 */
/*04a0*/ F2I.TRUNC.NTZ R0, R0 ; /* 0x0000000000007305 */
/* 0x000e70000020f100 */
/*04b0*/ I2F R5, R0 ; /* 0x0000000000057306 */
/* 0x002e640000201400 */
/*04c0*/ FADD R5, R5, R6 ; /* 0x0000000605057221 */
/* 0x002fcc0000000000 */
/*04d0*/ F2I.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e70000020f100 */
/*04e0*/ I2F R6, R5 ; /* 0x0000000500067306 */
/* 0x002e640000201400 */
/*04f0*/ FADD R6, R6, R7 ; /* 0x0000000706067221 */
/* 0x002fcc0000000000 */
/*0500*/ F2I.TRUNC.NTZ R2, R6 ; /* 0x0000000600027305 */
/* 0x000e70000020f100 */
/*0510*/ I2F R3, R2 ; /* 0x0000000200037306 */
/* 0x002e240000201400 */
/*0520*/ FADD R3, R3, R8 ; /* 0x0000000803037221 */
/* 0x001fcc0000000000 */
/*0530*/ F2I.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e30000020f100 */
/*0540*/ I2F R4, R3 ; /* 0x0000000300047306 */
/* 0x001e240000201400 */
/*0550*/ FADD R9, R4, R9 ; /* 0x0000000904097221 */
/* 0x001fcc0000000000 */
/*0560*/ F2I.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e30000020f100 */
/*0570*/ I2F R7, R9 ; /* 0x0000000900077306 */
/* 0x001e240000201400 */
/*0580*/ FADD R10, R7, R10 ; /* 0x0000000a070a7221 */
/* 0x001fc40000000000 */
/*0590*/ LDS.128 R4, [0x60] ; /* 0x00006000ff047984 */
/* 0x000e280000000c00 */
/*05a0*/ F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a7305 */
/* 0x000e70000020f100 */
/*05b0*/ I2F R0, R10 ; /* 0x0000000a00007306 */
/* 0x002e640000201400 */
/*05c0*/ FADD R0, R0, R11 ; /* 0x0000000b00007221 */
/* 0x002fcc0000000000 */
/*05d0*/ F2I.TRUNC.NTZ R0, R0 ; /* 0x0000000000007305 */
/* 0x000e70000020f100 */
/*05e0*/ I2F R11, R0 ; /* 0x00000000000b7306 */
/* 0x002e240000201400 */
/*05f0*/ FADD R4, R11, R4 ; /* 0x000000040b047221 */
/* 0x001fc40000000000 */
/*0600*/ LDS.128 R8, [0x70] ; /* 0x00007000ff087984 */
/* 0x000e280000000c00 */
/*0610*/ F2I.TRUNC.NTZ R4, R4 ; /* 0x0000000400047305 */
/* 0x000e70000020f100 */
/*0620*/ I2F R2, R4 ; /* 0x0000000400027306 */
/* 0x002e640000201400 */
/*0630*/ FADD R2, R2, R5 ; /* 0x0000000502027221 */
/* 0x002fcc0000000000 */
/*0640*/ F2I.TRUNC.NTZ R2, R2 ; /* 0x0000000200027305 */
/* 0x000e70000020f100 */
/*0650*/ I2F R3, R2 ; /* 0x0000000200037306 */
/* 0x002e640000201400 */
/*0660*/ FADD R3, R3, R6 ; /* 0x0000000603037221 */
/* 0x002fcc0000000000 */
/*0670*/ F2I.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e70000020f100 */
/*0680*/ I2F R6, R3 ; /* 0x0000000300067306 */
/* 0x0022a40000201400 */
/*0690*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x002fe20000000f00 */
/*06a0*/ FADD R6, R6, R7 ; /* 0x0000000706067221 */
/* 0x004fcc0000000000 */
/*06b0*/ F2I.TRUNC.NTZ R6, R6 ; /* 0x0000000600067305 */
/* 0x000e70000020f100 */
/*06c0*/ I2F R5, R6 ; /* 0x0000000600057306 */
/* 0x002e240000201400 */
/*06d0*/ FADD R5, R5, R8 ; /* 0x0000000805057221 */
/* 0x001fcc0000000000 */
/*06e0*/ F2I.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e30000020f100 */
/*06f0*/ I2F R0, R5 ; /* 0x0000000500007306 */
/* 0x001e240000201400 */
/*0700*/ FADD R0, R0, R9 ; /* 0x0000000900007221 */
/* 0x001fcc0000000000 */
/*0710*/ F2I.TRUNC.NTZ R0, R0 ; /* 0x0000000000007305 */
/* 0x000e30000020f100 */
/*0720*/ I2F R7, R0 ; /* 0x0000000000077306 */
/* 0x001e240000201400 */
/*0730*/ FADD R7, R7, R10 ; /* 0x0000000a07077221 */
/* 0x001fcc0000000000 */
/*0740*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e30000020f100 */
/*0750*/ I2F R2, R7 ; /* 0x0000000700027306 */
/* 0x001e240000201400 */
/*0760*/ FADD R11, R2, R11 ; /* 0x0000000b020b7221 */
/* 0x001fe20000000000 */
/*0770*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fca0000000f00 */
/*0780*/ F2I.TRUNC.NTZ R11, R11 ; /* 0x0000000b000b7305 */
/* 0x000e24000020f100 */
/*0790*/ RED.E.ADD.STRONG.GPU [R2.64], R11 ; /* 0x0000000b0200798e */
/* 0x001fe2000c10e184 */
/*07a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07b0*/ BRA 0x7b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#define BLOCK_SIZE 32
#define N 321
__global__ void sumValues(int *arr, int *sum) {
int index = BLOCK_SIZE * blockIdx.x + threadIdx.x;
__shared__ float temp[BLOCK_SIZE];
if (index < N) {
temp[threadIdx.x] = arr[index] * arr[index];
__syncthreads();
// The thread with index zero will sum up the values in temp
if (threadIdx.x == 0) {
int s = 0;
for (int i = 0; i < BLOCK_SIZE; i++) {
s += temp[i];
}
// Add the sum for this block to the
atomicAdd(sum, s);
}
}
}
int main() {
int *arr;
int *sum;
// Allocate Unified Memory -- accessible from CPU or GPU
cudaMallocManaged(&arr, N * sizeof(int));
cudaMallocManaged(&sum, sizeof(int));
for (int i = 0; i < N; i++) {
arr[i] = i;
}
int block_number =
N / BLOCK_SIZE * BLOCK_SIZE == N ? N / BLOCK_SIZE : N / BLOCK_SIZE + 1;
sumValues<<<block_number, BLOCK_SIZE>>>(arr, sum);
cudaDeviceSynchronize();
printf("sum = %d\n", *sum);
return 0;
} | .file "tmpxft_000947b6_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9sumValuesPiS_PiS_
.type _Z30__device_stub__Z9sumValuesPiS_PiS_, @function
_Z30__device_stub__Z9sumValuesPiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9sumValuesPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z9sumValuesPiS_PiS_, .-_Z30__device_stub__Z9sumValuesPiS_PiS_
.globl _Z9sumValuesPiS_
.type _Z9sumValuesPiS_, @function
_Z9sumValuesPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9sumValuesPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9sumValuesPiS_, .-_Z9sumValuesPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "sum = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1, %edx
movl $1284, %esi
call cudaMallocManaged@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
movl $0, %eax
.L12:
movq (%rsp), %rdx
movl %eax, (%rdx,%rax,4)
addq $1, %rax
cmpq $321, %rax
jne .L12
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $11, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
call cudaDeviceSynchronize@PLT
movq 8(%rsp), %rax
movl (%rax), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z30__device_stub__Z9sumValuesPiS_PiS_
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z9sumValuesPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9sumValuesPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#define BLOCK_SIZE 32
#define N 321
__global__ void sumValues(int *arr, int *sum) {
int index = BLOCK_SIZE * blockIdx.x + threadIdx.x;
__shared__ float temp[BLOCK_SIZE];
if (index < N) {
temp[threadIdx.x] = arr[index] * arr[index];
__syncthreads();
// The thread with index zero will sum up the values in temp
if (threadIdx.x == 0) {
int s = 0;
for (int i = 0; i < BLOCK_SIZE; i++) {
s += temp[i];
}
// Add the sum for this block to the
atomicAdd(sum, s);
}
}
}
int main() {
int *arr;
int *sum;
// Allocate Unified Memory -- accessible from CPU or GPU
cudaMallocManaged(&arr, N * sizeof(int));
cudaMallocManaged(&sum, sizeof(int));
for (int i = 0; i < N; i++) {
arr[i] = i;
}
int block_number =
N / BLOCK_SIZE * BLOCK_SIZE == N ? N / BLOCK_SIZE : N / BLOCK_SIZE + 1;
sumValues<<<block_number, BLOCK_SIZE>>>(arr, sum);
cudaDeviceSynchronize();
printf("sum = %d\n", *sum);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define BLOCK_SIZE 32
#define N 321
__global__ void sumValues(int *arr, int *sum) {
int index = BLOCK_SIZE * blockIdx.x + threadIdx.x;
__shared__ float temp[BLOCK_SIZE];
if (index < N) {
temp[threadIdx.x] = arr[index] * arr[index];
__syncthreads();
// The thread with index zero will sum up the values in temp
if (threadIdx.x == 0) {
int s = 0;
for (int i = 0; i < BLOCK_SIZE; i++) {
s += temp[i];
}
// Add the sum for this block to the
atomicAdd(sum, s);
}
}
}
int main() {
int *arr;
int *sum;
// Allocate Unified Memory -- accessible from CPU or GPU
hipMallocManaged(&arr, N * sizeof(int));
hipMallocManaged(&sum, sizeof(int));
for (int i = 0; i < N; i++) {
arr[i] = i;
}
int block_number =
N / BLOCK_SIZE * BLOCK_SIZE == N ? N / BLOCK_SIZE : N / BLOCK_SIZE + 1;
sumValues<<<block_number, BLOCK_SIZE>>>(arr, sum);
hipDeviceSynchronize();
printf("sum = %d\n", *sum);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define BLOCK_SIZE 32
#define N 321
__global__ void sumValues(int *arr, int *sum) {
int index = BLOCK_SIZE * blockIdx.x + threadIdx.x;
__shared__ float temp[BLOCK_SIZE];
if (index < N) {
temp[threadIdx.x] = arr[index] * arr[index];
__syncthreads();
// The thread with index zero will sum up the values in temp
if (threadIdx.x == 0) {
int s = 0;
for (int i = 0; i < BLOCK_SIZE; i++) {
s += temp[i];
}
// Add the sum for this block to the
atomicAdd(sum, s);
}
}
}
int main() {
int *arr;
int *sum;
// Allocate Unified Memory -- accessible from CPU or GPU
hipMallocManaged(&arr, N * sizeof(int));
hipMallocManaged(&sum, sizeof(int));
for (int i = 0; i < N; i++) {
arr[i] = i;
}
int block_number =
N / BLOCK_SIZE * BLOCK_SIZE == N ? N / BLOCK_SIZE : N / BLOCK_SIZE + 1;
sumValues<<<block_number, BLOCK_SIZE>>>(arr, sum);
hipDeviceSynchronize();
printf("sum = %d\n", *sum);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9sumValuesPiS_
.globl _Z9sumValuesPiS_
.p2align 8
.type _Z9sumValuesPiS_,@function
_Z9sumValuesPiS_:
v_lshl_add_u32 v1, s15, 5, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x141, v1
s_cbranch_execz .LBB0_6
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_mov_b32 s2, 0
global_load_b32 v1, v[1:2], off
v_lshlrev_b32_e32 v2, 2, v0
s_waitcnt vmcnt(0)
v_mul_lo_u32 v1, v1, v1
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_i32_e32 v1, v1
ds_store_b32 v2, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
.LBB0_3:
v_mov_b32_e32 v1, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cvt_f32_i32_e32 v0, v0
s_add_i32 s2, s2, 4
s_cmpk_eq_i32 s2, 0x80
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v0, v0
s_cbranch_scc0 .LBB0_3
s_mov_b32 s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v1, s2, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v1
s_and_b32 s3, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s3
s_cbranch_execz .LBB0_6
s_load_b64 s[0:1], s[0:1], 0x8
s_bcnt1_i32_b32 s2, s2
v_mov_b32_e32 v1, 0
v_mul_lo_u32 v0, v0, s2
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v1, v0, s[0:1]
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9sumValuesPiS_
.amdhsa_group_segment_fixed_size 128
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9sumValuesPiS_, .Lfunc_end0-_Z9sumValuesPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 128
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9sumValuesPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9sumValuesPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define BLOCK_SIZE 32
#define N 321
__global__ void sumValues(int *arr, int *sum) {
int index = BLOCK_SIZE * blockIdx.x + threadIdx.x;
__shared__ float temp[BLOCK_SIZE];
if (index < N) {
temp[threadIdx.x] = arr[index] * arr[index];
__syncthreads();
// The thread with index zero will sum up the values in temp
if (threadIdx.x == 0) {
int s = 0;
for (int i = 0; i < BLOCK_SIZE; i++) {
s += temp[i];
}
// Add the sum for this block to the
atomicAdd(sum, s);
}
}
}
int main() {
int *arr;
int *sum;
// Allocate Unified Memory -- accessible from CPU or GPU
hipMallocManaged(&arr, N * sizeof(int));
hipMallocManaged(&sum, sizeof(int));
for (int i = 0; i < N; i++) {
arr[i] = i;
}
int block_number =
N / BLOCK_SIZE * BLOCK_SIZE == N ? N / BLOCK_SIZE : N / BLOCK_SIZE + 1;
sumValues<<<block_number, BLOCK_SIZE>>>(arr, sum);
hipDeviceSynchronize();
printf("sum = %d\n", *sum);
return 0;
} | .text
.file "add.hip"
.globl _Z24__device_stub__sumValuesPiS_ # -- Begin function _Z24__device_stub__sumValuesPiS_
.p2align 4, 0x90
.type _Z24__device_stub__sumValuesPiS_,@function
_Z24__device_stub__sumValuesPiS_: # @_Z24__device_stub__sumValuesPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9sumValuesPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__sumValuesPiS_, .Lfunc_end0-_Z24__device_stub__sumValuesPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
leaq 8(%rsp), %rdi
movl $1284, %esi # imm = 0x504
movl $1, %edx
callq hipMallocManaged
movq %rsp, %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
xorl %eax, %eax
movq 8(%rsp), %rcx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rcx,%rax,4)
incq %rax
cmpq $321, %rax # imm = 0x141
jne .LBB1_1
# %bb.2:
movabsq $4294967307, %rdi # imm = 0x10000000B
leaq 21(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9sumValuesPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
movq (%rsp), %rax
movl (%rax), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9sumValuesPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9sumValuesPiS_,@object # @_Z9sumValuesPiS_
.section .rodata,"a",@progbits
.globl _Z9sumValuesPiS_
.p2align 3, 0x0
_Z9sumValuesPiS_:
.quad _Z24__device_stub__sumValuesPiS_
.size _Z9sumValuesPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "sum = %d\n"
.size .L.str, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9sumValuesPiS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__sumValuesPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9sumValuesPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9sumValuesPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0030*/ LEA R2, R2, R5, 0x5 ; /* 0x0000000502027211 */
/* 0x001fc800078e28ff */
/*0040*/ ISETP.GT.AND P0, PT, R2, 0x140, PT ; /* 0x000001400200780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*00b0*/ IMAD R0, R2, R2, RZ ; /* 0x0000000202007224 */
/* 0x004fcc00078e02ff */
/*00c0*/ I2F R0, R0 ; /* 0x0000000000007306 */
/* 0x000e240000201400 */
/*00d0*/ STS [R5.X4], R0 ; /* 0x0000000005007388 */
/* 0x0011e80000004800 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ LDS.128 R4, [RZ] ; /* 0x00000000ff047984 */
/* 0x001e280000000c00 */
/*0110*/ LDS.128 R8, [0x10] ; /* 0x00001000ff087984 */
/* 0x000e620000000c00 */
/*0120*/ FADD R4, RZ, R4 ; /* 0x00000004ff047221 */
/* 0x001fcc0000000000 */
/*0130*/ F2I.TRUNC.NTZ R4, R4 ; /* 0x0000000400047305 */
/* 0x000e30000020f100 */
/*0140*/ I2F R0, R4 ; /* 0x0000000400007306 */
/* 0x001e240000201400 */
/*0150*/ FADD R0, R0, R5 ; /* 0x0000000500007221 */
/* 0x001fcc0000000000 */
/*0160*/ F2I.TRUNC.NTZ R0, R0 ; /* 0x0000000000007305 */
/* 0x000e30000020f100 */
/*0170*/ I2F R3, R0 ; /* 0x0000000000037306 */
/* 0x001e240000201400 */
/*0180*/ FADD R3, R3, R6 ; /* 0x0000000603037221 */
/* 0x001fcc0000000000 */
/*0190*/ F2I.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e30000020f100 */
/*01a0*/ I2F R2, R3 ; /* 0x0000000300027306 */
/* 0x001e240000201400 */
/*01b0*/ FADD R2, R2, R7 ; /* 0x0000000702027221 */
/* 0x001fcc0000000000 */
/*01c0*/ F2I.TRUNC.NTZ R2, R2 ; /* 0x0000000200027305 */
/* 0x000e30000020f100 */
/*01d0*/ I2F R5, R2 ; /* 0x0000000200057306 */
/* 0x001e640000201400 */
/*01e0*/ FADD R8, R5, R8 ; /* 0x0000000805087221 */
/* 0x002fcc0000000000 */
/*01f0*/ F2I.TRUNC.NTZ R8, R8 ; /* 0x0000000800087305 */
/* 0x000e30000020f100 */
/*0200*/ I2F R4, R8 ; /* 0x0000000800047306 */
/* 0x001e240000201400 */
/*0210*/ FADD R9, R4, R9 ; /* 0x0000000904097221 */
/* 0x001fcc0000000000 */
/*0220*/ F2I.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e30000020f100 */
/*0230*/ I2F R5, R9 ; /* 0x0000000900057306 */
/* 0x001e240000201400 */
/*0240*/ FADD R10, R5, R10 ; /* 0x0000000a050a7221 */
/* 0x001fc40000000000 */
/*0250*/ LDS.128 R4, [0x20] ; /* 0x00002000ff047984 */
/* 0x000e280000000c00 */
/*0260*/ F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a7305 */
/* 0x000e70000020f100 */
/*0270*/ I2F R0, R10 ; /* 0x0000000a00007306 */
/* 0x002e640000201400 */
/*0280*/ FADD R0, R0, R11 ; /* 0x0000000b00007221 */
/* 0x002fc40000000000 */
/*0290*/ LDS.128 R8, [0x30] ; /* 0x00003000ff087984 */
/* 0x000e680000000c00 */
/*02a0*/ F2I.TRUNC.NTZ R0, R0 ; /* 0x0000000000007305 */
/* 0x000eb0000020f100 */
/*02b0*/ I2F R3, R0 ; /* 0x0000000000037306 */
/* 0x004e240000201400 */
/*02c0*/ FADD R3, R3, R4 ; /* 0x0000000403037221 */
/* 0x001fcc0000000000 */
/*02d0*/ F2I.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e30000020f100 */
/*02e0*/ I2F R2, R3 ; /* 0x0000000300027306 */
/* 0x001e240000201400 */
/*02f0*/ FADD R2, R2, R5 ; /* 0x0000000502027221 */
/* 0x001fcc0000000000 */
/*0300*/ F2I.TRUNC.NTZ R2, R2 ; /* 0x0000000200027305 */
/* 0x000e30000020f100 */
/*0310*/ I2F R5, R2 ; /* 0x0000000200057306 */
/* 0x001e240000201400 */
/*0320*/ FADD R5, R5, R6 ; /* 0x0000000605057221 */
/* 0x001fcc0000000000 */
/*0330*/ F2I.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e30000020f100 */
/*0340*/ I2F R4, R5 ; /* 0x0000000500047306 */
/* 0x001e240000201400 */
/*0350*/ FADD R4, R4, R7 ; /* 0x0000000704047221 */
/* 0x001fcc0000000000 */
/*0360*/ F2I.TRUNC.NTZ R0, R4 ; /* 0x0000000400007305 */
/* 0x000e30000020f100 */
/*0370*/ I2F R7, R0 ; /* 0x0000000000077306 */
/* 0x001e640000201400 */
/*0380*/ FADD R8, R7, R8 ; /* 0x0000000807087221 */
/* 0x002fcc0000000000 */
/*0390*/ F2I.TRUNC.NTZ R8, R8 ; /* 0x0000000800087305 */
/* 0x000e30000020f100 */
/*03a0*/ I2F R6, R8 ; /* 0x0000000800067306 */
/* 0x001e240000201400 */
/*03b0*/ FADD R9, R6, R9 ; /* 0x0000000906097221 */
/* 0x001fc40000000000 */
/*03c0*/ LDS.128 R4, [0x40] ; /* 0x00004000ff047984 */
/* 0x000e280000000c00 */
/*03d0*/ F2I.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e70000020f100 */
/*03e0*/ I2F R3, R9 ; /* 0x0000000900037306 */
/* 0x002e640000201400 */
/*03f0*/ FADD R3, R3, R10 ; /* 0x0000000a03037221 */
/* 0x002fcc0000000000 */
/*0400*/ F2I.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e70000020f100 */
/*0410*/ I2F R2, R3 ; /* 0x0000000300027306 */
/* 0x002e640000201400 */
/*0420*/ FADD R2, R2, R11 ; /* 0x0000000b02027221 */
/* 0x002fcc0000000000 */
/*0430*/ F2I.TRUNC.NTZ R2, R2 ; /* 0x0000000200027305 */
/* 0x000e70000020f100 */
/*0440*/ I2F R11, R2 ; /* 0x00000002000b7306 */
/* 0x002e240000201400 */
/*0450*/ FADD R4, R11, R4 ; /* 0x000000040b047221 */
/* 0x001fc40000000000 */
/*0460*/ LDS.128 R8, [0x50] ; /* 0x00005000ff087984 */
/* 0x000e280000000c00 */
/*0470*/ F2I.TRUNC.NTZ R4, R4 ; /* 0x0000000400047305 */
/* 0x000e70000020f100 */
/*0480*/ I2F R0, R4 ; /* 0x0000000400007306 */
/* 0x002e640000201400 */
/*0490*/ FADD R0, R0, R5 ; /* 0x0000000500007221 */
/* 0x002fcc0000000000 */
/*04a0*/ F2I.TRUNC.NTZ R0, R0 ; /* 0x0000000000007305 */
/* 0x000e70000020f100 */
/*04b0*/ I2F R5, R0 ; /* 0x0000000000057306 */
/* 0x002e640000201400 */
/*04c0*/ FADD R5, R5, R6 ; /* 0x0000000605057221 */
/* 0x002fcc0000000000 */
/*04d0*/ F2I.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e70000020f100 */
/*04e0*/ I2F R6, R5 ; /* 0x0000000500067306 */
/* 0x002e640000201400 */
/*04f0*/ FADD R6, R6, R7 ; /* 0x0000000706067221 */
/* 0x002fcc0000000000 */
/*0500*/ F2I.TRUNC.NTZ R2, R6 ; /* 0x0000000600027305 */
/* 0x000e70000020f100 */
/*0510*/ I2F R3, R2 ; /* 0x0000000200037306 */
/* 0x002e240000201400 */
/*0520*/ FADD R3, R3, R8 ; /* 0x0000000803037221 */
/* 0x001fcc0000000000 */
/*0530*/ F2I.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e30000020f100 */
/*0540*/ I2F R4, R3 ; /* 0x0000000300047306 */
/* 0x001e240000201400 */
/*0550*/ FADD R9, R4, R9 ; /* 0x0000000904097221 */
/* 0x001fcc0000000000 */
/*0560*/ F2I.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e30000020f100 */
/*0570*/ I2F R7, R9 ; /* 0x0000000900077306 */
/* 0x001e240000201400 */
/*0580*/ FADD R10, R7, R10 ; /* 0x0000000a070a7221 */
/* 0x001fc40000000000 */
/*0590*/ LDS.128 R4, [0x60] ; /* 0x00006000ff047984 */
/* 0x000e280000000c00 */
/*05a0*/ F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a7305 */
/* 0x000e70000020f100 */
/*05b0*/ I2F R0, R10 ; /* 0x0000000a00007306 */
/* 0x002e640000201400 */
/*05c0*/ FADD R0, R0, R11 ; /* 0x0000000b00007221 */
/* 0x002fcc0000000000 */
/*05d0*/ F2I.TRUNC.NTZ R0, R0 ; /* 0x0000000000007305 */
/* 0x000e70000020f100 */
/*05e0*/ I2F R11, R0 ; /* 0x00000000000b7306 */
/* 0x002e240000201400 */
/*05f0*/ FADD R4, R11, R4 ; /* 0x000000040b047221 */
/* 0x001fc40000000000 */
/*0600*/ LDS.128 R8, [0x70] ; /* 0x00007000ff087984 */
/* 0x000e280000000c00 */
/*0610*/ F2I.TRUNC.NTZ R4, R4 ; /* 0x0000000400047305 */
/* 0x000e70000020f100 */
/*0620*/ I2F R2, R4 ; /* 0x0000000400027306 */
/* 0x002e640000201400 */
/*0630*/ FADD R2, R2, R5 ; /* 0x0000000502027221 */
/* 0x002fcc0000000000 */
/*0640*/ F2I.TRUNC.NTZ R2, R2 ; /* 0x0000000200027305 */
/* 0x000e70000020f100 */
/*0650*/ I2F R3, R2 ; /* 0x0000000200037306 */
/* 0x002e640000201400 */
/*0660*/ FADD R3, R3, R6 ; /* 0x0000000603037221 */
/* 0x002fcc0000000000 */
/*0670*/ F2I.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e70000020f100 */
/*0680*/ I2F R6, R3 ; /* 0x0000000300067306 */
/* 0x0022a40000201400 */
/*0690*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x002fe20000000f00 */
/*06a0*/ FADD R6, R6, R7 ; /* 0x0000000706067221 */
/* 0x004fcc0000000000 */
/*06b0*/ F2I.TRUNC.NTZ R6, R6 ; /* 0x0000000600067305 */
/* 0x000e70000020f100 */
/*06c0*/ I2F R5, R6 ; /* 0x0000000600057306 */
/* 0x002e240000201400 */
/*06d0*/ FADD R5, R5, R8 ; /* 0x0000000805057221 */
/* 0x001fcc0000000000 */
/*06e0*/ F2I.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e30000020f100 */
/*06f0*/ I2F R0, R5 ; /* 0x0000000500007306 */
/* 0x001e240000201400 */
/*0700*/ FADD R0, R0, R9 ; /* 0x0000000900007221 */
/* 0x001fcc0000000000 */
/*0710*/ F2I.TRUNC.NTZ R0, R0 ; /* 0x0000000000007305 */
/* 0x000e30000020f100 */
/*0720*/ I2F R7, R0 ; /* 0x0000000000077306 */
/* 0x001e240000201400 */
/*0730*/ FADD R7, R7, R10 ; /* 0x0000000a07077221 */
/* 0x001fcc0000000000 */
/*0740*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000e30000020f100 */
/*0750*/ I2F R2, R7 ; /* 0x0000000700027306 */
/* 0x001e240000201400 */
/*0760*/ FADD R11, R2, R11 ; /* 0x0000000b020b7221 */
/* 0x001fe20000000000 */
/*0770*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fca0000000f00 */
/*0780*/ F2I.TRUNC.NTZ R11, R11 ; /* 0x0000000b000b7305 */
/* 0x000e24000020f100 */
/*0790*/ RED.E.ADD.STRONG.GPU [R2.64], R11 ; /* 0x0000000b0200798e */
/* 0x001fe2000c10e184 */
/*07a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07b0*/ BRA 0x7b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9sumValuesPiS_
.globl _Z9sumValuesPiS_
.p2align 8
.type _Z9sumValuesPiS_,@function
_Z9sumValuesPiS_:
v_lshl_add_u32 v1, s15, 5, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x141, v1
s_cbranch_execz .LBB0_6
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_mov_b32 s2, 0
global_load_b32 v1, v[1:2], off
v_lshlrev_b32_e32 v2, 2, v0
s_waitcnt vmcnt(0)
v_mul_lo_u32 v1, v1, v1
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_i32_e32 v1, v1
ds_store_b32 v2, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
.LBB0_3:
v_mov_b32_e32 v1, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cvt_f32_i32_e32 v0, v0
s_add_i32 s2, s2, 4
s_cmpk_eq_i32 s2, 0x80
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v0, v0
s_cbranch_scc0 .LBB0_3
s_mov_b32 s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mbcnt_lo_u32_b32 v1, s2, 0
v_cmp_eq_u32_e32 vcc_lo, 0, v1
s_and_b32 s3, exec_lo, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 exec_lo, s3
s_cbranch_execz .LBB0_6
s_load_b64 s[0:1], s[0:1], 0x8
s_bcnt1_i32_b32 s2, s2
v_mov_b32_e32 v1, 0
v_mul_lo_u32 v0, v0, s2
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v1, v0, s[0:1]
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9sumValuesPiS_
.amdhsa_group_segment_fixed_size 128
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9sumValuesPiS_, .Lfunc_end0-_Z9sumValuesPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 128
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9sumValuesPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9sumValuesPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000947b6_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9sumValuesPiS_PiS_
.type _Z30__device_stub__Z9sumValuesPiS_PiS_, @function
_Z30__device_stub__Z9sumValuesPiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9sumValuesPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z9sumValuesPiS_PiS_, .-_Z30__device_stub__Z9sumValuesPiS_PiS_
.globl _Z9sumValuesPiS_
.type _Z9sumValuesPiS_, @function
_Z9sumValuesPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9sumValuesPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9sumValuesPiS_, .-_Z9sumValuesPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "sum = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1, %edx
movl $1284, %esi
call cudaMallocManaged@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movl $4, %esi
call cudaMallocManaged@PLT
movl $0, %eax
.L12:
movq (%rsp), %rdx
movl %eax, (%rdx,%rax,4)
addq $1, %rax
cmpq $321, %rax
jne .L12
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $11, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
call cudaDeviceSynchronize@PLT
movq 8(%rsp), %rax
movl (%rax), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z30__device_stub__Z9sumValuesPiS_PiS_
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z9sumValuesPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9sumValuesPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add.hip"
.globl _Z24__device_stub__sumValuesPiS_ # -- Begin function _Z24__device_stub__sumValuesPiS_
.p2align 4, 0x90
.type _Z24__device_stub__sumValuesPiS_,@function
_Z24__device_stub__sumValuesPiS_: # @_Z24__device_stub__sumValuesPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9sumValuesPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__sumValuesPiS_, .Lfunc_end0-_Z24__device_stub__sumValuesPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
leaq 8(%rsp), %rdi
movl $1284, %esi # imm = 0x504
movl $1, %edx
callq hipMallocManaged
movq %rsp, %rdi
movl $4, %esi
movl $1, %edx
callq hipMallocManaged
xorl %eax, %eax
movq 8(%rsp), %rcx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rcx,%rax,4)
incq %rax
cmpq $321, %rax # imm = 0x141
jne .LBB1_1
# %bb.2:
movabsq $4294967307, %rdi # imm = 0x10000000B
leaq 21(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9sumValuesPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
movq (%rsp), %rax
movl (%rax), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9sumValuesPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9sumValuesPiS_,@object # @_Z9sumValuesPiS_
.section .rodata,"a",@progbits
.globl _Z9sumValuesPiS_
.p2align 3, 0x0
_Z9sumValuesPiS_:
.quad _Z24__device_stub__sumValuesPiS_
.size _Z9sumValuesPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "sum = %d\n"
.size .L.str, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9sumValuesPiS_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__sumValuesPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9sumValuesPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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